mirror of
https://github.com/holub/mame
synced 2025-06-03 03:16:30 +03:00
1432 lines
49 KiB
C
1432 lines
49 KiB
C
/***************************************************************************
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r3000->c
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Core implementation for the portable MIPS R3000 emulator.
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Written by Aaron Giles
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***************************************************************************/
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#include "debugger.h"
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#include "deprecat.h"
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#include "r3000.h"
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#define ENABLE_OVERFLOWS 0
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/***************************************************************************
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CONSTANTS
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***************************************************************************/
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#define COP0_Index 0
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#define COP0_Random 1
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#define COP0_EntryLo 2
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#define COP0_Context 4
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#define COP0_BadVAddr 8
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#define COP0_Status 12
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#define COP0_Cause 13
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#define COP0_EPC 14
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#define COP0_PRId 15
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#define SR_IEc 0x00000001
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#define SR_KUc 0x00000002
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#define SR_IEp 0x00000004
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#define SR_KUp 0x00000008
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#define SR_IEo 0x00000010
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#define SR_KUo 0x00000020
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#define SR_IMSW0 0x00000100
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#define SR_IMSW1 0x00000200
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#define SR_IMEX0 0x00000400
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#define SR_IMEX1 0x00000800
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#define SR_IMEX2 0x00001000
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#define SR_IMEX3 0x00002000
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#define SR_IMEX4 0x00004000
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#define SR_IMEX5 0x00008000
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#define SR_IsC 0x00010000
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#define SR_SwC 0x00020000
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#define SR_PZ 0x00040000
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#define SR_CM 0x00080000
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#define SR_PE 0x00100000
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#define SR_TS 0x00200000
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#define SR_BEV 0x00400000
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#define SR_RE 0x02000000
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#define SR_COP0 0x10000000
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#define SR_COP1 0x20000000
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#define SR_COP2 0x40000000
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#define SR_COP3 0x80000000
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#define EXCEPTION_INTERRUPT 0
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#define EXCEPTION_TLBMOD 1
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#define EXCEPTION_TLBLOAD 2
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#define EXCEPTION_TLBSTORE 3
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#define EXCEPTION_ADDRLOAD 4
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#define EXCEPTION_ADDRSTORE 5
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#define EXCEPTION_BUSINST 6
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#define EXCEPTION_BUSDATA 7
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#define EXCEPTION_SYSCALL 8
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#define EXCEPTION_BREAK 9
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#define EXCEPTION_INVALIDOP 10
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#define EXCEPTION_BADCOP 11
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#define EXCEPTION_OVERFLOW 12
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#define EXCEPTION_TRAP 13
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/***************************************************************************
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HELPER MACROS
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***************************************************************************/
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#define RSREG ((op >> 21) & 31)
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#define RTREG ((op >> 16) & 31)
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#define RDREG ((op >> 11) & 31)
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#define SHIFT ((op >> 6) & 31)
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#define RSVAL (r3000->r[RSREG])
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#define RTVAL (r3000->r[RTREG])
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#define RDVAL (r3000->r[RDREG])
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#define SIMMVAL ((INT16)op)
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#define UIMMVAL ((UINT16)op)
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#define LIMMVAL (op & 0x03ffffff)
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#define ADDPC(x) r3000->nextpc = r3000->pc + ((x) << 2)
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#define ADDPCL(x,l) { r3000->nextpc = r3000->pc + ((x) << 2); r3000->r[l] = r3000->pc + 4; }
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#define ABSPC(x) r3000->nextpc = (r3000->pc & 0xf0000000) | ((x) << 2)
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#define ABSPCL(x,l) { r3000->nextpc = (r3000->pc & 0xf0000000) | ((x) << 2); r3000->r[l] = r3000->pc + 4; }
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#define SETPC(x) r3000->nextpc = (x)
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#define SETPCL(x,l) { r3000->nextpc = (x); r3000->r[l] = r3000->pc + 4; }
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#define RBYTE(x) (*r3000->cur.readbyte)(x)
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#define RWORD(x) (*r3000->cur.readword)(x)
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#define RLONG(x) (*r3000->cur.readlong)(x)
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#define WBYTE(x,v) (*r3000->cur.writebyte)(x,v)
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#define WWORD(x,v) (*r3000->cur.writeword)(x,v)
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#define WLONG(x,v) (*r3000->cur.writelong)(x,v)
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#define HIVAL r3000->hi
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#define LOVAL r3000->lo
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#define SR r3000->cpr[0][COP0_Status]
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#define CAUSE r3000->cpr[0][COP0_Cause]
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/***************************************************************************
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STRUCTURES & TYPEDEFS
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***************************************************************************/
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/* memory access function table */
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typedef struct
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{
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UINT8 (*readbyte)(offs_t);
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UINT16 (*readword)(offs_t);
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UINT32 (*readlong)(offs_t);
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void (*writebyte)(offs_t, UINT8);
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void (*writeword)(offs_t, UINT16);
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void (*writelong)(offs_t, UINT32);
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} memory_accessors;
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/* R3000 Registers */
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typedef struct _r3000_state r3000_state;
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struct _r3000_state
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{
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/* core registers */
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UINT32 pc;
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UINT32 hi;
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UINT32 lo;
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UINT32 r[32];
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/* COP registers */
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UINT32 cpr[4][32];
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UINT32 ccr[4][32];
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UINT8 cf[4];
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/* internal stuff */
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UINT32 ppc;
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UINT32 nextpc;
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int op;
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int icount;
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int interrupt_cycles;
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int hasfpu;
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int (*irq_callback)(int irqline);
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/* endian-dependent load/store */
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void (*lwl)(r3000_state *r3000, UINT32 op);
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void (*lwr)(r3000_state *r3000, UINT32 op);
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void (*swl)(r3000_state *r3000, UINT32 op);
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void (*swr)(r3000_state *r3000, UINT32 op);
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/* memory accesses */
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UINT8 bigendian;
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memory_accessors cur;
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const memory_accessors *memory_hand;
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const memory_accessors *cache_hand;
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/* cache memory */
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UINT32 * cache;
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UINT32 * icache;
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UINT32 * dcache;
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size_t cache_size;
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size_t icache_size;
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size_t dcache_size;
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};
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/***************************************************************************
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FUNCTION PROTOTYPES
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***************************************************************************/
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static void lwl_be(r3000_state *r3000, UINT32 op);
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static void lwr_be(r3000_state *r3000, UINT32 op);
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static void swl_be(r3000_state *r3000, UINT32 op);
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static void swr_be(r3000_state *r3000, UINT32 op);
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static void lwl_le(r3000_state *r3000, UINT32 op);
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static void lwr_le(r3000_state *r3000, UINT32 op);
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static void swl_le(r3000_state *r3000, UINT32 op);
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static void swr_le(r3000_state *r3000, UINT32 op);
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static UINT8 readcache_be(offs_t offset);
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static UINT16 readcache_be_word(offs_t offset);
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static UINT32 readcache_be_dword(offs_t offset);
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static void writecache_be(offs_t offset, UINT8 data);
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static void writecache_be_word(offs_t offset, UINT16 data);
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static void writecache_be_dword(offs_t offset, UINT32 data);
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static UINT8 readcache_le(offs_t offset);
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static UINT16 readcache_le_word(offs_t offset);
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static UINT32 readcache_le_dword(offs_t offset);
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static void writecache_le(offs_t offset, UINT8 data);
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static void writecache_le_word(offs_t offset, UINT16 data);
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static void writecache_le_dword(offs_t offset, UINT32 data);
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/***************************************************************************
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PRIVATE GLOBAL VARIABLES
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***************************************************************************/
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static void *token;
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static const memory_accessors be_memory =
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{
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program_read_byte_32be, program_read_word_32be, program_read_dword_32be,
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program_write_byte_32be, program_write_word_32be, program_write_dword_32be
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};
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static const memory_accessors le_memory =
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{
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program_read_byte_32le, program_read_word_32le, program_read_dword_32le,
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program_write_byte_32le, program_write_word_32le, program_write_dword_32le
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};
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static const memory_accessors be_cache =
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{
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readcache_be, readcache_be_word, readcache_be_dword,
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writecache_be, writecache_be_word, writecache_be_dword
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};
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static const memory_accessors le_cache =
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{
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readcache_le, readcache_le_word, readcache_le_dword,
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writecache_le, writecache_le_word, writecache_le_dword
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};
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/***************************************************************************
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MEMORY ACCESSORS
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***************************************************************************/
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#define ROPCODE(pc) cpu_readop32(pc)
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/***************************************************************************
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EXECEPTION HANDLING
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***************************************************************************/
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INLINE void generate_exception(r3000_state *r3000, int exception)
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{
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/* set the exception PC */
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r3000->cpr[0][COP0_EPC] = r3000->pc;
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/* put the cause in the low 8 bits and clear the branch delay flag */
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CAUSE = (CAUSE & ~0x800000ff) | (exception << 2);
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/* if we were in a branch delay slot, adjust */
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if (r3000->nextpc != ~0)
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{
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r3000->nextpc = ~0;
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r3000->cpr[0][COP0_EPC] -= 4;
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CAUSE |= 0x80000000;
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}
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/* shift the exception bits */
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SR = (SR & 0xffffffc0) | ((SR << 2) & 0x3c);
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/* based on the BEV bit, we either go to ROM or RAM */
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r3000->pc = (SR & SR_BEV) ? 0xbfc00000 : 0x80000000;
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/* most exceptions go to offset 0x180, except for TLB stuff */
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if (exception >= EXCEPTION_TLBMOD && exception <= EXCEPTION_TLBSTORE)
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r3000->pc += 0x80;
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else
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r3000->pc += 0x180;
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/* swap to the new space */
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change_pc(r3000->pc);
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}
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INLINE void invalid_instruction(r3000_state *r3000, UINT32 op)
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{
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generate_exception(r3000, EXCEPTION_INVALIDOP);
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}
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/***************************************************************************
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IRQ HANDLING
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***************************************************************************/
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static void check_irqs(r3000_state *r3000)
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{
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if ((CAUSE & SR & 0xff00) && (SR & SR_IEc))
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generate_exception(r3000, EXCEPTION_INTERRUPT);
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}
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static void set_irq_line(r3000_state *r3000, int irqline, int state)
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{
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if (state != CLEAR_LINE)
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CAUSE |= 0x400 << irqline;
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else
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CAUSE &= ~(0x400 << irqline);
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check_irqs(r3000);
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}
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/***************************************************************************
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CONTEXT SWITCHING
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***************************************************************************/
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static void r3000_get_context(void *dst)
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{
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/* copy the context */
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if (dst)
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*(void **)dst = token;
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}
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static void r3000_set_context(void *src)
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{
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r3000_state *r3000;
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/* copy the context */
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if (src)
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token = *(void **)src;
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r3000 = token;
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change_pc(r3000->pc);
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/* check for IRQs */
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check_irqs(r3000);
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}
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/***************************************************************************
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INITIALIZATION AND SHUTDOWN
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***************************************************************************/
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static void r3000_init(int index, int clock, const void *_config, int (*irqcallback)(int))
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{
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const r3000_cpu_core *config = _config;
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r3000_state *r3000;
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token = auto_malloc(sizeof(r3000_state));
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r3000 = token;
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/* allocate memory */
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r3000->icache = auto_malloc(config->icache);
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r3000->dcache = auto_malloc(config->dcache);
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r3000->icache_size = config->icache;
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r3000->dcache_size = config->dcache;
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r3000->hasfpu = config->hasfpu;
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r3000->irq_callback = irqcallback;
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}
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static void r3000_reset(r3000_state *r3000, int bigendian)
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{
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/* set up the endianness */
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r3000->bigendian = bigendian;
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if (r3000->bigendian)
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{
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r3000->memory_hand = &be_memory;
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r3000->cache_hand = &be_cache;
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r3000->lwl = lwl_be;
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r3000->lwr = lwr_be;
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r3000->swl = swl_be;
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r3000->swr = swr_be;
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}
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else
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{
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r3000->memory_hand = &le_memory;
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r3000->cache_hand = &le_cache;
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r3000->lwl = lwl_le;
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r3000->lwr = lwr_le;
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r3000->swl = swl_le;
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r3000->swr = swr_le;
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}
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/* initialize the rest of the config */
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r3000->cur = *r3000->memory_hand;
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r3000->cache = r3000->dcache;
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r3000->cache_size = r3000->dcache_size;
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/* initialize the state */
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r3000->pc = 0xbfc00000;
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r3000->nextpc = ~0;
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r3000->cpr[0][COP0_PRId] = 0x0200;
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r3000->cpr[0][COP0_Status] = 0x0000;
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change_pc(r3000->pc);
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}
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static void r3000be_reset(void)
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{
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r3000_reset(token, 1);
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}
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static void r3000le_reset(void)
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{
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r3000_reset(token, 0);
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}
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static void r3000_exit(void)
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{
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}
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/***************************************************************************
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COP0 (SYSTEM) EXECUTION HANDLING
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***************************************************************************/
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INLINE UINT32 get_cop0_reg(r3000_state *r3000, int idx)
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{
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return r3000->cpr[0][idx];
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}
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INLINE void set_cop0_reg(r3000_state *r3000, int idx, UINT32 val)
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{
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if (idx == COP0_Cause)
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{
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CAUSE = (CAUSE & 0xfc00) | (val & ~0xfc00);
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/* update interrupts -- software ints can occur this way */
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check_irqs(r3000);
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}
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else if (idx == COP0_Status)
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{
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UINT32 oldsr = r3000->cpr[0][idx];
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UINT32 diff = oldsr ^ val;
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/* handle cache isolation */
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if (diff & SR_IsC)
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{
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if (val & SR_IsC)
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r3000->cur = *r3000->cache_hand;
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else
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r3000->cur = *r3000->memory_hand;
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}
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/* handle cache switching */
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if (diff & SR_SwC)
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{
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if (val & SR_SwC)
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r3000->cache = r3000->icache, r3000->cache_size = r3000->icache_size;
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else
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r3000->cache = r3000->dcache, r3000->cache_size = r3000->dcache_size;
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}
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r3000->cpr[0][idx] = val;
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/* update interrupts */
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check_irqs(r3000);
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}
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else
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r3000->cpr[0][idx] = val;
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}
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INLINE UINT32 get_cop0_creg(r3000_state *r3000, int idx)
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{
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return r3000->ccr[0][idx];
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}
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INLINE void set_cop0_creg(r3000_state *r3000, int idx, UINT32 val)
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{
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r3000->ccr[0][idx] = val;
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}
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INLINE void handle_cop0(r3000_state *r3000, UINT32 op)
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{
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if (!(SR & SR_COP0) && (SR & SR_KUc))
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generate_exception(r3000, EXCEPTION_BADCOP);
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switch (RSREG)
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{
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case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop0_reg(r3000, RDREG); break;
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case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop0_creg(r3000, RDREG); break;
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case 0x04: /* MTCz */ set_cop0_reg(r3000, RDREG, RTVAL); break;
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case 0x06: /* CTCz */ set_cop0_creg(r3000, RDREG, RTVAL); break;
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case 0x08: /* BC */
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switch (RTREG)
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{
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case 0x00: /* BCzF */ if (!r3000->cf[0]) ADDPC(SIMMVAL); break;
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case 0x01: /* BCzF */ if (r3000->cf[0]) ADDPC(SIMMVAL); break;
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case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break;
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case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break;
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default: invalid_instruction(r3000, op); break;
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}
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break;
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case 0x10:
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case 0x11:
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case 0x12:
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case 0x13:
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17:
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case 0x18:
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case 0x19:
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case 0x1a:
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case 0x1b:
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case 0x1c:
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case 0x1d:
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case 0x1e:
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case 0x1f: /* COP */
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switch (op & 0x01ffffff)
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{
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case 0x01: /* TLBR */ break;
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case 0x02: /* TLBWI */ break;
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case 0x06: /* TLBWR */ break;
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case 0x08: /* TLBP */ break;
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case 0x10: /* RFE */ SR = (SR & 0xfffffff0) | ((SR >> 2) & 0x0f); break;
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case 0x18: /* ERET */ invalid_instruction(r3000, op); break;
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default: invalid_instruction(r3000, op); break;
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}
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break;
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default: invalid_instruction(r3000, op); break;
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}
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}
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|
|
|
/***************************************************************************
|
|
COP1 (FPU) EXECUTION HANDLING
|
|
***************************************************************************/
|
|
|
|
INLINE UINT32 get_cop1_reg(r3000_state *r3000, int idx)
|
|
{
|
|
return r3000->cpr[1][idx];
|
|
}
|
|
|
|
INLINE void set_cop1_reg(r3000_state *r3000, int idx, UINT32 val)
|
|
{
|
|
r3000->cpr[1][idx] = val;
|
|
}
|
|
|
|
INLINE UINT32 get_cop1_creg(r3000_state *r3000, int idx)
|
|
{
|
|
return r3000->ccr[1][idx];
|
|
}
|
|
|
|
INLINE void set_cop1_creg(r3000_state *r3000, int idx, UINT32 val)
|
|
{
|
|
r3000->ccr[1][idx] = val;
|
|
}
|
|
|
|
INLINE void handle_cop1(r3000_state *r3000, UINT32 op)
|
|
{
|
|
if (!(SR & SR_COP1))
|
|
generate_exception(r3000, EXCEPTION_BADCOP);
|
|
if (!r3000->hasfpu)
|
|
return;
|
|
|
|
switch (RSREG)
|
|
{
|
|
case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop1_reg(r3000, RDREG); break;
|
|
case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop1_creg(r3000, RDREG); break;
|
|
case 0x04: /* MTCz */ set_cop1_reg(r3000, RDREG, RTVAL); break;
|
|
case 0x06: /* CTCz */ set_cop1_creg(r3000, RDREG, RTVAL); break;
|
|
case 0x08: /* BC */
|
|
switch (RTREG)
|
|
{
|
|
case 0x00: /* BCzF */ if (!r3000->cf[1]) ADDPC(SIMMVAL); break;
|
|
case 0x01: /* BCzF */ if (r3000->cf[1]) ADDPC(SIMMVAL); break;
|
|
case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break;
|
|
case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break;
|
|
default: invalid_instruction(r3000, op); break;
|
|
}
|
|
break;
|
|
case 0x10:
|
|
case 0x11:
|
|
case 0x12:
|
|
case 0x13:
|
|
case 0x14:
|
|
case 0x15:
|
|
case 0x16:
|
|
case 0x17:
|
|
case 0x18:
|
|
case 0x19:
|
|
case 0x1a:
|
|
case 0x1b:
|
|
case 0x1c:
|
|
case 0x1d:
|
|
case 0x1e:
|
|
case 0x1f: /* COP */ invalid_instruction(r3000, op); break;
|
|
default: invalid_instruction(r3000, op); break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
COP2 (CUSTOM) EXECUTION HANDLING
|
|
***************************************************************************/
|
|
|
|
INLINE UINT32 get_cop2_reg(r3000_state *r3000, int idx)
|
|
{
|
|
return r3000->cpr[2][idx];
|
|
}
|
|
|
|
INLINE void set_cop2_reg(r3000_state *r3000, int idx, UINT32 val)
|
|
{
|
|
r3000->cpr[2][idx] = val;
|
|
}
|
|
|
|
INLINE UINT32 get_cop2_creg(r3000_state *r3000, int idx)
|
|
{
|
|
return r3000->ccr[2][idx];
|
|
}
|
|
|
|
INLINE void set_cop2_creg(r3000_state *r3000, int idx, UINT32 val)
|
|
{
|
|
r3000->ccr[2][idx] = val;
|
|
}
|
|
|
|
INLINE void handle_cop2(r3000_state *r3000, UINT32 op)
|
|
{
|
|
if (!(SR & SR_COP2))
|
|
generate_exception(r3000, EXCEPTION_BADCOP);
|
|
|
|
switch (RSREG)
|
|
{
|
|
case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop2_reg(r3000, RDREG); break;
|
|
case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop2_creg(r3000, RDREG); break;
|
|
case 0x04: /* MTCz */ set_cop2_reg(r3000, RDREG, RTVAL); break;
|
|
case 0x06: /* CTCz */ set_cop2_creg(r3000, RDREG, RTVAL); break;
|
|
case 0x08: /* BC */
|
|
switch (RTREG)
|
|
{
|
|
case 0x00: /* BCzF */ if (!r3000->cf[2]) ADDPC(SIMMVAL); break;
|
|
case 0x01: /* BCzF */ if (r3000->cf[2]) ADDPC(SIMMVAL); break;
|
|
case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break;
|
|
case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break;
|
|
default: invalid_instruction(r3000, op); break;
|
|
}
|
|
break;
|
|
case 0x10:
|
|
case 0x11:
|
|
case 0x12:
|
|
case 0x13:
|
|
case 0x14:
|
|
case 0x15:
|
|
case 0x16:
|
|
case 0x17:
|
|
case 0x18:
|
|
case 0x19:
|
|
case 0x1a:
|
|
case 0x1b:
|
|
case 0x1c:
|
|
case 0x1d:
|
|
case 0x1e:
|
|
case 0x1f: /* COP */ invalid_instruction(r3000, op); break;
|
|
default: invalid_instruction(r3000, op); break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
COP3 (CUSTOM) EXECUTION HANDLING
|
|
***************************************************************************/
|
|
|
|
INLINE UINT32 get_cop3_reg(r3000_state *r3000, int idx)
|
|
{
|
|
return r3000->cpr[3][idx];
|
|
}
|
|
|
|
INLINE void set_cop3_reg(r3000_state *r3000, int idx, UINT32 val)
|
|
{
|
|
r3000->cpr[3][idx] = val;
|
|
}
|
|
|
|
INLINE UINT32 get_cop3_creg(r3000_state *r3000, int idx)
|
|
{
|
|
return r3000->ccr[3][idx];
|
|
}
|
|
|
|
INLINE void set_cop3_creg(r3000_state *r3000, int idx, UINT32 val)
|
|
{
|
|
r3000->ccr[3][idx] = val;
|
|
}
|
|
|
|
INLINE void handle_cop3(r3000_state *r3000, UINT32 op)
|
|
{
|
|
if (!(SR & SR_COP3))
|
|
generate_exception(r3000, EXCEPTION_BADCOP);
|
|
|
|
switch (RSREG)
|
|
{
|
|
case 0x00: /* MFCz */ if (RTREG) RTVAL = get_cop3_reg(r3000, RDREG); break;
|
|
case 0x02: /* CFCz */ if (RTREG) RTVAL = get_cop3_creg(r3000, RDREG); break;
|
|
case 0x04: /* MTCz */ set_cop3_reg(r3000, RDREG, RTVAL); break;
|
|
case 0x06: /* CTCz */ set_cop3_creg(r3000, RDREG, RTVAL); break;
|
|
case 0x08: /* BC */
|
|
switch (RTREG)
|
|
{
|
|
case 0x00: /* BCzF */ if (!r3000->cf[3]) ADDPC(SIMMVAL); break;
|
|
case 0x01: /* BCzF */ if (r3000->cf[3]) ADDPC(SIMMVAL); break;
|
|
case 0x02: /* BCzFL */ invalid_instruction(r3000, op); break;
|
|
case 0x03: /* BCzTL */ invalid_instruction(r3000, op); break;
|
|
default: invalid_instruction(r3000, op); break;
|
|
}
|
|
break;
|
|
case 0x10:
|
|
case 0x11:
|
|
case 0x12:
|
|
case 0x13:
|
|
case 0x14:
|
|
case 0x15:
|
|
case 0x16:
|
|
case 0x17:
|
|
case 0x18:
|
|
case 0x19:
|
|
case 0x1a:
|
|
case 0x1b:
|
|
case 0x1c:
|
|
case 0x1d:
|
|
case 0x1e:
|
|
case 0x1f: /* COP */ invalid_instruction(r3000, op); break;
|
|
default: invalid_instruction(r3000, op); break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
CORE EXECUTION LOOP
|
|
***************************************************************************/
|
|
|
|
static int r3000_execute(int cycles)
|
|
{
|
|
r3000_state *r3000 = token;
|
|
|
|
/* count cycles and interrupt cycles */
|
|
r3000->icount = cycles;
|
|
r3000->icount -= r3000->interrupt_cycles;
|
|
r3000->interrupt_cycles = 0;
|
|
change_pc(r3000->pc);
|
|
|
|
/* core execution loop */
|
|
do
|
|
{
|
|
UINT32 op;
|
|
UINT64 temp64;
|
|
int temp;
|
|
|
|
/* debugging */
|
|
r3000->ppc = r3000->pc;
|
|
debugger_instruction_hook(Machine, r3000->pc);
|
|
|
|
/* instruction fetch */
|
|
op = ROPCODE(r3000->pc);
|
|
|
|
/* adjust for next PC */
|
|
if (r3000->nextpc != ~0)
|
|
{
|
|
r3000->pc = r3000->nextpc;
|
|
r3000->nextpc = ~0;
|
|
change_pc(r3000->pc);
|
|
}
|
|
else
|
|
r3000->pc += 4;
|
|
|
|
/* parse the instruction */
|
|
switch (op >> 26)
|
|
{
|
|
case 0x00: /* SPECIAL */
|
|
switch (op & 63)
|
|
{
|
|
case 0x00: /* SLL */ if (RDREG) RDVAL = RTVAL << SHIFT; break;
|
|
case 0x02: /* SRL */ if (RDREG) RDVAL = RTVAL >> SHIFT; break;
|
|
case 0x03: /* SRA */ if (RDREG) RDVAL = (INT32)RTVAL >> SHIFT; break;
|
|
case 0x04: /* SLLV */ if (RDREG) RDVAL = RTVAL << (RSVAL & 31); break;
|
|
case 0x06: /* SRLV */ if (RDREG) RDVAL = RTVAL >> (RSVAL & 31); break;
|
|
case 0x07: /* SRAV */ if (RDREG) RDVAL = (INT32)RTVAL >> (RSVAL & 31); break;
|
|
case 0x08: /* JR */ SETPC(RSVAL); break;
|
|
case 0x09: /* JALR */ SETPCL(RSVAL,RDREG); break;
|
|
case 0x0c: /* SYSCALL */ generate_exception(r3000, EXCEPTION_SYSCALL); break;
|
|
case 0x0d: /* BREAK */ generate_exception(r3000, EXCEPTION_BREAK); break;
|
|
case 0x0f: /* SYNC */ invalid_instruction(r3000, op); break;
|
|
case 0x10: /* MFHI */ if (RDREG) RDVAL = HIVAL; break;
|
|
case 0x11: /* MTHI */ HIVAL = RSVAL; break;
|
|
case 0x12: /* MFLO */ if (RDREG) RDVAL = LOVAL; break;
|
|
case 0x13: /* MTLO */ LOVAL = RSVAL; break;
|
|
case 0x18: /* MULT */
|
|
temp64 = (INT64)(INT32)RSVAL * (INT64)(INT32)RTVAL;
|
|
LOVAL = (UINT32)temp64;
|
|
HIVAL = (UINT32)(temp64 >> 32);
|
|
r3000->icount -= 11;
|
|
break;
|
|
case 0x19: /* MULTU */
|
|
temp64 = (UINT64)RSVAL * (UINT64)RTVAL;
|
|
LOVAL = (UINT32)temp64;
|
|
HIVAL = (UINT32)(temp64 >> 32);
|
|
r3000->icount -= 11;
|
|
break;
|
|
case 0x1a: /* DIV */
|
|
if (RTVAL)
|
|
{
|
|
LOVAL = (INT32)RSVAL / (INT32)RTVAL;
|
|
HIVAL = (INT32)RSVAL % (INT32)RTVAL;
|
|
}
|
|
r3000->icount -= 34;
|
|
break;
|
|
case 0x1b: /* DIVU */
|
|
if (RTVAL)
|
|
{
|
|
LOVAL = RSVAL / RTVAL;
|
|
HIVAL = RSVAL % RTVAL;
|
|
}
|
|
r3000->icount -= 34;
|
|
break;
|
|
case 0x20: /* ADD */
|
|
if (ENABLE_OVERFLOWS && RSVAL > ~RTVAL) generate_exception(r3000, EXCEPTION_OVERFLOW);
|
|
else RDVAL = RSVAL + RTVAL;
|
|
break;
|
|
case 0x21: /* ADDU */ if (RDREG) RDVAL = RSVAL + RTVAL; break;
|
|
case 0x22: /* SUB */
|
|
if (ENABLE_OVERFLOWS && RSVAL < RTVAL) generate_exception(r3000, EXCEPTION_OVERFLOW);
|
|
else RDVAL = RSVAL - RTVAL;
|
|
break;
|
|
case 0x23: /* SUBU */ if (RDREG) RDVAL = RSVAL - RTVAL; break;
|
|
case 0x24: /* AND */ if (RDREG) RDVAL = RSVAL & RTVAL; break;
|
|
case 0x25: /* OR */ if (RDREG) RDVAL = RSVAL | RTVAL; break;
|
|
case 0x26: /* XOR */ if (RDREG) RDVAL = RSVAL ^ RTVAL; break;
|
|
case 0x27: /* NOR */ if (RDREG) RDVAL = ~(RSVAL | RTVAL); break;
|
|
case 0x2a: /* SLT */ if (RDREG) RDVAL = (INT32)RSVAL < (INT32)RTVAL; break;
|
|
case 0x2b: /* SLTU */ if (RDREG) RDVAL = (UINT32)RSVAL < (UINT32)RTVAL; break;
|
|
case 0x30: /* TEQ */ invalid_instruction(r3000, op); break;
|
|
case 0x31: /* TGEU */ invalid_instruction(r3000, op); break;
|
|
case 0x32: /* TLT */ invalid_instruction(r3000, op); break;
|
|
case 0x33: /* TLTU */ invalid_instruction(r3000, op); break;
|
|
case 0x34: /* TGE */ invalid_instruction(r3000, op); break;
|
|
case 0x36: /* TNE */ invalid_instruction(r3000, op); break;
|
|
default: /* ??? */ invalid_instruction(r3000, op); break;
|
|
}
|
|
break;
|
|
|
|
case 0x01: /* REGIMM */
|
|
switch (RTREG)
|
|
{
|
|
case 0x00: /* BLTZ */ if ((INT32)RSVAL < 0) ADDPC(SIMMVAL); break;
|
|
case 0x01: /* BGEZ */ if ((INT32)RSVAL >= 0) ADDPC(SIMMVAL); break;
|
|
case 0x02: /* BLTZL */ invalid_instruction(r3000, op); break;
|
|
case 0x03: /* BGEZL */ invalid_instruction(r3000, op); break;
|
|
case 0x08: /* TGEI */ invalid_instruction(r3000, op); break;
|
|
case 0x09: /* TGEIU */ invalid_instruction(r3000, op); break;
|
|
case 0x0a: /* TLTI */ invalid_instruction(r3000, op); break;
|
|
case 0x0b: /* TLTIU */ invalid_instruction(r3000, op); break;
|
|
case 0x0c: /* TEQI */ invalid_instruction(r3000, op); break;
|
|
case 0x0e: /* TNEI */ invalid_instruction(r3000, op); break;
|
|
case 0x10: /* BLTZAL */ if ((INT32)RSVAL < 0) ADDPCL(SIMMVAL,31); break;
|
|
case 0x11: /* BGEZAL */ if ((INT32)RSVAL >= 0) ADDPCL(SIMMVAL,31); break;
|
|
case 0x12: /* BLTZALL */ invalid_instruction(r3000, op); break;
|
|
case 0x13: /* BGEZALL */ invalid_instruction(r3000, op); break;
|
|
default: /* ??? */ invalid_instruction(r3000, op); break;
|
|
}
|
|
break;
|
|
|
|
case 0x02: /* J */ ABSPC(LIMMVAL); break;
|
|
case 0x03: /* JAL */ ABSPCL(LIMMVAL,31); break;
|
|
case 0x04: /* BEQ */ if (RSVAL == RTVAL) ADDPC(SIMMVAL); break;
|
|
case 0x05: /* BNE */ if (RSVAL != RTVAL) ADDPC(SIMMVAL); break;
|
|
case 0x06: /* BLEZ */ if ((INT32)RSVAL <= 0) ADDPC(SIMMVAL); break;
|
|
case 0x07: /* BGTZ */ if ((INT32)RSVAL > 0) ADDPC(SIMMVAL); break;
|
|
case 0x08: /* ADDI */
|
|
if (ENABLE_OVERFLOWS && RSVAL > ~SIMMVAL) generate_exception(r3000, EXCEPTION_OVERFLOW);
|
|
else if (RTREG) RTVAL = RSVAL + SIMMVAL;
|
|
break;
|
|
case 0x09: /* ADDIU */ if (RTREG) RTVAL = RSVAL + SIMMVAL; break;
|
|
case 0x0a: /* SLTI */ if (RTREG) RTVAL = (INT32)RSVAL < (INT32)SIMMVAL; break;
|
|
case 0x0b: /* SLTIU */ if (RTREG) RTVAL = (UINT32)RSVAL < (UINT32)SIMMVAL; break;
|
|
case 0x0c: /* ANDI */ if (RTREG) RTVAL = RSVAL & UIMMVAL; break;
|
|
case 0x0d: /* ORI */ if (RTREG) RTVAL = RSVAL | UIMMVAL; break;
|
|
case 0x0e: /* XORI */ if (RTREG) RTVAL = RSVAL ^ UIMMVAL; break;
|
|
case 0x0f: /* LUI */ if (RTREG) RTVAL = UIMMVAL << 16; break;
|
|
case 0x10: /* COP0 */ handle_cop0(r3000, op); break;
|
|
case 0x11: /* COP1 */ handle_cop1(r3000, op); break;
|
|
case 0x12: /* COP2 */ handle_cop2(r3000, op); break;
|
|
case 0x13: /* COP3 */ handle_cop3(r3000, op); break;
|
|
case 0x14: /* BEQL */ invalid_instruction(r3000, op); break;
|
|
case 0x15: /* BNEL */ invalid_instruction(r3000, op); break;
|
|
case 0x16: /* BLEZL */ invalid_instruction(r3000, op); break;
|
|
case 0x17: /* BGTZL */ invalid_instruction(r3000, op); break;
|
|
case 0x20: /* LB */ temp = RBYTE(SIMMVAL+RSVAL); if (RTREG) RTVAL = (INT8)temp; break;
|
|
case 0x21: /* LH */ temp = RWORD(SIMMVAL+RSVAL); if (RTREG) RTVAL = (INT16)temp; break;
|
|
case 0x22: /* LWL */ (*r3000->lwl)(r3000, op); break;
|
|
case 0x23: /* LW */ temp = RLONG(SIMMVAL+RSVAL); if (RTREG) RTVAL = temp; break;
|
|
case 0x24: /* LBU */ temp = RBYTE(SIMMVAL+RSVAL); if (RTREG) RTVAL = (UINT8)temp; break;
|
|
case 0x25: /* LHU */ temp = RWORD(SIMMVAL+RSVAL); if (RTREG) RTVAL = (UINT16)temp; break;
|
|
case 0x26: /* LWR */ (*r3000->lwr)(r3000, op); break;
|
|
case 0x28: /* SB */ WBYTE(SIMMVAL+RSVAL, RTVAL); break;
|
|
case 0x29: /* SH */ WWORD(SIMMVAL+RSVAL, RTVAL); break;
|
|
case 0x2a: /* SWL */ (*r3000->swl)(r3000, op); break;
|
|
case 0x2b: /* SW */ WLONG(SIMMVAL+RSVAL, RTVAL); break;
|
|
case 0x2e: /* SWR */ (*r3000->swr)(r3000, op); break;
|
|
case 0x2f: /* CACHE */ invalid_instruction(r3000, op); break;
|
|
case 0x30: /* LL */ invalid_instruction(r3000, op); break;
|
|
case 0x31: /* LWC1 */ set_cop1_reg(r3000, RTREG, RLONG(SIMMVAL+RSVAL)); break;
|
|
case 0x32: /* LWC2 */ set_cop2_reg(r3000, RTREG, RLONG(SIMMVAL+RSVAL)); break;
|
|
case 0x33: /* LWC3 */ set_cop3_reg(r3000, RTREG, RLONG(SIMMVAL+RSVAL)); break;
|
|
case 0x34: /* LDC0 */ invalid_instruction(r3000, op); break;
|
|
case 0x35: /* LDC1 */ invalid_instruction(r3000, op); break;
|
|
case 0x36: /* LDC2 */ invalid_instruction(r3000, op); break;
|
|
case 0x37: /* LDC3 */ invalid_instruction(r3000, op); break;
|
|
case 0x38: /* SC */ invalid_instruction(r3000, op); break;
|
|
case 0x39: /* LWC1 */ WLONG(SIMMVAL+RSVAL, get_cop1_reg(r3000, RTREG)); break;
|
|
case 0x3a: /* LWC2 */ WLONG(SIMMVAL+RSVAL, get_cop2_reg(r3000, RTREG)); break;
|
|
case 0x3b: /* LWC3 */ WLONG(SIMMVAL+RSVAL, get_cop3_reg(r3000, RTREG)); break;
|
|
case 0x3c: /* SDC0 */ invalid_instruction(r3000, op); break;
|
|
case 0x3d: /* SDC1 */ invalid_instruction(r3000, op); break;
|
|
case 0x3e: /* SDC2 */ invalid_instruction(r3000, op); break;
|
|
case 0x3f: /* SDC3 */ invalid_instruction(r3000, op); break;
|
|
default: /* ??? */ invalid_instruction(r3000, op); break;
|
|
}
|
|
r3000->icount--;
|
|
|
|
} while (r3000->icount > 0 || r3000->nextpc != ~0);
|
|
|
|
r3000->icount -= r3000->interrupt_cycles;
|
|
r3000->interrupt_cycles = 0;
|
|
return cycles - r3000->icount;
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
DISASSEMBLY HOOK
|
|
***************************************************************************/
|
|
|
|
static offs_t r3000_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
|
|
{
|
|
extern unsigned dasmr3k(char *, unsigned, UINT32);
|
|
r3000_state *r3000 = token;
|
|
UINT32 op = *(UINT32 *)oprom;
|
|
if (r3000->bigendian)
|
|
op = BIG_ENDIANIZE_INT32(op);
|
|
else
|
|
op = LITTLE_ENDIANIZE_INT32(op);
|
|
|
|
return dasmr3k(buffer, pc, op);
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
CACHE I/O
|
|
***************************************************************************/
|
|
|
|
static UINT8 readcache_be(offs_t offset)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
return (offset * 4 < r3000->cache_size) ? r3000->cache[BYTE4_XOR_BE(offset)] : 0xff;
|
|
}
|
|
|
|
static UINT16 readcache_be_word(offs_t offset)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
return (offset * 4 < r3000->cache_size) ? *(UINT16 *)&r3000->cache[WORD_XOR_BE(offset)] : 0xffff;
|
|
}
|
|
|
|
static UINT32 readcache_be_dword(offs_t offset)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
return (offset * 4 < r3000->cache_size) ? *(UINT32 *)&r3000->cache[offset] : 0xffffffff;
|
|
}
|
|
|
|
static void writecache_be(offs_t offset, UINT8 data)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
if (offset * 4 < r3000->cache_size) r3000->cache[BYTE4_XOR_BE(offset)] = data;
|
|
}
|
|
|
|
static void writecache_be_word(offs_t offset, UINT16 data)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
if (offset * 4 < r3000->cache_size) *(UINT16 *)&r3000->cache[WORD_XOR_BE(offset)] = data;
|
|
}
|
|
|
|
static void writecache_be_dword(offs_t offset, UINT32 data)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
if (offset * 4 < r3000->cache_size) *(UINT32 *)&r3000->cache[offset] = data;
|
|
}
|
|
|
|
static UINT8 readcache_le(offs_t offset)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
return (offset * 4 < r3000->cache_size) ? r3000->cache[BYTE4_XOR_LE(offset)] : 0xff;
|
|
}
|
|
|
|
static UINT16 readcache_le_word(offs_t offset)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
return (offset * 4 < r3000->cache_size) ? *(UINT16 *)&r3000->cache[WORD_XOR_LE(offset)] : 0xffff;
|
|
}
|
|
|
|
static UINT32 readcache_le_dword(offs_t offset)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
return (offset * 4 < r3000->cache_size) ? *(UINT32 *)&r3000->cache[offset] : 0xffffffff;
|
|
}
|
|
|
|
static void writecache_le(offs_t offset, UINT8 data)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
if (offset * 4 < r3000->cache_size) r3000->cache[BYTE4_XOR_LE(offset)] = data;
|
|
}
|
|
|
|
static void writecache_le_word(offs_t offset, UINT16 data)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
if (offset * 4 < r3000->cache_size) *(UINT16 *)&r3000->cache[WORD_XOR_LE(offset)] = data;
|
|
}
|
|
|
|
static void writecache_le_dword(offs_t offset, UINT32 data)
|
|
{
|
|
r3000_state *r3000 = token; /* fixme */
|
|
offset &= 0x1fffffff;
|
|
if (offset * 4 < r3000->cache_size) *(UINT32 *)&r3000->cache[offset] = data;
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
COMPLEX OPCODE IMPLEMENTATIONS
|
|
***************************************************************************/
|
|
|
|
static void lwl_be(r3000_state *r3000, UINT32 op)
|
|
{
|
|
offs_t offs = SIMMVAL + RSVAL;
|
|
UINT32 temp = RLONG(offs & ~3);
|
|
if (RTREG)
|
|
{
|
|
if (!(offs & 3)) RTVAL = temp;
|
|
else
|
|
{
|
|
int shift = 8 * (offs & 3);
|
|
RTVAL = (RTVAL & (0x00ffffff >> (24 - shift))) | (temp << shift);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void lwr_be(r3000_state *r3000, UINT32 op)
|
|
{
|
|
offs_t offs = SIMMVAL + RSVAL;
|
|
UINT32 temp = RLONG(offs & ~3);
|
|
if (RTREG)
|
|
{
|
|
if ((offs & 3) == 3) RTVAL = temp;
|
|
else
|
|
{
|
|
int shift = 8 * (offs & 3);
|
|
RTVAL = (RTVAL & (0xffffff00 << shift)) | (temp >> (24 - shift));
|
|
}
|
|
}
|
|
}
|
|
|
|
static void swl_be(r3000_state *r3000, UINT32 op)
|
|
{
|
|
offs_t offs = SIMMVAL + RSVAL;
|
|
if (!(offs & 3)) WLONG(offs, RTVAL);
|
|
else
|
|
{
|
|
UINT32 temp = RLONG(offs & ~3);
|
|
int shift = 8 * (offs & 3);
|
|
WLONG(offs & ~3, (temp & (0xffffff00 << (24 - shift))) | (RTVAL >> shift));
|
|
}
|
|
}
|
|
|
|
|
|
static void swr_be(r3000_state *r3000, UINT32 op)
|
|
{
|
|
offs_t offs = SIMMVAL + RSVAL;
|
|
if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL);
|
|
else
|
|
{
|
|
UINT32 temp = RLONG(offs & ~3);
|
|
int shift = 8 * (offs & 3);
|
|
WLONG(offs & ~3, (temp & (0x00ffffff >> shift)) | (RTVAL << (24 - shift)));
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static void lwl_le(r3000_state *r3000, UINT32 op)
|
|
{
|
|
offs_t offs = SIMMVAL + RSVAL;
|
|
UINT32 temp = RLONG(offs & ~3);
|
|
if (RTREG)
|
|
{
|
|
if (!(offs & 3)) RTVAL = temp;
|
|
else
|
|
{
|
|
int shift = 8 * (offs & 3);
|
|
RTVAL = (RTVAL & (0xffffff00 << (24 - shift))) | (temp >> shift);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void lwr_le(r3000_state *r3000, UINT32 op)
|
|
{
|
|
offs_t offs = SIMMVAL + RSVAL;
|
|
UINT32 temp = RLONG(offs & ~3);
|
|
if (RTREG)
|
|
{
|
|
if ((offs & 3) == 3) RTVAL = temp;
|
|
else
|
|
{
|
|
int shift = 8 * (offs & 3);
|
|
RTVAL = (RTVAL & (0x00ffffff >> shift)) | (temp << (24 - shift));
|
|
}
|
|
}
|
|
}
|
|
|
|
static void swl_le(r3000_state *r3000, UINT32 op)
|
|
{
|
|
offs_t offs = SIMMVAL + RSVAL;
|
|
if (!(offs & 3)) WLONG(offs, RTVAL);
|
|
else
|
|
{
|
|
UINT32 temp = RLONG(offs & ~3);
|
|
int shift = 8 * (offs & 3);
|
|
WLONG(offs & ~3, (temp & (0x00ffffff >> (24 - shift))) | (RTVAL << shift));
|
|
}
|
|
}
|
|
|
|
static void swr_le(r3000_state *r3000, UINT32 op)
|
|
{
|
|
offs_t offs = SIMMVAL + RSVAL;
|
|
if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL);
|
|
else
|
|
{
|
|
UINT32 temp = RLONG(offs & ~3);
|
|
int shift = 8 * (offs & 3);
|
|
WLONG(offs & ~3, (temp & (0xffffff00 << shift)) | (RTVAL >> (24 - shift)));
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/**************************************************************************
|
|
* Generic set_info
|
|
**************************************************************************/
|
|
|
|
static void r3000_set_info(UINT32 state, cpuinfo *info)
|
|
{
|
|
r3000_state *r3000 = token;
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are set as 64-bit signed integers --- */
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ0: set_irq_line(r3000, R3000_IRQ0, info->i); break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ1: set_irq_line(r3000, R3000_IRQ1, info->i); break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ2: set_irq_line(r3000, R3000_IRQ2, info->i); break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ3: set_irq_line(r3000, R3000_IRQ3, info->i); break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ4: set_irq_line(r3000, R3000_IRQ4, info->i); break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ5: set_irq_line(r3000, R3000_IRQ5, info->i); break;
|
|
|
|
case CPUINFO_INT_PC:
|
|
case CPUINFO_INT_REGISTER + R3000_PC: r3000->pc = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_SR: SR = info->i; break;
|
|
|
|
case CPUINFO_INT_REGISTER + R3000_R0: r3000->r[0] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R1: r3000->r[1] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R2: r3000->r[2] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R3: r3000->r[3] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R4: r3000->r[4] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R5: r3000->r[5] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R6: r3000->r[6] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R7: r3000->r[7] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R8: r3000->r[8] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R9: r3000->r[9] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R10: r3000->r[10] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R11: r3000->r[11] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R12: r3000->r[12] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R13: r3000->r[13] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R14: r3000->r[14] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R15: r3000->r[15] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R16: r3000->r[16] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R17: r3000->r[17] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R18: r3000->r[18] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R19: r3000->r[19] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R20: r3000->r[20] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R21: r3000->r[21] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R22: r3000->r[22] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R23: r3000->r[23] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R24: r3000->r[24] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R25: r3000->r[25] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R26: r3000->r[26] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R27: r3000->r[27] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R28: r3000->r[28] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R29: r3000->r[29] = info->i; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R30: r3000->r[30] = info->i; break;
|
|
case CPUINFO_INT_SP:
|
|
case CPUINFO_INT_REGISTER + R3000_R31: r3000->r[31] = info->i; break;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/**************************************************************************
|
|
* Generic get_info
|
|
**************************************************************************/
|
|
|
|
static void r3000_get_info(UINT32 state, cpuinfo *info)
|
|
{
|
|
r3000_state *r3000 = token;
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
|
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(r3000); break;
|
|
case CPUINFO_INT_INPUT_LINES: info->i = 6; break;
|
|
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
|
|
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
|
|
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
|
|
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
|
|
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break;
|
|
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
|
|
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
|
|
case CPUINFO_INT_MAX_CYCLES: info->i = 40; break;
|
|
|
|
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
|
|
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 29; break;
|
|
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
|
|
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
|
|
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
|
|
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
|
|
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
|
|
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
|
|
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
|
|
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ0: info->i = (r3000->cpr[0][COP0_Cause] & 0x400) ? ASSERT_LINE : CLEAR_LINE; break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ1: info->i = (r3000->cpr[0][COP0_Cause] & 0x800) ? ASSERT_LINE : CLEAR_LINE; break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ2: info->i = (r3000->cpr[0][COP0_Cause] & 0x1000) ? ASSERT_LINE : CLEAR_LINE; break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ3: info->i = (r3000->cpr[0][COP0_Cause] & 0x2000) ? ASSERT_LINE : CLEAR_LINE; break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ4: info->i = (r3000->cpr[0][COP0_Cause] & 0x4000) ? ASSERT_LINE : CLEAR_LINE; break;
|
|
case CPUINFO_INT_INPUT_STATE + R3000_IRQ5: info->i = (r3000->cpr[0][COP0_Cause] & 0x8000) ? ASSERT_LINE : CLEAR_LINE; break;
|
|
|
|
case CPUINFO_INT_PREVIOUSPC: info->i = r3000->ppc; break;
|
|
|
|
case CPUINFO_INT_PC: info->i = r3000->pc & 0x1fffffff; break;
|
|
case CPUINFO_INT_REGISTER + R3000_PC: info->i = r3000->pc; break;
|
|
case CPUINFO_INT_REGISTER + R3000_SR: info->i = SR; break;
|
|
|
|
case CPUINFO_INT_REGISTER + R3000_R0: info->i = r3000->r[0]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R1: info->i = r3000->r[1]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R2: info->i = r3000->r[2]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R3: info->i = r3000->r[3]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R4: info->i = r3000->r[4]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R5: info->i = r3000->r[5]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R6: info->i = r3000->r[6]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R7: info->i = r3000->r[7]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R8: info->i = r3000->r[8]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R9: info->i = r3000->r[9]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R10: info->i = r3000->r[10]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R11: info->i = r3000->r[11]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R12: info->i = r3000->r[12]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R13: info->i = r3000->r[13]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R14: info->i = r3000->r[14]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R15: info->i = r3000->r[15]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R16: info->i = r3000->r[16]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R17: info->i = r3000->r[17]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R18: info->i = r3000->r[18]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R19: info->i = r3000->r[19]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R20: info->i = r3000->r[20]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R21: info->i = r3000->r[21]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R22: info->i = r3000->r[22]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R23: info->i = r3000->r[23]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R24: info->i = r3000->r[24]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R25: info->i = r3000->r[25]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R26: info->i = r3000->r[26]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R27: info->i = r3000->r[27]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R28: info->i = r3000->r[28]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R29: info->i = r3000->r[29]; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R30: info->i = r3000->r[30]; break;
|
|
case CPUINFO_INT_SP: info->i = r3000->r[31] & 0x1fffffff; break;
|
|
case CPUINFO_INT_REGISTER + R3000_R31: info->i = r3000->r[31]; break;
|
|
|
|
/* --- the following bits of info are returned as pointers to data or functions --- */
|
|
case CPUINFO_PTR_SET_INFO: info->setinfo = r3000_set_info; break;
|
|
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = r3000_get_context; break;
|
|
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = r3000_set_context; break;
|
|
case CPUINFO_PTR_INIT: info->init = r3000_init; break;
|
|
case CPUINFO_PTR_RESET: /* provided per-CPU */ break;
|
|
case CPUINFO_PTR_EXIT: info->exit = r3000_exit; break;
|
|
case CPUINFO_PTR_EXECUTE: info->execute = r3000_execute; break;
|
|
case CPUINFO_PTR_BURN: info->burn = NULL; break;
|
|
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = r3000_dasm; break;
|
|
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &r3000->icount; break;
|
|
|
|
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
|
case CPUINFO_STR_NAME: strcpy(info->s, "R3000"); break;
|
|
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "MIPS II"); break;
|
|
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.0"); break;
|
|
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
|
|
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Aaron Giles"); break;
|
|
|
|
case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break;
|
|
|
|
case CPUINFO_STR_REGISTER + R3000_PC: sprintf(info->s, "PC: %08X", r3000->pc); break;
|
|
case CPUINFO_STR_REGISTER + R3000_SR: sprintf(info->s, "SR: %08X", r3000->cpr[0][COP0_Status]); break;
|
|
|
|
case CPUINFO_STR_REGISTER + R3000_R0: sprintf(info->s, "R0: %08X", r3000->r[0]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R1: sprintf(info->s, "R1: %08X", r3000->r[1]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R2: sprintf(info->s, "R2: %08X", r3000->r[2]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R3: sprintf(info->s, "R3: %08X", r3000->r[3]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R4: sprintf(info->s, "R4: %08X", r3000->r[4]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R5: sprintf(info->s, "R5: %08X", r3000->r[5]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R6: sprintf(info->s, "R6: %08X", r3000->r[6]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R7: sprintf(info->s, "R7: %08X", r3000->r[7]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R8: sprintf(info->s, "R8: %08X", r3000->r[8]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R9: sprintf(info->s, "R9: %08X", r3000->r[9]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R10: sprintf(info->s, "R10:%08X", r3000->r[10]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R11: sprintf(info->s, "R11:%08X", r3000->r[11]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R12: sprintf(info->s, "R12:%08X", r3000->r[12]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R13: sprintf(info->s, "R13:%08X", r3000->r[13]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R14: sprintf(info->s, "R14:%08X", r3000->r[14]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R15: sprintf(info->s, "R15:%08X", r3000->r[15]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R16: sprintf(info->s, "R16:%08X", r3000->r[16]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R17: sprintf(info->s, "R17:%08X", r3000->r[17]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R18: sprintf(info->s, "R18:%08X", r3000->r[18]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R19: sprintf(info->s, "R19:%08X", r3000->r[19]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R20: sprintf(info->s, "R20:%08X", r3000->r[20]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R21: sprintf(info->s, "R21:%08X", r3000->r[21]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R22: sprintf(info->s, "R22:%08X", r3000->r[22]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R23: sprintf(info->s, "R23:%08X", r3000->r[23]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R24: sprintf(info->s, "R24:%08X", r3000->r[24]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R25: sprintf(info->s, "R25:%08X", r3000->r[25]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R26: sprintf(info->s, "R26:%08X", r3000->r[26]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R27: sprintf(info->s, "R27:%08X", r3000->r[27]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R28: sprintf(info->s, "R28:%08X", r3000->r[28]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R29: sprintf(info->s, "R29:%08X", r3000->r[29]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R30: sprintf(info->s, "R30:%08X", r3000->r[30]); break;
|
|
case CPUINFO_STR_REGISTER + R3000_R31: sprintf(info->s, "R31:%08X", r3000->r[31]); break;
|
|
}
|
|
}
|
|
|
|
|
|
/**************************************************************************
|
|
* CPU-specific set_info
|
|
**************************************************************************/
|
|
|
|
void r3000be_get_info(UINT32 state, cpuinfo *info)
|
|
{
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
|
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_BE; break;
|
|
|
|
/* --- the following bits of info are returned as pointers to data or functions --- */
|
|
case CPUINFO_PTR_RESET: info->reset = r3000be_reset; break;
|
|
|
|
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
|
case CPUINFO_STR_NAME: strcpy(info->s, "R3000 (big)"); break;
|
|
|
|
default: r3000_get_info(state, info); break;
|
|
}
|
|
}
|
|
|
|
|
|
void r3000le_get_info(UINT32 state, cpuinfo *info)
|
|
{
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
|
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
|
|
|
|
/* --- the following bits of info are returned as pointers to data or functions --- */
|
|
case CPUINFO_PTR_RESET: info->reset = r3000le_reset; break;
|
|
|
|
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
|
case CPUINFO_STR_NAME: strcpy(info->s, "R3000 (little)"); break;
|
|
|
|
default: r3000_get_info(state, info); break;
|
|
}
|
|
}
|
|
|
|
|
|
void r3041be_get_info(UINT32 state, cpuinfo *info)
|
|
{
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
|
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_BE; break;
|
|
|
|
/* --- the following bits of info are returned as pointers to data or functions --- */
|
|
case CPUINFO_PTR_RESET: info->reset = r3000be_reset; break;
|
|
|
|
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
|
case CPUINFO_STR_NAME: strcpy(info->s, "R3041 (big)"); break;
|
|
|
|
default: r3000_get_info(state, info); break;
|
|
}
|
|
}
|
|
|
|
|
|
void r3041le_get_info(UINT32 state, cpuinfo *info)
|
|
{
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
|
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
|
|
|
|
/* --- the following bits of info are returned as pointers to data or functions --- */
|
|
case CPUINFO_PTR_RESET: info->reset = r3000le_reset; break;
|
|
|
|
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
|
case CPUINFO_STR_NAME: strcpy(info->s, "R3041 (little)"); break;
|
|
|
|
default: r3000_get_info(state, info); break;
|
|
}
|
|
}
|