mirror of
https://github.com/holub/mame
synced 2025-10-04 16:34:53 +03:00
254 lines
9.4 KiB
C++
254 lines
9.4 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:F. Ulivi
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//
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// *****************************************
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// Emulator for HP "hybrid" processor series
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// *****************************************
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//
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// The HP hybrid processor series is composed of a few different models with different
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// capabilities. The series was derived from HP's own 2116 processor by translating a
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// discrete implementation of the 1960s into a multi-chip module (hence the "hybrid" name).
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// This emulator currently supports both the 5061-3001 & the 5061-3011 versions.
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//
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// For this emulator I mainly relied on these sources:
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// - http://www.hp9845.net/ website
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// - HP manual "Assembly development ROM manual for the HP9845": this is the most precious
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// and "enabling" resource of all
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// - US Patent 4,180,854 describing the HP9845 system
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// - Study of disassembly of firmware of HP64000 & HP9845 systems
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// - hp9800e emulator for inspiration on implementing EMC instructions
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// - A lot of "educated" guessing
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#ifndef _HPHYBRID_H_
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#define _HPHYBRID_H_
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// Input lines
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#define HPHYBRID_IRH 0 // High-level interrupt
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#define HPHYBRID_IRL 1 // Low-level interrupt
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#define HPHYBRID_INT_LVLS 2 // Levels of interrupt
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// I/O addressing space (16-bit wide)
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// Addresses into this space are composed as follows:
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// b[5..2] = Peripheral address 0..15
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// b[1..0] = Register address (IC) 0..3
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#define HP_IOADDR_PA_SHIFT 2
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#define HP_IOADDR_IC_SHIFT 0
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// Compose an I/O address from PA & IC
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#define HP_MAKE_IOADDR(pa , ic) (((pa) << HP_IOADDR_PA_SHIFT) | ((ic) << HP_IOADDR_IC_SHIFT))
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// Addresses of memory mapped registers
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#define HP_REG_A_ADDR 0x0000
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#define HP_REG_B_ADDR 0x0001
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#define HP_REG_P_ADDR 0x0002
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#define HP_REG_R_ADDR 0x0003
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#define HP_REG_R4_ADDR 0x0004
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#define HP_REG_R5_ADDR 0x0005
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#define HP_REG_R6_ADDR 0x0006
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#define HP_REG_R7_ADDR 0x0007
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#define HP_REG_IV_ADDR 0x0008
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#define HP_REG_PA_ADDR 0x0009
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#define HP_REG_W_ADDR 0x000A
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#define HP_REG_DMAPA_ADDR 0x000B
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#define HP_REG_DMAMA_ADDR 0x000C
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#define HP_REG_DMAC_ADDR 0x000D
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#define HP_REG_C_ADDR 0x000e
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#define HP_REG_D_ADDR 0x000f
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#define HP_REG_AR2_ADDR 0x0010
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#define HP_REG_SE_ADDR 0x0014
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#define HP_REG_R25_ADDR 0x0015
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#define HP_REG_R26_ADDR 0x0016
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#define HP_REG_R27_ADDR 0x0017
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#define HP_REG_R32_ADDR 0x001a
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#define HP_REG_R33_ADDR 0x001b
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#define HP_REG_R34_ADDR 0x001c
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#define HP_REG_R35_ADDR 0x001d
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#define HP_REG_R36_ADDR 0x001e
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#define HP_REG_R37_ADDR 0x001f
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#define HP_REG_LAST_ADDR 0x001f
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#define HP_REG_AR1_ADDR 0xfff8
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#define HP_REG_IV_MASK 0xfff0
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#define HP_REG_PA_MASK 0x000f
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// Set boot mode of 5061-3001: either normal (false) or as in HP9845 system (true)
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#define MCFG_HPHYBRID_SET_9845_BOOT(_mode) \
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hp_5061_3001_cpu_device::set_boot_mode_static(*device, _mode);
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// PA changed callback
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#define MCFG_HPHYBRID_PA_CHANGED(_devcb) \
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hp_hybrid_cpu_device::set_pa_changed_func(*device , DEVCB_##_devcb);
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class hp_hybrid_cpu_device : public cpu_device
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{
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public:
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DECLARE_WRITE_LINE_MEMBER(dmar_w);
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DECLARE_WRITE_LINE_MEMBER(halt_w);
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DECLARE_WRITE_LINE_MEMBER(status_w);
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DECLARE_WRITE_LINE_MEMBER(flag_w);
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UINT8 pa_r(void) const;
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template<class _Object> static devcb_base &set_pa_changed_func(device_t &device, _Object object) { return downcast<hp_hybrid_cpu_device &>(device).m_pa_changed_func.set_callback(object); }
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protected:
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hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth);
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const override { return 6; }
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virtual UINT32 execute_input_lines() const override { return 2; }
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virtual UINT32 execute_default_irq_vector() const override { return 0xffff; }
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virtual void execute_run() override;
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virtual void execute_set_input(int inputnum, int state) override;
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UINT16 execute_one(UINT16 opcode);
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UINT16 execute_one_sub(UINT16 opcode);
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// Execute an instruction that doesn't belong to either BPC or IOC
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virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) = 0;
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : nullptr ); }
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// device_state_interface overrides
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void state_string_export(const device_state_entry &entry, std::string &str) const override;
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const override { return 2; }
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virtual UINT32 disasm_max_opcode_bytes() const override { return 2; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override;
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// Different cases of memory access
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// See patent @ pg 361
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typedef enum {
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AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses
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AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses
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AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses
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AEC_CASE_D, // DMA accesses
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AEC_CASE_I // Interrupt vector fetches
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} aec_cases_t;
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// do memory address extension
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virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) = 0;
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UINT16 remove_mae(UINT32 addr);
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UINT16 RM(aec_cases_t aec_case , UINT16 addr);
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UINT16 RM(UINT32 addr);
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virtual UINT16 read_non_common_reg(UINT16 addr) = 0;
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void WM(aec_cases_t aec_case , UINT16 addr , UINT16 v);
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void WM(UINT32 addr , UINT16 v);
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virtual void write_non_common_reg(UINT16 addr , UINT16 v) = 0;
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UINT16 fetch(void);
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UINT16 get_skip_addr(UINT16 opcode , bool condition) const;
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devcb_write8 m_pa_changed_func;
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int m_icount;
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bool m_forced_bsc_25;
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// State of processor
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UINT16 m_reg_A; // Register A
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UINT16 m_reg_B; // Register B
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UINT16 m_reg_P; // Register P
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UINT16 m_reg_R; // Register R
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UINT16 m_reg_C; // Register C
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UINT16 m_reg_D; // Register D
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UINT16 m_reg_IV; // Register IV
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UINT16 m_reg_W; // Register W
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UINT8 m_reg_PA[ HPHYBRID_INT_LVLS + 1 ]; // Stack of register PA (4 bit-long)
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UINT32 m_flags; // Flags
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UINT8 m_dmapa; // DMA peripheral address (4 bits)
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UINT16 m_dmama; // DMA address
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UINT16 m_dmac; // DMA counter
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UINT16 m_reg_I; // Instruction register
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UINT32 m_genpc; // Full PC
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private:
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address_space_config m_program_config;
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address_space_config m_io_config;
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address_space *m_program;
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direct_read_data *m_direct;
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address_space *m_io;
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UINT32 get_ea(UINT16 opcode);
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void do_add(UINT16& addend1 , UINT16 addend2);
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UINT16 get_skip_addr_sc(UINT16 opcode , UINT16& v , unsigned n);
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UINT16 get_skip_addr_sc(UINT16 opcode , UINT32& v , unsigned n);
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void do_pw(UINT16 opcode);
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void check_for_interrupts(void);
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virtual void enter_isr(void);
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void handle_dma(void);
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UINT16 RIO(UINT8 pa , UINT8 ic);
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void WIO(UINT8 pa , UINT8 ic , UINT16 v);
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};
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class hp_5061_3001_cpu_device : public hp_hybrid_cpu_device
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{
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public:
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hp_5061_3001_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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static void set_boot_mode_static(device_t &device, bool mode) { downcast<hp_5061_3001_cpu_device &>(device).m_boot_mode = mode; }
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protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual UINT32 execute_max_cycles() const override { return 237; } // FMP 15
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static UINT8 do_dec_shift_r(UINT8 d1 , UINT64& mantissa);
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static UINT8 do_dec_shift_l(UINT8 d12 , UINT64& mantissa);
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UINT64 get_ar1(void);
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void set_ar1(UINT64 v);
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UINT64 get_ar2(void) const;
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void set_ar2(UINT64 v);
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UINT64 do_mrxy(UINT64 ar);
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bool do_dec_add(bool carry_in , UINT64& a , UINT64 b);
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void do_mpy(void);
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virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) override;
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override;
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virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) override;
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virtual UINT16 read_non_common_reg(UINT16 addr) override;
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virtual void write_non_common_reg(UINT16 addr , UINT16 v) override;
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private:
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bool m_boot_mode;
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// Additional state of processor
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UINT16 m_reg_ar2[ 4 ]; // AR2 register
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UINT16 m_reg_se; // SE register (4 bits)
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UINT16 m_reg_r25; // R25 register
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UINT16 m_reg_r26; // R26 register
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UINT16 m_reg_r27; // R27 register
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UINT16 m_reg_aec[ HP_REG_R37_ADDR - HP_REG_R32_ADDR + 1 ]; // AEC registers R32-R37
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virtual void enter_isr(void) override;
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};
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class hp_5061_3011_cpu_device : public hp_hybrid_cpu_device
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{
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public:
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hp_5061_3011_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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protected:
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virtual UINT32 execute_max_cycles() const override { return 25; }
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virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) override;
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virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) override;
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virtual UINT16 read_non_common_reg(UINT16 addr) override;
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virtual void write_non_common_reg(UINT16 addr , UINT16 v) override;
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};
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extern const device_type HP_5061_3001;
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extern const device_type HP_5061_3011;
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#endif /* _HPHYBRID_H_ */
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