71f101d9a7
bbcbp: Added ATPL Sidewise+ internal expansion board. bbcm: Added Morley Master 'AA' and Vine Micros Overlay internal expansion boards.
303 lines
7.3 KiB
C++
303 lines
7.3 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:Nigel Barnes
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/**********************************************************************
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Solidisk Fourmeg RAM/ROM Expansions
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http://chrisacorns.computinghistory.org.uk/8bit_Upgrades/Solidisk_4Meg.html
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**********************************************************************/
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#include "emu.h"
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#include "stl4m32.h"
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//**************************************************************************
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// DEVICE DEFINITIONS
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//**************************************************************************
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DEFINE_DEVICE_TYPE(BBC_STL4M32, bbc_stl4m32_device, "bbc_stl4m32", "Solidisk Fourmeg 32K RAM/ROM Expansion");
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//-------------------------------------------------
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// INPUT_PORTS( stl4m )
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//-------------------------------------------------
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INPUT_PORTS_START(stl4m32)
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PORT_START("stl4m_clock")
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PORT_CONFNAME(0x01, 0x01, "4MHz Clock") PORT_CHANGED_MEMBER(DEVICE_SELF, bbc_stl4m32_device, clock_switch, 0)
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PORT_CONFSETTING(0x00, "2MHz")
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PORT_CONFSETTING(0x01, "4MHz")
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INPUT_PORTS_END
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//-------------------------------------------------
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// input_ports - device-specific input ports
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//-------------------------------------------------
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ioport_constructor bbc_stl4m32_device::device_input_ports() const
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{
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return INPUT_PORTS_NAME(stl4m32);
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}
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//-------------------------------------------------
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// ROM( stl4m32 )
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//-------------------------------------------------
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ROM_START(stl4m32)
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ROM_REGION(0x4000, "rom", 0)
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ROM_SYSTEM_BIOS(0, "30", "Manager 3.00 (16.6.86)")
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ROMX_LOAD("manager_4meg32k-16.6.86.rom", 0x0000, 0x4000, CRC(2024cd0d) SHA1(cf45217ac88480a6963cbf75e8cf684cd81c7b09), ROM_BIOS(0))
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ROM_END
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//-------------------------------------------------
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// device_add_mconfig - add device configuration
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//-------------------------------------------------
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void bbc_stl4m32_device::device_add_mconfig(machine_config &config)
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{
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//M65SC02(config.replace(), m_maincpu, DERIVED_CLOCK(1, 4));
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/* 5 x 32K rom sockets */
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BBC_ROMSLOT32(config, m_rom[4], bbc_rom_devices, nullptr);
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BBC_ROMSLOT32(config, m_rom[6], bbc_rom_devices, nullptr);
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BBC_ROMSLOT32(config, m_rom[8], bbc_rom_devices, nullptr);
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BBC_ROMSLOT32(config, m_rom[10], bbc_rom_devices, nullptr);
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BBC_ROMSLOT32(config, m_rom[12], bbc_rom_devices, nullptr);
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BBC_ROMSLOT16(config, m_rom[14], bbc_rom_devices, "ram").set_fixed_ram(true);
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BBC_ROMSLOT16(config, m_rom[15], bbc_rom_devices, "ram").set_fixed_ram(true);
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}
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const tiny_rom_entry *bbc_stl4m32_device::device_rom_region() const
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{
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return ROM_NAME(stl4m32);
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}
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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//-------------------------------------------------
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// bbc_stl4m32_device - constructor
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//-------------------------------------------------
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bbc_stl4m32_device::bbc_stl4m32_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: device_t(mconfig, BBC_STL4M32, tag, owner, clock)
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, device_bbc_internal_interface(mconfig, *this)
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, m_rom(*this, "romslot%u", 0U)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void bbc_stl4m32_device::device_start()
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{
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m_ram = std::make_unique<uint8_t[]>(0x8000);
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/* move internal roms to board */
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memmove(m_region_swr->base() + 0x30000, m_region_swr->base() + 0xc000, 0x4000);
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memcpy(m_region_swr->base() + 0x28000, memregion("rom")->base(), 0x4000);
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memset(m_region_swr->base() + 0x0c000, 0xff, 0x4000);
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/* register for save states */
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save_pointer(NAME(m_ram), 0x8000);
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save_item(NAME(m_romsel));
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save_item(NAME(m_ramsel));
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save_item(NAME(m_shadow));
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}
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//-------------------------------------------------
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// device_reset_after_children - reset after child devices
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//-------------------------------------------------
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void bbc_stl4m32_device::device_reset() //_after_children()
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{
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/* set cpu clock to 4mhz */
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//m_maincpu->set_clock(DERIVED_CLOCK(1, 4));
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}
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//**************************************************************************
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// IMPLEMENTATION
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//**************************************************************************
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INPUT_CHANGED_MEMBER(bbc_stl4m32_device::clock_switch)
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{
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switch (newval)
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{
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case 0:
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//m_maincpu->set_clock(DERIVED_CLOCK(1, 8));
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break;
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case 1:
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//m_maincpu->set_clock(DERIVED_CLOCK(1, 4));
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break;
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}
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}
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void bbc_stl4m32_device::romsel_w(offs_t offset, uint8_t data)
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{
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logerror("romsel_w: %04x = %02x\n", offset | 0xfe30, data);
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switch (offset & 0x0e)
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{
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case 0x00:
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m_romsel = data & 0x0f;
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break;
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case 0x02:
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m_ramsel = data;
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break;
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case 0x04:
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m_shadow = data;
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break;
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}
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}
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uint8_t bbc_stl4m32_device::ram_r(offs_t offset)
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{
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uint8_t data = 0xff;
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if (BIT(m_shadow, 7) && offset >= 0x2000)
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{
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data = m_ram[offset];
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}
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else
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{
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data = m_mb_ram->pointer()[offset];
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}
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return data;
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}
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void bbc_stl4m32_device::ram_w(offs_t offset, uint8_t data)
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{
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if ((offset & 0xff) == 0x00)
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logerror("ram_w: %04x = %02x\n", offset, data);
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if (BIT(m_romsel, 7) && offset >= 0x2000)
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{
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m_ram[offset] = data;
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}
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else
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{
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m_mb_ram->pointer()[offset] = data;
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}
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}
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uint8_t bbc_stl4m32_device::paged_r(offs_t offset)
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{
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uint8_t data = 0xff;
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if (BIT(m_romsel, 7) && offset < 0x2000)
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{
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data = m_ram[offset];
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}
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else
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{
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switch (m_romsel)
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{
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case 0: case 1: case 2: case 3:
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/* motherboard rom sockets */
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if (m_mb_rom[m_romsel] && m_mb_rom[m_romsel]->present())
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{
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data = m_mb_rom[m_romsel]->read(offset);
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}
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else
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{
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data = m_region_swr->base()[offset + (m_romsel << 14)];
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}
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break;
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case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11: case 12: case 13:
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/* expansion board rom sockets */
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if (m_rom[m_romsel & 0x0e] && m_rom[m_romsel & 0x0e]->present())
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{
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data = m_rom[m_romsel & 0x0e]->read(offset | (m_romsel & 0x01) << 14);
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}
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else
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{
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data = m_region_swr->base()[offset + (m_romsel << 14)];
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}
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break;
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case 14: case 15:
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/* expansion board ram sockets */
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data = m_ram[offset | ((m_romsel & 0x01) << 14)];
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break;
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}
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}
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return data;
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}
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void bbc_stl4m32_device::paged_w(offs_t offset, uint8_t data)
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{
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if ((offset & 0xff) == 0x00)
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logerror("paged_w: %04x = %02x\n", offset | 0x8000, data);
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if (BIT(m_romsel, 7) && offset < 0x2000)
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{
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m_ram[offset] = data;
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}
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else
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{
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switch (m_romsel)
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{
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case 0: case 1: case 2: case 3:
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/* motherboard rom sockets */
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if (m_mb_rom[m_romsel])
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{
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m_mb_rom[m_romsel]->write(offset, data);
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}
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break;
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case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11: case 12: case 13:
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/* expansion board rom sockets */
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if (m_rom[m_romsel & 0x0e])
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{
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m_rom[m_romsel & 0x0e]->write(offset | (m_romsel & 0x01) << 14, data);
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}
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break;
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}
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if (m_ramsel == 14 || m_ramsel == 15)
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{
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/* expansion board ram sockets */
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m_ram[offset | ((m_ramsel & 0x01) << 14)] = data;
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}
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}
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}
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uint8_t bbc_stl4m32_device::mos_r(offs_t offset)
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{
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uint8_t data = 0xff;
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//if (BIT(m_shadow, 7) && offset >= 0x2000)
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//{
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// data = m_ram[offset];
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//}
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//else
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//{
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data = m_region_mos->base()[offset];
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//}
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return data;
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}
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void bbc_stl4m32_device::mos_w(offs_t offset, uint8_t data)
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{
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if ((offset & 0xff) == 0x00)
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logerror("mos_w: %04x = %02x\n", offset | 0xc000, data);
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//if (BIT(m_romsel, 7) && offset >= 0x2000)
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//{
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// m_ram[offset] = data;
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//}
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} |