mirror of
https://github.com/holub/mame
synced 2025-06-23 04:48:37 +03:00
82a2535d38
- removed family_setter - naming alignment, family becomes model. - architecture cleanups.) - reviewed reset logic. - pass truthtable family as string to factory. This is another set of changes on the path to align logic families and models. As a side effect, the object model now makes a clear distinction between analog models and logic models. The number of macros in nl_base.h has decreased significantly due to these changes.
124 lines
2.4 KiB
C++
124 lines
2.4 KiB
C++
// license:GPL-2.0+
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// copyright-holders:Couriersud
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/*
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* nld_74174.cpp
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*
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*/
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#include "nld_74174.h"
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#include "netlist/nl_base.h"
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namespace netlist
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{
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namespace devices
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{
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NETLIB_OBJECT(74174)
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{
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NETLIB_CONSTRUCTOR(74174)
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, m_CLK(*this, "CLK", NETLIB_DELEGATE(74174, sub))
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, m_Q(*this, {"Q1", "Q2", "Q3", "Q4", "Q5", "Q6"})
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, m_clrq(*this, "m_clr", 0)
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, m_data(*this, "m_data", 0)
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, m_D(*this, {"D1", "D2", "D3", "D4", "D5", "D6"})
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, m_CLRQ(*this, "CLRQ")
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, m_power_pins(*this)
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{
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}
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NETLIB_RESETI()
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{
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m_CLK.set_state(logic_t::STATE_INP_LH);
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m_clrq = 0;
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m_data = 0xFF;
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}
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NETLIB_UPDATEI();
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NETLIB_HANDLERI(sub)
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{
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if (m_clrq)
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{
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for (std::size_t i=0; i<6; i++)
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{
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netlist_sig_t d = (m_data >> i) & 1;
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m_Q[i].push(d, NLTIME_FROM_NS(25));
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}
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m_CLK.inactivate();
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}
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}
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friend class NETLIB_NAME(74174_dip);
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private:
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logic_input_t m_CLK;
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object_array_t<logic_output_t, 6> m_Q;
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state_var<netlist_sig_t> m_clrq;
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state_var<unsigned> m_data;
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object_array_t<logic_input_t, 6> m_D;
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logic_input_t m_CLRQ;
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nld_power_pins m_power_pins;
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};
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NETLIB_OBJECT(74174_dip)
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{
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NETLIB_CONSTRUCTOR(74174_dip)
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, A(*this, "A")
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{
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register_subalias("1", A.m_CLRQ);
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register_subalias("9", A.m_CLK);
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register_subalias("3", A.m_D[0]);
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register_subalias("2", A.m_Q[0]);
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register_subalias("4", A.m_D[1]);
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register_subalias("5", A.m_Q[1]);
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register_subalias("6", A.m_D[2]);
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register_subalias("7", A.m_Q[2]);
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register_subalias("11", A.m_D[3]);
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register_subalias("10", A.m_Q[3]);
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register_subalias("13", A.m_D[4]);
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register_subalias("12", A.m_Q[4]);
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register_subalias("14", A.m_D[5]);
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register_subalias("15", A.m_Q[5]);
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register_subalias("8", "A.GND");
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register_subalias("16", "A.VCC");
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}
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NETLIB_RESETI() {}
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NETLIB_UPDATEI() {}
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private:
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NETLIB_SUB(74174) A;
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};
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NETLIB_UPDATE(74174)
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{
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uint_fast8_t d = 0;
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for (std::size_t i=0; i<6; i++)
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{
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d |= (m_D[i]() << i);
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}
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m_clrq = m_CLRQ();
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if (!m_clrq)
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{
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for (std::size_t i=0; i<6; i++)
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{
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m_Q[i].push(0, NLTIME_FROM_NS(40));
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}
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m_data = 0;
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} else if (d != m_data)
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{
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m_data = d;
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m_CLK.activate_lh();
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}
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}
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NETLIB_DEVICE_IMPL(74174, "TTL_74174", "+CLK,+D1,+D2,+D3,+D4,+D5,+D6,+CLRQ,@VCC,@GND")
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NETLIB_DEVICE_IMPL(74174_dip,"TTL_74174_DIP", "")
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} //namespace devices
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} // namespace netlist
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