mirror of
https://github.com/holub/mame
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370 lines
14 KiB
C
370 lines
14 KiB
C
// license:BSD-3-Clause
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// copyright-holders:Sandro Ronco
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/*********************************************************************
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NCR Decision mate slot bus and module emulation
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From the NCR System Technical manual:
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"The lower part of the controller board contains the I/0 bus together with
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seven user-accessible connectors. These connectors are identified on the board
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as J1 through J7 (reading from left to right), and correspond to the seven slots
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(numbers 1 through 7) at the rear of the cabinet.
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Position J1 is reserved for the connection of any one of the memory expansion modules
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(K200, K202, K208).
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Position J7 is reserved for the connection of either the diagnostic module (K220),
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or the customer-installable 16-bit processor module (K231).
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Positions J2 through J6 are the general purpose slots for the connection of the peripheral
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adapter and other interfaces to the computer. These five positions are identical, and Figure 2.2
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defines the type of connector, while the pin assignments are shown in Figure 2.3."
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Pinout (/ indicates an inverted signal, ie, one that would have a bar over it
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on a schematic diagram)
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a c
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|-------------------------|
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|+5V 1 +5 V |
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| 2 +12 V |
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System Reset Output, act. low |RESET/ 3 RESET IN/| active low, general system RESET
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I/O Write |IOW/ 4 IOR/ | I/O read R/W lines are Processor control lines
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Memory Write |MEMW/ 5 MEMR/ | Memory read active low, Tri-State possible
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BD0-BD7: Switch by IFSEL |BD1 6 BDO | BD0 - BD7: Data-Bus lines (8 bit)
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(I/O-Read). Normal Output. | | bidirectional, active high
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|BD3 7 BD2 |
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Direction can be changed |BD5 8 BD4 | Bus-Driver to peripheral Bus (LS245)
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by DIR/ signal. | | automatic detection
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|BD7 9 BD6 |
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Ready Signal from the |READY DMA 10 ABTRI / | Address Bus Tri-State, active low signal
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mem. contr. (XACK), act. hi. | |
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End of Process-EOP signals that|EOP/ 11 | cf. 8234A-6 spec.
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DMA service has been completed | |
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|INTACK/ 12 IFSEL 4/ |
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Change peripheral from board |AUTO/ 13 DIR/ | Direction of the databus driver. Low signal
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type 1 to 2.NC on type 1 | | change to input.
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Test Hold. External request |THOLD/ 14 HLDA | Hold Acknowledge. A response from the Z80
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to set the Z80 in hold state. | | The Z80 CPU is in hold state, active high.
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Processor-Clock: inverse signal|PCLK/ 15 CLK1 | Clock Output 1 MHz
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of the CPU clock, freq. 4MHz | |
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Logic Ground |LGRD 16 TRAMD/ | Test RAM-Disable. For ext. ROM or RAM expansion.
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| | Switching with the System RAM, RAM output disabled. act. low
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|BA19 17 BA18 | BA0-BA19: Buffered 20bit Address Bus
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|BA17 18 BA16 |
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|BA15 19 BA14 | Range to 1MB Normal output, active high
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|BA13 20 BA12 |
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|BA11 21 BA10 | Tri-State possible with ABTRI/ signal
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|BA9 22 BA8 |
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|BA7 23 BA6 |
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|BA5 24 BA4 |
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|BA3 25 BA2 |
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|BA1 26 BAO |
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IFSEL 0-4, active low |IFSEL3/ 27 IFSEL2/ | The select of the I/O pprts in the peripherals is made
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The interface does not need | | by any IFSEL and BA3 (BA3/). (10 peripherals). Automatic
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own address decoder |IFSEL1/ 28 IFSELO/ | change of the data bus direction. This change is not possible
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| | while a dma function is performed
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DRQ0-DRQ1: DMA Request for |DRQ1 29 DRQ0 | Asynchr. channel requests are used by peripherals
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resp. channels, act. high | | to request DMA service
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DACK0-DACK1: |DACK1 / 30 DACK0/ | DMA-Acknowledge Channels 0 and 1, active low
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| | These lines indicate an active DMA channel
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|WAIT/ 31 INT/ |
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Logic Ground |LGRD 32 LGRD | Logic Ground
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|-------------------------|
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Two additional plug/socket connections are possible on the bus. These are made on the solder side of the controller board
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and are designated J2A and J7 A. These connectors are not considered to be user accessible , rather for factory use ,
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or for use by field engineers and system integrators. Normally, these two connectors are used for:
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??? J2A - The connection of the fixed disk interface board, or a custom design board.
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??? J7A - The connection of the 16-bit processor board (factory option and kit K230).
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The processor and diagnostics module for Slots J7 and J7A have the following additional signals in addition to the ones present on Slots J2-J6.
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Note that the middle row of the connector (row "b") carries some signals too:
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A2 - OPT 2
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Signals A19-A26 and C19-C26 are called e.g. A7 instead of BA7 in the processor module schematic (fig. 2.14, page 2.21 System Technical Manual Hardware)
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Signals A6-A9 and C6-D9 are called e.g. D4 instead of BD4 in the processor module schematic
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B10 - READYP
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B11 - HOLD
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B12 - SWITCH 16/
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B13 - HLDA 16
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B14 - 16 BITAV
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B15 - STDMARQ
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B16 - LGRD
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B17 - 16 BITSET/
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B20 - MEMRQ/
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B32 - LGRD
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The memory modules on J1 share the same physical connector with the other expansion modules, but carry different signals:
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A1 - +5V C1 - +5V
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A2 C2
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A3 - AOUT7 C3
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A4 - AOUT6 C4 - AOUT5
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A5 - AOUT4 C5 - AOUT3
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A6 C6
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A7 C7
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A8 C8
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A9 C9
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A10 C10 - AOUT2
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A11 C11 - AOUT1
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A12 - OD0 C12 - AOUT0
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A13 - OD1 C13 - OD2
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A14 - OD3 C14
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A15 C15
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A16 - LGRD C16 - LGRD
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A17 C17
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A18 C18
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A19 - ID0 C19
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A20 - ID1 C20
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A21 - ID2 C21
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A22 - ID3 C22
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A23 - ID4 C23 - CAS7/
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A24 - ID5 C24 - CAS6/
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A25 - ID6 C25 - CAS5/
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A26 - ID7 C26 - CAS4/
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A27 - CAS2/ C27 - CAS1/
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A28 - CAS3/ C28
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A29 - OD4 C29 - OD5
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A30 - RAS/ C30 - WE/
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A31 - OD6 C31 - OD7
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A32 - LGRD C32 - LGRD
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***************************************************************************/
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#include "emu.h"
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#include "dmvbus.h"
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/***************************************************************************
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PARAMETERS
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***************************************************************************/
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//**************************************************************************
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// GLOBAL VARIABLES
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//**************************************************************************
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const device_type DMVCART_SLOT = &device_creator<dmvcart_slot_device>;
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//**************************************************************************
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// DMV cartridge interface
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//**************************************************************************
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//-------------------------------------------------
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// device_dmvslot_interface - constructor
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//-------------------------------------------------
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device_dmvslot_interface::device_dmvslot_interface(const machine_config &mconfig, device_t &device)
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: device_slot_card_interface(mconfig, device)
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{
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}
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//-------------------------------------------------
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// ~device_dmvslot_interface - destructor
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//-------------------------------------------------
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device_dmvslot_interface::~device_dmvslot_interface()
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{
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}
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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//-------------------------------------------------
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// dmvcart_slot_device - constructor
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//-------------------------------------------------
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dmvcart_slot_device::dmvcart_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, DMVCART_SLOT, "Decision Mate V cartridge slot", tag, owner, clock, "dmvcart_slot", __FILE__),
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device_slot_interface(mconfig, *this),
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m_prog_read_cb(*this),
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m_prog_write_cb(*this),
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m_out_int_cb(*this),
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m_out_irq_cb(*this),
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m_out_thold_cb(*this)
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{
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}
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//-------------------------------------------------
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// dmvcart_slot_device - destructor
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//-------------------------------------------------
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dmvcart_slot_device::~dmvcart_slot_device()
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void dmvcart_slot_device::device_start()
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{
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m_cart = dynamic_cast<device_dmvslot_interface *>(get_card_device());
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// resolve callbacks
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m_prog_read_cb.resolve_safe(0);
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m_prog_write_cb.resolve_safe();
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m_out_int_cb.resolve_safe();
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m_out_irq_cb.resolve_safe();
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m_out_thold_cb.resolve_safe();
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}
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/*-------------------------------------------------
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read
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-------------------------------------------------*/
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bool dmvcart_slot_device::read(offs_t offset, UINT8 &data)
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{
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if (m_cart)
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return m_cart->read(offset, data);
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return false;
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}
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/*-------------------------------------------------
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write
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-------------------------------------------------*/
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bool dmvcart_slot_device::write(offs_t offset, UINT8 data)
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{
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if (m_cart)
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return m_cart->write(offset, data);
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return false;
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}
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/*-------------------------------------------------
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read
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-------------------------------------------------*/
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void dmvcart_slot_device::ram_read(UINT8 cas, offs_t offset, UINT8 &data)
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{
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if (m_cart)
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m_cart->ram_read(cas, offset, data);
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}
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/*-------------------------------------------------
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write
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-------------------------------------------------*/
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void dmvcart_slot_device::ram_write(UINT8 cas, offs_t offset, UINT8 data)
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{
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if (m_cart)
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return m_cart->ram_write(cas, offset, data);
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}
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/*-------------------------------------------------
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IO read
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-------------------------------------------------*/
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void dmvcart_slot_device::io_read(address_space &space, int ifsel, offs_t offset, UINT8 &data)
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{
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if (m_cart)
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m_cart->io_read(space, ifsel, offset, data);
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}
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/*-------------------------------------------------
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IO write
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-------------------------------------------------*/
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void dmvcart_slot_device::io_write(address_space &space, int ifsel, offs_t offset, UINT8 data)
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{
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if (m_cart)
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m_cart->io_write(space, ifsel, offset, data);
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}
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/*-------------------------------------------------
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av16bit
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-------------------------------------------------*/
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bool dmvcart_slot_device::av16bit()
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{
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if (m_cart)
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return m_cart->av16bit();
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return false;
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}
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/*-------------------------------------------------
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hold_w
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-------------------------------------------------*/
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void dmvcart_slot_device::hold_w(int state)
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{
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if (m_cart)
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m_cart->hold_w(state);
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}
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void dmvcart_slot_device::switch16_w(int state)
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{
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if (m_cart)
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m_cart->switch16_w(state);
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}
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void dmvcart_slot_device::irq0_w(int state)
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{
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if (m_cart)
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m_cart->irq0_w(state);
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}
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void dmvcart_slot_device::irq1_w(int state)
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{
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if (m_cart)
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m_cart->irq1_w(state);
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}
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void dmvcart_slot_device::irq2_w(int state)
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{
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if (m_cart)
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m_cart->irq2_w(state);
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}
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void dmvcart_slot_device::irq3_w(int state)
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{
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if (m_cart)
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m_cart->irq3_w(state);
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}
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void dmvcart_slot_device::irq4_w(int state)
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{
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if (m_cart)
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m_cart->irq4_w(state);
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}
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void dmvcart_slot_device::irq5_w(int state)
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{
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if (m_cart)
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m_cart->irq5_w(state);
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}
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void dmvcart_slot_device::irq6_w(int state)
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{
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if (m_cart)
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m_cart->irq6_w(state);
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}
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void dmvcart_slot_device::irq7_w(int state)
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{
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if (m_cart)
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m_cart->irq7_w(state);
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}
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