mirror of
https://github.com/holub/mame
synced 2025-05-29 17:13:05 +03:00
332 lines
8.0 KiB
C
332 lines
8.0 KiB
C
/***************************************************************************
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Intel 82439TX System Controller (MTXC)
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***************************************************************************/
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#include "emu.h"
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#include "i82439tx.h"
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/***************************************************************************
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IMPLEMENTATION
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***************************************************************************/
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const device_type I82439TX = &device_creator<i82439tx_device>;
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i82439tx_device::i82439tx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: northbridge_device(mconfig, I82439TX, "Intel 82439TX", tag, owner, clock),
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pci_device_interface( mconfig, *this )
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{
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}
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void i82439tx_device::i82439tx_configure_memory(UINT8 val, offs_t begin, offs_t end)
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{
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switch (val & 0x03)
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{
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case 0:
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m_space->install_rom(begin, end, m_rom + (begin - 0xc0000));
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m_space->nop_write(begin, end);
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break;
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case 1:
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m_space->install_rom(begin, end, m_bios_ram + (begin - 0xc0000) / 4);
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m_space->nop_write(begin, end);
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break;
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case 2:
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m_space->install_rom(begin, end, m_rom + (begin - 0xc0000));
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m_space->install_writeonly(begin, end, m_bios_ram + (begin - 0xc0000) / 4);
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break;
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case 3:
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m_space->install_ram(begin, end, m_bios_ram + (begin - 0xc0000) / 4);
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break;
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}
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}
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/***************************************************************************
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PCI INTERFACE
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***************************************************************************/
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UINT32 i82439tx_device::pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask)
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{
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UINT32 result = 0;
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if (function != 0)
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return 0;
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switch(offset)
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{
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case 0x00: /* vendor/device ID */
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result = 0x71008086;
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break;
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case 0x08: /* revision identification register and class code register*/
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result = 0x06000001;
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break;
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case 0x04: /* PCI command register */
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case 0x0C:
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case 0x10: /* reserved */
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case 0x14: /* reserved */
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case 0x18: /* reserved */
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case 0x1C: /* reserved */
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case 0x20: /* reserved */
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case 0x24: /* reserved */
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case 0x28: /* reserved */
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case 0x2C: /* reserved */
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case 0x30: /* reserved */
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case 0x34: /* reserved */
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case 0x38: /* reserved */
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case 0x3C: /* reserved */
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case 0x40: /* reserved */
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case 0x44: /* reserved */
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case 0x48: /* reserved */
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case 0x4C: /* reserved */
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case 0x50:
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case 0x54:
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case 0x58:
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case 0x5C:
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case 0x60:
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case 0x64:
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case 0x68:
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case 0x6C:
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case 0x70:
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case 0x74:
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case 0x78:
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case 0x7C:
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case 0x80:
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case 0x84:
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case 0x88:
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case 0x8C:
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case 0x90:
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case 0x94:
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case 0x98:
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case 0x9C:
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case 0xA0:
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case 0xA4:
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case 0xA8:
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case 0xAC:
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case 0xB0:
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case 0xB4:
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case 0xB8:
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case 0xBC:
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case 0xC0:
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case 0xC4:
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case 0xC8:
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case 0xCC:
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case 0xD0:
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case 0xD4:
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case 0xD8:
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case 0xDC:
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case 0xE0:
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case 0xE4:
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case 0xE8:
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case 0xEC:
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case 0xF0:
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case 0xF4:
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case 0xF8:
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case 0xFC:
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result = m_regs[(offset - 0x50) / 4];
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break;
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default:
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fatalerror("i82439tx_pci_read(): Unexpected PCI read 0x%02X\n", offset);
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break;
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}
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return result;
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}
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void i82439tx_device::pci_write(pci_bus_device *pcibus, int function, int offset, UINT32 data, UINT32 mem_mask)
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{
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if (function != 0)
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return;
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switch(offset)
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{
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case 0x00: /* vendor/device ID */
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case 0x10: /* reserved */
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case 0x14: /* reserved */
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case 0x18: /* reserved */
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case 0x1C: /* reserved */
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case 0x20: /* reserved */
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case 0x24: /* reserved */
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case 0x28: /* reserved */
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case 0x2C: /* reserved */
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case 0x30: /* reserved */
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case 0x3C: /* reserved */
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case 0x40: /* reserved */
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case 0x44: /* reserved */
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case 0x48: /* reserved */
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case 0x4C: /* reserved */
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/* read only */
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break;
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case 0x04: /* PCI command register */
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case 0x0C:
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case 0x50:
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case 0x54:
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case 0x58:
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case 0x5C:
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case 0x60:
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case 0x64:
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case 0x68:
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case 0x6C:
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case 0x70:
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case 0x74:
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case 0x78:
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case 0x7C:
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case 0x80:
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case 0x84:
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case 0x88:
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case 0x8C:
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case 0x90:
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case 0x94:
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case 0x98:
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case 0x9C:
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case 0xA0:
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case 0xA4:
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case 0xA8:
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case 0xAC:
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case 0xB0:
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case 0xB4:
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case 0xB8:
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case 0xBC:
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case 0xC0:
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case 0xC4:
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case 0xC8:
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case 0xCC:
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case 0xD0:
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case 0xD4:
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case 0xD8:
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case 0xDC:
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case 0xE0:
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case 0xE4:
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case 0xE8:
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case 0xEC:
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case 0xF0:
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case 0xF4:
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case 0xF8:
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case 0xFC:
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switch(offset)
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{
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case 0x58:
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if ((mem_mask & 0x0000f000))
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i82439tx_configure_memory(data >> 12, 0xf0000, 0xfffff);
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if ((mem_mask & 0x000f0000))
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i82439tx_configure_memory(data >> 16, 0xc0000, 0xc3fff);
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if ((mem_mask & 0x00f00000))
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i82439tx_configure_memory(data >> 20, 0xc4000, 0xc7fff);
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if ((mem_mask & 0x0f000000))
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i82439tx_configure_memory(data >> 24, 0xc8000, 0xccfff);
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if ((mem_mask & 0xf0000000))
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i82439tx_configure_memory(data >> 28, 0xcc000, 0xcffff);
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break;
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case 0x5C:
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if ((mem_mask & 0x0000000f))
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i82439tx_configure_memory(data >> 0, 0xd0000, 0xd3fff);
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if ((mem_mask & 0x000000f0))
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i82439tx_configure_memory(data >> 4, 0xd4000, 0xd7fff);
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if ((mem_mask & 0x00000f00))
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i82439tx_configure_memory(data >> 8, 0xd8000, 0xdbfff);
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if ((mem_mask & 0x0000f000))
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i82439tx_configure_memory(data >> 12, 0xdc000, 0xdffff);
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if ((mem_mask & 0x000f0000))
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i82439tx_configure_memory(data >> 16, 0xe0000, 0xe3fff);
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if ((mem_mask & 0x00f00000))
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i82439tx_configure_memory(data >> 20, 0xe4000, 0xe7fff);
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if ((mem_mask & 0x0f000000))
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i82439tx_configure_memory(data >> 24, 0xe8000, 0xecfff);
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if ((mem_mask & 0xf0000000))
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i82439tx_configure_memory(data >> 28, 0xec000, 0xeffff);
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break;
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}
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COMBINE_DATA(&m_regs[(offset - 0x50) / 4]);
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break;
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default:
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fatalerror("i82439tx_pci_write(): Unexpected PCI write 0x%02X <-- 0x%08X\n", offset, data);
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break;
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}
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}
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//-------------------------------------------------
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// device_config_complete - perform any
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// operations now that the configuration is
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// complete
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//-------------------------------------------------
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void i82439tx_device::device_config_complete()
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{
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// inherit a copy of the static data
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const i82439tx_interface *intf = reinterpret_cast<const i82439tx_interface *>(static_config());
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if (intf != NULL)
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{
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*static_cast<i82439tx_interface *>(this) = *intf;
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}
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// or initialize to defaults if none provided
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else
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{
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memset(&m_cputag, 0, sizeof(m_cputag));
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memset(&m_rom_region, 0, sizeof(m_rom_region));
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}
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m_shortname = "i82439tx";
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void i82439tx_device::device_start()
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{
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northbridge_device::device_start();
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/* get address space we are working on */
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device_t *cpu = machine().device(m_cputag);
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assert(cpu != NULL);
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m_space = cpu->memory().space(AS_PROGRAM);
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/* get rom region */
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m_rom = machine().root_device().memregion(m_rom_region)->base();
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/* setup save states */
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save_item(NAME(m_regs));
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save_item(NAME(m_bios_ram));
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void i82439tx_device::device_reset()
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{
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northbridge_device::device_reset();
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/* setup initial values */
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m_regs[0x00] = 0x14020000;
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m_regs[0x01] = 0x01520000;
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m_regs[0x02] = 0x00000000;
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m_regs[0x03] = 0x00000000;
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m_regs[0x04] = 0x02020202;
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m_regs[0x05] = 0x00000002;
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m_regs[0x06] = 0x00000000;
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m_regs[0x07] = 0x00000000;
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/* configure initial memory state */
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i82439tx_configure_memory(0, 0xf0000, 0xfffff);
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i82439tx_configure_memory(0, 0xc0000, 0xc3fff);
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i82439tx_configure_memory(0, 0xc4000, 0xc7fff);
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i82439tx_configure_memory(0, 0xc8000, 0xccfff);
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i82439tx_configure_memory(0, 0xcc000, 0xcffff);
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i82439tx_configure_memory(0, 0xd0000, 0xd3fff);
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i82439tx_configure_memory(0, 0xd4000, 0xd7fff);
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i82439tx_configure_memory(0, 0xd8000, 0xdbfff);
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i82439tx_configure_memory(0, 0xdc000, 0xdffff);
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i82439tx_configure_memory(0, 0xe0000, 0xe3fff);
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i82439tx_configure_memory(0, 0xe4000, 0xe7fff);
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i82439tx_configure_memory(0, 0xe8000, 0xecfff);
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i82439tx_configure_memory(0, 0xec000, 0xeffff);
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}
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