mirror of
https://github.com/holub/mame
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919913f118
existing modern devices and the legacy wrappers to work in this environment. This in general greatly simplifies writing a modern device. [Aaron Giles] General notes: * some more cleanup probably needs to happen behind this change, but I needed to get it in before the next device modernization or import from MESS :) * new template function device_creator which automatically defines the static function that creates the device; use this instead of creating a static_alloc_device_config function * added device_stop() method which is called at around the time the previous device_t's destructor was called; if you auto_free anything, do it here because the machine is gone when the destructor is called * changed the static_set_* calls to pass a device_t & instead of a device_config * * for many devices, the static config structure member names over- lapped the device's names for devcb_* functions; in these cases the members in the interface were renamed to have a _cb suffix * changed the driver_enumerator to only cache 100 machine_configs because caching them all took a ton of memory; fortunately this implementation detail is completely hidden behind the driver_enumerator interface * got rid of the macros for creating derived classes; doing it manually is now clean enough that it isn't worth hiding the details in a macro
671 lines
20 KiB
C
671 lines
20 KiB
C
/*****************************************************************************
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*
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* scmp.c
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*
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* National Semiconductor SC/MP CPU Disassembly
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*
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* Initial version by Miodrag Milanovic
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*
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*****************************************************************************/
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#include "emu.h"
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#include "debugger.h"
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#include "scmp.h"
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#define VERBOSE 0
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#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
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/***************************************************************************
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TYPE DEFINITIONS
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***************************************************************************/
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typedef struct _scmp_state scmp_state;
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struct _scmp_state
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{
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scmp_config config;
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PAIR PC;
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PAIR P1;
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PAIR P2;
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PAIR P3;
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UINT8 AC;
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UINT8 ER;
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UINT8 SR;
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legacy_cpu_device *device;
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address_space *program;
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direct_read_data *direct;
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address_space *io;
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int icount;
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devcb_resolved_write8 flag_out_func;
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devcb_resolved_write_line sout_func;
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devcb_resolved_read_line sin_func;
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devcb_resolved_read_line sensea_func;
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devcb_resolved_read_line senseb_func;
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devcb_resolved_write_line halt_func;
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};
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/***************************************************************************
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MACROS
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***************************************************************************/
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/***************************************************************************
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INLINE FUNCTIONS
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***************************************************************************/
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INLINE scmp_state *get_safe_token(device_t *device)
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{
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assert(device != NULL);
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assert(device->type() == SCMP || device->type() == INS8060);
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return (scmp_state *)downcast<legacy_cpu_device *>(device)->token();
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}
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INLINE UINT16 ADD12(UINT16 addr, INT8 val)
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{
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return ((addr + val) & 0x0fff) | (addr & 0xf000);
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}
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INLINE UINT8 ROP(scmp_state *cpustate)
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{
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UINT16 pc = cpustate->PC.w.l;
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cpustate->PC.w.l = ADD12(cpustate->PC.w.l,1);
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return cpustate->direct->read_decrypted_byte( pc);
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}
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INLINE UINT8 ARG(scmp_state *cpustate)
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{
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UINT16 pc = cpustate->PC.w.l;
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cpustate->PC.w.l = ADD12(cpustate->PC.w.l,1);
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return cpustate->direct->read_raw_byte(pc);
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}
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INLINE UINT8 RM(scmp_state *cpustate,UINT32 a)
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{
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return cpustate->program->read_byte(a);
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}
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INLINE void WM(scmp_state *cpustate,UINT32 a, UINT8 v)
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{
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cpustate->program->write_byte(a, v);
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}
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INLINE void illegal(scmp_state *cpustate,UINT8 opcode)
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{
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#if VERBOSE
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UINT16 pc = cpustate->PC.w.l;
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LOG(("SC/MP illegal instruction %04X $%02X\n", pc-1, opcode));
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#endif
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}
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INLINE PAIR *GET_PTR_REG(scmp_state *cpustate, int num)
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{
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switch(num) {
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case 1: return &cpustate->P1;
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case 2: return &cpustate->P2;
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case 3: return &cpustate->P3;
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default :
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return &cpustate->PC;
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}
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}
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INLINE void BIN_ADD(scmp_state *cpustate, UINT8 val)
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{
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UINT16 tmp = cpustate->AC + val + ((cpustate->SR >> 7) & 1);
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UINT8 ov = (((cpustate->AC & 0x80)==(val & 0x80)) && ((cpustate->AC & 0x80)!=(tmp & 0x80))) ? 0x40 : 0x00;
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cpustate->AC = tmp & 0xff;
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cpustate->SR &= 0x3f; // clear CY/L and OV flag
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cpustate->SR |= (tmp & 0x100) ? 0x80 : 0x00; // set CY/L
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cpustate->SR |= ov;
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}
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INLINE void DEC_ADD(scmp_state *cpustate, UINT8 val)
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{
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UINT16 tmp = cpustate->AC + val + ((cpustate->SR >> 7) & 1);
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if ((tmp & 0x0f) > 9) tmp +=6;
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cpustate->AC = tmp % 0xa0;
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cpustate->SR &= 0x7f; // clear CY/L flag
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cpustate->SR |= (tmp > 0x99) ? 0x80 : 0x00;
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}
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INLINE UINT16 GET_ADDR(scmp_state *cpustate, UINT8 code)
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{
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UINT16 addr = 0;
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INT8 offset = 0;
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UINT16 retVal = 0;
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UINT16 ptr = GET_PTR_REG(cpustate,code & 0x03)->w.l;
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UINT8 arg = ARG(cpustate);
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if (arg == 0x80) {
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offset = cpustate->ER;
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} else {
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if (arg & 0x80) {
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offset = (INT8)arg;
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} else {
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offset = arg;
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}
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}
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addr = ADD12(ptr,offset);
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if (code & 0x04) {
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if (code & 0x03) {
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// Auto-indexed
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if (offset < 0) {
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// pre decrement
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GET_PTR_REG(cpustate,code & 0x03)->w.l = addr;
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retVal = addr;
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} else {
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// post increment
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retVal = ptr;
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GET_PTR_REG(cpustate,code & 0x03)->w.l = addr;
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}
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} else {
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// Immediate
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}
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} else {
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// Indexed
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retVal = addr;
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}
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return retVal;
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}
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static void execute_one(scmp_state *cpustate, int opcode)
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{
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UINT8 tmp;
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UINT8 ptr = opcode & 3;
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if (BIT(opcode,7)) {
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// two bytes instructions
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switch (opcode)
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{
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// Memory Reference Instructions
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case 0xc0 : case 0xc1 : case 0xc2 : case 0xc3 :
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case 0xc5 : case 0xc6 : case 0xc7 :
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//LD
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cpustate->icount -= 18;
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cpustate->AC = RM(cpustate,GET_ADDR(cpustate,opcode));
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break;
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case 0xc8 : case 0xc9 : case 0xca : case 0xcb :
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case 0xcd : case 0xce : case 0xcf :
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// ST
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cpustate->icount -= 18;
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WM(cpustate,GET_ADDR(cpustate,opcode),cpustate->AC);
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break;
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case 0xd0 : case 0xd1 : case 0xd2 : case 0xd3 :
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case 0xd5 : case 0xd6 : case 0xd7 :
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// AND
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cpustate->icount -= 18;
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cpustate->AC &= RM(cpustate,GET_ADDR(cpustate,opcode));
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break;
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case 0xd8 : case 0xd9 : case 0xda : case 0xdb :
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case 0xdd : case 0xde : case 0xdf :
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//OR
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cpustate->icount -= 18;
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cpustate->AC |= RM(cpustate,GET_ADDR(cpustate,opcode));
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break;
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case 0xe0 : case 0xe1 : case 0xe2 : case 0xe3 :
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case 0xe5 : case 0xe6 : case 0xe7 :
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// XOR
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cpustate->icount -= 18;
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cpustate->AC ^= RM(cpustate,GET_ADDR(cpustate,opcode));
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break;
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case 0xe8 : case 0xe9 : case 0xea : case 0xeb :
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case 0xed : case 0xee : case 0xef :
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// DAD
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cpustate->icount -= 23;
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DEC_ADD(cpustate,RM(cpustate,GET_ADDR(cpustate,opcode)));
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break;
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case 0xf0 : case 0xf1 : case 0xf2 : case 0xf3 :
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case 0xf5 : case 0xf6 : case 0xf7 :
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// ADD
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cpustate->icount -= 19;
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BIN_ADD(cpustate,RM(cpustate,GET_ADDR(cpustate,opcode)));
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break;
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case 0xf8 : case 0xf9 : case 0xfa : case 0xfb :
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case 0xfd : case 0xfe : case 0xff :
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// CAD
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cpustate->icount -= 20;
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BIN_ADD(cpustate,~RM(cpustate,GET_ADDR(cpustate,opcode)));
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break;
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// Memory Increment/Decrement Instructions
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case 0xa8 : case 0xa9 : case 0xaa : case 0xab :
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// IDL
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{
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UINT16 addr = GET_ADDR(cpustate,opcode);
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cpustate->icount -= 22;
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cpustate->AC = RM(cpustate,addr) + 1;
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WM(cpustate,addr,cpustate->AC);
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}
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break;
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case 0xb8 : case 0xb9 : case 0xba : case 0xbb :
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// DLD
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{
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UINT16 addr = GET_ADDR(cpustate,opcode);
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cpustate->icount -= 22;
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cpustate->AC = RM(cpustate,addr) - 1;
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WM(cpustate,addr,cpustate->AC);
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}
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break;
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// Immediate Instructions
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case 0xc4 : // LDI
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cpustate->icount -= 10;
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cpustate->AC = ARG(cpustate);
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break;
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case 0xd4 : // ANI
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cpustate->icount -= 10;
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cpustate->AC &= ARG(cpustate);
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break;
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case 0xdc : // ORI
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cpustate->icount -= 10;
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cpustate->AC |= ARG(cpustate);
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break;
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case 0xe4 : // XRI
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cpustate->icount -= 10;
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cpustate->AC ^= ARG(cpustate);
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break;
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case 0xec : // DAI
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cpustate->icount -= 15;
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DEC_ADD(cpustate,ARG(cpustate));
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break;
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case 0xf4 : // ADI
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cpustate->icount -= 11;
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BIN_ADD(cpustate,ARG(cpustate));
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break;
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case 0xfc : // CAI
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cpustate->icount -= 12;
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BIN_ADD(cpustate,~ARG(cpustate));
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break;
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// Transfer Instructions
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case 0x90 : case 0x91 : case 0x92 : case 0x93 :// JMP
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cpustate->icount -= 11;
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cpustate->PC.w.l = ADD12(GET_PTR_REG(cpustate,ptr)->w.l,(INT8)ARG(cpustate));
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break;
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case 0x94 : case 0x95 : case 0x96 : case 0x97 :
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// JP
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cpustate->icount -= 9;
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tmp = ARG(cpustate);
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if (!(cpustate->AC & 0x80)) {
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cpustate->PC.w.l = ADD12(GET_PTR_REG(cpustate,ptr)->w.l,(INT8)tmp);
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cpustate->icount -= 2;
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}
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break;
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case 0x98 : case 0x99 : case 0x9a : case 0x9b :
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// JZ
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cpustate->icount -= 9;
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tmp = ARG(cpustate);
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if (!cpustate->AC) {
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cpustate->PC.w.l = ADD12(GET_PTR_REG(cpustate,ptr)->w.l,(INT8)tmp);
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cpustate->icount -= 2;
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}
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break;
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case 0x9c : case 0x9d : case 0x9e : case 0x9f :
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// JNZ
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cpustate->icount -= 9;
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tmp = ARG(cpustate);
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if (cpustate->AC) {
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cpustate->PC.w.l = ADD12(GET_PTR_REG(cpustate,ptr)->w.l,(INT8)tmp);
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cpustate->icount -= 2;
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}
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break;
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// Double-Byte Miscellaneous Instructions
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case 0x8f: // DLY
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tmp = ARG(cpustate);
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cpustate->icount -= 13 + (cpustate->AC * 2) + (((UINT32)tmp) << 1) + (((UINT32)tmp) << 9);
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cpustate->AC = 0xff;
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break;
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// Others are illegal
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default : cpustate->icount -= 1;
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illegal (cpustate,opcode);
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break;
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}
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} else {
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// one byte instructions
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switch (opcode)
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{
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// Extension Register Instructions
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case 0x40: // LDE
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cpustate->icount -= 6;
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cpustate->AC = cpustate->ER;
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break;
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case 0x01: // XAE
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cpustate->icount -= 7;
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tmp = cpustate->AC;
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cpustate->AC = cpustate->ER;
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cpustate->ER = tmp;
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break;
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case 0x50: // ANE
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cpustate->icount -= 6;
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cpustate->AC &= cpustate->ER;
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break;
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case 0x58: // ORE
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cpustate->icount -= 6;
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cpustate->AC |= cpustate->ER;
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break;
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case 0x60: // XRE
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cpustate->icount -= 6;
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cpustate->AC ^= cpustate->ER;
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break;
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case 0x68: // DAE
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cpustate->icount -= 11;
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DEC_ADD(cpustate,cpustate->ER);
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break;
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case 0x70: // ADE
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cpustate->icount -= 7;
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BIN_ADD(cpustate,cpustate->ER);
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break;
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case 0x78: // CAE
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cpustate->icount -= 8;
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BIN_ADD(cpustate,~cpustate->ER);
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break;
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// Pointer Register Move Instructions
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case 0x30: case 0x31: case 0x32: case 0x33: // XPAL
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cpustate->icount -= 8;
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tmp = cpustate->AC;
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cpustate->AC = GET_PTR_REG(cpustate,ptr)->b.l;
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GET_PTR_REG(cpustate,ptr)->b.l = tmp;
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break;
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case 0x34: case 0x35 :case 0x36: case 0x37:
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// XPAH
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cpustate->icount -= 8;
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tmp = cpustate->AC;
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cpustate->AC = GET_PTR_REG(cpustate,ptr)->b.h;
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GET_PTR_REG(cpustate,ptr)->b.h = tmp;
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break;
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case 0x3c: case 0x3d :case 0x3e: case 0x3f:
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// XPPC
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{
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UINT16 tmp = ADD12(cpustate->PC.w.l,-1); // Since PC is incremented we need to fix it
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cpustate->icount -= 7;
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cpustate->PC.w.l = GET_PTR_REG(cpustate,ptr)->w.l;
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GET_PTR_REG(cpustate,ptr)->w.l = tmp;
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// After exchange CPU increment PC
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cpustate->PC.w.l = ADD12(cpustate->PC.w.l,1);
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}
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break;
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// Shift, Rotate, Serial I/O Instructions
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case 0x19: // SIO
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cpustate->icount -= 5;
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devcb_call_write_line(&cpustate->sout_func, cpustate->ER & 0x01);
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cpustate->ER >>= 1;
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cpustate->ER |= devcb_call_read_line(&cpustate->sin_func) ? 0x80 : 0x00;
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break;
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case 0x1c: // SR
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cpustate->icount -= 5;
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cpustate->AC >>= 1;
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break;
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case 0x1d: // SRL
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cpustate->icount -= 5;
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cpustate->AC >>= 1;
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cpustate->AC |= cpustate->SR & 0x80; // add C/L flag
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break;
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case 0x1e: // RR
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cpustate->icount -= 5;
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cpustate->AC = (cpustate->AC >> 1) | ((cpustate->AC & 0x01) << 7);
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break;
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case 0x1f: // RRL
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cpustate->icount -= 5;
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tmp = (cpustate->AC & 0x01) << 7;
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cpustate->AC = (cpustate->AC >> 1) | (cpustate->SR & 0x80);
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cpustate->SR = (cpustate->SR & 0x7f) | tmp;
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break;
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// Single Byte Miscellaneous Instructions
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case 0x00: // HALT
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cpustate->icount -= 8;
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devcb_call_write_line(&cpustate->halt_func, 1);
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devcb_call_write_line(&cpustate->halt_func, 0);
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break;
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case 0x02: // CCL
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cpustate->icount -= 5;
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cpustate->SR &= 0x7f;
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break;
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case 0x03: // SCL
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cpustate->icount -= 5;
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cpustate->SR |= 0x80;
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break;
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case 0x04: // DINT
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cpustate->icount -= 6;
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cpustate->SR &= 0xf7;
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break;
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case 0x05: // IEN
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cpustate->icount -= 6;
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cpustate->SR |= 0x08;
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break;
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case 0x06: // CSA
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cpustate->icount -= 5;
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cpustate->SR &= 0xcf; // clear SA and SB flags
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cpustate->SR |= devcb_call_read_line(&cpustate->sensea_func) ? 0x10 : 0x00;
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cpustate->SR |= devcb_call_read_line(&cpustate->senseb_func) ? 0x20 : 0x00;
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cpustate->AC = cpustate->SR;
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break;
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case 0x07: // CAS
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cpustate->icount -= 6;
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cpustate->SR = cpustate->AC;
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devcb_call_write8(&cpustate->flag_out_func, 0, cpustate->SR & 0x07);
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break;
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case 0x08: // NOP
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cpustate->icount -= 5;
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break;
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// Others are illegal
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default : cpustate->icount -= 1;
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illegal (cpustate,opcode);
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break;
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}
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}
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}
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/***************************************************************************
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COMMON EXECUTION
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***************************************************************************/
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static void take_interrupt(scmp_state *cpustate)
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{
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UINT16 tmp = ADD12(cpustate->PC.w.l,-1); // We fix PC so at return it goes to current location
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cpustate->SR &= 0xf7; // clear IE flag
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cpustate->icount -= 8; // assumption
|
|
// do XPPC 3
|
|
cpustate->PC.w.l = GET_PTR_REG(cpustate,3)->w.l;
|
|
GET_PTR_REG(cpustate,3)->w.l = tmp;
|
|
// After exchange CPU increment PC
|
|
cpustate->PC.w.l = ADD12(cpustate->PC.w.l,1);
|
|
}
|
|
|
|
static CPU_EXECUTE( scmp )
|
|
{
|
|
scmp_state *cpustate = get_safe_token(device);
|
|
|
|
do
|
|
{
|
|
if ((cpustate->SR & 0x08) && (devcb_call_read_line(&cpustate->sensea_func))) {
|
|
take_interrupt(cpustate);
|
|
}
|
|
debugger_instruction_hook(device, cpustate->PC.d);
|
|
execute_one(cpustate, ROP(cpustate));
|
|
|
|
} while (cpustate->icount > 0);
|
|
}
|
|
|
|
/***************************************************************************
|
|
CORE INITIALIZATION
|
|
***************************************************************************/
|
|
|
|
static CPU_INIT( scmp )
|
|
{
|
|
scmp_state *cpustate = get_safe_token(device);
|
|
|
|
if (device->static_config() != NULL)
|
|
cpustate->config = *(scmp_config *)device->static_config();
|
|
|
|
/* set up the state table */
|
|
{
|
|
device_state_interface *state;
|
|
device->interface(state);
|
|
state->state_add(SCMP_PC, "PC", cpustate->PC.w.l);
|
|
state->state_add(STATE_GENPC, "GENPC", cpustate->PC.w.l).noshow();
|
|
state->state_add(STATE_GENFLAGS, "GENFLAGS", cpustate->SR).noshow().formatstr("%8s");
|
|
state->state_add(SCMP_P1, "P1", cpustate->P1.w.l);
|
|
state->state_add(SCMP_P2, "P2", cpustate->P2.w.l);
|
|
state->state_add(SCMP_P3, "P3", cpustate->P3.w.l);
|
|
state->state_add(SCMP_AC, "AC", cpustate->AC);
|
|
state->state_add(SCMP_ER, "ER", cpustate->ER);
|
|
state->state_add(SCMP_SR, "SR", cpustate->SR);
|
|
}
|
|
|
|
cpustate->device = device;
|
|
|
|
cpustate->program = device->space(AS_PROGRAM);
|
|
cpustate->direct = &cpustate->program->direct();
|
|
|
|
/* resolve callbacks */
|
|
devcb_resolve_write8(&cpustate->flag_out_func, &cpustate->config.flag_out_func, device);
|
|
devcb_resolve_write_line(&cpustate->sout_func, &cpustate->config.sout_func, device);
|
|
devcb_resolve_read_line(&cpustate->sin_func, &cpustate->config.sin_func, device);
|
|
devcb_resolve_read_line(&cpustate->sensea_func, &cpustate->config.sensea_func, device);
|
|
devcb_resolve_read_line(&cpustate->senseb_func, &cpustate->config.senseb_func, device);
|
|
devcb_resolve_write_line(&cpustate->halt_func, &cpustate->config.halt_func, device);
|
|
|
|
device->save_item(NAME(cpustate->PC));
|
|
device->save_item(NAME(cpustate->P1));
|
|
device->save_item(NAME(cpustate->P2));
|
|
device->save_item(NAME(cpustate->P3));
|
|
device->save_item(NAME(cpustate->AC));
|
|
device->save_item(NAME(cpustate->ER));
|
|
device->save_item(NAME(cpustate->SR));
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
COMMON RESET
|
|
***************************************************************************/
|
|
|
|
static CPU_RESET( scmp )
|
|
{
|
|
scmp_state *cpustate = get_safe_token(device);
|
|
|
|
cpustate->PC.d = 0;
|
|
cpustate->P1.d = 0;
|
|
cpustate->P2.d = 0;
|
|
cpustate->P3.d = 0;
|
|
cpustate->AC = 0;
|
|
cpustate->ER = 0;
|
|
cpustate->SR = 0;
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
COMMON STATE IMPORT/EXPORT
|
|
***************************************************************************/
|
|
|
|
static CPU_IMPORT_STATE( scmp )
|
|
{
|
|
}
|
|
|
|
static CPU_EXPORT_STATE( scmp )
|
|
{
|
|
}
|
|
|
|
static CPU_EXPORT_STRING( scmp )
|
|
{
|
|
scmp_state *cpustate = get_safe_token(device);
|
|
|
|
switch (entry.index())
|
|
{
|
|
case STATE_GENFLAGS:
|
|
string.printf("%c%c%c%c%c%c%c%c",
|
|
(cpustate->SR & 0x80) ? 'C' : '.',
|
|
(cpustate->SR & 0x40) ? 'V' : '.',
|
|
(cpustate->SR & 0x20) ? 'B' : '.',
|
|
(cpustate->SR & 0x10) ? 'A' : '.',
|
|
(cpustate->SR & 0x08) ? 'I' : '.',
|
|
(cpustate->SR & 0x04) ? '2' : '.',
|
|
(cpustate->SR & 0x02) ? '1' : '.',
|
|
(cpustate->SR & 0x01) ? '0' : '.');
|
|
break;
|
|
}
|
|
}
|
|
|
|
/***************************************************************************
|
|
COMMON SET INFO
|
|
***************************************************************************/
|
|
static CPU_SET_INFO( scmp )
|
|
{
|
|
}
|
|
|
|
/***************************************************************************
|
|
SCMP GET INFO
|
|
***************************************************************************/
|
|
|
|
CPU_GET_INFO( scmp )
|
|
{
|
|
scmp_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
|
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(scmp_state); break;
|
|
case CPUINFO_INT_INPUT_LINES: info->i = 0; break;
|
|
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
|
|
case DEVINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
|
|
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
|
|
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
|
|
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
|
|
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 2; break;
|
|
case CPUINFO_INT_MIN_CYCLES: info->i = 5; break;
|
|
case CPUINFO_INT_MAX_CYCLES: info->i = 131593; break; // DLY instruction max time
|
|
|
|
case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
|
|
case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
|
|
case DEVINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
|
|
|
|
case DEVINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
|
|
case DEVINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
|
|
case DEVINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
|
|
|
|
case DEVINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
|
|
case DEVINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
|
|
case DEVINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
|
|
|
|
/* --- the following bits of info are returned as pointers to functions --- */
|
|
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(scmp); break;
|
|
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(scmp); break;
|
|
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(scmp); break;
|
|
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(scmp); break;
|
|
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(scmp); break;
|
|
case CPUINFO_FCT_IMPORT_STATE: info->import_state = CPU_IMPORT_STATE_NAME(scmp); break;
|
|
case CPUINFO_FCT_EXPORT_STATE: info->export_state = CPU_EXPORT_STATE_NAME(scmp); break;
|
|
case CPUINFO_FCT_EXPORT_STRING: info->export_string = CPU_EXPORT_STRING_NAME(scmp); break;
|
|
|
|
/* --- the following bits of info are returned as pointers --- */
|
|
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
|
|
|
|
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
|
case DEVINFO_STR_NAME: strcpy(info->s, "INS 8050 SC/MP"); break;
|
|
case DEVINFO_STR_FAMILY: strcpy(info->s, "National Semiconductor SC/MP"); break;
|
|
case DEVINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
|
|
case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
|
|
case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Miodrag Milanovic"); break;
|
|
}
|
|
}
|
|
|
|
/**************************************************************************
|
|
* CPU-specific set_info
|
|
**************************************************************************/
|
|
CPU_GET_INFO( ins8060 )
|
|
{
|
|
switch (state)
|
|
{
|
|
/* --- the following bits of info are returned as pointers to data or functions --- */
|
|
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 2; break;
|
|
|
|
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
|
case DEVINFO_STR_NAME: strcpy(info->s, "INS 8060 SC/MP II"); break;
|
|
|
|
default: CPU_GET_INFO_CALL(scmp); break;
|
|
}
|
|
}
|
|
|
|
DEFINE_LEGACY_CPU_DEVICE(SCMP, scmp);
|
|
DEFINE_LEGACY_CPU_DEVICE(INS8060, ins8060);
|