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modelling. [Couriersud] Added global NETLIST.DEFAULT_MOS_CAPMODEL parameter. Setting this to zero disables using capitance modelling in mos models. On a per mos device basis this can be achieved by adding CAPMODEL=0 to the model definition, e.g. MOSFET(X, "NMOS(CAPMODEL=0)") Improve MOSFET convergence by using log-stepping.
65 lines
1.1 KiB
C++
65 lines
1.1 KiB
C++
// license:GPL-2.0+
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// copyright-holders:Couriersud
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/*
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* cmos_inverter_clk
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*
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*/
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#include "netlist/devices/net_lib.h"
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#include "netlist/analog/nld_twoterm.h"
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#define USE_CLOCK (1)
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NETLIST_START(cmos_inverter_clk)
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/* Standard stuff */
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//SOLVER(Solver, 480000)
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SOLVER(Solver, 1e5)
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//SOLVER(Solver, 100000000000)
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PARAM(Solver.ACCURACY, 1e-7 )
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PARAM(Solver.NR_LOOPS, 500000)
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PARAM(Solver.DYNAMIC_TS, 0)
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PARAM(Solver.DYNAMIC_LTE, 1e-5)
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PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-8)
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ANALOG_INPUT(V5, 5)
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// CLOCK(clk, 0.5e6)
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#if (USE_CLOCK)
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CLOCK(V, 5000)
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PARAM(NETLIST.DEFAULT_MOS_CAPMODEL, 0) // Disable capacitance modeling
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//CLOCK(V, 500000)
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#else
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VS(V, 5)
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PARAM(V.FUNC, "T 5e6 *")
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#endif
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MOSFET(P, "PMOS(VTO=-0.5 GAMMA=0.5 TOX=20n)")
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MOSFET(M, "NMOS(VTO=0.5 GAMMA=0.5 TOX=20n)")
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RES(RG, 1)
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NET_C(P.S, V5)
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NET_C(P.D, M.D)
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#if (USE_CLOCK)
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NET_C(GND, M.S)
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NET_C(V.Q, RG.1)
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#else
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NET_C(GND, M.S, V.N)
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NET_C(V.P, RG.1)
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#endif
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NET_C(RG.2, M.G, P.G)
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// capacitance over D - S
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#if 0
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CAP(C, CAP_N(1))
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NET_C(M.D, C.1)
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NET_C(M.S, C.2)
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#endif
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#if 0
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LOG(log_G, M.G)
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LOG(log_D, M.D)
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LOGD(log_X, RG.1, RG.2)
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#endif
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NETLIST_END()
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