mirror of
https://github.com/holub/mame
synced 2025-10-06 09:00:04 +03:00
aec01e7407
Update MAME to use new function Instantiate ODR-used static constant members Make some of the UI code more localisable Remove use of retired functions in tools
567 lines
13 KiB
C++
567 lines
13 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:Miodrag Milanovic
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/*****************************************************************************
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*
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* scmp.c
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*
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* National Semiconductor SC/MP CPU Disassembly
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*
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*****************************************************************************/
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#include "emu.h"
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#include "debugger.h"
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#include "scmp.h"
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#define VERBOSE 0
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#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
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const device_type SCMP = &device_creator<scmp_device>;
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const device_type INS8060 = &device_creator<ins8060_device>;
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scmp_device::scmp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: cpu_device(mconfig, SCMP, "INS 8050 SC/MP", tag, owner, clock, "ins8050", __FILE__)
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, m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0), m_AC(0), m_ER(0), m_SR(0), m_program(nullptr), m_direct(nullptr), m_icount(0)
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, m_flag_out_func(*this)
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, m_sout_func(*this)
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, m_sin_func(*this)
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, m_sensea_func(*this)
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, m_senseb_func(*this)
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, m_halt_func(*this)
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{
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}
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scmp_device::scmp_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
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: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
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, m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0), m_AC(0), m_ER(0), m_SR(0), m_program(nullptr), m_direct(nullptr), m_icount(0)
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, m_flag_out_func(*this)
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, m_sout_func(*this)
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, m_sin_func(*this)
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, m_sensea_func(*this)
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, m_senseb_func(*this)
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, m_halt_func(*this)
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{
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}
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ins8060_device::ins8060_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: scmp_device(mconfig, INS8060, "INS 8060 SC/MP II", tag, owner, clock, "ins8060", __FILE__)
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{
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}
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offs_t scmp_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
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{
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extern CPU_DISASSEMBLE( scmp );
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return CPU_DISASSEMBLE_NAME(scmp)(this, buffer, pc, oprom, opram, options);
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}
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UINT16 scmp_device::ADD12(UINT16 addr, INT8 val)
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{
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return ((addr + val) & 0x0fff) | (addr & 0xf000);
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}
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UINT8 scmp_device::ROP()
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{
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UINT16 pc = m_PC.w.l;
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m_PC.w.l = ADD12(m_PC.w.l,1);
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return m_direct->read_byte( pc);
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}
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UINT8 scmp_device::ARG()
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{
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UINT16 pc = m_PC.w.l;
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m_PC.w.l = ADD12(m_PC.w.l,1);
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return m_direct->read_byte(pc);
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}
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UINT8 scmp_device::RM(UINT32 a)
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{
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return m_program->read_byte(a);
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}
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void scmp_device::WM(UINT32 a, UINT8 v)
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{
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m_program->write_byte(a, v);
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}
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void scmp_device::illegal(UINT8 opcode)
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{
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#if VERBOSE
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UINT16 pc = m_PC.w.l;
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LOG(("SC/MP illegal instruction %04X $%02X\n", pc-1, opcode));
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#endif
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}
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PAIR *scmp_device::GET_PTR_REG(int num)
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{
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switch(num) {
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case 1: return &m_P1;
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case 2: return &m_P2;
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case 3: return &m_P3;
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default :
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return &m_PC;
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}
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}
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void scmp_device::BIN_ADD(UINT8 val)
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{
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UINT16 tmp = m_AC + val + ((m_SR >> 7) & 1);
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UINT8 ov = (((m_AC & 0x80)==(val & 0x80)) && ((m_AC & 0x80)!=(tmp & 0x80))) ? 0x40 : 0x00;
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m_AC = tmp & 0xff;
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m_SR &= 0x3f; // clear CY/L and OV flag
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m_SR |= (tmp & 0x100) ? 0x80 : 0x00; // set CY/L
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m_SR |= ov;
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}
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void scmp_device::DEC_ADD(UINT8 val)
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{
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UINT16 tmp = m_AC + val + ((m_SR >> 7) & 1);
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if ((tmp & 0x0f) > 9) tmp +=6;
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m_AC = tmp % 0xa0;
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m_SR &= 0x7f; // clear CY/L flag
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m_SR |= (tmp > 0x99) ? 0x80 : 0x00;
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}
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UINT16 scmp_device::GET_ADDR(UINT8 code)
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{
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UINT16 addr;
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INT8 offset;
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UINT16 retVal = 0;
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UINT16 ptr = GET_PTR_REG(code & 0x03)->w.l;
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UINT8 arg = ARG();
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if (arg == 0x80) {
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offset = m_ER;
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} else {
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if (arg & 0x80) {
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offset = (INT8)arg;
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} else {
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offset = arg;
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}
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}
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addr = ADD12(ptr,offset);
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if (code & 0x04) {
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if (code & 0x03) {
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// Auto-indexed
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if (offset < 0) {
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// pre decrement
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GET_PTR_REG(code & 0x03)->w.l = addr;
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retVal = addr;
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} else {
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// post increment
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retVal = ptr;
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GET_PTR_REG(code & 0x03)->w.l = addr;
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}
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} else {
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// Immediate
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}
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} else {
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// Indexed
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retVal = addr;
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}
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return retVal;
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}
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void scmp_device::execute_one(int opcode)
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{
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UINT8 tmp;
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UINT8 ptr = opcode & 3;
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if (BIT(opcode,7)) {
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// two bytes instructions
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switch (opcode)
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{
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// Memory Reference Instructions
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case 0xc0 : case 0xc1 : case 0xc2 : case 0xc3 :
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case 0xc5 : case 0xc6 : case 0xc7 :
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//LD
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m_icount -= 18;
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m_AC = RM(GET_ADDR(opcode));
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break;
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case 0xc8 : case 0xc9 : case 0xca : case 0xcb :
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case 0xcd : case 0xce : case 0xcf :
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// ST
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m_icount -= 18;
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WM(GET_ADDR(opcode),m_AC);
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break;
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case 0xd0 : case 0xd1 : case 0xd2 : case 0xd3 :
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case 0xd5 : case 0xd6 : case 0xd7 :
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// AND
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m_icount -= 18;
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m_AC &= RM(GET_ADDR(opcode));
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break;
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case 0xd8 : case 0xd9 : case 0xda : case 0xdb :
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case 0xdd : case 0xde : case 0xdf :
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//OR
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m_icount -= 18;
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m_AC |= RM(GET_ADDR(opcode));
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break;
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case 0xe0 : case 0xe1 : case 0xe2 : case 0xe3 :
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case 0xe5 : case 0xe6 : case 0xe7 :
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// XOR
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m_icount -= 18;
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m_AC ^= RM(GET_ADDR(opcode));
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break;
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case 0xe8 : case 0xe9 : case 0xea : case 0xeb :
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case 0xed : case 0xee : case 0xef :
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// DAD
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m_icount -= 23;
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DEC_ADD(RM(GET_ADDR(opcode)));
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break;
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case 0xf0 : case 0xf1 : case 0xf2 : case 0xf3 :
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case 0xf5 : case 0xf6 : case 0xf7 :
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// ADD
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m_icount -= 19;
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BIN_ADD(RM(GET_ADDR(opcode)));
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break;
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case 0xf8 : case 0xf9 : case 0xfa : case 0xfb :
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case 0xfd : case 0xfe : case 0xff :
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// CAD
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m_icount -= 20;
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BIN_ADD(~RM(GET_ADDR(opcode)));
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break;
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// Memory Increment/Decrement Instructions
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case 0xa8 : case 0xa9 : case 0xaa : case 0xab :
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// IDL
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{
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UINT16 addr = GET_ADDR(opcode);
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m_icount -= 22;
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m_AC = RM(addr) + 1;
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WM(addr,m_AC);
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}
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break;
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case 0xb8 : case 0xb9 : case 0xba : case 0xbb :
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// DLD
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{
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UINT16 addr = GET_ADDR(opcode);
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m_icount -= 22;
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m_AC = RM(addr) - 1;
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WM(addr,m_AC);
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}
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break;
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// Immediate Instructions
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case 0xc4 : // LDI
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m_icount -= 10;
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m_AC = ARG();
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break;
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case 0xd4 : // ANI
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m_icount -= 10;
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m_AC &= ARG();
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break;
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case 0xdc : // ORI
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m_icount -= 10;
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m_AC |= ARG();
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break;
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case 0xe4 : // XRI
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m_icount -= 10;
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m_AC ^= ARG();
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break;
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case 0xec : // DAI
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m_icount -= 15;
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DEC_ADD(ARG());
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break;
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case 0xf4 : // ADI
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m_icount -= 11;
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BIN_ADD(ARG());
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break;
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case 0xfc : // CAI
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m_icount -= 12;
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BIN_ADD(~ARG());
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break;
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// Transfer Instructions
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case 0x90 : case 0x91 : case 0x92 : case 0x93 :// JMP
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m_icount -= 11;
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m_PC.w.l = ADD12(GET_PTR_REG(ptr)->w.l,(INT8)ARG());
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break;
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case 0x94 : case 0x95 : case 0x96 : case 0x97 :
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// JP
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m_icount -= 9;
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tmp = ARG();
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if (!(m_AC & 0x80)) {
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m_PC.w.l = ADD12(GET_PTR_REG(ptr)->w.l,(INT8)tmp);
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m_icount -= 2;
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}
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break;
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case 0x98 : case 0x99 : case 0x9a : case 0x9b :
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// JZ
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m_icount -= 9;
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tmp = ARG();
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if (!m_AC) {
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m_PC.w.l = ADD12(GET_PTR_REG(ptr)->w.l,(INT8)tmp);
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m_icount -= 2;
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}
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break;
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case 0x9c : case 0x9d : case 0x9e : case 0x9f :
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// JNZ
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m_icount -= 9;
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tmp = ARG();
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if (m_AC) {
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m_PC.w.l = ADD12(GET_PTR_REG(ptr)->w.l,(INT8)tmp);
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m_icount -= 2;
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}
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break;
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// Double-Byte Miscellaneous Instructions
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case 0x8f: // DLY
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tmp = ARG();
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m_icount -= 13 + (m_AC * 2) + (((UINT32)tmp) << 1) + (((UINT32)tmp) << 9);
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m_AC = 0xff;
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break;
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// Others are illegal
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default : m_icount -= 1;
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illegal (opcode);
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break;
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}
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} else {
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// one byte instructions
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switch (opcode)
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{
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// Extension Register Instructions
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case 0x40: // LDE
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m_icount -= 6;
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m_AC = m_ER;
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break;
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case 0x01: // XAE
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m_icount -= 7;
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tmp = m_AC;
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m_AC = m_ER;
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m_ER = tmp;
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break;
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case 0x50: // ANE
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m_icount -= 6;
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m_AC &= m_ER;
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break;
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case 0x58: // ORE
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m_icount -= 6;
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m_AC |= m_ER;
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break;
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case 0x60: // XRE
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m_icount -= 6;
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m_AC ^= m_ER;
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break;
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case 0x68: // DAE
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m_icount -= 11;
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DEC_ADD(m_ER);
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break;
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case 0x70: // ADE
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m_icount -= 7;
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BIN_ADD(m_ER);
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break;
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case 0x78: // CAE
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m_icount -= 8;
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BIN_ADD(~m_ER);
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break;
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// Pointer Register Move Instructions
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case 0x30: case 0x31: case 0x32: case 0x33: // XPAL
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m_icount -= 8;
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tmp = m_AC;
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m_AC = GET_PTR_REG(ptr)->b.l;
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GET_PTR_REG(ptr)->b.l = tmp;
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break;
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case 0x34: case 0x35 :case 0x36: case 0x37:
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// XPAH
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m_icount -= 8;
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tmp = m_AC;
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m_AC = GET_PTR_REG(ptr)->b.h;
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GET_PTR_REG(ptr)->b.h = tmp;
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break;
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case 0x3c: case 0x3d :case 0x3e: case 0x3f:
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// XPPC
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{
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UINT16 tmp16 = ADD12(m_PC.w.l,-1); // Since PC is incremented we need to fix it
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m_icount -= 7;
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m_PC.w.l = GET_PTR_REG(ptr)->w.l;
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GET_PTR_REG(ptr)->w.l = tmp16;
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// After exchange CPU increment PC
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m_PC.w.l = ADD12(m_PC.w.l,1);
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}
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break;
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// Shift, Rotate, Serial I/O Instructions
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case 0x19: // SIO
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m_icount -= 5;
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m_sout_func(m_ER & 0x01);
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m_ER >>= 1;
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m_ER |= m_sin_func() ? 0x80 : 0x00;
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break;
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case 0x1c: // SR
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m_icount -= 5;
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m_AC >>= 1;
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break;
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case 0x1d: // SRL
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m_icount -= 5;
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m_AC >>= 1;
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m_AC |= m_SR & 0x80; // add C/L flag
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break;
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case 0x1e: // RR
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m_icount -= 5;
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m_AC = (m_AC >> 1) | ((m_AC & 0x01) << 7);
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break;
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case 0x1f: // RRL
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m_icount -= 5;
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tmp = (m_AC & 0x01) << 7;
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m_AC = (m_AC >> 1) | (m_SR & 0x80);
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m_SR = (m_SR & 0x7f) | tmp;
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break;
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// Single Byte Miscellaneous Instructions
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case 0x00: // HALT
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m_icount -= 8;
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m_halt_func(1);
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m_halt_func(0);
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break;
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case 0x02: // CCL
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m_icount -= 5;
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m_SR &= 0x7f;
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break;
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case 0x03: // SCL
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m_icount -= 5;
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m_SR |= 0x80;
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break;
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case 0x04: // DINT
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m_icount -= 6;
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m_SR &= 0xf7;
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break;
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case 0x05: // IEN
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m_icount -= 6;
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m_SR |= 0x08;
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break;
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case 0x06: // CSA
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m_icount -= 5;
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m_SR &= 0xcf; // clear SA and SB flags
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m_SR |= m_sensea_func() ? 0x10 : 0x00;
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m_SR |= m_senseb_func() ? 0x20 : 0x00;
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m_AC = m_SR;
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break;
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case 0x07: // CAS
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m_icount -= 6;
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m_SR = m_AC;
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m_flag_out_func(m_SR & 0x07);
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break;
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case 0x08: // NOP
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m_icount -= 5;
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break;
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// Others are illegal
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default : m_icount -= 1;
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illegal (opcode);
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break;
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}
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}
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}
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/***************************************************************************
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COMMON EXECUTION
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***************************************************************************/
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void scmp_device::take_interrupt()
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{
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UINT16 tmp = ADD12(m_PC.w.l,-1); // We fix PC so at return it goes to current location
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m_SR &= 0xf7; // clear IE flag
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m_icount -= 8; // assumption
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// do XPPC 3
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m_PC.w.l = GET_PTR_REG(3)->w.l;
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GET_PTR_REG(3)->w.l = tmp;
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// After exchange CPU increment PC
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m_PC.w.l = ADD12(m_PC.w.l,1);
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}
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void scmp_device::execute_run()
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{
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do
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{
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if ((m_SR & 0x08) && (m_sensea_func())) {
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take_interrupt();
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}
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debugger_instruction_hook(this, m_PC.d);
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execute_one(ROP());
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} while (m_icount > 0);
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}
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/***************************************************************************
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CORE INITIALIZATION
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***************************************************************************/
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void scmp_device::device_start()
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{
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/* set up the state table */
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{
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state_add(SCMP_PC, "PC", m_PC.w.l);
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state_add(STATE_GENPC, "GENPC", m_PC.w.l).noshow();
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state_add(STATE_GENFLAGS, "GENFLAGS", m_SR).noshow().formatstr("%8s");
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state_add(SCMP_P1, "P1", m_P1.w.l);
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state_add(SCMP_P2, "P2", m_P2.w.l);
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state_add(SCMP_P3, "P3", m_P3.w.l);
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state_add(SCMP_AC, "AC", m_AC);
|
|
state_add(SCMP_ER, "ER", m_ER);
|
|
state_add(SCMP_SR, "SR", m_SR);
|
|
}
|
|
|
|
m_program = &space(AS_PROGRAM);
|
|
m_direct = &m_program->direct();
|
|
|
|
/* resolve callbacks */
|
|
m_flag_out_func.resolve_safe();
|
|
m_sout_func.resolve_safe();
|
|
m_sin_func.resolve_safe(0);
|
|
m_sensea_func.resolve_safe(0);
|
|
m_senseb_func.resolve_safe(0);
|
|
m_halt_func.resolve_safe();
|
|
|
|
save_item(NAME(m_PC));
|
|
save_item(NAME(m_P1));
|
|
save_item(NAME(m_P2));
|
|
save_item(NAME(m_P3));
|
|
save_item(NAME(m_AC));
|
|
save_item(NAME(m_ER));
|
|
save_item(NAME(m_SR));
|
|
|
|
m_icountptr = &m_icount;
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
COMMON RESET
|
|
***************************************************************************/
|
|
|
|
void scmp_device::device_reset()
|
|
{
|
|
m_PC.d = 0;
|
|
m_P1.d = 0;
|
|
m_P2.d = 0;
|
|
m_P3.d = 0;
|
|
m_AC = 0;
|
|
m_ER = 0;
|
|
m_SR = 0;
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************
|
|
COMMON STATE IMPORT/EXPORT
|
|
***************************************************************************/
|
|
|
|
void scmp_device::state_string_export(const device_state_entry &entry, std::string &str) const
|
|
{
|
|
switch (entry.index())
|
|
{
|
|
case STATE_GENFLAGS:
|
|
str = string_format("%c%c%c%c%c%c%c%c",
|
|
(m_SR & 0x80) ? 'C' : '.',
|
|
(m_SR & 0x40) ? 'V' : '.',
|
|
(m_SR & 0x20) ? 'B' : '.',
|
|
(m_SR & 0x10) ? 'A' : '.',
|
|
(m_SR & 0x08) ? 'I' : '.',
|
|
(m_SR & 0x04) ? '2' : '.',
|
|
(m_SR & 0x02) ? '1' : '.',
|
|
(m_SR & 0x01) ? '0' : '.');
|
|
break;
|
|
}
|
|
}
|