231 lines
6.7 KiB
C
231 lines
6.7 KiB
C
// license:MAME
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// copyright-holders:Robbbert
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/***************************************************************************
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CZK-80
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2010-08-30 Skeleton driver
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2010-11-27 Connected to a terminal
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2014-01-08 Added devices
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Only known info: http://forum.z80.de/showtopic.php?threadid=280
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On main board there are Z80A CPU, Z80A PIO, Z80A DART and Z80A CTC
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there is 8K ROM and XTAL 16MHz
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Two undumped proms, AM27S20DC and D3631-1.
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FDC board contains Z80A DMA and NEC 765A (XTAL on it is 8MHZ)
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Mega board contains 74LS612 and memory chips (32x 41256)
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Status:
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It prints 2 lines of text, then:
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- If fdc is enabled in address map, it hangs waiting for a fdc response.
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- Otherwise, it displays an error, and you can press a key to try again.
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ToDo:
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- Everything... no diagram or manuals, so EVERYTHING below is guesswork.
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- Need software
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I/O ports: These ranges are what is guessed
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40 : rom switching
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4c-4F : PIO
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50-53 : DART
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54-57 : CTC
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80-81 : Parallel port (no programming bytes are sent, so it isn't a device)
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C0-C1 : FDC
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It is not known what address is used by:
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- the DMA
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- the Motor-on signal(s)
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as there are no unknown writes.
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****************************************************************************/
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#include "emu.h"
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#include "cpu/z80/z80.h"
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#include "machine/upd765.h"
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#include "cpu/z80/z80daisy.h"
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#include "machine/z80pio.h"
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#include "machine/z80dart.h"
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#include "machine/z80ctc.h"
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#include "machine/terminal.h"
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#define TERMINAL_TAG "terminal"
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class czk80_state : public driver_device
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{
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public:
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czk80_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_terminal(*this, TERMINAL_TAG),
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m_fdc(*this, "fdc")
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{
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}
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DECLARE_DRIVER_INIT(czk80);
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DECLARE_MACHINE_RESET(czk80);
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TIMER_CALLBACK_MEMBER(czk80_reset);
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DECLARE_READ8_MEMBER(port80_r);
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DECLARE_READ8_MEMBER(port81_r);
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DECLARE_READ8_MEMBER(portc0_r);
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DECLARE_WRITE8_MEMBER(port40_w);
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DECLARE_WRITE8_MEMBER(kbd_put);
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DECLARE_WRITE_LINE_MEMBER(ctc_z0_w);
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DECLARE_WRITE_LINE_MEMBER(ctc_z1_w);
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DECLARE_WRITE_LINE_MEMBER(ctc_z2_w);
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private:
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UINT8 m_term_data;
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required_device<cpu_device> m_maincpu;
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required_device<generic_terminal_device> m_terminal;
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required_device<upd765a_device> m_fdc;
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};
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WRITE8_MEMBER( czk80_state::port40_w )
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{
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membank("bankr1")->set_entry(BIT(data, 1));
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}
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READ8_MEMBER( czk80_state::port80_r )
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{
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UINT8 ret = m_term_data;
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m_term_data = 0;
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return ret;
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}
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READ8_MEMBER( czk80_state::portc0_r )
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{
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return 0x80;
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}
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READ8_MEMBER( czk80_state::port81_r )
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{
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return (m_term_data) ? 3 : 1;
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}
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static ADDRESS_MAP_START(czk80_mem, AS_PROGRAM, 8, czk80_state)
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AM_RANGE(0x0000, 0x1fff) AM_READ_BANK("bankr0") AM_WRITE_BANK("bankw0")
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AM_RANGE(0x2000, 0xdfff) AM_RAM
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AM_RANGE(0xe000, 0xffff) AM_READ_BANK("bankr1") AM_WRITE_BANK("bankw1")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(czk80_io, AS_IO, 8, czk80_state)
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x40, 0x40) AM_WRITE(port40_w)
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AM_RANGE(0x4c, 0x4f) AM_DEVREADWRITE("z80pio", z80pio_device, read, write)
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AM_RANGE(0x50, 0x53) AM_DEVREADWRITE("z80dart", z80dart_device, cd_ba_r, cd_ba_w)
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AM_RANGE(0x54, 0x57) AM_DEVREADWRITE("z80ctc", z80ctc_device, read, write)
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AM_RANGE(0x80, 0x80) AM_READ(port80_r) AM_DEVWRITE(TERMINAL_TAG, generic_terminal_device, write)
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AM_RANGE(0x81, 0x81) AM_READ(port81_r)
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/* Select one of the below */
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//AM_RANGE(0xc0, 0xc0) AM_READ(portc0_r)
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AM_RANGE(0xc0, 0xc1) AM_DEVICE("fdc", upd765a_device, map)
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ADDRESS_MAP_END
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/* Input ports */
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static INPUT_PORTS_START( czk80 )
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INPUT_PORTS_END
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/* Z80 Daisy Chain */
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static const z80_daisy_config daisy_chain[] =
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{
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{ "z80pio" },
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{ "z80dart" },
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{ "z80ctc" },
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{ NULL }
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};
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/* Z80-CTC Interface */
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WRITE_LINE_MEMBER( czk80_state::ctc_z0_w )
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{
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// guess this generates clock for z80dart
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}
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WRITE_LINE_MEMBER( czk80_state::ctc_z1_w )
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{
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}
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WRITE_LINE_MEMBER( czk80_state::ctc_z2_w )
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{
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}
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/* after the first 4 bytes have been read from ROM, switch the ram back in */
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TIMER_CALLBACK_MEMBER( czk80_state::czk80_reset)
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{
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membank("bankr0")->set_entry(1);
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}
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MACHINE_RESET_MEMBER( czk80_state, czk80 )
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{
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machine().scheduler().timer_set(attotime::from_usec(3), timer_expired_delegate(FUNC(czk80_state::czk80_reset),this));
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membank("bankr0")->set_entry(0); // point at rom
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membank("bankw0")->set_entry(0); // always write to ram
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membank("bankr1")->set_entry(0); // point at rom
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membank("bankw1")->set_entry(0); // always write to ram
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}
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DRIVER_INIT_MEMBER( czk80_state, czk80 )
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{
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UINT8 *main = memregion("maincpu")->base();
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membank("bankr0")->configure_entry(1, &main[0x0000]);
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membank("bankr0")->configure_entry(0, &main[0x10000]);
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membank("bankw0")->configure_entry(0, &main[0x0000]);
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membank("bankr1")->configure_entry(1, &main[0xe000]);
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membank("bankr1")->configure_entry(0, &main[0x10000]);
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membank("bankw1")->configure_entry(0, &main[0xe000]);
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}
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static SLOT_INTERFACE_START( czk80_floppies )
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SLOT_INTERFACE( "525dd", FLOPPY_525_DD )
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SLOT_INTERFACE_END
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WRITE8_MEMBER( czk80_state::kbd_put )
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{
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m_term_data = data;
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}
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static MACHINE_CONFIG_START( czk80, czk80_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", Z80, XTAL_16MHz / 4)
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MCFG_CPU_PROGRAM_MAP(czk80_mem)
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MCFG_CPU_IO_MAP(czk80_io)
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MCFG_CPU_CONFIG(daisy_chain)
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MCFG_MACHINE_RESET_OVERRIDE(czk80_state, czk80)
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MCFG_DEVICE_ADD(TERMINAL_TAG, GENERIC_TERMINAL, 0)
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MCFG_GENERIC_TERMINAL_KEYBOARD_CB(WRITE8(czk80_state, kbd_put))
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MCFG_UPD765A_ADD("fdc", false, true)
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MCFG_FLOPPY_DRIVE_ADD("fdc:0", czk80_floppies, "525dd", floppy_image_device::default_floppy_formats)
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MCFG_DEVICE_ADD("z80ctc", Z80CTC, XTAL_16MHz / 4)
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MCFG_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_Z80CTC_ZC0_CB(WRITELINE(czk80_state, ctc_z0_w))
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MCFG_Z80CTC_ZC1_CB(WRITELINE(czk80_state, ctc_z1_w))
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MCFG_Z80CTC_ZC2_CB(WRITELINE(czk80_state, ctc_z2_w))
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MCFG_Z80DART_ADD("z80dart", XTAL_16MHz / 4, 0, 0, 0, 0 )
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//MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232", rs232_port_device, write_txd))
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//MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232", rs232_port_device, write_dtr))
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//MCFG_Z80DART_OUT_RTSA_CB(DEVWRITELINE("rs232", rs232_port_device, write_rts))
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MCFG_Z80DART_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_DEVICE_ADD("z80pio", Z80PIO, XTAL_16MHz/4)
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MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MACHINE_CONFIG_END
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/* ROM definition */
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ROM_START( czk80 )
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ROM_REGION( 0x12000, "maincpu", 0 )
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ROM_LOAD( "czk80.rom", 0x10000, 0x2000, CRC(7081b7c6) SHA1(13f75b14ea73b252bdfa2384e6eead6e720e49e3))
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ROM_END
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/* Driver */
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/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
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COMP( 198?, czk80, 0, 0, czk80, czk80, czk80_state, czk80, "<unknown>", "CZK-80", GAME_NOT_WORKING | GAME_NO_SOUND_HW)
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