mirror of
https://github.com/holub/mame
synced 2025-06-03 03:16:30 +03:00
377 lines
11 KiB
C
377 lines
11 KiB
C
// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz
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//================================================================
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//
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// mb86901defs.h - Helpful #defines for emulating the MB86901
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// series of SPARC processor.
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//
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//================================================================
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#pragma once
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#ifndef __MB86901_DEFS_H__
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#define __MB86901_DEFS_H__
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#define PSR_CWP_MASK 0x0000001f
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#define PSR_ET_SHIFT 5
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#define PSR_ET_MASK 0x00000020
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#define PSR_PS_SHIFT 6
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#define PSR_PS_MASK 0x00000040
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#define PSR_S_SHIFT 7
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#define PSR_S_MASK 0x00000080
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#define PSR_PIL_SHIFT 8
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#define PSR_PIL_MASK 0x00000f00
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#define PSR_EF_SHIFT 12
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#define PSR_EF_MASK 0x00001000
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#define PSR_EC_SHIFT 13
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#define PSR_EC_MASK 0x00002000
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#define PSR_ICC_SHIFT 20
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#define PSR_RES_MASK 0x000fc000
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#define PSR_ICC_MASK 0x00f00000
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#define PSR_N_MASK 0x00800000
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#define PSR_Z_MASK 0x00400000
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#define PSR_V_MASK 0x00200000
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#define PSR_C_MASK 0x00100000
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#define PSR_VER_SHIFT 24
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#define PSR_VER_MASK 0x0f000000
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#define PSR_VER 0
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#define PSR_IMPL_SHIFT 28
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#define PSR_IMPL_MASK 0xf0000000
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#define PSR_IMPL 0
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#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK)
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#define ICC_N_SET (m_psr & PSR_N_MASK)
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#define ICC_N (ICC_N_SET ? 1 : 0)
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#define ICC_N_CLEAR (!ICC_N_SET)
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#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0)
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#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0)
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#define ICC_Z_SET (m_psr & PSR_Z_MASK)
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#define ICC_Z (ICC_Z_SET ? 1 : 0)
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#define ICC_Z_CLEAR (!ICC_Z_SET)
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#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0)
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#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0)
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#define ICC_V_SET (m_psr & PSR_V_MASK)
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#define ICC_V (ICC_V_SET ? 1 : 0)
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#define ICC_V_CLEAR (!ICC_V_SET)
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#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0)
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#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0)
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#define ICC_C_SET (m_psr & PSR_C_MASK)
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#define ICC_C (ICC_C_SET ? 1 : 0)
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#define ICC_C_CLEAR (!ICC_C_SET)
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#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0)
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#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0)
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#define CLEAR_ICC do { m_psr &= ~PSR_ICC_MASK; } while(0)
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#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0)
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#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0)
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#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0)
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#define IS_SUPERVISOR (m_psr & PSR_S_MASK)
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#define IS_USER (!IS_SUPERVISOR)
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#define TRAPS_ENABLED (m_psr & PSR_ET_MASK)
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#define TRAPS_DISABLED (!TRAPS_ENABLED)
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#define PSR m_psr
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#define WIM m_wim
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#define TBR m_tbr
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#define OP (op >> 30) // gangnam style
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#define OP2 ((op >> 22) & 7)
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#define OP3 ((op >> 19) & 63)
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#define OPF ((op >> 5) & 0x1ff)
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#define OPC ((op >> 5) & 0x1ff)
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#define OPFLOW ((op >> 5) & 0x3f)
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#define DISP30 (INT32(op << 2))
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#define DISP22 (INT32(op << 10) >> 8)
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#define DISP19 (INT32(op << 13) >> 11)
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#define DISP16 (INT32(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14)
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#define IMM22 (op << 10)
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#define CONST22 (op & 0x3fffff)
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#define SIMM13 (INT32(op << 19) >> 19)
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#define SIMM11 (INT32(op << 21) >> 21)
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#define SIMM10 (INT32(op << 22) >> 22)
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#define SIMM8 (INT32(op << 24) >> 24)
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#define IMM7 (op & 0x7f)
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#define SIMM7 (INT32(op << 25) >> 25)
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#define SHCNT32 (op & 31)
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#define SHCNT64 (op & 63)
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#define IAMODE (op & 0x7)
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#define USEIMM ((op >> 13) & 1)
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#define USEEXT ((op >> 12) & 1)
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#define COND ((op >> 25) & 15)
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#define RCOND ((op >> 10) & 7)
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#define MOVCOND ((op >> 14) & 15)
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#define PRED ((op >> 19) & 1)
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#define ANNUL ((op >> 29) & 1)
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#define BRCC ((op >> 20) & 3)
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#define MOVCC (((op >> 11) & 3) | ((op >> 16) & 4))
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#define OPFCC ((op >> 11) & 7)
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#define TCCCC ((op >> 11) & 3)
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#define ASI ((op >> 5) & 255)
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#define MMASK (op & 15)
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#define CMASK ((op >> 4) & 7)
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#define RD ((op >> 25) & 31)
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#define RS1 ((op >> 14) & 31)
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#define RS2 (op & 31)
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#define FREG(x) m_fpr[(x)]
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#define FDREG m_fpr[RD]
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#define FSR m_fsr
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#define REG(x) *m_regs[(x)]
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#define RDREG *m_regs[RD]
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#define RS1REG *m_regs[RS1]
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#define RS2REG *m_regs[RS2]
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#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0)
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#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
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#define PC m_pc
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#define nPC m_npc
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#define Y m_y
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#define MAE m_mae
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#define HOLD_BUS m_hold_bus
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#define BIT31(x) ((x) & 0x80000000)
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#define UPDATE_PC true
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#define PC_UPDATED false
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#define OP_TYPE0 0
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#define OP_CALL 1
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#define OP_ALU 2
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#define OP_LDST 3
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#define OP2_UNIMP 0
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#define OP2_BICC 2
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#define OP2_SETHI 4
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#define OP2_FBFCC 6
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#define OP2_CBCCC 7
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#define OP3_ADD 0
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#define OP3_AND 1
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#define OP3_OR 2
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#define OP3_XOR 3
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#define OP3_SUB 4
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#define OP3_ANDN 5
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#define OP3_ORN 6
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#define OP3_XNOR 7
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#define OP3_ADDX 8
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#define OP3_UMUL 10
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#define OP3_SMUL 11
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#define OP3_SUBX 12
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#define OP3_UDIV 14
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#define OP3_SDIV 15
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#define OP3_ADDCC 16
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#define OP3_ANDCC 17
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#define OP3_ORCC 18
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#define OP3_XORCC 19
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#define OP3_SUBCC 20
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#define OP3_ANDNCC 21
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#define OP3_ORNCC 22
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#define OP3_XNORCC 23
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#define OP3_ADDXCC 24
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#define OP3_UMULCC 26
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#define OP3_SMULCC 27
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#define OP3_SUBXCC 28
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#define OP3_UDIVCC 30
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#define OP3_SDIVCC 31
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#define OP3_TADDCC 32
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#define OP3_TSUBCC 33
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#define OP3_TADDCCTV 34
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#define OP3_TSUBCCTV 35
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#define OP3_MULSCC 36
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#define OP3_SLL 37
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#define OP3_SRL 38
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#define OP3_SRA 39
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#define OP3_RDASR 40
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#define OP3_RDPSR 41
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#define OP3_RDWIM 42
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#define OP3_RDTBR 43
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#define OP3_WRASR 48
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#define OP3_WRPSR 49
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#define OP3_WRWIM 50
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#define OP3_WRTBR 51
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#define OP3_FPOP1 52
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#define OP3_FPOP2 53
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#define OP3_JMPL 56
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#define OP3_RETT 57
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#define OP3_TICC 58
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#define OP3_SAVE 60
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#define OP3_RESTORE 61
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#define OP3_LD 0
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#define OP3_LDUB 1
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#define OP3_LDUH 2
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#define OP3_LDD 3
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#define OP3_ST 4
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#define OP3_STB 5
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#define OP3_STH 6
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#define OP3_STD 7
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#define OP3_LDSB 9
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#define OP3_LDSH 10
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#define OP3_LDSTUB 13
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#define OP3_SWAP 15
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#define OP3_LDA 16
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#define OP3_LDUBA 17
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#define OP3_LDUHA 18
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#define OP3_LDDA 19
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#define OP3_STA 20
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#define OP3_STBA 21
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#define OP3_STHA 22
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#define OP3_STDA 23
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#define OP3_LDSBA 25
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#define OP3_LDSHA 26
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#define OP3_LDSTUBA 29
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#define OP3_SWAPA 31
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#define OP3_LDFPR 32
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#define OP3_LDFSR 33
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#define OP3_LDDFPR 35
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#define OP3_STFPR 36
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#define OP3_STFSR 37
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#define OP3_STDFQ 38
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#define OP3_STDFPR 39
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#define OP3_LDCPR 40
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#define OP3_LDCSR 41
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#define OP3_LDDCPR 43
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#define OP3_STCPR 44
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#define OP3_STCSR 45
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#define OP3_STDCQ 46
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#define OP3_STDCPR 47
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#define OP3_CPOP1 54
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#define OP3_CPOP2 55
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#define COND_BN 0
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#define COND_BE 1
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#define COND_BLE 2
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#define COND_BL 3
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#define COND_BLEU 4
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#define COND_BCS 5
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#define COND_BNEG 6
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#define COND_BVS 7
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#define COND_BA 8
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#define COND_BNE 9
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#define COND_BG 10
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#define COND_BGE 11
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#define COND_BGU 12
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#define COND_BCC 13
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#define COND_BPOS 14
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#define COND_BVC 15
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#define LDD (OP3 == OP3_LDD)
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#define LD (OP3 == OP3_LD)
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#define LDSH (OP3 == OP3_LDSH)
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#define LDUH (OP3 == OP3_LDUH)
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#define LDSB (OP3 == OP3_LDSB)
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#define LDUB (OP3 == OP3_LDUB)
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#define LDDF (OP3 == OP3_LDDFPR)
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#define LDF (OP3 == OP3_LDFPR)
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#define LDFSR (OP3 == OP3_LDFSR)
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#define LDDC (OP3 == OP3_LDDCPR)
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#define LDC (OP3 == OP3_LDCPR)
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#define LDCSR (OP3 == OP3_LDCSR)
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#define LDDA (OP3 == OP3_LDDA)
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#define LDA (OP3 == OP3_LDA)
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#define LDSHA (OP3 == OP3_LDSHA)
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#define LDUHA (OP3 == OP3_LDUHA)
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#define LDSBA (OP3 == OP3_LDSBA)
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#define LDUBA (OP3 == OP3_LDUBA)
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#define STD (OP3 == OP3_STD)
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#define ST (OP3 == OP3_ST)
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#define STH (OP3 == OP3_STH)
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#define STB (OP3 == OP3_STB)
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#define STDA (OP3 == OP3_STDA)
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#define STA (OP3 == OP3_STA)
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#define STHA (OP3 == OP3_STHA)
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#define STBA (OP3 == OP3_STBA)
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#define STF (OP3 == OP3_STFPR)
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#define STFSR (OP3 == OP3_STFSR)
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#define STDFQ (OP3 == OP3_STDFQ)
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#define STDF (OP3 == OP3_STDFPR)
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#define STC (OP3 == OP3_STCPR)
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#define STCSR (OP3 == OP3_STCSR)
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#define STDCQ (OP3 == OP3_STDCQ)
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#define STDC (OP3 == OP3_STDCPR)
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#define JMPL (OP3 == OP3_JMPL)
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#define TICC (OP3 == OP3_TICC)
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#define RETT (OP3 == OP3_RETT)
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#define SWAP (OP3 == OP3_SWAP)
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#define SWAPA (OP3 == OP3_SWAPA)
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#define FPOP1 (OP3 == OP3_FPOP1)
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#define FPOP2 (OP3 == OP3_FPOP2)
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#define CPOP1 (OP3 == OP3_CPOP1)
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#define CPOP2 (OP3 == OP3_CPOP2)
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#define LDSTUB (OP3 == OP3_LDSTUB)
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#define LDSTUBA (OP3 == OP3_LDSTUBA)
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#define ADD (OP3 == OP3_ADD)
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#define ADDX (OP3 == OP3_ADDX)
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#define ADDCC (OP3 == OP3_ADDCC)
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#define ADDXCC (OP3 == OP3_ADDXCC)
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#define SUB (OP3 == OP3_SUB)
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#define SUBX (OP3 == OP3_SUBX)
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#define SUBCC (OP3 == OP3_SUBCC)
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#define SUBXCC (OP3 == OP3_SUBXCC)
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#define TADDCCTV (OP3 == OP3_TADDCCTV)
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#define TSUBCCTV (OP3 == OP3_TSUBCCTV)
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#define AND (OP3 == OP3_AND)
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#define OR (OP3 == OP3_OR)
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#define XOR (OP3 == OP3_XOR)
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#define ANDN (OP3 == OP3_ANDN)
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#define ORN (OP3 == OP3_ORN)
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#define XNOR (OP3 == OP3_XNOR)
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#define ANDCC (OP3 == OP3_ANDCC)
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#define ORCC (OP3 == OP3_ORCC)
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#define XORCC (OP3 == OP3_XORCC)
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#define ANDNCC (OP3 == OP3_ANDNCC)
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#define ORNCC (OP3 == OP3_ORNCC)
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#define XNORCC (OP3 == OP3_XNORCC)
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#define SLL (OP3 == OP3_SLL)
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#define SRL (OP3 == OP3_SRL)
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#define SRA (OP3 == OP3_SRA)
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#define RDASR (OP3 == OP3_RDASR)
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#define RDPSR (OP3 == OP3_RDPSR)
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#define RDWIM (OP3 == OP3_RDWIM)
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#define RDTBR (OP3 == OP3_RDTBR)
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#define WRASR (OP3 == OP3_WRASR)
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#define WRPSR (OP3 == OP3_WRPSR)
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#define WRWIM (OP3 == OP3_WRWIM)
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#define WRTBR (OP3 == OP3_WRTBR)
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#define SAVE (OP3 == OP3_SAVE)
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#define RESTORE (OP3 == OP3_RESTORE)
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#define UMUL (OP3 == OP3_UMUL)
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#define UMULCC (OP3 == OP3_UMULCC)
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#define SMUL (OP3 == OP3_SMUL)
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#define SMULCC (OP3 == OP3_SMULCC)
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#define UDIV (OP3 == OP3_UDIV)
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#define UDIVCC (OP3 == OP3_UDIVCC)
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#define SDIV (OP3 == OP3_SDIV)
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#define SDIVCC (OP3 == OP3_SDIVCC)
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#endif // __MB86901_DEFS_H__
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