270 lines
6.7 KiB
C++
270 lines
6.7 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:hap
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/*
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Sharp SM511 MCU core implementation
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TODO:
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- undocumented/guessed opcodes:
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* $01 is guessed as DIV to ACC transfer, unknown which bits
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* $5d is certainly CEND
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* $65 is certainly divider reset, but not sure if it behaves same as on SM510
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* $6036 and $6037 may be instruction timing? (16kHz and 8kHz), mnemonics unknown
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*/
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#include "emu.h"
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#include "sm510.h"
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#include "sm510d.h"
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#include "debugger.h"
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// MCU types
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DEFINE_DEVICE_TYPE(SM511, sm511_device, "sm511", "SM511") // 4Kx8 ROM, 128x4 RAM(32x4 for LCD), melody controller
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DEFINE_DEVICE_TYPE(SM512, sm512_device, "sm512", "SM512") // 4Kx8 ROM, 128x4 RAM(48x4 for LCD), melody controller
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// internal memory maps
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ADDRESS_MAP_START(sm511_device::program_4k)
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AM_RANGE(0x0000, 0x0fff) AM_ROM
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ADDRESS_MAP_END
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ADDRESS_MAP_START(sm511_device::data_96_32x4)
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AM_RANGE(0x00, 0x5f) AM_RAM
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AM_RANGE(0x60, 0x6f) AM_RAM AM_SHARE("lcd_ram_a")
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AM_RANGE(0x70, 0x7f) AM_RAM AM_SHARE("lcd_ram_b")
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ADDRESS_MAP_END
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ADDRESS_MAP_START(sm512_device::data_80_48x4)
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AM_RANGE(0x00, 0x4f) AM_RAM
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AM_RANGE(0x50, 0x5f) AM_RAM AM_SHARE("lcd_ram_c")
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AM_RANGE(0x60, 0x6f) AM_RAM AM_SHARE("lcd_ram_a")
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AM_RANGE(0x70, 0x7f) AM_RAM AM_SHARE("lcd_ram_b")
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ADDRESS_MAP_END
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// disasm
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util::disasm_interface *sm511_device::create_disassembler()
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{
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return new sm511_disassembler;
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}
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// device definitions
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sm511_device::sm511_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: sm511_device(mconfig, SM511, tag, owner, clock, 2 /* stack levels */, 12 /* prg width */, address_map_constructor(FUNC(sm511_device::program_4k), this), 7 /* data width */, address_map_constructor(FUNC(sm511_device::data_96_32x4), this))
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{
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}
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sm511_device::sm511_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int stack_levels, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data)
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: sm510_base_device(mconfig, type, tag, owner, clock, stack_levels, prgwidth, program, datawidth, data)
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{
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}
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sm512_device::sm512_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: sm511_device(mconfig, SM512, tag, owner, clock, 2, 12, address_map_constructor(FUNC(sm512_device::program_4k), this), 7, address_map_constructor(FUNC(sm512_device::data_80_48x4), this))
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{
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void sm511_device::device_reset()
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{
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sm510_base_device::device_reset();
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m_melody_rd &= ~1;
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m_clk_div = 4; // 8kHz
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notify_clock_changed();
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}
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//-------------------------------------------------
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// melody controller
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//-------------------------------------------------
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void sm511_device::clock_melody()
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{
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if (!m_melody_rom)
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return;
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// tone cycle table (SM511/SM512 datasheet fig.5)
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// cmd 0 = rest, 1 = stop, > 13 = illegal(inactive?)
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static const u8 lut_tone_cycles[4*16] =
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{
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0, 0, 7, 8, 8, 9, 9, 10,11,11,12,13,14,14, 0, 0,
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0, 0, 8, 8, 9, 9, 10,11,11,12,13,13,14,15, 0, 0,
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0, 0, 8, 8, 9, 9, 10,10,11,12,12,13,14,15, 0, 0,
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0, 0, 8, 9, 9, 10,10,11,11,12,13,14,14,15, 0, 0,
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};
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u8 cmd = m_melody_rom[m_melody_address] & 0x3f;
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u8 out = 0;
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// clock duty cycle if tone is active
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if ((cmd & 0xf) >= 2 && (cmd & 0xf) <= 13)
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{
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out = m_melody_duty_index & m_melody_rd & 1;
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m_melody_duty_count++;
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int index = m_melody_duty_index << 4 | (cmd & 0xf);
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int shift = ~cmd >> 4 & 1; // OCT
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if (m_melody_duty_count >= (lut_tone_cycles[index] << shift))
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{
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m_melody_duty_count = 0;
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m_melody_duty_index = (m_melody_duty_index + 1) & 3;
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}
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}
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else if ((cmd & 0xf) == 1)
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{
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// set melody stop flag
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m_melody_rd |= 2;
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}
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// clock time base on F8(d7)
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if ((m_div & 0x7f) == 0)
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{
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u8 mask = (cmd & 0x20) ? 0x1f : 0x0f;
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m_melody_step_count = (m_melody_step_count + 1) & mask;
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if (m_melody_step_count == 0)
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m_melody_address++;
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}
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// output to R pin
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if (out != m_r_out)
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{
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m_write_r(0, out, 0xff);
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m_r_out = out;
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}
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}
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void sm511_device::init_melody()
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{
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if (!m_melody_rom)
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return;
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// verify melody rom
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for (int i = 0; i < 0x100; i++)
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{
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u8 data = m_melody_rom[i];
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if (data & 0xc0 || (data & 0x0f) > 13)
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logerror("%s unknown melody ROM data $%02X at $%02X\n", tag(), data, i);
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}
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}
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//-------------------------------------------------
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// execute
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//-------------------------------------------------
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void sm511_device::get_opcode_param()
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{
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// LBL, PRE, TL, TML and prefix opcodes are 2 bytes
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if ((m_op >= 0x5f && m_op <= 0x61) || (m_op & 0xf0) == 0x70 || (m_op & 0xfc) == 0x68)
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{
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m_icount--;
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m_param = m_program->read_byte(m_pc);
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increment_pc();
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}
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}
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void sm511_device::execute_one()
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{
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switch (m_op & 0xf0)
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{
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case 0x20: op_lax(); break;
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case 0x30: op_adx(); break;
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case 0x40: op_lb(); break;
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case 0x70: op_tl(); break;
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case 0x80: case 0x90: case 0xa0: case 0xb0:
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op_t(); break;
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case 0xc0: case 0xd0: case 0xe0: case 0xf0:
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op_tm(); break;
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default:
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switch (m_op & 0xfc)
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{
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case 0x04: op_rm(); break;
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case 0x0c: op_sm(); break;
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case 0x10: op_exc(); break;
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case 0x14: op_exci(); break;
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case 0x18: op_lda(); break;
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case 0x1c: op_excd(); break;
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case 0x54: op_tmi(); break;
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case 0x68: op_tml(); break;
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default:
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switch (m_op)
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{
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case 0x00: op_rot(); break;
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case 0x01: op_dta(); break;
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case 0x02: op_sbm(); break;
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case 0x03: op_atpl(); break;
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case 0x08: op_add(); break;
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case 0x09: op_add11(); break;
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case 0x0a: op_coma(); break;
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case 0x0b: op_exbla(); break;
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case 0x50: op_kta(); break;
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case 0x51: op_tb(); break;
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case 0x52: op_tc(); break;
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case 0x53: op_tam(); break;
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case 0x58: op_tis(); break;
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case 0x59: op_atl(); break;
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case 0x5a: op_ta0(); break;
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case 0x5b: op_tabl(); break;
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case 0x5c: op_atx(); break;
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case 0x5d: op_cend(); break;
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case 0x5e: op_tal(); break;
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case 0x5f: op_lbl(); break;
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case 0x61: op_pre(); break;
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case 0x62: op_wr(); break;
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case 0x63: op_ws(); break;
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case 0x64: op_incb(); break;
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case 0x65: op_dr(); break;
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case 0x66: op_rc(); break;
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case 0x67: op_sc(); break;
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case 0x6c: op_decb(); break;
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case 0x6d: op_ptw(); break;
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case 0x6e: op_rtn0(); break;
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case 0x6f: op_rtn1(); break;
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// extended opcodes
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case 0x60:
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m_op = m_op << 8 | m_param;
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switch (m_param)
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{
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case 0x30: op_rme(); break;
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case 0x31: op_sme(); break;
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case 0x32: op_tmel(); break;
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case 0x33: op_atfc(); break;
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case 0x34: op_bdc(); break;
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case 0x35: op_atbp(); break;
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case 0x36: op_clkhi(); break;
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case 0x37: op_clklo(); break;
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default: op_illegal(); break;
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}
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break; // 0x60
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default: op_illegal(); break;
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}
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break; // 0xff
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}
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break; // 0xfc
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} // big switch
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// BM high bit is only valid for 1 step
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m_sbm = (m_op == 0x02);
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}
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