mirror of
https://github.com/holub/mame
synced 2025-05-09 07:41:50 +03:00
d1b109625d
Converted PlayStation DMA to an internal device to the CPU core. DMA to external devices can be set in the machine config, the old calls are still there until the rest of the code is converted. [smf] The following MAME core changes have been required to allow internal devices to be configurable by the main machine config & to work with internal memory maps. device.machine_config_additions() are now processed as soon as the device is added, so sub devices can be configured straight away. replacing or removing a device removes any devices owned by the device being removed, as now they are added straight away. device_t::subdevice() uses the machine config device list instead of the machine to find the device as the machine is not created until after all the devices have been created. devices in an internal address map are assumed to be owned by the CPU, while devices in a standard address maps are assumed to be siblings of the CPU. A code review and regression test would be a good idea.
429 lines
11 KiB
C
429 lines
11 KiB
C
/*
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* PlayStation DMA emulator
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*
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* Copyright 2003-2011 smf
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*
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*/
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#include "emu.h"
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#include "dma.h"
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#include "includes/psx.h"
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#define VERBOSE_LEVEL ( 0 )
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INLINE void ATTR_PRINTF(3,4) verboselog( running_machine& machine, int n_level, const char *s_fmt, ... )
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{
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if( VERBOSE_LEVEL >= n_level )
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{
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va_list v;
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char buf[ 32768 ];
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va_start( v, s_fmt );
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vsprintf( buf, s_fmt, v );
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va_end( v );
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logerror( "%s: %s", machine.describe_context(), buf );
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}
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}
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const device_type PSX_DMA = &device_creator<psxdma_device>;
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psxdma_device::psxdma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, PSX_DMA, "PSX DMA", tag, owner, clock)
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{
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for( int index = 0; index < 7; index++ )
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{
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psx_dma_channel *dma = &channel[ index ];
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dma->fn_read = NULL;
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dma->fn_write = NULL;
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}
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}
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void psxdma_device::device_reset()
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{
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int n;
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n_dpcp = 0;
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n_dicr = 0;
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for( n = 0; n < 7; n++ )
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{
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dma_stop_timer( n );
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}
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}
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void psxdma_device::device_post_load()
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{
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int n;
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for( n = 0; n < 7; n++ )
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{
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dma_timer_adjust( n );
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}
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}
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void psxdma_device::device_start()
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{
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for( int index = 0; index < 7; index++ )
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{
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psx_dma_channel *dma = &channel[ index ];
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dma->timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(psxdma_device::dma_finished_callback), this));
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machine().save().save_item( "psxdma", tag(), index, NAME(dma->n_base) );
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machine().save().save_item( "psxdma", tag(), index, NAME(dma->n_blockcontrol) );
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machine().save().save_item( "psxdma", tag(), index, NAME(dma->n_channelcontrol) );
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machine().save().save_item( "psxdma", tag(), index, NAME(dma->n_ticks) );
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machine().save().save_item( "psxdma", tag(), index, NAME(dma->b_running) );
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}
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save_item( NAME(n_dpcp) );
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save_item( NAME(n_dicr) );
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}
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void psxdma_device::dma_start_timer( int index, UINT32 n_ticks )
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{
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psx_dma_channel *dma = &channel[ index ];
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dma->timer->adjust( attotime::from_hz(33868800) * n_ticks, index);
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dma->n_ticks = n_ticks;
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dma->b_running = 1;
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}
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void psxdma_device::dma_stop_timer( int index )
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{
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psx_dma_channel *dma = &channel[ index ];
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dma->timer->adjust( attotime::never);
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dma->b_running = 0;
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}
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void psxdma_device::dma_timer_adjust( int index )
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{
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psx_dma_channel *dma = &channel[ index ];
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if( dma->b_running )
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{
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dma_start_timer( index, dma->n_ticks );
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}
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else
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{
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dma_stop_timer( index );
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}
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}
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void psxdma_device::dma_interrupt_update()
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{
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int n_int;
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int n_mask;
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n_int = ( n_dicr >> 24 ) & 0x7f;
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n_mask = ( n_dicr >> 16 ) & 0xff;
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if( ( n_mask & 0x80 ) != 0 && ( n_int & n_mask ) != 0 )
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{
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verboselog( machine(), 2, "dma_interrupt_update( %02x, %02x ) interrupt triggered\n", n_int, n_mask );
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n_dicr |= 0x80000000;
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psx_irq_set( machine(), PSX_IRQ_DMA );
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}
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else if( n_int != 0 )
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{
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verboselog( machine(), 2, "dma_interrupt_update( %02x, %02x ) interrupt not enabled\n", n_int, n_mask );
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}
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n_dicr &= 0x00ffffff | ( n_dicr << 8 );
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}
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void psxdma_device::dma_finished( int index )
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{
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psx_machine *p_psx = machine().driver_data<psx_state>()->m_p_psx;
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UINT32 *p_n_psxram = p_psx->p_n_psxram;
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psx_dma_channel *dma = &channel[ index ];
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if( dma->n_channelcontrol == 0x01000401 && index == 2 )
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{
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UINT32 n_size;
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UINT32 n_total;
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UINT32 n_address = ( dma->n_base & 0xffffff );
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UINT32 n_adrmask = p_psx->n_psxramsize - 1;
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UINT32 n_nextaddress;
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if( n_address != 0xffffff )
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{
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n_total = 0;
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for( ;; )
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{
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if( n_address == 0xffffff )
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{
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dma->n_base = n_address;
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dma_start_timer( index, 19000 );
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return;
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}
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if( n_total > 65535 )
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{
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dma->n_base = n_address;
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//FIXME:
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// 16000 below is based on try and error.
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// Mametesters.org: sfex20103red
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//dma_start_timer( index, 16 );
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dma_start_timer( index, 16000 );
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return;
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}
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n_address &= n_adrmask;
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n_nextaddress = p_n_psxram[ n_address / 4 ];
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n_size = n_nextaddress >> 24;
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(*dma->fn_write)( machine(), n_address + 4, n_size );
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//FIXME:
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// The following conditions will cause an endless loop.
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// If stopping the transfer is correct I cannot judge
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// The patch is meant as a hint for somebody who knows
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// the hardware.
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// Mametesters.org: psyforce0105u5red, raystorm0111u1red
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if ((n_nextaddress & 0xffffff) != 0xffffff)
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if (n_address == p_n_psxram[ (n_nextaddress & 0xffffff) / 4])
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break;
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if (n_address == (n_nextaddress & 0xffffff) )
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break;
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n_address = ( n_nextaddress & 0xffffff );
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n_total += ( n_size + 1 );
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}
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}
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}
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dma->n_channelcontrol &= ~( ( 1L << 0x18 ) | ( 1L << 0x1c ) );
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n_dicr |= 1 << ( 24 + index );
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dma_interrupt_update();
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dma_stop_timer( index );
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}
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void psxdma_device::dma_finished_callback(void *ptr, int param)
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{
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dma_finished(param);
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}
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void psxdma_device::install_read_handler( int index, psx_dma_read_handler p_fn_dma_read )
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{
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channel[ index ].fn_read = p_fn_dma_read;
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}
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void psxdma_device::install_write_handler( int index, psx_dma_read_handler p_fn_dma_write )
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{
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channel[ index ].fn_write = p_fn_dma_write;
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}
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WRITE32_MEMBER( psxdma_device::write )
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{
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psx_machine *p_psx = machine().driver_data<psx_state>()->m_p_psx;
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UINT32 *p_n_psxram = p_psx->p_n_psxram;
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int index = offset / 4;
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psx_dma_channel *dma = &channel[ index ];
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if( index < 7 )
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{
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switch( offset % 4 )
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{
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case 0:
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verboselog( machine(), 2, "dmabase( %d ) = %08x\n", index, data );
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dma->n_base = data;
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break;
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case 1:
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verboselog( machine(), 2, "dmablockcontrol( %d ) = %08x\n", index, data );
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dma->n_blockcontrol = data;
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break;
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case 2:
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verboselog( machine(), 2, "dmachannelcontrol( %d ) = %08x\n", index, data );
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dma->n_channelcontrol = data;
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if( ( dma->n_channelcontrol & ( 1L << 0x18 ) ) != 0 && ( n_dpcp & ( 1 << ( 3 + ( index * 4 ) ) ) ) != 0 )
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{
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INT32 n_size;
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UINT32 n_address;
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UINT32 n_nextaddress;
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UINT32 n_adrmask;
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n_adrmask = p_psx->n_psxramsize - 1;
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n_address = ( dma->n_base & n_adrmask );
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n_size = dma->n_blockcontrol;
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if( ( dma->n_channelcontrol & 0x200 ) != 0 )
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{
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UINT32 n_ba;
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n_ba = dma->n_blockcontrol >> 16;
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if( n_ba == 0 )
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{
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n_ba = 0x10000;
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}
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n_size = ( n_size & 0xffff ) * n_ba;
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}
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if( dma->n_channelcontrol == 0x01000000 &&
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dma->fn_read != NULL )
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{
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verboselog( machine(), 1, "dma %d read block %08x %08x\n", index, n_address, n_size );
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(*dma->fn_read)( machine(), n_address, n_size );
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dma_finished( index );
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}
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else if (dma->n_channelcontrol == 0x11000000 && // CD DMA
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dma->fn_read != NULL )
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{
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verboselog( machine(), 1, "dma %d read block %08x %08x\n", index, n_address, n_size );
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// pSX's CD DMA size calc formula
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int oursize = (dma->n_blockcontrol>>16);
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oursize = (oursize > 1) ? oursize : 1;
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oursize *= (dma->n_blockcontrol&0xffff);
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(*dma->fn_read)( machine(), n_address, oursize );
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dma_finished( index );
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}
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else if( dma->n_channelcontrol == 0x01000200 &&
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dma->fn_read != NULL )
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{
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verboselog( machine(), 1, "dma %d read block %08x %08x\n", index, n_address, n_size );
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(*dma->fn_read)( machine(), n_address, n_size );
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if( index == 1 )
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{
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dma_start_timer( index, 26000 );
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}
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else
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{
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dma_finished( index );
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}
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}
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else if( dma->n_channelcontrol == 0x01000201 &&
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dma->fn_write != NULL )
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{
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verboselog( machine(), 1, "dma %d write block %08x %08x\n", index, n_address, n_size );
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(*dma->fn_write)( machine(), n_address, n_size );
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dma_finished( index );
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}
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else if( dma->n_channelcontrol == 0x11050100 &&
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dma->fn_write != NULL )
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{
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/* todo: check this is a write not a read... */
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verboselog( machine(), 1, "dma %d write block %08x %08x\n", index, n_address, n_size );
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(*dma->fn_write)( machine(), n_address, n_size );
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dma_finished( index );
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}
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else if( dma->n_channelcontrol == 0x11150100 &&
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dma->fn_write != NULL )
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{
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/* todo: check this is a write not a read... */
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verboselog( machine(), 1, "dma %d write block %08x %08x\n", index, n_address, n_size );
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(*dma->fn_write)( machine(), n_address, n_size );
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dma_finished( index );
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}
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else if( dma->n_channelcontrol == 0x01000401 &&
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index == 2 &&
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dma->fn_write != NULL )
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{
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verboselog( machine(), 1, "dma %d write linked list %08x\n",
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index, dma->n_base );
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dma_finished( index );
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}
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else if( dma->n_channelcontrol == 0x11000002 &&
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index == 6 )
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{
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verboselog( machine(), 1, "dma 6 reverse clear %08x %08x\n",
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dma->n_base, dma->n_blockcontrol );
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if( n_size > 0 )
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{
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n_size--;
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while( n_size > 0 )
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{
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n_nextaddress = ( n_address - 4 ) & 0xffffff;
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p_n_psxram[ n_address / 4 ] = n_nextaddress;
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n_address = n_nextaddress;
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n_size--;
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}
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p_n_psxram[ n_address / 4 ] = 0xffffff;
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}
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dma_start_timer( index, 2150 );
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}
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else
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{
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verboselog( machine(), 1, "dma %d unknown mode %08x\n", index, dma->n_channelcontrol );
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}
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}
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else if( dma->n_channelcontrol != 0 )
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{
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verboselog( machine(), 1, "psx_dma_w( %04x, %08x, %08x ) channel not enabled\n", offset, dma->n_channelcontrol, mem_mask );
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}
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break;
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default:
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verboselog( machine(), 1, "psx_dma_w( %04x, %08x, %08x ) Unknown dma channel register\n", offset, data, mem_mask );
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break;
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}
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}
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else
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{
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switch( offset % 4 )
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{
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case 0x0:
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verboselog( machine(), 1, "psx_dma_w( %04x, %08x, %08x ) dpcp\n", offset, data, mem_mask );
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n_dpcp = ( n_dpcp & ~mem_mask ) | data;
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break;
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case 0x1:
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n_dicr = ( n_dicr & ( 0x80000000 | ~mem_mask ) ) |
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( n_dicr & ~data & 0x7f000000 & mem_mask ) |
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( data & 0x00ffffff & mem_mask );
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if( ( n_dicr & 0x80000000 ) != 0 && ( n_dicr & 0x7f000000 ) == 0 )
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{
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verboselog( machine(), 2, "dma interrupt cleared\n" );
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n_dicr &= ~0x80000000;
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}
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verboselog( machine(), 1, "psx_dma_w( %04x, %08x, %08x ) dicr -> %08x\n", offset, data, mem_mask, n_dicr );
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break;
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default:
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verboselog( machine(), 0, "psx_dma_w( %04x, %08x, %08x ) Unknown dma control register\n", offset, data, mem_mask );
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break;
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}
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}
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}
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READ32_MEMBER( psxdma_device::read )
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{
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int index = offset / 4;
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psx_dma_channel *dma = &channel[ index ];
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if( index < 7 )
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{
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switch( offset % 4 )
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{
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case 0:
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verboselog( machine(), 1, "psx_dma_r dmabase[ %d ] ( %08x )\n", index, dma->n_base );
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return dma->n_base;
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case 1:
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verboselog( machine(), 1, "psx_dma_r dmablockcontrol[ %d ] ( %08x )\n", index, dma->n_blockcontrol );
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return dma->n_blockcontrol;
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case 2:
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verboselog( machine(), 1, "psx_dma_r dmachannelcontrol[ %d ] ( %08x )\n", index, dma->n_channelcontrol );
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return dma->n_channelcontrol;
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default:
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verboselog( machine(), 0, "psx_dma_r( %08x, %08x ) Unknown dma channel register\n", offset, mem_mask );
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break;
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}
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}
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else
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{
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switch( offset % 4 )
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{
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case 0x0:
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verboselog( machine(), 1, "psx_dma_r dpcp ( %08x )\n", n_dpcp );
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return n_dpcp;
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case 0x1:
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verboselog( machine(), 1, "psx_dma_r dicr ( %08x )\n", n_dicr );
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return n_dicr;
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default:
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verboselog( machine(), 0, "psx_dma_r( %08x, %08x ) Unknown dma control register\n", offset, mem_mask );
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break;
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}
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}
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return 0;
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}
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