smf- d485e8ed3c Fixed the SR masks for MTC0. ... Added ability to test the instruction/data cache ram. The scratchpad and BIU register are now handled internally to the CPU. All writes are performed with masks. SWL/SWR used to be implemented with two writes ( one byte and one word ) when writing three bytes, now it only ever performs one. Byte and Word writes use masks as they leave the rest of the register on the bus, which can be picked up by larger registers. The read/write functions to use are cached when the SR bits are updated, as are the bad address masks. Added coprocessor 1 & 3 support, though they don't do anything useful. All loads now go through the delay pipeline, a lwl/lwr will grab the value out of the pipeline if it's updating the same register. Added undocumented behaviour of BLEZ/BGTZ. The comparison for zero can be changed by specifying an alternate register in the RT field ( the documentation says you should always use register 0 ). Restricted to 16 COP0 registers & generate an exception if any of the 5 for the MMU are used. Added BCF/BCT instructions, although I have found no conditions that affect them yet. Generates an exception if any MMU instructions are executed. Sets the CE instruction for all exceptions, not just those involving a coprocessor. The bits of the opcode that specify the coprocessor are grabbed no matter what the instruction. Added TAR register and BT bit in SR. When an exception occurs during a branch, BT determines whether it was taken or not. The TAR register gets set to the destination of the branch. Fixed the BD bit when you are in a branch delay slot and you didn't take the branch, this shows up in the pipeline as !pc. Fixed branches within a branch delay slot. Multiply & divide instructions can be aborted if you write to HI/LO before reading the result. Added data breakpoints, you don't appear to be able to set breakpoints on any of the addresses internal to the CPU. Multiply/divide/GTE instructions can execute when an exception is taken, although the EPC indicates that it hasn't. The BIOS avoids rerunning GTE instructions as they are destructive, so you have to make sure they run. Added bus error handling, PSXCPU is limited to 8mb of ram & any access outside this range will trigger an exception. I believe this is to be an internal limit. Added CXD8611R as a specific CPU type, System 12 appears to allow more than 8mb of ram & it's possible that this is different. Mapped out all instructions to either generate an exception or ignore bits. Updated the disassembler to match the decoding. Fixed disassembling of branch instructions in a branch delay slot. Lui checks for a ori/addiu following and will show you the result. Added step over/out support. Fixed standalone disassembler.		2008-04-06 16:42:10 +00:00
docs	Cleanups on the doc files.	2008-02-13 16:55:14 +00:00
src	Fixed the SR masks for MTC0.	2008-04-06 16:42:10 +00:00
.gitattributes	Seibu COP stuff - just moving things around renaming them, comparing Legionnaire with Raiden 2 etc. No functional improvements just yet.	2008-04-05 13:08:11 +00:00
makefile	From: Marc Sandusky	2008-04-02 08:28:58 +00:00