mirror of
https://github.com/holub/mame
synced 2025-05-29 00:53:09 +03:00
58d832602b
* Fix build of ldplayer on OS X. Since the CUSTOM sound module no longer exists, I arbitrarily changed it to WAVE, as ar gets upset if it has no input files. I also removed the -all_load flag for ldplayer from the main makefile as it upsets the linker on OS X. * Fix build for PPC64 Linux. (This slightly messes up static branch prediction hints on OS X and AIX, but OS X for PPC64 is dead, and no- one builds MAME for AIX, and it will still build, anyway.) * Paramaterise the arguments to check for NULL in the ATTR_NONNULL macro rather than just checking the first argument. This requires compiler support for C99 variadic macros (MSVC2005 and GCC4 have this AFAIK). Vas
474 lines
13 KiB
C
474 lines
13 KiB
C
/***************************************************************************
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eigccppc.h
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PowerPC (32 and 64-bit) inline implementations for GCC compilers. This
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code is automatically included if appropriate by eminline.h.
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Copyright Nicola Salmoria and the MAME Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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***************************************************************************/
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#ifndef __EIGCCPPC__
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#define __EIGCCPPC__
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/***************************************************************************
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INLINE MATH FUNCTIONS
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***************************************************************************/
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/*-------------------------------------------------
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mul_32x32 - perform a signed 32 bit x 32 bit
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multiply and return the full 64 bit result
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-------------------------------------------------*/
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/* GCC can do a good job of this. */
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/*-------------------------------------------------
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mulu_32x32 - perform an unsigned 32 bit x
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32 bit multiply and return the full 64 bit
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result
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-------------------------------------------------*/
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/* GCC can do a good job of this */
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/*-------------------------------------------------
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mul_32x32_hi - perform a signed 32 bit x 32 bit
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multiply and return the upper 32 bits of the
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result
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-------------------------------------------------*/
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#define mul_32x32_hi _mul_32x32_hi
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INLINE INT32 ATTR_CONST ATTR_FORCE_INLINE
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_mul_32x32_hi(INT32 val1, INT32 val2)
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{
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register INT32 result;
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__asm__ (
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" mulhw %[result], %[val1], %[val2] \n"
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: [result] "=r" (result)
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: [val1] "%r" (val1)
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, [val2] "r" (val2)
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);
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return result;
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}
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/*-------------------------------------------------
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mulu_32x32_hi - perform an unsigned 32 bit x
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32 bit multiply and return the upper 32 bits
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of the result
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-------------------------------------------------*/
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#define mulu_32x32_hi _mulu_32x32_hi
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INLINE UINT32 ATTR_CONST ATTR_FORCE_INLINE
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_mulu_32x32_hi(UINT32 val1, UINT32 val2)
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{
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register UINT32 result;
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__asm__ (
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" mulhwu %[result], %[val1], %[val2] \n"
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: [result] "=r" (result)
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: [val1] "%r" (val1)
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, [val2] "r" (val2)
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);
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return result;
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}
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/*-------------------------------------------------
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mul_32x32_shift - perform a signed 32 bit x
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32 bit multiply and shift the result by the
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given number of bits before truncating the
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result to 32 bits
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-------------------------------------------------*/
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#if !defined(__ppc64__) && !defined(__PPC64__) && !defined(_ARCH_PPC64)
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#define mul_32x32_shift _mul_32x32_shift
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INLINE INT32 ATTR_CONST ATTR_FORCE_INLINE
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_mul_32x32_shift(INT32 val1, INT32 val2, UINT8 shift)
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{
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register INT32 result;
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/* Valid for (0 <= shift <= 32) */
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__asm__ (
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" mullw %[result], %[val1], %[val2] \n"
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" mulhw %[val1], %[val1], %[val2] \n"
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" srw %[result], %[result], %[shift] \n"
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" subfic %[shift], %[shift], 0x20 \n"
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" slw %[val1], %[val1], %[shift] \n"
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" or %[result], %[result], %[val1] \n"
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: [result] "=&r" (result)
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, [shift] "+r" (shift)
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, [val1] "+r" (val1)
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: [val2] "r" (val2)
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: "xer"
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);
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return result;
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}
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#endif
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/*-------------------------------------------------
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mulu_32x32_shift - perform an unsigned 32 bit x
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32 bit multiply and shift the result by the
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given number of bits before truncating the
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result to 32 bits
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-------------------------------------------------*/
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#if !defined(__ppc64__) && !defined(__PPC64__) && !defined(_ARCH_PPC64)
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#define mulu_32x32_shift _mulu_32x32_shift
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INLINE UINT32 ATTR_CONST ATTR_FORCE_INLINE
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_mulu_32x32_shift(UINT32 val1, UINT32 val2, UINT8 shift)
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{
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register UINT32 result;
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/* Valid for (0 <= shift <= 32) */
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__asm__ (
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" mullw %[result], %[val1], %[val2] \n"
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" mulhwu %[val1], %[val1], %[val2] \n"
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" srw %[result], %[result], %[shift] \n"
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" subfic %[shift], %[shift], 0x20 \n"
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" slw %[val1], %[val1], %[shift] \n"
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" or %[result], %[result], %[val1] \n"
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: [result] "=&r" (result)
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, [shift] "+r" (shift)
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, [val1] "+r" (val1)
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: [val2] "r" (val2)
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: "xer"
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);
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return result;
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}
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#endif
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/*-------------------------------------------------
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div_64x32 - perform a signed 64 bit x 32 bit
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divide and return the 32 bit quotient
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-------------------------------------------------*/
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/* TBD */
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/*-------------------------------------------------
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divu_64x32 - perform an unsigned 64 bit x 32 bit
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divide and return the 32 bit quotient
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-------------------------------------------------*/
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/* TBD */
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/*-------------------------------------------------
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div_64x32_rem - perform a signed 64 bit x 32
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bit divide and return the 32 bit quotient and
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32 bit remainder
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-------------------------------------------------*/
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/* TBD */
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/*-------------------------------------------------
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divu_64x32_rem - perform an unsigned 64 bit x
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32 bit divide and return the 32 bit quotient
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and 32 bit remainder
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-------------------------------------------------*/
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/* TBD */
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/*-------------------------------------------------
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div_32x32_shift - perform a signed divide of
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two 32 bit values, shifting the first before
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division, and returning the 32 bit quotient
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-------------------------------------------------*/
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/* TBD */
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/*-------------------------------------------------
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divu_32x32_shift - perform an unsigned divide of
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two 32 bit values, shifting the first before
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division, and returning the 32 bit quotient
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-------------------------------------------------*/
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/* TBD */
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/*-------------------------------------------------
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mod_64x32 - perform a signed 64 bit x 32 bit
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divide and return the 32 bit remainder
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-------------------------------------------------*/
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/* TBD */
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/*-------------------------------------------------
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modu_64x32 - perform an unsigned 64 bit x 32 bit
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divide and return the 32 bit remainder
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-------------------------------------------------*/
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/* TBD */
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/*-------------------------------------------------
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recip_approx - compute an approximate floating
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point reciprocal
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-------------------------------------------------*/
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#define recip_approx _recip_approx
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INLINE float ATTR_CONST ATTR_FORCE_INLINE
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_recip_approx(float value)
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{
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register float result;
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__asm__ (
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" fres %[result], %[value] \n"
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: [result] "=f" (result)
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: [value] "f" (value)
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);
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return result;
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}
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/***************************************************************************
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INLINE BIT MANIPULATION FUNCTIONS
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***************************************************************************/
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/*-------------------------------------------------
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count_leading_zeros - return the number of
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leading zero bits in a 32-bit value
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-------------------------------------------------*/
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#define count_leading_zeros _count_leading_zeros
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INLINE UINT8 ATTR_CONST ATTR_FORCE_INLINE
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_count_leading_zeros(UINT32 value)
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{
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register UINT32 result;
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__asm__ (
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" cntlzw %[result], %[value] \n"
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: [result] "=r" (result) /* result can be in any register */
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: [value] "r" (value) /* 'value' can be in any register */
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);
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return result;
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}
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/*-------------------------------------------------
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count_leading_ones - return the number of
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leading one bits in a 32-bit value
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-------------------------------------------------*/
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#define count_leading_ones _count_leading_ones
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INLINE UINT8 ATTR_CONST ATTR_FORCE_INLINE
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_count_leading_ones(UINT32 value)
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{
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register UINT32 result;
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__asm__ (
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" not %[result], %[value] \n"
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" cntlzw %[result], %[result] \n"
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: [result] "=r" (result) /* result can be in any register */
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: [value] "r" (value) /* 'value' can be in any register */
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);
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return result;
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}
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/***************************************************************************
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INLINE SYNCHRONIZATION FUNCTIONS
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***************************************************************************/
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/*-------------------------------------------------
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compare_exchange32 - compare the 'compare'
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value against the memory at 'ptr'; if equal,
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swap in the 'exchange' value. Regardless,
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return the previous value at 'ptr'.
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-------------------------------------------------*/
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#define compare_exchange32 _compare_exchange32
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INLINE INT32 ATTR_NONNULL(1) ATTR_FORCE_INLINE
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_compare_exchange32(INT32 volatile *ptr, INT32 compare, INT32 exchange)
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{
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register INT32 result;
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__asm__ __volatile__ (
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"1: lwarx %[result], 0, %[ptr] \n"
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" cmpw %[compare], %[result] \n"
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" bne 2f \n"
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" sync \n"
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" stwcx. %[exchange], 0, %[ptr] \n"
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" bne- 1b \n"
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"2: "
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&r" (result)
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: [ptr] "r" (ptr)
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, [exchange] "r" (exchange)
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, [compare] "r" (compare)
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: "cr0"
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);
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return result;
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}
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/*-------------------------------------------------
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compare_exchange64 - compare the 'compare'
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value against the memory at 'ptr'; if equal,
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swap in the 'exchange' value. Regardless,
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return the previous value at 'ptr'.
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-------------------------------------------------*/
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#if defined(__ppc64__) || defined(__PPC64__)
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#define compare_exchange64 _compare_exchange64
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INLINE INT64 ATTR_NONNULL(1) ATTR_FORCE_INLINE
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_compare_exchange64(INT64 volatile *ptr, INT64 compare, INT64 exchange)
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{
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register INT64 result;
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__asm__ __volatile__ (
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"1: ldarx %[result], 0, %[ptr] \n"
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" cmpd %[compare], %[result] \n"
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" bne 2f \n"
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" stdcx. %[exchange], 0, %[ptr] \n"
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" bne- 1b \n"
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"2: "
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&r" (result)
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: [ptr] "r" (ptr)
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, [exchange] "r" (exchange)
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, [compare] "r" (compare)
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: "cr0"
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);
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return result;
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}
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#endif
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/*-------------------------------------------------
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atomic_exchange32 - atomically exchange the
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exchange value with the memory at 'ptr',
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returning the original value.
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-------------------------------------------------*/
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#define atomic_exchange32 _atomic_exchange32
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INLINE INT32 ATTR_NONNULL(1) ATTR_FORCE_INLINE
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_atomic_exchange32(INT32 volatile *ptr, INT32 exchange)
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{
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register INT32 result;
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__asm__ __volatile__ (
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"1: lwarx %[result], 0, %[ptr] \n"
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" sync \n"
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" stwcx. %[exchange], 0, %[ptr] \n"
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" bne- 1b \n"
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&r" (result)
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: [ptr] "r" (ptr)
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, [exchange] "r" (exchange)
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: "cr0"
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);
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return result;
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}
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/*-------------------------------------------------
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atomic_add32 - atomically add the delta value
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to the memory at 'ptr', returning the final
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result.
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-------------------------------------------------*/
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#define atomic_add32 _atomic_add32
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INLINE INT32 ATTR_NONNULL(1) ATTR_FORCE_INLINE
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_atomic_add32(INT32 volatile *ptr, INT32 delta)
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{
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register INT32 result;
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__asm__ __volatile__ (
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"1: lwarx %[result], 0, %[ptr] \n"
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" add %[result], %[result], %[delta] \n"
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" sync \n"
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" stwcx. %[result], 0, %[ptr] \n"
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" bne- 1b \n"
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&b" (result)
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: [ptr] "r" (ptr)
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, [delta] "r" (delta)
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: "cr0"
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);
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return result;
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}
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/*-------------------------------------------------
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atomic_increment32 - atomically increment the
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32-bit value in memory at 'ptr', returning the
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final result.
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-------------------------------------------------*/
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#define atomic_increment32 _atomic_increment32
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INLINE INT32 ATTR_NONNULL(1) ATTR_FORCE_INLINE
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_atomic_increment32(INT32 volatile *ptr)
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{
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register INT32 result;
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__asm__ __volatile__ (
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"1: lwarx %[result], 0, %[ptr] \n"
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" addi %[result], %[result], 1 \n"
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" sync \n"
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" stwcx. %[result], 0, %[ptr] \n"
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" bne- 1b \n"
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&b" (result)
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: [ptr] "r" (ptr)
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: "cr0"
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);
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return result;
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}
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/*-------------------------------------------------
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atomic_decrement32 - atomically decrement the
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32-bit value in memory at 'ptr', returning the
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final result.
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-------------------------------------------------*/
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#define atomic_decrement32 _atomic_decrement32
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INLINE INT32 ATTR_NONNULL(1) ATTR_FORCE_INLINE
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_atomic_decrement32(INT32 volatile *ptr)
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{
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register INT32 result;
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__asm__ __volatile__ (
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"1: lwarx %[result], 0, %[ptr] \n"
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" addi %[result], %[result], -1 \n"
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" sync \n"
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" stwcx. %[result], 0, %[ptr] \n"
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" bne- 1b \n"
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: [dummy] "+m" (*ptr) /* Lets GCC know that *ptr will be read/written in case it's not marked volatile */
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, [result] "=&b" (result)
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: [ptr] "r" (ptr)
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: "cr0"
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);
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return result;
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}
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#endif /* __EIGCCPPC__ */
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