mirror of
https://github.com/holub/mame
synced 2025-04-16 05:24:54 +03:00
e6180e3510
- Add more or less complete implementations of sis630_host, sis950_lpc, sis630_gui, sis5513_ide, sis7001_usb, sis7018_audio, sis900_eth devices; - Removed gamecstl.cpp in favour to the new sis630.cpp driver; - i386.cpp: enable CMOV feature for Pentium III and 4; - i386.cpp: add PSN stub feature for Pentium III; New machines marked as NOT_WORKING ---------------------------------- Shuttle MS-11 [Angelo Salese, archive.org]
90 lines
2.8 KiB
C++
90 lines
2.8 KiB
C++
// license: BSD-3-Clause
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// copyright-holders: Angelo Salese
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#ifndef MAME_MACHINE_SIS5513_IDE_H
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#define MAME_MACHINE_SIS5513_IDE_H
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#pragma once
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#include "pci.h"
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#include "machine/pci-ide.h"
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class sis5513_ide_device : public pci_device
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{
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public:
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template <typename T> sis5513_ide_device(
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const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock,
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T &&host_tag, uint32_t bmspace = AS_PROGRAM
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) : sis5513_ide_device(mconfig, tag, owner, clock)
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{
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// IDE controller with 0xd0 as programming i/f "ATA Host Adapters standard"
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// pclass bits 1-3 are actually 1 when controller is in native mode
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// pclass bits 0-2 can be r/w from $09
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set_ids(0x10395513, 0xd0, 0x010180, 0x00);
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m_bus_master_space.set_tag(host_tag, bmspace);
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}
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sis5513_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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auto irq_pri() { return m_irq_pri_callback.bind(); }
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auto irq_sec() { return m_irq_sec_callback.bind(); }
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protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_add_mconfig(machine_config &config) override;
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// virtual void reset_all_mappings() override;
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// virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
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// uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
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virtual void config_map(address_map &map) override;
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void ide1_command_map(address_map &map);
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void ide1_control_map(address_map &map);
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void ide2_command_map(address_map &map);
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void ide2_control_map(address_map &map);
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void bus_master_ide_control_map(address_map &map);
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private:
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required_device<bus_master_ide_controller_device> m_ide1;
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required_device<bus_master_ide_controller_device> m_ide2;
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devcb_write_line m_irq_pri_callback;
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devcb_write_line m_irq_sec_callback;
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required_address_space m_bus_master_space;
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bool ide1_mode();
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bool ide2_mode();
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u32 bar_r(offs_t offset);
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void bar_w(offs_t offset, u32 data);
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u32 m_bar[5]{};
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void prog_if_w(u8 data);
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u8 ide_ctrl_0_r();
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void ide_ctrl_0_w(u8 data);
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u8 ide_misc_ctrl_r();
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void ide_misc_ctrl_w(u8 data);
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u8 m_ide_ctrl0 = 0;
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u8 m_ide_misc = 0;
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uint32_t ide1_read32_cs0_r(offs_t offset, uint32_t mem_mask = ~0);
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void ide1_write32_cs0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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uint32_t ide2_read32_cs0_r(offs_t offset, uint32_t mem_mask = ~0);
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void ide2_write32_cs0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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uint8_t ide1_read_cs1_r();
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void ide1_write_cs1_w(uint8_t data);
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uint8_t ide2_read_cs1_r();
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void ide2_write_cs1_w(uint8_t data);
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// void compatible_io_map(address_map &map);
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void flush_ide_mode();
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u8 unmap_log_r(offs_t offset);
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void unmap_log_w(offs_t offset, u8 data);
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};
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DECLARE_DEVICE_TYPE(SIS5513_IDE, sis5513_ide_device)
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#endif
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