mirror of
https://github.com/holub/mame
synced 2025-05-31 10:01:51 +03:00
384 lines
12 KiB
C++
384 lines
12 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:Miodrag Milanovic
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/***************************************************************************
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ISA bus device
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8 bit ISA bus connector:
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A1 O I/O CH CHK B1 GND
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A2 IO D7 B2 I RESET
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A3 IO D6 B3 +5V
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A4 IO D5 B4 O IRQ2
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A5 IO D4 B5 -5V
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A6 IO D3 B6 O DRQ2
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A7 IO D2 B7 -12V
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A8 IO D1 B8 O /NOWS
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A9 IO D0 B9 +12V
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A10 O I/O CH RDY B10 GND
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A11 I AEN B11 I /SMEMW
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A12 IO A19 B12 I /SMEMR
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A13 IO A18 B13 I /IOW
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A14 IO A17 B14 I /IOR
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A15 IO A16 B15 I /DACK3
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A16 IO A15 B16 O DRQ3
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A17 IO A14 B17 I /DACK1
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A18 IO A13 B18 O DRQ1
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A19 IO A12 B19 IO /REFRESH
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A20 IO A11 B20 I CLOCK
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A21 IO A10 B21 O IRQ7
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A22 IO A9 B22 O IRQ6
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A23 IO A8 B23 O IRQ5
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A24 IO A7 B24 O IRQ4
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A25 IO A6 B25 O IRQ3
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A26 IO A5 B26 I /DACK2
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A27 IO A4 B27 I T/C
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A28 IO A3 B28 I ALE
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A29 IO A2 B29 +5V
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A30 IO A1 B30 I OSC
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A31 IO A0 B31 GND
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16 bit ISA bus extension
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C1 I SBHE D1 I /MEM CS 16
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C2 IO A23 D2 I /I/O CS 16
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C3 IO A22 D3 O IRQ10
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C4 IO A21 D4 O IRQ11
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C5 IO A20 D5 O IRQ12
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C6 IO A19 D6 O IRQ15
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C7 IO A18 D7 O IRQ14
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C8 IO A17 D8 I /DACK0
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C9 I /MEMR D9 O DRQ0
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C10 I /MEMW D10 I /DACK5
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C11 IO D8 D11 O DRQ5
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C12 IO D9 D12 I /DACK6
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C13 IO D10 D13 O DRQ6
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C14 IO D11 D14 I /DACK7
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C15 IO D12 D15 O DRQ7
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C16 IO D13 D16 +5V
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C17 IO D14 D17 I MASTER
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C18 IO D15 D18 GND
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***************************************************************************/
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#ifndef MAME_BUS_ISA_ISA_H
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#define MAME_BUS_ISA_ISA_H
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#pragma once
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#include <forward_list>
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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class isa8_device;
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class isa8_slot_device : public device_t, public device_slot_interface
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{
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public:
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// construction/destruction
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template <typename T, typename U>
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isa8_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&isa_tag, U &&opts, const char *dflt, bool fixed)
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: isa8_slot_device(mconfig, tag, owner, clock)
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{
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option_reset();
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opts(*this);
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set_default_option(dflt);
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set_fixed(fixed);
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m_isa_bus.set_tag(std::forward<T>(isa_tag));
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}
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isa8_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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isa8_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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// device-level overrides
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virtual void device_start() override;
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// configuration
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required_device<device_t> m_isa_bus;
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};
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// device type definition
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DECLARE_DEVICE_TYPE(ISA8_SLOT, isa8_slot_device)
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class device_isa8_card_interface;
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// ======================> isa8_device
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class isa8_device : public device_t,
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public device_memory_interface
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{
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public:
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enum
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{
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AS_ISA_MEM = 0,
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AS_ISA_IO = 1,
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AS_ISA_MEMALT = 2,
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AS_ISA_IOALT = 3
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};
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// construction/destruction
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isa8_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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// inline configuration
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template <typename T> void set_cputag(T &&tag) { m_maincpu.set_tag(std::forward<T>(tag)); }
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auto iochck_callback() { return m_write_iochck.bind(); }
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auto irq2_callback() { return m_out_irq2_cb.bind(); }
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auto irq3_callback() { return m_out_irq3_cb.bind(); }
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auto irq4_callback() { return m_out_irq4_cb.bind(); }
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auto irq5_callback() { return m_out_irq5_cb.bind(); }
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auto irq6_callback() { return m_out_irq6_cb.bind(); }
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auto irq7_callback() { return m_out_irq7_cb.bind(); }
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auto drq1_callback() { return m_out_drq1_cb.bind(); }
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auto drq2_callback() { return m_out_drq2_cb.bind(); }
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auto drq3_callback() { return m_out_drq3_cb.bind(); }
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// include this in a driver to have ISA allocate its own address spaces (e.g. non-x86)
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void set_custom_spaces() { m_allocspaces = true; }
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// for ISA8, put the 8-bit configs in the primary slots and the 16-bit configs in the secondary
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virtual space_config_vector memory_space_config() const override;
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template<typename R, typename W> void install_device(offs_t start, offs_t end, R rhandler, W whandler);
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template<typename T> void install_device(offs_t addrstart, offs_t addrend, T &device, void (T::*map)(class address_map &map), uint64_t unitmask = ~u64(0))
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{
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m_iospace->install_device(addrstart, addrend, device, map, unitmask);
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}
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void install_bank(offs_t start, offs_t end, const char *tag, uint8_t *data);
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void install_rom(device_t *dev, offs_t start, offs_t end, const char *tag, const char *region);
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template<typename R, typename W> void install_memory(offs_t start, offs_t end, R rhandler, W whandler);
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void unmap_device(offs_t start, offs_t end) const { m_iospace->unmap_readwrite(start, end); }
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void unmap_bank(offs_t start, offs_t end);
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void unmap_rom(offs_t start, offs_t end);
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bool is_option_rom_space_available(offs_t start, int size);
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// FIXME: shouldn't need to expose this
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address_space &memspace() const { return m_maincpu->space(AS_PROGRAM); }
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DECLARE_WRITE_LINE_MEMBER( irq2_w );
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DECLARE_WRITE_LINE_MEMBER( irq3_w );
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DECLARE_WRITE_LINE_MEMBER( irq4_w );
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DECLARE_WRITE_LINE_MEMBER( irq5_w );
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DECLARE_WRITE_LINE_MEMBER( irq6_w );
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DECLARE_WRITE_LINE_MEMBER( irq7_w );
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DECLARE_WRITE_LINE_MEMBER( drq1_w );
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DECLARE_WRITE_LINE_MEMBER( drq2_w );
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DECLARE_WRITE_LINE_MEMBER( drq3_w );
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// 8 bit accessors for ISA-defined address spaces
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DECLARE_READ8_MEMBER(mem_r);
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DECLARE_WRITE8_MEMBER(mem_w);
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DECLARE_READ8_MEMBER(io_r);
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DECLARE_WRITE8_MEMBER(io_w);
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uint8_t dack_r(int line);
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void dack_w(int line,uint8_t data);
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void eop_w(int channels, int state);
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void nmi();
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void set_nmi_state(bool enabled) { m_nmi_enabled = enabled; }
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virtual void set_dma_channel(uint8_t channel, device_isa8_card_interface *dev, bool do_eop);
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void add_slot(const char *tag);
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void add_slot(device_slot_interface *slot);
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virtual void remap(int space_id, offs_t start, offs_t end);
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const address_space_config m_mem_config, m_io_config, m_mem16_config, m_io16_config;
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protected:
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isa8_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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template<typename R, typename W> void install_space(int spacenum, offs_t start, offs_t end, R rhandler, W whandler);
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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// internal state
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required_device<cpu_device> m_maincpu;
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// address spaces
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address_space *m_iospace, *m_memspace;
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int m_iowidth, m_memwidth;
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bool m_allocspaces;
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devcb_write_line m_out_irq2_cb;
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devcb_write_line m_out_irq3_cb;
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devcb_write_line m_out_irq4_cb;
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devcb_write_line m_out_irq5_cb;
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devcb_write_line m_out_irq6_cb;
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devcb_write_line m_out_irq7_cb;
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devcb_write_line m_out_drq1_cb;
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devcb_write_line m_out_drq2_cb;
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devcb_write_line m_out_drq3_cb;
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device_isa8_card_interface *m_dma_device[8];
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bool m_dma_eop[8];
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bool m_nmi_enabled;
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std::forward_list<device_slot_interface *> m_slot_list;
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private:
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devcb_write_line m_write_iochck;
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};
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// device type definition
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DECLARE_DEVICE_TYPE(ISA8, isa8_device)
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// ======================> device_isa8_card_interface
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// class representing interface-specific live isa8 card
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class device_isa8_card_interface : public device_slot_card_interface
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{
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friend class isa8_device;
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template <class ElementType> friend class simple_list;
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public:
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// construction/destruction
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virtual ~device_isa8_card_interface();
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device_isa8_card_interface *next() const { return m_next; }
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void set_isa_device();
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// configuration access
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virtual uint8_t dack_r(int line);
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virtual void dack_w(int line,uint8_t data);
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virtual void eop_w(int state);
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virtual void remap(int space_id, offs_t start, offs_t end) {}
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// inline configuration
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void set_isabus(device_t *isa_device) { m_isa_dev = isa_device; }
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public:
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device_isa8_card_interface(const machine_config &mconfig, device_t &device);
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isa8_device *m_isa;
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device_t *m_isa_dev;
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private:
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device_isa8_card_interface *m_next;
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};
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class isa16_device;
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class isa16_slot_device : public isa8_slot_device
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{
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public:
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// construction/destruction
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template <typename T, typename U>
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isa16_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&isa_tag, U &&opts, const char *dflt, bool fixed)
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: isa16_slot_device(mconfig, tag, owner, clock)
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{
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option_reset();
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opts(*this);
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set_default_option(dflt);
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set_fixed(fixed);
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m_isa_bus.set_tag(std::forward<T>(isa_tag));
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}
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isa16_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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protected:
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// device-level overrides
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virtual void device_start() override;
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};
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// device type definition
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DECLARE_DEVICE_TYPE(ISA16_SLOT, isa16_slot_device)
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// ======================> isa16_device
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class isa16_device : public isa8_device
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{
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public:
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// construction/destruction
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isa16_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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auto irq10_callback() { return m_out_irq10_cb.bind(); }
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auto irq11_callback() { return m_out_irq11_cb.bind(); }
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auto irq12_callback() { return m_out_irq12_cb.bind(); }
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auto irq14_callback() { return m_out_irq14_cb.bind(); }
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auto irq15_callback() { return m_out_irq15_cb.bind(); }
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auto drq0_callback() { return m_out_drq0_cb.bind(); }
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auto drq5_callback() { return m_out_drq5_cb.bind(); }
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auto drq6_callback() { return m_out_drq6_cb.bind(); }
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auto drq7_callback() { return m_out_drq7_cb.bind(); }
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void install16_device(offs_t start, offs_t end, read16_delegate rhandler, write16_delegate whandler);
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// for ISA16, put the 16-bit configs in the primary slots and the 8-bit configs in the secondary
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virtual space_config_vector memory_space_config() const override;
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DECLARE_WRITE_LINE_MEMBER( irq10_w );
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DECLARE_WRITE_LINE_MEMBER( irq11_w );
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DECLARE_WRITE_LINE_MEMBER( irq12_w );
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DECLARE_WRITE_LINE_MEMBER( irq14_w );
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DECLARE_WRITE_LINE_MEMBER( irq15_w );
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DECLARE_WRITE_LINE_MEMBER( drq0_w );
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DECLARE_WRITE_LINE_MEMBER( drq5_w );
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DECLARE_WRITE_LINE_MEMBER( drq6_w );
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DECLARE_WRITE_LINE_MEMBER( drq7_w );
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uint16_t dack16_r(int line);
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void dack16_w(int line,uint16_t data);
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virtual void remap(int space_id, offs_t start, offs_t end) override;
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// 16 bit accessors for ISA-defined address spaces
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DECLARE_READ16_MEMBER(mem16_r);
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DECLARE_WRITE16_MEMBER(mem16_w);
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DECLARE_READ16_MEMBER(io16_r);
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DECLARE_WRITE16_MEMBER(io16_w);
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// byte-swapped versions of 16-bit accessors
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DECLARE_READ16_MEMBER(mem16_swap_r);
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DECLARE_WRITE16_MEMBER(mem16_swap_w);
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DECLARE_READ16_MEMBER(io16_swap_r);
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DECLARE_WRITE16_MEMBER(io16_swap_w);
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protected:
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// device-level overrides
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virtual void device_start() override;
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private:
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// internal state
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devcb_write_line m_out_irq10_cb;
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devcb_write_line m_out_irq11_cb;
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devcb_write_line m_out_irq12_cb;
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devcb_write_line m_out_irq14_cb;
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devcb_write_line m_out_irq15_cb;
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devcb_write_line m_out_drq0_cb;
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devcb_write_line m_out_drq5_cb;
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devcb_write_line m_out_drq6_cb;
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devcb_write_line m_out_drq7_cb;
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};
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// device type definition
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DECLARE_DEVICE_TYPE(ISA16, isa16_device)
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// ======================> device_isa16_card_interface
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// class representing interface-specific live isa16 card
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class device_isa16_card_interface : public device_isa8_card_interface
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{
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friend class isa16_device;
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public:
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// construction/destruction
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virtual ~device_isa16_card_interface();
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virtual uint16_t dack16_r(int line);
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virtual void dack16_w(int line,uint16_t data);
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void set_isa_device();
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protected:
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device_isa16_card_interface(const machine_config &mconfig, device_t &device);
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isa16_device *m_isa;
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};
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#endif // MAME_BUS_ISA_ISA_H
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