mirror of
https://github.com/holub/mame
synced 2025-10-04 16:34:53 +03:00
ed0207f126
and paths consistently for devices, I/O ports, memory
regions, memory banks, and memory shares. [Aaron Giles]
NOTE: there are likely regressions lurking here, mostly
due to devices not being properly found. I have temporarily
added more logging to -verbose to help understand what's
going on. Please let me know ASAP if anything that is being
actively worked on got broken.
As before, the driver device is the root device and all
other devices are owned by it. Previously all devices
were kept in a single master list, and the hierarchy was
purely logical. With this change, each device owns its
own list of subdevices, and the hierarchy is explicitly
manifest. This means when a device is removed, all of its
subdevices are automatically removed as well.
A side effect of this is that walking the device list is
no longer simple. To address this, a new set of iterator
classes is provided, which walks the device tree in a depth
first manner. There is a general device_iterator class for
walking all devices, plus templates for a device_type_iterator
and a device_interface_iterator which are used to build
iterators for identifying only devices of a given type or
with a given interface. Typedefs for commonly-used cases
(e.g., screen_device_iterator, memory_interface_iterator)
are provided. Iterators can also provide counts, and can
perform indexed lookups.
All device name lookups are now done relative to another
device. The maching_config and running_machine classes now
have a root_device() method to get the root of the hierarchy.
The existing machine->device("name") is now equivalent to
machine->root_device().subdevice("name").
A proper and normalized device path structure is now
supported. Device names that start with a colon are
treated as absolute paths from the root device. Device
names can also use a caret (^) to refer to the owning
device. Querying the device's tag() returns the device's
full path from the root. A new method basetag() returns
just the final tag.
The new pathing system is built on top of the
device_t::subtag() method, so anyone using that will
automatically support the new pathing rules. Each device
has its own internal map to cache successful lookups so
that subsequent lookups should be very fast.
Updated every place I could find that referenced devices,
memory regions, I/O ports, memory banks and memory shares
to leverage subtag/subdevice (or siblingtag/siblingdevice
which are built on top).
Removed the device_list class, as it doesn't apply any
more. Moved some of its methods into running_machine
instead.
Simplified the device callback system since the new
pathing can describe all of the special-case devices that
were previously handled manually.
Changed the core output function callbacks to be delegates.
Completely rewrote the validity checking mechanism. The
validity checker is now a proper C++ class, and temporarily
takes over the error and warning outputs. All errors and
warnings are collected during a session, and then output in
a consistent manner, with an explicit driver and source file
listed for each one, as well as additional device and/or
I/O port contexts where appropriate. Validity checkers
should no longer explicitly output this information, just
the error, assuming that the context is provided.
Rewrote the software_list_device as a modern device, getting
rid of the software_list_config abstraction and simplifying
things.
Changed the way FLAC compiles so that it works like other
external libraries, and also compiles successfully for MSVC
builds.
456 lines
13 KiB
C++
456 lines
13 KiB
C++
/*
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* PlayStation CPU emulator
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*
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* Copyright 2003-2011 smf
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*
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*/
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#pragma once
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#ifndef __PSXCPU_H__
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#define __PSXCPU_H__
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#include "gte.h"
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#include "dma.h"
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#include "sio.h"
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#include "includes/psx.h"
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//**************************************************************************
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// CONSTANTS
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//**************************************************************************
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// cache
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#define ICACHE_ENTRIES ( 0x400 )
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#define DCACHE_ENTRIES ( 0x100 )
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// interrupts
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#define PSXCPU_IRQ0 ( 0 )
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#define PSXCPU_IRQ1 ( 1 )
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#define PSXCPU_IRQ2 ( 2 )
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#define PSXCPU_IRQ3 ( 3 )
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#define PSXCPU_IRQ4 ( 4 )
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#define PSXCPU_IRQ5 ( 5 )
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// register enumeration
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enum
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{
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PSXCPU_PC = 1,
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PSXCPU_DELAYV, PSXCPU_DELAYR,
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PSXCPU_HI, PSXCPU_LO,
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PSXCPU_BIU,
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PSXCPU_R0, PSXCPU_R1,
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PSXCPU_R2, PSXCPU_R3,
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PSXCPU_R4, PSXCPU_R5,
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PSXCPU_R6, PSXCPU_R7,
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PSXCPU_R8, PSXCPU_R9,
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PSXCPU_R10, PSXCPU_R11,
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PSXCPU_R12, PSXCPU_R13,
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PSXCPU_R14, PSXCPU_R15,
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PSXCPU_R16, PSXCPU_R17,
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PSXCPU_R18, PSXCPU_R19,
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PSXCPU_R20, PSXCPU_R21,
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PSXCPU_R22, PSXCPU_R23,
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PSXCPU_R24, PSXCPU_R25,
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PSXCPU_R26, PSXCPU_R27,
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PSXCPU_R28, PSXCPU_R29,
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PSXCPU_R30, PSXCPU_R31,
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PSXCPU_CP0R0, PSXCPU_CP0R1,
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PSXCPU_CP0R2, PSXCPU_CP0R3,
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PSXCPU_CP0R4, PSXCPU_CP0R5,
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PSXCPU_CP0R6, PSXCPU_CP0R7,
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PSXCPU_CP0R8, PSXCPU_CP0R9,
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PSXCPU_CP0R10, PSXCPU_CP0R11,
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PSXCPU_CP0R12, PSXCPU_CP0R13,
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PSXCPU_CP0R14, PSXCPU_CP0R15,
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PSXCPU_CP2DR0, PSXCPU_CP2DR1,
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PSXCPU_CP2DR2, PSXCPU_CP2DR3,
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PSXCPU_CP2DR4, PSXCPU_CP2DR5,
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PSXCPU_CP2DR6, PSXCPU_CP2DR7,
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PSXCPU_CP2DR8, PSXCPU_CP2DR9,
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PSXCPU_CP2DR10, PSXCPU_CP2DR11,
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PSXCPU_CP2DR12, PSXCPU_CP2DR13,
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PSXCPU_CP2DR14, PSXCPU_CP2DR15,
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PSXCPU_CP2DR16, PSXCPU_CP2DR17,
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PSXCPU_CP2DR18, PSXCPU_CP2DR19,
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PSXCPU_CP2DR20, PSXCPU_CP2DR21,
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PSXCPU_CP2DR22, PSXCPU_CP2DR23,
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PSXCPU_CP2DR24, PSXCPU_CP2DR25,
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PSXCPU_CP2DR26, PSXCPU_CP2DR27,
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PSXCPU_CP2DR28, PSXCPU_CP2DR29,
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PSXCPU_CP2DR30, PSXCPU_CP2DR31,
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PSXCPU_CP2CR0, PSXCPU_CP2CR1,
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PSXCPU_CP2CR2, PSXCPU_CP2CR3,
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PSXCPU_CP2CR4, PSXCPU_CP2CR5,
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PSXCPU_CP2CR6, PSXCPU_CP2CR7,
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PSXCPU_CP2CR8, PSXCPU_CP2CR9,
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PSXCPU_CP2CR10, PSXCPU_CP2CR11,
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PSXCPU_CP2CR12, PSXCPU_CP2CR13,
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PSXCPU_CP2CR14, PSXCPU_CP2CR15,
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PSXCPU_CP2CR16, PSXCPU_CP2CR17,
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PSXCPU_CP2CR18, PSXCPU_CP2CR19,
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PSXCPU_CP2CR20, PSXCPU_CP2CR21,
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PSXCPU_CP2CR22, PSXCPU_CP2CR23,
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PSXCPU_CP2CR24, PSXCPU_CP2CR25,
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PSXCPU_CP2CR26, PSXCPU_CP2CR27,
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PSXCPU_CP2CR28, PSXCPU_CP2CR29,
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PSXCPU_CP2CR30, PSXCPU_CP2CR31
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};
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//**************************************************************************
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// INTERFACE CONFIGURATION MACROS
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//**************************************************************************
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#define MCFG_PSX_DMA_CHANNEL_READ( cputag, channel, handler ) \
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psxcpu_device::getcpu( *owner, cputag )->subdevice<psxdma_device>("dma")->install_read_handler( channel, handler );
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#define MCFG_PSX_DMA_CHANNEL_WRITE( cputag, channel, handler ) \
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psxcpu_device::getcpu( *owner, cputag )->subdevice<psxdma_device>("dma")->install_write_handler( channel, handler );
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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// ======================> psxcpu_device
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class psxcpu_device : public cpu_device
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{
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public:
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// construction/destruction
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psxcpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// public interfaces
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WRITE32_MEMBER( biu_w );
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READ32_MEMBER( biu_r );
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WRITE32_MEMBER( berr_w );
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READ32_MEMBER( berr_r );
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static psxcpu_device *getcpu( device_t &device, const char *cputag );
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static void install_sio_handler( device_t &device, const char *cputag, int n_port, psx_sio_handler p_f_sio_handler );
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static void sio_input( device_t &device, const char *cputag, int n_port, int n_mask, int n_data );
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static void irq_set( device_t &device, const char *cputag, UINT32 bitmask );
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protected:
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psxcpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, address_map_constructor internal_map);
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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virtual void device_post_load();
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machine_config_constructor device_mconfig_additions() const;
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const { return 1; }
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virtual UINT32 execute_max_cycles() const { return 40; }
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virtual UINT32 execute_input_lines() const { return 6; }
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virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return ( clocks + 3 ) / 4; }
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virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return cycles * 4; }
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virtual void execute_run();
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virtual void execute_set_input(int inputnum, int state);
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
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// device_state_interface overrides
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virtual void state_import(const device_state_entry &entry);
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virtual void state_string_export(const device_state_entry &entry, astring &string);
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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// CPU registers
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UINT32 m_pc;
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UINT32 m_r[ 32 ];
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UINT32 m_cp0r[ 16 ];
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UINT32 m_hi;
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UINT32 m_lo;
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// internal stuff
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UINT32 m_op;
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// memory access
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inline UINT32 program_read(UINT32 addr);
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inline void program_write(UINT32 addr, UINT32 data);
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inline UINT32 opcode_read();
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// address spaces
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const address_space_config m_program_config;
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address_space *m_program;
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direct_read_data *m_direct;
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// other internal states
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int m_icount;
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UINT32 m_delayv;
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UINT32 m_delayr;
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UINT32 m_berr;
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UINT32 m_biu;
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UINT32 m_icacheTag[ ICACHE_ENTRIES / 4 ];
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UINT32 m_icache[ ICACHE_ENTRIES ];
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UINT32 m_dcache[ DCACHE_ENTRIES ];
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int m_multiplier_operation;
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UINT32 m_multiplier_operand1;
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UINT32 m_multiplier_operand2;
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int m_bus_attached;
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UINT32 m_bad_byte_address_mask;
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UINT32 m_bad_half_address_mask;
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UINT32 m_bad_word_address_mask;
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void stop();
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UINT32 cache_readword( UINT32 offset );
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void cache_writeword( UINT32 offset, UINT32 data );
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UINT8 readbyte( UINT32 address );
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UINT16 readhalf( UINT32 address );
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UINT32 readword( UINT32 address );
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UINT32 readword_masked( UINT32 address, UINT32 mask );
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void writeword( UINT32 address, UINT32 data );
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void writeword_masked( UINT32 address, UINT32 data, UINT32 mask );
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UINT32 log_bioscall_parameter( int parm );
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const char *log_bioscall_string( int parm );
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const char *log_bioscall_hex( int parm );
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const char *log_bioscall_char( int parm );
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void log_bioscall();
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void log_syscall();
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void update_memory_handlers();
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void funct_mthi();
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void funct_mtlo();
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void funct_mult();
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void funct_multu();
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void funct_div();
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void funct_divu();
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void multiplier_update();
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UINT32 get_hi();
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UINT32 get_lo();
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int execute_unstoppable_instructions( int executeCop2 );
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void update_address_masks();
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void update_scratchpad();
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void update_cop0( int reg );
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void commit_delayed_load();
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void set_pc( unsigned pc );
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void fetch_next_op();
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int advance_pc();
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void load( UINT32 reg, UINT32 value );
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void delayed_load( UINT32 reg, UINT32 value );
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void branch( UINT32 address );
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void conditional_branch( int takeBranch );
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void unconditional_branch();
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void common_exception( int exception, UINT32 romOffset, UINT32 ramOffset );
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void exception( int exception );
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void breakpoint_exception();
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void load_bus_error_exception();
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void store_bus_error_exception();
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void load_bad_address( UINT32 address );
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void store_bad_address( UINT32 address );
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int data_address_breakpoint( int dcic_rw, int dcic_status, UINT32 address );
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int load_data_address_breakpoint( UINT32 address );
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int store_data_address_breakpoint( UINT32 address );
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UINT32 get_register_from_pipeline( int reg );
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int cop0_usable();
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void lwc( int cop, int sr_cu );
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void swc( int cop, int sr_cu );
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void bc( int cop, int sr_cu, int condition );
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UINT32 getcp1dr( int reg );
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void setcp1dr( int reg, UINT32 value );
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UINT32 getcp1cr( int reg );
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void setcp1cr( int reg, UINT32 value );
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UINT32 getcp3dr( int reg );
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void setcp3dr( int reg, UINT32 value );
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UINT32 getcp3cr( int reg );
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void setcp3cr( int reg, UINT32 value );
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gte m_gte;
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};
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class cxd8530aq_device : public psxcpu_device
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{
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public:
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// construction/destruction
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cxd8530aq_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class cxd8530bq_device : public psxcpu_device
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{
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public:
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// construction/destruction
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cxd8530bq_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class cxd8530cq_device : public psxcpu_device
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{
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public:
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// construction/destruction
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cxd8530cq_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class cxd8661r_device : public psxcpu_device
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{
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public:
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// construction/destruction
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cxd8661r_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class cxd8606bq_device : public psxcpu_device
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{
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public:
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// construction/destruction
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cxd8606bq_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class cxd8606cq_device : public psxcpu_device
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{
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public:
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// construction/destruction
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cxd8606cq_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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// device type definition
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extern const device_type CXD8530AQ;
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extern const device_type CXD8530BQ;
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extern const device_type CXD8530CQ;
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extern const device_type CXD8661R;
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extern const device_type CXD8606BQ;
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extern const device_type CXD8606CQ;
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#define PSXCPU_DELAYR_PC ( 32 )
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#define PSXCPU_DELAYR_NOTPC ( 33 )
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#define PSXCPU_BYTE_EXTEND( a ) ( (INT32)(INT8)a )
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#define PSXCPU_WORD_EXTEND( a ) ( (INT32)(INT16)a )
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#define INS_OP( op ) ( ( op >> 26 ) & 63 )
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#define INS_RS( op ) ( ( op >> 21 ) & 31 )
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#define INS_RT( op ) ( ( op >> 16 ) & 31 )
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#define INS_IMMEDIATE( op ) ( op & 0xffff )
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#define INS_TARGET( op ) ( op & 0x3ffffff )
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#define INS_RD( op ) ( ( op >> 11 ) & 31 )
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#define INS_SHAMT( op ) ( ( op >> 6 ) & 31 )
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#define INS_FUNCT( op ) ( op & 63 )
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#define INS_CODE( op ) ( ( op >> 6 ) & 0xfffff )
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#define INS_CO( op ) ( ( op >> 25 ) & 1 )
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#define INS_COFUN( op ) ( op & 0x1ffffff )
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#define INS_CF( op ) ( op & 31 )
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#define INS_BC( op ) ( ( op >> 16 ) & 1 )
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#define INS_RT_REGIMM( op ) ( ( op >> 16 ) & 1 )
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#define OP_SPECIAL ( 0 )
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#define OP_REGIMM ( 1 )
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#define OP_J ( 2 )
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#define OP_JAL ( 3 )
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#define OP_BEQ ( 4 )
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#define OP_BNE ( 5 )
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#define OP_BLEZ ( 6 )
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#define OP_BGTZ ( 7 )
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#define OP_ADDI ( 8 )
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#define OP_ADDIU ( 9 )
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#define OP_SLTI ( 10 )
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#define OP_SLTIU ( 11 )
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#define OP_ANDI ( 12 )
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#define OP_ORI ( 13 )
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#define OP_XORI ( 14 )
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#define OP_LUI ( 15 )
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#define OP_COP0 ( 16 )
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#define OP_COP1 ( 17 )
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#define OP_COP2 ( 18 )
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#define OP_COP3 ( 19 )
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#define OP_LB ( 32 )
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#define OP_LH ( 33 )
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#define OP_LWL ( 34 )
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#define OP_LW ( 35 )
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#define OP_LBU ( 36 )
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#define OP_LHU ( 37 )
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#define OP_LWR ( 38 )
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#define OP_SB ( 40 )
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#define OP_SH ( 41 )
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#define OP_SWL ( 42 )
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#define OP_SW ( 43 )
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#define OP_SWR ( 46 )
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#define OP_LWC0 ( 48 )
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#define OP_LWC1 ( 49 )
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#define OP_LWC2 ( 50 )
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#define OP_LWC3 ( 51 )
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#define OP_SWC0 ( 56 )
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#define OP_SWC1 ( 57 )
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#define OP_SWC2 ( 58 )
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#define OP_SWC3 ( 59 )
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/* OP_SPECIAL */
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#define FUNCT_SLL ( 0 )
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#define FUNCT_SRL ( 2 )
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#define FUNCT_SRA ( 3 )
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#define FUNCT_SLLV ( 4 )
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#define FUNCT_SRLV ( 6 )
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#define FUNCT_SRAV ( 7 )
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#define FUNCT_JR ( 8 )
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#define FUNCT_JALR ( 9 )
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#define FUNCT_SYSCALL ( 12 )
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#define FUNCT_BREAK ( 13 )
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#define FUNCT_MFHI ( 16 )
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#define FUNCT_MTHI ( 17 )
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#define FUNCT_MFLO ( 18 )
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#define FUNCT_MTLO ( 19 )
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#define FUNCT_MULT ( 24 )
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#define FUNCT_MULTU ( 25 )
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#define FUNCT_DIV ( 26 )
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#define FUNCT_DIVU ( 27 )
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#define FUNCT_ADD ( 32 )
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#define FUNCT_ADDU ( 33 )
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#define FUNCT_SUB ( 34 )
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#define FUNCT_SUBU ( 35 )
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#define FUNCT_AND ( 36 )
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#define FUNCT_OR ( 37 )
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#define FUNCT_XOR ( 38 )
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#define FUNCT_NOR ( 39 )
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#define FUNCT_SLT ( 42 )
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#define FUNCT_SLTU ( 43 )
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/* OP_REGIMM */
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#define RT_BLTZ ( 0 )
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#define RT_BGEZ ( 1 )
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#define RT_BLTZAL ( 16 )
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#define RT_BGEZAL ( 17 )
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/* OP_COP0/OP_COP1/OP_COP2 */
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#define RS_MFC ( 0 )
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#define RS_CFC ( 2 )
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#define RS_MTC ( 4 )
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#define RS_CTC ( 6 )
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#define RS_BC ( 8 )
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#define RS_BC_ALT ( 12 )
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/* BC_BC */
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#define BC_BCF ( 0 )
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#define BC_BCT ( 1 )
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/* OP_COP0 */
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#define CF_TLBR ( 1 )
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#define CF_TLBWI ( 2 )
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#define CF_TLBWR ( 6 )
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#define CF_TLBP ( 8 )
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#define CF_RFE ( 16 )
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typedef struct _DasmPSXCPU_state DasmPSXCPU_state;
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struct _DasmPSXCPU_state
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{
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UINT32 pc;
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int delayr;
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UINT32 delayv;
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UINT32 r[ 32 ];
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};
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extern unsigned DasmPSXCPU( DasmPSXCPU_state *state, char *buffer, UINT32 pc, const UINT8 *opram );
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#endif /* __PSXCPU_H__ */
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