mirror of
https://github.com/holub/mame
synced 2025-06-05 04:16:28 +03:00
eeee1cb437
trace through in a debug build, yet should operate the same as before. Created a complete set of functions for all databus sizes (8,16,32,64) and all endiannesses. A few functions are redundant, but it is now very clear which functions to use in which scenarios. It is also now possible to rely on being able to access values of 8, 16, 32 or 64 bits via the built-in accessors without fear of crashing. Updated all cores using 8-bit handlers to explicitly call the 8-bit handlers with the appropriate endianness. Fixed a few games which were calling n-bit handlers directly to use the generic forms. In the future, this is all the access drivers will have.
259 lines
6.8 KiB
C
259 lines
6.8 KiB
C
/***************************************************************************
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mips3com.h
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Common MIPS III/IV definitions and functions
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***************************************************************************/
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#ifndef __MIPS3COM_H__
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#define __MIPS3COM_H__
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#include "cpuintrf.h"
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#include "mips3.h"
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/***************************************************************************
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CONSTANTS
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***************************************************************************/
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/* core parameters */
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#define MIPS3_MIN_PAGE_SHIFT 12
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#define MIPS3_MIN_PAGE_SIZE (1 << MIPS3_MIN_PAGE_SHIFT)
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#define MIPS3_MIN_PAGE_MASK (MIPS3_MIN_PAGE_SIZE - 1)
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#define MIPS3_MAX_PADDR_SHIFT 32
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/* cycle parameters */
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#define MIPS3_COUNT_READ_CYCLES 250
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#define MIPS3_CAUSE_READ_CYCLES 250
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/* MIPS flavors */
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enum _mips3_flavor
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{
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/* MIPS III variants */
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MIPS3_TYPE_MIPS_III,
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MIPS3_TYPE_R4600,
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MIPS3_TYPE_R4650,
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MIPS3_TYPE_R4700,
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/* MIPS IV variants */
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MIPS3_TYPE_MIPS_IV,
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MIPS3_TYPE_R5000,
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MIPS3_TYPE_QED5271,
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MIPS3_TYPE_RM7000
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};
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typedef enum _mips3_flavor mips3_flavor;
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/* COP0 registers */
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#define COP0_Index 0
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#define COP0_Random 1
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#define COP0_EntryLo 2
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#define COP0_EntryLo0 2
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#define COP0_EntryLo1 3
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#define COP0_Context 4
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#define COP0_PageMask 5
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#define COP0_Wired 6
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#define COP0_BadVAddr 8
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#define COP0_Count 9
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#define COP0_EntryHi 10
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#define COP0_Compare 11
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#define COP0_Status 12
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#define COP0_Cause 13
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#define COP0_EPC 14
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#define COP0_PRId 15
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#define COP0_Config 16
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#define COP0_XContext 20
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/* Status register bits */
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#define SR_IE 0x00000001
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#define SR_EXL 0x00000002
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#define SR_ERL 0x00000004
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#define SR_KSU_MASK 0x00000018
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#define SR_KSU_KERNEL 0x00000000
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#define SR_KSU_SUPERVISOR 0x00000008
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#define SR_KSU_USER 0x00000010
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#define SR_IMSW0 0x00000100
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#define SR_IMSW1 0x00000200
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#define SR_IMEX0 0x00000400
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#define SR_IMEX1 0x00000800
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#define SR_IMEX2 0x00001000
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#define SR_IMEX3 0x00002000
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#define SR_IMEX4 0x00004000
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#define SR_IMEX5 0x00008000
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#define SR_DE 0x00010000
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#define SR_CE 0x00020000
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#define SR_CH 0x00040000
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#define SR_SR 0x00100000
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#define SR_TS 0x00200000
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#define SR_BEV 0x00400000
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#define SR_RE 0x02000000
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#define SR_FR 0x04000000
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#define SR_RP 0x08000000
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#define SR_COP0 0x10000000
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#define SR_COP1 0x20000000
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#define SR_COP2 0x40000000
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#define SR_COP3 0x80000000
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/* exception types */
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#define EXCEPTION_INTERRUPT 0
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#define EXCEPTION_TLBMOD 1
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#define EXCEPTION_TLBLOAD 2
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#define EXCEPTION_TLBSTORE 3
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#define EXCEPTION_ADDRLOAD 4
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#define EXCEPTION_ADDRSTORE 5
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#define EXCEPTION_BUSINST 6
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#define EXCEPTION_BUSDATA 7
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#define EXCEPTION_SYSCALL 8
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#define EXCEPTION_BREAK 9
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#define EXCEPTION_INVALIDOP 10
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#define EXCEPTION_BADCOP 11
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#define EXCEPTION_OVERFLOW 12
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#define EXCEPTION_TRAP 13
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#define EXCEPTION_COUNT 16
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/***************************************************************************
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HELPER MACROS
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***************************************************************************/
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#define REG_LO 32
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#define REG_HI 33
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#define RSREG ((op >> 21) & 31)
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#define RTREG ((op >> 16) & 31)
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#define RDREG ((op >> 11) & 31)
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#define SHIFT ((op >> 6) & 31)
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#define FRREG ((op >> 21) & 31)
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#define FTREG ((op >> 16) & 31)
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#define FSREG ((op >> 11) & 31)
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#define FDREG ((op >> 6) & 31)
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#define IS_SINGLE(o) (((o) & (1 << 21)) == 0)
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#define IS_DOUBLE(o) (((o) & (1 << 21)) != 0)
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#define IS_FLOAT(o) (((o) & (1 << 23)) == 0)
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#define IS_INTEGRAL(o) (((o) & (1 << 23)) != 0)
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#define SIMMVAL ((INT16)op)
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#define UIMMVAL ((UINT16)op)
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#define LIMMVAL (op & 0x03ffffff)
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/***************************************************************************
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STRUCTURES & TYPEDEFS
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***************************************************************************/
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/* memory access function table */
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typedef struct _memory_accessors memory_accessors;
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struct _memory_accessors
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{
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UINT8 (*readbyte)(offs_t);
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UINT16 (*readhalf)(offs_t);
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UINT32 (*readword)(offs_t);
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UINT32 (*readword_masked)(offs_t, UINT32);
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UINT64 (*readdouble)(offs_t);
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UINT64 (*readdouble_masked)(offs_t, UINT64);
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void (*writebyte)(offs_t, UINT8);
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void (*writehalf)(offs_t, UINT16);
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void (*writeword)(offs_t, UINT32);
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void (*writeword_masked)(offs_t, UINT32, UINT32);
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void (*writedouble)(offs_t, UINT64);
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void (*writedouble_masked)(offs_t, UINT64, UINT64);
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};
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/* MIPS3 TLB entry */
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typedef struct _mips3_tlb_entry mips3_tlb_entry;
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struct _mips3_tlb_entry
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{
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UINT64 page_mask;
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UINT64 entry_hi;
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UINT64 entry_lo[2];
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};
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/* MIPS3 state */
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typedef struct _mips3_state mips3_state;
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struct _mips3_state
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{
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/* core registers */
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UINT32 pc;
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int icount;
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UINT64 r[35];
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/* COP registers */
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UINT64 cpr[3][32];
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UINT64 ccr[3][32];
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UINT8 cf[3][8];
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/* internal stuff */
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mips3_flavor flavor;
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int (*irq_callback)(int irqline);
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UINT32 system_clock;
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UINT32 cpu_clock;
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UINT64 count_zero_time;
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emu_timer * compare_int_timer;
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/* memory accesses */
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UINT8 bigendian;
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memory_accessors memory;
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/* cache memory */
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UINT32 * icache;
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UINT32 * dcache;
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size_t icache_size;
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size_t dcache_size;
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/* MMU */
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mips3_tlb_entry tlb[48];
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UINT32 * tlb_table;
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};
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/***************************************************************************
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FUNCTION PROTOTYPES
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***************************************************************************/
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size_t mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, int index, int clock, const struct mips3_config *config, int (*irqcallback)(int), void *memory);
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void mips3com_reset(mips3_state *mips);
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#ifdef ENABLE_DEBUGGER
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offs_t mips3com_dasm(mips3_state *mips, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
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#endif
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void mips3com_update_cycle_counting(mips3_state *mips);
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void mips3com_map_tlb_entries(mips3_state *mips);
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void mips3com_unmap_tlb_entries(mips3_state *mips);
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void mips3com_recompute_tlb_table(mips3_state *mips);
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int mips3com_translate_address(mips3_state *mips, int space, offs_t *address);
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void mips3com_tlbr(mips3_state *mips);
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void mips3com_tlbwi(mips3_state *mips);
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void mips3com_tlbwr(mips3_state *mips);
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void mips3com_tlbp(mips3_state *mips);
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void mips3com_set_info(mips3_state *mips, UINT32 state, cpuinfo *info);
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void mips3com_get_info(mips3_state *mips, UINT32 state, cpuinfo *info);
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/***************************************************************************
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INLINE FUNCTIONS
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***************************************************************************/
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/*-------------------------------------------------
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mips3com_set_irq_line - set or clear the given
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IRQ line
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-------------------------------------------------*/
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INLINE void mips3com_set_irq_line(mips3_state *mips, int irqline, int state)
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{
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if (state != CLEAR_LINE)
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mips->cpr[0][COP0_Cause] |= 0x400 << irqline;
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else
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mips->cpr[0][COP0_Cause] &= ~(0x400 << irqline);
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}
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#endif
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