mirror of
https://github.com/holub/mame
synced 2025-04-19 07:00:31 +03:00
985 lines
29 KiB
C++
985 lines
29 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:ElSemi, R. Belmont, Ryan Holtz
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/*
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* wd33c93.c
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*
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* WD/AMD 33c93 SCSI controller, as seen in
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* early PCs, some MSX add-ons, NEC PC-88, and SGI
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* Indigo, Indigo2, and Indy systems.
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*
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* References:
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* WD 33c93 manual
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* NetBSD 33c93 driver
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*
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*/
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#include "emu.h"
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#include "wd33c93.h"
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#define LOG_READS (1 << 0)
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#define LOG_WRITES (1 << 1)
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#define LOG_COMMANDS (1 << 2)
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#define LOG_ERRORS (1 << 3)
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#define LOG_MISC (1 << 4)
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#define LOG_REGS (LOG_READS | LOG_WRITES)
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#define LOG_ALL (LOG_REGS | LOG_COMMANDS | LOG_ERRORS | LOG_MISC)
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#define VERBOSE (0)
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#include "logmacro.h"
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/* WD commands */
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#define WD_CMD_RESET 0x00
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#define WD_CMD_ABORT 0x01
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#define WD_CMD_ASSERT_ATN 0x02
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#define WD_CMD_NEGATE_ACK 0x03
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#define WD_CMD_DISCONNECT 0x04
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#define WD_CMD_RESELECT 0x05
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#define WD_CMD_SEL_ATN 0x06
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#define WD_CMD_SEL 0x07
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#define WD_CMD_SEL_ATN_XFER 0x08
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#define WD_CMD_SEL_XFER 0x09
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#define WD_CMD_RESEL_RECEIVE 0x0a
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#define WD_CMD_RESEL_SEND 0x0b
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#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
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#define WD_CMD_SSCC 0x0d
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#define WD_CMD_SND_DISC 0x0e
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#define WD_CMD_SET_IDI 0x0f
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#define WD_CMD_RCV_CMD 0x10
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#define WD_CMD_RCV_DATA 0x11
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#define WD_CMD_RCV_MSG_OUT 0x12
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#define WD_CMD_RCV 0x13
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#define WD_CMD_SND_STATUS 0x14
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#define WD_CMD_SND_DATA 0x15
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#define WD_CMD_SND_MSG_IN 0x16
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#define WD_CMD_SND 0x17
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#define WD_CMD_TRANS_ADDR 0x18
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#define WD_CMD_XFER_PAD 0x19
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#define WD_CMD_TRANS_INFO 0x20
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#define WD_CMD_TRANSFER_PAD 0x21
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#define WD_CMD_SBT_MODE 0x80
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/* ASR register */
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#define ASR_INT 0x80
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#define ASR_LCI 0x40
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#define ASR_BSY 0x20
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#define ASR_CIP 0x10
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#define ASR_PE 0x02
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#define ASR_DBR 0x01
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/* SCSI Bus Phases */
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#define PHS_DATA_OUT 0x00
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#define PHS_DATA_IN 0x01
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#define PHS_COMMAND 0x02
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#define PHS_STATUS 0x03
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#define PHS_MESS_OUT 0x06
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#define PHS_MESS_IN 0x07
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/* Command Status Register definitions */
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/* reset state interrupts */
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#define CSR_RESET 0x00
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#define CSR_RESET_AF 0x01
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/* successful completion interrupts */
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#define CSR_RESELECT 0x10
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#define CSR_SELECT 0x11
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#define CSR_SEL_XFER_DONE 0x16
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#define CSR_XFER_DONE 0x18
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/* paused or aborted interrupts */
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#define CSR_MSGIN 0x20
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#define CSR_SDP 0x21
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#define CSR_SEL_ABORT 0x22
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#define CSR_RESEL_ABORT 0x25
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#define CSR_RESEL_ABORT_AM 0x27
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#define CSR_ABORT 0x28
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/* terminated interrupts */
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#define CSR_INVALID 0x40
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#define CSR_UNEXP_DISC 0x41
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#define CSR_TIMEOUT 0x42
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#define CSR_PARITY 0x43
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#define CSR_PARITY_ATN 0x44
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#define CSR_BAD_STATUS 0x45
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#define CSR_UNEXP 0x48
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/* service required interrupts */
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#define CSR_RESEL 0x80
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#define CSR_RESEL_AM 0x81
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#define CSR_DISC 0x85
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#define CSR_SRV_REQ 0x88
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/* Own ID/CDB Size register */
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#define OWNID_EAF 0x08
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#define OWNID_EHP 0x10
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#define OWNID_RAF 0x20
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#define OWNID_FS_8 0x00
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#define OWNID_FS_12 0x40
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#define OWNID_FS_16 0x80
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/* Control register */
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#define CTRL_HSP 0x01
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#define CTRL_HA 0x02
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#define CTRL_IDI 0x04
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#define CTRL_EDI 0x08
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#define CTRL_HHP 0x10
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#define CTRL_POLLED 0x00
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#define CTRL_BURST 0x20
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#define CTRL_BUS 0x40
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#define CTRL_DMA 0x80
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/* Synchronous Transfer Register */
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#define STR_FSS 0x80
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/* Destination ID register */
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#define DSTID_DPD 0x40
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#define DATA_OUT_DIR 0
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#define DATA_IN_DIR 1
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#define DSTID_SCC 0x80
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/* Source ID register */
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#define SRCID_MASK 0x07
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#define SRCID_SIV 0x08
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#define SRCID_DSP 0x20
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#define SRCID_ES 0x40
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#define SRCID_ER 0x80
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/* convernience functions */
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uint8_t wd33c93_device::getunit()
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{
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/* return the destination unit id */
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return m_regs[WD_DESTINATION_ID] & SRCID_MASK;
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}
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void wd33c93_device::set_xfer_count( int count )
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{
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/* set the count */
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m_regs[WD_TRANSFER_COUNT_LSB] = count & 0xff;
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m_regs[WD_TRANSFER_COUNT] = (count >> 8) & 0xff;
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m_regs[WD_TRANSFER_COUNT_MSB] = (count >> 16) & 0xff;
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}
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int wd33c93_device::get_xfer_count()
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{
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/* get the count */
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int count = m_regs[WD_TRANSFER_COUNT_MSB];
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count <<= 8;
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count |= m_regs[WD_TRANSFER_COUNT];
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count <<= 8;
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count |= m_regs[WD_TRANSFER_COUNT_LSB];
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return count;
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}
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void wd33c93_device::complete_immediate(int status)
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{
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/* reset our timer */
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m_cmd_timer->reset();
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/* set the new status */
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m_regs[WD_SCSI_STATUS] = status & 0xff;
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/* set interrupt pending */
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m_regs[WD_AUXILIARY_STATUS] |= ASR_INT;
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/* check for error conditions */
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if (get_xfer_count() > 0)
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{
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/* set data buffer ready */
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m_regs[WD_AUXILIARY_STATUS] |= ASR_DBR;
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}
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else
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{
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/* clear data buffer ready */
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m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
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}
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/* clear command in progress and bus busy */
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m_regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
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/* if we have a callback, call it */
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if (!m_irq_cb.isnull())
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{
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m_irq_cb(1);
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}
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}
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void wd33c93_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
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{
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switch (tid)
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{
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case 0:
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complete_immediate(param);
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break;
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case 1:
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complete_immediate(CSR_SRV_REQ | m_busphase);
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break;
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case 2:
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m_regs[WD_AUXILIARY_STATUS] &= ~ASR_CIP;
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break;
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}
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}
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void wd33c93_device::complete_cmd(uint8_t status)
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{
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/* fire off a timer to complete the command */
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m_cmd_timer->adjust(attotime::from_usec(1), status);
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}
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/* command handlers */
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void wd33c93_device::unimplemented_cmd()
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{
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LOGMASKED(LOG_COMMANDS | LOG_ERRORS, "%s: Unimplemented SCSI controller command: %02x\n", machine().describe_context(), m_regs[WD_COMMAND]);
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/* complete the command */
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complete_cmd(CSR_INVALID);
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}
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void wd33c93_device::invalid_cmd()
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{
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LOGMASKED(LOG_COMMANDS | LOG_ERRORS, "%s: Invalid SCSI controller command: %02x\n", machine().describe_context(), m_regs[WD_COMMAND]);
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/* complete the command */
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complete_cmd(CSR_INVALID);
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}
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void wd33c93_device::reset_cmd()
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{
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int advanced = 0;
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/* see if it wants us to reset with advanced features */
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if (m_regs[WD_OWN_ID] & OWNID_EAF)
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{
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advanced = 1;
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}
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/* clear out all registers */
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memset(m_regs, 0, sizeof(m_regs));
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/* complete the command */
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complete_cmd(advanced ? CSR_RESET_AF : CSR_RESET);
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}
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void wd33c93_device::abort_cmd()
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{
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/* complete the command */
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complete_cmd(CSR_ABORT);
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}
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void wd33c93_device::disconnect_cmd()
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{
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/* complete the command */
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m_regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
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}
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void wd33c93_device::select_cmd()
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{
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uint8_t unit = getunit();
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uint8_t newstatus;
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/* see if we can select that device */
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if (select(unit))
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{
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/* device is available - signal selection done */
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newstatus = CSR_SELECT;
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/* determine the next bus phase depending on the command */
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if ((m_regs[WD_COMMAND] & 0x7f) == WD_CMD_SEL_ATN)
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{
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/* /ATN asserted during select: Move to Message Out Phase to read identify */
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m_busphase = PHS_MESS_OUT;
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}
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else
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{
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/* No /ATN asserted: Move to Command Phase */
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m_busphase = PHS_COMMAND;
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}
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/* queue up a service request out in the future */
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m_service_req_timer->adjust( attotime::from_usec(50) );
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}
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else
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{
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/* device is not available */
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newstatus = CSR_TIMEOUT;
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}
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/* complete the command */
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complete_cmd(newstatus);
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}
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void wd33c93_device::selectxfer_cmd()
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{
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uint8_t unit = getunit();
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uint8_t newstatus;
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/* see if we can select that device */
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if (select(unit))
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{
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if (m_regs[WD_COMMAND_PHASE] < 0x45)
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{
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/* device is available */
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/* do the request */
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send_command(&m_regs[WD_CDB_1], 12);
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int phase = get_phase();
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/* set transfer count */
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if (get_xfer_count() > TEMP_INPUT_LEN)
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{
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LOGMASKED(LOG_ERRORS, "WD33C93: Transfer count too big. Please increase TEMP_INPUT_LEN (size=%d)\n", get_xfer_count());
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set_xfer_count(TEMP_INPUT_LEN);
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}
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switch (phase)
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{
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case SCSI_PHASE_DATAIN:
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m_read_pending = true;
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break;
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}
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}
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if (m_read_pending)
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{
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int len = TEMP_INPUT_LEN;
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if (get_xfer_count() < len)
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len = get_xfer_count();
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memset(&m_temp_input[0], 0, TEMP_INPUT_LEN);
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read_data(&m_temp_input[0], len);
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m_temp_input_pos = 0;
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m_read_pending = false;
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}
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m_regs[WD_TARGET_LUN] = 0;
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m_regs[WD_CONTROL] |= CTRL_EDI;
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m_regs[WD_COMMAND_PHASE] = 0x60;
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/* signal transfer ready */
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newstatus = CSR_SEL_XFER_DONE;
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/* if allowed disconnect, queue a service request */
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if (m_identify & 0x40)
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{
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/* queue disconnect message in */
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m_busphase = PHS_MESS_IN;
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/* queue up a service request out in the future */
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m_service_req_timer->adjust(attotime::from_usec(50));
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}
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}
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else
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{
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/* device is not available */
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newstatus = CSR_TIMEOUT;
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set_xfer_count(0);
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}
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/* complete the command */
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complete_cmd(newstatus);
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}
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void wd33c93_device::negate_ack()
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{
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LOGMASKED(LOG_MISC, "WD33C93: ACK Negated\n");
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/* complete the command */
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m_regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP | ASR_BSY);
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}
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void wd33c93_device::xferinfo_cmd()
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{
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/* make the buffer available right away */
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m_regs[WD_AUXILIARY_STATUS] |= ASR_DBR;
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m_regs[WD_AUXILIARY_STATUS] |= ASR_CIP;
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/* the command will be completed once the data is transferred */
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m_deassert_cip_timer->adjust(attotime::from_msec(1));
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}
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/* Handle pending commands */
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void wd33c93_device::dispatch_command()
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{
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/* get the command */
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uint8_t cmd = m_regs[WD_COMMAND] & 0x7f;
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switch (cmd)
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{
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case WD_CMD_RESET:
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LOGMASKED(LOG_COMMANDS, "WD33C93: %s - Reset Command\n", machine().describe_context());
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reset_cmd();
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break;
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case WD_CMD_ABORT:
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LOGMASKED(LOG_COMMANDS, "WD33C93: %s - Abort Command\n", machine().describe_context());
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abort_cmd();
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break;
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case WD_CMD_NEGATE_ACK:
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LOGMASKED(LOG_COMMANDS, "WD33C93: %s - Negate ACK Command\n", machine().describe_context());
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negate_ack();
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break;
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case WD_CMD_DISCONNECT:
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LOGMASKED(LOG_COMMANDS, "WD33C93: %s - Disconnect Command\n", machine().describe_context());
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disconnect_cmd();
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break;
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case WD_CMD_SEL_ATN:
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case WD_CMD_SEL:
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LOGMASKED(LOG_COMMANDS, "WD33C93: %s - Select %sCommand\n", machine().describe_context(), cmd == WD_CMD_SEL_ATN ? "w/ ATN " : "");
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select_cmd();
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break;
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case WD_CMD_SEL_ATN_XFER:
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case WD_CMD_SEL_XFER:
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LOGMASKED(LOG_COMMANDS, "WD33C93: %s - Select %sand Xfer Command\n", machine().describe_context(), cmd == WD_CMD_SEL_ATN ? "w/ ATN " : "");
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selectxfer_cmd();
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break;
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case WD_CMD_TRANS_INFO:
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LOGMASKED(LOG_COMMANDS, "WD33C93: %s - Transfer Info Command\n", machine().describe_context());
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xferinfo_cmd();
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break;
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case WD_CMD_ASSERT_ATN:
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case WD_CMD_RESELECT:
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case WD_CMD_RESEL_RECEIVE:
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case WD_CMD_RESEL_SEND:
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case WD_CMD_WAIT_SEL_RECEIVE:
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case WD_CMD_SSCC:
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case WD_CMD_SND_DISC:
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case WD_CMD_SET_IDI:
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case WD_CMD_RCV_CMD:
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case WD_CMD_RCV_DATA:
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case WD_CMD_RCV_MSG_OUT:
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case WD_CMD_RCV:
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case WD_CMD_SND_STATUS:
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case WD_CMD_SND_DATA:
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case WD_CMD_SND_MSG_IN:
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case WD_CMD_SND:
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case WD_CMD_TRANS_ADDR:
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case WD_CMD_XFER_PAD:
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case WD_CMD_TRANSFER_PAD:
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unimplemented_cmd();
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break;
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default:
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invalid_cmd();
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break;
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}
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}
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WRITE8_MEMBER(wd33c93_device::write)
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{
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switch (offset)
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{
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case 0:
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{
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/* update register select */
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m_sasr = data & 0x1f;
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}
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break;
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case 1:
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{
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/* update the register */
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if (m_sasr != WD_SCSI_STATUS && m_sasr <= WD_QUEUE_TAG)
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{
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m_regs[m_sasr] = data;
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}
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switch (m_sasr)
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{
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case WD_OWN_ID:
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LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Own ID Register (CDB Size) = %02x\n", machine().describe_context(), m_sasr, data);
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break;
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case WD_CONTROL:
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LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Control Register = %02x\n", machine().describe_context(), m_sasr, data);
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break;
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case WD_TIMEOUT_PERIOD:
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LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Timeout Period Register = %02x\n", machine().describe_context(), m_sasr, data);
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break;
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case WD_CDB_1:
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LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Total Sectors Register (CDB1) = %02x\n", machine().describe_context(), m_sasr, data);
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m_regs[WD_COMMAND_PHASE] = 0;
|
|
break;
|
|
case WD_CDB_2:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Total Heads Register (CDB2) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_3:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Total Cylinders Register MSB (CDB3) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_4:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Total Cylinders Register LSB (CDB4) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_5:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Logical Address Register MSB (CDB5) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_6:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Logical Address Register 2nd (CDB6) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_7:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Logical Address Register 3rd (CDB7) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_8:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Logical Address Register LSB (CDB8) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_9:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Sector Number Register (CDB9) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_10:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Head Number Register (CDB10) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_11:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Cylinder Number Register MSB (CDB11) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_CDB_12:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Cylinder Number Register LSB (CDB12) = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_TARGET_LUN:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Target LUN Register = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_COMMAND_PHASE:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Command Phase Register = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_SYNCHRONOUS_TRANSFER:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Synchronous Transfer Register = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_TRANSFER_COUNT_MSB:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Transfer Count Register MSB = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_TRANSFER_COUNT:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Transfer Count Register 2nd = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_TRANSFER_COUNT_LSB:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Transfer Count Register LSB = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_DESTINATION_ID:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Destination ID Register = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_SOURCE_ID:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Source ID Register = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_SCSI_STATUS:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, SCSI Status Register (read-only!) = %02x (ignored)\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_COMMAND:
|
|
/* if we receive a command, schedule to process it */
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Command Register = %02x - unit %d\n", machine().describe_context(), m_sasr, data, getunit());
|
|
|
|
/* signal we're processing it */
|
|
m_regs[WD_AUXILIARY_STATUS] |= ASR_CIP;
|
|
|
|
/* process the command */
|
|
dispatch_command();
|
|
break;
|
|
case WD_DATA:
|
|
{
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Data Register = %02x\n", machine().describe_context(), m_sasr, data);
|
|
|
|
/* if data was written, and we have a count, send to device */
|
|
int count = get_xfer_count();
|
|
|
|
if (m_regs[WD_COMMAND] & 0x80)
|
|
count = 1;
|
|
|
|
if (count-- > 0)
|
|
{
|
|
/* write to FIFO */
|
|
if (m_fifo_pos < FIFO_SIZE)
|
|
{
|
|
m_fifo[m_fifo_pos++] = data;
|
|
}
|
|
|
|
/* update count */
|
|
set_xfer_count(count);
|
|
|
|
/* if we're done with the write, see where we're at */
|
|
if (count == 0)
|
|
{
|
|
m_regs[WD_AUXILIARY_STATUS] |= ASR_INT;
|
|
m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
|
|
|
|
switch (m_busphase)
|
|
{
|
|
case PHS_MESS_OUT:
|
|
{
|
|
/* reset fifo */
|
|
m_fifo_pos = 0;
|
|
|
|
/* Message out phase. Data is probably SCSI Identify. Move to command phase. */
|
|
m_busphase = PHS_COMMAND;
|
|
|
|
m_identify = m_fifo[0];
|
|
}
|
|
break;
|
|
|
|
case PHS_COMMAND:
|
|
{
|
|
/* Execute the command. Depending on the command, we'll move to data in or out */
|
|
send_command(&m_fifo[0], 12);
|
|
int xfercount = get_length();
|
|
int phase = get_phase();
|
|
|
|
/* reset fifo */
|
|
m_fifo_pos = 0;
|
|
|
|
/* set the new count */
|
|
set_xfer_count(xfercount);
|
|
|
|
switch (phase)
|
|
{
|
|
case SCSI_PHASE_STATUS:
|
|
m_busphase = PHS_STATUS;
|
|
break;
|
|
|
|
case SCSI_PHASE_DATAIN:
|
|
m_busphase = PHS_DATA_IN;
|
|
m_read_pending = true;
|
|
break;
|
|
|
|
case SCSI_PHASE_DATAOUT:
|
|
m_busphase = PHS_DATA_OUT;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case PHS_DATA_OUT:
|
|
{
|
|
/* write data out to device */
|
|
write_data(m_fifo, m_fifo_pos);
|
|
|
|
/* reset fifo */
|
|
m_fifo_pos = 0;
|
|
|
|
/* move to status phase */
|
|
m_busphase = PHS_STATUS;
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* complete the command */
|
|
complete_immediate(CSR_XFER_DONE | m_busphase);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
LOGMASKED(LOG_MISC | LOG_ERRORS, "WD33C93: Sending data to device with transfer count = 0!. Ignoring...\n");
|
|
}
|
|
break;
|
|
}
|
|
case WD_QUEUE_TAG:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Queue Tag Register = %02x\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
case WD_AUXILIARY_STATUS:
|
|
LOGMASKED(LOG_WRITES, "WD33C93: %s - Write Register %02x, Auxiliary Status Register (read-only!) = %02x (ignored)\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
default:
|
|
LOGMASKED(LOG_WRITES | LOG_ERRORS, "WD33C93: %s - Write Register %02x, Unknown = %02x (ignored)\n", machine().describe_context(), m_sasr, data);
|
|
break;
|
|
}
|
|
|
|
/* auto-increment register select if not on special registers */
|
|
if (m_sasr != WD_COMMAND && m_sasr != WD_DATA && m_sasr != WD_AUXILIARY_STATUS)
|
|
{
|
|
m_sasr = (m_sasr + 1) & 0x1f;
|
|
}
|
|
}
|
|
break;
|
|
|
|
default:
|
|
{
|
|
LOGMASKED(LOG_ERRORS, "WD33C93: Write to invalid offset %d (data=%02x)\n", offset, data);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
READ8_MEMBER(wd33c93_device::read)
|
|
{
|
|
switch (offset)
|
|
{
|
|
case 0:
|
|
/* read aux status */
|
|
return m_regs[WD_AUXILIARY_STATUS];
|
|
|
|
case 1:
|
|
{
|
|
switch (m_sasr)
|
|
{
|
|
case WD_OWN_ID:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Own ID Register (CDB Size) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CONTROL:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Control Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_TIMEOUT_PERIOD:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Timeout Period Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_1:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Total Sectors Register (CDB1) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
m_regs[WD_COMMAND_PHASE] = 0;
|
|
break;
|
|
case WD_CDB_2:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Total Heads Register (CDB2) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_3:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Total Cylinders Register MSB (CDB3) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_4:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Total Cylinders Register LSB (CDB4) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_5:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Logical Address Register MSB (CDB5) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_6:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Logical Address Register 2nd (CDB6) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_7:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Logical Address Register 3rd (CDB7) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_8:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Logical Address Register LSB (CDB8) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_9:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Sector Number Register (CDB9) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_10:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Head Number Register (CDB10) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_11:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Cylinder Number Register MSB (CDB11) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_CDB_12:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Cylinder Number Register LSB (CDB12) (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_TARGET_LUN:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Target LUN Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_COMMAND_PHASE:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Command Phase Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_SYNCHRONOUS_TRANSFER:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Synchronous Transfer Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_TRANSFER_COUNT_MSB:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Transfer Count Register MSB (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_TRANSFER_COUNT:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Transfer Count Register 2nd (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_TRANSFER_COUNT_LSB:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Transfer Count Register LSB (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_DESTINATION_ID:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Destination ID Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_SOURCE_ID:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Source ID Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_SCSI_STATUS:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, SCSI Status Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
m_regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
|
|
|
|
/* if reading status, clear irq flag */
|
|
if (!m_irq_cb.isnull())
|
|
{
|
|
m_irq_cb(0);
|
|
}
|
|
break;
|
|
case WD_COMMAND:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Command Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_DATA:
|
|
{
|
|
/* we're going to be doing synchronous reads */
|
|
|
|
/* get the transfer count */
|
|
int count = get_xfer_count();
|
|
|
|
/* initialize the return value */
|
|
m_regs[WD_DATA] = 0;
|
|
|
|
if (count <= 0 && m_busphase == PHS_MESS_IN)
|
|
{
|
|
/* move to disconnect */
|
|
complete_cmd(CSR_DISC);
|
|
}
|
|
else if (count == 1 && m_busphase == PHS_STATUS)
|
|
{
|
|
/* update the count */
|
|
set_xfer_count(0);
|
|
|
|
/* move to message in phase */
|
|
m_busphase = PHS_MESS_IN;
|
|
|
|
/* complete the command */
|
|
complete_cmd(CSR_XFER_DONE | m_busphase);
|
|
}
|
|
else if (count-- > 0) /* make sure we still have data to send */
|
|
{
|
|
if (m_read_pending)
|
|
{
|
|
int len = TEMP_INPUT_LEN;
|
|
|
|
if ((count + 1) < len )
|
|
len = count + 1;
|
|
read_data(&m_temp_input[0], len);
|
|
m_temp_input_pos = 0;
|
|
m_read_pending = false;
|
|
}
|
|
|
|
m_regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
|
|
|
|
/* read in one byte */
|
|
if (m_temp_input_pos < TEMP_INPUT_LEN)
|
|
m_regs[WD_DATA] = m_temp_input[m_temp_input_pos++];
|
|
|
|
/* update the count */
|
|
set_xfer_count(count);
|
|
|
|
/* transfer finished, see where we're at */
|
|
if (count == 0)
|
|
{
|
|
if (m_regs[WD_COMMAND_PHASE] != 0x60)
|
|
{
|
|
/* move to status phase */
|
|
m_busphase = PHS_STATUS;
|
|
|
|
/* complete the command */
|
|
complete_cmd(CSR_XFER_DONE | m_busphase);
|
|
}
|
|
else
|
|
{
|
|
m_regs[WD_AUXILIARY_STATUS] |= ASR_INT;
|
|
m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
|
|
}
|
|
}
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Data Register (%02x)\n", machine().describe_context(), WD_DATA, m_regs[WD_DATA]);
|
|
}
|
|
break;
|
|
}
|
|
case WD_QUEUE_TAG:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Queue Tag Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
case WD_AUXILIARY_STATUS:
|
|
LOGMASKED(LOG_READS, "WD33C93: %s - Read Register %02x, Auxiliary Status Register (%02x)\n", machine().describe_context(), m_sasr, m_regs[m_sasr]);
|
|
break;
|
|
default:
|
|
LOGMASKED(LOG_READS | LOG_ERRORS, "WD33C93: %s - Read Register %02x, Unknown\n", machine().describe_context(), m_sasr);
|
|
break;
|
|
}
|
|
|
|
/* get the register value */
|
|
uint8_t ret = 0xff;
|
|
if (m_sasr == WD_AUXILIARY_STATUS || m_sasr <= WD_QUEUE_TAG)
|
|
ret = m_regs[m_sasr];
|
|
|
|
/* auto-increment register select if not on special registers */
|
|
if (m_sasr != WD_COMMAND && m_sasr != WD_DATA && m_sasr != WD_AUXILIARY_STATUS)
|
|
{
|
|
m_sasr = (m_sasr + 1) & 0x1f;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
default:
|
|
LOGMASKED(LOG_READS | LOG_ERRORS, "WD33C93: Read from invalid offset %d\n", offset);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
wd33c93_device::wd33c93_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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legacy_scsi_host_adapter(mconfig, WD33C93, tag, owner, clock),
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m_irq_cb(*this)
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{
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}
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void wd33c93_device::device_start()
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{
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legacy_scsi_host_adapter::device_start();
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memset(m_regs, 0, sizeof(m_regs));
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memset(m_fifo, 0, sizeof(m_fifo));
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memset(m_temp_input, 0, sizeof(m_temp_input));
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m_sasr = 0;
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m_fifo_pos = 0;
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m_temp_input_pos = 0;
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m_busphase = 0;
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m_identify = 0;
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m_read_pending = 0;
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m_irq_cb.resolve();
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/* allocate a timer for commands */
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m_cmd_timer = timer_alloc(0);
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m_service_req_timer = timer_alloc(1);
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m_deassert_cip_timer = timer_alloc(2);
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save_item(NAME(m_sasr));
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save_item(NAME(m_regs));
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save_item(NAME(m_fifo));
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save_item(NAME(m_fifo_pos));
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save_item(NAME(m_temp_input));
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save_item(NAME(m_temp_input_pos));
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save_item(NAME(m_busphase));
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save_item(NAME(m_identify));
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save_item(NAME(m_read_pending));
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}
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int wd33c93_device::dma_read_data(int bytes, uint8_t *data)
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{
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int len = bytes;
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if (len >= get_xfer_count())
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len = get_xfer_count();
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if (len == 0)
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return 0;
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if ((m_temp_input_pos + len) >= TEMP_INPUT_LEN)
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{
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LOGMASKED(LOG_ERRORS, "Reading past end of buffer, increase TEMP_INPUT_LEN size\n");
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len = TEMP_INPUT_LEN - len;
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}
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assert(len);
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memcpy(data, &m_temp_input[m_temp_input_pos], len);
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m_temp_input_pos += len;
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set_xfer_count(get_xfer_count() - len);
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return len;
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}
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void wd33c93_device::dma_write_data(int bytes, uint8_t *data)
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{
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write_data(data, bytes);
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}
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void wd33c93_device::clear_dma()
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{
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/* indicate DMA completed by clearing the transfer count */
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set_xfer_count(0);
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m_regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
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}
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int wd33c93_device::get_dma_count()
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{
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return get_xfer_count();
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}
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DEFINE_DEVICE_TYPE(WD33C93, wd33c93_device, "wd33c93", "Western Digital WD33C93 SCSI")
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