mirror of
https://github.com/holub/mame
synced 2025-04-16 21:44:32 +03:00
333 lines
7.9 KiB
C
333 lines
7.9 KiB
C
// license:BSD-3-Clause
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// copyright-holders:Luca Elia
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/***************************************************************************
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TMP68301 basic emulation + Interrupt Handling
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The Toshiba TMP68301 is a 68HC000 + serial I/O, parallel I/O,
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3 timers, address decoder, wait generator, interrupt controller,
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all integrated in a single chip.
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TODO:
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- Interrupt generation: handle pending / in-service mechanisms
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- Parallel port: handle timing latency
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- Serial port: not done at all
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- (and many other things)
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***************************************************************************/
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#include "emu.h"
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#include "machine/tmp68301.h"
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const device_type TMP68301 = &device_creator<tmp68301_device>;
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static ADDRESS_MAP_START( tmp68301_regs, AS_0, 16, tmp68301_device )
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// AM_RANGE(0x000,0x3ff) AM_RAM
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AM_RANGE(0x094,0x095) AM_READWRITE(imr_r,imr_w)
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AM_RANGE(0x098,0x099) AM_READWRITE(iisr_r,iisr_w)
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/* Parallel Port */
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AM_RANGE(0x100,0x101) AM_READWRITE(pdir_r,pdir_w)
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AM_RANGE(0x10a,0x10b) AM_READWRITE(pdr_r,pdr_w)
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/* Serial Port */
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AM_RANGE(0x18e,0x18f) AM_READWRITE(scr_r,scr_w)
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ADDRESS_MAP_END
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// IRQ Mask register, 0x94
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READ16_MEMBER(tmp68301_device::imr_r)
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{
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return m_imr;
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}
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WRITE16_MEMBER(tmp68301_device::imr_w)
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{
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COMBINE_DATA(&m_imr);
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}
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// IRQ In-Service Register
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READ16_MEMBER(tmp68301_device::iisr_r)
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{
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return m_iisr;
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}
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WRITE16_MEMBER(tmp68301_device::iisr_w)
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{
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COMBINE_DATA(&m_iisr);
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}
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// Serial Control Register (TODO: 8-bit wide)
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READ16_MEMBER(tmp68301_device::scr_r)
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{
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return m_scr;
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}
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WRITE16_MEMBER(tmp68301_device::scr_w)
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{
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/*
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*--- ---- CKSE
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--*- ---- RES
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---- ---* INTM
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*/
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COMBINE_DATA(&m_scr);
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m_scr &= 0xa1;
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}
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/* Parallel direction: 1 = output, 0 = input */
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READ16_MEMBER(tmp68301_device::pdir_r)
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{
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return m_pdir;
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}
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WRITE16_MEMBER(tmp68301_device::pdir_w)
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{
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m_pdir = data;
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}
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READ16_MEMBER(tmp68301_device::pdr_r)
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{
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return m_in_parallel_cb(0) & ~m_pdir;
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}
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WRITE16_MEMBER(tmp68301_device::pdr_w)
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{
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m_out_parallel_cb(0, data & m_pdir, mem_mask);
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}
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tmp68301_device::tmp68301_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, TMP68301, "TMP68301", tag, owner, clock, "tmp68301", __FILE__),
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device_memory_interface(mconfig, *this),
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m_in_parallel_cb(*this),
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m_out_parallel_cb(*this),
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m_imr(0),
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m_iisr(0),
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m_scr(0),
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m_pdir(0),
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m_space_config("regs", ENDIANNESS_LITTLE, 16, 10, 0, NULL, *ADDRESS_MAP_NAME(tmp68301_regs))
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{
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memset(m_regs, 0, sizeof(m_regs));
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memset(m_IE, 0, sizeof(m_IE));
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memset(m_irq_vector, 0, sizeof(m_irq_vector));
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void tmp68301_device::device_start()
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{
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int i;
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for (i = 0; i < 3; i++)
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m_tmp68301_timer[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tmp68301_device::timer_callback), this));
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m_in_parallel_cb.resolve_safe(0);
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m_out_parallel_cb.resolve_safe();
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save_item(NAME(m_regs));
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save_item(NAME(m_IE));
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save_item(NAME(m_irq_vector));
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save_item(NAME(m_imr));
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save_item(NAME(m_iisr));
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save_item(NAME(m_scr));
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save_item(NAME(m_pdir));
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void tmp68301_device::device_reset()
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{
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int i;
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for (i = 0; i < 3; i++)
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m_IE[i] = 0;
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m_imr = 0x7f7; // mask all irqs
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}
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//-------------------------------------------------
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// memory_space_config - return a description of
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// any address spaces owned by this device
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//-------------------------------------------------
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const address_space_config *tmp68301_device::memory_space_config(address_spacenum spacenum) const
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{
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return (spacenum == AS_0) ? &m_space_config : NULL;
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}
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//**************************************************************************
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// INLINE HELPERS
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//**************************************************************************
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//-------------------------------------------------
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// read_byte - read a byte at the given address
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//-------------------------------------------------
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inline UINT16 tmp68301_device::read_word(offs_t address)
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{
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return space(AS_0).read_word(address << 1);
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}
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//-------------------------------------------------
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// write_byte - write a byte at the given address
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//-------------------------------------------------
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inline void tmp68301_device::write_word(offs_t address, UINT16 data)
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{
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space(AS_0).write_word(address << 1, data);
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}
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IRQ_CALLBACK_MEMBER(tmp68301_device::irq_callback)
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{
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int vector = m_irq_vector[irqline];
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// logerror("%s: irq callback returns %04X for level %x\n",machine.describe_context(),vector,int_level);
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return vector;
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}
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TIMER_CALLBACK_MEMBER( tmp68301_device::timer_callback )
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{
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int i = param;
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UINT16 TCR = m_regs[(0x200 + i * 0x20)/2];
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UINT16 ICR = m_regs[0x8e/2+i]; // Interrupt Controller Register (ICR7..9)
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UINT16 IVNR = m_regs[0x9a/2]; // Interrupt Vector Number Register (IVNR)
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// logerror("s: callback timer %04X, j = %d\n",machine.describe_context(),i,tcount);
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if ( (TCR & 0x0004) && // INT
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!(m_imr & (0x100<<i))
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)
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{
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int level = ICR & 0x0007;
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// Interrupt Vector Number Register (IVNR)
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m_irq_vector[level] = IVNR & 0x00e0;
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m_irq_vector[level] += 4+i;
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machine().firstcpu->set_input_line(level,HOLD_LINE);
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}
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if (TCR & 0x0080) // N/1
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{
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// Repeat
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update_timer(i);
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}
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else
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{
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// One Shot
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}
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}
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void tmp68301_device::update_timer( int i )
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{
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UINT16 TCR = m_regs[(0x200 + i * 0x20)/2];
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UINT16 MAX1 = m_regs[(0x204 + i * 0x20)/2];
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UINT16 MAX2 = m_regs[(0x206 + i * 0x20)/2];
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int max = 0;
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attotime duration = attotime::zero;
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m_tmp68301_timer[i]->adjust(attotime::never,i);
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// timers 1&2 only
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switch( (TCR & 0x0030)>>4 ) // MR2..1
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{
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case 1:
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max = MAX1;
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break;
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case 2:
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max = MAX2;
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break;
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}
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switch ( (TCR & 0xc000)>>14 ) // CK2..1
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{
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case 0: // System clock (CLK)
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if (max)
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{
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int scale = (TCR & 0x3c00)>>10; // P4..1
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if (scale > 8) scale = 8;
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duration = attotime::from_hz(machine().firstcpu->unscaled_clock()) * ((1 << scale) * max);
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}
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break;
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}
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// logerror("%s: TMP68301 Timer %d, duration %lf, max %04X\n",machine().describe_context(),i,duration,max);
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if (!(TCR & 0x0002)) // CS
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{
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if (duration != attotime::zero)
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m_tmp68301_timer[i]->adjust(duration,i);
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else
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logerror("%s: TMP68301 error, timer %d duration is 0\n",machine().describe_context(),i);
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}
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}
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/* Update the IRQ state based on all possible causes */
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void tmp68301_device::update_irq_state()
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{
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int i;
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/* Take care of external interrupts */
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UINT16 IVNR = m_regs[0x9a/2]; // Interrupt Vector Number Register (IVNR)
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for (i = 0; i < 3; i++)
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{
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if ( (m_IE[i]) &&
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!(m_imr & (1<<i))
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)
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{
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UINT16 ICR = m_regs[0x80/2+i]; // Interrupt Controller Register (ICR0..2)
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// Interrupt Controller Register (ICR0..2)
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int level = ICR & 0x0007;
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// Interrupt Vector Number Register (IVNR)
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m_irq_vector[level] = IVNR & 0x00e0;
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m_irq_vector[level] += i;
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m_IE[i] = 0; // Interrupts are edge triggerred
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machine().firstcpu->set_input_line(level,HOLD_LINE);
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}
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}
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}
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READ16_MEMBER( tmp68301_device::regs_r )
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{
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return read_word(offset);
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}
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WRITE16_MEMBER( tmp68301_device::regs_w )
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{
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COMBINE_DATA(&m_regs[offset]);
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write_word(offset,m_regs[offset]);
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if (!ACCESSING_BITS_0_7) return;
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// logerror("CPU #0 PC %06X: TMP68301 Reg %04X<-%04X & %04X\n",space.device().safe_pc(),offset*2,data,mem_mask^0xffff);
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switch( offset * 2 )
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{
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// Timers
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case 0x200:
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case 0x220:
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case 0x240:
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{
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int i = ((offset*2) >> 5) & 3;
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update_timer( i );
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}
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break;
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}
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}
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void tmp68301_device::external_interrupt_0() { m_IE[0] = 1; update_irq_state(); }
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void tmp68301_device::external_interrupt_1() { m_IE[1] = 1; update_irq_state(); }
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void tmp68301_device::external_interrupt_2() { m_IE[2] = 1; update_irq_state(); }
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