mirror of
https://github.com/Tolik-Trek/Estex-DSS.git
synced 2026-06-15 01:11:48 +03:00
337 lines
5.1 KiB
NASM
337 lines
5.1 KiB
NASM
;!TODO Procedures
|
||
;----------------------------------------------------------------------;
|
||
; ‡ ª®¤¨à®¢ âì ¢à¥¬ï/¤ âã
|
||
; ¢å®¤: de - ¤¥ì/¬¥áïæ
|
||
; hl - ç áë/¬¨ãâë
|
||
; b - ᥪã¤ë
|
||
; ix - £®¤
|
||
; ¢ë室: de - ¢à¥¬ï
|
||
; bc - ¬¥áïæ/¤¥ì
|
||
; ix - £®¤
|
||
;
|
||
;INPUT: D - DAY; E - MONTH
|
||
; H - HOUR; L - MINUTE
|
||
; B - SECOND (0...59)
|
||
; IX- YEAR (0...65535)
|
||
;OUTPUT: DE - hhhhhmmmmmmsssss h - hour, m - min, s - sec/2
|
||
; BC - yyyyyyymmmmddddd y - year, m - month, d - day
|
||
; (1980-2108)
|
||
MK_TIME:
|
||
LD A,L
|
||
RLCA
|
||
RLCA
|
||
SLA A
|
||
RL H
|
||
SLA A
|
||
RL H
|
||
SLA A
|
||
RL H
|
||
SRL B
|
||
OR B
|
||
LD L,A
|
||
|
||
LD BC,#F844 ;(-1980)
|
||
ADD IX,BC
|
||
LD A,E
|
||
RLCA
|
||
RLCA
|
||
RLCA
|
||
RLCA
|
||
AND #F0
|
||
LD B,XL
|
||
SLA A
|
||
RL B
|
||
OR D
|
||
LD C,A
|
||
EX DE,HL
|
||
AND A
|
||
RET
|
||
;----------------------------------------------------------------------;
|
||
|
||
;!TODO Procedures
|
||
;----------------------------------------------------------------------;
|
||
; <20> ᪮¤¨à®¢ âì ¢à¥¬ï/¤ âã
|
||
; ¢å®¤: de - ¢à¥¬ï
|
||
; bc - ¬¥áïæ/¤¥ì
|
||
; ix - £®¤
|
||
; ¢ë室: de - ¤¥ì/¬¥áïæ
|
||
; hl - ç áë/¬¨ãâë
|
||
; b - ᥪã¤ë
|
||
; ix - £®¤
|
||
;
|
||
;INPUT: DE - hhhhhmmmmmmsssss h - hour, m - min, s - sec/2
|
||
; BC - yyyyyyymmmmddddd y - year, m - month, d - day
|
||
; (1980-2108)
|
||
;OUTPUT: D - DAY; E - MONTH
|
||
; H - HOUR; L - MINUTE
|
||
; B - SECOND (0...59)
|
||
; IX- YEAR (0...65535)
|
||
RMKTIME:
|
||
EX DE,HL
|
||
LD A,C
|
||
AND #1F
|
||
LD D,A
|
||
SRL B
|
||
RR C
|
||
LD A,C
|
||
RRCA
|
||
RRCA
|
||
RRCA
|
||
RRCA
|
||
AND #0F
|
||
LD E,A
|
||
LD C,B
|
||
LD B,0
|
||
LD IX,1980
|
||
ADD IX,BC
|
||
LD A,L
|
||
AND #1F
|
||
ADD A,A
|
||
LD B,A
|
||
SRL H
|
||
RR L
|
||
SRL H
|
||
RR L
|
||
SRL H
|
||
RR L
|
||
SRL L
|
||
SRL L
|
||
AND A
|
||
RET
|
||
;----------------------------------------------------------------------;
|
||
|
||
|
||
|
||
;----------------------------------------------------------------------;
|
||
; a..z -> A..Z
|
||
UPPER: CP 'a'
|
||
RET C
|
||
CP 'z' + 1
|
||
JR NC,.MDUPPER
|
||
SUB #20
|
||
.NOUPPER:
|
||
RET
|
||
.MDUPPER:
|
||
CP ' ' ; àãááª ï ¡ãª¢ , ª®¤ #A0
|
||
JR C,.NOUPPER
|
||
CP '¯' ; àãááª ï ¡ãª¢ ¯, ª®¤ #B0
|
||
JR NC,.BGUPPER
|
||
SUB #20
|
||
RET
|
||
.BGUPPER:
|
||
CP 'à' ; àãááª ï ¡ãª¢ à, ª®¤ #E0
|
||
JR C,.NOUPPER
|
||
CP 'ð' ; àãááª ï ¡ãª¢ ð, ª®¤ #F0
|
||
JR NC,.HGUPPER
|
||
SUB #50
|
||
RET
|
||
.HGUPPER: CP 'ñ' ; àãááª ï ¡ãª¢ ñ, ª®¤ #F1
|
||
RET NZ
|
||
DEC A
|
||
RET
|
||
;----------------------------------------------------------------------;
|
||
|
||
|
||
|
||
;!TODO hardware
|
||
;----------------------------------------------------------------------;
|
||
; —⥨¥ ॣ¨áâ஢ CMOS
|
||
; ¢å®¤: d=®¬¥à ॣ¨áâà
|
||
RCMOS: LD C,BIOS.CMOS_RD
|
||
RST ToBIOS
|
||
;JP BCD2HEX
|
||
; INPUT : A - BCD
|
||
; OUTPUT: A - HEX
|
||
BCD2HEX:
|
||
LD E,A
|
||
RRCA
|
||
RRCA
|
||
RRCA
|
||
RRCA
|
||
AND #0F
|
||
LD D,A
|
||
ADD A,A
|
||
ADD A,A
|
||
ADD A,D
|
||
ADD A,A
|
||
LD D,A
|
||
LD A,E
|
||
AND #0F
|
||
ADD A,D
|
||
RET
|
||
;----------------------------------------------------------------------;
|
||
|
||
;!TODO hardware
|
||
;----------------------------------------------------------------------;
|
||
;!FIXIT ¯¥à¥¤¥« âì ¯® ¤®ª¥ „ «« á ¨ § ¯¨áì ¢ ï祩ª¨ ç ᮢ
|
||
; ‡ ¯¨áì ॣ¨áâ஢ CMOS
|
||
; ¢å®¤: d=®¬¥à ॣ¨áâà
|
||
WCMOS: CALL HEX2BCD
|
||
LD C,BIOS.CMOS_WR
|
||
JP ToBIOS
|
||
|
||
; INPUT : A - HEX
|
||
; OUTPUT: A - BCD
|
||
HEX2BCD:
|
||
LD BC,#0AFF
|
||
.loop: INC C
|
||
SUB B
|
||
JR NC,.loop
|
||
ADD A,B
|
||
LD B,A
|
||
LD A,C
|
||
RLCA
|
||
RLCA
|
||
RLCA
|
||
RLCA
|
||
AND #F0
|
||
OR B
|
||
RET
|
||
;----------------------------------------------------------------------;
|
||
;
|
||
|
||
; HL:DE / C => DE:IX HL-OSTATOK (DE:BC.HL). ‹¥£ª® ¯¥à¥¤¥« âì ¯®¤ HL:DE / A => HL:DE.A
|
||
;----------------------------------------------------------------------;
|
||
DIV_for_SPC:
|
||
LD A,C
|
||
DEC A
|
||
JR Z,.exit
|
||
;
|
||
AND E
|
||
LD B,A ; ®áâ ⮪
|
||
LD A,C
|
||
RRCA
|
||
;
|
||
.loop: SRL H : RR L
|
||
RR D : RR E
|
||
RRCA
|
||
JP NC,.loop
|
||
LD A,B
|
||
;
|
||
.exit: LD XH,D
|
||
LD XL,E
|
||
EX DE,HL
|
||
LD H,0
|
||
LD L,A
|
||
RET
|
||
;----------------------------------------------------------------------;
|
||
|
||
; DIV32: LD A,#FF
|
||
; LD B,E
|
||
; .loop: SRL C
|
||
; JR C,.exitLoop
|
||
; SRL H : RR L : RR D : RR E : SLA A
|
||
; JP .loop
|
||
; .exitLoop:
|
||
; CPL
|
||
; AND B
|
||
; LD XH,D
|
||
; LD XL,E
|
||
; EX DE,HL
|
||
; LD H,0
|
||
; LD L,A
|
||
; RET
|
||
/*
|
||
DEFINE NEW_DIV 1
|
||
|
||
DIV32: LD XH,D
|
||
LD XL,E
|
||
|
||
IFN NEW_DIV
|
||
EX DE,HL
|
||
LD HL,0
|
||
LD A,#20
|
||
DIV001: ADD IX,IX
|
||
EX DE,HL
|
||
ADC HL,HL
|
||
EX DE,HL
|
||
ADC HL,HL
|
||
SBC HL,BC
|
||
JR NC,DIV002
|
||
ADD HL,BC
|
||
DEC A
|
||
JR NZ,DIV001
|
||
RET
|
||
DIV002: INC IX
|
||
DEC A
|
||
JR NZ,DIV001
|
||
RET
|
||
ELSE
|
||
|
||
|
||
div32_16:
|
||
;HLIX/BC -> HLIX remainder DE
|
||
;174+4*div32_16_sub8
|
||
;min: 2186cc
|
||
;max: 2794cc
|
||
;avg: 2466cc
|
||
;61 bytes
|
||
ex de,hl ; 4
|
||
|
||
; Negate BC to allow add instead of sbc
|
||
xor a ; 4
|
||
; Need to set HL to 0 anyways, so save 2cc and a byte
|
||
ld h,a ; 4
|
||
ld l,a ; 4
|
||
sub c ; 4
|
||
ld c,a ; 4
|
||
sbc a,a ; 4
|
||
sub b ; 4
|
||
ld b,a ; 4
|
||
|
||
|
||
ld a,d ; 4
|
||
call div32_16_sub8 ; 17
|
||
rla ; 4
|
||
ld d,a ; 4
|
||
|
||
ld a,e ; 4
|
||
call div32_16_sub8 ; 17
|
||
rla ; 4
|
||
ld e,a ; 4
|
||
|
||
ld a,ixh ; 8
|
||
call div32_16_sub8 ; 17
|
||
rla ; 4
|
||
ld ixh,a ; 8
|
||
|
||
ld a,ixl ; 8
|
||
call div32_16_sub8 ; 17
|
||
rla ; 4
|
||
ld ixl,a ; 8
|
||
|
||
;ex de,hl ; 4
|
||
ret ; 10
|
||
|
||
div32_16_sub8:
|
||
;119+8*div32_16_sub
|
||
;min: 503cc
|
||
;max: 655cc
|
||
;avg: 573cc
|
||
call 1F
|
||
1:
|
||
;17+2(17+2(div32_16_sub)))
|
||
call 1F
|
||
1:
|
||
;17+2(div32_16_sub)
|
||
call div32_16_sub
|
||
div32_16_sub:
|
||
;48+{8,0+{0,19}}
|
||
;min: 48cc
|
||
;max: 67cc
|
||
;avg: 56.75cc
|
||
rla ; 4
|
||
adc hl,hl ; 15
|
||
jr c,1F ;12/7
|
||
add hl,bc ; 11
|
||
ret c ;11/5
|
||
sbc hl,bc ; 15
|
||
ret ; 10
|
||
1:
|
||
add hl,bc ; 11
|
||
scf ; 4
|
||
ret ; 10
|
||
|
||
ENDIF
|
||
*/
|
||
; |