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sinclair/sprinter.cpp tmkonf

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Andrei Holub 2026-03-05 21:02:59 -05:00 committed by Andrei I. Holub
parent c71bbb1c10
commit 7ea867099e
1 changed files with 65 additions and 15 deletions
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80
src/mame/sinclair/sprinter.cpp
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@ -222,8 +222,8 @@ private:
void do_accel_block(bool is_read); void do_accel_block(bool is_read);
void accel_mem_r(offs_t offset); void accel_mem_r(offs_t offset);
void accel_mem_w(offs_t offset, u8 data); void accel_mem_w(offs_t offset, u8 data);
u8 &accel_buffer(u8 idx); u8 &accel_buffer(u16 idx);
void update_accel_buffer(u8 idx, u8 data); void update_accel_buffer(u16 idx, u8 data);
u8 kbd_fe_r(offs_t offset); u8 kbd_fe_r(offs_t offset);
void on_kbd_data(int state); void on_kbd_data(int state);
@ -299,8 +299,8 @@ private:
// Accelerator // Accelerator
u8 m_prf_d; u8 m_prf_d;
u8 m_rgacc; u8 m_rgacc;
u8 m_acc_cnt; u16 m_acc_cnt;
u8 m_accel_buffer[256] = {}; u8 m_accel_buffer[1024] = {};
bool m_alt_acc; bool m_alt_acc;
u16 m_aagr; u16 m_aagr;
u8 m_xcnt; u8 m_xcnt;
@ -308,6 +308,10 @@ private:
u8 m_acc_dir; u8 m_acc_dir;
accel_state m_fn_acc; accel_state m_fn_acc;
access_state m_access_state; access_state m_access_state;
u8 m_acc_ctrl;
u8 m_acc_rect_w;
u8 m_acc_rect_counter;
// Covox Blaster // Covox Blaster
u8 m_cbl_xx; u8 m_cbl_xx;
@ -661,6 +665,13 @@ u8 sprinter_state::dcp_r(offs_t offset)
} }
break; break;
case 0x80:
data = m_acc_ctrl;
break;
case 0x81:
data = m_acc_rect_w;
break;
case 0x89: case 0x89:
data = m_cbl_xx; data = m_cbl_xx;
break; break;
@ -785,6 +796,13 @@ void sprinter_state::dcp_w(offs_t offset, u8 data)
machine().schedule_soft_reset(); machine().schedule_soft_reset();
break; break;
case 0x80:
m_acc_ctrl = data;
break;
case 0x81:
m_acc_rect_w = data;
break;
case 0x88: case 0x88:
if (cbl_mode()) if (cbl_mode())
m_cbl_data[m_cbl_wa++] = data << 8; m_cbl_data[m_cbl_wa++] = data << 8;
@ -959,9 +977,10 @@ void sprinter_state::accel_control_r(u8 data)
TIMER_CALLBACK_MEMBER(sprinter_state::acc_tick) TIMER_CALLBACK_MEMBER(sprinter_state::acc_tick)
{ {
assert(m_access_state == ACCEL_GO); assert(m_access_state == ACCEL_GO);
m_acc_cnt = m_rgacc; m_acc_cnt = BIT(m_acc_ctrl, 5) ? (m_rgacc == 0 ? 1024 : m_rgacc * 4) : (m_rgacc == 0 ? 256 : m_rgacc);
m_acc_rect_counter = m_acc_rect_w + 1;
m_access_state = ACCEL_ON; m_access_state = ACCEL_ON;
const bool is_read = param & 1; const bool is_read = param & 1;
int ticks42 = 0; int ticks42 = 0;
bool is_block_op = BIT(m_acc_dir, 2); bool is_block_op = BIT(m_acc_dir, 2);
@ -1099,7 +1118,27 @@ void sprinter_state::do_accel_block(bool is_read)
if (BIT(m_acc_dir, 4)) // graph line if (BIT(m_acc_dir, 4)) // graph line
m_port_y++; m_port_y++;
else else
m_z80_addr++; {
if (BIT(m_acc_ctrl, 4) && !is_read) // bit 4 - acc rect mode
{
m_acc_rect_counter--;
if (m_acc_rect_counter == 0)
{
if (BIT(m_acc_ctrl, 6))
m_z80_addr += m_acc_rect_w + 1;
else
m_z80_addr -= m_acc_rect_w + 1;
m_acc_rect_counter = m_acc_rect_w + 1;
m_port_y++;
};
}
if (BIT(m_acc_ctrl, 6))
m_z80_addr--;
else
m_z80_addr++;
}
} }
void sprinter_state::accel_mem_r(offs_t offset) void sprinter_state::accel_mem_r(offs_t offset)
@ -1118,7 +1157,7 @@ void sprinter_state::accel_mem_w(offs_t offset, u8 data)
} }
} }
u8 &sprinter_state::accel_buffer(u8 idx) u8 &sprinter_state::accel_buffer(u16 idx)
{ {
if (m_alt_acc) if (m_alt_acc)
{ {
@ -1128,10 +1167,10 @@ u8 &sprinter_state::accel_buffer(u8 idx)
m_xagr = xcnt_agr & 0xff; m_xagr = xcnt_agr & 0xff;
} }
return m_accel_buffer[idx]; return m_accel_buffer[1023 & idx];
} }
void sprinter_state::update_accel_buffer(u8 idx, u8 data) void sprinter_state::update_accel_buffer(u16 idx, u8 data)
{ {
switch (m_fn_acc) switch (m_fn_acc)
{ {
@ -1199,11 +1238,15 @@ template <u8 Bank> void sprinter_state::ram_w(offs_t offset, u8 data)
if ((page & 0xf0) == 0x50) if ((page & 0xf0) == 0x50)
{ {
const u32 vaddr = m_port_y * 1024 + (offset & 0x3ff); if (((~m_acc_ctrl & 1) || (((~m_port_y & 128) && (m_acc_ctrl & 2)) || ((m_port_y & 128) && (~m_acc_ctrl & 2)))) // y-clip
if (BIT(~page, 2)) && ((~m_acc_ctrl & 4) || (((~offset & 128) && (m_acc_ctrl & 8)) || ((offset & 128) && (~m_acc_ctrl & 8))))) // x-clip
m_ram->pointer()[(0x50 << 14) + vaddr] = data; {
if (!(BIT(page, 3) && (data == 0xff))) const u32 vaddr = m_port_y * 1024 + (offset & 0x3ff);
vram_w(vaddr, data); if (BIT(~page, 2))
m_ram->pointer()[(0x50 << 14) + vaddr] = data;
if (BIT(~page, 3) || (data != 0xff))
vram_w(vaddr, data);
}
} }
else else
{ {
@ -1518,11 +1561,15 @@ void sprinter_state::machine_start()
save_item(NAME(m_acc_dir)); save_item(NAME(m_acc_dir));
save_item(NAME(m_fn_acc)); save_item(NAME(m_fn_acc));
save_item(NAME(m_access_state)); save_item(NAME(m_access_state));
save_item(NAME(m_acc_ctrl));
save_item(NAME(m_acc_rect_w));
save_item(NAME(m_acc_rect_counter));
save_item(NAME(m_cbl_xx)); save_item(NAME(m_cbl_xx));
save_item(NAME(m_cbl_data)); save_item(NAME(m_cbl_data));
save_item(NAME(m_cbl_cnt)); save_item(NAME(m_cbl_cnt));
save_item(NAME(m_cbl_wa)); save_item(NAME(m_cbl_wa));
save_item(NAME(m_cbl_wae)); save_item(NAME(m_cbl_wae));
m_beta->enable(); m_beta->enable();
@ -1613,6 +1660,9 @@ void sprinter_state::machine_reset()
m_prf_d = false; m_prf_d = false;
m_acc_dir = 0; m_acc_dir = 0;
m_alt_acc = 0; m_alt_acc = 0;
m_acc_ctrl = 0;
m_acc_rect_w = 0;
m_acc_rect_counter = 0;
m_cbl_xx = 0; m_cbl_xx = 0;
m_cbl_wa = 0; m_cbl_wa = 0;