sinclair/sprinter.cpp tmkonf
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@ -222,8 +222,8 @@ private:
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void do_accel_block(bool is_read);
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void accel_mem_r(offs_t offset);
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void accel_mem_w(offs_t offset, u8 data);
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u8 &accel_buffer(u8 idx);
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void update_accel_buffer(u8 idx, u8 data);
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u8 &accel_buffer(u16 idx);
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void update_accel_buffer(u16 idx, u8 data);
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u8 kbd_fe_r(offs_t offset);
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void on_kbd_data(int state);
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@ -299,8 +299,8 @@ private:
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// Accelerator
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u8 m_prf_d;
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u8 m_rgacc;
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u8 m_acc_cnt;
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u8 m_accel_buffer[256] = {};
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u16 m_acc_cnt;
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u8 m_accel_buffer[1024] = {};
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bool m_alt_acc;
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u16 m_aagr;
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u8 m_xcnt;
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@ -309,6 +309,10 @@ private:
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accel_state m_fn_acc;
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access_state m_access_state;
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u8 m_acc_ctrl;
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u8 m_acc_rect_w;
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u8 m_acc_rect_counter;
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// Covox Blaster
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u8 m_cbl_xx;
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u16 m_cbl_data[256] = {};
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@ -661,6 +665,13 @@ u8 sprinter_state::dcp_r(offs_t offset)
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}
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break;
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case 0x80:
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data = m_acc_ctrl;
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break;
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case 0x81:
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data = m_acc_rect_w;
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break;
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case 0x89:
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data = m_cbl_xx;
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break;
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@ -785,6 +796,13 @@ void sprinter_state::dcp_w(offs_t offset, u8 data)
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machine().schedule_soft_reset();
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break;
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case 0x80:
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m_acc_ctrl = data;
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break;
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case 0x81:
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m_acc_rect_w = data;
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break;
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case 0x88:
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if (cbl_mode())
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m_cbl_data[m_cbl_wa++] = data << 8;
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@ -959,7 +977,8 @@ void sprinter_state::accel_control_r(u8 data)
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TIMER_CALLBACK_MEMBER(sprinter_state::acc_tick)
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{
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assert(m_access_state == ACCEL_GO);
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m_acc_cnt = m_rgacc;
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m_acc_cnt = BIT(m_acc_ctrl, 5) ? (m_rgacc == 0 ? 1024 : m_rgacc * 4) : (m_rgacc == 0 ? 256 : m_rgacc);
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m_acc_rect_counter = m_acc_rect_w + 1;
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m_access_state = ACCEL_ON;
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const bool is_read = param & 1;
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@ -1098,9 +1117,29 @@ void sprinter_state::do_accel_block(bool is_read)
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if (BIT(m_acc_dir, 4)) // graph line
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m_port_y++;
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else
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{
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if (BIT(m_acc_ctrl, 4) && !is_read) // bit 4 - acc rect mode
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{
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m_acc_rect_counter--;
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if (m_acc_rect_counter == 0)
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{
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if (BIT(m_acc_ctrl, 6))
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m_z80_addr += m_acc_rect_w + 1;
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else
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m_z80_addr -= m_acc_rect_w + 1;
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m_acc_rect_counter = m_acc_rect_w + 1;
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m_port_y++;
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};
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}
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if (BIT(m_acc_ctrl, 6))
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m_z80_addr--;
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else
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m_z80_addr++;
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}
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}
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void sprinter_state::accel_mem_r(offs_t offset)
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{
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@ -1118,7 +1157,7 @@ void sprinter_state::accel_mem_w(offs_t offset, u8 data)
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}
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}
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u8 &sprinter_state::accel_buffer(u8 idx)
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u8 &sprinter_state::accel_buffer(u16 idx)
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{
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if (m_alt_acc)
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{
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@ -1128,10 +1167,10 @@ u8 &sprinter_state::accel_buffer(u8 idx)
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m_xagr = xcnt_agr & 0xff;
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}
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return m_accel_buffer[idx];
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return m_accel_buffer[1023 & idx];
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}
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void sprinter_state::update_accel_buffer(u8 idx, u8 data)
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void sprinter_state::update_accel_buffer(u16 idx, u8 data)
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{
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switch (m_fn_acc)
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{
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@ -1198,13 +1237,17 @@ template <u8 Bank> void sprinter_state::ram_w(offs_t offset, u8 data)
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machine().schedule_soft_reset();
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if ((page & 0xf0) == 0x50)
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{
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if (((~m_acc_ctrl & 1) || (((~m_port_y & 128) && (m_acc_ctrl & 2)) || ((m_port_y & 128) && (~m_acc_ctrl & 2)))) // y-clip
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&& ((~m_acc_ctrl & 4) || (((~offset & 128) && (m_acc_ctrl & 8)) || ((offset & 128) && (~m_acc_ctrl & 8))))) // x-clip
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{
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const u32 vaddr = m_port_y * 1024 + (offset & 0x3ff);
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if (BIT(~page, 2))
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m_ram->pointer()[(0x50 << 14) + vaddr] = data;
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if (!(BIT(page, 3) && (data == 0xff)))
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if (BIT(~page, 3) || (data != 0xff))
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vram_w(vaddr, data);
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}
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}
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else
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{
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if (~m_all_mode & 1)
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@ -1518,12 +1561,16 @@ void sprinter_state::machine_start()
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save_item(NAME(m_acc_dir));
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save_item(NAME(m_fn_acc));
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save_item(NAME(m_access_state));
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save_item(NAME(m_acc_ctrl));
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save_item(NAME(m_acc_rect_w));
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save_item(NAME(m_acc_rect_counter));
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save_item(NAME(m_cbl_xx));
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save_item(NAME(m_cbl_data));
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save_item(NAME(m_cbl_cnt));
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save_item(NAME(m_cbl_wa));
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save_item(NAME(m_cbl_wae));
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m_beta->enable();
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// reconfigure ROMs
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@ -1613,6 +1660,9 @@ void sprinter_state::machine_reset()
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m_prf_d = false;
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m_acc_dir = 0;
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m_alt_acc = 0;
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m_acc_ctrl = 0;
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m_acc_rect_w = 0;
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m_acc_rect_counter = 0;
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m_cbl_xx = 0;
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m_cbl_wa = 0;
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