This commit is contained in:
Anatoliy Belyanskiy 2023-08-22 01:57:45 +10:00
parent 8be4b3a70b
commit 05e89d7636

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@ -1576,19 +1576,26 @@ INIT_TBL_IDE2 HDD_INIT_TABLE = SYS_PAGE.IDE_2 ; !HARDC
INIT_TBL_IDE3 HDD_INIT_TABLE = SYS_PAGE.IDE_3 ; !HARDCODE table in SYS_PAGE INIT_TBL_IDE3 HDD_INIT_TABLE = SYS_PAGE.IDE_3 ; !HARDCODE table in SYS_PAGE
;IDE_STATUS_3F7 EQU #29 ; HDD - ¤®¯. ॣ¨áâà á®áâ®ï­¨ï 3F7. ¢­¥è­¨© #4055
; <EFBFBD>¥£¨áâà  ¤à¥á  ­ ª®¯¨â¥«ï (3F7 ç⥭¨¥) ᮤ¥à¦¨â ­®¬¥à £®«®¢ª¨ ¨ <EFBFBD>†Œ„, ¢ë¡à ­­ë¥ ¢ ¯à¥¤ë¤ã饩 ®¯¥à æ¨¨.
; <EFBFBD>¨âë 0, 1 - /DSO, /DS1 - ¡¨âë ¢ë¡®à  á®®â¢¥âáâ¢ãî饣® ­ ª®¯¨â¥«ï 0 ¨«¨ 1.
; <EFBFBD>¨âë 2...5 - /HSO../HS3 - ᮤ¥à¦ â ¤¢®¨ç­ë© ª®¤ ¢ë¡à ­­®© £®«®¢ª¨.
; <EFBFBD>¨â 6 - Write Gate - ¡¨â ¢ë¯®«­¥­¨ï § ¯¨á¨,  ªâ¨¢¥­ ¢® ¢à¥¬ï ®¯¥à æ¨¨ § ¯¨á¨
Write: Write:
.DeviceControl EQU #4154 ; ; #3F6 Device Control register .DeviceControl EQU #4154 ; ; #3F6 Device Control register
.DriveCtrl EQU #4152 ; HDW_DRV P_HD_CS ; #1F6 Drive Control register .DriveCtrl EQU #4152 ; HDW_DRV P_HD_CS ; #1F6 Drive Control register
.Command EQU #4153 ; HDW_COM P_CMD ; #1F7 Command register .Command EQU #4153 ; HDW_COM P_CMD ; #1F7 Command register
.Data EQU #0150 ; HDW_DAT W170 ; #1F0 Data register .Data EQU #0150 ; HDW_DAT W170 ; #1F0 Data register
.Error EQU #0151 ; HDW_ERR W171 ; #1F1 Error register .Features EQU #0151 ; HDW_ERR W171 ; #1F1 Features register
.Counter EQU #0152 ; HDW_CNT P_S_CNT W172 ; #1F2 Counter register .Counter EQU #0152 ; HDW_CNT P_S_CNT W172 ; #1F2 Counter register
.Sector EQU #0153 ; HDW_SEC P_S_NUM W173 ; #1F3 Sector register .Sector EQU #0153 ; HDW_SEC P_S_NUM W173 ; #1F3 Sector register
.CylinderLow EQU #0154 ; HDW_CLL P_C_LOW W174 ; #1F4 Cylinder Low register .CylinderLow EQU #0154 ; HDW_CLL P_C_LOW W174 ; #1F4 Cylinder Low register
.CylinderHigh EQU #0155 ; HDW_CLH P_C_HIG W175 ; #1F5 Cylinder High register .CylinderHigh EQU #0155 ; HDW_CLH P_C_HIG W175 ; #1F5 Cylinder High register
Read: Read:
.DrvAddress EQU #4055 ; #3F7
.AltControl EQU #4054 ; ; #3F6 Alternate Status register .AltControl EQU #4054 ; ; #3F6 Alternate Status register
.Control EQU #4052 ; HDR_DRV R176 ; #1F6 Drive Control register .Control EQU #4052 ; HDR_DRV R176 ; #1F6 Drive Control register
.Status EQU #4053 ; HDR_CTL P_HDST R177 ; #1F7 Status (Control) register .Status EQU #4053 ; HDR_CTL P_HDST R177 ; #1F7 Status (Control) register
@ -1606,8 +1613,8 @@ ControlBit: ; Bits for HardDrive.Read.Status
.StreamErrror EQU .Fault .StreamErrror EQU .Fault
.DeferredWriteError EQU 4 .DeferredWriteError EQU 4
.DataRequest EQU 3 ; DRQ .DataRequest EQU 3 ; DRQ
.AlignmentError EQU 2 .AlignmentError EQU 2 ; obsolete
.SenseDataAvailable EQU 1 .SenseDataAvailable EQU 1 ; obsolete
.Error EQU 0 ; Indicates an error occurred. Send a new command to clear it (or nuke it with a Software Reset). .Error EQU 0 ; Indicates an error occurred. Send a new command to clear it (or nuke it with a Software Reset).
.CheckCondition EQU .Error .CheckCondition EQU .Error
/* /*