From 54298bfb52826572bda5ccd0609320a9418d08c9 Mon Sep 17 00:00:00 2001 From: Anatoliy Belyanskiy Date: Sat, 30 Dec 2023 02:49:19 +1000 Subject: [PATCH] ... --- constants/SP2000.inc | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/constants/SP2000.inc b/constants/SP2000.inc index 93e100b..e881fda 100644 --- a/constants/SP2000.inc +++ b/constants/SP2000.inc @@ -2022,41 +2022,41 @@ STC3_C EQU #13 ;-------------------[Ports] ; Counter Timer Control CTC: -.Ch_0 EQU #10 ; Control Register -.Ch_1 EQU #11 ; Control Register -.Ch_2 EQU #12 ; Control Register -.Ch_3 EQU #13 ; Control Register +.Ch_0 EQU #10 ; Control Register +.Ch_1 EQU #11 ; Control Register +.Ch_2 EQU #12 ; Control Register +.Ch_3 EQU #13 ; Control Register ; Serial I/O SIO: -.Ch_A.Data EQU #18 ; Data register COM -.Ch_A.Ctrl EQU #19 ; Control register COM -.Ch_B.Data EQU #1A ; Data register keyboard & mouse -.Ch_B.Ctrl EQU #1B ; Control register keyboard & mouse +.Ch_A.Data EQU #18 ; Data register keyboard DAT_A +.Ch_A.Ctrl EQU #19 ; Control register keyboard COM_A +.Ch_B.Data EQU #1A ; Data register mouse DMOUSE +.Ch_B.Ctrl EQU #1B ; Control register mouse CMOUSE ; Parallel I/O PIO: -.Port_A.Data EQU #1C ; Data register LPT 1 -.Port_A.Command EQU #1D ; Command register LPT 1 -.Port_B.Data EQU #1E ; Data register LPT 2 +.Port_A.Data EQU #1C ; Data register LPT 1 +.Port_A.Command EQU #1D ; Command register LPT 1 +.Port_B.Data EQU #1E ; Data register LPT 2 ;только через регистр BC, иначе Альтера перехватит -.Port_B.Command EQU #1F ; Command register LPT 2 +.Port_B.Command EQU #1F ; Command register LPT 2 ; Watch Dog timer WDT: -.Master_Reg EQU #F0 ; Master register WDTMR -.Control_Reg EQU #F1 ; Control register WDTCR +.Master_Reg EQU #F0 ; Master register WDTMR +.Control_Reg EQU #F1 ; Control register WDTCR ; Interrupt Priority Register -IntPrior_Reg EQU #F4 +IntPrior_Reg EQU #F4 ;System Control SYS: -.Control EQU #EE ; System Control Register Pointer SCRP -.Data EQU #EF ; System Control Data Port SCDP +.Control EQU #EE ; System Control Register Pointer SCRP +.Data EQU #EF ; System Control Data Port SCDP ;------------------------[] ;-------------------[Regs ] REG: -.WaitState_Ctrl EQU 00 ; Wait state control register WCR -.WaitState_MemBound EQU 01 ; Memory Wait state Boundary Register MWBR -.CS_Boundary EQU 02 ; Chip Select Boundary Register CSBR -.Misc_Ctrl EQU 03 ; Misc.Control Register MCR +.WaitState_Ctrl EQU 00 ; Wait state control register WCR +.WaitState_MemBound EQU 01 ; Memory Wait state Boundary Register MWBR +.CS_Boundary EQU 02 ; Chip Select Boundary Register CSBR +.Misc_Ctrl EQU 03 ; Misc.Control Register MCR ;------------------------[] ENDMODULE ;