Analysis & Synthesis report for SP2_ACEX
Sun Aug 28 15:25:51 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                               ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Failed - Sun Aug 28 15:25:51 2022            ;
; Quartus II Version          ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name               ; SP2_ACEX                                     ;
; Top-level Entity Name       ; SP2_ACEX                                     ;
; Family                      ; ACEX1K                                       ;
+-----------------------------+----------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                ;
+--------------------------------------------------------------+---------------+---------------+
; Option                                                       ; Setting       ; Default Value ;
+--------------------------------------------------------------+---------------+---------------+
; Device                                                       ; EP1K30QC208-3 ;               ;
; Top-level entity name                                        ; SP2_ACEX      ; SP2_ACEX      ;
; Family name                                                  ; ACEX1K        ; Stratix II    ;
; Use smart compilation                                        ; Off           ; Off           ;
; Create Debugging Nodes for IP Cores                          ; Off           ; Off           ;
; Preserve fewer node names                                    ; On            ; On            ;
; Disable OpenCore Plus hardware evaluation                    ; Off           ; Off           ;
; Verilog Version                                              ; Verilog_2001  ; Verilog_2001  ;
; VHDL Version                                                 ; VHDL93        ; VHDL93        ;
; State Machine Processing                                     ; Auto          ; Auto          ;
; Safe State Machine                                           ; Off           ; Off           ;
; Extract Verilog State Machines                               ; On            ; On            ;
; Extract VHDL State Machines                                  ; On            ; On            ;
; Ignore Verilog initial constructs                            ; Off           ; Off           ;
; Iteration limit for constant Verilog loops                   ; 5000          ; 5000          ;
; Iteration limit for non-constant Verilog loops               ; 250           ; 250           ;
; Add Pass-Through Logic to Inferred RAMs                      ; On            ; On            ;
; Parallel Synthesis                                           ; Off           ; Off           ;
; NOT Gate Push-Back                                           ; On            ; On            ;
; Power-Up Don't Care                                          ; On            ; On            ;
; Remove Redundant Logic Cells                                 ; Off           ; Off           ;
; Remove Duplicate Registers                                   ; On            ; On            ;
; Ignore CARRY Buffers                                         ; Off           ; Off           ;
; Ignore CASCADE Buffers                                       ; Off           ; Off           ;
; Ignore GLOBAL Buffers                                        ; Off           ; Off           ;
; Ignore ROW GLOBAL Buffers                                    ; Off           ; Off           ;
; Ignore LCELL Buffers                                         ; Off           ; Off           ;
; Ignore SOFT Buffers                                          ; On            ; On            ;
; Limit AHDL Integers to 32 Bits                               ; Off           ; Off           ;
; Auto Implement in ROM                                        ; Off           ; Off           ;
; Optimization Technique                                       ; Area          ; Area          ;
; Carry Chain Length                                           ; 32            ; 32            ;
; Cascade Chain Length                                         ; 2             ; 2             ;
; Auto Carry Chains                                            ; On            ; On            ;
; Auto Open-Drain Pins                                         ; On            ; On            ;
; Auto ROM Replacement                                         ; On            ; On            ;
; Auto RAM Replacement                                         ; On            ; On            ;
; Auto Clock Enable Replacement                                ; On            ; On            ;
; Strict RAM Replacement                                       ; Off           ; Off           ;
; Auto Resource Sharing                                        ; Off           ; Off           ;
; Allow Any RAM Size For Recognition                           ; Off           ; Off           ;
; Allow Any ROM Size For Recognition                           ; Off           ; Off           ;
; Use LogicLock Constraints during Resource Balancing          ; On            ; On            ;
; Ignore translate_off and synthesis_off directives            ; Off           ; Off           ;
; Show Parameter Settings Tables in Synthesis Report           ; On            ; On            ;
; HDL message level                                            ; Level2        ; Level2        ;
; Suppress Register Optimization Related Messages              ; Off           ; Off           ;
; Number of Removed Registers Reported in Synthesis Report     ; 100           ; 100           ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100           ; 100           ;
; Block Design Naming                                          ; Auto          ; Auto          ;
; Synthesis Effort                                             ; Auto          ; Auto          ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On            ; On            ;
; Analysis & Synthesis Message Level                           ; Medium        ; Medium        ;
+--------------------------------------------------------------+---------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                       ;
+----------------------------------+-----------------+-----------------------+-----------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type             ; File Name with Absolute Path                                    ;
+----------------------------------+-----------------+-----------------------+-----------------------------------------------------------------+
; SP2_ACEX.tdf                     ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf                ;
; lpm_ram_dp.inc                   ; yes             ; Auto-Found AHDL File  ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dp.inc  ;
; kbd.inc                          ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/acex/kbd.inc                     ;
; video2.inc                       ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/acex/video2.inc                  ;
; dcp.inc                          ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/acex/dcp.inc                     ;
; acceler.inc                      ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/acex/acceler.inc                 ;
; ay.inc                           ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/acex/ay.inc                      ;
; mouse.inc                        ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/acex/mouse.inc                   ;
; MOUSE.tdf                        ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/acex/MOUSE.tdf                   ;
; lpm_add_sub.inc                  ; yes             ; Auto-Found AHDL File  ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; kbd.tdf                          ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/acex/kbd.tdf                     ;
; lpm_ram_dq.inc                   ; yes             ; Auto-Found AHDL File  ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.inc  ;
; lpm_ram_dq.tdf                   ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf  ;
; altram.inc                       ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/altram.inc      ;
; lpm_mux.inc                      ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_mux.inc     ;
; lpm_decode.inc                   ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_decode.inc  ;
; aglobal90.inc                    ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/aglobal90.inc   ;
; altram.tdf                       ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/altram.tdf      ;
; memmodes.inc                     ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/others/maxplus2/memmodes.inc  ;
; altsyncram.inc                   ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/altsyncram.inc  ;
; altqpram.inc                     ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/altqpram.inc    ;
+----------------------------------+-----------------+-----------------------+-----------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Sun Aug 28 15:25:50 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SP2_ACEX -c SP2_ACEX
Warning: Using design file SP2_ACEX.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SP2_ACEX
Info: Elaborating entity "SP2_ACEX" for the top level hierarchy
Warning: Variable or input pin "DMD" is defined but never used
Warning: Variable or input pin "T_SIGNAL" is defined but never used
Warning: Variable or input pin "RED" is defined but never used
Warning: Variable or input pin "GREEN" is defined but never used
Warning: Variable or input pin "BLUE" is defined but never used
Warning: Variable or input pin "MDR" is defined but never used
Warning: Variable or input pin "ISA_CASH" is defined but never used
Warning: Variable or input pin "ROM_WRITE_MODE" is defined but never used
Warning: Variable or input pin "/HALT" is defined but never used
Warning: Using design file MOUSE.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: mouse
Info: Elaborating entity "MOUSE" for hierarchy "MOUSE:MS"
Warning: Variable or input pin "KB_OFL" is defined but never used
Warning: Using design file kbd.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: kbd
Info: Elaborating entity "kbd" for hierarchy "kbd:KEYS"
Warning: Variable or input pin "/IOM" is defined but never used
Warning: Variable or input pin "/M1" is defined but never used
Info: Elaborating entity "lpm_ram_dq" for hierarchy "kbd:KEYS|lpm_ram_dq:$00021"
Info: Elaborated megafunction instantiation "kbd:KEYS|lpm_ram_dq:$00021"
Info: Instantiated megafunction "kbd:KEYS|lpm_ram_dq:$00021" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_WIDTHAD" = "8"
    Info: Parameter "LPM_FILE" = "KBD_INI2.MIF"
    Info: Parameter "LPM_OUTDATA" = "UNREGISTERED"
Info: Elaborating entity "altram" for hierarchy "kbd:KEYS|lpm_ram_dq:$00021|altram:sram"
Error: Memory Initialization File or Hexadecimal (Intel-Format) File "KBD_INI2.MIF" contains illegal syntax at line 13 File: C:/Sprinter/src/altera/quartus/acex/KBD_INI2.MIF Line: 13
Critical Warning: Can't read Memory Initialization File or Hexadecimal (Intel-Format) File KBD_INI2.MIF -- setting all initial values to 0
Error: Can't elaborate user hierarchy "kbd:KEYS|lpm_ram_dq:$00021|altram:sram" File: c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf Line: 101
Info: Elaborated megafunction instantiation "kbd:KEYS|lpm_ram_dq:$00021|altram:sram", which is child of megafunction instantiation "kbd:KEYS|lpm_ram_dq:$00021"
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 16 warnings
    Error: Peak virtual memory: 228 megabytes
    Error: Processing ended: Sun Aug 28 15:25:51 2022
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01


