mirror of
https://github.com/Tolik-Trek/Sprinter-BIOS.git
synced 2026-06-15 01:11:47 +03:00
Переход на относительные URL подмодулей
This commit is contained in:
Анатолий Белянский
Tolik
parent
314ba263d6
commit
3b64afe4e1
2
.gitmodules
vendored
2
.gitmodules
vendored
@ -1,4 +1,4 @@
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[submodule "Shared_Includes"]
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branch = main
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path = Shared_Includes
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url = https://github.com/Tolik-Trek/Shared_Includes.git
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url = ../Shared_Includes.git
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@ -1 +1 @@
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Subproject commit 51198ce44bd19f511b63e6fafaf91b3de5470f9d
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Subproject commit 591d3212c9341f17d6dd034bf2b8da91bd2f6107
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@ -16,7 +16,7 @@
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;---------------------------------------;
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;-----------[Shared Includes]-----------
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INCLUDE 'src/bios/shared/includes.inc' ; Includes
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INCLUDE 'bios/shared/includes.inc' ; Includes
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;---------------------------------------
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@ -41,16 +41,14 @@
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print ()
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if detected_os == "Windows" then
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pack_prog = "src\\bin\\hrust.exe Build\\Bin\\temp\\MAIN.PAK Build\\Bin\\temp\\MAIN.BIN"
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elseif detected_os == "MacOS" then
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pack_prog = "src/bin/mhmt -hst -zxh Build/Bin/temp/MAIN.BIN Build/Bin/temp/MAIN.PAK"
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elseif detected_os == "Linux" then
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pack_prog = "src/bin/mhmt -hst -zxh Build/Bin/temp/MAIN.BIN Build/Bin/temp/MAIN.PAK"
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pack_prog = "bin\\hrust.exe Build\\Bin\\temp\\MAIN.PAK Build\\Bin\\temp\\MAIN.BIN"
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else
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pack_prog = "bin/mhmt -hst -zxh Build/Bin/temp/MAIN.BIN Build/Bin/temp/MAIN.PAK"
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end
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-- ª®¬¯¨«ïæ¨ï ¤«ï ¯®«ã票ï ᦠ⮣® ä ©« MAIN ¨ 宫®á⮩ ¯à®å®¤ Set_Pictures.asm
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if (os.execute("sjasmplus -DPREBUILD=1 -Wall --msg=war --nologo --syntax=w --fullpath --lst=Build/Prebuilds.LST SRC/BIOS/ROM/SETUP/MAIN.ASM")) then
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if (os.execute("sjasmplus -DPREBUILD=1 -Wall --msg=war --nologo --syntax=w --fullpath --lst=Build/Prebuilds.LST BIOS/ROM/SETUP/MAIN.ASM")) then
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print("--[ MAIN.ASM Prebuild DONE ]--")
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if (os.execute(pack_prog)) then
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print("--[ Hrusting MAIN.BIN DONE ]--")
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@ -71,7 +69,7 @@
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;----------[MAIN's referenses]----------; Š®¬¯¨«ïæ¨ï ¤«ï ¯®«ãç¥¨ï ¤à¥á®¢ ¬¥â®ª ¨ ¯à®æ¥¤ãà
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MMU 2 e, 18 ; áâà ¨æ 18 ¢ ¡ ªã 2 ¨ ¯à®¢¥àª £à ¨æë.
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ORG COMPILE_ADDR.MAIN
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INCLUDE 'src/bios/ROM/SETUP/MAIN.asm'
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INCLUDE 'bios/ROM/SETUP/MAIN.asm'
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;---------------------------------------
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ENDIF
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@ -83,7 +81,7 @@
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DEFINE+ IsInBIOS 1
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OUTPUT 'Build/Bin/EXP.BIN'
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ShowInfo 'EXP block Start', 0 ; !!!!! test
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INCLUDE 'src/bios/EXP/EXP.asm'
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INCLUDE 'bios/EXP/EXP.asm'
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ShowInfo 'EXP block End', 0 ; !!!!! test
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OUTEND
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;---------------------------------------
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@ -97,7 +95,7 @@
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DEFINE+ IsInBIOS 0
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OUTPUT 'Build/Bin/ROM.BIN'
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ShowInfo 'ROM block Start', 0 ; !!!!! test
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INCLUDE 'src/bios/ROM/ROM.asm'
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INCLUDE 'bios/ROM/ROM.asm'
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ShowInfo 'ROM block End', 0 ; !!!!! test
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OUTEND
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UNDEFINE IsInBIOS
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@ -135,7 +133,7 @@
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MMU 1 e, 1 ; áâà ¨æ 1 ¢ ¡ ªã 1 ¨ ¯à®¢¥àª £à ¨æë.
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ORG ROM_MAP.LOGO
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OUTPUT 'Build/Bin/LOGO.BIN'
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INCLUDE 'src/bios/logo/Set_Pictures.asm'
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INCLUDE 'bios/logo/Set_Pictures.asm'
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OUTEND
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;---------------------------------------
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;
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@ -2,7 +2,7 @@
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;------------[LUA functions]------------;
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includelua 'Shared_Includes/LUA/Functions.lua'
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;---------------------------------------;
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DEFINE PICTURE_FILE './src/bios/logo/psfathers.bmp'
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DEFINE PICTURE_FILE './bios/logo/psfathers.bmp'
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LUA PASS1
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@ -20,8 +20,8 @@
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*/
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INCLUDE 'shared/defines.inc'
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DEFINE IMG_RECOVERY 'src/bios/shared/recovery.img'
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;DEFINE IMG_RECOVERY 'src/bios/shared/recovery_tst.img'
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DEFINE IMG_RECOVERY 'bios/shared/recovery.img'
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;DEFINE IMG_RECOVERY 'bios/shared/recovery_tst.img'
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;
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;[--------------------------------------------------------------------------]
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@ -32,9 +32,9 @@
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ENDM
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;[--------------------------------------------------------------------------]
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DEFINE SP_128_BIN INCBIN 'src/ZX_ROMS/NEW/SP_128.BIN'
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DEFINE SP__48_BIN INCBIN 'src/ZX_ROMS/NEW/SP__48.BIN'
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DEFINE SP_TRDOS_BIN INCBIN 'src/ZX_ROMS/NEW/SP_TRDOS.BIN'
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DEFINE SP_128_BIN INCBIN 'ZX_ROMS/NEW/SP_128.BIN'
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DEFINE SP__48_BIN INCBIN 'ZX_ROMS/NEW/SP__48.BIN'
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DEFINE SP_TRDOS_BIN INCBIN 'ZX_ROMS/NEW/SP_TRDOS.BIN'
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;[--------------------------------------------------------------------------]
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MACRO ROM_BUILD bitstream
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@ -143,7 +143,7 @@
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.STRING: DB ACEX.RELOAD_STRING
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.Conf_header: include 'src/bios/Loader/bitstream_header.inc'
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.Conf_header: include 'bios/Loader/bitstream_header.inc'
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.Conf_header.length EQU $-.Conf_header
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;----------------------;
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54
bios/logo/Set_Pictures.asm
Normal file
54
bios/logo/Set_Pictures.asm
Normal file
@ -0,0 +1,54 @@
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;
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;------------[LUA functions]------------;
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includelua 'Shared_Includes/LUA/Functions.lua'
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;---------------------------------------;
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LUA PASS1
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-- <EFBFBD>஢¥à塞 BMP, ¤®áâ ñ¬ ¨§ ¥£® ¯ à ¬¥âàë, ०¥¬ ªã᪨
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bmp_width, bmp_height, bmp_image_size, bmp_image_offset, bmp_colors = Get_bmp8bit_values (sj.get_define("PICTURE_FILE"))
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if bmp_width ~= 128 then sj.error("Invalid BMP width", bmp_width) end
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if bmp_height ~= 72 then sj.error("Invalid BMP height", bmp_height) end
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if bmp_colors ~= 256 then sj.error("Invalid BMP number of colors", bmp_colors) end
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if not File_save(sj.get_define("PICTURE_FILE"), "./Build/Bin/LOGO_PAL.BIN", bmp_image_offset-1024, 1024) then sj.error("Palete save error!") end
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if not File_save(sj.get_define("PICTURE_FILE"), "./Build/Bin/LOGO_DAT.BIN", bmp_image_offset, bmp_image_size) then sj.error("Image data save error!") end
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ENDLUA
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LUA ALLPASS
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function make_pic_files (fileName, needPal, needPic)
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local fileNameBMP = "'" .. fileName .. ".bmp" .. "'"
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local fileNamePAL = fileName .. "_PAL.BIN"
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local fileNameDAT = fileName .. "_DAT.BIN"
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local bmp_width, bmp_height, bmp_image_size, bmp_image_offset, bmp_colors = Get_bmp8bit_values (fileNameBMP)
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if needPal == 1 then
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if bmp_width ~= 128 then sj.error(fileNameBMP .. "Invalid BMP width", bmp_width) end
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if bmp_height ~= 72 then sj.error(fileNameBMP .. "Invalid BMP height", bmp_height) end
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if bmp_colors ~= 256 then sj.error(fileNameBMP .. "Invalid BMP number of colors", bmp_colors) end
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if not File_save(fileNameBMP, fileNamePAL, bmp_image_offset-1024, 1024) then
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sj.error(fileNameBMP .. "Palete save error!")
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end
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end
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if needPic == 1 then
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local correctWidth = ((bmp_width*3)%4)+bmp_width
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if correctWidth > bmp_width then
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File_save(fileNameBMP, fileNameDAT, bmp_image_offset, bmp_image_size, bmp_width, correctWidth-bmp_width)
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else
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File_save(fileNameBMP, fileNameDAT, bmp_image_offset, bmp_image_size)
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end
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end
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print("Resolution: " .. bmp_width .. "x" .. bmp_height, fileNameDAT)
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end
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ENDLUA
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MODULE MAIN_LOGO
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Pallete:
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INCBIN 'Build/Bin/LOGO_PAL.BIN'
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.length EQU $-Pallete
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Raster:
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INCBIN 'Build/Bin/LOGO_DAT.BIN'
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.length EQU $-Raster
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ENDMODULE
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Before Width: | Height: | Size: 10 KiB After Width: | Height: | Size: 10 KiB |
|
Before Width: | Height: | Size: 10 KiB After Width: | Height: | Size: 10 KiB |
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Before Width: | Height: | Size: 10 KiB After Width: | Height: | Size: 10 KiB |
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Before Width: | Height: | Size: 10 KiB After Width: | Height: | Size: 10 KiB |
@ -194,7 +194,7 @@ SETUP_MAIN:
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DEPACK_DATA:
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DISP DEPACKER.WorkAddr
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MODULE UnPacker
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INCLUDE 'src/bios/ROM/SETUP/DEHRUST.asm' ; !TODO ᤥ« âì LUA ¢â®¢ë¡®à ¤¥ª®¬¯à¥áá®à ¨ ª®¬¯à¥áá®à
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INCLUDE 'bios/ROM/SETUP/DEHRUST.asm' ; !TODO ᤥ« âì LUA ¢â®¢ë¡®à ¤¥ª®¬¯à¥áá®à ¨ ª®¬¯à¥áá®à
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PackedMAIN: INCBIN 'Build/Bin/temp/MAIN.PAK'
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ENDMODULE
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ENT
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@ -205,7 +205,7 @@ DEPACK_DATA.length EQU $-DEPACK_DATA
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ELSE
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DISP COMPILE_ADDR.SETUP
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ShowInfo 'Setup block DISP start', 1 ; !!!!! test
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SETUP_MAIN: INCLUDE 'src/bios/ROM/SETUP/Main.asm'
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SETUP_MAIN: INCLUDE 'bios/ROM/SETUP/Main.asm'
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SETUP_MAIN.Size EQU $-SETUP_MAIN
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ShowInfo 'Setup block DISP end', 1 ; !!!!! test
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ENT
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@ -48,7 +48,7 @@
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; ENCODING "DOS"
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DEVICE ZXSPECTRUM4096 ; ¬®¤¥«ì á 4 ¬¥âà ¬¨ ¯ ¬ïâ¨
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MMU 2 e, 0 ; áâà ¨æ 0 ¢ ¡ ªã 2 ¨ ¯à®¢¥àª £à ¨æë.
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INCLUDE 'src/bios/shared/includes.inc'
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INCLUDE 'bios/shared/includes.inc'
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ORG COMPILE_ADDR.MAIN
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OUTPUT 'Build/Bin/temp/MAIN.BIN'
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ENDIF
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@ -1858,7 +1858,7 @@ init_zx_roms: DI
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;---------------------------------------
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INCLUDE 'src/bios/ROM/SETUP/messages.z80'
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INCLUDE 'bios/ROM/SETUP/messages.z80'
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;---------------------------------------
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;
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@ -1886,7 +1886,7 @@ STACK EQU #C000
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DISPLAY '-----[Set_Pictures Prebuild start]-----'
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MMU 1 e, 0 ; áâà ¨æ 0 ¢ ¡ ªã 0 ¨ ¯à®¢¥àª £à ¨æë.
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ORG ROM_MAP.LOGO
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INCLUDE 'src/bios/logo/Set_Pictures.asm'
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INCLUDE 'bios/logo/Set_Pictures.asm'
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DISPLAY '-----[Set_Pictures Prebuild done ]-----'
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ELSE
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MAIN_END_CODE_ADDRESS EQU $-1
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@ -10,7 +10,7 @@ RELEASEhotFIX EQU 0 ;
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DEFINE SP2000_Loader_Flag #0107 ;
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DEFINE IDE_Optimization 1 ; á«¥£ª ®¯â¨¬¨§¨àã¥â ¥ª®â®àë¥ ¯à®æ¥¤ãàë à ¡®âë á HDD
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DEFINE NeedSafePort_Y 1 ; ¥á«¨ 0, â® ¢ ०¨¬¥ ¡¥§ ªá¥«ï ¥ª®â®àë¥ ¯à®æ¥¤ãàë ¬®£ãâ § áà âì íªà
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DEFINE PICTURE_FILE './src/bios/logo/psfathers.bmp' ;
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DEFINE PICTURE_FILE './bios/logo/psfathers.bmp' ;
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DEFINE StandartCGApallete 1 ; <20>®¤ª«îç âì ¯ «¨âàã ¨§ standart_colors.inc
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DEFINE BitStream_SizeInPages 4 ;
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DEFINE USE_E1_SCANCODE 0 ;
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17
bios/shared/includes.inc
Normal file
17
bios/shared/includes.inc
Normal file
@ -0,0 +1,17 @@
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;
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;---------[All shared includes]---------
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INCLUDE 'bios/shared/DEFINES.INC' ; Shared defines
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INCLUDE 'Shared_Includes/structures/FileSystem.inc'
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INCLUDE 'Shared_Includes/structures/ATA_ATAPI.inc'
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INCLUDE 'bios/Loader/Loader.asm' ; Bitstream loader as macros
|
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INCLUDE 'bios/shared/CompMacro.asm' ; ¬ ªà®áë
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INCLUDE 'Shared_Includes/constants/SP2000.inc' ; ª®áâ âë
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||||
INCLUDE 'Shared_Includes/constants/zx_char_codes.inc' ; ª®áâ âë
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INCLUDE 'Shared_Includes/constants/zx_vars.inc' ;
|
||||
INCLUDE 'Shared_Includes/macroses/macros.z80'
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INCLUDE 'bios/ROM/MEM_MAP.inc' ; ª àâ ¯ ¬ïâ¨
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INCLUDE 'bios/shared/VERSION.inc' ; ‚¥àá¨ï EXP ¨ ROM
|
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INCLUDE 'Shared_Includes/constants/BIOS_EQU.inc'
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INCLUDE 'bios/ROM/BIOS.inc'
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;---------------------------------------
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||||
;
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||||
@ -1,568 +0,0 @@
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--
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||||
-- Copyright (C) 1988-2000 Altera Corporation
|
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-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
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-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
--
|
||||
CHIP acceler
|
||||
BEGIN
|
||||
DEVICE = EP1K30QC208-3;
|
||||
END;
|
||||
|
||||
DEFAULT_DEVICES
|
||||
BEGIN
|
||||
AUTO_DEVICE = EP1K100FC484-1;
|
||||
AUTO_DEVICE = EP1K100FC256-1;
|
||||
AUTO_DEVICE = EP1K100QC208-1;
|
||||
AUTO_DEVICE = EP1K50FC484-1;
|
||||
AUTO_DEVICE = EP1K50FC256-1;
|
||||
AUTO_DEVICE = EP1K50QC208-1;
|
||||
AUTO_DEVICE = EP1K50TC144-1;
|
||||
AUTO_DEVICE = EP1K30FC256-1;
|
||||
AUTO_DEVICE = EP1K30QC208-1;
|
||||
AUTO_DEVICE = EP1K30TC144-1;
|
||||
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
|
||||
END;
|
||||
|
||||
TIMING_POINT
|
||||
BEGIN
|
||||
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3;
|
||||
FREQUENCY = 200MHz;
|
||||
MAINTAIN_STABLE_SYNTHESIS = OFF;
|
||||
CUT_ALL_CLEAR_PRESET = ON;
|
||||
CUT_ALL_BIDIR = ON;
|
||||
END;
|
||||
|
||||
IGNORED_ASSIGNMENTS
|
||||
BEGIN
|
||||
FIT_IGNORE_TIMING = OFF;
|
||||
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
|
||||
IGNORE_DEVICE_ASSIGNMENTS = OFF;
|
||||
IGNORE_LC_ASSIGNMENTS = OFF;
|
||||
IGNORE_PIN_ASSIGNMENTS = OFF;
|
||||
IGNORE_CHIP_ASSIGNMENTS = OFF;
|
||||
IGNORE_TIMING_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
|
||||
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_DEVICE_OPTIONS
|
||||
BEGIN
|
||||
MAX7000B_ENABLE_VREFB = OFF;
|
||||
MAX7000B_ENABLE_VREFA = OFF;
|
||||
MAX7000B_VCCIO_IOBANK2 = 3.3V;
|
||||
MAX7000B_VCCIO_IOBANK1 = 3.3V;
|
||||
CONFIG_EPROM_PULLUP_RESISTOR = ON;
|
||||
CONFIG_EPROM_USER_CODE = FFFFFFFF;
|
||||
FLEX_CONFIGURATION_EPROM = AUTO;
|
||||
MAX7000AE_ENABLE_JTAG = ON;
|
||||
MAX7000AE_USER_CODE = FFFFFFFF;
|
||||
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
|
||||
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX6000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
|
||||
MULTIVOLT_IO = OFF;
|
||||
MAX7000S_ENABLE_JTAG = ON;
|
||||
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
|
||||
MAX7000S_USER_CODE = FFFF;
|
||||
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
|
||||
FLEX10K_JTAG_USER_CODE = 7F;
|
||||
ENABLE_INIT_DONE_OUTPUT = OFF;
|
||||
ENABLE_CHIP_WIDE_OE = OFF;
|
||||
ENABLE_CHIP_WIDE_RESET = OFF;
|
||||
nCEO = UNRESERVED;
|
||||
CLKUSR = UNRESERVED;
|
||||
ADD17 = UNRESERVED;
|
||||
ADD16 = UNRESERVED;
|
||||
ADD15 = UNRESERVED;
|
||||
ADD14 = UNRESERVED;
|
||||
ADD13 = UNRESERVED;
|
||||
ADD0_TO_ADD12 = UNRESERVED;
|
||||
SDOUT = RESERVED_DRIVES_OUT;
|
||||
RDCLK = UNRESERVED;
|
||||
RDYnBUSY = UNRESERVED;
|
||||
nWS_nRS_nCS_CS = UNRESERVED;
|
||||
DATA1_TO_DATA7 = UNRESERVED;
|
||||
DATA0 = RESERVED_TRI_STATED;
|
||||
FLEX8000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME = ACTIVE_SERIAL;
|
||||
DISABLE_TIME_OUT = OFF;
|
||||
ENABLE_DCLK_OUTPUT = OFF;
|
||||
RELEASE_CLEARS = OFF;
|
||||
AUTO_RESTART = OFF;
|
||||
USER_CLOCK = OFF;
|
||||
SECURITY_BIT = OFF;
|
||||
RESERVED_PINS_PERCENT = 0;
|
||||
RESERVED_LCELLS_PERCENT = 0;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
|
||||
BEGIN
|
||||
STYLE = FAST;
|
||||
DEVICE_FAMILY = ACEX1K;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
|
||||
AUTO_IMPLEMENT_IN_EAB = OFF;
|
||||
AUTO_OPEN_DRAIN_PINS = ON;
|
||||
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
|
||||
AUTO_REGISTER_PACKING = OFF;
|
||||
AUTO_FAST_IO = OFF;
|
||||
AUTO_GLOBAL_OE = ON;
|
||||
AUTO_GLOBAL_PRESET = ON;
|
||||
AUTO_GLOBAL_CLEAR = ON;
|
||||
AUTO_GLOBAL_CLOCK = ON;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
|
||||
OPTIMIZE_FOR_SPEED = 5;
|
||||
END;
|
||||
|
||||
COMPILER_PROCESSING_CONFIGURATION
|
||||
BEGIN
|
||||
USE_QUARTUS_FITTER = ON;
|
||||
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
|
||||
FITTER_SETTINGS = NORMAL;
|
||||
SMART_RECOMPILE = OFF;
|
||||
GENERATE_AHDL_TDO_FILE = OFF;
|
||||
RPT_FILE_USER_ASSIGNMENTS = ON;
|
||||
RPT_FILE_LCELL_INTERCONNECT = ON;
|
||||
RPT_FILE_HIERARCHY = ON;
|
||||
RPT_FILE_EQUATIONS = ON;
|
||||
LINKED_SNF_EXTRACTOR = OFF;
|
||||
OPTIMIZE_TIMING_SNF = OFF;
|
||||
TIMING_SNF_EXTRACTOR = ON;
|
||||
FUNCTIONAL_SNF_EXTRACTOR = OFF;
|
||||
DESIGN_DOCTOR_RULES = EPLD;
|
||||
DESIGN_DOCTOR = OFF;
|
||||
END;
|
||||
|
||||
COMPILER_INTERFACES_CONFIGURATION
|
||||
BEGIN
|
||||
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
|
||||
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
|
||||
EDIF_BUS_DELIMITERS = [];
|
||||
EDIF_FLATTEN_BUS = OFF;
|
||||
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
|
||||
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
|
||||
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
|
||||
EDIF_OUTPUT_USE_EDC = OFF;
|
||||
EDIF_INPUT_USE_LMF2 = OFF;
|
||||
EDIF_INPUT_USE_LMF1 = OFF;
|
||||
EDIF_OUTPUT_GND = GND;
|
||||
EDIF_OUTPUT_VCC = VCC;
|
||||
EDIF_INPUT_GND = GND;
|
||||
EDIF_INPUT_VCC = VCC;
|
||||
EDIF_OUTPUT_EDC_FILE = *.edc;
|
||||
EDIF_INPUT_LMF2 = *.lmf;
|
||||
EDIF_INPUT_LMF1 = *.lmf;
|
||||
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
|
||||
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
|
||||
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
|
||||
VHDL_FLATTEN_BUS = OFF;
|
||||
VERILOG_FLATTEN_BUS = OFF;
|
||||
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
VHDL_WRITER_VERSION = VHDL87;
|
||||
VHDL_READER_VERSION = VHDL87;
|
||||
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
|
||||
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
|
||||
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
|
||||
SYNOPSYS_DESIGNWARE = OFF;
|
||||
SYNOPSYS_COMPILER = DESIGN;
|
||||
USE_SYNOPSYS_SYNTHESIS = OFF;
|
||||
VHDL_NETLIST_WRITER = OFF;
|
||||
VERILOG_NETLIST_WRITER = OFF;
|
||||
XNF_GENERATE_AHDL_TDX_FILE = ON;
|
||||
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
|
||||
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
|
||||
EDIF_OUTPUT_VERSION = 200;
|
||||
EDIF_NETLIST_WRITER = OFF;
|
||||
END;
|
||||
|
||||
CUSTOM_DESIGN_DOCTOR_RULES
|
||||
BEGIN
|
||||
MASTER_RESET = OFF;
|
||||
EXPANDER_NETWORKS = ON;
|
||||
RACE_CONDITIONS = ON;
|
||||
DELAY_CHAINS = ON;
|
||||
ASYNCHRONOUS_INPUTS = ON;
|
||||
PRESET_CLEAR_NETWORKS = ON;
|
||||
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
|
||||
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
|
||||
MULTI_CLOCK_NETWORKS = ON;
|
||||
MULTI_LEVEL_CLOCKS = ON;
|
||||
GATED_CLOCKS = ON;
|
||||
RIPPLE_CLOCKS = ON;
|
||||
END;
|
||||
|
||||
SIMULATOR_CONFIGURATION
|
||||
BEGIN
|
||||
END_TIME = 5.0us;
|
||||
BIDIR_PIN = STRONG;
|
||||
START_TIME = 0.0ns;
|
||||
GLITCH_TIME = 0.0ns;
|
||||
GLITCH = OFF;
|
||||
OSCILLATION_TIME = 0.0ns;
|
||||
OSCILLATION = OFF;
|
||||
CHECK_OUTPUTS = OFF;
|
||||
SETUP_HOLD = OFF;
|
||||
USE_DEVICE = OFF;
|
||||
END;
|
||||
|
||||
TIMING_ANALYZER_CONFIGURATION
|
||||
BEGIN
|
||||
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
|
||||
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
|
||||
LIST_PATH_FREQUENCY = 10MHz;
|
||||
LIST_PATH_COUNT = 10;
|
||||
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
|
||||
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
|
||||
INCLUDE_PATHS_LESS_THAN = OFF;
|
||||
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
|
||||
INCLUDE_PATHS_GREATER_THAN = OFF;
|
||||
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
|
||||
CELL_WIDTH = 18;
|
||||
LIST_ONLY_LONGEST_PATH = ON;
|
||||
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
|
||||
CUT_OFF_IO_PIN_FEEDBACK = ON;
|
||||
AUTO_RECALCULATE = OFF;
|
||||
END;
|
||||
|
||||
OTHER_CONFIGURATION
|
||||
BEGIN
|
||||
LAST_MAXPLUS2_VERSION = 10.0;
|
||||
ROW_PINS_LCELL_INSERT = ON;
|
||||
CARRY_OUT_PINS_LCELL_INSERT = OFF;
|
||||
NORMAL_LCELL_INSERT = ON;
|
||||
EXPLICIT_FAMILY = 1;
|
||||
FLEX_10K_52_COLUMNS = 40;
|
||||
DEFAULT_9K_EXP_PER_LCELL = 1/2;
|
||||
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
|
||||
LCELLS_PER_ROW_PERCENT = 100;
|
||||
FAN_IN_PER_LCELL_PERCENT = 100;
|
||||
EXP_PER_LCELL_PERCENT = 100;
|
||||
ROW_PINS_PERCENT = 50;
|
||||
ORIGINAL_MAXPLUS2_VERSION = 9.6;
|
||||
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = ON;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
||||
BEGIN
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = AUTO;
|
||||
CASCADE_CHAIN = AUTO;
|
||||
MINIMIZATION = FULL;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = MANUAL;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = MANUAL;
|
||||
END;
|
||||
|
||||
@ -1,26 +0,0 @@
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
|
||||
-- MAX+plus II Include File
|
||||
-- Version 10.0 9/14/2000
|
||||
-- Created: Fri Jan 25 12:59:19 2002
|
||||
|
||||
FUNCTION acceler (clk42, /reset, ct[2..0], ras, cas, clk_z80, mc_end, mc_begin, mc_type, mc_write, ai[15..0], di[7..0], /io, /rd, /wr, /mr, /rf, /m1, /iom, dcp[7..0], mdi[15..0], acc_ena, hddr[7..0], hdd_flip)
|
||||
RETURNS (continue, ao[15..0], do[7..0], mdo[15..0], md[7..0], g_line[7..0], glisser, acc_on, double_cas, acc_dir[7..0]);
|
||||
@ -1,374 +0,0 @@
|
||||
|
||||
TITLE "ACCELERATOR";
|
||||
|
||||
INCLUDE "lpm_ram_dp";
|
||||
|
||||
SUBDESIGN acceler
|
||||
(
|
||||
CLK42 : INPUT;
|
||||
/RESET : INPUT;
|
||||
CT[2..0] : INPUT;
|
||||
|
||||
RAS : INPUT;
|
||||
CAS : INPUT;
|
||||
CLK_Z80 : INPUT;
|
||||
|
||||
CONTINUE : OUTPUT;
|
||||
|
||||
MC_END : INPUT;
|
||||
MC_BEGIN : INPUT;
|
||||
MC_TYPE : INPUT;
|
||||
MC_WRITE : INPUT;
|
||||
-- MCA[1..0] : INPUT;
|
||||
|
||||
AI[15..0] : INPUT;
|
||||
DI[7..0] : INPUT;
|
||||
|
||||
AO[15..0] : OUTPUT;
|
||||
DO[7..0] : OUTPUT;
|
||||
|
||||
/IO : INPUT;
|
||||
/RD : INPUT;
|
||||
/WR : INPUT;
|
||||
/MR : INPUT;
|
||||
/RF : INPUT;
|
||||
/M1 : INPUT;
|
||||
/IOM : INPUT;
|
||||
|
||||
DCP[7..0] : INPUT;
|
||||
|
||||
MDI[15..0] : INPUT;
|
||||
MDO[15..0] : OUTPUT;
|
||||
MD[7..0] : OUTPUT;
|
||||
|
||||
G_LINE[7..0]: OUTPUT;
|
||||
|
||||
GLISSER : OUTPUT;
|
||||
|
||||
ACC_ON : OUTPUT;
|
||||
|
||||
ACC_ENA : INPUT;
|
||||
|
||||
DOUBLE_CAS : OUTPUT;
|
||||
|
||||
HDDR[7..0] : INPUT;
|
||||
HDD_FLIP : INPUT;
|
||||
|
||||
ACC_DIR[7..0] : OUTPUT;
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
RAM : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8);
|
||||
|
||||
DO[7..0] : DFFE;
|
||||
MDO[15..0] : DFFE;
|
||||
|
||||
PRF_CMD : DFFE;
|
||||
ED_CMD : DFFE;
|
||||
CB_CMD : DFFE;
|
||||
ID_CMD : DFFE;
|
||||
IN_OUT_CMD : DFFE;
|
||||
|
||||
CORRECT_1F : NODE;
|
||||
|
||||
ACC_BLK : DFF;
|
||||
|
||||
RETI : DFFE;
|
||||
RETN : DFFE;
|
||||
|
||||
AA[15..0] : DFFE;
|
||||
|
||||
RGACC[7..0] : DFFE;
|
||||
AGR[7..0] : DFFE;
|
||||
ACC_CNT[7..0] : DFFE;
|
||||
|
||||
START_ACC : NODE;
|
||||
ACC_END : DFFE;
|
||||
FN_ACC[2..0]: DFFE;
|
||||
ACC_MODE[3..0] : DFFE;
|
||||
|
||||
MD[7..0] : LCELL;
|
||||
XMD[7..0] : DFF;
|
||||
XMDH[7..0] : DFF;
|
||||
|
||||
ACC_DIR[7..0] : LCELL;
|
||||
|
||||
/M1M : NODE;
|
||||
|
||||
ACC_GO : NODE;
|
||||
ACC_GO_1 : NODE;
|
||||
|
||||
RAM_WR : NODE;
|
||||
|
||||
STATE_EI : DFFE;
|
||||
|
||||
-- HDDR[7..0] : DFFE;
|
||||
|
||||
XAGR[7..0] : DFFE;
|
||||
AAGR[9..0] : DFFE;
|
||||
XCNT[7..0] : DFFE;
|
||||
ALT_ACC : NODE;
|
||||
|
||||
RAM_ADR[7..0] : NODE;
|
||||
ACC_C : NODE;
|
||||
WR_C7 : NODE;
|
||||
|
||||
XCNT_AGR[15..0] : NODE;
|
||||
|
||||
MDOX[7..0] : DFF;
|
||||
MDOY[7..0] : DFF;
|
||||
|
||||
GLISS_R : DFF;
|
||||
|
||||
ACC_TIME : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
ACC_ON = ACC_DIR0;
|
||||
|
||||
/M1M = DFF(!/M1,CLK_Z80,/RESET,);
|
||||
|
||||
PRF_CMD.clk = /MR;
|
||||
PRF_CMD.ena = /M1M;
|
||||
PRF_CMD.d = (DI[] == B"11XX1XX1") &
|
||||
((DI[] == B"XX00X01X") or -- CB
|
||||
(DI[] == B"XX01X10X") or -- DD
|
||||
(DI[] == B"XX10X10X") or -- ED
|
||||
(DI[] == B"XX11X10X")); -- FD
|
||||
|
||||
-- === interrupt === 0 - disable; 1 - enable
|
||||
|
||||
STATE_EI.clk = /MR;
|
||||
STATE_EI.ena = /M1M & !PRF_CMD & (DI[] == B"1111X011");
|
||||
STATE_EI.d = DI3;
|
||||
|
||||
-- RETI comand
|
||||
|
||||
ED_CMD.clk = /MR;
|
||||
ED_CMD.ena = /M1M;
|
||||
ED_CMD.d = (DI[] == H"ED");
|
||||
|
||||
RETI.clk = /MR;
|
||||
RETI.ena = /M1M;
|
||||
RETI.d = ED_CMD & (DI[] == H"4D");
|
||||
|
||||
-- "1" on the RETI triger is the end of interupt sycle.
|
||||
|
||||
RETN.clk = /MR;
|
||||
RETN.ena = /M1M;
|
||||
RETN.d = ED_CMD & (DI[] == H"45");
|
||||
|
||||
-- The end of NMI sycle.
|
||||
|
||||
ACC_BLK.clk = /M1;
|
||||
ACC_BLK.d = DFF(((/IO & ACC_BLK) or (!ACC_BLK & RETI)),CLK_Z80,,);
|
||||
ACC_BLK.prn = /RESET & ACC_MODE3;
|
||||
|
||||
CB_CMD.clk = /MR;
|
||||
ID_CMD.clk = /MR;
|
||||
CB_CMD.ena = /M1M;
|
||||
ID_CMD.ena = /M1M;
|
||||
|
||||
CB_CMD.d = (DI[] == H"CB");
|
||||
ID_CMD.d = (DI[] == B"11X11101");
|
||||
|
||||
IN_OUT_CMD.clk = /MR;
|
||||
IN_OUT_CMD.ena = /M1M;
|
||||
IN_OUT_CMD.d = (DI[] == B"1101X011") & !PRF_CMD; -- D3/DB
|
||||
IN_OUT_CMD.clrn = /IO;
|
||||
|
||||
CORRECT_1F = LCELL(IN_OUT_CMD & (DO[] == H"1F") & !/MR & !/RD);
|
||||
DO[4..3].clrn = !CORRECT_1F;
|
||||
|
||||
ACC_GO = DFFE((CAS or START_ACC),CLK42,,(!/MR & /M1),CT1);
|
||||
ACC_GO_1 = DFF(ACC_GO,CLK42,,);
|
||||
|
||||
-- == accelerator number ==
|
||||
|
||||
RGACC[].clk = /MR;
|
||||
RGACC[].ena = DFF((/M1 & /RF & ACC_DIR3),CLK_Z80,,);
|
||||
RGACC[].d = DI[];
|
||||
|
||||
-- == accelerator grafic line ==
|
||||
|
||||
AGR[].clk = CLK42;
|
||||
AGR[].ena = !DFF((/IOM or /WR or !DFF((DCP[] == B"1100X100"),CLK42,,)),CLK42,,) or
|
||||
!(!ACC_DIR4 or ACC_GO or !ACC_GO_1);
|
||||
|
||||
CASE DFF(START_ACC,CLK42,,) IS
|
||||
WHEN 0 => AGR[].d = AGR[] + 1;
|
||||
WHEN 1 => AGR[].d = DI[];
|
||||
END CASE;
|
||||
|
||||
AGR[].clrn = /RESET;
|
||||
|
||||
G_LINE[] = AGR[];
|
||||
|
||||
-- == accelerator counter ==
|
||||
|
||||
ACC_C = (!ACC_GO & DFF(((CT0 & !/RD) or (CT1 & !/WR)),CLK42,,));
|
||||
ACC_CNT[].clk = CLK42;
|
||||
-- ACC_CNT[].ena = START_ACC or (ACC_C & ACC_DIR2);
|
||||
ACC_CNT[].ena = LCELL(START_ACC or (ACC_C & ACC_DIR2));
|
||||
|
||||
CASE DFF(START_ACC,CLK42,,) IS
|
||||
WHEN 1 => ACC_CNT[].d = RGACC[];
|
||||
WHEN 0 => ACC_CNT[].d = ACC_CNT[] - 1;
|
||||
END CASE;
|
||||
|
||||
WR_C7 = DFF((/IOM or DFF(!/IOM,CLK42,,) or /WR or DFF(!(DCP[] == B"1100X111"),CLK42,,)),CLK42,,);
|
||||
ALT_ACC = DFF(VCC,WR_C7,/RESET,);
|
||||
|
||||
(AAGR[].ena,XCNT[].ena,XAGR[].ena) = LCELL(!WR_C7 or (ACC_DIR1 & ACC_C));
|
||||
(AAGR[].clk,XCNT[].clk,XAGR[].clk) = CLK42;
|
||||
|
||||
XCNT_AGR[15..0] = (XCNT[],XAGR[]) + (B"000000",AAGR[]);
|
||||
|
||||
CASE !DFF(START_ACC,CLK42,,) IS
|
||||
WHEN 1 => AAGR[].d = AAGR[];
|
||||
(XCNT[].d,XAGR[].d) = XCNT_AGR[15..0];
|
||||
WHEN 0 => AAGR[].d = (AI9,AI8,DI[]);
|
||||
(XCNT[].d,XAGR[].d) = (B"00",AI[15..10],B"00000000");
|
||||
END CASE;
|
||||
|
||||
-- == accelerator dir ==
|
||||
|
||||
START_ACC = LCELL(LCELL(/MR or !/M1 or !/RF or !ACC_BLK) or (!ACC_DIR0 or MC_TYPE));
|
||||
|
||||
DOUBLE_CAS= LCELL(ACC_DIR6 & !START_ACC);
|
||||
|
||||
ACC_END.clk = CLK42;
|
||||
ACC_END.ena = !ACC_GO & ACC_GO_1;
|
||||
ACC_END.prn = /M1;
|
||||
ACC_END.d = (ACC_CNT[] == 1) or !ACC_DIR2;
|
||||
|
||||
CONTINUE = ACC_END;
|
||||
|
||||
CASE ACC_MODE[2..0] IS
|
||||
WHEN 0 => ACC_DIR[] = B"00000000"; % LD B,B %
|
||||
WHEN 1 => ACC_DIR[] = B"00100101"; % LD C,C % % fill by constant %
|
||||
WHEN 2 => ACC_DIR[] = B"00001001"; % LD D,D % % load count accelerator %
|
||||
WHEN 3 => ACC_DIR[] = B"00010101"; % LD E,E % % fill by constant VERTICAL %
|
||||
WHEN 4 => ACC_DIR[] = B"01000001"; % LD H,H % % duble byte fn %
|
||||
WHEN 5 => ACC_DIR[] = B"00100111"; % LD L,L % % copy line %
|
||||
WHEN 6 => ACC_DIR[] = B"00000000"; % HALT %
|
||||
WHEN 7 => ACC_DIR[] = B"00010111"; % LD A,A % % copy line VERTICAL %
|
||||
END CASE;
|
||||
|
||||
-- == accelerator mode ==
|
||||
|
||||
ACC_MODE[].clk = /MR;
|
||||
ACC_MODE[].ena = DFF((!/M1 & !PRF_CMD &
|
||||
LCELL((DI[] == B"XXX00X00") or
|
||||
(DI[] == B"XXX01X01") or
|
||||
(DI[] == B"XXX10X10") or
|
||||
(DI[] == B"XXX11X11")) &
|
||||
LCELL((DI[] == B"010XX0XX") or
|
||||
(DI[] == B"011XX1XX"))),CLK_Z80,,);
|
||||
ACC_MODE[].d = (VCC,DI[2..0]);
|
||||
ACC_MODE[2..0].clrn = /RESET & ACC_ENA;
|
||||
ACC_MODE[3].clrn = /RESET & !DFF(ACC_MODE3,CLK_Z80,,);
|
||||
|
||||
-- == accelerator datas ==
|
||||
|
||||
CASE DFFE(AA0,CLK42,,,(CT2 & CT1)) IS
|
||||
WHEN 0 => MD[] = MDI[7..0];
|
||||
-- GLISSER = DFF((MDO[7..0] == H"FF"),CLK42,,);
|
||||
WHEN 1 => MD[] = MDI[15..8];
|
||||
-- GLISSER = DFF((MDO[15..8] == H"FF"),CLK42,,);
|
||||
END CASE;
|
||||
|
||||
GLISS_R.clk = CLK42;
|
||||
CASE ACC_DIR1 IS
|
||||
WHEN 0 => GLISS_R = LCELL(DI[] == H"FF");
|
||||
WHEN 1 => GLISS_R = LCELL(RAM.q[7..4] == H"F") & LCELL(RAM.q[3..0] == H"F");
|
||||
END CASE;
|
||||
GLISSER = GLISS_R;
|
||||
|
||||
-- MDO[].clk = !CLK42;
|
||||
MDO[].clk = CLK42;
|
||||
|
||||
MDO[].ena = CAS;
|
||||
|
||||
MDOX[].clk = CLK42;
|
||||
MDOY[].clk = CLK42;
|
||||
|
||||
CASE LCELL(MC_END & HDD_FLIP) IS
|
||||
WHEN 0 => MDOX[7..0] = DI[];
|
||||
WHEN 1 => MDOX[7..0] = HDDR[];
|
||||
END CASE;
|
||||
|
||||
CASE ACC_DIR6 IS
|
||||
WHEN 0 => MDOY[7..0] = DI[];
|
||||
WHEN 1 => MDOY[7..0] = HDDR[];
|
||||
END CASE;
|
||||
|
||||
CASE LCELL(/IO & ACC_DIR1) IS
|
||||
WHEN 0 => MDO[].d = (MDOY[],MDOX[]);
|
||||
WHEN 1 => MDO[].d = (RAM.q[7..0],RAM.q[7..0]);
|
||||
END CASE;
|
||||
|
||||
DO[].clk = DFF(MC_END,!CLK42,,);
|
||||
-- DO[].clk = !CLK42;
|
||||
DO[].ena = VCC;
|
||||
-- DO[].ena = DFF(!MC_END,CLK42,,);
|
||||
DO[].d = MD[];
|
||||
|
||||
-- == accelerator functions ==
|
||||
|
||||
FN_ACC[].clk = /MR;
|
||||
FN_ACC[].ena = /M1M;
|
||||
FN_ACC[].d = LCELL(DI7 & !DI6 & !PRF_CMD) & !(DI[5..3]);
|
||||
|
||||
XMDH[].clk = !CLK42;
|
||||
XMDH[] = MDI[15..8];
|
||||
|
||||
XMD[].clk = !CLK42;
|
||||
CASE FN_ACC[1..0] IS
|
||||
WHEN 0 =>
|
||||
XMD[] = MD[]; % BE %
|
||||
WHEN 1 =>
|
||||
XMD[] = MD[] or RAM.q[7..0]; % B6 %
|
||||
WHEN 2 =>
|
||||
XMD[] = MD[] xor RAM.q[7..0]; % AE %
|
||||
WHEN 3 =>
|
||||
XMD[] = MD[] & RAM.q[7..0]; % A6 %
|
||||
END CASE;
|
||||
|
||||
CASE ALT_ACC IS
|
||||
WHEN 0 => RAM_ADR[] = ACC_CNT[];
|
||||
WHEN 1 => RAM_ADR[] = XCNT[];
|
||||
END CASE;
|
||||
|
||||
ACC_TIME = LCELL((!ACC_END or !DFFE(ACC_END,CLK42,,,(CT1 & CT2))));
|
||||
|
||||
-- RAM_WR = DFF((!/RD & (!ACC_GO & CT0) & ACC_TIME),CLK42,,);
|
||||
RAM_WR = DFF((!/RD & (!ACC_GO & CT0) & ACC_DIR1),CLK42,,);
|
||||
|
||||
RAM.wren = RAM_WR;
|
||||
RAM.data[] = (XMD[],XMD[]);
|
||||
-- RAM.wraddress[] = ACC_CNT[];
|
||||
RAM.wraddress[] = RAM_ADR[];
|
||||
RAM.wrclock = CLK42;
|
||||
RAM.wrclken = VCC;
|
||||
RAM.rden = VCC;
|
||||
-- RAM.rdaddress[] = ACC_CNT[];
|
||||
RAM.rdaddress[] = RAM_ADR[];
|
||||
RAM.rdclock = CLK42;
|
||||
RAM.rdclken = VCC;
|
||||
|
||||
AA[].clk = CLK42;
|
||||
-- AA[].ena = START_ACC or (ACC_DIR5 & !ACC_GO & ACC_GO_1);
|
||||
AA[].ena = LCELL(START_ACC or (ACC_DIR5 & !(CAS or START_ACC) & (ACC_GO or (ACC_GO_1 & ACC_DIR6))));
|
||||
|
||||
CASE DFF(START_ACC,CLK42,,) IS
|
||||
WHEN 1 => AA[].d = AI[];
|
||||
-- WHEN 0 => AA[].d = AA[] + (B"00000000000000",ACC_DIR6,!ACC_DIR6);
|
||||
WHEN 0 => AA[].d = AA[] + 1;
|
||||
END CASE;
|
||||
|
||||
AO[] = (AA[15..0]);
|
||||
|
||||
END;
|
||||
|
||||
@ -1,578 +0,0 @@
|
||||
--
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
--
|
||||
CHIP ay
|
||||
BEGIN
|
||||
DEVICE = EP1K30QC208-3;
|
||||
END;
|
||||
|
||||
DEFAULT_DEVICES
|
||||
BEGIN
|
||||
AUTO_DEVICE = EP1K100FC484-1;
|
||||
AUTO_DEVICE = EP1K100FC256-1;
|
||||
AUTO_DEVICE = EP1K100QC208-1;
|
||||
AUTO_DEVICE = EP1K50FC484-1;
|
||||
AUTO_DEVICE = EP1K50FC256-1;
|
||||
AUTO_DEVICE = EP1K50QC208-1;
|
||||
AUTO_DEVICE = EP1K50TC144-1;
|
||||
AUTO_DEVICE = EP1K30FC256-1;
|
||||
AUTO_DEVICE = EP1K30QC208-1;
|
||||
AUTO_DEVICE = EP1K30TC144-1;
|
||||
AUTO_DEVICE = EP1K10FC256-1;
|
||||
AUTO_DEVICE = EP1K10QC208-1;
|
||||
AUTO_DEVICE = EP1K10TC144-1;
|
||||
AUTO_DEVICE = EP1K10TC100-1;
|
||||
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
|
||||
END;
|
||||
|
||||
TIMING_POINT
|
||||
BEGIN
|
||||
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3;
|
||||
FREQUENCY = 100MHz;
|
||||
MAINTAIN_STABLE_SYNTHESIS = OFF;
|
||||
CUT_ALL_CLEAR_PRESET = ON;
|
||||
CUT_ALL_BIDIR = ON;
|
||||
END;
|
||||
|
||||
IGNORED_ASSIGNMENTS
|
||||
BEGIN
|
||||
FIT_IGNORE_TIMING = ON;
|
||||
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
|
||||
IGNORE_DEVICE_ASSIGNMENTS = OFF;
|
||||
IGNORE_LC_ASSIGNMENTS = OFF;
|
||||
IGNORE_PIN_ASSIGNMENTS = OFF;
|
||||
IGNORE_CHIP_ASSIGNMENTS = OFF;
|
||||
IGNORE_TIMING_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
|
||||
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_DEVICE_OPTIONS
|
||||
BEGIN
|
||||
MAX7000B_ENABLE_VREFB = OFF;
|
||||
MAX7000B_ENABLE_VREFA = OFF;
|
||||
MAX7000B_VCCIO_IOBANK2 = 3.3V;
|
||||
MAX7000B_VCCIO_IOBANK1 = 3.3V;
|
||||
CONFIG_EPROM_PULLUP_RESISTOR = ON;
|
||||
CONFIG_EPROM_USER_CODE = FFFFFFFF;
|
||||
FLEX_CONFIGURATION_EPROM = AUTO;
|
||||
MAX7000AE_ENABLE_JTAG = ON;
|
||||
MAX7000AE_USER_CODE = FFFFFFFF;
|
||||
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
|
||||
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX6000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
|
||||
MULTIVOLT_IO = OFF;
|
||||
MAX7000S_ENABLE_JTAG = ON;
|
||||
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
|
||||
MAX7000S_USER_CODE = FFFF;
|
||||
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
|
||||
FLEX10K_JTAG_USER_CODE = 7F;
|
||||
ENABLE_INIT_DONE_OUTPUT = OFF;
|
||||
ENABLE_CHIP_WIDE_OE = OFF;
|
||||
ENABLE_CHIP_WIDE_RESET = OFF;
|
||||
nCEO = UNRESERVED;
|
||||
CLKUSR = UNRESERVED;
|
||||
ADD17 = UNRESERVED;
|
||||
ADD16 = UNRESERVED;
|
||||
ADD15 = UNRESERVED;
|
||||
ADD14 = UNRESERVED;
|
||||
ADD13 = UNRESERVED;
|
||||
ADD0_TO_ADD12 = UNRESERVED;
|
||||
SDOUT = RESERVED_DRIVES_OUT;
|
||||
RDCLK = UNRESERVED;
|
||||
RDYnBUSY = UNRESERVED;
|
||||
nWS_nRS_nCS_CS = UNRESERVED;
|
||||
DATA1_TO_DATA7 = UNRESERVED;
|
||||
DATA0 = RESERVED_TRI_STATED;
|
||||
FLEX8000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME = ACTIVE_SERIAL;
|
||||
DISABLE_TIME_OUT = OFF;
|
||||
ENABLE_DCLK_OUTPUT = OFF;
|
||||
RELEASE_CLEARS = OFF;
|
||||
AUTO_RESTART = OFF;
|
||||
USER_CLOCK = OFF;
|
||||
SECURITY_BIT = OFF;
|
||||
RESERVED_PINS_PERCENT = 0;
|
||||
RESERVED_LCELLS_PERCENT = 0;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
|
||||
BEGIN
|
||||
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
|
||||
AUTO_IMPLEMENT_IN_EAB = OFF;
|
||||
AUTO_OPEN_DRAIN_PINS = ON;
|
||||
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
|
||||
AUTO_REGISTER_PACKING = OFF;
|
||||
DEVICE_FAMILY = ACEX1K;
|
||||
STYLE = NORMAL;
|
||||
AUTO_FAST_IO = OFF;
|
||||
AUTO_GLOBAL_OE = ON;
|
||||
AUTO_GLOBAL_PRESET = ON;
|
||||
AUTO_GLOBAL_CLEAR = ON;
|
||||
AUTO_GLOBAL_CLOCK = ON;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
|
||||
OPTIMIZE_FOR_SPEED = 5;
|
||||
END;
|
||||
|
||||
COMPILER_PROCESSING_CONFIGURATION
|
||||
BEGIN
|
||||
USE_QUARTUS_FITTER = ON;
|
||||
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
|
||||
FITTER_SETTINGS = NORMAL;
|
||||
SMART_RECOMPILE = OFF;
|
||||
GENERATE_AHDL_TDO_FILE = OFF;
|
||||
RPT_FILE_USER_ASSIGNMENTS = ON;
|
||||
RPT_FILE_LCELL_INTERCONNECT = ON;
|
||||
RPT_FILE_HIERARCHY = ON;
|
||||
RPT_FILE_EQUATIONS = ON;
|
||||
LINKED_SNF_EXTRACTOR = OFF;
|
||||
OPTIMIZE_TIMING_SNF = OFF;
|
||||
TIMING_SNF_EXTRACTOR = ON;
|
||||
FUNCTIONAL_SNF_EXTRACTOR = OFF;
|
||||
DESIGN_DOCTOR_RULES = EPLD;
|
||||
DESIGN_DOCTOR = OFF;
|
||||
END;
|
||||
|
||||
COMPILER_INTERFACES_CONFIGURATION
|
||||
BEGIN
|
||||
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
|
||||
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
|
||||
EDIF_BUS_DELIMITERS = [];
|
||||
EDIF_FLATTEN_BUS = OFF;
|
||||
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
|
||||
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
|
||||
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
|
||||
EDIF_OUTPUT_USE_EDC = OFF;
|
||||
EDIF_INPUT_USE_LMF2 = OFF;
|
||||
EDIF_INPUT_USE_LMF1 = OFF;
|
||||
EDIF_OUTPUT_GND = GND;
|
||||
EDIF_OUTPUT_VCC = VCC;
|
||||
EDIF_INPUT_GND = GND;
|
||||
EDIF_INPUT_VCC = VCC;
|
||||
EDIF_OUTPUT_EDC_FILE = *.edc;
|
||||
EDIF_INPUT_LMF2 = *.lmf;
|
||||
EDIF_INPUT_LMF1 = *.lmf;
|
||||
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
|
||||
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
|
||||
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
|
||||
VHDL_FLATTEN_BUS = OFF;
|
||||
VERILOG_FLATTEN_BUS = OFF;
|
||||
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
VHDL_WRITER_VERSION = VHDL93;
|
||||
VHDL_READER_VERSION = VHDL93;
|
||||
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
|
||||
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
|
||||
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
|
||||
SYNOPSYS_DESIGNWARE = OFF;
|
||||
SYNOPSYS_COMPILER = DESIGN;
|
||||
USE_SYNOPSYS_SYNTHESIS = OFF;
|
||||
VHDL_NETLIST_WRITER = OFF;
|
||||
VERILOG_NETLIST_WRITER = OFF;
|
||||
XNF_GENERATE_AHDL_TDX_FILE = ON;
|
||||
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
|
||||
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
|
||||
EDIF_OUTPUT_VERSION = 200;
|
||||
EDIF_NETLIST_WRITER = OFF;
|
||||
END;
|
||||
|
||||
CUSTOM_DESIGN_DOCTOR_RULES
|
||||
BEGIN
|
||||
MASTER_RESET = OFF;
|
||||
EXPANDER_NETWORKS = ON;
|
||||
RACE_CONDITIONS = ON;
|
||||
DELAY_CHAINS = ON;
|
||||
ASYNCHRONOUS_INPUTS = ON;
|
||||
PRESET_CLEAR_NETWORKS = ON;
|
||||
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
|
||||
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
|
||||
MULTI_CLOCK_NETWORKS = ON;
|
||||
MULTI_LEVEL_CLOCKS = ON;
|
||||
GATED_CLOCKS = ON;
|
||||
RIPPLE_CLOCKS = ON;
|
||||
END;
|
||||
|
||||
SIMULATOR_CONFIGURATION
|
||||
BEGIN
|
||||
BIDIR_PIN = STRONG;
|
||||
END_TIME = 0.0ns;
|
||||
START_TIME = 0.0ns;
|
||||
GLITCH_TIME = 0.0ns;
|
||||
GLITCH = OFF;
|
||||
OSCILLATION_TIME = 0.0ns;
|
||||
OSCILLATION = OFF;
|
||||
CHECK_OUTPUTS = OFF;
|
||||
SETUP_HOLD = OFF;
|
||||
USE_DEVICE = OFF;
|
||||
END;
|
||||
|
||||
TIMING_ANALYZER_CONFIGURATION
|
||||
BEGIN
|
||||
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
|
||||
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
|
||||
LIST_PATH_FREQUENCY = 10MHz;
|
||||
LIST_PATH_COUNT = 10;
|
||||
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
|
||||
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
|
||||
INCLUDE_PATHS_LESS_THAN = OFF;
|
||||
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
|
||||
INCLUDE_PATHS_GREATER_THAN = OFF;
|
||||
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
|
||||
CELL_WIDTH = 18;
|
||||
LIST_ONLY_LONGEST_PATH = ON;
|
||||
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
|
||||
CUT_OFF_IO_PIN_FEEDBACK = ON;
|
||||
AUTO_RECALCULATE = OFF;
|
||||
END;
|
||||
|
||||
OTHER_CONFIGURATION
|
||||
BEGIN
|
||||
ROW_PINS_LCELL_INSERT = ON;
|
||||
CARRY_OUT_PINS_LCELL_INSERT = OFF;
|
||||
NORMAL_LCELL_INSERT = ON;
|
||||
EXPLICIT_FAMILY = 1;
|
||||
LAST_MAXPLUS2_VERSION = 10.0;
|
||||
FLEX_10K_52_COLUMNS = 40;
|
||||
DEFAULT_9K_EXP_PER_LCELL = 1/2;
|
||||
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
|
||||
LCELLS_PER_ROW_PERCENT = 100;
|
||||
FAN_IN_PER_LCELL_PERCENT = 100;
|
||||
EXP_PER_LCELL_PERCENT = 100;
|
||||
ROW_PINS_PERCENT = 50;
|
||||
ORIGINAL_MAXPLUS2_VERSION = 10.0;
|
||||
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = ON;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = AUTO;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = AUTO;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = MANUAL;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = MANUAL;
|
||||
END;
|
||||
|
||||
@ -1,26 +0,0 @@
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
|
||||
-- MAX+plus II Include File
|
||||
-- Version 10.0 9/14/2000
|
||||
-- Created: Sat May 26 07:09:40 2001
|
||||
|
||||
FUNCTION ay (/reset, clk42, ay_t[8..0], ay_d_wr, ay_a_wr, d[7..0], beeper)
|
||||
RETURNS (do[7..0], ay_ch_a[3..0], ay_ch_b[3..0], ay_ch_c[3..0], ay_ch_l[9..0], ay_ch_r[9..0], ay_ch_val);
|
||||
@ -1,154 +0,0 @@
|
||||
DEPTH = 256; % Memory depth and width are required %
|
||||
WIDTH = 8; % Enter a decimal number %
|
||||
|
||||
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
|
||||
DATA_RADIX = BIN; % Enter BIN, DEC, HEX, or OCT; unless %
|
||||
% otherwise specified, radixes = HEX %
|
||||
|
||||
-- Specify values for addresses, which can be single address or range
|
||||
|
||||
CONTENT
|
||||
BEGIN
|
||||
[0..7F] : 00000000;
|
||||
0 : 00000000 00000000
|
||||
00000000 00000000
|
||||
00000000 00000000
|
||||
00000000 11111111
|
||||
00000000 00000000
|
||||
00000000 00000000
|
||||
00000000 00000000
|
||||
00000000 00000000
|
||||
|
||||
11111111 11111111
|
||||
11111111 11111111
|
||||
11111111 11111111
|
||||
11111111 11111111
|
||||
11111111 11111111
|
||||
11111111 11111111
|
||||
11111111 00000001
|
||||
00000000 11111111
|
||||
;
|
||||
1E : 00000000;
|
||||
1F : 11111111;
|
||||
|
||||
30 : 00000000
|
||||
00000010
|
||||
00000011
|
||||
00000100
|
||||
00000110
|
||||
00001000
|
||||
00001011
|
||||
00010000
|
||||
00010110
|
||||
00100000
|
||||
00101101
|
||||
01000000
|
||||
01011010
|
||||
10000000
|
||||
10110100
|
||||
11111111;
|
||||
|
||||
[80..FF]: 00000000;
|
||||
|
||||
%
|
||||
000 - set CX, load & sub 1
|
||||
001 - load
|
||||
010 - save, if NZ,reset CX
|
||||
011 - bit_out
|
||||
100 - load & sub 1
|
||||
101 - load & sub C
|
||||
110 - if CX, save
|
||||
111 - read states /RESET, AY_F_RES
|
||||
%
|
||||
|
||||
80 :
|
||||
00010000 -- set C,CX load reg10 & sub C
|
||||
01010000 -- save reg10 & reset CX if NZ
|
||||
10110001 -- load reg11 & sub C
|
||||
01010001 -- save reg11 & reset CX if NZ
|
||||
|
||||
00100000 -- set C load reg00 & sub C
|
||||
11010000 -- save reg10 if CX
|
||||
00100001 -- load reg01 & sub C
|
||||
11010001 -- save reg11 if CX
|
||||
|
||||
00101000 -- load reg08
|
||||
01100001 -- set AY_OUT1
|
||||
|
||||
|
||||
00010010 -- set C,CX load reg12 & sub C
|
||||
01010010 -- save reg12 & reset CX if NZ
|
||||
10110011 -- load reg13 & sub C
|
||||
01010011 -- save reg13 & reset CX if NZ
|
||||
|
||||
00100010 -- set C load reg02 & sub C
|
||||
11010010 -- save reg12 if CX
|
||||
00100011 -- load reg03 & reset CX if NZ
|
||||
11010011 -- save reg13 if CX
|
||||
|
||||
00101001 -- load reg09
|
||||
01100010 -- set AY_OUT2
|
||||
|
||||
|
||||
00010100 -- set C,CX load reg14 & sub C
|
||||
01010100 -- save reg14 & reset CX if NZ
|
||||
10110101 -- load reg15 & sub C
|
||||
01010101 -- save reg15 & reset CX if NZ
|
||||
|
||||
00100100 -- set C load reg04 & sub C
|
||||
11010100 -- save reg14 if CX
|
||||
00100101 -- load reg05 & reset CX if NZ
|
||||
11010101 -- save reg15 if CX
|
||||
|
||||
00101010 -- load reg0A
|
||||
01100011 -- set AY_OUT3
|
||||
|
||||
|
||||
00010111 -- set C,CX load reg17 & dec 1
|
||||
01010111 -- save reg17 & reset CX if NZ
|
||||
00100110 -- load reg06 dec 1 ***********
|
||||
11010111 -- save reg17 if CX
|
||||
|
||||
01100100 -- set AY_SH
|
||||
00000000 -- NOP
|
||||
|
||||
00011000 -- set C,CX load reg18 & sub C
|
||||
01011000 -- save reg18 & reset CX if NZ
|
||||
10111001 -- load reg19 & sub C
|
||||
01011001 -- save reg19 & reset CX if NZ
|
||||
|
||||
00101011 -- load reg0B & sub 1
|
||||
11011000 -- save reg18 if CX
|
||||
00101100 -- load reg0C & sub C
|
||||
11011001 -- save reg19 if CX
|
||||
|
||||
01100101 -- set FORM_CLK
|
||||
|
||||
11100000 -- set CX = AY_F_RES
|
||||
|
||||
-- 00101011 -- load reg0B & sub 1
|
||||
-- 11011000 -- save reg18 if CX
|
||||
-- 00101100 -- load reg0C & sub C
|
||||
-- 11011001 -- save reg19 if CX
|
||||
|
||||
11100001 -- set CX = /RESET
|
||||
|
||||
00111111 -- load reg1F - FF ***********
|
||||
11000111 -- save reg07 if CX
|
||||
00111110 -- load reg1E - 00 ***********
|
||||
|
||||
11001101 -- save reg0D if CX
|
||||
11001000 -- save reg08 if CX
|
||||
11001001 -- save reg09 if CX
|
||||
11001010 -- save reg0a if CX
|
||||
|
||||
00100111 -- load reg07 ***********
|
||||
01100110 -- set keys_bits
|
||||
|
||||
00101101 -- load reg0D ***********
|
||||
01100111 -- set keys_bits SET-FORM-bits
|
||||
|
||||
-- 01100000 -- set AY_OUT_ALL
|
||||
|
||||
;
|
||||
END ;
|
||||
@ -1,368 +0,0 @@
|
||||
|
||||
TITLE "AY-3-8910";
|
||||
|
||||
include "lpm_ram_dq";
|
||||
include "lpm_add_sub";
|
||||
|
||||
SUBDESIGN ay
|
||||
(
|
||||
/RESET : INPUT;
|
||||
CLK42 : INPUT; -- â ªâë 42
|
||||
AY_T[8..0] : INPUT; -- ¢¥è¨© áç¥â稪 ⠪⮢
|
||||
|
||||
AY_D_WR : INPUT;
|
||||
AY_A_WR : INPUT;
|
||||
|
||||
D[7..0] : INPUT;
|
||||
DO[7..0] : OUTPUT;
|
||||
|
||||
AY_CH_A[3..0] : OUTPUT;
|
||||
AY_CH_B[3..0] : OUTPUT;
|
||||
AY_CH_C[3..0] : OUTPUT;
|
||||
|
||||
AY_CH_L[9..0] : OUTPUT;
|
||||
AY_CH_R[9..0] : OUTPUT;
|
||||
|
||||
AY_CH_VAL : OUTPUT; -- chanels data valid
|
||||
BEEPER : INPUT;
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
BD[7..0] : DFFE;
|
||||
BWR : DFFE;
|
||||
AWR : DFFE;
|
||||
|
||||
AY_DI[7..0] : NODE;
|
||||
AY_DO[7..0] : NODE;
|
||||
|
||||
AY_F_RES : NODE;
|
||||
AY_F_R1 : NODE;
|
||||
|
||||
AY_ADR[7..0] : DFF;
|
||||
AY_AAX[1..0] : DFF;
|
||||
|
||||
AY_X_[5..0] : DFFE;
|
||||
AY_GF[3..0] : DFFE;
|
||||
|
||||
AY_OUT[3..1] : DFFE;
|
||||
AY_OUTS[3..1] : NODE;
|
||||
|
||||
AY_CLK1 : NODE;
|
||||
AY_SH[16..0] : DFFE;
|
||||
AY_AA[3..0] : DFF;
|
||||
AY_SH_Q : NODE;
|
||||
|
||||
AY_ABLK : NODE;
|
||||
AY_BBLK : NODE;
|
||||
AY_AINV : NODE;
|
||||
AY_BINV : NODE;
|
||||
|
||||
AY_ADRX[7..0] : NODE;
|
||||
AY_CCC[8..0] : DFF;
|
||||
AY_AX[7..0] : NODE;
|
||||
AY_C : DFFE;
|
||||
AY_CX : DFFE;
|
||||
AY_CXX : DFFE;
|
||||
AY_WR : NODE;
|
||||
AY_VA[3..0] : DFFE;
|
||||
AY_VAR : DFFE;
|
||||
AY_VX : DFFE;
|
||||
|
||||
AY_DAT_WR : DFF;
|
||||
AY_DAT[7..0] : DFFE;
|
||||
|
||||
AY_DQ1[3..0] : DFFE;
|
||||
AY_DQ2[3..0] : DFFE;
|
||||
AY_DQ3[3..0] : DFFE;
|
||||
|
||||
AY_DQX[3..0] : DFFE;
|
||||
AY_OUTSX : NODE;
|
||||
AY_CH_MIX : DFF;
|
||||
|
||||
AY_AMP[3..0] : DFF;
|
||||
|
||||
AY_DD[7..0] : DFFE;
|
||||
|
||||
AY_CH_A[3..0] : DFF;
|
||||
AY_CH_B[3..0] : DFF;
|
||||
AY_CH_C[3..0] : DFF;
|
||||
|
||||
AY_CH_CS[8..0] : DFF;
|
||||
AY_CH_LX[10..0] : DFFE;
|
||||
AY_CH_RX[10..0] : DFFE;
|
||||
|
||||
-- AY_CH_L[9..0] : DFF;
|
||||
-- AY_CH_R[9..0] : DFF;
|
||||
|
||||
AY_CH_DIR[7..0] : DFFE;
|
||||
|
||||
AY_OUTS1X : NODE;
|
||||
AY_OUTS2X : NODE;
|
||||
AY_OUTS3X : NODE;
|
||||
|
||||
AY_OUTS1Y : NODE;
|
||||
-- AY_OUTS2Y : NODE;
|
||||
AY_OUTS3Y : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- ====== AY8910 III version =========
|
||||
|
||||
BD[].clk = CLK42;
|
||||
AWR.clk = CLK42;
|
||||
BWR.clk = CLK42;
|
||||
|
||||
BD[].ena = AY_CCC1;
|
||||
BWR.ena = AY_CCC1;
|
||||
AWR.ena = AY_CCC1;
|
||||
|
||||
BD[7..5].clrn = !((AY_ADR[3..0] == B"00X1") or -- ch 1,2
|
||||
(AY_ADR[3..0] == B"0101") or -- ch 3
|
||||
(AY_ADR[3..0] == B"0110") -- ch shum
|
||||
);
|
||||
BD4.clrn = !((AY_ADR[3..0] == B"00X1") or -- ch 1,2
|
||||
(AY_ADR[3..0] == B"0101") -- ch 3
|
||||
);
|
||||
|
||||
BD[] = D[];
|
||||
|
||||
AWR = AY_A_WR;
|
||||
-- BWR = (AY_D_WR or !(AY_ADR[5..4] == 0));
|
||||
BWR = AY_D_WR;
|
||||
|
||||
AY_CH_DIR[].clk = AY_D_WR;
|
||||
AY_CH_DIR[].ena = (AY_ADR[] == B"XXX10000");
|
||||
AY_CH_DIR[].d = D[];
|
||||
AY_CH_DIR[].clrn= /RESET;
|
||||
|
||||
AY_CCC[].clk = CLK42;
|
||||
AY_CCC[8..0].d = AY_T[];
|
||||
|
||||
(AY_AAX[].clk,AY_ADR[].clk) = AY_A_WR;
|
||||
AY_ADR[].d = D[];
|
||||
|
||||
-- Write to 0D register
|
||||
AY_AAX0.d = (D[3..0] == B"1101");
|
||||
-- Write to AMP registers 08,09,0A
|
||||
AY_AAX1.d = (D[3..0] == B"1000") or (D[3..0] == B"1001") or (D[3..0] == B"1010");
|
||||
|
||||
-- reset signal for form generator
|
||||
-- AY_F_RES = DFF(VCC,DFF((!((AY_DO[7..5] == B"111") & AY_CCC1 & !AY_DO0) or AY_F_RES),CLK42,,),LCELL(!(AY_AAX0 or (AY_AAX1 & BD4)) or BWR),);
|
||||
|
||||
-- AY_F_R1 = DFF((!(AY_AAX0 or (AY_AAX1)) or BWR),CLK42,,);
|
||||
AY_F_R1 = DFF((!AY_AAX0 or BWR),CLK42,,);
|
||||
AY_F_RES = DFF(DFF(VCC,AY_CCC7,AY_F_R1,),AY_CCC7,AY_F_R1,);
|
||||
|
||||
AY_X_[].prn = VCC;
|
||||
|
||||
-- AY_GF[3..0].clrn = /RESET;
|
||||
-- AY_GF[3..0].clk = AY_D_WR;
|
||||
-- AY_GF[3..0].ena = AY_ADR[] == B"XXXX1101";
|
||||
-- AY_GF[3..0].d = D[3..0];
|
||||
|
||||
AY_DAT_WR.clk = CLK42;
|
||||
|
||||
CASE AY_CCC[1..0] IS
|
||||
WHEN B"00" =>
|
||||
AY_AX[] = (VCC,GND,AY_CCC[7..2]); -- CMD adress
|
||||
AY_WR = GND;
|
||||
AY_DI[] = AY_DAT[];
|
||||
|
||||
AY_DAT_WR = VCC;
|
||||
|
||||
WHEN B"01" =>
|
||||
AY_AX[] = (B"0000",AY_ADR[3..0]);
|
||||
AY_WR = !BWR;
|
||||
AY_DI[] = BD[];
|
||||
|
||||
AY_DAT_WR = VCC;
|
||||
|
||||
WHEN B"1X" =>
|
||||
AY_AX[] = (GND,GND,GND,AY_DO[4..0]);
|
||||
AY_DAT_WR = AY_DO6;
|
||||
AY_WR = !LCELL(!(AY_DO[7..5] == B"010") &
|
||||
!((AY_DO[7..5] == B"110") & AY_CXX));
|
||||
-- !((AY_DO[7..5] == B"110") & AY_CX));
|
||||
AY_DI[] = AY_DAT[];
|
||||
END CASE;
|
||||
|
||||
AY_DD[].clk = CLK42;
|
||||
AY_DD[].ena = !AY_CCC1 & !AY_CCC0;
|
||||
AY_DD[] = AY_DO[];
|
||||
|
||||
AY_DO[] = lpm_ram_dq(AY_DI[],AY_AX[],AY_WR,CLK42,CLK42)
|
||||
WITH (lpm_width=8,lpm_widthad=8,lpm_file="AY.MIF");
|
||||
|
||||
-- AY_CX.prn = !DFF((((AY_DO[7..5] == B"00X") & AY_CCC1) & (!AY_DO5 or AY_C)),CLK42,,);
|
||||
AY_CX.prn = !DFF(((AY_DO[7..5] == B"000") & AY_CCC1),CLK42,,);
|
||||
AY_CXX.prn = !DFF(((AY_DO[7..5] == B"000") & AY_CCC1),CLK42,,);
|
||||
AY_C.prn = VCC;
|
||||
|
||||
AY_CX.clk = CLK42;
|
||||
AY_CXX.clk = CLK42;
|
||||
(AY_CXX.ena,AY_CX.ena) = DFF((((AY_DO[7..5] == B"010") or (AY_DO[7..5] == B"111")) & AY_CCC1),CLK42,,);
|
||||
|
||||
IF DFF(((AY_DO[7..5] == B"010")),CLK42,,) THEN
|
||||
AY_CX = (LCELL(AY_DAT[] == 0) & AY_CX);
|
||||
-- AY_CXX = (LCELL(AY_DAT[] == 0) & AY_CXX);
|
||||
-- AY_CX = (LCELL(AY_DAT[] == 0) & AY_CX) or (AY_C & DFF(AY_DO0,CLK42,,));
|
||||
AY_CXX = (LCELL(AY_DAT[] == 0) & AY_CXX) or (AY_C & DFF(AY_DO0,CLK42,,));
|
||||
ELSE
|
||||
AY_CXX = DFF(((!/RESET & AY_DO0) or (!AY_F_RES & !AY_DO0)),CLK42,,);
|
||||
AY_CX = DFF(((!/RESET & AY_DO0) or (!AY_F_RES & !AY_DO0)),CLK42,,);
|
||||
END IF;
|
||||
|
||||
(AY_C.clk,AY_DAT[].clk) = CLK42;
|
||||
(AY_C.ena,AY_DAT[].ena) = !DFF(AY_DAT_WR,CLK42,,);
|
||||
(AY_C,AY_DAT[]) = (GND,AY_DO[]) - (B"00000000",DFF((DFF(!AY_DO5,CLK42,,) or (AY_C & DFF(AY_DO7,CLK42,,))),CLK42,,));
|
||||
|
||||
AY_OUT[].clk = CLK42;
|
||||
|
||||
AY_AMP[].clk = CLK42;
|
||||
AY_AMP[] = ((AY_DAT[3..0] or AY_DAT[4]) & (AY_AA[] or !AY_DAT[4]));
|
||||
|
||||
AY_DQ1[].clk = CLK42;
|
||||
AY_OUTS1 = DFF(((AY_DO[7..0] == B"011XX001") & AY_CCC1),CLK42,,);
|
||||
AY_OUT1.ena = AY_OUTS1;
|
||||
AY_OUT1 = AY_CX xor AY_OUT1;
|
||||
AY_DQ1[].ena = AY_OUTS1;
|
||||
AY_DQ1[] = AY_AMP[] & LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0));
|
||||
|
||||
AY_DQ2[].clk = CLK42;
|
||||
AY_OUTS2 = DFF(((AY_DO[7..0] == B"011XX010") & AY_CCC1),CLK42,,);
|
||||
AY_OUT2.ena = AY_OUTS2;
|
||||
AY_OUT2 = AY_CX xor AY_OUT2;
|
||||
AY_DQ2[].ena = AY_OUTS2;
|
||||
AY_DQ2[] = AY_AMP[] & LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0));
|
||||
|
||||
AY_DQ3[].clk = CLK42;
|
||||
AY_OUTS3 = DFF(((AY_DO[7..0] == B"011XX011") & AY_CCC1),CLK42,,);
|
||||
AY_OUT3.ena = AY_OUTS3;
|
||||
AY_OUT3 = AY_CX xor AY_OUT3;
|
||||
AY_DQ3[].ena = AY_OUTS3;
|
||||
AY_DQ3[] = AY_AMP[] & LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0));
|
||||
|
||||
AY_OUTSX = DFF((((AY_DO[7..0] == B"011XX01X") or
|
||||
(AY_DO[7..0] == B"011XX0X1")) & AY_CCC1),CLK42,,);
|
||||
AY_DQX[].clk = CLK42;
|
||||
AY_DQX[].ena = AY_OUTSX;
|
||||
AY_DQX[] = AY_AMP[] & AY_CH_MIX;
|
||||
|
||||
AY_DQX[].clrn = !AY_SH_Q;
|
||||
AY_DQX[].prn = (B"0010") or !DFF((AY_SH_Q & BEEPER),CLK42,,);
|
||||
|
||||
AY_CH_MIX.clk = CLK42;
|
||||
CASE AY_DO[1..0] IS
|
||||
WHEN 0,1 => AY_CH_MIX = LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0));
|
||||
WHEN 2 => AY_CH_MIX = LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0));
|
||||
WHEN 3 => AY_CH_MIX = LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0));
|
||||
END CASE;
|
||||
|
||||
AY_SH_Q = DFF(((AY_DO[7..0] == B"011XX100") & AY_CCC1),CLK42,,);
|
||||
|
||||
AY_SH[].clk = CLK42;
|
||||
AY_SH[].prn = /RESET;
|
||||
AY_SH[].ena = AY_SH_Q & AY_CXX;
|
||||
AY_SH[] = ((AY_SH3 xor AY_SH0),AY_SH[16..1]);
|
||||
|
||||
AY_VAR.clk = CLK42;
|
||||
AY_VX.clk = CLK42;
|
||||
AY_VA[].clk = CLK42;
|
||||
|
||||
(AY_VAR.clrn,AY_VA[].clrn) = AY_F_RES;
|
||||
AY_VX.clrn = AY_F_RES;
|
||||
|
||||
(AY_VX.ena,AY_VA[].ena,AY_VAR.ena) = DFF(((AY_DO[7..0] == B"011XX101") & AY_CCC1 & !AY_BBLK & AY_CX),CLK42,,);
|
||||
(AY_VX,AY_VA[],AY_VAR) = (AY_VX,AY_VA[],AY_VAR) + 1;
|
||||
|
||||
AY_X_[].clk = CLK42;
|
||||
AY_X_[].ena = DFF(((AY_DO[7..0] == B"011XX110") & AY_CCC1),CLK42,,);
|
||||
AY_X_[] = AY_DAT[5..0];
|
||||
|
||||
AY_GF[].clk = CLK42;
|
||||
AY_GF[].ena = DFF(((AY_DO[7..0] == B"011XX111") & AY_CCC1),CLK42,,);
|
||||
AY_GF[] = AY_DAT[3..0];
|
||||
|
||||
-- block count when 1-st period end
|
||||
AY_BBLK = DFF((AY_VX & (AY_GF0 or !AY_GF3)),CLK42,,); -- VA_COUNT_STOP
|
||||
|
||||
-- set ALL ZERO when 1-st period end
|
||||
AY_ABLK = DFF((!AY_GF3 & AY_VX),CLK42,,);
|
||||
|
||||
-- inverse 2-nd-s periods
|
||||
AY_BINV = DFF((AY_VX & ((AY_GF[] == B"1X10") or (AY_GF == B"1X01"))),CLK42,,);
|
||||
|
||||
-- inverse ALL
|
||||
AY_AINV = AY_GF2;
|
||||
|
||||
AY_AA[].clrn= VCC;
|
||||
AY_AA[].clk = CLK42;
|
||||
AY_AA[].d = (AY_VA[] xor AY_BINV xor !AY_AINV) & !AY_ABLK;
|
||||
|
||||
%
|
||||
AY_AA[].clrn= VCC;
|
||||
AY_AA[].prn = GND;
|
||||
AY_AA[].clk = CLK42;
|
||||
AY_AA[] = VCC;
|
||||
%
|
||||
|
||||
AY_CH_A[3..0].clk = AY_CCC7;
|
||||
AY_CH_B[3..0].clk = AY_CCC7;
|
||||
AY_CH_C[3..0].clk = AY_CCC7;
|
||||
|
||||
AY_CH_A[3..0] = AY_DQ1[3..0];
|
||||
AY_CH_B[3..0] = AY_DQ2[3..0];
|
||||
AY_CH_C[3..0] = AY_DQ3[3..0];
|
||||
|
||||
DO[7..0] = AY_DD[];
|
||||
|
||||
AY_CH_CS[].clk = CLK42;
|
||||
CASE AY_DQX[] IS
|
||||
WHEN 15 => AY_CH_CS[] = 360 ;
|
||||
WHEN 14 => AY_CH_CS[] = 255 ;
|
||||
WHEN 13 => AY_CH_CS[] = 180 ;
|
||||
WHEN 12 => AY_CH_CS[] = 127 ;
|
||||
WHEN 11 => AY_CH_CS[] = 90 ;
|
||||
WHEN 10 => AY_CH_CS[] = 64 ;
|
||||
WHEN 9 => AY_CH_CS[] = 45 ;
|
||||
WHEN 8 => AY_CH_CS[] = 32 ;
|
||||
WHEN 7 => AY_CH_CS[] = 22 ;
|
||||
WHEN 6 => AY_CH_CS[] = 16 ;
|
||||
WHEN 5 => AY_CH_CS[] = 11 ;
|
||||
WHEN 4 => AY_CH_CS[] = 8 ;
|
||||
WHEN 3 => AY_CH_CS[] = 6 ;
|
||||
WHEN 2 => AY_CH_CS[] = 4 ;
|
||||
WHEN 1 => AY_CH_CS[] = 2 ;
|
||||
WHEN 0 => AY_CH_CS[] = 0 ;
|
||||
END CASE;
|
||||
|
||||
AY_OUTS1X = DFF(AY_OUTS1,CLK42,,);
|
||||
AY_OUTS2X = DFF((AY_OUTS2 or AY_SH_Q),CLK42,,);
|
||||
AY_OUTS3X = DFF(AY_OUTS3,CLK42,,);
|
||||
|
||||
AY_OUTS1Y = DFF(AY_OUTS1 or AY_OUTS1X,CLK42,,);
|
||||
-- AY_OUTS2Y = DFF(AY_OUTS2 or AY_OUTS2X,CLK42,,);
|
||||
AY_OUTS3Y = DFF(AY_OUTS3 or AY_OUTS3X,CLK42,,);
|
||||
|
||||
(AY_CH_LX[].clrn,AY_CH_RX[].clrn) = !DFF((AY_CCC[7..2] == 0),CLK42,,);
|
||||
|
||||
(AY_CH_LX[],,) = LPM_ADD_SUB (,AY_CH_LX[],(B"00",AY_CH_CS[]),,,,)
|
||||
WITH(LPM_WIDTH=11,LPM_REPRESENTATION="UNSIGNED");
|
||||
(AY_CH_RX[],,) = LPM_ADD_SUB (,AY_CH_RX[],(B"00",AY_CH_CS[]),,,,)
|
||||
WITH (LPM_WIDTH=11,LPM_REPRESENTATION="UNSIGNED");
|
||||
|
||||
AY_CH_LX[].clk = CLK42;
|
||||
AY_CH_RX[].clk = CLK42;
|
||||
AY_CH_LX[].ena = DFF(DFF((AY_OUTS1 or AY_OUTS1Y or AY_OUTS2X or AY_OUTS2),CLK42,,),CLK42,,);
|
||||
AY_CH_RX[].ena = DFF(DFF((AY_OUTS3 or AY_OUTS3Y or AY_OUTS2X or AY_OUTS2),CLK42,,),CLK42,,);
|
||||
|
||||
AY_CH_VAL = DFF((AY_CCC[7..2] == B"111100"),CLK42,,);
|
||||
|
||||
-- AY_CH_L[].clk = AY_CH_VAL;
|
||||
-- AY_CH_R[].clk = AY_CH_VAL;
|
||||
AY_CH_L[] = AY_CH_LX[10..1];
|
||||
AY_CH_R[] = AY_CH_RX[10..1];
|
||||
|
||||
END;
|
||||
|
||||
@ -1,568 +0,0 @@
|
||||
--
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
--
|
||||
CHIP dcp
|
||||
BEGIN
|
||||
DEVICE = EP1K30FC256-3;
|
||||
END;
|
||||
|
||||
DEFAULT_DEVICES
|
||||
BEGIN
|
||||
AUTO_DEVICE = EP1K100FC484-1;
|
||||
AUTO_DEVICE = EP1K100FC256-1;
|
||||
AUTO_DEVICE = EP1K100QC208-1;
|
||||
AUTO_DEVICE = EP1K50FC484-1;
|
||||
AUTO_DEVICE = EP1K50FC256-1;
|
||||
AUTO_DEVICE = EP1K50QC208-1;
|
||||
AUTO_DEVICE = EP1K50TC144-1;
|
||||
AUTO_DEVICE = EP1K30FC256-1;
|
||||
AUTO_DEVICE = EP1K30QC208-1;
|
||||
AUTO_DEVICE = EP1K30TC144-1;
|
||||
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
|
||||
END;
|
||||
|
||||
TIMING_POINT
|
||||
BEGIN
|
||||
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30FC256-3;
|
||||
FREQUENCY = 200MHz;
|
||||
MAINTAIN_STABLE_SYNTHESIS = OFF;
|
||||
CUT_ALL_CLEAR_PRESET = ON;
|
||||
CUT_ALL_BIDIR = ON;
|
||||
END;
|
||||
|
||||
IGNORED_ASSIGNMENTS
|
||||
BEGIN
|
||||
FIT_IGNORE_TIMING = OFF;
|
||||
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
|
||||
IGNORE_DEVICE_ASSIGNMENTS = OFF;
|
||||
IGNORE_LC_ASSIGNMENTS = OFF;
|
||||
IGNORE_PIN_ASSIGNMENTS = OFF;
|
||||
IGNORE_CHIP_ASSIGNMENTS = OFF;
|
||||
IGNORE_TIMING_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
|
||||
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_DEVICE_OPTIONS
|
||||
BEGIN
|
||||
MAX7000B_ENABLE_VREFB = OFF;
|
||||
MAX7000B_ENABLE_VREFA = OFF;
|
||||
MAX7000B_VCCIO_IOBANK2 = 3.3V;
|
||||
MAX7000B_VCCIO_IOBANK1 = 3.3V;
|
||||
CONFIG_EPROM_PULLUP_RESISTOR = ON;
|
||||
CONFIG_EPROM_USER_CODE = FFFFFFFF;
|
||||
FLEX_CONFIGURATION_EPROM = AUTO;
|
||||
MAX7000AE_ENABLE_JTAG = ON;
|
||||
MAX7000AE_USER_CODE = FFFFFFFF;
|
||||
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
|
||||
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX6000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
|
||||
MULTIVOLT_IO = OFF;
|
||||
MAX7000S_ENABLE_JTAG = ON;
|
||||
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
|
||||
MAX7000S_USER_CODE = FFFF;
|
||||
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
|
||||
FLEX10K_JTAG_USER_CODE = 7F;
|
||||
ENABLE_INIT_DONE_OUTPUT = OFF;
|
||||
ENABLE_CHIP_WIDE_OE = OFF;
|
||||
ENABLE_CHIP_WIDE_RESET = OFF;
|
||||
nCEO = UNRESERVED;
|
||||
CLKUSR = UNRESERVED;
|
||||
ADD17 = UNRESERVED;
|
||||
ADD16 = UNRESERVED;
|
||||
ADD15 = UNRESERVED;
|
||||
ADD14 = UNRESERVED;
|
||||
ADD13 = UNRESERVED;
|
||||
ADD0_TO_ADD12 = UNRESERVED;
|
||||
SDOUT = RESERVED_DRIVES_OUT;
|
||||
RDCLK = UNRESERVED;
|
||||
RDYnBUSY = UNRESERVED;
|
||||
nWS_nRS_nCS_CS = UNRESERVED;
|
||||
DATA1_TO_DATA7 = UNRESERVED;
|
||||
DATA0 = RESERVED_TRI_STATED;
|
||||
FLEX8000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME = ACTIVE_SERIAL;
|
||||
DISABLE_TIME_OUT = OFF;
|
||||
ENABLE_DCLK_OUTPUT = OFF;
|
||||
RELEASE_CLEARS = OFF;
|
||||
AUTO_RESTART = OFF;
|
||||
USER_CLOCK = OFF;
|
||||
SECURITY_BIT = OFF;
|
||||
RESERVED_PINS_PERCENT = 0;
|
||||
RESERVED_LCELLS_PERCENT = 0;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
|
||||
BEGIN
|
||||
STYLE = FAST;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
|
||||
AUTO_IMPLEMENT_IN_EAB = OFF;
|
||||
AUTO_OPEN_DRAIN_PINS = ON;
|
||||
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
|
||||
AUTO_REGISTER_PACKING = OFF;
|
||||
DEVICE_FAMILY = ACEX1K;
|
||||
AUTO_FAST_IO = OFF;
|
||||
AUTO_GLOBAL_OE = ON;
|
||||
AUTO_GLOBAL_PRESET = ON;
|
||||
AUTO_GLOBAL_CLEAR = ON;
|
||||
AUTO_GLOBAL_CLOCK = ON;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
|
||||
OPTIMIZE_FOR_SPEED = 5;
|
||||
END;
|
||||
|
||||
COMPILER_PROCESSING_CONFIGURATION
|
||||
BEGIN
|
||||
USE_QUARTUS_FITTER = ON;
|
||||
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
|
||||
FITTER_SETTINGS = NORMAL;
|
||||
SMART_RECOMPILE = OFF;
|
||||
GENERATE_AHDL_TDO_FILE = OFF;
|
||||
RPT_FILE_USER_ASSIGNMENTS = ON;
|
||||
RPT_FILE_LCELL_INTERCONNECT = ON;
|
||||
RPT_FILE_HIERARCHY = ON;
|
||||
RPT_FILE_EQUATIONS = ON;
|
||||
LINKED_SNF_EXTRACTOR = OFF;
|
||||
OPTIMIZE_TIMING_SNF = OFF;
|
||||
TIMING_SNF_EXTRACTOR = ON;
|
||||
FUNCTIONAL_SNF_EXTRACTOR = OFF;
|
||||
DESIGN_DOCTOR_RULES = EPLD;
|
||||
DESIGN_DOCTOR = OFF;
|
||||
END;
|
||||
|
||||
COMPILER_INTERFACES_CONFIGURATION
|
||||
BEGIN
|
||||
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
|
||||
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
|
||||
EDIF_BUS_DELIMITERS = [];
|
||||
EDIF_FLATTEN_BUS = OFF;
|
||||
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
|
||||
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
|
||||
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
|
||||
EDIF_OUTPUT_USE_EDC = OFF;
|
||||
EDIF_INPUT_USE_LMF2 = OFF;
|
||||
EDIF_INPUT_USE_LMF1 = OFF;
|
||||
EDIF_OUTPUT_GND = GND;
|
||||
EDIF_OUTPUT_VCC = VCC;
|
||||
EDIF_INPUT_GND = GND;
|
||||
EDIF_INPUT_VCC = VCC;
|
||||
EDIF_OUTPUT_EDC_FILE = *.edc;
|
||||
EDIF_INPUT_LMF2 = *.lmf;
|
||||
EDIF_INPUT_LMF1 = *.lmf;
|
||||
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
|
||||
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
|
||||
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
|
||||
VHDL_FLATTEN_BUS = OFF;
|
||||
VERILOG_FLATTEN_BUS = OFF;
|
||||
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
VHDL_WRITER_VERSION = VHDL87;
|
||||
VHDL_READER_VERSION = VHDL87;
|
||||
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
|
||||
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
|
||||
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
|
||||
SYNOPSYS_DESIGNWARE = OFF;
|
||||
SYNOPSYS_COMPILER = DESIGN;
|
||||
USE_SYNOPSYS_SYNTHESIS = OFF;
|
||||
VHDL_NETLIST_WRITER = OFF;
|
||||
VERILOG_NETLIST_WRITER = OFF;
|
||||
XNF_GENERATE_AHDL_TDX_FILE = ON;
|
||||
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
|
||||
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
|
||||
EDIF_OUTPUT_VERSION = 200;
|
||||
EDIF_NETLIST_WRITER = OFF;
|
||||
END;
|
||||
|
||||
CUSTOM_DESIGN_DOCTOR_RULES
|
||||
BEGIN
|
||||
MASTER_RESET = OFF;
|
||||
EXPANDER_NETWORKS = ON;
|
||||
RACE_CONDITIONS = ON;
|
||||
DELAY_CHAINS = ON;
|
||||
ASYNCHRONOUS_INPUTS = ON;
|
||||
PRESET_CLEAR_NETWORKS = ON;
|
||||
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
|
||||
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
|
||||
MULTI_CLOCK_NETWORKS = ON;
|
||||
MULTI_LEVEL_CLOCKS = ON;
|
||||
GATED_CLOCKS = ON;
|
||||
RIPPLE_CLOCKS = ON;
|
||||
END;
|
||||
|
||||
SIMULATOR_CONFIGURATION
|
||||
BEGIN
|
||||
END_TIME = 5.0us;
|
||||
BIDIR_PIN = STRONG;
|
||||
START_TIME = 0.0ns;
|
||||
GLITCH_TIME = 0.0ns;
|
||||
GLITCH = OFF;
|
||||
OSCILLATION_TIME = 0.0ns;
|
||||
OSCILLATION = OFF;
|
||||
CHECK_OUTPUTS = OFF;
|
||||
SETUP_HOLD = OFF;
|
||||
USE_DEVICE = OFF;
|
||||
END;
|
||||
|
||||
TIMING_ANALYZER_CONFIGURATION
|
||||
BEGIN
|
||||
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
|
||||
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
|
||||
LIST_PATH_FREQUENCY = 10MHz;
|
||||
LIST_PATH_COUNT = 10;
|
||||
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
|
||||
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
|
||||
INCLUDE_PATHS_LESS_THAN = OFF;
|
||||
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
|
||||
INCLUDE_PATHS_GREATER_THAN = OFF;
|
||||
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
|
||||
CELL_WIDTH = 18;
|
||||
LIST_ONLY_LONGEST_PATH = ON;
|
||||
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
|
||||
CUT_OFF_IO_PIN_FEEDBACK = ON;
|
||||
AUTO_RECALCULATE = OFF;
|
||||
END;
|
||||
|
||||
OTHER_CONFIGURATION
|
||||
BEGIN
|
||||
LAST_MAXPLUS2_VERSION = 10.0;
|
||||
EXPLICIT_FAMILY = 1;
|
||||
ROW_PINS_LCELL_INSERT = ON;
|
||||
CARRY_OUT_PINS_LCELL_INSERT = OFF;
|
||||
NORMAL_LCELL_INSERT = ON;
|
||||
FLEX_10K_52_COLUMNS = 40;
|
||||
DEFAULT_9K_EXP_PER_LCELL = 1/2;
|
||||
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
|
||||
LCELLS_PER_ROW_PERCENT = 100;
|
||||
FAN_IN_PER_LCELL_PERCENT = 100;
|
||||
EXP_PER_LCELL_PERCENT = 100;
|
||||
ROW_PINS_PERCENT = 50;
|
||||
ORIGINAL_MAXPLUS2_VERSION = 9.6;
|
||||
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = ON;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
||||
BEGIN
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = AUTO;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = AUTO;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = MANUAL;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = MANUAL;
|
||||
END;
|
||||
|
||||
@ -1,27 +0,0 @@
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
|
||||
-- MAX+plus II Include File
|
||||
-- Version 10.0 9/14/2000
|
||||
-- Created: Thu Feb 07 21:14:23 2002
|
||||
|
||||
FUNCTION dcp (clk42, /reset, ct[2..0], continue, a[15..0], di[7..0], turbo_hand, /io, /rd, /wr, /mr, /rf, /m1, md[7..0], dos, refresh, g_line[9..0], test_r, acc_on, double_cas, blk_mem)
|
||||
WITH (UPDATE)
|
||||
RETURNS (/res, ras, cas, mc_end, mc_begin, mc_type, mc_write, do[7..0], ma[11..0], mca[1..0], clk_z80, turbo, /wait, /iom, /iomm, ra[17..14], page[11..0], type[3..0], cs_rom, cs_ram, v_ram, port, wr_dwg, wr_tm9, wr_awg, rd_kp11, kp11_mix, ga[9..0], graf, sp_scr, sp_sa, scr128, hdd_data, hdd_flip, ram, blk_r, pn4q, dcpp[7..0]);
|
||||
@ -1,119 +0,0 @@
|
||||
DEPTH = 256; % Memory depth and width are required %
|
||||
WIDTH = 16; % Enter a decimal number %
|
||||
|
||||
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
|
||||
DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless %
|
||||
% otherwise specified, radixes = HEX %
|
||||
|
||||
-- Specify values for addresses, which can be single address or range
|
||||
|
||||
CONTENT
|
||||
BEGIN
|
||||
[0..FF] : 1000;
|
||||
|
||||
0 : 1040 % DCP PAGE %;
|
||||
|
||||
%
|
||||
MA[11..0] bit0 - WG_A5
|
||||
bit1 - WG_A6
|
||||
|
||||
bit2 - MUX_KP11, 0 - WG,CMOS 1 - KMPS,TM9
|
||||
bit3 - RD/WR 0 - WRITE 1 - READ
|
||||
bit4 - CS_WG93 or WR_TM9
|
||||
|
||||
bit5 - HDD/CMOS strobe
|
||||
bit6,7 - 00 - FDD/Scr switches
|
||||
01 - HDD Switch/ Reset
|
||||
10 - HDD1/HDD2
|
||||
11 - CMOS
|
||||
bit8 - HDD CS1/CS3 or CMOS data/adr
|
||||
bit9,10,11 - HDD_A[2..0]
|
||||
%
|
||||
10 :
|
||||
7018 % RD WG93 1F,0F %
|
||||
7019 % RD WG93 3F %
|
||||
701A % RD WG93 5F %
|
||||
701B % RD WG93 7F %
|
||||
|
||||
7017 % WR_PDOS FF %
|
||||
701F % RD_KEYS/ WR_A20 %
|
||||
|
||||
7023 % Set 720 %
|
||||
7027 % Set 1440 %;
|
||||
|
||||
-- 18 :
|
||||
-- 1000 % No_function %
|
||||
|
||||
-- 1B : 1000; % ISA_A20 WR %
|
||||
|
||||
1C : 71D8 % CMOS_DAT_RD %;
|
||||
1D : 70D4 % CMOS_ADR_WR %;
|
||||
1E : 71D4 % CMOS_DAT_WR %;
|
||||
|
||||
20 :
|
||||
60A8 % HD_CS1 ports %
|
||||
62A8
|
||||
64A8
|
||||
66A8
|
||||
68A8
|
||||
6AA8
|
||||
6CA8
|
||||
6EA8
|
||||
|
||||
6DA8 % HD_CS3 3F6 port %
|
||||
6FA8 % HD_CS3 3F7 port %
|
||||
|
||||
7060 % Set HDD1 %
|
||||
7064 % Set HDD2 %
|
||||
|
||||
7120 % Set 320 Lines %
|
||||
7124 % Set 312 Lines %
|
||||
|
||||
7160 % Soft Reset %
|
||||
7164 % ??? %;
|
||||
|
||||
|
||||
30 :
|
||||
7000 % slot 1 ports %
|
||||
7001 % slot 2 ports %
|
||||
7002 % slot 1 mem %
|
||||
7003 % slot 2 mem %
|
||||
;
|
||||
|
||||
40 : 4000; % kb read %
|
||||
|
||||
52 : 3000; -- AY_D READ
|
||||
|
||||
58 : 5000; -- KEMPSTON-Mouse
|
||||
|
||||
[80..FF]: C000;
|
||||
|
||||
88 : 2000; -- COVOX
|
||||
89 : 2000; -- COVOX-Mode
|
||||
|
||||
8C : 3000; -- AY_D READ
|
||||
8D : 2000; -- AY_A WRITE
|
||||
8E : 2000; -- AY_D WRITE
|
||||
|
||||
8F : 2000; -- port for ROM_WRITE
|
||||
|
||||
-- 80 : 7F 7F 7F 7F 7F 7F 7F 7F % KBD_DAT %;
|
||||
-- 90 : 7F % PORT FF %;
|
||||
|
||||
90 : 3030 3031 2032 2033 2034 2035 2036 2037
|
||||
2038 2039 203A 203B 203C 203D 203E 203F; % RAM PAGES %
|
||||
|
||||
B0 : 2020 2021 2022 2023 2024 2025 2026 2027
|
||||
2028 2029 202A 202B 202C 202D 202E 202F; % RAM PAGES %
|
||||
|
||||
[C0..CF]: 2000 % SYS PORTS COPYES %;
|
||||
|
||||
D0 : 2010 2011 2012 2013 2014 2015 2016 2017
|
||||
2018 2019 201A 201B 201C 201D 201E 201F; % RAM PAGES %
|
||||
E0 : 2041 2041 2041 2041 2041 2041 2041 2041
|
||||
2000 2005 2002 2041 20FF 2000 2000 2041; % ROM PAGES %
|
||||
-- E0 : 41 42 43 44 45 46 47 48 00 05 02 E0 F0 00 00 E8; % ROM PAGES %
|
||||
F0 : 2000 2001 2002 2003 2004 2005 2006 2007
|
||||
2008 2009 200A 200B 200C 200D 200E 200F; % RAM PAGES %
|
||||
|
||||
END ;
|
||||
@ -1,750 +0,0 @@
|
||||
|
||||
TITLE "DCP";
|
||||
|
||||
PARAMETERS
|
||||
(
|
||||
UPDATE = 1
|
||||
);
|
||||
|
||||
INCLUDE "lpm_ram_dp";
|
||||
-- INCLUDE "DC_PORT2";
|
||||
|
||||
SUBDESIGN dcp
|
||||
(
|
||||
CLK42 : INPUT;
|
||||
/RESET : INPUT;
|
||||
|
||||
/RES : OUTPUT;
|
||||
|
||||
CT[2..0] : INPUT;
|
||||
|
||||
CONTINUE : INPUT;
|
||||
RAS : OUTPUT;
|
||||
CAS : OUTPUT;
|
||||
MC_END : OUTPUT;
|
||||
MC_BEGIN : OUTPUT;
|
||||
MC_TYPE : OUTPUT;
|
||||
MC_WRITE : OUTPUT;
|
||||
|
||||
A[15..0] : INPUT;
|
||||
DI[7..0] : INPUT;
|
||||
DO[7..0] : OUTPUT;
|
||||
MA[11..0] : OUTPUT;
|
||||
MCA[1..0] : OUTPUT;
|
||||
|
||||
TURBO_HAND : INPUT;
|
||||
CLK_Z80 : OUTPUT;
|
||||
TURBO : OUTPUT;
|
||||
|
||||
/IO : INPUT;
|
||||
/RD : INPUT;
|
||||
/WR : INPUT;
|
||||
/MR : INPUT;
|
||||
/RF : INPUT;
|
||||
/M1 : INPUT;
|
||||
|
||||
/WAIT : OUTPUT;
|
||||
/IOM : OUTPUT;
|
||||
/IOMM : OUTPUT;
|
||||
|
||||
MD[7..0] : INPUT;
|
||||
RA[17..14] : OUTPUT;
|
||||
PAGE[11..0] : OUTPUT;
|
||||
|
||||
TYPE[3..0] : OUTPUT;
|
||||
|
||||
CS_ROM : OUTPUT;
|
||||
CS_RAM : OUTPUT;
|
||||
V_RAM : OUTPUT;
|
||||
PORT : OUTPUT;
|
||||
-- DOS : OUTPUT;
|
||||
DOS : INPUT;
|
||||
|
||||
WR_DWG : OUTPUT;
|
||||
|
||||
WR_TM9 : OUTPUT;
|
||||
WR_AWG : OUTPUT;
|
||||
RD_KP11 : OUTPUT;
|
||||
KP11_MIX : OUTPUT;
|
||||
|
||||
REFRESH : INPUT;
|
||||
|
||||
G_LINE[9..0]: INPUT;
|
||||
GA[9..0] : OUTPUT;
|
||||
GRAF : OUTPUT;
|
||||
|
||||
SP_SCR : OUTPUT;
|
||||
SP_SA : OUTPUT;
|
||||
SCR128 : OUTPUT;
|
||||
|
||||
TEST_R : INPUT;
|
||||
|
||||
HDD_DATA : OUTPUT;
|
||||
HDD_FLIP : OUTPUT;
|
||||
RAM : OUTPUT;
|
||||
BLK_R : OUTPUT;
|
||||
|
||||
PN4Q : OUTPUT;
|
||||
|
||||
ACC_ON : INPUT; -- asselerator state - 1 - present
|
||||
|
||||
DCPP[7..0] : OUTPUT;
|
||||
|
||||
DOUBLE_CAS : INPUT;
|
||||
|
||||
BLK_MEM : INPUT;
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
CLK21 : NODE;
|
||||
|
||||
-- DC : DC_PORT2;
|
||||
|
||||
CLK84 : NODE;
|
||||
CLK42X : NODE;
|
||||
|
||||
CTZ[1..0] : DFF;
|
||||
|
||||
-- CT[2..0] : DFF;
|
||||
|
||||
MEM : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="DCP.MIF");
|
||||
|
||||
D[7..0] : NODE;
|
||||
ADR8_MEM : NODE;
|
||||
MEM_D[15..0]: NODE;
|
||||
MEM_WR : NODE;
|
||||
|
||||
DCP_CX : NODE;
|
||||
SC_LCELL : NODE;
|
||||
|
||||
PG3[5..0] : NODE;
|
||||
PG0[5..0] : NODE;
|
||||
MPGS[7..0] : LCELL;
|
||||
PGS[7..0] : DFF;
|
||||
-- PGS[7..0] : NODE;
|
||||
|
||||
PN[7..0] : DFFE;
|
||||
SC[7..0] : DFFE;
|
||||
SYS : DFFE;
|
||||
CNF[7..0] : DFFE;
|
||||
AROM16 : DFFE;
|
||||
TB_SW : DFFE;
|
||||
|
||||
CASH_ON : NODE;
|
||||
NMI_ENA : NODE;
|
||||
|
||||
DD[7..0] : DFFE;
|
||||
STARTING : NODE;
|
||||
|
||||
-- DOS_ : NODE;
|
||||
-- DOS : NODE;
|
||||
-- DOS_ON_ : NODE;
|
||||
|
||||
MC_RQ : NODE;
|
||||
MC_END : DFFE;
|
||||
MC_BEGIN : DFFE;
|
||||
MC_TYPE : DFFE;
|
||||
MC_WRITE : DFFE;
|
||||
RAS : DFFE;
|
||||
CAS : DFFE;
|
||||
|
||||
MA_[11..0] : DFFE;
|
||||
MCA[1..0] : DFFE;
|
||||
|
||||
/IOM : DFFE;
|
||||
/IOMM : DFFE;
|
||||
/IOMX : DFFE;
|
||||
/IOMY : DFFE;
|
||||
|
||||
WT_CT[3..0] : DFFE;
|
||||
W_TAB[3..0] : LCELL;
|
||||
HDD_W[3..0] : NODE;
|
||||
/IO_WAIT : NODE;
|
||||
/MR_WAIT : NODE;
|
||||
|
||||
MEM_RW : NODE;
|
||||
IO_RW : NODE;
|
||||
IO_RWM : NODE;
|
||||
|
||||
MA_CT[1..0] : DFFE;
|
||||
|
||||
WR_TM9 : DFFE;
|
||||
RD_KP11 : DFFE;
|
||||
|
||||
/RES : NODE;
|
||||
|
||||
RFT : DFF;
|
||||
RFC : DFFE;
|
||||
|
||||
GRAF : DFFE;
|
||||
GRAF_X : NODE;
|
||||
GA[9..0] : LCELL;
|
||||
|
||||
SP_SCR : LCELL;
|
||||
SP_SA : LCELL;
|
||||
|
||||
HDD_FLIP : DFFE;
|
||||
/IOMZ : DFFE;
|
||||
|
||||
HDD_DATA : NODE;
|
||||
HDD_ENA : NODE;
|
||||
|
||||
BLK_C : NODE;
|
||||
/CASH : NODE;
|
||||
|
||||
DCPP[7..0] : DFFE;
|
||||
|
||||
PORTS_X : NODE;
|
||||
|
||||
NO_IO_WAIT : NODE;
|
||||
|
||||
DCP_RES : NODE;
|
||||
|
||||
HDD_A[3..0] : DFF;
|
||||
|
||||
X_ADR[11..0]: LCELL;
|
||||
X_MA_[11..0]: LCELL;
|
||||
|
||||
WR_AWGX : NODE;
|
||||
|
||||
/IOWR : NODE;
|
||||
|
||||
RA[17..14] : LCELL;
|
||||
|
||||
-- SPR_[1..0] : NODE;
|
||||
SPR_[1..0] : LCELL;
|
||||
|
||||
SYS_ENA : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
%
|
||||
-- DC.CLK42 = CLK42;
|
||||
-- DC./RESET = /RESET;
|
||||
--
|
||||
-- DC.A[15..0] = A[15..0];
|
||||
--
|
||||
-- DC./IO = /IO;
|
||||
-- DC./WR = /WR;
|
||||
-- DC./M1 = /M1;
|
||||
--
|
||||
-- -- DC./IOM;
|
||||
-- -- DC./IOMM;
|
||||
-- -- DC.DCP[7..0];
|
||||
--
|
||||
-- DC.DOS = DOS;
|
||||
-- DC.CNF[1..0]= CNF[4..3];
|
||||
--
|
||||
-- DC.SYS = SYS;
|
||||
--
|
||||
-- -- DC.PORT_X;
|
||||
%
|
||||
|
||||
|
||||
-- ==============================================================
|
||||
%
|
||||
-- CT[].clk = CLK42;
|
||||
--
|
||||
-- IF CT1 THEN
|
||||
-- CT[1..0] = GND;
|
||||
-- CT2 = !CT2;
|
||||
-- ELSE
|
||||
-- CT[1..0] = CT[1..0]+1;
|
||||
-- CT2 = CT2;
|
||||
-- END IF;
|
||||
%
|
||||
|
||||
/RES = DFFE(VCC,CLK42,,,CT0);
|
||||
-- ==============================================================
|
||||
|
||||
-- TURBO = DFFE((TB_SW & TURBO_HAND),CLK42,,/RESET,CLK_Z80);
|
||||
TURBO = DFF(DFFE((TB_SW & TURBO_HAND),CLK_Z80,,/RESET,!/RF),CLK42,,);
|
||||
|
||||
CLK84 = CLK42 xor LCELL(CLK42X);
|
||||
CLK42X = DFF(!CLK42X,CLK84,,);
|
||||
|
||||
CTZ[].clk = CLK84 xor CTZ1;
|
||||
CTZ[] = CTZ[]+1;
|
||||
|
||||
-- CLK_Z80 = CTZ1;
|
||||
|
||||
-- CLK_Z80 = DFF((!CLK21 & TURBO) or (TFF((CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,);
|
||||
-- CLK_Z80 = DFF((CLK21 & TURBO) or (TFF((CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,);
|
||||
|
||||
CLK_Z80 = DFF((CLK21 & TURBO) or (TFF((!CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,);
|
||||
-- CLK_Z80 = DFF((!CLK21 & TURBO) or (TFF((!CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,);
|
||||
|
||||
-- ==============================================================
|
||||
CLK21 = DFF((!CT0 xor CT2),CLK42,,);
|
||||
-- === Adress Multiplexer =======================================
|
||||
|
||||
MA_[].clk = CLK42;
|
||||
-- MA_[].ena = (CT2 xor CT0);
|
||||
MA_[].ena = CLK21;
|
||||
|
||||
WR_TM9.clk = CLK42;
|
||||
-- WR_TM9.ena = (CT2 xor CT0);
|
||||
WR_TM9.ena = CLK21;
|
||||
WR_TM9.prn = /RES;
|
||||
|
||||
RD_KP11.clk = !CLK42;
|
||||
-- RD_KP11.ena = (CT2 xor CT0);
|
||||
RD_KP11.ena = CLK21;
|
||||
RD_KP11.prn = /RES;
|
||||
RD_KP11.d = !(MA_CT[] == 0);
|
||||
|
||||
-- WR_AWGX = DFF((WR_TM9 or CLK21),!CLK42,,);
|
||||
WR_AWGX = DFF(GND,!WR_TM9,,DFF(WR_AWGX,CLK42,,));
|
||||
|
||||
-- WR_TM9 = (!MA_CT1 or (!IO_RW & !PORTS_X));
|
||||
WR_TM9 = (!MA_CT1 or (!/IO & !PORTS_X));
|
||||
|
||||
WR_AWG = WR_AWGX;
|
||||
|
||||
KP11_MIX = TFF(VCC,RD_KP11,,);
|
||||
|
||||
WR_DWG = !MC_BEGIN;
|
||||
-- WR_DWG = DFF(!MC_BEGIN,CLK42,,);
|
||||
-- WR_DWG = LCELL(!MC_BEGIN);
|
||||
|
||||
-- MA_CT[].ena = (CT2 xor CT0);
|
||||
MA_CT[].ena = CLK21;
|
||||
MA_CT[].clk = CLK42;
|
||||
|
||||
IF !LCELL(CT2 & !CT1) THEN
|
||||
MA_CT[] = MA_CT[]+1;
|
||||
ELSE
|
||||
MA_CT[] = GND;
|
||||
END IF;
|
||||
|
||||
%
|
||||
-- MA_[11..0] bit0 - WG_A5
|
||||
-- bit1 - WG_A6
|
||||
-- bit2 - MUX_KP11, 0 - WG,CMOS 1 - KMPS,TM9
|
||||
-- bit3 - RD/WR 0 - WRITE 1 - READ
|
||||
-- bit4 - CS_WG93 or WR_TM9
|
||||
-- bit5 - HDD/CMOS strobe
|
||||
-- bit7,6 - 00 - not
|
||||
-- 01 - ????
|
||||
-- 10 - HDD1/2
|
||||
-- 11 - CMOS
|
||||
-- bit8 - HDD CS1/CS3 or CMOS data/adr
|
||||
-- bit9,10,11 - HDD_A[2..0]
|
||||
%
|
||||
CASE A[15..14] IS
|
||||
WHEN 0 => SP_SCR = GND; SP_SA = GND;
|
||||
WHEN 1 => SP_SCR = !GRAF; SP_SA = GND;
|
||||
WHEN 2 => SP_SCR = GND; SP_SA = PG3[1];
|
||||
WHEN 3 => SP_SCR = !GRAF & LCELL(PG3[] == B"1101X1"); SP_SA = PG3[1];
|
||||
END CASE;
|
||||
|
||||
CASE GRAF IS
|
||||
WHEN 0 => GA[] = (GND,GND,MEM.q[3..0],A[13..10]);
|
||||
-- WHEN 1 => GA[] = (VCC,(G_LINE[8..0] + (B"00000",A[13..10])));
|
||||
WHEN 1 => GA[] = (VCC,G_LINE[8..0]);
|
||||
END CASE;
|
||||
|
||||
CASE (IO_RW,MA_CT0) IS
|
||||
WHEN 0 => X_ADR[] = (GND,CNF4,PN5,DOS,/WR,A15,A14,A[6..5],A13,A7,A[2]);
|
||||
WHEN 1 => X_ADR[] = (GND,GND,CNF[4..3],B"01000000");
|
||||
WHEN 2 => X_ADR[] = (GND,GA3,GA[1..0],A[9..2]);
|
||||
WHEN 3 => X_ADR[] = (GND,GND,GA[3..2],MEM.q[7..4],GA[7..4]);
|
||||
END CASE;
|
||||
|
||||
CASE IO_RW IS
|
||||
WHEN 0 => X_MA_[] = (HDD_A[2..0],MEM.q[8..6],((MEM.q[5..4]) & (!/IOMZ,!/IOMY)),/WR,MEM.q2,A[6..5]);
|
||||
WHEN 1 => X_MA_[] = (HDD_A[2..0],B"00000",/WR,VCC,A[6..5]);
|
||||
END CASE;
|
||||
%
|
||||
-- CASE MA_CT1 IS
|
||||
---- WHEN 0 => MA_[] = X_ADR[];
|
||||
-- WHEN 0 => MA_[] = (GND,X_ADR[10..0]);
|
||||
-- WHEN 1 => MA_[] = (HDD_A[2..0],X_MA_[8..4],/WR,X_MA_[3],A[6..5]);
|
||||
-- END CASE;
|
||||
%
|
||||
|
||||
CASE (IO_RW,MA_CT1) IS
|
||||
WHEN B"00" =>
|
||||
MA_[] = (X_ADR[11..0]);
|
||||
WHEN B"01" =>
|
||||
MA_[] = (HDD_A[2..0],MEM.q[8..6],((MEM.q[5..4]) & (!/IOMZ,!/IOMY)),/WR,MEM.q2,A[6..5]);
|
||||
WHEN B"10" =>
|
||||
MA_[] = (X_ADR[11..0]);
|
||||
WHEN B"11" =>
|
||||
MA_[] = (HDD_A[2..0],B"00000",/WR,VCC,A[6..5]);
|
||||
END CASE;
|
||||
|
||||
MA[] = MA_[];
|
||||
|
||||
MCA[].ena = CT2 & CT1;
|
||||
MCA[].clk = CLK42;
|
||||
MCA[] = A[1..0]; -- adress for CAS
|
||||
|
||||
HDD_A[].clk = CLK42;
|
||||
CASE (A[14],A[2..0]) IS
|
||||
WHEN 0 => HDD_A[] = 0;
|
||||
WHEN 1 => HDD_A[] = 1;
|
||||
WHEN 2 => HDD_A[] = 2;
|
||||
WHEN 3 => HDD_A[] = 3;
|
||||
WHEN 4 => HDD_A[] = 4;
|
||||
WHEN 5 => HDD_A[] = 5;
|
||||
WHEN 6 => HDD_A[] = 0;
|
||||
WHEN 7 => HDD_A[] = 0;
|
||||
WHEN 8 => HDD_A[] = 0;
|
||||
WHEN 9 => HDD_A[] = 0;
|
||||
WHEN 10 => HDD_A[] = 6;
|
||||
WHEN 11 => HDD_A[] = 7;
|
||||
WHEN 12 => HDD_A[] = 14;
|
||||
WHEN 13 => HDD_A[] = 15;
|
||||
WHEN 14 => HDD_A[] = 0;
|
||||
WHEN 15 => HDD_A[] = 0;
|
||||
END CASE;
|
||||
|
||||
|
||||
-- === Memory Sinchronizer ======================================
|
||||
|
||||
|
||||
% RF | MEM | RF
|
||||
____ | | _______
|
||||
/MR \__________/
|
||||
| |
|
||||
_____| | _______
|
||||
MC_BEGIN \________/
|
||||
| |__
|
||||
MC_END ____________/ \_______
|
||||
______ |__________
|
||||
MC_TYPE \_____/
|
||||
| |
|
||||
RAS __ _ ___ __
|
||||
\__/|\__/ | \__/
|
||||
____ _ __
|
||||
CAS \__/ | \__/|\__/
|
||||
| |
|
||||
|
||||
%
|
||||
|
||||
-- MC_RQ = DFF(((/MR & DFF(/IO,CLK42,,)) or (/RD & /WR)),CLK42,,);
|
||||
|
||||
-- MC_RQ = DFF(((/MR & DFFE(GND,!CLK42,,!/IO,CT0)) or (/RD & /WR)),!CLK42,,);
|
||||
|
||||
-- MC_RQ = DFF((((/MR or !/RF) & DFF(/IO,CLK42,,/M1)) or (/RD & /WR)),CLK42,,);
|
||||
|
||||
-- MC_RQ = DFF((((/MR or !/RF) & IO_RW) or (/RD & /WR)),CLK42,,);
|
||||
|
||||
-- MC_RQ = DFF(((MEM_RW & IO_RW) or (/RD & /WR)),CLK42,,);
|
||||
|
||||
MC_RQ = DFF(((MEM_RW & DFF(DFF(IO_RW,CLK42,,!/IO),CLK42,,!/IO)) or (/RD & /WR)),!CLK42,,);
|
||||
|
||||
MC_BEGIN.clk= CLK42;
|
||||
MC_BEGIN.ena= CT1 & CT2;
|
||||
MC_BEGIN.d = MC_RQ;
|
||||
MC_BEGIN.prn= !(/MR & /IO);
|
||||
|
||||
MC_END.clk = CLK42;
|
||||
MC_END.d = VCC;
|
||||
MC_END.ena = (CT0 & CT2) & !MC_BEGIN & CONTINUE & !BLK_C;
|
||||
MC_END.clrn = !(/MR & /IO);
|
||||
|
||||
MC_TYPE.clk = CLK42;
|
||||
MC_TYPE.ena = CT1 & CT2;
|
||||
MC_TYPE.d = MC_RQ or MC_END;
|
||||
MC_TYPE.prn = /RES;
|
||||
|
||||
MC_WRITE.clk= CLK42;
|
||||
MC_WRITE.ena= CT1 & CT2;
|
||||
MC_WRITE.d = MC_RQ or CS_RAM or /WR or MC_END;
|
||||
MC_WRITE.prn= /RES;
|
||||
|
||||
RFT.clk = REFRESH;
|
||||
RFT.d = GND;
|
||||
RFT.prn = RFC;
|
||||
-- RFT.prn = VCC;
|
||||
|
||||
RFC.clk = CLK42;
|
||||
RFC.d = !MC_RQ or RFT;
|
||||
-- RFC.d = !MC_RQ;
|
||||
RFC.ena = CT1 & CT2;
|
||||
|
||||
RAS.ena = (!(CT1 or (CT0 xor MC_TYPE))) & (!MC_TYPE or !RFC);
|
||||
CAS.ena = (!(CT1 or (CT0 xor !MC_TYPE))) & (!MC_TYPE or !RFC);
|
||||
-- RAS.ena = (!(CT1 or (CT0 xor MC_TYPE)));
|
||||
-- CAS.ena = (!(CT1 or (CT0 xor !MC_TYPE)));
|
||||
|
||||
RAS.clk = CLK42; CAS.clk = CLK42;
|
||||
RAS.d = CT2; CAS.d = CT2 or BLK_C;
|
||||
|
||||
RAS.prn = /RES;
|
||||
CAS.prn = /RES;
|
||||
-- CAS.prn = !BLK_C;
|
||||
|
||||
-- /MR_WAIT = (MEM_RW or /CASH or DFF(MC_END,CLK42,!/MR,)) or (!TURBO & !ACC_ON);
|
||||
-- /MR_WAIT = MC_END or LCELL(MEM_RW or /CASH or (!TURBO & !ACC_ON));
|
||||
|
||||
/MR_WAIT = LCELL(MC_END or MEM_RW or /CASH or (!TURBO & !ACC_ON));
|
||||
|
||||
-- MEM_RW = LCELL(/MR or !/RF);
|
||||
|
||||
-- anti gluk!
|
||||
MEM_RW = DFF((!/RF or BLK_MEM),!/MR,,LCELL(MEM_RW or !/MR));
|
||||
IO_RWM = DFF(!/M1,!/IO,,LCELL(IO_RW or !/IO));
|
||||
|
||||
IO_RW = DFF(/IO,CLK42,,/M1);
|
||||
|
||||
/IOMM.clk = CLK42;
|
||||
-- /IOMM.ena = CT0 xor CT2;
|
||||
/IOMM.ena = CLK21;
|
||||
/IOMM.d = IO_RW or !MC_END or DFF((WT_CT[] == 0),CLK42,,);
|
||||
/IOMM.prn = /RES;
|
||||
|
||||
/IOMX.clk = CLK42;
|
||||
-- /IOMX.ena = CT0 xor CT2;
|
||||
/IOMX.ena = CLK21;
|
||||
/IOMX.d = /IOMM;
|
||||
/IOMX.prn = /RES;
|
||||
|
||||
/IOMY.clk = CLK42;
|
||||
-- /IOMY.ena = CT0 xor CT2;
|
||||
/IOMY.ena = CLK21;
|
||||
/IOMY.d = /IOMX or !MC_END or DFF((WT_CT[] == B"000X"),CLK42,,);
|
||||
-- /IOMY.prn = /RES;
|
||||
/IOMY.prn = PORTS_X;
|
||||
|
||||
PORTS_X = DFF(((DCPP[7..4] == B"0010") or (DCPP[7..4] == B"0001")),CLK42,,);
|
||||
|
||||
/IOMZ.clk = CLK42;
|
||||
-- /IOMZ.ena = CT0 xor CT2;
|
||||
/IOMZ.ena = CLK21;
|
||||
/IOMZ.d = (A8 xor /RD) or /IOMX or !MC_END or DFF((WT_CT[] == B"000X"),CLK42,,);
|
||||
/IOMZ.prn = PORTS_X;
|
||||
|
||||
HDD_DATA = DFF((HDD_ENA & DFF((MEM.q[11..8] == 0),CLK42,,) & PORTS_X),CLK42,,);
|
||||
HDD_ENA = (MEM.q[7..5] == B"101");
|
||||
|
||||
HDD_FLIP.clk = /IOM;
|
||||
HDD_FLIP.ena = HDD_ENA & DFF((DCPP[] == B"0010XXXX"),CLK42,,);
|
||||
HDD_FLIP.d = !HDD_FLIP & (MEM.q[11..8] == 0);
|
||||
HDD_FLIP.clrn = /RESET & DFF(GND,!DOUBLE_CAS,,HDD_FLIP);
|
||||
|
||||
/IOM.clk = CLK42;
|
||||
-- /IOM.ena = CT0 xor CT2;
|
||||
/IOM.ena = CLK21;
|
||||
/IOM.d = (/IOMX & /IOM);
|
||||
/IOM.prn = !/IO & /M1;
|
||||
|
||||
-- /IO_WAIT = LCELL(/IO or !/M1 or DFF(DFFE((WT_CT[] == 0),CLK42,,,CLK21),CLK42,,NO_IO_WAIT));
|
||||
|
||||
/IO_WAIT = LCELL(IO_RWM or DFF(DFFE((WT_CT[] == 0),CLK42,,,CLK21),CLK42,,NO_IO_WAIT));
|
||||
|
||||
NO_IO_WAIT = !DFF(((A[7..0] == B"111XX1XX") & !TURBO & DOS),CLK42,,);
|
||||
-- NO_IO_WAIT = TURBO;
|
||||
|
||||
WT_CT[].clk = CLK42;
|
||||
-- WT_CT[].ena = (CT2 xor CT0);
|
||||
WT_CT[].ena = CLK21;
|
||||
-- WT_CT[].ena = CT1;
|
||||
WT_CT[].prn = MC_END;
|
||||
|
||||
CASE (/IOM,DFF((WT_CT[] == 0),CLK42,,)) IS
|
||||
WHEN B"1X" => WT_CT[].d = W_TAB[];
|
||||
WHEN B"00" => WT_CT[].d = WT_CT[]-1;
|
||||
WHEN B"01" => WT_CT[].d = GND;
|
||||
END CASE;
|
||||
|
||||
CASE (TURBO,MEM.q[14..12]) IS
|
||||
WHEN 0 => W_TAB[] = 2; WHEN 8 => W_TAB[] = 2;
|
||||
WHEN 1 => W_TAB[] = 2; WHEN 9 => W_TAB[] = 2;
|
||||
WHEN 2 => W_TAB[] = 1; WHEN 10 => W_TAB[] = 4;
|
||||
WHEN 3 => W_TAB[] = 1; WHEN 11 => W_TAB[] = 4;
|
||||
WHEN 4 => W_TAB[] = 1; WHEN 12 => W_TAB[] = 7;
|
||||
WHEN 5 => W_TAB[] = 2; WHEN 13 => W_TAB[] = 7;
|
||||
-- WHEN 6 => W_TAB[] = 10; WHEN 14 => W_TAB[] = 10;
|
||||
WHEN 6 => W_TAB[] = 7; WHEN 14 => W_TAB[] = 7;
|
||||
-- WHEN 6 => W_TAB[] = 13; WHEN 14 => W_TAB[] = 13;
|
||||
WHEN 7 => W_TAB[] = 10; WHEN 15 => W_TAB[] = 10;
|
||||
END CASE;
|
||||
|
||||
CASE LCELL(MEM.q[11..8] == 0) IS
|
||||
WHEN 0 => HDD_W[] = 10; -- registers wait
|
||||
WHEN 1 => HDD_W[] = 4; -- datas wait
|
||||
END CASE;
|
||||
|
||||
/WAIT = (/IO_WAIT & /MR_WAIT);
|
||||
|
||||
|
||||
-- === Other Devicese CASHE, ISA, ROM... ===
|
||||
|
||||
V_RAM = PN2; -- for ORIGINAL Waits
|
||||
|
||||
IF UPDATE == 1 GENERATE
|
||||
-- all ROM/RAM switches in main .tdf
|
||||
BLK_R = SC4;
|
||||
-- all cashes in main .tdf
|
||||
/CASH = GND;
|
||||
-- cashe dir in main .tdf
|
||||
CASH_ON = GND;
|
||||
ELSE GENERATE
|
||||
-- for blk wait
|
||||
/CASH = DFF((MEM.q[7..4] == 15),!CLK42,BLK_R,);
|
||||
-- when BLK_R = 1 => Other Devices stay Active!
|
||||
BLK_R = DFF( (LCELL((MEM.q7 & MEM.q6 & RAM) or
|
||||
(MEM.q7 & LCELL(A14 & A15 & SC4))) &
|
||||
!DFF(DFF(MC_RQ,CLK42,,!/MR),CLK42,,!/MR)),!CLK42,!/MR,);
|
||||
CASH_ON = DFFE(A7,(/IO or /RD),/RESET,,DFF((DCPP[] == H"88"),CLK42,,));
|
||||
END GENERATE;
|
||||
|
||||
RAM = !LCELL(A14 or A15 or (SC0 & SYS));
|
||||
|
||||
CS_ROM = LCELL(/MR or !RAM or !/RF);
|
||||
CS_RAM = LCELL(/MR or RAM or !/RF);
|
||||
|
||||
-- ==============================================
|
||||
|
||||
-- graf screen enable for pages
|
||||
|
||||
GRAF_X = LCELL(MEM.q[7..4] == B"0101");
|
||||
|
||||
GRAF.clk = CLK42;
|
||||
GRAF.ena = (CT0 & CT2);
|
||||
GRAF.d = GRAF_X;
|
||||
|
||||
BLK_C = LCELL((GRAF_X xor GRAF) & !MC_TYPE);
|
||||
|
||||
-----------------------------------------
|
||||
|
||||
SCR128 = PN3;
|
||||
|
||||
D[] = DI[];
|
||||
-- when not IO - reset DCPP!
|
||||
|
||||
DCP_RES = DFF((STARTING & !/IO & /M1),CLK42,,);
|
||||
|
||||
DCPP[].clk = CLK42;
|
||||
DCPP[].ena = !DFF(MC_END,CLK42,,);
|
||||
DCPP[].clrn = MC_END & DCP_RES; -- not in/out when START
|
||||
DCPP[].d = MD[];
|
||||
|
||||
-- DD[].clk = !CLK42;
|
||||
-- DD[].ena = !DFF(MC_END,!CLK42,,);
|
||||
|
||||
DD[].clk = CLK42;
|
||||
DD[].ena = !DFF(MC_END,CLK42,,);
|
||||
DD[].clrn = MC_END & DCP_RES;
|
||||
|
||||
CASE LCELL(MD[7..4] == 15) IS
|
||||
WHEN 0 => DD[].d = MD[];
|
||||
WHEN 1 => DD[].d = (VCC,VCC,PG3[]);
|
||||
END CASE;
|
||||
|
||||
-- === Port Decoder =============================================
|
||||
|
||||
DCP_CX = (DCPP[] == B"1100XXXX");
|
||||
SYS_ENA = DFF((DCP_CX & (DCPP[] == B"XXXXX110")),CLK42,,);
|
||||
|
||||
-- /IOWR = DFF((/WR or /IO),CLK42,,!/IO);
|
||||
/IOWR = LCELL(/IO or /WR or !/M1);
|
||||
|
||||
CNF[].ena = SYS_ENA; CNF[].d = (DI[] & DI2) or (CNF[] & !DI2);
|
||||
AROM16.ena = SYS_ENA; AROM16.d = (DI0 & !DI1) or (AROM16 & DI1);
|
||||
TB_SW.ena = SYS_ENA; TB_SW.d = (DI0 & DI1) or (TB_SW & !DI1);
|
||||
SYS.ena = SYS_ENA; SYS.d = !A6;
|
||||
|
||||
SC[].ena = DFF((DCP_CX & (DCPP[] == B"XXXXX000")),CLK42,,) ;SC[].d = DI[];
|
||||
PN[].ena = DFF((DCP_CX & (DCPP[] == B"XXXXX001")),CLK42,,) ;PN[].d = DI[];
|
||||
|
||||
TB_SW.clk = /IOWR;
|
||||
AROM16.clk = /IOWR;
|
||||
PN[].clk = /IOWR;
|
||||
SC[].clk = /IOWR;
|
||||
SYS.clk = /IOWR;
|
||||
CNF[].clk = /IOWR;
|
||||
|
||||
AROM16.clrn = /RESET;
|
||||
TB_SW.prn = /RESET;
|
||||
SYS.clrn = /RESET;
|
||||
CNF[].clrn = /RESET;
|
||||
|
||||
SC[].clrn = /RESET & !CNF6; -- Scorpion-OFF
|
||||
|
||||
PN[5..0].clrn = /RESET & !CNF5; -- reset PN5
|
||||
PN[7..6].clrn = /RESET & CNF7; -- set Pentagon-512
|
||||
|
||||
PN4Q = PN4;
|
||||
|
||||
-- ====================================
|
||||
|
||||
-- ********** Pages decoder ***********
|
||||
|
||||
-- ====================================
|
||||
|
||||
PG3[] = (!PN7,VCC,LCELL((SC4 & !CNF7) or (CNF7 & PN6)),PN[2..0]);
|
||||
|
||||
-- SC0,SC1,SYS,DOS,PN4,AROM16,CASH_ON,NMI_ENA
|
||||
PG0[] = (VCC,GND,
|
||||
LCELL(SC0 or !SYS or CASH_ON or !NMI_ENA),
|
||||
LCELL(((AROM16 & !(SC0 & SYS)) or (CASH_ON & NMI_ENA))),
|
||||
LCELL((SPR_1 & SC_LCELL) or !SYS or !NMI_ENA),
|
||||
LCELL((SPR_0 & SC_LCELL) or !SYS or !NMI_ENA));
|
||||
|
||||
-- SC_LCELL = LCELL(!(SC0 & SYS) & !CASH_ON);
|
||||
SC_LCELL = (!(SC0 & SYS) & !CASH_ON);
|
||||
|
||||
NMI_ENA = VCC;
|
||||
|
||||
SPR_[] = !SC1 & (DOS,(PN4 or !DOS)); -- expansion/dos/basic128/basic48
|
||||
|
||||
CASE (TEST_R,SYS) IS
|
||||
WHEN B"X0" => RA[] = (!AROM16,B"000"); -- system 0/1
|
||||
WHEN B"01" => RA[] = (!AROM16,GND,SPR_[]); -- expansion/dos/basic
|
||||
WHEN B"11" => RA[] = (B"001",SPR_0); -- test
|
||||
END CASE;
|
||||
|
||||
-- ====================================
|
||||
|
||||
CASE A[15..14] IS
|
||||
WHEN 0 => MPGS[5..0] = PG0[];
|
||||
WHEN 1 => MPGS[5..0] = B"101001"; %H"E9"%
|
||||
WHEN 2 => MPGS[5..0] = B"101010"; %H"EA"%
|
||||
WHEN 3 => MPGS[5..0] = PG3[];
|
||||
END CASE;
|
||||
MPGS[7..6] = VCC;
|
||||
|
||||
-- STARTING = DFF(GND,VCC,/RESET,(/IO or /RD));
|
||||
STARTING = LCELL(/RESET & (STARTING or !(/IO or /RD)));
|
||||
|
||||
PGS[].clk = !CLK42;
|
||||
CASE (LCELL(/IO & !(A14 & A15 & !STARTING)),MC_END) IS
|
||||
WHEN B"1X" => PGS[] = (VCC,VCC,MPGS[5..0]);
|
||||
WHEN B"01" => PGS[] = DD[];
|
||||
WHEN B"00" => PGS[] = GND;
|
||||
END CASE;
|
||||
|
||||
MEM_WR = DFFE((DCPP[7] & DCPP[6] & STARTING & DFF(DFF((MC_END & !/WR),CLK42,,),CLK42,,)),CLK42,!/IO,,CT1);
|
||||
|
||||
ADR8_MEM = GND;
|
||||
|
||||
CASE ADR8_MEM IS
|
||||
WHEN 1 => MEM_D[] = (DI[],MEM.q[7..0]); DO[] = MEM.q[15..8];
|
||||
WHEN 0 => MEM_D[] = (MEM.q[15..8],DI[]); DO[] = MEM.q[7..0];
|
||||
END CASE;
|
||||
|
||||
MEM.wren = MEM_WR;
|
||||
MEM.data[] = MEM_D[];
|
||||
MEM.wraddress[] = PGS[];
|
||||
MEM.wrclock = CLK42;
|
||||
MEM.wrclken = VCC;
|
||||
MEM.rden = VCC;
|
||||
MEM.rdaddress[] = PGS[];
|
||||
MEM.rdclock = CLK42;
|
||||
MEM.rdclken = VCC;
|
||||
-- = MEM.q[];
|
||||
|
||||
PAGE[] = MEM.q[11..0];
|
||||
TYPE[] = MEM.q[15..12];
|
||||
|
||||
|
||||
PORT = !(MEM.q[15..12] == 0) or /IO or (/RD & /WR);
|
||||
|
||||
END;
|
||||
|
||||
|
||||
@ -1,568 +0,0 @@
|
||||
--
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
--
|
||||
CHIP kbd
|
||||
BEGIN
|
||||
DEVICE = EP1K30QC208-3;
|
||||
END;
|
||||
|
||||
DEFAULT_DEVICES
|
||||
BEGIN
|
||||
AUTO_DEVICE = EP1K100FC484-1;
|
||||
AUTO_DEVICE = EP1K100FC256-1;
|
||||
AUTO_DEVICE = EP1K100QC208-1;
|
||||
AUTO_DEVICE = EP1K50FC484-1;
|
||||
AUTO_DEVICE = EP1K50FC256-1;
|
||||
AUTO_DEVICE = EP1K50QC208-1;
|
||||
AUTO_DEVICE = EP1K50TC144-1;
|
||||
AUTO_DEVICE = EP1K30FC256-1;
|
||||
AUTO_DEVICE = EP1K30QC208-1;
|
||||
AUTO_DEVICE = EP1K30TC144-1;
|
||||
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
|
||||
END;
|
||||
|
||||
TIMING_POINT
|
||||
BEGIN
|
||||
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3;
|
||||
FREQUENCY = 100MHz;
|
||||
MAINTAIN_STABLE_SYNTHESIS = OFF;
|
||||
CUT_ALL_CLEAR_PRESET = ON;
|
||||
CUT_ALL_BIDIR = ON;
|
||||
END;
|
||||
|
||||
IGNORED_ASSIGNMENTS
|
||||
BEGIN
|
||||
FIT_IGNORE_TIMING = OFF;
|
||||
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
|
||||
IGNORE_DEVICE_ASSIGNMENTS = OFF;
|
||||
IGNORE_LC_ASSIGNMENTS = OFF;
|
||||
IGNORE_PIN_ASSIGNMENTS = OFF;
|
||||
IGNORE_CHIP_ASSIGNMENTS = OFF;
|
||||
IGNORE_TIMING_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
|
||||
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_DEVICE_OPTIONS
|
||||
BEGIN
|
||||
MAX7000B_ENABLE_VREFB = OFF;
|
||||
MAX7000B_ENABLE_VREFA = OFF;
|
||||
MAX7000B_VCCIO_IOBANK2 = 3.3V;
|
||||
MAX7000B_VCCIO_IOBANK1 = 3.3V;
|
||||
CONFIG_EPROM_PULLUP_RESISTOR = ON;
|
||||
CONFIG_EPROM_USER_CODE = FFFFFFFF;
|
||||
FLEX_CONFIGURATION_EPROM = AUTO;
|
||||
MAX7000AE_ENABLE_JTAG = ON;
|
||||
MAX7000AE_USER_CODE = FFFFFFFF;
|
||||
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
|
||||
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX6000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
|
||||
MULTIVOLT_IO = OFF;
|
||||
MAX7000S_ENABLE_JTAG = ON;
|
||||
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
|
||||
MAX7000S_USER_CODE = FFFF;
|
||||
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
|
||||
FLEX10K_JTAG_USER_CODE = 7F;
|
||||
ENABLE_INIT_DONE_OUTPUT = OFF;
|
||||
ENABLE_CHIP_WIDE_OE = OFF;
|
||||
ENABLE_CHIP_WIDE_RESET = OFF;
|
||||
nCEO = UNRESERVED;
|
||||
CLKUSR = UNRESERVED;
|
||||
ADD17 = UNRESERVED;
|
||||
ADD16 = UNRESERVED;
|
||||
ADD15 = UNRESERVED;
|
||||
ADD14 = UNRESERVED;
|
||||
ADD13 = UNRESERVED;
|
||||
ADD0_TO_ADD12 = UNRESERVED;
|
||||
SDOUT = RESERVED_DRIVES_OUT;
|
||||
RDCLK = UNRESERVED;
|
||||
RDYnBUSY = UNRESERVED;
|
||||
nWS_nRS_nCS_CS = UNRESERVED;
|
||||
DATA1_TO_DATA7 = UNRESERVED;
|
||||
DATA0 = RESERVED_TRI_STATED;
|
||||
FLEX8000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME = ACTIVE_SERIAL;
|
||||
DISABLE_TIME_OUT = OFF;
|
||||
ENABLE_DCLK_OUTPUT = OFF;
|
||||
RELEASE_CLEARS = OFF;
|
||||
AUTO_RESTART = OFF;
|
||||
USER_CLOCK = OFF;
|
||||
SECURITY_BIT = OFF;
|
||||
RESERVED_PINS_PERCENT = 0;
|
||||
RESERVED_LCELLS_PERCENT = 0;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
|
||||
BEGIN
|
||||
STYLE = FAST;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
|
||||
AUTO_IMPLEMENT_IN_EAB = OFF;
|
||||
AUTO_OPEN_DRAIN_PINS = ON;
|
||||
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
|
||||
AUTO_REGISTER_PACKING = OFF;
|
||||
DEVICE_FAMILY = ACEX1K;
|
||||
AUTO_FAST_IO = OFF;
|
||||
AUTO_GLOBAL_OE = ON;
|
||||
AUTO_GLOBAL_PRESET = ON;
|
||||
AUTO_GLOBAL_CLEAR = ON;
|
||||
AUTO_GLOBAL_CLOCK = ON;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
|
||||
OPTIMIZE_FOR_SPEED = 5;
|
||||
END;
|
||||
|
||||
COMPILER_PROCESSING_CONFIGURATION
|
||||
BEGIN
|
||||
USE_QUARTUS_FITTER = ON;
|
||||
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
|
||||
FITTER_SETTINGS = NORMAL;
|
||||
SMART_RECOMPILE = OFF;
|
||||
GENERATE_AHDL_TDO_FILE = OFF;
|
||||
RPT_FILE_USER_ASSIGNMENTS = ON;
|
||||
RPT_FILE_LCELL_INTERCONNECT = ON;
|
||||
RPT_FILE_HIERARCHY = ON;
|
||||
RPT_FILE_EQUATIONS = ON;
|
||||
LINKED_SNF_EXTRACTOR = OFF;
|
||||
OPTIMIZE_TIMING_SNF = OFF;
|
||||
TIMING_SNF_EXTRACTOR = ON;
|
||||
FUNCTIONAL_SNF_EXTRACTOR = OFF;
|
||||
DESIGN_DOCTOR_RULES = EPLD;
|
||||
DESIGN_DOCTOR = OFF;
|
||||
END;
|
||||
|
||||
COMPILER_INTERFACES_CONFIGURATION
|
||||
BEGIN
|
||||
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
|
||||
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
|
||||
EDIF_BUS_DELIMITERS = [];
|
||||
EDIF_FLATTEN_BUS = OFF;
|
||||
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
|
||||
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
|
||||
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
|
||||
EDIF_OUTPUT_USE_EDC = OFF;
|
||||
EDIF_INPUT_USE_LMF2 = OFF;
|
||||
EDIF_INPUT_USE_LMF1 = OFF;
|
||||
EDIF_OUTPUT_GND = GND;
|
||||
EDIF_OUTPUT_VCC = VCC;
|
||||
EDIF_INPUT_GND = GND;
|
||||
EDIF_INPUT_VCC = VCC;
|
||||
EDIF_OUTPUT_EDC_FILE = *.edc;
|
||||
EDIF_INPUT_LMF2 = *.lmf;
|
||||
EDIF_INPUT_LMF1 = *.lmf;
|
||||
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
|
||||
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
|
||||
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
|
||||
VHDL_FLATTEN_BUS = OFF;
|
||||
VERILOG_FLATTEN_BUS = OFF;
|
||||
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
VHDL_WRITER_VERSION = VHDL87;
|
||||
VHDL_READER_VERSION = VHDL87;
|
||||
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
|
||||
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
|
||||
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
|
||||
SYNOPSYS_DESIGNWARE = OFF;
|
||||
SYNOPSYS_COMPILER = DESIGN;
|
||||
USE_SYNOPSYS_SYNTHESIS = OFF;
|
||||
VHDL_NETLIST_WRITER = OFF;
|
||||
VERILOG_NETLIST_WRITER = OFF;
|
||||
XNF_GENERATE_AHDL_TDX_FILE = ON;
|
||||
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
|
||||
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
|
||||
EDIF_OUTPUT_VERSION = 200;
|
||||
EDIF_NETLIST_WRITER = OFF;
|
||||
END;
|
||||
|
||||
CUSTOM_DESIGN_DOCTOR_RULES
|
||||
BEGIN
|
||||
MASTER_RESET = OFF;
|
||||
EXPANDER_NETWORKS = ON;
|
||||
RACE_CONDITIONS = ON;
|
||||
DELAY_CHAINS = ON;
|
||||
ASYNCHRONOUS_INPUTS = ON;
|
||||
PRESET_CLEAR_NETWORKS = ON;
|
||||
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
|
||||
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
|
||||
MULTI_CLOCK_NETWORKS = ON;
|
||||
MULTI_LEVEL_CLOCKS = ON;
|
||||
GATED_CLOCKS = ON;
|
||||
RIPPLE_CLOCKS = ON;
|
||||
END;
|
||||
|
||||
SIMULATOR_CONFIGURATION
|
||||
BEGIN
|
||||
BIDIR_PIN = STRONG;
|
||||
END_TIME = 0.0ns;
|
||||
START_TIME = 0.0ns;
|
||||
GLITCH_TIME = 0.0ns;
|
||||
GLITCH = OFF;
|
||||
OSCILLATION_TIME = 0.0ns;
|
||||
OSCILLATION = OFF;
|
||||
CHECK_OUTPUTS = OFF;
|
||||
SETUP_HOLD = OFF;
|
||||
USE_DEVICE = OFF;
|
||||
END;
|
||||
|
||||
TIMING_ANALYZER_CONFIGURATION
|
||||
BEGIN
|
||||
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
|
||||
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
|
||||
LIST_PATH_FREQUENCY = 10MHz;
|
||||
LIST_PATH_COUNT = 10;
|
||||
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
|
||||
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
|
||||
INCLUDE_PATHS_LESS_THAN = OFF;
|
||||
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
|
||||
INCLUDE_PATHS_GREATER_THAN = OFF;
|
||||
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
|
||||
CELL_WIDTH = 18;
|
||||
LIST_ONLY_LONGEST_PATH = ON;
|
||||
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
|
||||
CUT_OFF_IO_PIN_FEEDBACK = ON;
|
||||
AUTO_RECALCULATE = OFF;
|
||||
END;
|
||||
|
||||
OTHER_CONFIGURATION
|
||||
BEGIN
|
||||
LAST_MAXPLUS2_VERSION = 10.0;
|
||||
EXPLICIT_FAMILY = 1;
|
||||
ROW_PINS_LCELL_INSERT = ON;
|
||||
CARRY_OUT_PINS_LCELL_INSERT = OFF;
|
||||
NORMAL_LCELL_INSERT = ON;
|
||||
FLEX_10K_52_COLUMNS = 40;
|
||||
DEFAULT_9K_EXP_PER_LCELL = 1/2;
|
||||
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
|
||||
LCELLS_PER_ROW_PERCENT = 100;
|
||||
FAN_IN_PER_LCELL_PERCENT = 100;
|
||||
EXP_PER_LCELL_PERCENT = 100;
|
||||
ROW_PINS_PERCENT = 50;
|
||||
ORIGINAL_MAXPLUS2_VERSION = 9.6;
|
||||
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = ON;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
||||
BEGIN
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = AUTO;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = AUTO;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = MANUAL;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = MANUAL;
|
||||
END;
|
||||
|
||||
@ -1,26 +0,0 @@
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
|
||||
-- MAX+plus II Include File
|
||||
-- Version 10.0 9/14/2000
|
||||
-- Created: Thu May 03 21:43:31 2001
|
||||
|
||||
FUNCTION kbd (clk42, clk_k, kbd_cc, kbd_dd, /rf, /io, /iom, /m1, a[15..8], ena, int_ena)
|
||||
RETURNS (kbo[7..0], kb_reset, kb_f12, kb_ctrl, kb_alt, kb_sh, int);
|
||||
@ -1,180 +0,0 @@
|
||||
|
||||
TITLE "ZX-Keyboard";
|
||||
|
||||
INCLUDE "lpm_ram_dq";
|
||||
|
||||
SUBDESIGN kbd
|
||||
(
|
||||
CLK42 : INPUT; -- full sinc 42MHz
|
||||
CLK_K : INPUT; -- sinc input 15KHz
|
||||
KBD_CC : INPUT; -- sinc KBD
|
||||
KBD_DD : INPUT; -- data KBD
|
||||
|
||||
/RF : INPUT; -- /rfsh
|
||||
/IO : INPUT; -- /iorq
|
||||
/IOM : INPUT;
|
||||
/M1 : INPUT;
|
||||
|
||||
A[15..8] : INPUT;
|
||||
|
||||
KBO[7..0] : OUTPUT; -- output
|
||||
|
||||
KB_RESET : OUTPUT;
|
||||
|
||||
KB_F12 : OUTPUT;
|
||||
KB_CTRL : OUTPUT;
|
||||
KB_ALT : OUTPUT;
|
||||
KB_SH : OUTPUT;
|
||||
|
||||
ENA : INPUT;
|
||||
INT_ENA : INPUT;
|
||||
INT : OUTPUT;
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
KB_CT[2..0] : DFF;
|
||||
KB_D[10..0] : DFF;
|
||||
KB_OFF : DFFE;
|
||||
|
||||
KB_EXT : DFF;
|
||||
KB_ALT : DFF;
|
||||
KB_CTRL : DFF;
|
||||
KB_SH : DFF;
|
||||
|
||||
KB_CTRL_X : NODE;
|
||||
KB_ALT_X : NODE;
|
||||
KB_SH_X : NODE;
|
||||
KB_XXX : NODE;
|
||||
KB_RESET : DFF;
|
||||
RXA[1..0] : DFFE;
|
||||
|
||||
K_CLK : NODE;
|
||||
KA[15..0] : NODE;
|
||||
KB_MA[2..0] : DFF;
|
||||
KB_MXA : NODE;
|
||||
KDCA[2..0] : LCELL;
|
||||
|
||||
KDD[7..0] : DFF;
|
||||
KBD[5..0] : DFF;
|
||||
KD[7..0] : NODE;
|
||||
KDX[5..0] : DFF;
|
||||
KDXX[5..0] : DFF;
|
||||
WR_KBD : NODE;
|
||||
KB_OFL : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
INT = DFF((KB_CT[] == 0),CLK42,,INT_ENA);
|
||||
|
||||
-- KB_CT[].clk = DFF(CLK_K,CLK42,,);
|
||||
KB_CT[].clk = CLK_K;
|
||||
KB_CT[].prn = DFF(KBD_CC,CLK42,,);
|
||||
|
||||
CASE KB_CT[] IS
|
||||
WHEN 0 => KB_CT[].d = GND;
|
||||
WHEN 1,2,3,4,5,6,7 => KB_CT[].d = KB_CT[] - 1;
|
||||
END CASE;
|
||||
|
||||
KB_D[].clk = DFF(!KBD_CC,CLK42,,);
|
||||
KB_D[].d = (KBD_DD,KB_D[10..1]);
|
||||
|
||||
KB_OFF.ena = !KB_EXT;
|
||||
KB_OFF.clk = DFF((KB_CT[] == 0),CLK42,,);
|
||||
KB_OFF.d = KB_D[] == B"XX11110000X";
|
||||
|
||||
KB_EXT.clk = DFF((KB_CT[] == 1),CLK42,,);
|
||||
KB_EXT.d = KB_D[] == B"XX11100000X";
|
||||
|
||||
KB_CTRL.clk = !KB_CT2;
|
||||
KB_ALT.clk = !KB_CT2;
|
||||
KB_SH.clk = !KB_CT2;
|
||||
|
||||
KB_CTRL_X = LCELL(KB_D[] == B"XXXXX1X100X");
|
||||
KB_ALT_X = LCELL(KB_D[] == B"XXXXX1X001X");
|
||||
KB_SH_X = LCELL(KB_D[] == B"XX0X01X0XXX") &
|
||||
CASCADE((KB_D[] == B"XXX1XX1X01X") or (KB_D[] == B"XXX0XX0X10X"));
|
||||
KB_XXX = LCELL(KB_D[] == B"XX000X0XXXX");
|
||||
|
||||
CASE KB_OFF IS
|
||||
WHEN 0 =>
|
||||
KB_CTRL.d = (KB_CTRL_X & KB_XXX) or KB_CTRL;
|
||||
KB_ALT.d = (KB_ALT_X & KB_XXX) or KB_ALT;
|
||||
KB_SH.d = (KB_SH_X) or KB_SH;
|
||||
WHEN 1 =>
|
||||
KB_CTRL.d = !(KB_CTRL_X & KB_XXX) & KB_CTRL;
|
||||
KB_ALT.d = !(KB_ALT_X & KB_XXX) & KB_ALT;
|
||||
KB_SH.d = !(KB_SH_X) & KB_SH;
|
||||
END CASE;
|
||||
|
||||
KB_F12 = DFF(!((KB_XXX & LCELL(KB_D[] == B"XXXXX0X111X")) & !KB_OFF),
|
||||
!KB_CT2,,!(KB_CT[] == 1));
|
||||
|
||||
KB_RESET.clk = !KB_CT2;
|
||||
KB_RESET.d = !(KB_ALT_X & (KB_D[] == B"XX011X0XXXX") & !KB_OFF & KB_CTRL & KB_ALT);
|
||||
KB_RESET.prn = !DFF((KB_CT[] == 1),CLK42,,);
|
||||
|
||||
K_CLK = DFF(/RF,CLK42,,);
|
||||
|
||||
RXA[].ena = VCC;
|
||||
RXA[].clk = K_CLK;
|
||||
|
||||
CASE DFF((!(KB_CT[] == B"01X") & (RXA[] == 0)),CLK42,,) IS
|
||||
WHEN B"1" => RXA[] = GND;
|
||||
WHEN B"0" => RXA[] = (RXA0,!RXA1);
|
||||
END CASE;
|
||||
|
||||
CASE (DFF((/IO & (RXA[] == 0),CLK42,,)),LCELL(KDD7 & KDD6)) IS
|
||||
WHEN B"0X" => KA[15..8] = (B"101",KDCA[],B"11");
|
||||
WHEN B"10" => KA[15..8] = (B"110000",KDD7,KDD6);
|
||||
WHEN B"11" => KA[15..8] = KB_D[8..1];
|
||||
END CASE;
|
||||
|
||||
KB_MA[].clk = CLK42;
|
||||
KB_MA[].d = KB_MA[] + 1;
|
||||
KB_MA[].clrn = !DFF(/IO,CLK42,,);
|
||||
|
||||
KB_MXA = DFF(( (((KB_MA[] == 7) & A15) or ((KB_MA[] == 6) & A14))
|
||||
or (((KB_MA[] == 5) & A13) or ((KB_MA[] == 4) & A12))
|
||||
or (((KB_MA[] == 3) & A11) or ((KB_MA[] == 2) & A10))
|
||||
or (((KB_MA[] == 1) & A9 ) or ((KB_MA[] == 0) & A8 ))),CLK42,,);
|
||||
|
||||
IF !DFF(/IO,CLK42,,) THEN
|
||||
KDCA[] = KB_MA[];
|
||||
ELSE
|
||||
KDCA[] = KDD[5..3];
|
||||
END IF;
|
||||
|
||||
KDD[].clk = RXA0;
|
||||
KDD[].d = KD[];
|
||||
KDD[7..6].prn = !KB_CT2;
|
||||
|
||||
KDXX[].clk = RXA0;
|
||||
KDXX[].d = !((KD[2..0] == 5),(KD[2..0] == 4),
|
||||
(KD[2..0] == 3),(KD[2..0] == 2),
|
||||
(KD[2..0] == 1),(KD[2..0] == 0));
|
||||
|
||||
KDX[].clk = RXA1;
|
||||
|
||||
CASE KB_OFF IS
|
||||
WHEN B"0" => KDX[].d = (KD[5..0] & KDXX[]);
|
||||
WHEN B"1" => KDX[].d = (KD[5..0] or !KDXX[]);
|
||||
END CASE;
|
||||
|
||||
-- ==============================
|
||||
|
||||
WR_KBD = K_CLK or !DFF((KB_CT[] == 2),CLK42,,) or !(RXA[] == 3);
|
||||
|
||||
KD[] = lpm_ram_dq((B"11",KDX[5..0]),KA[15..8],!WR_KBD,CLK42,)
|
||||
WITH (lpm_width=8,lpm_widthad=8,lpm_file="KBD_INI2.MIF",
|
||||
lpm_outdata="UNREGISTERED");
|
||||
|
||||
KBD[].clk = CLK42;
|
||||
KBD[].prn = DFF(VCC,KB_MA2,(!/IO & ENA),);
|
||||
|
||||
-- KBD[].prn = DFF(!/IOM,CLK42,,);
|
||||
KBD[].d = KBD[] & (KD[5..0] or KB_MXA);
|
||||
|
||||
KBO[] = (VCC,VCC,KBD[]);
|
||||
|
||||
END;
|
||||
|
||||
@ -1,167 +0,0 @@
|
||||
DEPTH = 256; % Memory depth and width are required %
|
||||
WIDTH = 8; % Enter a decimal number %
|
||||
|
||||
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
|
||||
DATA_RADIX = BIN; % Enter BIN, DEC, HEX, or OCT; unless %
|
||||
% otherwise specified, radixes = HEX %
|
||||
|
||||
-- Specify values for addresses, which can be single address or range
|
||||
|
||||
CONTENT
|
||||
BEGIN
|
||||
[0..FF] : 11111111;
|
||||
0 :
|
||||
11111111 % .. %
|
||||
00100001 % F9 %
|
||||
11111111 % .. %
|
||||
00011100 % F5 %
|
||||
00011010 % F3 %
|
||||
00011000 % F1 %
|
||||
00011001 % F2 %
|
||||
11111111 % F12 %
|
||||
11111111 % .. %
|
||||
00100000 % F10 %
|
||||
|
||||
00100010 % F8 %
|
||||
00100100 % F6 %
|
||||
00011011 % F4 %
|
||||
01011000 % Tab %
|
||||
10001000 % ~` %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
01111001 % Alt %
|
||||
11000000 % Left Shift %
|
||||
11111111 % .. %
|
||||
|
||||
11111001 % Ctrl %
|
||||
11010000 % 'Q' %
|
||||
11011000 % '1' %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
11000001 % 'Z' %
|
||||
11001001 % 'S' %
|
||||
11001000 % 'A' %
|
||||
11010001 % 'W' %
|
||||
|
||||
11011001 % '2' %
|
||||
01110000 % left WIN %
|
||||
11111111 % .. %
|
||||
11000011 % 'C' %
|
||||
11000010 % 'X' %
|
||||
11001010 % 'D' %
|
||||
11010010 % 'E' %
|
||||
11011011 % '4' %
|
||||
11011010 % '3' %
|
||||
10110000 % Right WIN %
|
||||
|
||||
11111111 % .. %
|
||||
11111000 % ' ' %
|
||||
11000100 % 'V' %
|
||||
11001011 % 'F' %
|
||||
11010100 % 'T' %
|
||||
11010011 % 'R' %
|
||||
11011100 % '5' %
|
||||
10111000 % Right Mouse %
|
||||
11111111 % .. %
|
||||
11111011 % 'N' %
|
||||
|
||||
11111100 % 'B' %
|
||||
11110100 % 'H' %
|
||||
11001100 % 'G' %
|
||||
11101100 % 'Y' %
|
||||
11100100 % '6' %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
11111010 % 'M' %
|
||||
11110011 % 'J' %
|
||||
|
||||
11101011 % 'U' %
|
||||
11100011 % '7' %
|
||||
11100010 % '8' %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
10111011 % ',' %
|
||||
11110010 % 'K' %
|
||||
11101010 % 'I' %
|
||||
11101001 % 'O' %
|
||||
11100000 % '0' %
|
||||
|
||||
11100001 % '9' %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
10111010 % '.' %
|
||||
10000100 % '/' %
|
||||
11110001 % 'L' %
|
||||
10101001 % ';' %
|
||||
11101000 % 'P' %
|
||||
10110011 % '-' %
|
||||
11111111 % .. %
|
||||
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
10101000 % "'" %
|
||||
11111111 % .. %
|
||||
10101100 % '[' %
|
||||
10110001 % '=' %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
01011001 % Caps Lock %
|
||||
11000000 % Right SHIFT %
|
||||
|
||||
11110000 % ENTER %
|
||||
10101011 % ']' %
|
||||
11111111 % .. %
|
||||
10001010 % '\' %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
01100000 % Back %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
10010010 % End %
|
||||
11111111 % .. %
|
||||
01011100 % <- %
|
||||
10010000 % Home %
|
||||
11111111 % .. %
|
||||
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
10010001 % ins %
|
||||
01100001 % DEL %
|
||||
01100100 % Dn %
|
||||
10101010 % grey 5 ; ctrl + I %
|
||||
01100010 % -> %
|
||||
01100011 % Up %
|
||||
01111000 % ESC %
|
||||
00111111 % Num %
|
||||
|
||||
11111111 % F11 %
|
||||
10110010 % G+ %
|
||||
01011011 % PDn ; caps + 4 %
|
||||
10110011 % G- %
|
||||
10111100 % G* %
|
||||
01011010 % PUp ; caps + 3 %
|
||||
00000000 % Scrol Lock %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
11111111 % .. %
|
||||
|
||||
11111111 % .. %
|
||||
00100011 % F7 % ;
|
||||
% !! DATA FOR CAPS !! %
|
||||
C0 :
|
||||
11111101 % Function shift %
|
||||
11000000 % Left Shift %
|
||||
11111001 % Ctrl %
|
||||
11111111 ; % no shift %
|
||||
END ;
|
||||
|
||||
|
||||
@ -1,571 +0,0 @@
|
||||
--
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
--
|
||||
CHIP mouse
|
||||
BEGIN
|
||||
DEVICE = EP1K30QC208-3;
|
||||
END;
|
||||
|
||||
DEFAULT_DEVICES
|
||||
BEGIN
|
||||
AUTO_DEVICE = EP1K100FC484-1;
|
||||
AUTO_DEVICE = EP1K100FC256-1;
|
||||
AUTO_DEVICE = EP1K100QC208-1;
|
||||
AUTO_DEVICE = EP1K50FC484-1;
|
||||
AUTO_DEVICE = EP1K50FC256-1;
|
||||
AUTO_DEVICE = EP1K50QC208-1;
|
||||
AUTO_DEVICE = EP1K50TC144-1;
|
||||
AUTO_DEVICE = EP1K30FC256-1;
|
||||
AUTO_DEVICE = EP1K30QC208-1;
|
||||
AUTO_DEVICE = EP1K30TC144-1;
|
||||
AUTO_DEVICE = EP1K10FC256-1;
|
||||
AUTO_DEVICE = EP1K10QC208-1;
|
||||
AUTO_DEVICE = EP1K10TC144-1;
|
||||
AUTO_DEVICE = EP1K10TC100-1;
|
||||
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
|
||||
END;
|
||||
|
||||
TIMING_POINT
|
||||
BEGIN
|
||||
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3;
|
||||
FREQUENCY = 200MHz;
|
||||
MAINTAIN_STABLE_SYNTHESIS = OFF;
|
||||
CUT_ALL_CLEAR_PRESET = ON;
|
||||
CUT_ALL_BIDIR = ON;
|
||||
END;
|
||||
|
||||
IGNORED_ASSIGNMENTS
|
||||
BEGIN
|
||||
FIT_IGNORE_TIMING = OFF;
|
||||
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
|
||||
IGNORE_DEVICE_ASSIGNMENTS = OFF;
|
||||
IGNORE_LC_ASSIGNMENTS = OFF;
|
||||
IGNORE_PIN_ASSIGNMENTS = OFF;
|
||||
IGNORE_CHIP_ASSIGNMENTS = OFF;
|
||||
IGNORE_TIMING_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
|
||||
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_DEVICE_OPTIONS
|
||||
BEGIN
|
||||
MAX7000B_ENABLE_VREFB = OFF;
|
||||
MAX7000B_ENABLE_VREFA = OFF;
|
||||
MAX7000B_VCCIO_IOBANK2 = 3.3V;
|
||||
MAX7000B_VCCIO_IOBANK1 = 3.3V;
|
||||
CONFIG_EPROM_PULLUP_RESISTOR = ON;
|
||||
CONFIG_EPROM_USER_CODE = FFFFFFFF;
|
||||
FLEX_CONFIGURATION_EPROM = AUTO;
|
||||
MAX7000AE_ENABLE_JTAG = ON;
|
||||
MAX7000AE_USER_CODE = FFFFFFFF;
|
||||
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
|
||||
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX6000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
|
||||
MULTIVOLT_IO = OFF;
|
||||
MAX7000S_ENABLE_JTAG = ON;
|
||||
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
|
||||
MAX7000S_USER_CODE = FFFF;
|
||||
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
|
||||
FLEX10K_JTAG_USER_CODE = 7F;
|
||||
ENABLE_INIT_DONE_OUTPUT = OFF;
|
||||
ENABLE_CHIP_WIDE_OE = OFF;
|
||||
ENABLE_CHIP_WIDE_RESET = OFF;
|
||||
nCEO = UNRESERVED;
|
||||
CLKUSR = UNRESERVED;
|
||||
ADD17 = UNRESERVED;
|
||||
ADD16 = UNRESERVED;
|
||||
ADD15 = UNRESERVED;
|
||||
ADD14 = UNRESERVED;
|
||||
ADD13 = UNRESERVED;
|
||||
ADD0_TO_ADD12 = UNRESERVED;
|
||||
SDOUT = RESERVED_DRIVES_OUT;
|
||||
RDCLK = UNRESERVED;
|
||||
RDYnBUSY = UNRESERVED;
|
||||
nWS_nRS_nCS_CS = UNRESERVED;
|
||||
DATA1_TO_DATA7 = UNRESERVED;
|
||||
DATA0 = RESERVED_TRI_STATED;
|
||||
FLEX8000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME = ACTIVE_SERIAL;
|
||||
DISABLE_TIME_OUT = OFF;
|
||||
ENABLE_DCLK_OUTPUT = OFF;
|
||||
RELEASE_CLEARS = OFF;
|
||||
AUTO_RESTART = OFF;
|
||||
USER_CLOCK = OFF;
|
||||
SECURITY_BIT = OFF;
|
||||
RESERVED_PINS_PERCENT = 0;
|
||||
RESERVED_LCELLS_PERCENT = 0;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
|
||||
BEGIN
|
||||
STYLE = FAST;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
|
||||
AUTO_IMPLEMENT_IN_EAB = OFF;
|
||||
AUTO_OPEN_DRAIN_PINS = ON;
|
||||
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
|
||||
AUTO_REGISTER_PACKING = OFF;
|
||||
DEVICE_FAMILY = ACEX1K;
|
||||
AUTO_FAST_IO = OFF;
|
||||
AUTO_GLOBAL_OE = ON;
|
||||
AUTO_GLOBAL_PRESET = ON;
|
||||
AUTO_GLOBAL_CLEAR = ON;
|
||||
AUTO_GLOBAL_CLOCK = ON;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
|
||||
OPTIMIZE_FOR_SPEED = 5;
|
||||
END;
|
||||
|
||||
COMPILER_PROCESSING_CONFIGURATION
|
||||
BEGIN
|
||||
USE_QUARTUS_FITTER = ON;
|
||||
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
|
||||
FITTER_SETTINGS = NORMAL;
|
||||
SMART_RECOMPILE = OFF;
|
||||
GENERATE_AHDL_TDO_FILE = OFF;
|
||||
RPT_FILE_USER_ASSIGNMENTS = ON;
|
||||
RPT_FILE_LCELL_INTERCONNECT = ON;
|
||||
RPT_FILE_HIERARCHY = ON;
|
||||
RPT_FILE_EQUATIONS = ON;
|
||||
LINKED_SNF_EXTRACTOR = OFF;
|
||||
OPTIMIZE_TIMING_SNF = OFF;
|
||||
TIMING_SNF_EXTRACTOR = ON;
|
||||
FUNCTIONAL_SNF_EXTRACTOR = OFF;
|
||||
DESIGN_DOCTOR_RULES = EPLD;
|
||||
DESIGN_DOCTOR = OFF;
|
||||
END;
|
||||
|
||||
COMPILER_INTERFACES_CONFIGURATION
|
||||
BEGIN
|
||||
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
|
||||
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
|
||||
EDIF_BUS_DELIMITERS = [];
|
||||
EDIF_FLATTEN_BUS = OFF;
|
||||
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
|
||||
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
|
||||
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
|
||||
EDIF_OUTPUT_USE_EDC = OFF;
|
||||
EDIF_INPUT_USE_LMF2 = OFF;
|
||||
EDIF_INPUT_USE_LMF1 = OFF;
|
||||
EDIF_OUTPUT_GND = GND;
|
||||
EDIF_OUTPUT_VCC = VCC;
|
||||
EDIF_INPUT_GND = GND;
|
||||
EDIF_INPUT_VCC = VCC;
|
||||
EDIF_OUTPUT_EDC_FILE = *.edc;
|
||||
EDIF_INPUT_LMF2 = *.lmf;
|
||||
EDIF_INPUT_LMF1 = *.lmf;
|
||||
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
|
||||
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
|
||||
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
|
||||
VHDL_FLATTEN_BUS = OFF;
|
||||
VERILOG_FLATTEN_BUS = OFF;
|
||||
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
VHDL_WRITER_VERSION = VHDL93;
|
||||
VHDL_READER_VERSION = VHDL93;
|
||||
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
|
||||
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
|
||||
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
|
||||
SYNOPSYS_DESIGNWARE = OFF;
|
||||
SYNOPSYS_COMPILER = DESIGN;
|
||||
USE_SYNOPSYS_SYNTHESIS = OFF;
|
||||
VHDL_NETLIST_WRITER = OFF;
|
||||
VERILOG_NETLIST_WRITER = OFF;
|
||||
XNF_GENERATE_AHDL_TDX_FILE = ON;
|
||||
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
|
||||
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
|
||||
EDIF_OUTPUT_VERSION = 200;
|
||||
EDIF_NETLIST_WRITER = OFF;
|
||||
END;
|
||||
|
||||
CUSTOM_DESIGN_DOCTOR_RULES
|
||||
BEGIN
|
||||
MASTER_RESET = OFF;
|
||||
EXPANDER_NETWORKS = ON;
|
||||
RACE_CONDITIONS = ON;
|
||||
DELAY_CHAINS = ON;
|
||||
ASYNCHRONOUS_INPUTS = ON;
|
||||
PRESET_CLEAR_NETWORKS = ON;
|
||||
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
|
||||
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
|
||||
MULTI_CLOCK_NETWORKS = ON;
|
||||
MULTI_LEVEL_CLOCKS = ON;
|
||||
GATED_CLOCKS = ON;
|
||||
RIPPLE_CLOCKS = ON;
|
||||
END;
|
||||
|
||||
SIMULATOR_CONFIGURATION
|
||||
BEGIN
|
||||
END_TIME = 10.0us;
|
||||
BIDIR_PIN = STRONG;
|
||||
START_TIME = 0.0ns;
|
||||
GLITCH_TIME = 0.0ns;
|
||||
GLITCH = OFF;
|
||||
OSCILLATION_TIME = 0.0ns;
|
||||
OSCILLATION = OFF;
|
||||
CHECK_OUTPUTS = OFF;
|
||||
SETUP_HOLD = OFF;
|
||||
USE_DEVICE = OFF;
|
||||
END;
|
||||
|
||||
TIMING_ANALYZER_CONFIGURATION
|
||||
BEGIN
|
||||
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
|
||||
LIST_PATH_FREQUENCY = 10MHz;
|
||||
LIST_PATH_COUNT = 10;
|
||||
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
|
||||
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
|
||||
INCLUDE_PATHS_LESS_THAN = OFF;
|
||||
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
|
||||
INCLUDE_PATHS_GREATER_THAN = OFF;
|
||||
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
|
||||
CELL_WIDTH = 18;
|
||||
LIST_ONLY_LONGEST_PATH = ON;
|
||||
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
|
||||
CUT_OFF_IO_PIN_FEEDBACK = ON;
|
||||
AUTO_RECALCULATE = OFF;
|
||||
ANALYSIS_MODE = DELAY_MATRIX;
|
||||
END;
|
||||
|
||||
OTHER_CONFIGURATION
|
||||
BEGIN
|
||||
EXPLICIT_FAMILY = 1;
|
||||
ROW_PINS_LCELL_INSERT = ON;
|
||||
CARRY_OUT_PINS_LCELL_INSERT = OFF;
|
||||
NORMAL_LCELL_INSERT = ON;
|
||||
LAST_MAXPLUS2_VERSION = 10.0;
|
||||
FLEX_10K_52_COLUMNS = 40;
|
||||
DEFAULT_9K_EXP_PER_LCELL = 1/2;
|
||||
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
|
||||
LCELLS_PER_ROW_PERCENT = 100;
|
||||
FAN_IN_PER_LCELL_PERCENT = 100;
|
||||
EXP_PER_LCELL_PERCENT = 100;
|
||||
ROW_PINS_PERCENT = 50;
|
||||
ORIGINAL_MAXPLUS2_VERSION = 10.0;
|
||||
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = ON;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = AUTO;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = AUTO;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = MANUAL;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = MANUAL;
|
||||
END;
|
||||
|
||||
@ -1,26 +0,0 @@
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
|
||||
-- MAX+plus II Include File
|
||||
-- Version 10.0 9/14/2000
|
||||
-- Created: Sat Jun 16 17:49:35 2001
|
||||
|
||||
FUNCTION mouse (mouse_d, clk)
|
||||
RETURNS (out_x[9..0], out_y[9..0], out_k[1..0], int);
|
||||
@ -1,65 +0,0 @@
|
||||
DEPTH = 256; % Memory depth and width are required %
|
||||
WIDTH = 16; % Enter a decimal number %
|
||||
|
||||
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
|
||||
DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless %
|
||||
% otherwise specified, radixes = HEX %
|
||||
|
||||
-- Specify values for addresses, which can be single address or range
|
||||
|
||||
CONTENT
|
||||
BEGIN
|
||||
|
||||
[0..FF] : 0;
|
||||
|
||||
%
|
||||
11
|
||||
1211
|
||||
122211
|
||||
12222211
|
||||
1222222211
|
||||
122222222211
|
||||
1222222211
|
||||
12222221
|
||||
12222221
|
||||
121112221
|
||||
11 12221
|
||||
1 1221
|
||||
111
|
||||
|
||||
|
||||
|
||||
%
|
||||
|
||||
00 : 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0;
|
||||
10 : 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0;
|
||||
20 : 1 2 2 2 1 1 0 0 0 0 0 0 0 0 0 0;
|
||||
30 : 1 2 2 2 2 2 1 1 0 0 0 0 0 0 0 0;
|
||||
40 : 1 2 2 2 2 2 2 2 1 1 0 0 0 0 0 0;
|
||||
50 : 1 2 2 2 2 2 2 2 2 2 1 1 0 0 0 0;
|
||||
60 : 1 2 2 2 2 2 2 2 1 1 0 0 0 0 0 0;
|
||||
E0 : 1 2 2 2 2 2 2 1 0 0 0 0 0 0 0 0;
|
||||
70 : 1 2 2 2 2 2 2 1 0 0 0 0 0 0 0 0;
|
||||
80 : 1 2 1 1 1 2 2 2 1 0 0 0 0 0 0 0;
|
||||
90 : 1 1 0 0 0 1 2 2 2 1 0 0 0 0 0 0;
|
||||
A0 : 1 0 0 0 0 0 1 2 2 1 0 0 0 0 0 0;
|
||||
B0 : 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0;
|
||||
C0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0;
|
||||
D0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0;
|
||||
E0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0;
|
||||
F0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0;
|
||||
|
||||
%
|
||||
|
||||
1110 0000 0000 0 00 0000 0000 0000 0000
|
||||
1000 0000 0000 0100 0000 0100 0000 0000
|
||||
1000 1100 1010 0000 1100 1110 0100 1010
|
||||
1110 1010 1100 0100 1010 0100 1010 1100
|
||||
0010 1010 1000 0100 1010 0100 1110 1000
|
||||
0010 1100 1000 0100 1010 0100 1000 1000
|
||||
1110 1000 1000 0100 1010 0010 0110 1000
|
||||
0000 1000 0000 0000 0000 0000 0000 0000
|
||||
|
||||
%
|
||||
|
||||
END;
|
||||
@ -1,76 +0,0 @@
|
||||
|
||||
TITLE "Sp-Mouse";
|
||||
|
||||
INCLUDE "lpm_add_sub";
|
||||
|
||||
SUBDESIGN mouse
|
||||
(
|
||||
MOUSE_D : INPUT;
|
||||
CLK : INPUT;
|
||||
OUT_X[9..0] : OUTPUT;
|
||||
OUT_Y[9..0] : OUTPUT;
|
||||
OUT_K[1..0] : OUTPUT;
|
||||
INT : OUTPUT;
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
SUM_X[9..0] : DFFE;
|
||||
SUM_Y[9..0] : DFFE;
|
||||
|
||||
CT[3..0] : DFF;
|
||||
RG[9..0] : DFFE;
|
||||
STATE[1..0] : DFFE;
|
||||
RGK[5..0] : DFFE;
|
||||
|
||||
MOUSE_IMP : NODE;
|
||||
|
||||
DDX[7..0] : NODE;
|
||||
DDY[7..0] : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
CT[].clk = CLK;
|
||||
|
||||
MOUSE_IMP = MOUSE_D xor !DFF(MOUSE_D,CLK,,);
|
||||
|
||||
CT[].clrn = MOUSE_IMP;
|
||||
|
||||
IF CT[] == 12 THEN
|
||||
CT[] = GND;
|
||||
ELSE
|
||||
CT[] = CT[]+1;
|
||||
END IF;
|
||||
|
||||
RG[].clk = CLK;
|
||||
RG[].ena = (CT[] == 4) or !RG0;
|
||||
RG[].d = ((MOUSE_D,RG[9..1]) or !RG0);
|
||||
RG[].prn = VCC;
|
||||
|
||||
STATE[].ena = !RG0;
|
||||
STATE[].clk = CLK;
|
||||
|
||||
STATE[].d = (STATE0,RG7);
|
||||
|
||||
RGK[].clk = CLK;
|
||||
RGK[].ena = (RG7 & !RG0);
|
||||
RGK[].d = RG[6..1];
|
||||
|
||||
DDX[] = (RGK[1..0],RG[6..1]);
|
||||
DDY[] = (RGK[3..2],RG[6..1]);
|
||||
|
||||
SUM_X[].ena = LCELL(!RG7 & (STATE[] == 1) & !RG0);
|
||||
SUM_Y[].ena = LCELL(!RG7 & (STATE[] == 2) & !RG0);
|
||||
|
||||
SUM_X[].clk = CLK;
|
||||
SUM_Y[].clk = CLK;
|
||||
|
||||
SUM_X[] = SUM_X[] + (DDX7,DDX7,DDX[]);
|
||||
SUM_Y[] = SUM_Y[] + (DDY7,DDY7,DDY[]);
|
||||
|
||||
OUT_X[] = SUM_X[];
|
||||
OUT_Y[] = SUM_Y[];
|
||||
OUT_K[] = RGK[5..4];
|
||||
|
||||
INT = DFF(((STATE[] == 2) & !RG0),CLK,,);
|
||||
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,588 +0,0 @@
|
||||
--
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
--
|
||||
CHIP video2
|
||||
BEGIN
|
||||
DEVICE = AUTO;
|
||||
END;
|
||||
|
||||
DEFAULT_DEVICES
|
||||
BEGIN
|
||||
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
|
||||
AUTO_DEVICE = EP1K30TC144-1;
|
||||
AUTO_DEVICE = EP1K30QC208-1;
|
||||
AUTO_DEVICE = EP1K30FC256-1;
|
||||
AUTO_DEVICE = EP1K50TC144-1;
|
||||
AUTO_DEVICE = EP1K50QC208-1;
|
||||
AUTO_DEVICE = EP1K50FC256-1;
|
||||
AUTO_DEVICE = EP1K50FC484-1;
|
||||
AUTO_DEVICE = EP1K100QC208-1;
|
||||
AUTO_DEVICE = EP1K100FC256-1;
|
||||
AUTO_DEVICE = EP1K100FC484-1;
|
||||
END;
|
||||
|
||||
TIMING_POINT
|
||||
BEGIN
|
||||
MAINTAIN_STABLE_SYNTHESIS = ON;
|
||||
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30FC256-3;
|
||||
CUT_ALL_BIDIR = ON;
|
||||
CUT_ALL_CLEAR_PRESET = ON;
|
||||
FREQUENCY = 200MHz;
|
||||
END;
|
||||
|
||||
IGNORED_ASSIGNMENTS
|
||||
BEGIN
|
||||
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
|
||||
IGNORE_TIMING_ASSIGNMENTS = OFF;
|
||||
IGNORE_CHIP_ASSIGNMENTS = OFF;
|
||||
IGNORE_PIN_ASSIGNMENTS = OFF;
|
||||
IGNORE_LC_ASSIGNMENTS = OFF;
|
||||
IGNORE_DEVICE_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
|
||||
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
|
||||
FIT_IGNORE_TIMING = OFF;
|
||||
END;
|
||||
|
||||
LOGIC_OPTIONS
|
||||
BEGIN
|
||||
|VAO15 : FAST_IO = ON;
|
||||
|VAO14 : FAST_IO = ON;
|
||||
|VAO13 : FAST_IO = ON;
|
||||
|VAO12 : FAST_IO = ON;
|
||||
|VAO11 : FAST_IO = ON;
|
||||
|VAO10 : FAST_IO = ON;
|
||||
|VAO9 : FAST_IO = ON;
|
||||
|VAO8 : FAST_IO = ON;
|
||||
|VAO7 : FAST_IO = ON;
|
||||
|VAO6 : FAST_IO = ON;
|
||||
|VAO5 : FAST_IO = ON;
|
||||
|VAO4 : FAST_IO = ON;
|
||||
|VAO3 : FAST_IO = ON;
|
||||
|VAO2 : FAST_IO = ON;
|
||||
|VAO1 : FAST_IO = ON;
|
||||
|VAO0 : FAST_IO = ON;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_DEVICE_OPTIONS
|
||||
BEGIN
|
||||
RESERVED_LCELLS_PERCENT = 0;
|
||||
RESERVED_PINS_PERCENT = 0;
|
||||
SECURITY_BIT = OFF;
|
||||
USER_CLOCK = OFF;
|
||||
AUTO_RESTART = OFF;
|
||||
RELEASE_CLEARS = OFF;
|
||||
ENABLE_DCLK_OUTPUT = OFF;
|
||||
DISABLE_TIME_OUT = OFF;
|
||||
CONFIG_SCHEME = ACTIVE_SERIAL;
|
||||
FLEX8000_ENABLE_JTAG = OFF;
|
||||
DATA0 = RESERVED_TRI_STATED;
|
||||
DATA1_TO_DATA7 = UNRESERVED;
|
||||
nWS_nRS_nCS_CS = UNRESERVED;
|
||||
RDYnBUSY = UNRESERVED;
|
||||
RDCLK = UNRESERVED;
|
||||
SDOUT = RESERVED_DRIVES_OUT;
|
||||
ADD0_TO_ADD12 = UNRESERVED;
|
||||
ADD13 = UNRESERVED;
|
||||
ADD14 = UNRESERVED;
|
||||
ADD15 = UNRESERVED;
|
||||
ADD16 = UNRESERVED;
|
||||
ADD17 = UNRESERVED;
|
||||
CLKUSR = UNRESERVED;
|
||||
nCEO = UNRESERVED;
|
||||
ENABLE_CHIP_WIDE_RESET = OFF;
|
||||
ENABLE_CHIP_WIDE_OE = OFF;
|
||||
ENABLE_INIT_DONE_OUTPUT = OFF;
|
||||
FLEX10K_JTAG_USER_CODE = 7F;
|
||||
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
|
||||
MAX7000S_USER_CODE = FFFF;
|
||||
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
|
||||
MAX7000S_ENABLE_JTAG = ON;
|
||||
MULTIVOLT_IO = OFF;
|
||||
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
|
||||
FLEX6000_ENABLE_JTAG = OFF;
|
||||
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
|
||||
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
MAX7000AE_USER_CODE = FFFFFFFF;
|
||||
MAX7000AE_ENABLE_JTAG = ON;
|
||||
FLEX_CONFIGURATION_EPROM = AUTO;
|
||||
CONFIG_EPROM_USER_CODE = FFFFFFFF;
|
||||
CONFIG_EPROM_PULLUP_RESISTOR = ON;
|
||||
MAX7000B_VCCIO_IOBANK1 = 3.3V;
|
||||
MAX7000B_VCCIO_IOBANK2 = 3.3V;
|
||||
MAX7000B_ENABLE_VREFA = OFF;
|
||||
MAX7000B_ENABLE_VREFB = OFF;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
|
||||
BEGIN
|
||||
OPTIMIZE_FOR_SPEED = 5;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
|
||||
AUTO_GLOBAL_CLOCK = ON;
|
||||
AUTO_GLOBAL_CLEAR = ON;
|
||||
AUTO_GLOBAL_PRESET = ON;
|
||||
AUTO_GLOBAL_OE = ON;
|
||||
AUTO_FAST_IO = OFF;
|
||||
DEVICE_FAMILY = ACEX1K;
|
||||
AUTO_REGISTER_PACKING = OFF;
|
||||
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
|
||||
AUTO_OPEN_DRAIN_PINS = ON;
|
||||
AUTO_IMPLEMENT_IN_EAB = OFF;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
|
||||
STYLE = FAST;
|
||||
END;
|
||||
|
||||
COMPILER_PROCESSING_CONFIGURATION
|
||||
BEGIN
|
||||
USE_QUARTUS_FITTER = ON;
|
||||
DESIGN_DOCTOR = OFF;
|
||||
DESIGN_DOCTOR_RULES = EPLD;
|
||||
FUNCTIONAL_SNF_EXTRACTOR = OFF;
|
||||
TIMING_SNF_EXTRACTOR = ON;
|
||||
OPTIMIZE_TIMING_SNF = OFF;
|
||||
LINKED_SNF_EXTRACTOR = OFF;
|
||||
RPT_FILE_EQUATIONS = ON;
|
||||
RPT_FILE_HIERARCHY = ON;
|
||||
RPT_FILE_LCELL_INTERCONNECT = ON;
|
||||
RPT_FILE_USER_ASSIGNMENTS = ON;
|
||||
GENERATE_AHDL_TDO_FILE = OFF;
|
||||
SMART_RECOMPILE = OFF;
|
||||
FITTER_SETTINGS = NORMAL;
|
||||
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
|
||||
END;
|
||||
|
||||
COMPILER_INTERFACES_CONFIGURATION
|
||||
BEGIN
|
||||
EDIF_NETLIST_WRITER = OFF;
|
||||
EDIF_OUTPUT_VERSION = 200;
|
||||
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
|
||||
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
|
||||
XNF_GENERATE_AHDL_TDX_FILE = ON;
|
||||
VERILOG_NETLIST_WRITER = OFF;
|
||||
VHDL_NETLIST_WRITER = OFF;
|
||||
USE_SYNOPSYS_SYNTHESIS = OFF;
|
||||
SYNOPSYS_COMPILER = DESIGN;
|
||||
SYNOPSYS_DESIGNWARE = OFF;
|
||||
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
|
||||
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
|
||||
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
|
||||
VHDL_READER_VERSION = VHDL87;
|
||||
VHDL_WRITER_VERSION = VHDL87;
|
||||
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_FLATTEN_BUS = OFF;
|
||||
VHDL_FLATTEN_BUS = OFF;
|
||||
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
|
||||
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
|
||||
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
|
||||
EDIF_INPUT_LMF1 = *.lmf;
|
||||
EDIF_INPUT_LMF2 = *.lmf;
|
||||
EDIF_OUTPUT_EDC_FILE = *.edc;
|
||||
EDIF_INPUT_VCC = VCC;
|
||||
EDIF_INPUT_GND = GND;
|
||||
EDIF_OUTPUT_VCC = VCC;
|
||||
EDIF_OUTPUT_GND = GND;
|
||||
EDIF_INPUT_USE_LMF1 = OFF;
|
||||
EDIF_INPUT_USE_LMF2 = OFF;
|
||||
EDIF_OUTPUT_USE_EDC = OFF;
|
||||
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
|
||||
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
|
||||
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
|
||||
EDIF_FLATTEN_BUS = OFF;
|
||||
EDIF_BUS_DELIMITERS = [];
|
||||
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
|
||||
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
|
||||
END;
|
||||
|
||||
CUSTOM_DESIGN_DOCTOR_RULES
|
||||
BEGIN
|
||||
RIPPLE_CLOCKS = ON;
|
||||
GATED_CLOCKS = ON;
|
||||
MULTI_LEVEL_CLOCKS = ON;
|
||||
MULTI_CLOCK_NETWORKS = ON;
|
||||
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
|
||||
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
|
||||
PRESET_CLEAR_NETWORKS = ON;
|
||||
ASYNCHRONOUS_INPUTS = ON;
|
||||
DELAY_CHAINS = ON;
|
||||
RACE_CONDITIONS = ON;
|
||||
EXPANDER_NETWORKS = ON;
|
||||
MASTER_RESET = OFF;
|
||||
END;
|
||||
|
||||
SIMULATOR_CONFIGURATION
|
||||
BEGIN
|
||||
CHECK_OUTPUTS = OFF;
|
||||
USE_DEVICE = OFF;
|
||||
SETUP_HOLD = OFF;
|
||||
OSCILLATION = OFF;
|
||||
OSCILLATION_TIME = 0.0ns;
|
||||
GLITCH = OFF;
|
||||
GLITCH_TIME = 0.0ns;
|
||||
START_TIME = 0.0ns;
|
||||
BIDIR_PIN = STRONG;
|
||||
END_TIME = 10.0us;
|
||||
END;
|
||||
|
||||
TIMING_ANALYZER_CONFIGURATION
|
||||
BEGIN
|
||||
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
|
||||
AUTO_RECALCULATE = OFF;
|
||||
CUT_OFF_IO_PIN_FEEDBACK = ON;
|
||||
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
|
||||
LIST_ONLY_LONGEST_PATH = ON;
|
||||
CELL_WIDTH = 18;
|
||||
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
|
||||
INCLUDE_PATHS_GREATER_THAN = OFF;
|
||||
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
|
||||
INCLUDE_PATHS_LESS_THAN = OFF;
|
||||
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
|
||||
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
|
||||
LIST_PATH_COUNT = 10;
|
||||
LIST_PATH_FREQUENCY = 10MHz;
|
||||
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
|
||||
END;
|
||||
|
||||
OTHER_CONFIGURATION
|
||||
BEGIN
|
||||
LAST_MAXPLUS2_VERSION = 10.0;
|
||||
EXPLICIT_FAMILY = 1;
|
||||
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
|
||||
ORIGINAL_MAXPLUS2_VERSION = 9.6;
|
||||
ROW_PINS_PERCENT = 50;
|
||||
EXP_PER_LCELL_PERCENT = 100;
|
||||
FAN_IN_PER_LCELL_PERCENT = 100;
|
||||
LCELLS_PER_ROW_PERCENT = 100;
|
||||
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
|
||||
DEFAULT_9K_EXP_PER_LCELL = 1/2;
|
||||
FLEX_10K_52_COLUMNS = 40;
|
||||
NORMAL_LCELL_INSERT = ON;
|
||||
CARRY_OUT_PINS_LCELL_INSERT = OFF;
|
||||
ROW_PINS_LCELL_INSERT = ON;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
|
||||
BEGIN
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
MINIMIZATION = FULL;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
TURBO_BIT = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
FAST_IO = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
|
||||
BEGIN
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
MINIMIZATION = FULL;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
TURBO_BIT = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
FAST_IO = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
|
||||
BEGIN
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
MINIMIZATION = FULL;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
FAST_IO = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
||||
BEGIN
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
MINIMIZATION = FULL;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
||||
BEGIN
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
TURBO_BIT = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
FAST_IO = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
||||
BEGIN
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
TURBO_BIT = ON;
|
||||
PARALLEL_EXPANDERS = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
FAST_IO = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
||||
BEGIN
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
FAST_IO = OFF;
|
||||
MINIMIZATION = FULL;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
||||
BEGIN
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
MINIMIZATION = FULL;
|
||||
CASCADE_CHAIN = AUTO;
|
||||
CARRY_CHAIN = AUTO;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
||||
BEGIN
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
MINIMIZATION = PARTIAL;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
FAST_IO = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
||||
BEGIN
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
MINIMIZATION = PARTIAL;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
FAST_IO = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
||||
BEGIN
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN_LENGTH = -1;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CARRY_CHAIN_LENGTH = -1;
|
||||
MINIMIZATION = PARTIAL;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
FAST_IO = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
||||
BEGIN
|
||||
CASCADE_CHAIN = MANUAL;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CARRY_CHAIN = MANUAL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
MINIMIZATION = PARTIAL;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
REFACTORIZATION = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
END;
|
||||
|
||||
@ -1,27 +0,0 @@
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
|
||||
-- MAX+plus II Include File
|
||||
-- Version 10.0 9/14/2000
|
||||
-- Created: Mon Nov 19 00:36:42 2001
|
||||
|
||||
FUNCTION video2 (clk42, start_up, copy_sinc_h, copy_sinc_v, wr, vai[19..0], d[7..0], mdi[15..0], vdm0[7..0], vdm1[7..0], vdm2[7..0], vdm3[7..0], zx_port[7..0], dir_port[7..0], double_cas, mouse_x[9..0], mouse_y[9..0])
|
||||
WITH (MODE, MOUSE)
|
||||
RETURNS (ct[5..0], cth[5..0], ctv[8..0], ctf[6..0], blank, vao[15..0], vdo0[7..0], vdo1[7..0], vdo2[7..0], vdo3[7..0], v_wr[3..0], v_wen[3..0], v_cs[1..0], wr_pix, intt);
|
||||
@ -1,783 +0,0 @@
|
||||
|
||||
TITLE "Video-controller";
|
||||
|
||||
INCLUDE "lpm_ram_dp";
|
||||
|
||||
PARAMETERS
|
||||
(
|
||||
MODE = "SPRINTER",
|
||||
MOUSE = "NO",
|
||||
HOR_PLACE = H"50",
|
||||
VER_PLACE = H"91" -- 122h/2
|
||||
);
|
||||
|
||||
SUBDESIGN video2
|
||||
(
|
||||
CLK42 : INPUT;
|
||||
|
||||
CT[5..0] : OUTPUT;
|
||||
CTH[5..0] : OUTPUT;
|
||||
CTV[8..0] : OUTPUT;
|
||||
CTF[6..0] : OUTPUT;
|
||||
|
||||
BLANK : OUTPUT;
|
||||
|
||||
START_UP : INPUT;
|
||||
COPY_SINC_H : INPUT;
|
||||
COPY_SINC_V : INPUT;
|
||||
|
||||
WR : INPUT;
|
||||
|
||||
VAI[19..0] : INPUT; -- input screen adress
|
||||
|
||||
VAO[15..0] : OUTPUT;
|
||||
|
||||
D[7..0] : INPUT;
|
||||
MDI[15..0] : INPUT;
|
||||
|
||||
VDO0[7..0] : OUTPUT;
|
||||
VDO1[7..0] : OUTPUT;
|
||||
VDO2[7..0] : OUTPUT;
|
||||
VDO3[7..0] : OUTPUT;
|
||||
|
||||
VDM0[7..0] : INPUT;
|
||||
VDM1[7..0] : INPUT;
|
||||
VDM2[7..0] : INPUT;
|
||||
VDM3[7..0] : INPUT;
|
||||
|
||||
V_WR[3..0] : OUTPUT;
|
||||
V_WEN[3..0] : OUTPUT;
|
||||
|
||||
V_CS[1..0] : OUTPUT;
|
||||
WR_PIX : OUTPUT;
|
||||
|
||||
-- ZX_COLOR[3..0] : OUTPUT;
|
||||
|
||||
ZX_PORT[7..0] : INPUT;
|
||||
DIR_PORT[7..0] : INPUT;
|
||||
|
||||
%
|
||||
bit0 - Spectrum SCREEN Switch
|
||||
bit1 - Spectrum Adress MODE
|
||||
bit2 - Write to Spectrum Screen OFF
|
||||
bit3 - MODE page 0/1
|
||||
bit4 - MODE on/off screen
|
||||
|
||||
bit7..5 - Border
|
||||
%
|
||||
|
||||
INTT : OUTPUT;
|
||||
|
||||
DOUBLE_CAS : INPUT;
|
||||
|
||||
MOUSE_X[9..0] : INPUT;
|
||||
MOUSE_Y[9..0] : INPUT;
|
||||
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
-- CLK84 : NODE;
|
||||
-- CLK84_X : NODE;
|
||||
-- CLK84_Y : NODE;
|
||||
|
||||
ZX_COLOR[3..0] : NODE;
|
||||
|
||||
CT[5..0] : DFFE;
|
||||
CTH[5..0] : DFFE;
|
||||
CTV[8..0] : DFFE;
|
||||
CTF[6..0] : DFF;
|
||||
|
||||
VXA[19..0] : DFFE;
|
||||
|
||||
VXD0[7..0] : DFFE;
|
||||
VXD1[7..0] : DFFE;
|
||||
VXD2[7..0] : DFFE;
|
||||
VXD3[7..0] : DFFE;
|
||||
|
||||
E_WR : NODE;
|
||||
E_WRD : NODE;
|
||||
|
||||
BLANK : NODE;
|
||||
BORD : NODE;
|
||||
-- INTT_T : NODE;
|
||||
INTTX : NODE;
|
||||
|
||||
VLA[17..0] : DFF;
|
||||
-- SVA[17..0] : NODE;
|
||||
SVA[17..0] : DFF;
|
||||
-- RSVA[8..0] : LCELL;
|
||||
RSVA[8..0] : NODE;
|
||||
-- RSVA[8..0] : DFF;
|
||||
|
||||
V_CST[1..0] : DFF;
|
||||
VCM[2..0] : DFF;
|
||||
TSN_W3 : DFF;
|
||||
V_WE : DFF;
|
||||
V_WEX : DFF;
|
||||
|
||||
V_WEM : NODE;
|
||||
V_WEM2 : NODE;
|
||||
V_WRM : NODE;
|
||||
V_WRM2 : NODE;
|
||||
%
|
||||
V_WEMM : NODE;
|
||||
V_WEMMM : NODE;
|
||||
V_WEMMN : NODE;
|
||||
V_WEMMO : NODE;
|
||||
%
|
||||
V_WEMM : NODE;
|
||||
V_WEMMM : NODE;
|
||||
V_WEMMN : NODE;
|
||||
V_WEMMO : NODE;
|
||||
V_WEMMP : NODE;
|
||||
V_WEMMQ : NODE;
|
||||
V_WEMMR : NODE;
|
||||
V_WEMMS : NODE;
|
||||
V_WEMMT : NODE;
|
||||
V_WEMMU : NODE;
|
||||
V_WEMMV : NODE;
|
||||
V_WEMMW : NODE;
|
||||
V_WEMMX : NODE;
|
||||
V_WEMMY : NODE;
|
||||
V_WEMMZ : NODE;
|
||||
|
||||
|
||||
|
||||
V_WET[3..0] : DFF;
|
||||
|
||||
D_PIC0[7..0] : DFFE;
|
||||
-- D_PIC0_[7..0] : LCELL;
|
||||
|
||||
D_PIC0_[7..0] : DFFE;
|
||||
D_PIC1_[7..0] : DFFE;
|
||||
D_PIC2_[7..0] : DFFE;
|
||||
D_PIC3_[7..0] : DFFE;
|
||||
|
||||
D_PICX_[7..0] : NODE;
|
||||
|
||||
LWR_PIC : NODE;
|
||||
LWR_COL : NODE;
|
||||
|
||||
WR_PIC : DFF;
|
||||
WR_COL : DFF;
|
||||
LD_PIC : NODE;
|
||||
MXL: NODE;
|
||||
MXR: NODE;
|
||||
|
||||
RBRVA[10..8]: DFF;
|
||||
BRVA[7..0] : DFF;
|
||||
DCOL[7..0] : DFFE;
|
||||
|
||||
MXWE : NODE;
|
||||
-- MXCE : NODE;
|
||||
|
||||
AX128 : NODE;
|
||||
|
||||
BRD[2..0] : NODE;
|
||||
|
||||
ZX_COL[3..0] : LCELL;
|
||||
|
||||
ZXA15 : NODE;
|
||||
ZXS[5..0] : NODE;
|
||||
ZX_SCREEN : NODE;
|
||||
SCR128 : NODE;
|
||||
|
||||
MODE0[7..0] : DFFE;
|
||||
MODE1[7..0] : DFFE;
|
||||
MODE2[7..0] : DFFE;
|
||||
-- MODE3[7..0] : DFF;
|
||||
|
||||
WR_MODE : DFF;
|
||||
LWR_MODE : NODE;
|
||||
X_MODE[7..4]: NODE;
|
||||
X_MODE_BOND : NODE;
|
||||
|
||||
-- M_CTV[2..0] : DFF;
|
||||
-- M_CT[5..3] : DFF;
|
||||
M_CTV[2..0] : LCELL;
|
||||
M_CT[5..3] : LCELL;
|
||||
|
||||
DOUBLE : DFFE;
|
||||
|
||||
PIC_CLK : NODE;
|
||||
|
||||
MS_X[9..0] : DFF;
|
||||
MS_Y[9..0] : DFF;
|
||||
|
||||
MS_POINT : NODE;
|
||||
MS_POINT2 : NODE;
|
||||
MS_PNT : NODE;
|
||||
|
||||
MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF");
|
||||
|
||||
SCR_ENA : DFFE;
|
||||
V_WR_[3..0] : LCELL;
|
||||
V_WEY[3..0] : LCELL;
|
||||
|
||||
V_WE_R : NODE;
|
||||
|
||||
V_CSX[3..0] : NODE;
|
||||
|
||||
V_EN[3..0] : NODE;
|
||||
|
||||
F_WR : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
DEFAULTS
|
||||
WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC;
|
||||
V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC;
|
||||
V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC;
|
||||
V_WET[].d = VCC;
|
||||
END DEFAULTS;
|
||||
|
||||
ZX_COLOR[] = ZX_COL[];
|
||||
|
||||
-- === MOUSE counters ========
|
||||
|
||||
MS_X[].clk = !CT1;
|
||||
CASE LCELL(CTH[5..2] == 12) IS
|
||||
WHEN 0 => MS_X[] = MS_X[] + 1;
|
||||
WHEN 1 => MS_X[] = (!MOUSE_X[9..0]);
|
||||
END CASE;
|
||||
|
||||
MS_Y[].clk = !CTH5;
|
||||
CASE LCELL(CTV8 & !CTV5 & CTV4) IS
|
||||
WHEN 0 => MS_Y[] = MS_Y[] + 1;
|
||||
WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]);
|
||||
END CASE;
|
||||
|
||||
MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,);
|
||||
|
||||
MS_DAT.wren = GND;
|
||||
MS_DAT.data[] = GND;
|
||||
MS_DAT.wraddress[] = GND;
|
||||
MS_DAT.wrclock = CLK42;
|
||||
MS_DAT.wrclken = GND;
|
||||
MS_DAT.rden = VCC;
|
||||
MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]);
|
||||
MS_DAT.rdclock = CLK42;
|
||||
MS_DAT.rdclken = VCC;
|
||||
|
||||
IF MOUSE == "NO" GENERATE
|
||||
MS_POINT = GND;
|
||||
MS_POINT2 = GND;
|
||||
ELSE GENERATE
|
||||
MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,);
|
||||
MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,);
|
||||
END GENERATE;
|
||||
|
||||
-- === Sinc-counts GENERATOR ============================================
|
||||
|
||||
-- CT[].clrn = START_UP;
|
||||
|
||||
-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE;
|
||||
-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE;
|
||||
|
||||
-- CTV[].clrn = !COPY_SINC_V or VER_PLACE;
|
||||
-- CTV[].prn = !COPY_SINC_V or !VER_PLACE;
|
||||
|
||||
CT[5].clrn = !COPY_SINC_H;
|
||||
|
||||
-- set CTH to 50 (32h)
|
||||
CTH[0].clrn = !COPY_SINC_H;
|
||||
CTH[1].prn = !COPY_SINC_H;
|
||||
CTH[2].clrn = !COPY_SINC_H;
|
||||
CTH[3].clrn = !COPY_SINC_H;
|
||||
CTH[4].prn = !COPY_SINC_H;
|
||||
CTH[5].prn = !COPY_SINC_H;
|
||||
|
||||
-- set CTV to 122h
|
||||
CTV[0].clrn = !COPY_SINC_V;
|
||||
CTV[1].prn = !COPY_SINC_V;
|
||||
CTV[3..2].clrn = !COPY_SINC_V;
|
||||
|
||||
CTV[4].clrn = !COPY_SINC_V;
|
||||
CTV[5].prn = !COPY_SINC_V;
|
||||
CTV[7..6].clrn = !COPY_SINC_V;
|
||||
CTV[8].prn = !COPY_SINC_V;
|
||||
|
||||
CT[5..0].clk = CLK42;
|
||||
CTH[5..0].clk = CLK42;
|
||||
CTV[8..0].clk = CLK42;
|
||||
|
||||
CT[2..0].ena = VCC;
|
||||
|
||||
CASE CT[2..0] IS
|
||||
WHEN 0 => CT[2..0] = 1;
|
||||
WHEN 1 => CT[2..0] = 2;
|
||||
WHEN 2 => CT[2..0] = 4;
|
||||
WHEN 3 => CT[2..0] = 4;
|
||||
WHEN 4 => CT[2..0] = 5;
|
||||
WHEN 5 => CT[2..0] = 6;
|
||||
WHEN 6 => CT[2..0] = 0;
|
||||
WHEN 7 => CT[2..0] = 0;
|
||||
END CASE;
|
||||
|
||||
-- for remove sinc jitter
|
||||
-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,);
|
||||
CT[5..3].ena = DFF((CT0 & CT2),CLK42,,);
|
||||
CT[5..3] = CT[5..3]+1;
|
||||
%
|
||||
CASE CT[4..3] IS
|
||||
WHEN 0 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 1 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 2 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 3 => CT[5..3] = CT[5..3]+1;
|
||||
END CASE;
|
||||
%
|
||||
CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,);
|
||||
CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,);
|
||||
|
||||
IF CTH[] == 55 THEN
|
||||
CTH[] = GND;
|
||||
ELSE
|
||||
CTH[] = CTH[] + 1;
|
||||
END IF;
|
||||
|
||||
IF CTV[] == 319 THEN
|
||||
CTV[] = GND;
|
||||
ELSE
|
||||
CTV[] = CTV[] + 1;
|
||||
END IF;
|
||||
|
||||
CTF[].clk = CTV8;
|
||||
CTF[] = CTF[]+1;
|
||||
|
||||
-- ==== Video ==========================================================
|
||||
|
||||
ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens
|
||||
ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write
|
||||
ZXA15 = ZX_PORT7; -- ZX A15' line
|
||||
|
||||
SCR128 = DIR_PORT0;
|
||||
|
||||
-- WR_PIX = LCELL(TSN_W3);
|
||||
WR_PIX = TSN_W3;
|
||||
|
||||
DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS;
|
||||
VXA[].clk = CLK42; VXA[].ena = !E_WR;
|
||||
|
||||
VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[];
|
||||
VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[];
|
||||
VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[];
|
||||
VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[];
|
||||
|
||||
-- VXD0[] = D[];
|
||||
-- VXD1[] = D[];
|
||||
-- VXD2[] = D[];
|
||||
-- VXD3[] = D[];
|
||||
|
||||
(VXD0[],VXD1[]) = MDI[];
|
||||
(VXD2[],VXD3[]) = MDI[];
|
||||
|
||||
BRD[] = DIR_PORT[7..5];
|
||||
|
||||
VCM[].clk = CLK42;
|
||||
TSN_W3.clk = CLK42;
|
||||
V_CST[].clk = CLK42;
|
||||
V_WE.clk = CLK42;
|
||||
V_WET[].clk = CLK42;
|
||||
VLA[].clk = CLK42;
|
||||
|
||||
SCR_ENA.clk = CLK42;
|
||||
SCR_ENA.ena = !E_WR;
|
||||
SCR_ENA.d = !(VAI19 or ZX_SCREEN);
|
||||
|
||||
E_WRD = DFF(E_WR,CLK42,,);
|
||||
E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,));
|
||||
-- E_WR = LCELL(WR or !DFF(WR,CLK42,,));
|
||||
|
||||
-- ****************************************************
|
||||
|
||||
IF MODE == "SPRINTER" GENERATE
|
||||
|
||||
-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode
|
||||
|
||||
-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE);
|
||||
MXWE = DFF(MXWE,CLK42,E_WR,V_WE);
|
||||
|
||||
IF VAI[19] THEN
|
||||
-- in graf mode all 256k(512k) range
|
||||
VXA[] = VAI[];
|
||||
ELSE
|
||||
-- in spectrum mode 8k/16k range pages
|
||||
VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]);
|
||||
END IF;
|
||||
|
||||
-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,);
|
||||
-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,);
|
||||
-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,);
|
||||
|
||||
BORD = DFF((MODE0[7..4] == 15),LWR_COL,,);
|
||||
BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,);
|
||||
INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,);
|
||||
|
||||
INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,);
|
||||
|
||||
-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,);
|
||||
-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]);
|
||||
|
||||
CASE CT[2..0] IS
|
||||
WHEN B"110" => VCM[2..0].d = 5; -- 110 -> 101 6 -> 5
|
||||
WHEN B"000" => VCM[2..0].d = 1; -- 000 -> 001 0 -> 1
|
||||
WHEN B"001" => VCM[2..0].d = 4; -- 001 -> 100 1 -> 4
|
||||
WHEN B"010" => VCM[2..0].d = 3; -- 010 -> 011 2 -> 3
|
||||
WHEN B"100" => VCM[2..0].d = 2; -- 100 -> 010 4 -> 2
|
||||
WHEN B"101" => VCM[2..0].d = 0; -- 101 -> 000 5 -> 0
|
||||
END CASE;
|
||||
|
||||
CASE VCM[1..0] IS
|
||||
WHEN 0 =>
|
||||
VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
%
|
||||
IF VCM2 THEN
|
||||
-- TSN_W3.d = X_MODE5;
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE5);
|
||||
ELSE
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE_BOND);
|
||||
END IF;
|
||||
%
|
||||
|
||||
WHEN 1 =>
|
||||
WR_PIC.d = !VCM2;
|
||||
WR_COL.d = VCM2;
|
||||
VLA[].d = SVA[];
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
WHEN 2 =>
|
||||
VLA[].d = VXA[17..0];
|
||||
V_CST[].d = (!VXA18,VXA18) or MXWE;
|
||||
V_WE.d = MXWE;
|
||||
V_WEX.d = GND;
|
||||
V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
WHEN 3 =>
|
||||
-- WR_PIC.d = X_MODE5;
|
||||
-- NEW 26.08.2022, fix bug with first column
|
||||
-- it was reproducing when changes mode 320 -> 640, like any 320px screen squares -> text mode squares
|
||||
WR_PIC.d = MODE0[5];
|
||||
VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND);
|
||||
WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
END CASE;
|
||||
|
||||
-- choose V-RAM komplect
|
||||
|
||||
V_CST1.prn = GND;
|
||||
-- V_CS0.clrn = GND;
|
||||
V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0)));
|
||||
V_CS1 = VCC;
|
||||
-- V_CS0 = LCELL(V_CST0);
|
||||
|
||||
V_CSX0 = LCELL(!CLK42);
|
||||
V_CSX1 = LCELL(V_CSX0);
|
||||
V_CSX2 = LCELL(V_CSX1 & V_CSX0);
|
||||
V_CSX3 = LCELL(V_CSX2);
|
||||
|
||||
-- V_CS0 = V_CSX3;
|
||||
V_CS0 = GND;
|
||||
|
||||
-- =====================
|
||||
|
||||
SVA[].clk = CLK42;
|
||||
SVA[9..6] = MODE0[3..0];
|
||||
-- RSVA[].clk = CLK42;
|
||||
(SVA[12..10],SVA[5..0]) = RSVA[];
|
||||
|
||||
-- M_CTV[2..0].clk = CLK42;
|
||||
-- M_CT[5..3].clk = CLK42;
|
||||
M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]);
|
||||
M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]);
|
||||
|
||||
CASE (!VCM2,MODE0[4]) IS
|
||||
-- CASE (!VCM1,MODE0[4]) IS
|
||||
WHEN B"X0" =>
|
||||
-- Graf adress --
|
||||
RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = CTV[2..0];
|
||||
-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]);
|
||||
WHEN B"01" =>
|
||||
-- ZX-atr adress --
|
||||
RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
SVA[17..13] = MODE2[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE2[2..0];
|
||||
-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
WHEN B"11" =>
|
||||
-- ZX-pic adress --
|
||||
RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE1[2..0];
|
||||
-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
END CASE;
|
||||
|
||||
-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC));
|
||||
X_MODE_BOND = GND;
|
||||
|
||||
-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
|
||||
|
||||
-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS
|
||||
|
||||
-- D_PIC0_[].clk = !CLK42;
|
||||
-- D_PIC1_[].clk = !CLK42;
|
||||
-- D_PIC2_[].clk = !CLK42;
|
||||
-- D_PIC3_[].clk = !CLK42;
|
||||
|
||||
-- PIC_CLK = LCELL(LCELL(CLK42));
|
||||
PIC_CLK = !CLK42;
|
||||
|
||||
D_PIC0_[].clk = PIC_CLK;
|
||||
D_PIC1_[].clk = PIC_CLK;
|
||||
D_PIC2_[].clk = PIC_CLK;
|
||||
D_PIC3_[].clk = PIC_CLK;
|
||||
|
||||
D_PIC0_[] = VDM0[];
|
||||
D_PIC1_[] = VDM1[];
|
||||
D_PIC2_[] = VDM2[];
|
||||
D_PIC3_[] = VDM3[];
|
||||
|
||||
CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS
|
||||
WHEN 0 => D_PICX_[] = D_PIC0_[];
|
||||
WHEN 1 => D_PICX_[] = D_PIC1_[];
|
||||
WHEN 2 => D_PICX_[] = D_PIC2_[];
|
||||
WHEN 3 => D_PICX_[] = D_PIC3_[];
|
||||
END CASE;
|
||||
|
||||
MODE0[].ena = VCC;
|
||||
MODE1[].ena = VCC;
|
||||
MODE2[].ena = VCC;
|
||||
MODE0[].clk = LWR_MODE;
|
||||
MODE1[].clk = LWR_MODE;
|
||||
MODE2[].clk = LWR_MODE;
|
||||
MODE0[].d = VDM3[];
|
||||
MODE1[].d = VDM2[];
|
||||
MODE2[].d = VDM1[];
|
||||
LWR_MODE = LCELL(LCELL(WR_MODE));
|
||||
%
|
||||
MODE0[].ena = LWR_MODE;
|
||||
MODE1[].ena = LWR_MODE;
|
||||
MODE2[].ena = LWR_MODE;
|
||||
MODE0[].clk = CLK42;
|
||||
MODE1[].clk = CLK42;
|
||||
MODE2[].clk = CLK42;
|
||||
MODE0[].d = D_PIC3_[];
|
||||
MODE1[].d = D_PIC2_[];
|
||||
MODE2[].d = D_PIC1_[];
|
||||
LWR_MODE = DFF(!WR_MODE,CLK42,,);
|
||||
%
|
||||
X_MODE7 = DFF(MODE0[7],LWR_COL,,);
|
||||
X_MODE6 = DFF(MODE0[6],LWR_COL,,);
|
||||
X_MODE5 = DFF(MODE0[5],LWR_COL,,);
|
||||
X_MODE4 = DFF(MODE0[4],LWR_COL,,);
|
||||
|
||||
VAO[] = VLA[17..2];
|
||||
|
||||
WR_PIC.clk = CLK42;
|
||||
WR_COL.clk = CLK42;
|
||||
WR_MODE.clk = CLK42;
|
||||
|
||||
-- LWR_PIC = LCELL(LCELL(WR_PIC));
|
||||
-- LWR_COL = LCELL(LCELL(WR_COL));
|
||||
-- LWR_PIC = LCELL(WR_PIC);
|
||||
-- LWR_COL = LCELL(WR_COL);
|
||||
LWR_PIC = DFF(WR_PIC,CLK42,,);
|
||||
LWR_COL = DFF(WR_COL,CLK42,,);
|
||||
|
||||
-- D_PIC0[].ena = VCC;
|
||||
-- D_PIC0[].clk = (LWR_PIC);
|
||||
D_PIC0[].ena = !LWR_PIC;
|
||||
D_PIC0[].clk = CLK42;
|
||||
|
||||
|
||||
|
||||
|
||||
IF LD_PIC THEN
|
||||
-- D_PIC0[] = D_PIC0_[];
|
||||
D_PIC0[] = D_PICX_[];
|
||||
ELSE
|
||||
D_PIC0[] = (D_PIC0[6..0],GND);
|
||||
END IF;
|
||||
|
||||
|
||||
-- DCOL[].clk = (LWR_COL);
|
||||
DCOL[].ena = !LWR_COL;
|
||||
DCOL[].clk = CLK42;
|
||||
|
||||
IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN
|
||||
DCOL[].d = (B"00",BRD[2..0],BRD[2..0]);
|
||||
ELSE
|
||||
-- DCOL[].d = D_PIC0_[];
|
||||
DCOL[].d = D_PICX_[];
|
||||
END IF;
|
||||
|
||||
DCOL[].clrn = !BLANK;
|
||||
|
||||
BRVA[].clk = CLK42;
|
||||
BRVA[].clrn = !MS_POINT;
|
||||
BRVA[].prn = !MS_POINT2;
|
||||
|
||||
-- MODE0[4] - graph / text
|
||||
-- MODE0[5] - 320 / 640 resolution
|
||||
|
||||
-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS
|
||||
CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS
|
||||
WHEN B"1X" => BRVA[7..0] = DCOL[];
|
||||
WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]);
|
||||
WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]);
|
||||
END CASE;
|
||||
|
||||
-- BRVA[10..8] = (x_mode4,RBRVA[9..8]);
|
||||
RBRVA[].clk = CLK42;
|
||||
|
||||
CASE (BORD,X_MODE4) IS
|
||||
WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]);
|
||||
WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]);
|
||||
END CASE;
|
||||
|
||||
RBRVA[9..8].clrn = !BORD;
|
||||
RBRVA[10].prn = !BORD;
|
||||
|
||||
CASE (RBRVA[9..8],BRVA7) IS
|
||||
WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]);
|
||||
WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]);
|
||||
END CASE;
|
||||
|
||||
-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
|
||||
V_WE_R = DFF(GND,!CLK42,,!V_WE);
|
||||
V_WE.prn = V_WE_R;
|
||||
V_WET[].prn = V_WE_R;
|
||||
|
||||
-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
|
||||
-- V_WR[] = (V_WE) or !(
|
||||
|
||||
V_WEX.clk = CLK42;
|
||||
-- V_WEX.d = V_WE;
|
||||
-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX));
|
||||
|
||||
|
||||
|
||||
|
||||
V_WEMMM = LCELL(V_WE);
|
||||
-- V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok
|
||||
-- V_WEMMO = LCELL(V_WEMMN); -- green arts
|
||||
-- V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts
|
||||
-- V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??)
|
||||
-- V_WEMMS = LCELL(V_WEMMR);
|
||||
-- V_WEMMT = LCELL(V_WEMMS);
|
||||
-- V_WEMMU = LCELL(V_WEMMT);
|
||||
-- V_WEMMV = LCELL(V_WEMMU);
|
||||
-- V_WEMMW = LCELL(V_WEMMV);
|
||||
-- V_WEMMX = LCELL(V_WEMMW);
|
||||
-- V_WEMMY = LCELL(V_WEMMX);
|
||||
-- V_WEMMZ = LCELL(V_WEMMY);
|
||||
|
||||
V_WRM = LCELL(V_WE or V_WEMMM);
|
||||
|
||||
|
||||
-- V_WRM = LCELL(V_WEMMN or V_WEMMM);
|
||||
-- V_WRM2 = LCELL(V_WEMMN or V_WEMMM);
|
||||
-- V_WRM2 = LCELL(V_WEMMR);
|
||||
-- V_WRM = LCELL(V_WEMMM or V_WEMMN);
|
||||
-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN);
|
||||
|
||||
V_WEM = (V_WE);
|
||||
|
||||
-- V_WEM2 = LCELL(V_WE);
|
||||
-- V_WEM = LCELL(V_WEMMM & V_WEMMN);
|
||||
-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO);
|
||||
|
||||
--- LWR_COL = DFF(WR_COL,CLK42,,);
|
||||
F_WR = ((LCELL(LCELL(LCELL(DFF(VCC,V_WE,,))))));
|
||||
--- F_WR = DFF(V_WE,CLK42,,);
|
||||
-- V_WEMMZ = LCELL(CLK42);
|
||||
V_EN3 = (DFF(!(!VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,));
|
||||
V_EN2 = (DFF(!(!VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,));
|
||||
V_EN1 = (DFF(!(VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,));
|
||||
V_EN0 = (DFF(!(VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,));
|
||||
|
||||
|
||||
-- V_WR_3 = LCELL(V_WRM or V_EN3);
|
||||
-- V_WR_2 = LCELL(V_WRM or V_EN2);
|
||||
-- V_WR_1 = LCELL(V_WRM or V_EN1);
|
||||
-- V_WR_0 = LCELL(V_WRM or V_EN0);
|
||||
V_WR_3 = (LCELL(LCELL(LCELL(V_WRM or V_EN3))));
|
||||
V_WR_2 = (LCELL(LCELL(LCELL(V_WRM or V_EN2))));
|
||||
V_WR_1 = (LCELL(LCELL(LCELL(V_WRM or V_EN1))));
|
||||
V_WR_0 = (LCELL(LCELL(LCELL(V_WRM or V_EN0))));
|
||||
|
||||
V_WEY3 = LCELL(V_WE or V_EN3);
|
||||
V_WEY2 = LCELL(V_WE or V_EN2);
|
||||
V_WEY1 = LCELL(V_WE or V_EN1);
|
||||
V_WEY0 = LCELL(V_WE or V_EN0);
|
||||
|
||||
V_WR[] = V_WR_[]; -- V_WR0-3
|
||||
V_WEN[] = V_WEY[]; -- VD0-3
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
%
|
||||
V_WEMMM = LCELL(V_WE);
|
||||
V_WEMMN = LCELL(V_WEMMM);
|
||||
V_WEMMO = LCELL(V_WEMMN);
|
||||
V_WEMM = LCELL(V_WEMMO);
|
||||
|
||||
V_WRM = LCELL(V_WEMMN & V_WEMMM);
|
||||
V_WRM2 = LCELL(V_WEMMN & V_WEMMM);
|
||||
|
||||
V_WEM = LCELL(V_WEMMM & V_WEMMO);
|
||||
V_WEM2 = LCELL(V_WEMMM & V_WEMMO);
|
||||
|
||||
V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)),CLK42,F_WR,);
|
||||
V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
|
||||
F_WR = DFF(VCC,V_WE,,);
|
||||
|
||||
V_WR_3 = V_WRM or V_EN3;
|
||||
V_WR_2 = V_WRM2 or V_EN2;
|
||||
V_WR_1 = V_WRM or V_EN1;
|
||||
V_WR_0 = V_WRM or V_EN0;
|
||||
|
||||
V_WEY3 = V_WEM or V_EN3;
|
||||
V_WEY2 = V_WEM2 or V_EN2;
|
||||
V_WEY1 = V_WEM or V_EN1;
|
||||
V_WEY0 = V_WEM or V_EN0;
|
||||
|
||||
V_WR[] = V_WR_[];
|
||||
V_WEN[] = V_WEY[];
|
||||
%
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- CLK84 = LCELL(CLK42 xor CLK84_X);
|
||||
-- CLK84_X = DFF(!CLK84_X,CLK84,,);
|
||||
-- CLK84_Y = CLK84;
|
||||
|
||||
END GENERATE; -- end "sprinter" mode
|
||||
|
||||
|
||||
END;
|
||||
@ -1,708 +0,0 @@
|
||||
|
||||
TITLE "Video-controller";
|
||||
|
||||
INCLUDE "lpm_ram_dp";
|
||||
|
||||
PARAMETERS
|
||||
(
|
||||
MODE = "SPRINTER",
|
||||
MOUSE = "NO",
|
||||
HOR_PLACE = H"50",
|
||||
VER_PLACE = H"91" -- 122h/2
|
||||
);
|
||||
|
||||
SUBDESIGN video2
|
||||
(
|
||||
CLK42 : INPUT;
|
||||
|
||||
CT[5..0] : OUTPUT;
|
||||
CTH[5..0] : OUTPUT;
|
||||
CTV[8..0] : OUTPUT;
|
||||
CTF[6..0] : OUTPUT;
|
||||
|
||||
BLANK : OUTPUT;
|
||||
|
||||
START_UP : INPUT;
|
||||
COPY_SINC_H : INPUT;
|
||||
COPY_SINC_V : INPUT;
|
||||
|
||||
WR : INPUT;
|
||||
|
||||
VAI[19..0] : INPUT; -- input screen adress
|
||||
|
||||
VAO[15..0] : OUTPUT;
|
||||
|
||||
D[7..0] : INPUT;
|
||||
MDI[15..0] : INPUT;
|
||||
|
||||
VDO0[7..0] : OUTPUT;
|
||||
VDO1[7..0] : OUTPUT;
|
||||
VDO2[7..0] : OUTPUT;
|
||||
VDO3[7..0] : OUTPUT;
|
||||
|
||||
VDM0[7..0] : INPUT;
|
||||
VDM1[7..0] : INPUT;
|
||||
VDM2[7..0] : INPUT;
|
||||
VDM3[7..0] : INPUT;
|
||||
|
||||
V_WR[3..0] : OUTPUT;
|
||||
V_WEN[3..0] : OUTPUT;
|
||||
|
||||
V_CS[1..0] : OUTPUT;
|
||||
WR_PIX : OUTPUT;
|
||||
|
||||
-- ZX_COLOR[3..0] : OUTPUT;
|
||||
|
||||
ZX_PORT[7..0] : INPUT;
|
||||
DIR_PORT[7..0] : INPUT;
|
||||
|
||||
%
|
||||
bit0 - Spectrum SCREEN Switch
|
||||
bit1 - Spectrum Adress MODE
|
||||
bit2 - Write to Spectrum Screen OFF
|
||||
bit3 - MODE page 0/1
|
||||
bit4 - MODE on/off screen
|
||||
|
||||
bit7..5 - Border
|
||||
%
|
||||
|
||||
INTT : OUTPUT;
|
||||
|
||||
DOUBLE_CAS : INPUT;
|
||||
|
||||
MOUSE_X[9..0] : INPUT;
|
||||
MOUSE_Y[9..0] : INPUT;
|
||||
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
CLK84 : NODE;
|
||||
CLK84_X : NODE;
|
||||
CLK84_Y : NODE;
|
||||
|
||||
ZX_COLOR[3..0] : NODE;
|
||||
|
||||
CT[5..0] : DFFE;
|
||||
CTH[5..0] : DFFE;
|
||||
CTV[8..0] : DFFE;
|
||||
CTF[6..0] : DFF;
|
||||
|
||||
VXA[19..0] : DFFE;
|
||||
|
||||
VXD0[7..0] : DFFE;
|
||||
VXD1[7..0] : DFFE;
|
||||
VXD2[7..0] : DFFE;
|
||||
VXD3[7..0] : DFFE;
|
||||
|
||||
E_WR : NODE;
|
||||
E_WRD : NODE;
|
||||
|
||||
BLANK : NODE;
|
||||
BORD : NODE;
|
||||
-- INTT_T : NODE;
|
||||
INTTX : NODE;
|
||||
|
||||
VLA[17..0] : DFF;
|
||||
-- SVA[17..0] : NODE;
|
||||
SVA[17..0] : DFF;
|
||||
-- RSVA[8..0] : LCELL;
|
||||
RSVA[8..0] : NODE;
|
||||
-- RSVA[8..0] : DFF;
|
||||
|
||||
V_CST[1..0] : DFF;
|
||||
VCM[2..0] : DFF;
|
||||
TSN_W3 : DFF;
|
||||
V_WE : DFF;
|
||||
V_WEX : DFF;
|
||||
|
||||
V_WEM : NODE;
|
||||
V_WEM1 : NODE;
|
||||
V_WEM2 : NODE;
|
||||
V_WEM3 : NODE;
|
||||
V_WRM : NODE;
|
||||
V_WRM1 : NODE;
|
||||
V_WRM2 : NODE;
|
||||
V_WRM3 : NODE;
|
||||
|
||||
V_WEMM : NODE;
|
||||
V_WEMMM : NODE;
|
||||
V_WEMMN : NODE;
|
||||
V_WEMMO : NODE;
|
||||
V_WEMMP : NODE;
|
||||
V_WEMMQ : NODE;
|
||||
V_WEMMR : NODE;
|
||||
V_WEMMS : NODE;
|
||||
V_WEMMT : NODE;
|
||||
V_WEMMU : NODE;
|
||||
V_WEMMV : NODE;
|
||||
V_WEMMW : NODE;
|
||||
V_WEMMX : NODE;
|
||||
V_WEMMY : NODE;
|
||||
V_WEMMZ : NODE;
|
||||
|
||||
V_WET[3..0] : DFF;
|
||||
|
||||
D_PIC0[7..0] : DFFE;
|
||||
-- D_PIC0_[7..0] : LCELL;
|
||||
|
||||
D_PIC0_[7..0] : DFFE;
|
||||
D_PIC1_[7..0] : DFFE;
|
||||
D_PIC2_[7..0] : DFFE;
|
||||
D_PIC3_[7..0] : DFFE;
|
||||
|
||||
D_PICX_[7..0] : NODE;
|
||||
|
||||
LWR_PIC : NODE;
|
||||
LWR_COL : NODE;
|
||||
|
||||
WR_PIC : DFF;
|
||||
WR_COL : DFF;
|
||||
LD_PIC : NODE;
|
||||
|
||||
RBRVA[10..8]: DFF;
|
||||
BRVA[7..0] : DFF;
|
||||
DCOL[7..0] : DFFE;
|
||||
|
||||
MXWE : NODE;
|
||||
-- MXCE : NODE;
|
||||
|
||||
AX128 : NODE;
|
||||
|
||||
BRD[2..0] : NODE;
|
||||
|
||||
ZX_COL[3..0] : LCELL;
|
||||
|
||||
ZXA15 : NODE;
|
||||
ZXS[5..0] : NODE;
|
||||
ZX_SCREEN : NODE;
|
||||
SCR128 : NODE;
|
||||
|
||||
MODE0[7..0] : DFFE;
|
||||
MODE1[7..0] : DFFE;
|
||||
MODE2[7..0] : DFFE;
|
||||
-- MODE3[7..0] : DFF;
|
||||
|
||||
WR_MODE : DFF;
|
||||
LWR_MODE : NODE;
|
||||
X_MODE[7..4]: NODE;
|
||||
X_MODE_BOND : NODE;
|
||||
|
||||
-- M_CTV[2..0] : DFF;
|
||||
-- M_CT[5..3] : DFF;
|
||||
M_CTV[2..0] : LCELL;
|
||||
M_CT[5..3] : LCELL;
|
||||
|
||||
DOUBLE : DFFE;
|
||||
|
||||
PIC_CLK : NODE;
|
||||
|
||||
MS_X[9..0] : DFF;
|
||||
MS_Y[9..0] : DFF;
|
||||
|
||||
MS_POINT : NODE;
|
||||
MS_POINT2 : NODE;
|
||||
MS_PNT : NODE;
|
||||
|
||||
MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF");
|
||||
|
||||
SCR_ENA : DFFE;
|
||||
V_WR_[3..0] : LCELL;
|
||||
V_WEY[3..0] : LCELL;
|
||||
|
||||
V_WE_R : NODE;
|
||||
|
||||
V_CSX[3..0] : NODE;
|
||||
|
||||
V_EN[3..0] : NODE;
|
||||
|
||||
F_WR : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
DEFAULTS
|
||||
WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC;
|
||||
V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC;
|
||||
V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC;
|
||||
V_WET[].d = VCC;
|
||||
END DEFAULTS;
|
||||
|
||||
ZX_COLOR[] = ZX_COL[];
|
||||
|
||||
-- === MOUSE counters ========
|
||||
|
||||
MS_X[].clk = !CT1;
|
||||
CASE LCELL(CTH[5..2] == 12) IS
|
||||
WHEN 0 => MS_X[] = MS_X[] + 1;
|
||||
WHEN 1 => MS_X[] = (!MOUSE_X[9..0]);
|
||||
END CASE;
|
||||
|
||||
MS_Y[].clk = !CTH5;
|
||||
CASE LCELL(CTV8 & !CTV5 & CTV4) IS
|
||||
WHEN 0 => MS_Y[] = MS_Y[] + 1;
|
||||
WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]);
|
||||
END CASE;
|
||||
|
||||
MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,);
|
||||
|
||||
MS_DAT.wren = GND;
|
||||
MS_DAT.data[] = GND;
|
||||
MS_DAT.wraddress[] = GND;
|
||||
MS_DAT.wrclock = CLK42;
|
||||
MS_DAT.wrclken = GND;
|
||||
MS_DAT.rden = VCC;
|
||||
MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]);
|
||||
MS_DAT.rdclock = CLK42;
|
||||
MS_DAT.rdclken = VCC;
|
||||
|
||||
IF MOUSE == "NO" GENERATE
|
||||
MS_POINT = GND;
|
||||
MS_POINT2 = GND;
|
||||
ELSE GENERATE
|
||||
MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,);
|
||||
MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,);
|
||||
END GENERATE;
|
||||
|
||||
-- === Sinc-counts GENERATOR ============================================
|
||||
|
||||
-- CT[].clrn = START_UP;
|
||||
|
||||
-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE;
|
||||
-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE;
|
||||
|
||||
-- CTV[].clrn = !COPY_SINC_V or VER_PLACE;
|
||||
-- CTV[].prn = !COPY_SINC_V or !VER_PLACE;
|
||||
|
||||
CT[5].clrn = !COPY_SINC_H;
|
||||
|
||||
-- set CTH to 50 (32h)
|
||||
CTH[0].clrn = !COPY_SINC_H;
|
||||
CTH[1].prn = !COPY_SINC_H;
|
||||
CTH[2].clrn = !COPY_SINC_H;
|
||||
CTH[3].clrn = !COPY_SINC_H;
|
||||
CTH[4].prn = !COPY_SINC_H;
|
||||
CTH[5].prn = !COPY_SINC_H;
|
||||
|
||||
-- set CTV to 122h
|
||||
CTV[0].clrn = !COPY_SINC_V;
|
||||
CTV[1].prn = !COPY_SINC_V;
|
||||
CTV[3..2].clrn = !COPY_SINC_V;
|
||||
|
||||
CTV[4].clrn = !COPY_SINC_V;
|
||||
CTV[5].prn = !COPY_SINC_V;
|
||||
CTV[7..6].clrn = !COPY_SINC_V;
|
||||
CTV[8].prn = !COPY_SINC_V;
|
||||
|
||||
CT[5..0].clk = CLK42;
|
||||
CTH[5..0].clk = CLK42;
|
||||
CTV[8..0].clk = CLK42;
|
||||
|
||||
CT[2..0].ena = VCC;
|
||||
CASE CT[2..0] IS
|
||||
WHEN 0 => CT[2..0] = 1;
|
||||
WHEN 1 => CT[2..0] = 2;
|
||||
WHEN 2 => CT[2..0] = 4;
|
||||
WHEN 3 => CT[2..0] = 4;
|
||||
WHEN 4 => CT[2..0] = 5;
|
||||
WHEN 5 => CT[2..0] = 6;
|
||||
WHEN 6 => CT[2..0] = 0;
|
||||
WHEN 7 => CT[2..0] = 0;
|
||||
END CASE;
|
||||
-- for remove sinc jitter
|
||||
-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,);
|
||||
CT[5..3].ena = DFF((CT0 & CT2),CLK42,,);
|
||||
CT[5..3] = CT[5..3]+1;
|
||||
%
|
||||
CASE CT[4..3] IS
|
||||
WHEN 0 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 1 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 2 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 3 => CT[5..3] = CT[5..3]+1;
|
||||
END CASE;
|
||||
%
|
||||
CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,);
|
||||
CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,);
|
||||
|
||||
IF CTH[] == 55 THEN
|
||||
CTH[] = GND;
|
||||
ELSE
|
||||
CTH[] = CTH[] + 1;
|
||||
END IF;
|
||||
|
||||
IF CTV[] == 319 THEN
|
||||
CTV[] = GND;
|
||||
ELSE
|
||||
CTV[] = CTV[] + 1;
|
||||
END IF;
|
||||
|
||||
CTF[].clk = CTV8;
|
||||
CTF[] = CTF[]+1;
|
||||
|
||||
-- ==== Video ==========================================================
|
||||
|
||||
ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens
|
||||
ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write
|
||||
ZXA15 = ZX_PORT7; -- ZX A15' line
|
||||
|
||||
SCR128 = DIR_PORT0;
|
||||
|
||||
-- WR_PIX = LCELL(TSN_W3);
|
||||
WR_PIX = (TSN_W3);
|
||||
|
||||
DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS;
|
||||
VXA[].clk = CLK42; VXA[].ena = !E_WR;
|
||||
|
||||
VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[];
|
||||
VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[];
|
||||
VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[];
|
||||
VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[];
|
||||
|
||||
-- VXD0[] = D[];
|
||||
-- VXD1[] = D[];
|
||||
-- VXD2[] = D[];
|
||||
-- VXD3[] = D[];
|
||||
|
||||
(VXD0[],VXD1[]) = MDI[];
|
||||
(VXD2[],VXD3[]) = MDI[];
|
||||
|
||||
BRD[] = DIR_PORT[7..5];
|
||||
|
||||
VCM[].clk = CLK42;
|
||||
TSN_W3.clk = CLK42;
|
||||
V_CST[].clk = CLK42;
|
||||
V_WE.clk = CLK42;
|
||||
V_WET[].clk = CLK42;
|
||||
VLA[].clk = CLK42;
|
||||
|
||||
SCR_ENA.clk = CLK42;
|
||||
SCR_ENA.ena = !E_WR;
|
||||
SCR_ENA.d = !(VAI19 or ZX_SCREEN);
|
||||
|
||||
E_WRD = DFF(E_WR,CLK42,,);
|
||||
E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,));
|
||||
-- E_WR = LCELL(WR or !DFF(WR,CLK42,,));
|
||||
|
||||
-- ****************************************************
|
||||
|
||||
IF MODE == "SPRINTER" GENERATE
|
||||
|
||||
-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode
|
||||
|
||||
-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE);
|
||||
MXWE = DFF(MXWE,CLK42,E_WR,V_WE);
|
||||
|
||||
IF VAI[19] THEN
|
||||
-- in graf mode all 256k(512k) range
|
||||
VXA[] = VAI[];
|
||||
ELSE
|
||||
-- in spectrum mode 8k/16k range pages
|
||||
VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]);
|
||||
END IF;
|
||||
|
||||
-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,);
|
||||
-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,);
|
||||
-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,);
|
||||
|
||||
BORD = DFF((MODE0[7..4] == 15),LWR_COL,,);
|
||||
BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,);
|
||||
INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,);
|
||||
|
||||
INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,);
|
||||
|
||||
-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,);
|
||||
-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]);
|
||||
|
||||
CASE CT[2..0] IS
|
||||
WHEN B"110" => VCM[2..0].d = 5; -- 101
|
||||
WHEN B"000" => VCM[2..0].d = 1; -- 001
|
||||
WHEN B"001" => VCM[2..0].d = 4; -- 100
|
||||
WHEN B"010" => VCM[2..0].d = 3; -- 011
|
||||
WHEN B"100" => VCM[2..0].d = 2; -- 010
|
||||
WHEN B"101" => VCM[2..0].d = 0; -- 000
|
||||
END CASE;
|
||||
|
||||
CASE VCM[1..0] IS
|
||||
WHEN 0 =>
|
||||
VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
IF VCM2 THEN
|
||||
-- TSN_W3.d = X_MODE5;
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE5);
|
||||
ELSE
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE_BOND);
|
||||
END IF;
|
||||
WHEN 1 =>
|
||||
WR_PIC.d = !VCM2;
|
||||
WR_COL.d = VCM2;
|
||||
VLA[].d = SVA[];
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
WHEN 2 =>
|
||||
VLA[].d = VXA[17..0];
|
||||
V_CST[].d = (!VXA18,VXA18) or MXWE;
|
||||
V_WE.d = MXWE;
|
||||
V_WEX.d = GND;
|
||||
V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
WHEN 3 =>
|
||||
WR_PIC.d = X_MODE5;
|
||||
VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND);
|
||||
WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
END CASE;
|
||||
|
||||
-- choose V-RAM komplect
|
||||
|
||||
V_CST1.prn = GND;
|
||||
-- V_CS0.clrn = GND;
|
||||
V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0)));
|
||||
V_CS1 = VCC;
|
||||
-- V_CS0 = LCELL(V_CST0);
|
||||
|
||||
V_CSX0 = LCELL(!CLK42);
|
||||
V_CSX1 = LCELL(V_CSX0);
|
||||
V_CSX2 = LCELL(V_CSX1 & V_CSX0);
|
||||
V_CSX3 = LCELL(V_CSX2);
|
||||
|
||||
-- V_CS0 = V_CSX3;
|
||||
V_CS0 = GND;
|
||||
|
||||
-- =====================
|
||||
|
||||
SVA[].clk = CLK42;
|
||||
SVA[9..6] = MODE0[3..0];
|
||||
-- RSVA[].clk = CLK42;
|
||||
(SVA[12..10],SVA[5..0]) = RSVA[];
|
||||
|
||||
-- M_CTV[2..0].clk = CLK42;
|
||||
-- M_CT[5..3].clk = CLK42;
|
||||
M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]);
|
||||
M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]);
|
||||
|
||||
CASE (!VCM2,MODE0[4]) IS
|
||||
-- CASE (!VCM1,MODE0[4]) IS
|
||||
WHEN B"X0" =>
|
||||
-- Graf adress --
|
||||
RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = CTV[2..0];
|
||||
-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]);
|
||||
WHEN B"01" =>
|
||||
-- ZX-atr adress --
|
||||
RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
SVA[17..13] = MODE2[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE2[2..0];
|
||||
-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
WHEN B"11" =>
|
||||
-- ZX-pic adress --
|
||||
RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE1[2..0];
|
||||
-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
END CASE;
|
||||
|
||||
-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC));
|
||||
X_MODE_BOND = GND;
|
||||
|
||||
-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
|
||||
-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS
|
||||
|
||||
-- D_PIC0_[].clk = !CLK42;
|
||||
-- D_PIC1_[].clk = !CLK42;
|
||||
-- D_PIC2_[].clk = !CLK42;
|
||||
-- D_PIC3_[].clk = !CLK42;
|
||||
|
||||
-- PIC_CLK = LCELL(LCELL(CLK42));
|
||||
PIC_CLK = !CLK42;
|
||||
|
||||
D_PIC0_[].clk = PIC_CLK;
|
||||
D_PIC1_[].clk = PIC_CLK;
|
||||
D_PIC2_[].clk = PIC_CLK;
|
||||
D_PIC3_[].clk = PIC_CLK;
|
||||
|
||||
D_PIC0_[] = VDM0[];
|
||||
D_PIC1_[] = VDM1[];
|
||||
D_PIC2_[] = VDM2[];
|
||||
D_PIC3_[] = VDM3[];
|
||||
|
||||
CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS
|
||||
WHEN 0 => D_PICX_[] = D_PIC0_[];
|
||||
WHEN 1 => D_PICX_[] = D_PIC1_[];
|
||||
WHEN 2 => D_PICX_[] = D_PIC2_[];
|
||||
WHEN 3 => D_PICX_[] = D_PIC3_[];
|
||||
END CASE;
|
||||
|
||||
MODE0[].ena = VCC;
|
||||
MODE1[].ena = VCC;
|
||||
MODE2[].ena = VCC;
|
||||
MODE0[].clk = LWR_MODE;
|
||||
MODE1[].clk = LWR_MODE;
|
||||
MODE2[].clk = LWR_MODE;
|
||||
MODE0[].d = VDM3[];
|
||||
MODE1[].d = VDM2[];
|
||||
MODE2[].d = VDM1[];
|
||||
LWR_MODE = LCELL(LCELL(WR_MODE));
|
||||
%
|
||||
MODE0[].ena = LWR_MODE;
|
||||
MODE1[].ena = LWR_MODE;
|
||||
MODE2[].ena = LWR_MODE;
|
||||
MODE0[].clk = CLK42;
|
||||
MODE1[].clk = CLK42;
|
||||
MODE2[].clk = CLK42;
|
||||
MODE0[].d = D_PIC3_[];
|
||||
MODE1[].d = D_PIC2_[];
|
||||
MODE2[].d = D_PIC1_[];
|
||||
LWR_MODE = DFF(!WR_MODE,CLK42,,);
|
||||
%
|
||||
X_MODE7 = DFF(MODE0[7],LWR_COL,,);
|
||||
X_MODE6 = DFF(MODE0[6],LWR_COL,,);
|
||||
X_MODE5 = DFF(MODE0[5],LWR_COL,,);
|
||||
X_MODE4 = DFF(MODE0[4],LWR_COL,,);
|
||||
|
||||
VAO[] = VLA[17..2];
|
||||
|
||||
WR_PIC.clk = CLK42;
|
||||
WR_COL.clk = CLK42;
|
||||
WR_MODE.clk = CLK42;
|
||||
|
||||
-- LWR_PIC = LCELL(LCELL(WR_PIC));
|
||||
-- LWR_COL = LCELL(LCELL(WR_COL));
|
||||
-- LWR_PIC = LCELL(WR_PIC);
|
||||
-- LWR_COL = LCELL(WR_COL);
|
||||
LWR_PIC = DFF(WR_PIC,CLK42,,);
|
||||
LWR_COL = DFF(WR_COL,CLK42,,);
|
||||
|
||||
-- D_PIC0[].ena = VCC;
|
||||
-- D_PIC0[].clk = (LWR_PIC);
|
||||
D_PIC0[].ena = !LWR_PIC;
|
||||
D_PIC0[].clk = CLK42;
|
||||
|
||||
IF LD_PIC THEN
|
||||
-- D_PIC0[] = D_PIC0_[];
|
||||
D_PIC0[] = D_PICX_[];
|
||||
ELSE
|
||||
D_PIC0[] = (D_PIC0[6..0],GND);
|
||||
END IF;
|
||||
|
||||
-- DCOL[].clk = (LWR_COL);
|
||||
DCOL[].ena = !LWR_COL;
|
||||
DCOL[].clk = CLK42;
|
||||
|
||||
IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN
|
||||
DCOL[].d = (B"00",BRD[2..0],BRD[2..0]);
|
||||
ELSE
|
||||
-- DCOL[].d = D_PIC0_[];
|
||||
DCOL[].d = D_PICX_[];
|
||||
END IF;
|
||||
|
||||
DCOL[].clrn = !BLANK;
|
||||
|
||||
BRVA[].clk = CLK42;
|
||||
BRVA[].clrn = !MS_POINT;
|
||||
BRVA[].prn = !MS_POINT2;
|
||||
|
||||
-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS
|
||||
CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS
|
||||
WHEN B"1X" => BRVA[7..0] = DCOL[];
|
||||
WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]);
|
||||
WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]);
|
||||
END CASE;
|
||||
|
||||
-- BRVA[10..8] = (x_mode4,RBRVA[9..8]);
|
||||
RBRVA[].clk = CLK42;
|
||||
|
||||
CASE (BORD,X_MODE4) IS
|
||||
WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]);
|
||||
WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]);
|
||||
END CASE;
|
||||
|
||||
RBRVA[9..8].clrn = !BORD;
|
||||
RBRVA[10].prn = !BORD;
|
||||
|
||||
CASE (RBRVA[9..8],BRVA7) IS
|
||||
WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]);
|
||||
WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]);
|
||||
END CASE;
|
||||
|
||||
-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
|
||||
V_WE_R = DFF(GND,!CLK42,,!V_WE);
|
||||
V_WE.prn = V_WE_R;
|
||||
V_WET[].prn = V_WE_R;
|
||||
|
||||
-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
|
||||
-- V_WR[] = (V_WE) or !(
|
||||
|
||||
V_WEX.clk = CLK42;
|
||||
-- V_WEX.d = V_WE;
|
||||
-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX));
|
||||
|
||||
|
||||
-- V_WE_R1 = LCELL(V_WE);
|
||||
-- V_WEMMM = LCELL(V_WE_R1);
|
||||
|
||||
V_WEMMM = LCELL(V_WE);
|
||||
V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok
|
||||
V_WEMMO = LCELL(V_WEMMN); -- green arts
|
||||
V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts
|
||||
V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??)
|
||||
V_WEMMS = LCELL(V_WEMMR);
|
||||
-- V_WEMMT = LCELL(V_WEMMS);
|
||||
-- V_WEMMU = LCELL(V_WEMMT);
|
||||
-- V_WEMMV = LCELL(V_WEMMU);
|
||||
-- V_WEMMW = LCELL(V_WEMMV);
|
||||
-- V_WEMMX = LCELL(V_WEMMW);
|
||||
-- V_WEMMY = LCELL(V_WEMMX);
|
||||
-- V_WEMMZ = LCELL(V_WEMMY);
|
||||
|
||||
V_WRM = LCELL(V_WEMMN or V_WEMMM);
|
||||
-- V_WRM2 = LCELL(V_WEMMR);
|
||||
-- V_WRM = LCELL(V_WEMMM or V_WEMMN);
|
||||
-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN);
|
||||
|
||||
V_WEM = LCELL(V_WE);
|
||||
-- V_WEM2 = LCELL(V_WE);
|
||||
-- V_WEM = LCELL(V_WEMMM & V_WEMMN);
|
||||
-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO);
|
||||
|
||||
F_WR = DFF(VCC,V_WE,,);
|
||||
V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,);
|
||||
V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,);
|
||||
V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,);
|
||||
V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,);
|
||||
|
||||
|
||||
V_WR_3 = (V_WRM or V_EN3);
|
||||
V_WR_2 = (V_WRM or V_EN2);
|
||||
V_WR_1 = (V_WRM or V_EN1);
|
||||
V_WR_0 = (V_WRM or V_EN0);
|
||||
|
||||
V_WEY3 = V_WEM or V_EN3;
|
||||
V_WEY2 = V_WEM or V_EN2;
|
||||
V_WEY1 = V_WEM or V_EN1;
|
||||
V_WEY0 = V_WEM or V_EN0;
|
||||
|
||||
V_WR[] = V_WR_[];
|
||||
V_WEN[] = V_WEY[];
|
||||
|
||||
-- CLK84 = LCELL(CLK42 xor CLK84_X);
|
||||
-- CLK84_X = DFF(!CLK84_X,CLK84,,);
|
||||
-- CLK84_Y = CLK84;
|
||||
|
||||
END GENERATE; -- end "sprinter" mode
|
||||
|
||||
|
||||
END;
|
||||
@ -1,773 +0,0 @@
|
||||
|
||||
TITLE "Video-controller";
|
||||
|
||||
INCLUDE "lpm_ram_dp";
|
||||
|
||||
PARAMETERS
|
||||
(
|
||||
MODE = "SPRINTER",
|
||||
MOUSE = "NO",
|
||||
HOR_PLACE = H"50",
|
||||
VER_PLACE = H"91" -- 122h/2
|
||||
);
|
||||
|
||||
SUBDESIGN video2
|
||||
(
|
||||
CLK42 : INPUT;
|
||||
|
||||
CT[5..0] : OUTPUT;
|
||||
CTH[5..0] : OUTPUT;
|
||||
CTV[8..0] : OUTPUT;
|
||||
CTF[6..0] : OUTPUT;
|
||||
|
||||
BLANK : OUTPUT;
|
||||
|
||||
START_UP : INPUT;
|
||||
COPY_SINC_H : INPUT;
|
||||
COPY_SINC_V : INPUT;
|
||||
|
||||
WR : INPUT;
|
||||
|
||||
VAI[19..0] : INPUT; -- input screen adress
|
||||
|
||||
VAO[15..0] : OUTPUT;
|
||||
|
||||
D[7..0] : INPUT;
|
||||
MDI[15..0] : INPUT;
|
||||
|
||||
VDO0[7..0] : OUTPUT;
|
||||
VDO1[7..0] : OUTPUT;
|
||||
VDO2[7..0] : OUTPUT;
|
||||
VDO3[7..0] : OUTPUT;
|
||||
|
||||
VDM0[7..0] : INPUT;
|
||||
VDM1[7..0] : INPUT;
|
||||
VDM2[7..0] : INPUT;
|
||||
VDM3[7..0] : INPUT;
|
||||
|
||||
V_WR[3..0] : OUTPUT;
|
||||
V_WEN[3..0] : OUTPUT;
|
||||
|
||||
V_CS[1..0] : OUTPUT;
|
||||
WR_PIX : OUTPUT;
|
||||
|
||||
-- ZX_COLOR[3..0] : OUTPUT;
|
||||
|
||||
ZX_PORT[7..0] : INPUT;
|
||||
DIR_PORT[7..0] : INPUT;
|
||||
|
||||
%
|
||||
bit0 - Spectrum SCREEN Switch
|
||||
bit1 - Spectrum Adress MODE
|
||||
bit2 - Write to Spectrum Screen OFF
|
||||
bit3 - MODE page 0/1
|
||||
bit4 - MODE on/off screen
|
||||
|
||||
bit7..5 - Border
|
||||
%
|
||||
|
||||
INTT : OUTPUT;
|
||||
|
||||
DOUBLE_CAS : INPUT;
|
||||
|
||||
MOUSE_X[9..0] : INPUT;
|
||||
MOUSE_Y[9..0] : INPUT;
|
||||
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
-- CLK84 : NODE;
|
||||
-- CLK84_X : NODE;
|
||||
-- CLK84_Y : NODE;
|
||||
|
||||
ZX_COLOR[3..0] : NODE;
|
||||
|
||||
CT[5..0] : DFFE;
|
||||
CTH[5..0] : DFFE;
|
||||
CTV[8..0] : DFFE;
|
||||
CTF[6..0] : DFF;
|
||||
|
||||
VXA[19..0] : DFFE;
|
||||
|
||||
VXD0[7..0] : DFFE;
|
||||
VXD1[7..0] : DFFE;
|
||||
VXD2[7..0] : DFFE;
|
||||
VXD3[7..0] : DFFE;
|
||||
|
||||
E_WR : NODE;
|
||||
E_WRD : NODE;
|
||||
|
||||
BLANK : NODE;
|
||||
BORD : NODE;
|
||||
-- INTT_T : NODE;
|
||||
INTTX : NODE;
|
||||
|
||||
VLA[17..0] : DFF;
|
||||
-- SVA[17..0] : NODE;
|
||||
SVA[17..0] : DFF;
|
||||
-- RSVA[8..0] : LCELL;
|
||||
RSVA[8..0] : NODE;
|
||||
-- RSVA[8..0] : DFF;
|
||||
|
||||
V_CST[1..0] : DFF;
|
||||
VCM[2..0] : DFF;
|
||||
TSN_W3 : DFF;
|
||||
V_WE : DFF;
|
||||
V_WEX : DFF;
|
||||
|
||||
V_WEM : NODE;
|
||||
V_WEM2 : NODE;
|
||||
V_WRM : NODE;
|
||||
V_WRM2 : NODE;
|
||||
%
|
||||
V_WEMM : NODE;
|
||||
V_WEMMM : NODE;
|
||||
V_WEMMN : NODE;
|
||||
V_WEMMO : NODE;
|
||||
%
|
||||
V_WEMM : NODE;
|
||||
V_WEMMM : NODE;
|
||||
V_WEMMN : NODE;
|
||||
V_WEMMO : NODE;
|
||||
V_WEMMP : NODE;
|
||||
V_WEMMQ : NODE;
|
||||
V_WEMMR : NODE;
|
||||
V_WEMMS : NODE;
|
||||
V_WEMMT : NODE;
|
||||
V_WEMMU : NODE;
|
||||
V_WEMMV : NODE;
|
||||
V_WEMMW : NODE;
|
||||
V_WEMMX : NODE;
|
||||
V_WEMMY : NODE;
|
||||
V_WEMMZ : NODE;
|
||||
|
||||
|
||||
|
||||
V_WET[3..0] : DFF;
|
||||
|
||||
D_PIC0[7..0] : DFFE;
|
||||
-- D_PIC0_[7..0] : LCELL;
|
||||
|
||||
D_PIC0_[7..0] : DFFE;
|
||||
D_PIC1_[7..0] : DFFE;
|
||||
D_PIC2_[7..0] : DFFE;
|
||||
D_PIC3_[7..0] : DFFE;
|
||||
|
||||
D_PICX_[7..0] : NODE;
|
||||
|
||||
LWR_PIC : NODE;
|
||||
LWR_COL : NODE;
|
||||
|
||||
WR_PIC : DFF;
|
||||
WR_COL : DFF;
|
||||
LD_PIC : NODE;
|
||||
MXL: NODE;
|
||||
MXR: NODE;
|
||||
|
||||
RBRVA[10..8]: DFF;
|
||||
BRVA[7..0] : DFF;
|
||||
DCOL[7..0] : DFFE;
|
||||
|
||||
MXWE : NODE;
|
||||
-- MXCE : NODE;
|
||||
|
||||
AX128 : NODE;
|
||||
|
||||
BRD[2..0] : NODE;
|
||||
|
||||
ZX_COL[3..0] : LCELL;
|
||||
|
||||
ZXA15 : NODE;
|
||||
ZXS[5..0] : NODE;
|
||||
ZX_SCREEN : NODE;
|
||||
SCR128 : NODE;
|
||||
|
||||
MODE0[7..0] : DFFE;
|
||||
MODE1[7..0] : DFFE;
|
||||
MODE2[7..0] : DFFE;
|
||||
-- MODE3[7..0] : DFF;
|
||||
|
||||
WR_MODE : DFF;
|
||||
LWR_MODE : NODE;
|
||||
X_MODE[7..4]: NODE;
|
||||
X_MODE_BOND : NODE;
|
||||
|
||||
-- M_CTV[2..0] : DFF;
|
||||
-- M_CT[5..3] : DFF;
|
||||
M_CTV[2..0] : LCELL;
|
||||
M_CT[5..3] : LCELL;
|
||||
|
||||
DOUBLE : DFFE;
|
||||
|
||||
PIC_CLK : NODE;
|
||||
|
||||
MS_X[9..0] : DFF;
|
||||
MS_Y[9..0] : DFF;
|
||||
|
||||
MS_POINT : NODE;
|
||||
MS_POINT2 : NODE;
|
||||
MS_PNT : NODE;
|
||||
|
||||
MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF");
|
||||
|
||||
SCR_ENA : DFFE;
|
||||
V_WR_[3..0] : LCELL;
|
||||
V_WEY[3..0] : LCELL;
|
||||
|
||||
V_WE_R : NODE;
|
||||
|
||||
V_CSX[3..0] : NODE;
|
||||
|
||||
V_EN[3..0] : NODE;
|
||||
|
||||
F_WR : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
DEFAULTS
|
||||
WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC;
|
||||
V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC;
|
||||
V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC;
|
||||
V_WET[].d = VCC;
|
||||
END DEFAULTS;
|
||||
|
||||
ZX_COLOR[] = ZX_COL[];
|
||||
|
||||
-- === MOUSE counters ========
|
||||
|
||||
MS_X[].clk = !CT1;
|
||||
CASE LCELL(CTH[5..2] == 12) IS
|
||||
WHEN 0 => MS_X[] = MS_X[] + 1;
|
||||
WHEN 1 => MS_X[] = (!MOUSE_X[9..0]);
|
||||
END CASE;
|
||||
|
||||
MS_Y[].clk = !CTH5;
|
||||
CASE LCELL(CTV8 & !CTV5 & CTV4) IS
|
||||
WHEN 0 => MS_Y[] = MS_Y[] + 1;
|
||||
WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]);
|
||||
END CASE;
|
||||
|
||||
MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,);
|
||||
|
||||
MS_DAT.wren = GND;
|
||||
MS_DAT.data[] = GND;
|
||||
MS_DAT.wraddress[] = GND;
|
||||
MS_DAT.wrclock = CLK42;
|
||||
MS_DAT.wrclken = GND;
|
||||
MS_DAT.rden = VCC;
|
||||
MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]);
|
||||
MS_DAT.rdclock = CLK42;
|
||||
MS_DAT.rdclken = VCC;
|
||||
|
||||
IF MOUSE == "NO" GENERATE
|
||||
MS_POINT = GND;
|
||||
MS_POINT2 = GND;
|
||||
ELSE GENERATE
|
||||
MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,);
|
||||
MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,);
|
||||
END GENERATE;
|
||||
|
||||
-- === Sinc-counts GENERATOR ============================================
|
||||
|
||||
-- CT[].clrn = START_UP;
|
||||
|
||||
-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE;
|
||||
-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE;
|
||||
|
||||
-- CTV[].clrn = !COPY_SINC_V or VER_PLACE;
|
||||
-- CTV[].prn = !COPY_SINC_V or !VER_PLACE;
|
||||
|
||||
CT[5].clrn = !COPY_SINC_H;
|
||||
|
||||
-- set CTH to 50 (32h)
|
||||
CTH[0].clrn = !COPY_SINC_H;
|
||||
CTH[1].prn = !COPY_SINC_H;
|
||||
CTH[2].clrn = !COPY_SINC_H;
|
||||
CTH[3].clrn = !COPY_SINC_H;
|
||||
CTH[4].prn = !COPY_SINC_H;
|
||||
CTH[5].prn = !COPY_SINC_H;
|
||||
|
||||
-- set CTV to 122h
|
||||
CTV[0].clrn = !COPY_SINC_V;
|
||||
CTV[1].prn = !COPY_SINC_V;
|
||||
CTV[3..2].clrn = !COPY_SINC_V;
|
||||
|
||||
CTV[4].clrn = !COPY_SINC_V;
|
||||
CTV[5].prn = !COPY_SINC_V;
|
||||
CTV[7..6].clrn = !COPY_SINC_V;
|
||||
CTV[8].prn = !COPY_SINC_V;
|
||||
|
||||
CT[5..0].clk = CLK42;
|
||||
CTH[5..0].clk = CLK42;
|
||||
CTV[8..0].clk = CLK42;
|
||||
|
||||
CT[2..0].ena = VCC;
|
||||
|
||||
CASE CT[2..0] IS
|
||||
WHEN 0 => CT[2..0] = 1;
|
||||
WHEN 1 => CT[2..0] = 2;
|
||||
WHEN 2 => CT[2..0] = 4;
|
||||
WHEN 3 => CT[2..0] = 4;
|
||||
WHEN 4 => CT[2..0] = 5;
|
||||
WHEN 5 => CT[2..0] = 6;
|
||||
WHEN 6 => CT[2..0] = 0;
|
||||
WHEN 7 => CT[2..0] = 0;
|
||||
END CASE;
|
||||
|
||||
-- for remove sinc jitter
|
||||
-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,);
|
||||
CT[5..3].ena = DFF((CT0 & CT2),CLK42,,);
|
||||
CT[5..3] = CT[5..3]+1;
|
||||
%
|
||||
CASE CT[4..3] IS
|
||||
WHEN 0 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 1 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 2 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 3 => CT[5..3] = CT[5..3]+1;
|
||||
END CASE;
|
||||
%
|
||||
CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,);
|
||||
CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,);
|
||||
|
||||
IF CTH[] == 55 THEN
|
||||
CTH[] = GND;
|
||||
ELSE
|
||||
CTH[] = CTH[] + 1;
|
||||
END IF;
|
||||
|
||||
IF CTV[] == 319 THEN
|
||||
CTV[] = GND;
|
||||
ELSE
|
||||
CTV[] = CTV[] + 1;
|
||||
END IF;
|
||||
|
||||
CTF[].clk = CTV8;
|
||||
CTF[] = CTF[]+1;
|
||||
|
||||
-- ==== Video ==========================================================
|
||||
|
||||
ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens
|
||||
ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write
|
||||
ZXA15 = ZX_PORT7; -- ZX A15' line
|
||||
|
||||
SCR128 = DIR_PORT0;
|
||||
|
||||
-- WR_PIX = LCELL(TSN_W3);
|
||||
WR_PIX = (TSN_W3);
|
||||
|
||||
DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS;
|
||||
VXA[].clk = CLK42; VXA[].ena = !E_WR;
|
||||
|
||||
VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[];
|
||||
VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[];
|
||||
VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[];
|
||||
VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[];
|
||||
|
||||
-- VXD0[] = D[];
|
||||
-- VXD1[] = D[];
|
||||
-- VXD2[] = D[];
|
||||
-- VXD3[] = D[];
|
||||
|
||||
(VXD0[],VXD1[]) = MDI[];
|
||||
(VXD2[],VXD3[]) = MDI[];
|
||||
|
||||
BRD[] = DIR_PORT[7..5];
|
||||
|
||||
VCM[].clk = CLK42;
|
||||
TSN_W3.clk = CLK42;
|
||||
V_CST[].clk = CLK42;
|
||||
V_WE.clk = CLK42;
|
||||
V_WET[].clk = CLK42;
|
||||
VLA[].clk = CLK42;
|
||||
|
||||
SCR_ENA.clk = CLK42;
|
||||
SCR_ENA.ena = !E_WR;
|
||||
SCR_ENA.d = !(VAI19 or ZX_SCREEN);
|
||||
|
||||
E_WRD = DFF(E_WR,CLK42,,);
|
||||
E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,));
|
||||
-- E_WR = LCELL(WR or !DFF(WR,CLK42,,));
|
||||
|
||||
-- ****************************************************
|
||||
|
||||
IF MODE == "SPRINTER" GENERATE
|
||||
|
||||
-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode
|
||||
|
||||
-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE);
|
||||
MXWE = DFF(MXWE,CLK42,E_WR,V_WE);
|
||||
|
||||
IF VAI[19] THEN
|
||||
-- in graf mode all 256k(512k) range
|
||||
VXA[] = VAI[];
|
||||
ELSE
|
||||
-- in spectrum mode 8k/16k range pages
|
||||
VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]);
|
||||
END IF;
|
||||
|
||||
-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,);
|
||||
-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,);
|
||||
-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,);
|
||||
|
||||
BORD = DFF((MODE0[7..4] == 15),LWR_COL,,);
|
||||
BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,);
|
||||
INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,);
|
||||
|
||||
INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,);
|
||||
|
||||
-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,);
|
||||
-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]);
|
||||
|
||||
CASE CT[2..0] IS
|
||||
WHEN B"110" => VCM[2..0].d = 5; -- 110 -> 101 6 -> 5
|
||||
WHEN B"000" => VCM[2..0].d = 1; -- 000 -> 001 0 -> 1
|
||||
WHEN B"001" => VCM[2..0].d = 4; -- 001 -> 100 1 -> 4
|
||||
WHEN B"010" => VCM[2..0].d = 3; -- 010 -> 011 2 -> 3
|
||||
WHEN B"100" => VCM[2..0].d = 2; -- 100 -> 010 4 -> 2
|
||||
WHEN B"101" => VCM[2..0].d = 0; -- 101 -> 000 5 -> 0
|
||||
END CASE;
|
||||
|
||||
CASE VCM[1..0] IS
|
||||
WHEN 0 =>
|
||||
VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
IF VCM2 THEN
|
||||
-- TSN_W3.d = X_MODE5;
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE5);
|
||||
ELSE
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE_BOND);
|
||||
END IF;
|
||||
WHEN 1 =>
|
||||
WR_PIC.d = !VCM2;
|
||||
WR_COL.d = VCM2;
|
||||
VLA[].d = SVA[];
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
WHEN 2 =>
|
||||
VLA[].d = VXA[17..0];
|
||||
V_CST[].d = (!VXA18,VXA18) or MXWE;
|
||||
V_WE.d = MXWE;
|
||||
V_WEX.d = GND;
|
||||
V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
WHEN 3 =>
|
||||
-- WR_PIC.d = X_MODE5;
|
||||
-- NEW 26.08.2022, fix bug with first column
|
||||
-- it was reproducing when changes mode 320 -> 640, like any 320px screen squares -> text mode squares
|
||||
WR_PIC.d = MODE0[5];
|
||||
VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND);
|
||||
WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
END CASE;
|
||||
|
||||
-- choose V-RAM komplect
|
||||
|
||||
V_CST1.prn = GND;
|
||||
-- V_CS0.clrn = GND;
|
||||
V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0)));
|
||||
V_CS1 = VCC;
|
||||
-- V_CS0 = LCELL(V_CST0);
|
||||
|
||||
V_CSX0 = LCELL(!CLK42);
|
||||
V_CSX1 = LCELL(V_CSX0);
|
||||
V_CSX2 = LCELL(V_CSX1 & V_CSX0);
|
||||
V_CSX3 = LCELL(V_CSX2);
|
||||
|
||||
-- V_CS0 = V_CSX3;
|
||||
V_CS0 = GND;
|
||||
|
||||
-- =====================
|
||||
|
||||
SVA[].clk = CLK42;
|
||||
SVA[9..6] = MODE0[3..0];
|
||||
-- RSVA[].clk = CLK42;
|
||||
(SVA[12..10],SVA[5..0]) = RSVA[];
|
||||
|
||||
-- M_CTV[2..0].clk = CLK42;
|
||||
-- M_CT[5..3].clk = CLK42;
|
||||
M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]);
|
||||
M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]);
|
||||
|
||||
CASE (!VCM2,MODE0[4]) IS
|
||||
-- CASE (!VCM1,MODE0[4]) IS
|
||||
WHEN B"X0" =>
|
||||
-- Graf adress --
|
||||
RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = CTV[2..0];
|
||||
-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]);
|
||||
WHEN B"01" =>
|
||||
-- ZX-atr adress --
|
||||
RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
SVA[17..13] = MODE2[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE2[2..0];
|
||||
-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
WHEN B"11" =>
|
||||
-- ZX-pic adress --
|
||||
RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE1[2..0];
|
||||
-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
END CASE;
|
||||
|
||||
-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC));
|
||||
X_MODE_BOND = GND;
|
||||
|
||||
-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
LD_PIC = LCELL((MODE0[5] & DFF((CT[5..2] == B"0000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
|
||||
|
||||
-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS
|
||||
|
||||
-- D_PIC0_[].clk = !CLK42;
|
||||
-- D_PIC1_[].clk = !CLK42;
|
||||
-- D_PIC2_[].clk = !CLK42;
|
||||
-- D_PIC3_[].clk = !CLK42;
|
||||
|
||||
-- PIC_CLK = LCELL(LCELL(CLK42));
|
||||
PIC_CLK = !CLK42;
|
||||
|
||||
D_PIC0_[].clk = PIC_CLK;
|
||||
D_PIC1_[].clk = PIC_CLK;
|
||||
D_PIC2_[].clk = PIC_CLK;
|
||||
D_PIC3_[].clk = PIC_CLK;
|
||||
|
||||
D_PIC0_[] = VDM0[];
|
||||
D_PIC1_[] = VDM1[];
|
||||
D_PIC2_[] = VDM2[];
|
||||
D_PIC3_[] = VDM3[];
|
||||
|
||||
CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS
|
||||
WHEN 0 => D_PICX_[] = D_PIC0_[];
|
||||
WHEN 1 => D_PICX_[] = D_PIC1_[];
|
||||
WHEN 2 => D_PICX_[] = D_PIC2_[];
|
||||
WHEN 3 => D_PICX_[] = D_PIC3_[];
|
||||
END CASE;
|
||||
|
||||
MODE0[].ena = VCC;
|
||||
MODE1[].ena = VCC;
|
||||
MODE2[].ena = VCC;
|
||||
MODE0[].clk = LWR_MODE;
|
||||
MODE1[].clk = LWR_MODE;
|
||||
MODE2[].clk = LWR_MODE;
|
||||
MODE0[].d = VDM3[];
|
||||
MODE1[].d = VDM2[];
|
||||
MODE2[].d = VDM1[];
|
||||
LWR_MODE = LCELL(LCELL(WR_MODE));
|
||||
%
|
||||
MODE0[].ena = LWR_MODE;
|
||||
MODE1[].ena = LWR_MODE;
|
||||
MODE2[].ena = LWR_MODE;
|
||||
MODE0[].clk = CLK42;
|
||||
MODE1[].clk = CLK42;
|
||||
MODE2[].clk = CLK42;
|
||||
MODE0[].d = D_PIC3_[];
|
||||
MODE1[].d = D_PIC2_[];
|
||||
MODE2[].d = D_PIC1_[];
|
||||
LWR_MODE = DFF(!WR_MODE,CLK42,,);
|
||||
%
|
||||
X_MODE7 = DFF(MODE0[7],LWR_COL,,);
|
||||
X_MODE6 = DFF(MODE0[6],LWR_COL,,);
|
||||
X_MODE5 = DFF(MODE0[5],LWR_COL,,);
|
||||
X_MODE4 = DFF(MODE0[4],LWR_COL,,);
|
||||
|
||||
VAO[] = VLA[17..2];
|
||||
|
||||
WR_PIC.clk = CLK42;
|
||||
WR_COL.clk = CLK42;
|
||||
WR_MODE.clk = CLK42;
|
||||
|
||||
-- LWR_PIC = LCELL(LCELL(WR_PIC));
|
||||
-- LWR_COL = LCELL(LCELL(WR_COL));
|
||||
-- LWR_PIC = LCELL(WR_PIC);
|
||||
-- LWR_COL = LCELL(WR_COL);
|
||||
LWR_PIC = DFF(WR_PIC,CLK42,,);
|
||||
LWR_COL = DFF(WR_COL,CLK42,,);
|
||||
|
||||
-- D_PIC0[].ena = VCC;
|
||||
-- D_PIC0[].clk = (LWR_PIC);
|
||||
D_PIC0[].ena = !LWR_PIC;
|
||||
D_PIC0[].clk = CLK42;
|
||||
|
||||
|
||||
|
||||
|
||||
IF LD_PIC THEN
|
||||
-- D_PIC0[] = D_PIC0_[];
|
||||
D_PIC0[] = D_PICX_[];
|
||||
ELSE
|
||||
D_PIC0[] = (D_PIC0[6..0],GND);
|
||||
END IF;
|
||||
|
||||
|
||||
-- DCOL[].clk = (LWR_COL);
|
||||
DCOL[].ena = !LWR_COL;
|
||||
DCOL[].clk = CLK42;
|
||||
|
||||
IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN
|
||||
DCOL[].d = (B"00",BRD[2..0],BRD[2..0]);
|
||||
ELSE
|
||||
-- DCOL[].d = D_PIC0_[];
|
||||
DCOL[].d = D_PICX_[];
|
||||
END IF;
|
||||
|
||||
DCOL[].clrn = !BLANK;
|
||||
|
||||
BRVA[].clk = CLK42;
|
||||
BRVA[].clrn = !MS_POINT;
|
||||
BRVA[].prn = !MS_POINT2;
|
||||
|
||||
-- MODE0[4] - graph / text
|
||||
-- MODE0[5] - 320 / 640 resolution
|
||||
|
||||
-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS
|
||||
CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS
|
||||
WHEN B"1X" => BRVA[7..0] = DCOL[];
|
||||
WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]);
|
||||
WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]);
|
||||
END CASE;
|
||||
|
||||
-- BRVA[10..8] = (x_mode4,RBRVA[9..8]);
|
||||
RBRVA[].clk = CLK42;
|
||||
|
||||
CASE (BORD,X_MODE4) IS
|
||||
WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]);
|
||||
WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]);
|
||||
END CASE;
|
||||
|
||||
RBRVA[9..8].clrn = !BORD;
|
||||
RBRVA[10].prn = !BORD;
|
||||
|
||||
CASE (RBRVA[9..8],BRVA7) IS
|
||||
WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]);
|
||||
WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]);
|
||||
END CASE;
|
||||
|
||||
-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
|
||||
V_WE_R = DFF(GND,!CLK42,,!V_WE);
|
||||
V_WE.prn = V_WE_R;
|
||||
V_WET[].prn = V_WE_R;
|
||||
|
||||
-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
|
||||
-- V_WR[] = (V_WE) or !(
|
||||
|
||||
V_WEX.clk = CLK42;
|
||||
-- V_WEX.d = V_WE;
|
||||
-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX));
|
||||
|
||||
|
||||
|
||||
|
||||
V_WEMMM = LCELL(V_WE);
|
||||
V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok
|
||||
V_WEMMO = LCELL(V_WEMMN); -- green arts
|
||||
V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts
|
||||
V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??)
|
||||
V_WEMMS = LCELL(V_WEMMR);
|
||||
-- V_WEMMT = LCELL(V_WEMMS);
|
||||
-- V_WEMMU = LCELL(V_WEMMT);
|
||||
-- V_WEMMV = LCELL(V_WEMMU);
|
||||
-- V_WEMMW = LCELL(V_WEMMV);
|
||||
-- V_WEMMX = LCELL(V_WEMMW);
|
||||
-- V_WEMMY = LCELL(V_WEMMX);
|
||||
-- V_WEMMZ = LCELL(V_WEMMY);
|
||||
|
||||
V_WRM = LCELL(V_WE or V_WEMMM);
|
||||
-- V_WRM = LCELL(V_WEMMN or V_WEMMM);
|
||||
-- V_WRM2 = LCELL(V_WEMMN or V_WEMMM);
|
||||
-- V_WRM2 = LCELL(V_WEMMR);
|
||||
-- V_WRM = LCELL(V_WEMMM or V_WEMMN);
|
||||
-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN);
|
||||
|
||||
V_WEM = (V_WE);
|
||||
-- V_WEM2 = LCELL(V_WE);
|
||||
-- V_WEM = LCELL(V_WEMMM & V_WEMMN);
|
||||
-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO);
|
||||
|
||||
F_WR = DFF(VCC,V_WE,,);
|
||||
V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,);
|
||||
V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,);
|
||||
V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,);
|
||||
V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,);
|
||||
|
||||
|
||||
-- V_WR_3 = LCELL(V_WRM or V_EN3);
|
||||
-- V_WR_2 = LCELL(V_WRM or V_EN2);
|
||||
-- V_WR_1 = LCELL(V_WRM or V_EN1);
|
||||
-- V_WR_0 = LCELL(V_WRM or V_EN0);
|
||||
V_WR_3 = LCELL(LCELL(LCELL(V_WRM or V_EN3)));
|
||||
V_WR_2 = LCELL(LCELL(LCELL(V_WRM or V_EN2)));
|
||||
V_WR_1 = LCELL(LCELL(LCELL(V_WRM or V_EN1)));
|
||||
V_WR_0 = LCELL(LCELL(LCELL(V_WRM or V_EN0)));
|
||||
|
||||
V_WEY3 = LCELL(V_WEM or V_EN3);
|
||||
V_WEY2 = LCELL(V_WEM or V_EN2);
|
||||
V_WEY1 = LCELL(V_WEM or V_EN1);
|
||||
V_WEY0 = LCELL(V_WEM or V_EN0);
|
||||
|
||||
V_WR[] = V_WR_[]; -- V_WR0-3
|
||||
V_WEN[] = V_WEY[]; -- VD0-3
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
%
|
||||
V_WEMMM = LCELL(V_WE);
|
||||
V_WEMMN = LCELL(V_WEMMM);
|
||||
V_WEMMO = LCELL(V_WEMMN);
|
||||
V_WEMM = LCELL(V_WEMMO);
|
||||
|
||||
V_WRM = LCELL(V_WEMMN & V_WEMMM);
|
||||
V_WRM2 = LCELL(V_WEMMN & V_WEMMM);
|
||||
|
||||
V_WEM = LCELL(V_WEMMM & V_WEMMO);
|
||||
V_WEM2 = LCELL(V_WEMMM & V_WEMMO);
|
||||
|
||||
V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)),CLK42,F_WR,);
|
||||
V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
|
||||
F_WR = DFF(VCC,V_WE,,);
|
||||
|
||||
V_WR_3 = V_WRM or V_EN3;
|
||||
V_WR_2 = V_WRM2 or V_EN2;
|
||||
V_WR_1 = V_WRM or V_EN1;
|
||||
V_WR_0 = V_WRM or V_EN0;
|
||||
|
||||
V_WEY3 = V_WEM or V_EN3;
|
||||
V_WEY2 = V_WEM2 or V_EN2;
|
||||
V_WEY1 = V_WEM or V_EN1;
|
||||
V_WEY0 = V_WEM or V_EN0;
|
||||
|
||||
V_WR[] = V_WR_[];
|
||||
V_WEN[] = V_WEY[];
|
||||
%
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- CLK84 = LCELL(CLK42 xor CLK84_X);
|
||||
-- CLK84_X = DFF(!CLK84_X,CLK84,,);
|
||||
-- CLK84_Y = CLK84;
|
||||
|
||||
END GENERATE; -- end "sprinter" mode
|
||||
|
||||
|
||||
END;
|
||||
@ -1,783 +0,0 @@
|
||||
|
||||
TITLE "Video-controller";
|
||||
|
||||
INCLUDE "lpm_ram_dp";
|
||||
|
||||
PARAMETERS
|
||||
(
|
||||
MODE = "SPRINTER",
|
||||
MOUSE = "NO",
|
||||
HOR_PLACE = H"50",
|
||||
VER_PLACE = H"91" -- 122h/2
|
||||
);
|
||||
|
||||
SUBDESIGN video2
|
||||
(
|
||||
CLK42 : INPUT;
|
||||
|
||||
CT[5..0] : OUTPUT;
|
||||
CTH[5..0] : OUTPUT;
|
||||
CTV[8..0] : OUTPUT;
|
||||
CTF[6..0] : OUTPUT;
|
||||
|
||||
BLANK : OUTPUT;
|
||||
|
||||
START_UP : INPUT;
|
||||
COPY_SINC_H : INPUT;
|
||||
COPY_SINC_V : INPUT;
|
||||
|
||||
WR : INPUT;
|
||||
|
||||
VAI[19..0] : INPUT; -- input screen adress
|
||||
|
||||
VAO[15..0] : OUTPUT;
|
||||
|
||||
D[7..0] : INPUT;
|
||||
MDI[15..0] : INPUT;
|
||||
|
||||
VDO0[7..0] : OUTPUT;
|
||||
VDO1[7..0] : OUTPUT;
|
||||
VDO2[7..0] : OUTPUT;
|
||||
VDO3[7..0] : OUTPUT;
|
||||
|
||||
VDM0[7..0] : INPUT;
|
||||
VDM1[7..0] : INPUT;
|
||||
VDM2[7..0] : INPUT;
|
||||
VDM3[7..0] : INPUT;
|
||||
|
||||
V_WR[3..0] : OUTPUT;
|
||||
V_WEN[3..0] : OUTPUT;
|
||||
|
||||
V_CS[1..0] : OUTPUT;
|
||||
WR_PIX : OUTPUT;
|
||||
|
||||
-- ZX_COLOR[3..0] : OUTPUT;
|
||||
|
||||
ZX_PORT[7..0] : INPUT;
|
||||
DIR_PORT[7..0] : INPUT;
|
||||
|
||||
%
|
||||
bit0 - Spectrum SCREEN Switch
|
||||
bit1 - Spectrum Adress MODE
|
||||
bit2 - Write to Spectrum Screen OFF
|
||||
bit3 - MODE page 0/1
|
||||
bit4 - MODE on/off screen
|
||||
|
||||
bit7..5 - Border
|
||||
%
|
||||
|
||||
INTT : OUTPUT;
|
||||
|
||||
DOUBLE_CAS : INPUT;
|
||||
|
||||
MOUSE_X[9..0] : INPUT;
|
||||
MOUSE_Y[9..0] : INPUT;
|
||||
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
-- CLK84 : NODE;
|
||||
-- CLK84_X : NODE;
|
||||
-- CLK84_Y : NODE;
|
||||
|
||||
ZX_COLOR[3..0] : NODE;
|
||||
|
||||
CT[5..0] : DFFE;
|
||||
CTH[5..0] : DFFE;
|
||||
CTV[8..0] : DFFE;
|
||||
CTF[6..0] : DFF;
|
||||
|
||||
VXA[19..0] : DFFE;
|
||||
|
||||
VXD0[7..0] : DFFE;
|
||||
VXD1[7..0] : DFFE;
|
||||
VXD2[7..0] : DFFE;
|
||||
VXD3[7..0] : DFFE;
|
||||
|
||||
E_WR : NODE;
|
||||
E_WRD : NODE;
|
||||
|
||||
BLANK : NODE;
|
||||
BORD : NODE;
|
||||
-- INTT_T : NODE;
|
||||
INTTX : NODE;
|
||||
|
||||
VLA[17..0] : DFF;
|
||||
-- SVA[17..0] : NODE;
|
||||
SVA[17..0] : DFF;
|
||||
-- RSVA[8..0] : LCELL;
|
||||
RSVA[8..0] : NODE;
|
||||
-- RSVA[8..0] : DFF;
|
||||
|
||||
V_CST[1..0] : DFF;
|
||||
VCM[2..0] : DFF;
|
||||
TSN_W3 : DFF;
|
||||
V_WE : DFF;
|
||||
V_WEX : DFF;
|
||||
|
||||
V_WEM : NODE;
|
||||
V_WEM2 : NODE;
|
||||
V_WRM : NODE;
|
||||
V_WRM2 : NODE;
|
||||
%
|
||||
V_WEMM : NODE;
|
||||
V_WEMMM : NODE;
|
||||
V_WEMMN : NODE;
|
||||
V_WEMMO : NODE;
|
||||
%
|
||||
V_WEMM : NODE;
|
||||
V_WEMMM : NODE;
|
||||
V_WEMMN : NODE;
|
||||
V_WEMMO : NODE;
|
||||
V_WEMMP : NODE;
|
||||
V_WEMMQ : NODE;
|
||||
V_WEMMR : NODE;
|
||||
V_WEMMS : NODE;
|
||||
V_WEMMT : NODE;
|
||||
V_WEMMU : NODE;
|
||||
V_WEMMV : NODE;
|
||||
V_WEMMW : NODE;
|
||||
V_WEMMX : NODE;
|
||||
V_WEMMY : NODE;
|
||||
V_WEMMZ : NODE;
|
||||
|
||||
|
||||
|
||||
V_WET[3..0] : DFF;
|
||||
|
||||
D_PIC0[7..0] : DFFE;
|
||||
-- D_PIC0_[7..0] : LCELL;
|
||||
|
||||
D_PIC0_[7..0] : DFFE;
|
||||
D_PIC1_[7..0] : DFFE;
|
||||
D_PIC2_[7..0] : DFFE;
|
||||
D_PIC3_[7..0] : DFFE;
|
||||
|
||||
D_PICX_[7..0] : NODE;
|
||||
|
||||
LWR_PIC : NODE;
|
||||
LWR_COL : NODE;
|
||||
|
||||
WR_PIC : DFF;
|
||||
WR_COL : DFF;
|
||||
LD_PIC : NODE;
|
||||
MXL: NODE;
|
||||
MXR: NODE;
|
||||
|
||||
RBRVA[10..8]: DFF;
|
||||
BRVA[7..0] : DFF;
|
||||
DCOL[7..0] : DFFE;
|
||||
|
||||
MXWE : NODE;
|
||||
-- MXCE : NODE;
|
||||
|
||||
AX128 : NODE;
|
||||
|
||||
BRD[2..0] : NODE;
|
||||
|
||||
ZX_COL[3..0] : LCELL;
|
||||
|
||||
ZXA15 : NODE;
|
||||
ZXS[5..0] : NODE;
|
||||
ZX_SCREEN : NODE;
|
||||
SCR128 : NODE;
|
||||
|
||||
MODE0[7..0] : DFFE;
|
||||
MODE1[7..0] : DFFE;
|
||||
MODE2[7..0] : DFFE;
|
||||
-- MODE3[7..0] : DFF;
|
||||
|
||||
WR_MODE : DFF;
|
||||
LWR_MODE : NODE;
|
||||
X_MODE[7..4]: NODE;
|
||||
X_MODE_BOND : NODE;
|
||||
|
||||
-- M_CTV[2..0] : DFF;
|
||||
-- M_CT[5..3] : DFF;
|
||||
M_CTV[2..0] : LCELL;
|
||||
M_CT[5..3] : LCELL;
|
||||
|
||||
DOUBLE : DFFE;
|
||||
|
||||
PIC_CLK : NODE;
|
||||
|
||||
MS_X[9..0] : DFF;
|
||||
MS_Y[9..0] : DFF;
|
||||
|
||||
MS_POINT : NODE;
|
||||
MS_POINT2 : NODE;
|
||||
MS_PNT : NODE;
|
||||
|
||||
MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF");
|
||||
|
||||
SCR_ENA : DFFE;
|
||||
V_WR_[3..0] : LCELL;
|
||||
V_WEY[3..0] : LCELL;
|
||||
|
||||
V_WE_R : NODE;
|
||||
|
||||
V_CSX[3..0] : NODE;
|
||||
|
||||
V_EN[3..0] : NODE;
|
||||
|
||||
F_WR : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
DEFAULTS
|
||||
WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC;
|
||||
V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC;
|
||||
V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC;
|
||||
V_WET[].d = VCC;
|
||||
END DEFAULTS;
|
||||
|
||||
ZX_COLOR[] = ZX_COL[];
|
||||
|
||||
-- === MOUSE counters ========
|
||||
|
||||
MS_X[].clk = !CT1;
|
||||
CASE LCELL(CTH[5..2] == 12) IS
|
||||
WHEN 0 => MS_X[] = MS_X[] + 1;
|
||||
WHEN 1 => MS_X[] = (!MOUSE_X[9..0]);
|
||||
END CASE;
|
||||
|
||||
MS_Y[].clk = !CTH5;
|
||||
CASE LCELL(CTV8 & !CTV5 & CTV4) IS
|
||||
WHEN 0 => MS_Y[] = MS_Y[] + 1;
|
||||
WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]);
|
||||
END CASE;
|
||||
|
||||
MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,);
|
||||
|
||||
MS_DAT.wren = GND;
|
||||
MS_DAT.data[] = GND;
|
||||
MS_DAT.wraddress[] = GND;
|
||||
MS_DAT.wrclock = CLK42;
|
||||
MS_DAT.wrclken = GND;
|
||||
MS_DAT.rden = VCC;
|
||||
MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]);
|
||||
MS_DAT.rdclock = CLK42;
|
||||
MS_DAT.rdclken = VCC;
|
||||
|
||||
IF MOUSE == "NO" GENERATE
|
||||
MS_POINT = GND;
|
||||
MS_POINT2 = GND;
|
||||
ELSE GENERATE
|
||||
MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,);
|
||||
MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,);
|
||||
END GENERATE;
|
||||
|
||||
-- === Sinc-counts GENERATOR ============================================
|
||||
|
||||
-- CT[].clrn = START_UP;
|
||||
|
||||
-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE;
|
||||
-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE;
|
||||
|
||||
-- CTV[].clrn = !COPY_SINC_V or VER_PLACE;
|
||||
-- CTV[].prn = !COPY_SINC_V or !VER_PLACE;
|
||||
|
||||
CT[5].clrn = !COPY_SINC_H;
|
||||
|
||||
-- set CTH to 50 (32h)
|
||||
CTH[0].clrn = !COPY_SINC_H;
|
||||
CTH[1].prn = !COPY_SINC_H;
|
||||
CTH[2].clrn = !COPY_SINC_H;
|
||||
CTH[3].clrn = !COPY_SINC_H;
|
||||
CTH[4].prn = !COPY_SINC_H;
|
||||
CTH[5].prn = !COPY_SINC_H;
|
||||
|
||||
-- set CTV to 122h
|
||||
CTV[0].clrn = !COPY_SINC_V;
|
||||
CTV[1].prn = !COPY_SINC_V;
|
||||
CTV[3..2].clrn = !COPY_SINC_V;
|
||||
|
||||
CTV[4].clrn = !COPY_SINC_V;
|
||||
CTV[5].prn = !COPY_SINC_V;
|
||||
CTV[7..6].clrn = !COPY_SINC_V;
|
||||
CTV[8].prn = !COPY_SINC_V;
|
||||
|
||||
CT[5..0].clk = CLK42;
|
||||
CTH[5..0].clk = CLK42;
|
||||
CTV[8..0].clk = CLK42;
|
||||
|
||||
CT[2..0].ena = VCC;
|
||||
|
||||
CASE CT[2..0] IS
|
||||
WHEN 0 => CT[2..0] = 1;
|
||||
WHEN 1 => CT[2..0] = 2;
|
||||
WHEN 2 => CT[2..0] = 4;
|
||||
WHEN 3 => CT[2..0] = 4;
|
||||
WHEN 4 => CT[2..0] = 5;
|
||||
WHEN 5 => CT[2..0] = 6;
|
||||
WHEN 6 => CT[2..0] = 0;
|
||||
WHEN 7 => CT[2..0] = 0;
|
||||
END CASE;
|
||||
|
||||
-- for remove sinc jitter
|
||||
-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,);
|
||||
CT[5..3].ena = DFF((CT0 & CT2),CLK42,,);
|
||||
CT[5..3] = CT[5..3]+1;
|
||||
%
|
||||
CASE CT[4..3] IS
|
||||
WHEN 0 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 1 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 2 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 3 => CT[5..3] = CT[5..3]+1;
|
||||
END CASE;
|
||||
%
|
||||
CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,);
|
||||
CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,);
|
||||
|
||||
IF CTH[] == 55 THEN
|
||||
CTH[] = GND;
|
||||
ELSE
|
||||
CTH[] = CTH[] + 1;
|
||||
END IF;
|
||||
|
||||
IF CTV[] == 319 THEN
|
||||
CTV[] = GND;
|
||||
ELSE
|
||||
CTV[] = CTV[] + 1;
|
||||
END IF;
|
||||
|
||||
CTF[].clk = CTV8;
|
||||
CTF[] = CTF[]+1;
|
||||
|
||||
-- ==== Video ==========================================================
|
||||
|
||||
ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens
|
||||
ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write
|
||||
ZXA15 = ZX_PORT7; -- ZX A15' line
|
||||
|
||||
SCR128 = DIR_PORT0;
|
||||
|
||||
-- WR_PIX = LCELL(TSN_W3);
|
||||
WR_PIX = TSN_W3;
|
||||
|
||||
DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS;
|
||||
VXA[].clk = CLK42; VXA[].ena = !E_WR;
|
||||
|
||||
VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[];
|
||||
VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[];
|
||||
VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[];
|
||||
VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[];
|
||||
|
||||
-- VXD0[] = D[];
|
||||
-- VXD1[] = D[];
|
||||
-- VXD2[] = D[];
|
||||
-- VXD3[] = D[];
|
||||
|
||||
(VXD0[],VXD1[]) = MDI[];
|
||||
(VXD2[],VXD3[]) = MDI[];
|
||||
|
||||
BRD[] = DIR_PORT[7..5];
|
||||
|
||||
VCM[].clk = CLK42;
|
||||
TSN_W3.clk = CLK42;
|
||||
V_CST[].clk = CLK42;
|
||||
V_WE.clk = CLK42;
|
||||
V_WET[].clk = CLK42;
|
||||
VLA[].clk = CLK42;
|
||||
|
||||
SCR_ENA.clk = CLK42;
|
||||
SCR_ENA.ena = !E_WR;
|
||||
SCR_ENA.d = !(VAI19 or ZX_SCREEN);
|
||||
|
||||
E_WRD = DFF(E_WR,CLK42,,);
|
||||
E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,));
|
||||
-- E_WR = LCELL(WR or !DFF(WR,CLK42,,));
|
||||
|
||||
-- ****************************************************
|
||||
|
||||
IF MODE == "SPRINTER" GENERATE
|
||||
|
||||
-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode
|
||||
|
||||
-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE);
|
||||
MXWE = DFF(MXWE,CLK42,E_WR,V_WE);
|
||||
|
||||
IF VAI[19] THEN
|
||||
-- in graf mode all 256k(512k) range
|
||||
VXA[] = VAI[];
|
||||
ELSE
|
||||
-- in spectrum mode 8k/16k range pages
|
||||
VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]);
|
||||
END IF;
|
||||
|
||||
-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,);
|
||||
-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,);
|
||||
-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,);
|
||||
|
||||
BORD = DFF((MODE0[7..4] == 15),LWR_COL,,);
|
||||
BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,);
|
||||
INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,);
|
||||
|
||||
INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,);
|
||||
|
||||
-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,);
|
||||
-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]);
|
||||
|
||||
CASE CT[2..0] IS
|
||||
WHEN B"110" => VCM[2..0].d = 5; -- 110 -> 101 6 -> 5
|
||||
WHEN B"000" => VCM[2..0].d = 1; -- 000 -> 001 0 -> 1
|
||||
WHEN B"001" => VCM[2..0].d = 4; -- 001 -> 100 1 -> 4
|
||||
WHEN B"010" => VCM[2..0].d = 3; -- 010 -> 011 2 -> 3
|
||||
WHEN B"100" => VCM[2..0].d = 2; -- 100 -> 010 4 -> 2
|
||||
WHEN B"101" => VCM[2..0].d = 0; -- 101 -> 000 5 -> 0
|
||||
END CASE;
|
||||
|
||||
CASE VCM[1..0] IS
|
||||
WHEN 0 =>
|
||||
VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
%
|
||||
IF VCM2 THEN
|
||||
-- TSN_W3.d = X_MODE5;
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE5);
|
||||
ELSE
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE_BOND);
|
||||
END IF;
|
||||
%
|
||||
|
||||
WHEN 1 =>
|
||||
WR_PIC.d = !VCM2;
|
||||
WR_COL.d = VCM2;
|
||||
VLA[].d = SVA[];
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
WHEN 2 =>
|
||||
VLA[].d = VXA[17..0];
|
||||
V_CST[].d = (!VXA18,VXA18) or MXWE;
|
||||
V_WE.d = MXWE;
|
||||
V_WEX.d = GND;
|
||||
V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
WHEN 3 =>
|
||||
-- WR_PIC.d = X_MODE5;
|
||||
-- NEW 26.08.2022, fix bug with first column
|
||||
-- it was reproducing when changes mode 320 -> 640, like any 320px screen squares -> text mode squares
|
||||
WR_PIC.d = MODE0[5];
|
||||
VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND);
|
||||
WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
END CASE;
|
||||
|
||||
-- choose V-RAM komplect
|
||||
|
||||
V_CST1.prn = GND;
|
||||
-- V_CS0.clrn = GND;
|
||||
V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0)));
|
||||
V_CS1 = VCC;
|
||||
-- V_CS0 = LCELL(V_CST0);
|
||||
|
||||
V_CSX0 = LCELL(!CLK42);
|
||||
V_CSX1 = LCELL(V_CSX0);
|
||||
V_CSX2 = LCELL(V_CSX1 & V_CSX0);
|
||||
V_CSX3 = LCELL(V_CSX2);
|
||||
|
||||
-- V_CS0 = V_CSX3;
|
||||
V_CS0 = GND;
|
||||
|
||||
-- =====================
|
||||
|
||||
SVA[].clk = CLK42;
|
||||
SVA[9..6] = MODE0[3..0];
|
||||
-- RSVA[].clk = CLK42;
|
||||
(SVA[12..10],SVA[5..0]) = RSVA[];
|
||||
|
||||
-- M_CTV[2..0].clk = CLK42;
|
||||
-- M_CT[5..3].clk = CLK42;
|
||||
M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]);
|
||||
M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]);
|
||||
|
||||
CASE (!VCM2,MODE0[4]) IS
|
||||
-- CASE (!VCM1,MODE0[4]) IS
|
||||
WHEN B"X0" =>
|
||||
-- Graf adress --
|
||||
RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = CTV[2..0];
|
||||
-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]);
|
||||
WHEN B"01" =>
|
||||
-- ZX-atr adress --
|
||||
RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
SVA[17..13] = MODE2[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE2[2..0];
|
||||
-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
WHEN B"11" =>
|
||||
-- ZX-pic adress --
|
||||
RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE1[2..0];
|
||||
-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
END CASE;
|
||||
|
||||
-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC));
|
||||
X_MODE_BOND = GND;
|
||||
|
||||
-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
|
||||
|
||||
-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS
|
||||
|
||||
-- D_PIC0_[].clk = !CLK42;
|
||||
-- D_PIC1_[].clk = !CLK42;
|
||||
-- D_PIC2_[].clk = !CLK42;
|
||||
-- D_PIC3_[].clk = !CLK42;
|
||||
|
||||
-- PIC_CLK = LCELL(LCELL(CLK42));
|
||||
PIC_CLK = !CLK42;
|
||||
|
||||
D_PIC0_[].clk = PIC_CLK;
|
||||
D_PIC1_[].clk = PIC_CLK;
|
||||
D_PIC2_[].clk = PIC_CLK;
|
||||
D_PIC3_[].clk = PIC_CLK;
|
||||
|
||||
D_PIC0_[] = VDM0[];
|
||||
D_PIC1_[] = VDM1[];
|
||||
D_PIC2_[] = VDM2[];
|
||||
D_PIC3_[] = VDM3[];
|
||||
|
||||
CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS
|
||||
WHEN 0 => D_PICX_[] = D_PIC0_[];
|
||||
WHEN 1 => D_PICX_[] = D_PIC1_[];
|
||||
WHEN 2 => D_PICX_[] = D_PIC2_[];
|
||||
WHEN 3 => D_PICX_[] = D_PIC3_[];
|
||||
END CASE;
|
||||
|
||||
MODE0[].ena = VCC;
|
||||
MODE1[].ena = VCC;
|
||||
MODE2[].ena = VCC;
|
||||
MODE0[].clk = LWR_MODE;
|
||||
MODE1[].clk = LWR_MODE;
|
||||
MODE2[].clk = LWR_MODE;
|
||||
MODE0[].d = VDM3[];
|
||||
MODE1[].d = VDM2[];
|
||||
MODE2[].d = VDM1[];
|
||||
LWR_MODE = LCELL(LCELL(WR_MODE));
|
||||
%
|
||||
MODE0[].ena = LWR_MODE;
|
||||
MODE1[].ena = LWR_MODE;
|
||||
MODE2[].ena = LWR_MODE;
|
||||
MODE0[].clk = CLK42;
|
||||
MODE1[].clk = CLK42;
|
||||
MODE2[].clk = CLK42;
|
||||
MODE0[].d = D_PIC3_[];
|
||||
MODE1[].d = D_PIC2_[];
|
||||
MODE2[].d = D_PIC1_[];
|
||||
LWR_MODE = DFF(!WR_MODE,CLK42,,);
|
||||
%
|
||||
X_MODE7 = DFF(MODE0[7],LWR_COL,,);
|
||||
X_MODE6 = DFF(MODE0[6],LWR_COL,,);
|
||||
X_MODE5 = DFF(MODE0[5],LWR_COL,,);
|
||||
X_MODE4 = DFF(MODE0[4],LWR_COL,,);
|
||||
|
||||
VAO[] = VLA[17..2];
|
||||
|
||||
WR_PIC.clk = CLK42;
|
||||
WR_COL.clk = CLK42;
|
||||
WR_MODE.clk = CLK42;
|
||||
|
||||
-- LWR_PIC = LCELL(LCELL(WR_PIC));
|
||||
-- LWR_COL = LCELL(LCELL(WR_COL));
|
||||
-- LWR_PIC = LCELL(WR_PIC);
|
||||
-- LWR_COL = LCELL(WR_COL);
|
||||
LWR_PIC = DFF(WR_PIC,CLK42,,);
|
||||
LWR_COL = DFF(WR_COL,CLK42,,);
|
||||
|
||||
-- D_PIC0[].ena = VCC;
|
||||
-- D_PIC0[].clk = (LWR_PIC);
|
||||
D_PIC0[].ena = !LWR_PIC;
|
||||
D_PIC0[].clk = CLK42;
|
||||
|
||||
|
||||
|
||||
|
||||
IF LD_PIC THEN
|
||||
-- D_PIC0[] = D_PIC0_[];
|
||||
D_PIC0[] = D_PICX_[];
|
||||
ELSE
|
||||
D_PIC0[] = (D_PIC0[6..0],GND);
|
||||
END IF;
|
||||
|
||||
|
||||
-- DCOL[].clk = (LWR_COL);
|
||||
DCOL[].ena = !LWR_COL;
|
||||
DCOL[].clk = CLK42;
|
||||
|
||||
IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN
|
||||
DCOL[].d = (B"00",BRD[2..0],BRD[2..0]);
|
||||
ELSE
|
||||
-- DCOL[].d = D_PIC0_[];
|
||||
DCOL[].d = D_PICX_[];
|
||||
END IF;
|
||||
|
||||
DCOL[].clrn = !BLANK;
|
||||
|
||||
BRVA[].clk = CLK42;
|
||||
BRVA[].clrn = !MS_POINT;
|
||||
BRVA[].prn = !MS_POINT2;
|
||||
|
||||
-- MODE0[4] - graph / text
|
||||
-- MODE0[5] - 320 / 640 resolution
|
||||
|
||||
-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS
|
||||
CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS
|
||||
WHEN B"1X" => BRVA[7..0] = DCOL[];
|
||||
WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]);
|
||||
WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]);
|
||||
END CASE;
|
||||
|
||||
-- BRVA[10..8] = (x_mode4,RBRVA[9..8]);
|
||||
RBRVA[].clk = CLK42;
|
||||
|
||||
CASE (BORD,X_MODE4) IS
|
||||
WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]);
|
||||
WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]);
|
||||
END CASE;
|
||||
|
||||
RBRVA[9..8].clrn = !BORD;
|
||||
RBRVA[10].prn = !BORD;
|
||||
|
||||
CASE (RBRVA[9..8],BRVA7) IS
|
||||
WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]);
|
||||
WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]);
|
||||
END CASE;
|
||||
|
||||
-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
|
||||
V_WE_R = DFF(GND,!CLK42,,!V_WE);
|
||||
V_WE.prn = V_WE_R;
|
||||
V_WET[].prn = V_WE_R;
|
||||
|
||||
-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
|
||||
-- V_WR[] = (V_WE) or !(
|
||||
|
||||
V_WEX.clk = CLK42;
|
||||
-- V_WEX.d = V_WE;
|
||||
-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX));
|
||||
|
||||
|
||||
|
||||
|
||||
V_WEMMM = LCELL(V_WE);
|
||||
-- V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok
|
||||
-- V_WEMMO = LCELL(V_WEMMN); -- green arts
|
||||
-- V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts
|
||||
-- V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??)
|
||||
-- V_WEMMS = LCELL(V_WEMMR);
|
||||
-- V_WEMMT = LCELL(V_WEMMS);
|
||||
-- V_WEMMU = LCELL(V_WEMMT);
|
||||
-- V_WEMMV = LCELL(V_WEMMU);
|
||||
-- V_WEMMW = LCELL(V_WEMMV);
|
||||
-- V_WEMMX = LCELL(V_WEMMW);
|
||||
-- V_WEMMY = LCELL(V_WEMMX);
|
||||
-- V_WEMMZ = LCELL(V_WEMMY);
|
||||
|
||||
V_WRM = LCELL(V_WE or V_WEMMM);
|
||||
|
||||
|
||||
-- V_WRM = LCELL(V_WEMMN or V_WEMMM);
|
||||
-- V_WRM2 = LCELL(V_WEMMN or V_WEMMM);
|
||||
-- V_WRM2 = LCELL(V_WEMMR);
|
||||
-- V_WRM = LCELL(V_WEMMM or V_WEMMN);
|
||||
-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN);
|
||||
|
||||
V_WEM = (V_WE);
|
||||
|
||||
-- V_WEM2 = LCELL(V_WE);
|
||||
-- V_WEM = LCELL(V_WEMMM & V_WEMMN);
|
||||
-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO);
|
||||
|
||||
--- LWR_COL = DFF(WR_COL,CLK42,,);
|
||||
F_WR = (LCELL(LCELL(LCELL(LCELL(DFF(VCC,V_WE,,))))));
|
||||
--- F_WR = DFF(V_WE,CLK42,,);
|
||||
V_WEMMZ = LCELL(CLK42);
|
||||
V_EN3 = (DFF(!(!VXA1 & LCELL(!VXA0 or DOUBLE)), V_WEMMZ, F_WR,));
|
||||
V_EN2 = (DFF(!(!VXA1 & LCELL(VXA0 or DOUBLE)), V_WEMMZ, F_WR,));
|
||||
V_EN1 = (DFF(!(VXA1 & LCELL(!VXA0 or DOUBLE)), V_WEMMZ, F_WR,));
|
||||
V_EN0 = (DFF(!(VXA1 & LCELL(VXA0 or DOUBLE)), V_WEMMZ, F_WR,));
|
||||
|
||||
|
||||
-- V_WR_3 = LCELL(V_WRM or V_EN3);
|
||||
-- V_WR_2 = LCELL(V_WRM or V_EN2);
|
||||
-- V_WR_1 = LCELL(V_WRM or V_EN1);
|
||||
-- V_WR_0 = LCELL(V_WRM or V_EN0);
|
||||
V_WR_3 = LCELL(LCELL(LCELL(LCELL(V_WE or V_EN3))));
|
||||
V_WR_2 = LCELL(LCELL(LCELL(LCELL(V_WE or V_EN2))));
|
||||
V_WR_1 = LCELL(LCELL(LCELL(LCELL(V_WE or V_EN1))));
|
||||
V_WR_0 = LCELL(LCELL(LCELL(LCELL(V_WE or V_EN0))));
|
||||
|
||||
V_WEY3 = LCELL(V_WE or V_EN3);
|
||||
V_WEY2 = LCELL(V_WE or V_EN2);
|
||||
V_WEY1 = LCELL(V_WE or V_EN1);
|
||||
V_WEY0 = LCELL(V_WE or V_EN0);
|
||||
|
||||
V_WR[] = V_WR_[]; -- V_WR0-3
|
||||
V_WEN[] = V_WEY[]; -- VD0-3
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
%
|
||||
V_WEMMM = LCELL(V_WE);
|
||||
V_WEMMN = LCELL(V_WEMMM);
|
||||
V_WEMMO = LCELL(V_WEMMN);
|
||||
V_WEMM = LCELL(V_WEMMO);
|
||||
|
||||
V_WRM = LCELL(V_WEMMN & V_WEMMM);
|
||||
V_WRM2 = LCELL(V_WEMMN & V_WEMMM);
|
||||
|
||||
V_WEM = LCELL(V_WEMMM & V_WEMMO);
|
||||
V_WEM2 = LCELL(V_WEMMM & V_WEMMO);
|
||||
|
||||
V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)),CLK42,F_WR,);
|
||||
V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
|
||||
F_WR = DFF(VCC,V_WE,,);
|
||||
|
||||
V_WR_3 = V_WRM or V_EN3;
|
||||
V_WR_2 = V_WRM2 or V_EN2;
|
||||
V_WR_1 = V_WRM or V_EN1;
|
||||
V_WR_0 = V_WRM or V_EN0;
|
||||
|
||||
V_WEY3 = V_WEM or V_EN3;
|
||||
V_WEY2 = V_WEM2 or V_EN2;
|
||||
V_WEY1 = V_WEM or V_EN1;
|
||||
V_WEY0 = V_WEM or V_EN0;
|
||||
|
||||
V_WR[] = V_WR_[];
|
||||
V_WEN[] = V_WEY[];
|
||||
%
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- CLK84 = LCELL(CLK42 xor CLK84_X);
|
||||
-- CLK84_X = DFF(!CLK84_X,CLK84,,);
|
||||
-- CLK84_Y = CLK84;
|
||||
|
||||
END GENERATE; -- end "sprinter" mode
|
||||
|
||||
|
||||
END;
|
||||
@ -1,783 +0,0 @@
|
||||
|
||||
TITLE "Video-controller";
|
||||
|
||||
INCLUDE "lpm_ram_dp";
|
||||
|
||||
PARAMETERS
|
||||
(
|
||||
MODE = "SPRINTER",
|
||||
MOUSE = "NO",
|
||||
HOR_PLACE = H"50",
|
||||
VER_PLACE = H"91" -- 122h/2
|
||||
);
|
||||
|
||||
SUBDESIGN video2
|
||||
(
|
||||
CLK42 : INPUT;
|
||||
|
||||
CT[5..0] : OUTPUT;
|
||||
CTH[5..0] : OUTPUT;
|
||||
CTV[8..0] : OUTPUT;
|
||||
CTF[6..0] : OUTPUT;
|
||||
|
||||
BLANK : OUTPUT;
|
||||
|
||||
START_UP : INPUT;
|
||||
COPY_SINC_H : INPUT;
|
||||
COPY_SINC_V : INPUT;
|
||||
|
||||
WR : INPUT;
|
||||
|
||||
VAI[19..0] : INPUT; -- input screen adress
|
||||
|
||||
VAO[15..0] : OUTPUT;
|
||||
|
||||
D[7..0] : INPUT;
|
||||
MDI[15..0] : INPUT;
|
||||
|
||||
VDO0[7..0] : OUTPUT;
|
||||
VDO1[7..0] : OUTPUT;
|
||||
VDO2[7..0] : OUTPUT;
|
||||
VDO3[7..0] : OUTPUT;
|
||||
|
||||
VDM0[7..0] : INPUT;
|
||||
VDM1[7..0] : INPUT;
|
||||
VDM2[7..0] : INPUT;
|
||||
VDM3[7..0] : INPUT;
|
||||
|
||||
V_WR[3..0] : OUTPUT;
|
||||
V_WEN[3..0] : OUTPUT;
|
||||
|
||||
V_CS[1..0] : OUTPUT;
|
||||
WR_PIX : OUTPUT;
|
||||
|
||||
-- ZX_COLOR[3..0] : OUTPUT;
|
||||
|
||||
ZX_PORT[7..0] : INPUT;
|
||||
DIR_PORT[7..0] : INPUT;
|
||||
|
||||
%
|
||||
bit0 - Spectrum SCREEN Switch
|
||||
bit1 - Spectrum Adress MODE
|
||||
bit2 - Write to Spectrum Screen OFF
|
||||
bit3 - MODE page 0/1
|
||||
bit4 - MODE on/off screen
|
||||
|
||||
bit7..5 - Border
|
||||
%
|
||||
|
||||
INTT : OUTPUT;
|
||||
|
||||
DOUBLE_CAS : INPUT;
|
||||
|
||||
MOUSE_X[9..0] : INPUT;
|
||||
MOUSE_Y[9..0] : INPUT;
|
||||
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
-- CLK84 : NODE;
|
||||
-- CLK84_X : NODE;
|
||||
-- CLK84_Y : NODE;
|
||||
|
||||
ZX_COLOR[3..0] : NODE;
|
||||
|
||||
CT[5..0] : DFFE;
|
||||
CTH[5..0] : DFFE;
|
||||
CTV[8..0] : DFFE;
|
||||
CTF[6..0] : DFF;
|
||||
|
||||
VXA[19..0] : DFFE;
|
||||
|
||||
VXD0[7..0] : DFFE;
|
||||
VXD1[7..0] : DFFE;
|
||||
VXD2[7..0] : DFFE;
|
||||
VXD3[7..0] : DFFE;
|
||||
|
||||
E_WR : NODE;
|
||||
E_WRD : NODE;
|
||||
|
||||
BLANK : NODE;
|
||||
BORD : NODE;
|
||||
-- INTT_T : NODE;
|
||||
INTTX : NODE;
|
||||
|
||||
VLA[17..0] : DFF;
|
||||
-- SVA[17..0] : NODE;
|
||||
SVA[17..0] : DFF;
|
||||
-- RSVA[8..0] : LCELL;
|
||||
RSVA[8..0] : NODE;
|
||||
-- RSVA[8..0] : DFF;
|
||||
|
||||
V_CST[1..0] : DFF;
|
||||
VCM[2..0] : DFF;
|
||||
TSN_W3 : DFF;
|
||||
V_WE : DFF;
|
||||
V_WEX : DFF;
|
||||
|
||||
V_WEM : NODE;
|
||||
V_WEM2 : NODE;
|
||||
V_WRM : NODE;
|
||||
V_WRM2 : NODE;
|
||||
%
|
||||
V_WEMM : NODE;
|
||||
V_WEMMM : NODE;
|
||||
V_WEMMN : NODE;
|
||||
V_WEMMO : NODE;
|
||||
%
|
||||
V_WEMM : NODE;
|
||||
V_WEMMM : NODE;
|
||||
V_WEMMN : NODE;
|
||||
V_WEMMO : NODE;
|
||||
V_WEMMP : NODE;
|
||||
V_WEMMQ : NODE;
|
||||
V_WEMMR : NODE;
|
||||
V_WEMMS : NODE;
|
||||
V_WEMMT : NODE;
|
||||
V_WEMMU : NODE;
|
||||
V_WEMMV : NODE;
|
||||
V_WEMMW : NODE;
|
||||
V_WEMMX : NODE;
|
||||
V_WEMMY : NODE;
|
||||
V_WEMMZ : NODE;
|
||||
|
||||
|
||||
|
||||
V_WET[3..0] : DFF;
|
||||
|
||||
D_PIC0[7..0] : DFFE;
|
||||
-- D_PIC0_[7..0] : LCELL;
|
||||
|
||||
D_PIC0_[7..0] : DFFE;
|
||||
D_PIC1_[7..0] : DFFE;
|
||||
D_PIC2_[7..0] : DFFE;
|
||||
D_PIC3_[7..0] : DFFE;
|
||||
|
||||
D_PICX_[7..0] : NODE;
|
||||
|
||||
LWR_PIC : NODE;
|
||||
LWR_COL : NODE;
|
||||
|
||||
WR_PIC : DFF;
|
||||
WR_COL : DFF;
|
||||
LD_PIC : NODE;
|
||||
MXL: NODE;
|
||||
MXR: NODE;
|
||||
|
||||
RBRVA[10..8]: DFF;
|
||||
BRVA[7..0] : DFF;
|
||||
DCOL[7..0] : DFFE;
|
||||
|
||||
MXWE : NODE;
|
||||
-- MXCE : NODE;
|
||||
|
||||
AX128 : NODE;
|
||||
|
||||
BRD[2..0] : NODE;
|
||||
|
||||
ZX_COL[3..0] : LCELL;
|
||||
|
||||
ZXA15 : NODE;
|
||||
ZXS[5..0] : NODE;
|
||||
ZX_SCREEN : NODE;
|
||||
SCR128 : NODE;
|
||||
|
||||
MODE0[7..0] : DFFE;
|
||||
MODE1[7..0] : DFFE;
|
||||
MODE2[7..0] : DFFE;
|
||||
-- MODE3[7..0] : DFF;
|
||||
|
||||
WR_MODE : DFF;
|
||||
LWR_MODE : NODE;
|
||||
X_MODE[7..4]: NODE;
|
||||
X_MODE_BOND : NODE;
|
||||
|
||||
-- M_CTV[2..0] : DFF;
|
||||
-- M_CT[5..3] : DFF;
|
||||
M_CTV[2..0] : LCELL;
|
||||
M_CT[5..3] : LCELL;
|
||||
|
||||
DOUBLE : DFFE;
|
||||
|
||||
PIC_CLK : NODE;
|
||||
|
||||
MS_X[9..0] : DFF;
|
||||
MS_Y[9..0] : DFF;
|
||||
|
||||
MS_POINT : NODE;
|
||||
MS_POINT2 : NODE;
|
||||
MS_PNT : NODE;
|
||||
|
||||
MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF");
|
||||
|
||||
SCR_ENA : DFFE;
|
||||
V_WR_[3..0] : LCELL;
|
||||
V_WEY[3..0] : LCELL;
|
||||
|
||||
V_WE_R : NODE;
|
||||
|
||||
V_CSX[3..0] : NODE;
|
||||
|
||||
V_EN[3..0] : NODE;
|
||||
|
||||
F_WR : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
DEFAULTS
|
||||
WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC;
|
||||
V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC;
|
||||
V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC;
|
||||
V_WET[].d = VCC;
|
||||
END DEFAULTS;
|
||||
|
||||
ZX_COLOR[] = ZX_COL[];
|
||||
|
||||
-- === MOUSE counters ========
|
||||
|
||||
MS_X[].clk = !CT1;
|
||||
CASE LCELL(CTH[5..2] == 12) IS
|
||||
WHEN 0 => MS_X[] = MS_X[] + 1;
|
||||
WHEN 1 => MS_X[] = (!MOUSE_X[9..0]);
|
||||
END CASE;
|
||||
|
||||
MS_Y[].clk = !CTH5;
|
||||
CASE LCELL(CTV8 & !CTV5 & CTV4) IS
|
||||
WHEN 0 => MS_Y[] = MS_Y[] + 1;
|
||||
WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]);
|
||||
END CASE;
|
||||
|
||||
MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,);
|
||||
|
||||
MS_DAT.wren = GND;
|
||||
MS_DAT.data[] = GND;
|
||||
MS_DAT.wraddress[] = GND;
|
||||
MS_DAT.wrclock = CLK42;
|
||||
MS_DAT.wrclken = GND;
|
||||
MS_DAT.rden = VCC;
|
||||
MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]);
|
||||
MS_DAT.rdclock = CLK42;
|
||||
MS_DAT.rdclken = VCC;
|
||||
|
||||
IF MOUSE == "NO" GENERATE
|
||||
MS_POINT = GND;
|
||||
MS_POINT2 = GND;
|
||||
ELSE GENERATE
|
||||
MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,);
|
||||
MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,);
|
||||
END GENERATE;
|
||||
|
||||
-- === Sinc-counts GENERATOR ============================================
|
||||
|
||||
-- CT[].clrn = START_UP;
|
||||
|
||||
-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE;
|
||||
-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE;
|
||||
|
||||
-- CTV[].clrn = !COPY_SINC_V or VER_PLACE;
|
||||
-- CTV[].prn = !COPY_SINC_V or !VER_PLACE;
|
||||
|
||||
CT[5].clrn = !COPY_SINC_H;
|
||||
|
||||
-- set CTH to 50 (32h)
|
||||
CTH[0].clrn = !COPY_SINC_H;
|
||||
CTH[1].prn = !COPY_SINC_H;
|
||||
CTH[2].clrn = !COPY_SINC_H;
|
||||
CTH[3].clrn = !COPY_SINC_H;
|
||||
CTH[4].prn = !COPY_SINC_H;
|
||||
CTH[5].prn = !COPY_SINC_H;
|
||||
|
||||
-- set CTV to 122h
|
||||
CTV[0].clrn = !COPY_SINC_V;
|
||||
CTV[1].prn = !COPY_SINC_V;
|
||||
CTV[3..2].clrn = !COPY_SINC_V;
|
||||
|
||||
CTV[4].clrn = !COPY_SINC_V;
|
||||
CTV[5].prn = !COPY_SINC_V;
|
||||
CTV[7..6].clrn = !COPY_SINC_V;
|
||||
CTV[8].prn = !COPY_SINC_V;
|
||||
|
||||
CT[5..0].clk = CLK42;
|
||||
CTH[5..0].clk = CLK42;
|
||||
CTV[8..0].clk = CLK42;
|
||||
|
||||
CT[2..0].ena = VCC;
|
||||
|
||||
CASE CT[2..0] IS
|
||||
WHEN 0 => CT[2..0] = 1;
|
||||
WHEN 1 => CT[2..0] = 2;
|
||||
WHEN 2 => CT[2..0] = 4;
|
||||
WHEN 3 => CT[2..0] = 4;
|
||||
WHEN 4 => CT[2..0] = 5;
|
||||
WHEN 5 => CT[2..0] = 6;
|
||||
WHEN 6 => CT[2..0] = 0;
|
||||
WHEN 7 => CT[2..0] = 0;
|
||||
END CASE;
|
||||
|
||||
-- for remove sinc jitter
|
||||
-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,);
|
||||
CT[5..3].ena = DFF((CT0 & CT2),CLK42,,);
|
||||
CT[5..3] = CT[5..3]+1;
|
||||
%
|
||||
CASE CT[4..3] IS
|
||||
WHEN 0 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 1 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 2 => CT[5..3] = CT[5..3]+1;
|
||||
WHEN 3 => CT[5..3] = CT[5..3]+1;
|
||||
END CASE;
|
||||
%
|
||||
CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,);
|
||||
CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,);
|
||||
|
||||
IF CTH[] == 55 THEN
|
||||
CTH[] = GND;
|
||||
ELSE
|
||||
CTH[] = CTH[] + 1;
|
||||
END IF;
|
||||
|
||||
IF CTV[] == 319 THEN
|
||||
CTV[] = GND;
|
||||
ELSE
|
||||
CTV[] = CTV[] + 1;
|
||||
END IF;
|
||||
|
||||
CTF[].clk = CTV8;
|
||||
CTF[] = CTF[]+1;
|
||||
|
||||
-- ==== Video ==========================================================
|
||||
|
||||
ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens
|
||||
ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write
|
||||
ZXA15 = ZX_PORT7; -- ZX A15' line
|
||||
|
||||
SCR128 = DIR_PORT0;
|
||||
|
||||
-- WR_PIX = LCELL(TSN_W3);
|
||||
WR_PIX = TSN_W3;
|
||||
|
||||
DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS;
|
||||
VXA[].clk = CLK42; VXA[].ena = !E_WR;
|
||||
|
||||
VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[];
|
||||
VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[];
|
||||
VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[];
|
||||
VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[];
|
||||
|
||||
-- VXD0[] = D[];
|
||||
-- VXD1[] = D[];
|
||||
-- VXD2[] = D[];
|
||||
-- VXD3[] = D[];
|
||||
|
||||
(VXD0[],VXD1[]) = MDI[];
|
||||
(VXD2[],VXD3[]) = MDI[];
|
||||
|
||||
BRD[] = DIR_PORT[7..5];
|
||||
|
||||
VCM[].clk = CLK42;
|
||||
TSN_W3.clk = CLK42;
|
||||
V_CST[].clk = CLK42;
|
||||
V_WE.clk = CLK42;
|
||||
V_WET[].clk = CLK42;
|
||||
VLA[].clk = CLK42;
|
||||
|
||||
SCR_ENA.clk = CLK42;
|
||||
SCR_ENA.ena = !E_WR;
|
||||
SCR_ENA.d = !(VAI19 or ZX_SCREEN);
|
||||
|
||||
E_WRD = DFF(E_WR,CLK42,,);
|
||||
E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,));
|
||||
-- E_WR = LCELL(WR or !DFF(WR,CLK42,,));
|
||||
|
||||
-- ****************************************************
|
||||
|
||||
IF MODE == "SPRINTER" GENERATE
|
||||
|
||||
-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode
|
||||
|
||||
-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE);
|
||||
MXWE = DFF(MXWE,CLK42,E_WR,V_WE);
|
||||
|
||||
IF VAI[19] THEN
|
||||
-- in graf mode all 256k(512k) range
|
||||
VXA[] = VAI[];
|
||||
ELSE
|
||||
-- in spectrum mode 8k/16k range pages
|
||||
VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]);
|
||||
END IF;
|
||||
|
||||
-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,);
|
||||
-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,);
|
||||
-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,);
|
||||
|
||||
BORD = DFF((MODE0[7..4] == 15),LWR_COL,,);
|
||||
BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,);
|
||||
INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,);
|
||||
|
||||
INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,);
|
||||
|
||||
-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,);
|
||||
-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]);
|
||||
|
||||
CASE CT[2..0] IS
|
||||
WHEN B"110" => VCM[2..0].d = 5; -- 110 -> 101 6 -> 5
|
||||
WHEN B"000" => VCM[2..0].d = 1; -- 000 -> 001 0 -> 1
|
||||
WHEN B"001" => VCM[2..0].d = 4; -- 001 -> 100 1 -> 4
|
||||
WHEN B"010" => VCM[2..0].d = 3; -- 010 -> 011 2 -> 3
|
||||
WHEN B"100" => VCM[2..0].d = 2; -- 100 -> 010 4 -> 2
|
||||
WHEN B"101" => VCM[2..0].d = 0; -- 101 -> 000 5 -> 0
|
||||
END CASE;
|
||||
|
||||
CASE VCM[1..0] IS
|
||||
WHEN 0 =>
|
||||
VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
%
|
||||
IF VCM2 THEN
|
||||
-- TSN_W3.d = X_MODE5;
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE5);
|
||||
ELSE
|
||||
TSN_W3.d = X_MODE_BOND;
|
||||
-- V_CST[].d = (VCC,X_MODE_BOND);
|
||||
END IF;
|
||||
%
|
||||
|
||||
WHEN 1 =>
|
||||
WR_PIC.d = !VCM2;
|
||||
WR_COL.d = VCM2;
|
||||
VLA[].d = SVA[];
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
WHEN 2 =>
|
||||
VLA[].d = VXA[17..0];
|
||||
V_CST[].d = (!VXA18,VXA18) or MXWE;
|
||||
V_WE.d = MXWE;
|
||||
V_WEX.d = GND;
|
||||
V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
WHEN 3 =>
|
||||
-- WR_PIC.d = X_MODE5;
|
||||
-- NEW 26.08.2022, fix bug with first column
|
||||
-- it was reproducing when changes mode 320 -> 640, like any 320px screen squares -> text mode squares
|
||||
WR_PIC.d = MODE0[5];
|
||||
VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND);
|
||||
WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]);
|
||||
V_CST[].d = (VCC,GND);
|
||||
V_WE.d = VCC;
|
||||
V_WEX.d = VCC;
|
||||
END CASE;
|
||||
|
||||
-- choose V-RAM komplect
|
||||
|
||||
V_CST1.prn = GND;
|
||||
-- V_CS0.clrn = GND;
|
||||
V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0)));
|
||||
V_CS1 = VCC;
|
||||
-- V_CS0 = LCELL(V_CST0);
|
||||
|
||||
V_CSX0 = LCELL(!CLK42);
|
||||
V_CSX1 = LCELL(V_CSX0);
|
||||
V_CSX2 = LCELL(V_CSX1 & V_CSX0);
|
||||
V_CSX3 = LCELL(V_CSX2);
|
||||
|
||||
-- V_CS0 = V_CSX3;
|
||||
V_CS0 = GND;
|
||||
|
||||
-- =====================
|
||||
|
||||
SVA[].clk = CLK42;
|
||||
SVA[9..6] = MODE0[3..0];
|
||||
-- RSVA[].clk = CLK42;
|
||||
(SVA[12..10],SVA[5..0]) = RSVA[];
|
||||
|
||||
-- M_CTV[2..0].clk = CLK42;
|
||||
-- M_CT[5..3].clk = CLK42;
|
||||
M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]);
|
||||
M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]);
|
||||
|
||||
CASE (!VCM2,MODE0[4]) IS
|
||||
-- CASE (!VCM1,MODE0[4]) IS
|
||||
WHEN B"X0" =>
|
||||
-- Graf adress --
|
||||
RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = CTV[2..0];
|
||||
-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]);
|
||||
WHEN B"01" =>
|
||||
-- ZX-atr adress --
|
||||
RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
SVA[17..13] = MODE2[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE2[2..0];
|
||||
-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]);
|
||||
WHEN B"11" =>
|
||||
-- ZX-pic adress --
|
||||
RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
SVA[17..13] = MODE1[7..3];
|
||||
|
||||
-- SVA[12..10] = MODE1[2..0];
|
||||
-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0);
|
||||
END CASE;
|
||||
|
||||
-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC));
|
||||
X_MODE_BOND = GND;
|
||||
|
||||
-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,)));
|
||||
|
||||
|
||||
-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS
|
||||
|
||||
-- D_PIC0_[].clk = !CLK42;
|
||||
-- D_PIC1_[].clk = !CLK42;
|
||||
-- D_PIC2_[].clk = !CLK42;
|
||||
-- D_PIC3_[].clk = !CLK42;
|
||||
|
||||
-- PIC_CLK = LCELL(LCELL(CLK42));
|
||||
PIC_CLK = !CLK42;
|
||||
|
||||
D_PIC0_[].clk = PIC_CLK;
|
||||
D_PIC1_[].clk = PIC_CLK;
|
||||
D_PIC2_[].clk = PIC_CLK;
|
||||
D_PIC3_[].clk = PIC_CLK;
|
||||
|
||||
D_PIC0_[] = VDM0[];
|
||||
D_PIC1_[] = VDM1[];
|
||||
D_PIC2_[] = VDM2[];
|
||||
D_PIC3_[] = VDM3[];
|
||||
|
||||
CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS
|
||||
WHEN 0 => D_PICX_[] = D_PIC0_[];
|
||||
WHEN 1 => D_PICX_[] = D_PIC1_[];
|
||||
WHEN 2 => D_PICX_[] = D_PIC2_[];
|
||||
WHEN 3 => D_PICX_[] = D_PIC3_[];
|
||||
END CASE;
|
||||
|
||||
MODE0[].ena = VCC;
|
||||
MODE1[].ena = VCC;
|
||||
MODE2[].ena = VCC;
|
||||
MODE0[].clk = LWR_MODE;
|
||||
MODE1[].clk = LWR_MODE;
|
||||
MODE2[].clk = LWR_MODE;
|
||||
MODE0[].d = VDM3[];
|
||||
MODE1[].d = VDM2[];
|
||||
MODE2[].d = VDM1[];
|
||||
LWR_MODE = LCELL(LCELL(WR_MODE));
|
||||
%
|
||||
MODE0[].ena = LWR_MODE;
|
||||
MODE1[].ena = LWR_MODE;
|
||||
MODE2[].ena = LWR_MODE;
|
||||
MODE0[].clk = CLK42;
|
||||
MODE1[].clk = CLK42;
|
||||
MODE2[].clk = CLK42;
|
||||
MODE0[].d = D_PIC3_[];
|
||||
MODE1[].d = D_PIC2_[];
|
||||
MODE2[].d = D_PIC1_[];
|
||||
LWR_MODE = DFF(!WR_MODE,CLK42,,);
|
||||
%
|
||||
X_MODE7 = DFF(MODE0[7],LWR_COL,,);
|
||||
X_MODE6 = DFF(MODE0[6],LWR_COL,,);
|
||||
X_MODE5 = DFF(MODE0[5],LWR_COL,,);
|
||||
X_MODE4 = DFF(MODE0[4],LWR_COL,,);
|
||||
|
||||
VAO[] = VLA[17..2];
|
||||
|
||||
WR_PIC.clk = CLK42;
|
||||
WR_COL.clk = CLK42;
|
||||
WR_MODE.clk = CLK42;
|
||||
|
||||
-- LWR_PIC = LCELL(LCELL(WR_PIC));
|
||||
-- LWR_COL = LCELL(LCELL(WR_COL));
|
||||
-- LWR_PIC = LCELL(WR_PIC);
|
||||
-- LWR_COL = LCELL(WR_COL);
|
||||
LWR_PIC = DFF(WR_PIC,CLK42,,);
|
||||
LWR_COL = DFF(WR_COL,CLK42,,);
|
||||
|
||||
-- D_PIC0[].ena = VCC;
|
||||
-- D_PIC0[].clk = (LWR_PIC);
|
||||
D_PIC0[].ena = !LWR_PIC;
|
||||
D_PIC0[].clk = CLK42;
|
||||
|
||||
|
||||
|
||||
|
||||
IF LD_PIC THEN
|
||||
-- D_PIC0[] = D_PIC0_[];
|
||||
D_PIC0[] = D_PICX_[];
|
||||
ELSE
|
||||
D_PIC0[] = (D_PIC0[6..0],GND);
|
||||
END IF;
|
||||
|
||||
|
||||
-- DCOL[].clk = (LWR_COL);
|
||||
DCOL[].ena = !LWR_COL;
|
||||
DCOL[].clk = CLK42;
|
||||
|
||||
IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN
|
||||
DCOL[].d = (B"00",BRD[2..0],BRD[2..0]);
|
||||
ELSE
|
||||
-- DCOL[].d = D_PIC0_[];
|
||||
DCOL[].d = D_PICX_[];
|
||||
END IF;
|
||||
|
||||
DCOL[].clrn = !BLANK;
|
||||
|
||||
BRVA[].clk = CLK42;
|
||||
BRVA[].clrn = !MS_POINT;
|
||||
BRVA[].prn = !MS_POINT2;
|
||||
|
||||
-- MODE0[4] - graph / text
|
||||
-- MODE0[5] - 320 / 640 resolution
|
||||
|
||||
-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS
|
||||
CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS
|
||||
WHEN B"1X" => BRVA[7..0] = DCOL[];
|
||||
WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]);
|
||||
WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]);
|
||||
END CASE;
|
||||
|
||||
-- BRVA[10..8] = (x_mode4,RBRVA[9..8]);
|
||||
RBRVA[].clk = CLK42;
|
||||
|
||||
CASE (BORD,X_MODE4) IS
|
||||
WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]);
|
||||
WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]);
|
||||
END CASE;
|
||||
|
||||
RBRVA[9..8].clrn = !BORD;
|
||||
RBRVA[10].prn = !BORD;
|
||||
|
||||
CASE (RBRVA[9..8],BRVA7) IS
|
||||
WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]);
|
||||
WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]);
|
||||
END CASE;
|
||||
|
||||
-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE));
|
||||
|
||||
V_WE_R = DFF(GND,!CLK42,,!V_WE);
|
||||
V_WE.prn = V_WE_R;
|
||||
V_WET[].prn = V_WE_R;
|
||||
|
||||
-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0));
|
||||
|
||||
-- V_WR[] = (V_WE) or !(
|
||||
|
||||
V_WEX.clk = CLK42;
|
||||
-- V_WEX.d = V_WE;
|
||||
-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX));
|
||||
|
||||
|
||||
|
||||
|
||||
V_WEMMM = LCELL(V_WE);
|
||||
-- V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok
|
||||
-- V_WEMMO = LCELL(V_WEMMN); -- green arts
|
||||
-- V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts
|
||||
-- V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??)
|
||||
-- V_WEMMS = LCELL(V_WEMMR);
|
||||
-- V_WEMMT = LCELL(V_WEMMS);
|
||||
-- V_WEMMU = LCELL(V_WEMMT);
|
||||
-- V_WEMMV = LCELL(V_WEMMU);
|
||||
-- V_WEMMW = LCELL(V_WEMMV);
|
||||
-- V_WEMMX = LCELL(V_WEMMW);
|
||||
-- V_WEMMY = LCELL(V_WEMMX);
|
||||
-- V_WEMMZ = LCELL(V_WEMMY);
|
||||
|
||||
V_WRM = LCELL(V_WE or V_WEMMM);
|
||||
|
||||
|
||||
-- V_WRM = LCELL(V_WEMMN or V_WEMMM);
|
||||
-- V_WRM2 = LCELL(V_WEMMN or V_WEMMM);
|
||||
-- V_WRM2 = LCELL(V_WEMMR);
|
||||
-- V_WRM = LCELL(V_WEMMM or V_WEMMN);
|
||||
-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN);
|
||||
|
||||
V_WEM = (V_WE);
|
||||
|
||||
-- V_WEM2 = LCELL(V_WE);
|
||||
-- V_WEM = LCELL(V_WEMMM & V_WEMMN);
|
||||
-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO);
|
||||
|
||||
--- LWR_COL = DFF(WR_COL,CLK42,,);
|
||||
F_WR = ((LCELL(LCELL(LCELL(DFF(VCC,V_WE,,))))));
|
||||
--- F_WR = DFF(V_WE,CLK42,,);
|
||||
-- V_WEMMZ = LCELL(CLK42);
|
||||
V_EN3 = (DFF(!(!VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,));
|
||||
V_EN2 = (DFF(!(!VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,));
|
||||
V_EN1 = (DFF(!(VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,));
|
||||
V_EN0 = (DFF(!(VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,));
|
||||
|
||||
|
||||
-- V_WR_3 = LCELL(V_WRM or V_EN3);
|
||||
-- V_WR_2 = LCELL(V_WRM or V_EN2);
|
||||
-- V_WR_1 = LCELL(V_WRM or V_EN1);
|
||||
-- V_WR_0 = LCELL(V_WRM or V_EN0);
|
||||
V_WR_3 = (LCELL(LCELL(LCELL(V_WRM or V_EN3))));
|
||||
V_WR_2 = (LCELL(LCELL(LCELL(V_WRM or V_EN2))));
|
||||
V_WR_1 = (LCELL(LCELL(LCELL(V_WRM or V_EN1))));
|
||||
V_WR_0 = (LCELL(LCELL(LCELL(V_WRM or V_EN0))));
|
||||
|
||||
V_WEY3 = LCELL(V_WE or V_EN3);
|
||||
V_WEY2 = LCELL(V_WE or V_EN2);
|
||||
V_WEY1 = LCELL(V_WE or V_EN1);
|
||||
V_WEY0 = LCELL(V_WE or V_EN0);
|
||||
|
||||
V_WR[] = V_WR_[]; -- V_WR0-3
|
||||
V_WEN[] = V_WEY[]; -- VD0-3
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
%
|
||||
V_WEMMM = LCELL(V_WE);
|
||||
V_WEMMN = LCELL(V_WEMMM);
|
||||
V_WEMMO = LCELL(V_WEMMN);
|
||||
V_WEMM = LCELL(V_WEMMO);
|
||||
|
||||
V_WRM = LCELL(V_WEMMN & V_WEMMM);
|
||||
V_WRM2 = LCELL(V_WEMMN & V_WEMMM);
|
||||
|
||||
V_WEM = LCELL(V_WEMMM & V_WEMMO);
|
||||
V_WEM2 = LCELL(V_WEMMM & V_WEMMO);
|
||||
|
||||
V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)),CLK42,F_WR,);
|
||||
V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,);
|
||||
|
||||
F_WR = DFF(VCC,V_WE,,);
|
||||
|
||||
V_WR_3 = V_WRM or V_EN3;
|
||||
V_WR_2 = V_WRM2 or V_EN2;
|
||||
V_WR_1 = V_WRM or V_EN1;
|
||||
V_WR_0 = V_WRM or V_EN0;
|
||||
|
||||
V_WEY3 = V_WEM or V_EN3;
|
||||
V_WEY2 = V_WEM2 or V_EN2;
|
||||
V_WEY1 = V_WEM or V_EN1;
|
||||
V_WEY0 = V_WEM or V_EN0;
|
||||
|
||||
V_WR[] = V_WR_[];
|
||||
V_WEN[] = V_WEY[];
|
||||
%
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- CLK84 = LCELL(CLK42 xor CLK84_X);
|
||||
-- CLK84_X = DFF(!CLK84_X,CLK84,,);
|
||||
-- CLK84_Y = CLK84;
|
||||
|
||||
END GENERATE; -- end "sprinter" mode
|
||||
|
||||
|
||||
END;
|
||||
@ -1,5 +0,0 @@
|
||||
C:
|
||||
cd "C:\users\tolik\Documents\SP_Projects\ASM\GIT\SP_Core\Build\acex\tmp\"
|
||||
"C:\Program Files (x86)\MAXPLUS2\MAXPLUS2.EXE" -compile SP2_ACEX >> compile.log
|
||||
transttf.exe SP2_ACEX.ttf ..\STREAM.BIN
|
||||
exit
|
||||
@ -1,10 +0,0 @@
|
||||
@echo off
|
||||
|
||||
cd acex
|
||||
call make.cmd
|
||||
|
||||
cd ..\max
|
||||
call make.cmd
|
||||
|
||||
cd ..
|
||||
|
||||
@ -1,653 +0,0 @@
|
||||
--
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
--
|
||||
CHIP SP2_MAX
|
||||
BEGIN
|
||||
DEVICE = EPM7064STC100-10;
|
||||
|GND65 : INPUT_PIN = 65;
|
||||
|GND33 : INPUT_PIN = 33;
|
||||
|/CONF_X : BIDIR_PIN = 54;
|
||||
|10K_D0 : OUTPUT_PIN = 58;
|
||||
|CLKZZ : BIDIR_PIN = 32;
|
||||
|10K_CLK : OUTPUT_PIN = 56;
|
||||
|XHD2_CS2 : OUTPUT_PIN = 83;
|
||||
|XHD2_CS1 : OUTPUT_PIN = 81;
|
||||
|XHD1_CS2 : OUTPUT_PIN = 80;
|
||||
|XHD1_CS1 : OUTPUT_PIN = 79;
|
||||
|XHD_WR : OUTPUT_PIN = 75;
|
||||
|XHD_RES : OUTPUT_PIN = 71;
|
||||
|XHD_RD : OUTPUT_PIN = 76;
|
||||
|WR_PDOS : OUTPUT_PIN = 8;
|
||||
|/WG_WR : OUTPUT_PIN = 93;
|
||||
|/WG_RD : OUTPUT_PIN = 97;
|
||||
|WDAT : OUTPUT_PIN = 98;
|
||||
|TG42_OUT : OUTPUT_PIN = 85;
|
||||
|TG42_BUF : OUTPUT_PIN = 36;
|
||||
|SINC_2 : OUTPUT_PIN = 19;
|
||||
|SINC_1 : OUTPUT_PIN = 20;
|
||||
|SINC_V : OUTPUT_PIN = 64;
|
||||
|SINC_H : OUTPUT_PIN = 68;
|
||||
|SINC : OUTPUT_PIN = 67;
|
||||
|QDAT : OUTPUT_PIN = 16;
|
||||
|HD_DIR : OUTPUT_PIN = 48;
|
||||
|HD_CS : OUTPUT_PIN = 52;
|
||||
|FDAT : OUTPUT_PIN = 14;
|
||||
|DENS_X : OUTPUT_PIN = 96;
|
||||
|CMOS_DWR : OUTPUT_PIN = 100;
|
||||
|CMOS_DRD : OUTPUT_PIN = 99;
|
||||
|CMOS_AS : OUTPUT_PIN = 6;
|
||||
|CLK14 : OUTPUT_PIN = 31;
|
||||
|CLK_WG : OUTPUT_PIN = 13;
|
||||
|BEEP : OUTPUT_PIN = 84;
|
||||
|AUD : OUTPUT_PIN = 35;
|
||||
|XHR_RDY : INPUT_PIN = 88;
|
||||
|XA2 : INPUT_PIN = 23;
|
||||
|XA1 : INPUT_PIN = 21;
|
||||
|XA0 : INPUT_PIN = 17;
|
||||
|XACS : INPUT_PIN = 37;
|
||||
|WSTB : INPUT_PIN = 10;
|
||||
|WR_CNF : INPUT_PIN = 57;
|
||||
|WD : INPUT_PIN = 9;
|
||||
|VGA_IN : INPUT_PIN = 61;
|
||||
|TR43 : INPUT_PIN = 12;
|
||||
|TG42_IN : INPUT_PIN = 87;
|
||||
|STE : INPUT_PIN = 94;
|
||||
|SR : INPUT_PIN = 29;
|
||||
|SL : INPUT_PIN = 30;
|
||||
|SINC_IN : INPUT_PIN = 69;
|
||||
|RSTB : INPUT_PIN = 25;
|
||||
|RDAT : INPUT_PIN = 92;
|
||||
|PW_GOOD : INPUT_PIN = 90;
|
||||
|HDD_C3 : INPUT_PIN = 40;
|
||||
|HDD_C2 : INPUT_PIN = 41;
|
||||
|HDD_C1 : INPUT_PIN = 42;
|
||||
|HDD_C0 : INPUT_PIN = 47;
|
||||
|FDD_C2 : INPUT_PIN = 46;
|
||||
|FDD_C1 : INPUT_PIN = 45;
|
||||
|FDD_C0 : INPUT_PIN = 44;
|
||||
|EPM_RES : INPUT_PIN = 89;
|
||||
|D0 : INPUT_PIN = 60;
|
||||
END;
|
||||
|
||||
DEFAULT_DEVICES
|
||||
BEGIN
|
||||
AUTO_DEVICE = EPM7256SQC208-7;
|
||||
AUTO_DEVICE = EPM7256SRC208-7;
|
||||
AUTO_DEVICE = EPM7192SQC160-7;
|
||||
AUTO_DEVICE = EPM7160SQC160-6;
|
||||
AUTO_DEVICE = EPM7160STC100-6;
|
||||
AUTO_DEVICE = EPM7160SLC84-6;
|
||||
AUTO_DEVICE = EPM7128SQC160-6;
|
||||
AUTO_DEVICE = EPM7128STC100-6;
|
||||
AUTO_DEVICE = EPM7128SQC100-6;
|
||||
AUTO_DEVICE = EPM7128SLC84-6;
|
||||
AUTO_DEVICE = EPM7064STC100-5;
|
||||
AUTO_DEVICE = EPM7064SLC84-5;
|
||||
AUTO_DEVICE = EPM7064STC44-5;
|
||||
AUTO_DEVICE = EPM7064SLC44-5;
|
||||
AUTO_DEVICE = EPM7032STC44-5;
|
||||
AUTO_DEVICE = EPM7032SLC44-5;
|
||||
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
|
||||
END;
|
||||
|
||||
TIMING_POINT
|
||||
BEGIN
|
||||
DEVICE_FOR_TIMING_SYNTHESIS = EPM7064STC100-10;
|
||||
FREQUENCY = 100MHz;
|
||||
MAINTAIN_STABLE_SYNTHESIS = OFF;
|
||||
CUT_ALL_CLEAR_PRESET = ON;
|
||||
CUT_ALL_BIDIR = ON;
|
||||
END;
|
||||
|
||||
IGNORED_ASSIGNMENTS
|
||||
BEGIN
|
||||
FIT_IGNORE_TIMING = ON;
|
||||
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
|
||||
IGNORE_DEVICE_ASSIGNMENTS = OFF;
|
||||
IGNORE_LC_ASSIGNMENTS = OFF;
|
||||
IGNORE_PIN_ASSIGNMENTS = OFF;
|
||||
IGNORE_CHIP_ASSIGNMENTS = OFF;
|
||||
IGNORE_TIMING_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
|
||||
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
|
||||
END;
|
||||
|
||||
LOGIC_OPTIONS
|
||||
BEGIN
|
||||
|LR_T1 : TURBO_BIT = ON;
|
||||
|LR_T0 : TURBO_BIT = ON;
|
||||
|CLK_WG : TURBO_BIT = ON;
|
||||
|TG42_BUF : STYLE = WYSIWYG;
|
||||
|TG42_OUT : STYLE = WYSIWYG;
|
||||
|XHD_RD : TURBO_BIT = OFF;
|
||||
|XHD_RES : TURBO_BIT = OFF;
|
||||
|XHD_WR : TURBO_BIT = OFF;
|
||||
|XHD1_CS1 : TURBO_BIT = OFF;
|
||||
|XHD1_CS2 : TURBO_BIT = OFF;
|
||||
|XHD2_CS1 : TURBO_BIT = OFF;
|
||||
|XHD2_CS2 : TURBO_BIT = OFF;
|
||||
|10K_CLK : TURBO_BIT = OFF;
|
||||
|10K_D0 : TURBO_BIT = OFF;
|
||||
|REG_P0 : TURBO_BIT = ON;
|
||||
|REG_P1 : TURBO_BIT = ON;
|
||||
|REG_P2 : TURBO_BIT = ON;
|
||||
|TG42_BUF : TURBO_BIT = ON;
|
||||
|TG42_OUT : TURBO_BIT = ON;
|
||||
|STWG0 : TURBO_BIT = ON;
|
||||
|STWG1 : TURBO_BIT = ON;
|
||||
|STWG2 : TURBO_BIT = ON;
|
||||
|XCT0 : TURBO_BIT = ON;
|
||||
|XCT1 : TURBO_BIT = ON;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_DEVICE_OPTIONS
|
||||
BEGIN
|
||||
MULTIVOLT_IO = OFF;
|
||||
SECURITY_BIT = ON;
|
||||
MAX7000B_ENABLE_VREFB = OFF;
|
||||
MAX7000B_ENABLE_VREFA = OFF;
|
||||
MAX7000B_VCCIO_IOBANK2 = 3.3V;
|
||||
MAX7000B_VCCIO_IOBANK1 = 3.3V;
|
||||
CONFIG_EPROM_PULLUP_RESISTOR = ON;
|
||||
CONFIG_EPROM_USER_CODE = FFFFFFFF;
|
||||
FLEX_CONFIGURATION_EPROM = AUTO;
|
||||
MAX7000AE_ENABLE_JTAG = ON;
|
||||
MAX7000AE_USER_CODE = FFFFFFFF;
|
||||
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
|
||||
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX6000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
|
||||
MAX7000S_ENABLE_JTAG = ON;
|
||||
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
|
||||
MAX7000S_USER_CODE = FFFF;
|
||||
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
|
||||
FLEX10K_JTAG_USER_CODE = 7F;
|
||||
ENABLE_INIT_DONE_OUTPUT = OFF;
|
||||
ENABLE_CHIP_WIDE_OE = OFF;
|
||||
ENABLE_CHIP_WIDE_RESET = OFF;
|
||||
nCEO = UNRESERVED;
|
||||
CLKUSR = UNRESERVED;
|
||||
ADD17 = UNRESERVED;
|
||||
ADD16 = UNRESERVED;
|
||||
ADD15 = UNRESERVED;
|
||||
ADD14 = UNRESERVED;
|
||||
ADD13 = UNRESERVED;
|
||||
ADD0_TO_ADD12 = UNRESERVED;
|
||||
SDOUT = RESERVED_DRIVES_OUT;
|
||||
RDCLK = UNRESERVED;
|
||||
RDYnBUSY = UNRESERVED;
|
||||
nWS_nRS_nCS_CS = UNRESERVED;
|
||||
DATA1_TO_DATA7 = UNRESERVED;
|
||||
DATA0 = RESERVED_TRI_STATED;
|
||||
FLEX8000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME = ACTIVE_SERIAL;
|
||||
DISABLE_TIME_OUT = OFF;
|
||||
ENABLE_DCLK_OUTPUT = OFF;
|
||||
RELEASE_CLEARS = OFF;
|
||||
AUTO_RESTART = OFF;
|
||||
USER_CLOCK = OFF;
|
||||
RESERVED_PINS_PERCENT = 0;
|
||||
RESERVED_LCELLS_PERCENT = 0;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
|
||||
BEGIN
|
||||
STYLE = NORMAL;
|
||||
AUTO_GLOBAL_CLEAR = OFF;
|
||||
AUTO_GLOBAL_CLOCK = OFF;
|
||||
DEVICE_FAMILY = MAX7000S;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
|
||||
AUTO_IMPLEMENT_IN_EAB = OFF;
|
||||
AUTO_OPEN_DRAIN_PINS = ON;
|
||||
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
|
||||
AUTO_REGISTER_PACKING = OFF;
|
||||
AUTO_FAST_IO = OFF;
|
||||
AUTO_GLOBAL_OE = ON;
|
||||
AUTO_GLOBAL_PRESET = ON;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
|
||||
OPTIMIZE_FOR_SPEED = 5;
|
||||
END;
|
||||
|
||||
COMPILER_PROCESSING_CONFIGURATION
|
||||
BEGIN
|
||||
FITTER_SETTINGS = ADVANCED;
|
||||
USE_QUARTUS_FITTER = OFF;
|
||||
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
|
||||
SMART_RECOMPILE = OFF;
|
||||
GENERATE_AHDL_TDO_FILE = OFF;
|
||||
RPT_FILE_USER_ASSIGNMENTS = ON;
|
||||
RPT_FILE_LCELL_INTERCONNECT = ON;
|
||||
RPT_FILE_HIERARCHY = ON;
|
||||
RPT_FILE_EQUATIONS = ON;
|
||||
LINKED_SNF_EXTRACTOR = OFF;
|
||||
OPTIMIZE_TIMING_SNF = OFF;
|
||||
TIMING_SNF_EXTRACTOR = ON;
|
||||
FUNCTIONAL_SNF_EXTRACTOR = OFF;
|
||||
DESIGN_DOCTOR_RULES = EPLD;
|
||||
DESIGN_DOCTOR = OFF;
|
||||
END;
|
||||
|
||||
COMPILER_INTERFACES_CONFIGURATION
|
||||
BEGIN
|
||||
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
|
||||
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
|
||||
EDIF_BUS_DELIMITERS = [];
|
||||
EDIF_FLATTEN_BUS = OFF;
|
||||
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
|
||||
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
|
||||
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
|
||||
EDIF_OUTPUT_USE_EDC = OFF;
|
||||
EDIF_INPUT_USE_LMF2 = OFF;
|
||||
EDIF_INPUT_USE_LMF1 = OFF;
|
||||
EDIF_OUTPUT_GND = GND;
|
||||
EDIF_OUTPUT_VCC = VCC;
|
||||
EDIF_INPUT_GND = GND;
|
||||
EDIF_INPUT_VCC = VCC;
|
||||
EDIF_OUTPUT_EDC_FILE = *.edc;
|
||||
EDIF_INPUT_LMF2 = *.lmf;
|
||||
EDIF_INPUT_LMF1 = *.lmf;
|
||||
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
|
||||
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
|
||||
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
|
||||
VHDL_FLATTEN_BUS = OFF;
|
||||
VERILOG_FLATTEN_BUS = OFF;
|
||||
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
VHDL_WRITER_VERSION = VHDL87;
|
||||
VHDL_READER_VERSION = VHDL87;
|
||||
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
|
||||
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
|
||||
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
|
||||
SYNOPSYS_DESIGNWARE = OFF;
|
||||
SYNOPSYS_COMPILER = DESIGN;
|
||||
USE_SYNOPSYS_SYNTHESIS = OFF;
|
||||
VHDL_NETLIST_WRITER = OFF;
|
||||
VERILOG_NETLIST_WRITER = OFF;
|
||||
XNF_GENERATE_AHDL_TDX_FILE = ON;
|
||||
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
|
||||
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
|
||||
EDIF_OUTPUT_VERSION = 200;
|
||||
EDIF_NETLIST_WRITER = OFF;
|
||||
END;
|
||||
|
||||
CUSTOM_DESIGN_DOCTOR_RULES
|
||||
BEGIN
|
||||
MASTER_RESET = OFF;
|
||||
EXPANDER_NETWORKS = ON;
|
||||
RACE_CONDITIONS = ON;
|
||||
DELAY_CHAINS = ON;
|
||||
ASYNCHRONOUS_INPUTS = ON;
|
||||
PRESET_CLEAR_NETWORKS = ON;
|
||||
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
|
||||
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
|
||||
MULTI_CLOCK_NETWORKS = ON;
|
||||
MULTI_LEVEL_CLOCKS = ON;
|
||||
GATED_CLOCKS = ON;
|
||||
RIPPLE_CLOCKS = ON;
|
||||
END;
|
||||
|
||||
SIMULATOR_CONFIGURATION
|
||||
BEGIN
|
||||
END_TIME = 25.0us;
|
||||
BIDIR_PIN = STRONG;
|
||||
START_TIME = 0.0ns;
|
||||
GLITCH_TIME = 0.0ns;
|
||||
GLITCH = OFF;
|
||||
OSCILLATION_TIME = 0.0ns;
|
||||
OSCILLATION = OFF;
|
||||
CHECK_OUTPUTS = OFF;
|
||||
SETUP_HOLD = OFF;
|
||||
USE_DEVICE = OFF;
|
||||
END;
|
||||
|
||||
TIMING_ANALYZER_CONFIGURATION
|
||||
BEGIN
|
||||
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
|
||||
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
|
||||
LIST_PATH_FREQUENCY = 10MHz;
|
||||
LIST_PATH_COUNT = 10;
|
||||
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
|
||||
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
|
||||
INCLUDE_PATHS_LESS_THAN = OFF;
|
||||
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
|
||||
INCLUDE_PATHS_GREATER_THAN = OFF;
|
||||
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
|
||||
CELL_WIDTH = 18;
|
||||
LIST_ONLY_LONGEST_PATH = ON;
|
||||
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
|
||||
CUT_OFF_IO_PIN_FEEDBACK = ON;
|
||||
AUTO_RECALCULATE = OFF;
|
||||
END;
|
||||
|
||||
OTHER_CONFIGURATION
|
||||
BEGIN
|
||||
LAST_MAXPLUS2_VERSION = 10.0;
|
||||
ROW_PINS_LCELL_INSERT = ON;
|
||||
CARRY_OUT_PINS_LCELL_INSERT = OFF;
|
||||
NORMAL_LCELL_INSERT = ON;
|
||||
EXPLICIT_FAMILY = 1;
|
||||
FLEX_10K_52_COLUMNS = 40;
|
||||
DEFAULT_9K_EXP_PER_LCELL = 1/2;
|
||||
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
|
||||
LCELLS_PER_ROW_PERCENT = 100;
|
||||
FAN_IN_PER_LCELL_PERCENT = 100;
|
||||
EXP_PER_LCELL_PERCENT = 100;
|
||||
ROW_PINS_PERCENT = 50;
|
||||
ORIGINAL_MAXPLUS2_VERSION = 9.6;
|
||||
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
|
||||
BEGIN
|
||||
TURBO_BIT = ON;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
||||
BEGIN
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
||||
BEGIN
|
||||
TURBO_BIT = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = ON;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
||||
BEGIN
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = AUTO;
|
||||
CASCADE_CHAIN = AUTO;
|
||||
MINIMIZATION = FULL;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = MANUAL;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = MANUAL;
|
||||
END;
|
||||
|
||||
@ -1,499 +0,0 @@
|
||||
|
||||
TITLE "SINC_controller";
|
||||
|
||||
PARAMETERS
|
||||
(
|
||||
G_MODE = 1, -- 1 on LCELL, 0 - on EXP
|
||||
|
||||
NUM = "NO",
|
||||
NUMBER1 = B"00100000X", -- 0 - sinc
|
||||
NUMBER2 = B"00110111X", -- 7
|
||||
NUMBER3 = B"01001101X", -- D
|
||||
NUMBER4 = B"01010010X", -- 2
|
||||
NUMBER5 = B"00100000X", --
|
||||
NUMBER6 = B"00100000X", --
|
||||
NUMBER7 = B"00100000X" --
|
||||
);
|
||||
|
||||
SUBDESIGN SP2_MAX
|
||||
(
|
||||
|
||||
TG42_IN : INPUT;
|
||||
TG42_OUT : OUTPUT;
|
||||
TG42_BUF : OUTPUT;
|
||||
CLKZZ : BIDIR;
|
||||
CLK14 : OUTPUT;
|
||||
|
||||
AUD : OUTPUT; -- clk for timers
|
||||
BEEP : OUTPUT;
|
||||
|
||||
CMOS_DRD : OUTPUT;
|
||||
CMOS_AS : OUTPUT;
|
||||
CMOS_DWR : OUTPUT;
|
||||
|
||||
WR_PDOS : OUTPUT;
|
||||
WD : INPUT;
|
||||
WSTB : INPUT;
|
||||
SR,SL : INPUT;
|
||||
RSTB : INPUT;
|
||||
TR43 : INPUT;
|
||||
CLK_WG : OUTPUT;
|
||||
FDAT : OUTPUT;
|
||||
QDAT : OUTPUT;
|
||||
RDAT : INPUT;
|
||||
/WG_WR : OUTPUT;
|
||||
/WG_RD : OUTPUT;
|
||||
STE : INPUT;
|
||||
DENS_X : OUTPUT;
|
||||
WDAT : OUTPUT;
|
||||
|
||||
|
||||
-- XA[2..0] : BIDIR;
|
||||
XA[2..0] : INPUT;
|
||||
XACS : INPUT;
|
||||
-- SINC_1 : OUTPUT;
|
||||
SINC_1 : BIDIR;
|
||||
SINC_2 : BIDIR;
|
||||
|
||||
HDD_C[3..0] : INPUT;
|
||||
FDD_C[2..0] : INPUT;
|
||||
|
||||
HD_DIR : OUTPUT;
|
||||
HD_CS : OUTPUT;
|
||||
|
||||
/CONF_X : BIDIR;
|
||||
10K_CLK : OUTPUT;
|
||||
WR_CNF : INPUT;
|
||||
10K_D0 : OUTPUT;
|
||||
D0 : INPUT;
|
||||
|
||||
VGA_IN : INPUT;
|
||||
-- WR_COL : INPUT;
|
||||
SINC_V : OUTPUT;
|
||||
SINC_H : OUTPUT;
|
||||
SINC : OUTPUT;
|
||||
SINC_IN : INPUT;
|
||||
|
||||
XHD_RES : OUTPUT;
|
||||
XHD_WR : OUTPUT;
|
||||
XHD_RD : OUTPUT;
|
||||
|
||||
XHD1_CS[2..1] : OUTPUT;
|
||||
XHD2_CS[2..1] : OUTPUT;
|
||||
XHR_RDY : INPUT;
|
||||
|
||||
EPM_RES : INPUT;
|
||||
PW_GOOD : INPUT;
|
||||
|
||||
UNUSED65 : INPUT; -- was GND65, hack for 3000 family
|
||||
UNUSED33 : INPUT; -- was GND33, hack for 3000 family
|
||||
UNUSED1 : INPUT;
|
||||
UNUSED2 : INPUT;
|
||||
UNUSED5 : INPUT;
|
||||
UNUSED7 : INPUT;
|
||||
UNUSED22 : INPUT;
|
||||
UNUSED24 : INPUT;
|
||||
UNUSED27 : INPUT;
|
||||
UNUSED28 : INPUT;
|
||||
UNUSED49 : INPUT;
|
||||
UNUSED50 : INPUT;
|
||||
UNUSED53 : INPUT;
|
||||
UNUSED55 : INPUT;
|
||||
UNUSED63 : INPUT;
|
||||
UNUSED70 : INPUT;
|
||||
UNUSED72 : INPUT;
|
||||
UNUSED77 : INPUT;
|
||||
UNUSED78 : INPUT;
|
||||
|
||||
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
XCT[2..0] : DFF;
|
||||
CNF_ON : NODE;
|
||||
CNF_OFF : NODE;
|
||||
|
||||
CLK42 : NODE;
|
||||
|
||||
CT[3..0] : DFF;
|
||||
CTH[5..0] : DFF;
|
||||
CTV[8..0] : DFFE;
|
||||
|
||||
SINC_HT : DFF;
|
||||
SINC_VT : DFFE;
|
||||
|
||||
TURBING : NODE;
|
||||
FDD_1440 : NODE;
|
||||
NFDD_1440 : NODE;
|
||||
|
||||
CT_WG : NODE;
|
||||
CT_WG1 : NODE;
|
||||
|
||||
STWG[2..0] : DFF;
|
||||
CLK_PRC : NODE;
|
||||
WGR[4..0] : DFF;
|
||||
RDAT_X : NODE;
|
||||
|
||||
REG_P[2..0] : DFF;
|
||||
|
||||
/RESET : NODE;
|
||||
|
||||
|
||||
S144,S720 : NODE;
|
||||
|
||||
SHDD1,SHDD2 : NODE;
|
||||
THDD : NODE;
|
||||
NTHDD : NODE;
|
||||
|
||||
NO_HDD : NODE;
|
||||
|
||||
S320,S312 : NODE;
|
||||
T320 : NODE;
|
||||
NT320 : NODE;
|
||||
|
||||
SOFT_RESET : NODE;
|
||||
SOFT_RESET2 : NODE;
|
||||
|
||||
HDD_CLK : NODE;
|
||||
|
||||
LR_T[1..0] : DFF;
|
||||
|
||||
EXP_X : NODE;
|
||||
EXP_Y : NODE;
|
||||
|
||||
CTV8M : DFF;
|
||||
|
||||
CTV8C : NODE;
|
||||
|
||||
FN_NUM : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
/RESET = DFF((EPM_RES & XHD_RES),!CT3,SOFT_RESET,);
|
||||
|
||||
-- /RESET = (EXP(!EPM_RES & EXP(EXP(EXP(EPM_RES)))) & SOFT_RESET);
|
||||
|
||||
EXP_X = EXP(TG42_IN);
|
||||
EXP_Y = EXP(TG42_IN);
|
||||
|
||||
IF (G_MODE == 0) GENERATE
|
||||
TG42_OUT = LCELL(EXP_X);
|
||||
ELSE GENERATE
|
||||
TG42_OUT = LCELL(TG42_BUF);
|
||||
END GENERATE;
|
||||
|
||||
TG42_BUF = LCELL(!TG42_IN);
|
||||
|
||||
CLK42 = TG42_IN;
|
||||
|
||||
-- CT[].clk = CLK14;
|
||||
CT[].clk = XCT1;
|
||||
CT[] = CT[] + 1;
|
||||
|
||||
-- === horizontal sinc =====
|
||||
|
||||
CTH[].clk = !CT3;
|
||||
SINC_HT.clk = !CT3;
|
||||
|
||||
IF !((CTH[] == B"XXXX11") & SINC_HT) THEN
|
||||
CTH[] = CTH[] + 1;
|
||||
ELSE
|
||||
CTH[] = GND;
|
||||
END IF;
|
||||
|
||||
-- SINC_1 = CTH5;
|
||||
SINC_1 = TRI(CTH5,VCC);
|
||||
SINC_2 = TRI(CTV8,VCC);
|
||||
|
||||
SINC_HT.d = (CTH[] == B"1101XX");
|
||||
|
||||
SINC_H = SINC_HT;
|
||||
|
||||
-- === vertical sinc =======
|
||||
|
||||
-- CTV[].clk = !CT3;
|
||||
-- SINC_VT.clk = !CT3;
|
||||
|
||||
CTV[].clk = SINC_HT;
|
||||
SINC_VT.clk = SINC_HT;
|
||||
|
||||
CTV8M.clk = SINC_HT;
|
||||
|
||||
-- CTV[].ena = (CTH[] == B"110111");
|
||||
-- SINC_VT.ena = (CTH[] == B"110111");
|
||||
CTV[].ena = VCC;
|
||||
SINC_VT.ena = VCC;
|
||||
|
||||
-- IF (CTV[] == B"100111111") THEN
|
||||
|
||||
IF (NUM == "YES") GENERATE
|
||||
|
||||
FN_NUM =(
|
||||
(CTV[8..0] == NUMBER1) or
|
||||
(CTV[8..0] == NUMBER2) or
|
||||
(CTV[8..0] == NUMBER3) or
|
||||
(CTV[8..0] == NUMBER4) or
|
||||
(CTV[8..0] == NUMBER5) or
|
||||
(CTV[8..0] == NUMBER6) or
|
||||
(CTV[8..0] == NUMBER7)
|
||||
) & !NO_HDD;
|
||||
|
||||
ELSE GENERATE
|
||||
|
||||
FN_NUM = GND;
|
||||
|
||||
END GENERATE;
|
||||
|
||||
|
||||
IF EXP((CTV[] == B"XXXXXXX11") & SINC_VT) THEN
|
||||
|
||||
(CTV[8..0]) = ((CTV[8..0]) + 1) xor (CTV8M,B"00000000");
|
||||
CTV8M = FN_NUM;
|
||||
|
||||
ELSE
|
||||
CTV[7..0] = GND;
|
||||
CTV8M = GND;
|
||||
CTV8 = GND;
|
||||
END IF;
|
||||
|
||||
SINC_VT.d = ((CTV[8..0] == B"1001111XX") or ((CTV[8..0] == B"1001101XX")) & NT320);
|
||||
|
||||
SINC_V = SINC_VT;
|
||||
|
||||
SINC = SINC_V xor SINC_H;
|
||||
|
||||
-- =============================
|
||||
|
||||
-- =========================================
|
||||
-- divide by 6
|
||||
|
||||
XCT[].clk = (TG42_IN xor !XCT1);
|
||||
XCT[].d = XCT[] + 1;
|
||||
|
||||
-- CLKZZ = 14 MHz
|
||||
|
||||
CLKZZ = TRI(XCT1,CNF_OFF);
|
||||
CLK14 = DFF(!CLK14,XCT0,,);
|
||||
|
||||
-- test exists
|
||||
|
||||
-- CNF_OFF = EXP(CNF_ON & /RESET);
|
||||
-- CNF_ON = EXP(CNF_OFF & XACS);
|
||||
|
||||
CNF_OFF = DFF(GND,GND,XACS,/RESET);
|
||||
CNF_ON = !CNF_OFF;
|
||||
|
||||
-- =========================================
|
||||
|
||||
-- ======== FDD controller ==================
|
||||
|
||||
TURBING = EXP(EXP(TURBING & !WSTB & !RSTB) & !STE & NFDD_1440);
|
||||
-- TURBING = GND;
|
||||
|
||||
CT_WG = TFF(VCC,(XCT1 xor (CT_WG & TURBING)),,);
|
||||
|
||||
STWG[].clk = (CT_WG xor STWG2);
|
||||
STWG[].d = STWG[] + 1;
|
||||
|
||||
CLK_WG = STWG2;
|
||||
|
||||
-- CLK_PRC = STWG0;
|
||||
CLK_PRC = CT_WG;
|
||||
|
||||
CT_WG1 = EXP(EXP(XCT1 & FDD_1440) & EXP(CT0 & NFDD_1440));
|
||||
|
||||
WGR[].clk = CT_WG1;
|
||||
|
||||
IF !FDAT THEN
|
||||
TABLE WGR[3..0] => WGR[3..0].d;
|
||||
0 => 4; 1 => 5; 2 => 4; 3 => 5;
|
||||
4 => 6; 5 => 7; 6 => 8; 7 => 8;
|
||||
8 => 9; 9 => 9; 10 => 10; 11 => 11;
|
||||
12 => 12; 13 => 13; 14 => 14; 15 => 15;
|
||||
END TABLE;
|
||||
WGR4.d = WGR4;
|
||||
ELSE
|
||||
IF WGR[3..0] == 0 THEN
|
||||
WGR[3..0].d = 3;
|
||||
WGR4.d = WGR4;
|
||||
ELSE
|
||||
WGR[].d = WGR[] + 1;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
QDAT = WGR4;
|
||||
RDAT_X = EXP(EXP(RDAT_X & EXP(!RDAT & !CT_WG1)) & EXP(RDAT & !CT_WG1));
|
||||
-- FDAT = DFF((RDAT_X or !DFF(RDAT_X,CT_WG1,,)),CT_WG1,,);
|
||||
FDAT = DFF((RDAT_X or EXP(DFF(RDAT_X,CT_WG1,,))),CT_WG1,,);
|
||||
-- ==========================================================
|
||||
-- now not complete!
|
||||
|
||||
AUD = CT3;
|
||||
BEEP = GND;
|
||||
|
||||
-- /CONF_X = TRI(GND,!/RESET);
|
||||
|
||||
/CONF_X = OPNDRN(/RESET);
|
||||
|
||||
-- 10K_CLK = WR_CNF; -- now not protect!
|
||||
|
||||
10K_CLK = DFF((WR_CNF & CNF_OFF) or ((HDD_C0 or FDD_C2) & CNF_ON),CLK42,,);
|
||||
|
||||
10K_D0 = DFFE(D0,10K_CLK,S720,(S144 & /RESET),CNF_OFF);
|
||||
|
||||
DENS_X = VCC;
|
||||
|
||||
-- === now NOT PRECOMP! =====
|
||||
|
||||
-- WDAT = WD;
|
||||
|
||||
WDAT = REG_P2;
|
||||
|
||||
REG_P[].clk = !CLK_PRC;
|
||||
|
||||
-- CASE WD IS
|
||||
-- WHEN 1 => REG_P[].d = (GND,SL,!(SL or SR),SR);
|
||||
-- WHEN 0 => REG_P[].d = (EXP(EXP(REG_P2)),REG_P[1..0],GND);
|
||||
-- END CASE;
|
||||
|
||||
-- CASE (DFF(WD,CLK_WG,,),DFF((SL & TR43),CLK_WG,,),DFF((SR & TR43),CLK_WG,,)) IS
|
||||
|
||||
LR_T[].clk = STWG2;
|
||||
-- LR_T[].clk = CLK_WG;
|
||||
|
||||
LR_T[].d = ((WD & !(SL & TR43)),(WD & !(SR & TR43)));
|
||||
|
||||
CASE LR_T[] IS
|
||||
WHEN 0 => REG_P[1..0] = (REG_P[1..0] - 1) & EXP(REG_P[1..0] == 0);
|
||||
REG_P[2] = EXP(EXP(REG_P[1..0] == 1));
|
||||
-- REG_P[2] = (REG_P[1..0] == 1);
|
||||
WHEN 1 => REG_P[1..0] = 1; REG_P[2] = GND;
|
||||
WHEN 2 => REG_P[1..0] = 3; REG_P[2] = GND;
|
||||
WHEN 3 => REG_P[1..0] = 2; REG_P[2] = GND;
|
||||
END CASE;
|
||||
%
|
||||
CASE (WD,DFF((SL & TR43),CLK_WG,,),DFF((SR & TR43),CLK_WG,,)) IS
|
||||
WHEN B"0XX" => REG_P[1..0] = (REG_P[1..0] - 1) & EXP(REG_P[1..0] == 0);
|
||||
WHEN B"100" => REG_P[1..0] = 2;
|
||||
WHEN B"110" => REG_P[1..0] = 1;
|
||||
WHEN B"101" => REG_P[1..0] = 3;
|
||||
WHEN B"111" => REG_P[1..0] = 2;
|
||||
END CASE;
|
||||
%
|
||||
|
||||
%
|
||||
CASE WD IS
|
||||
WHEN 0 => REG_P[3] = EXP(EXP(REG_P[1..0] == 1));
|
||||
WHEN 1 => REG_P[3] = GND;
|
||||
END CASE;
|
||||
%
|
||||
|
||||
-- === Port Controls ====================================
|
||||
%
|
||||
FDD_C0 - 0 - WG93 / 1 - kmps/ p_dos
|
||||
FDD_C1 - 0 - write / 1 - read
|
||||
FDD_C2 - 0 - no / 1 - CS_WG/ strobe
|
||||
|
||||
HDD_C0 - strobe
|
||||
HDD_C[2..1] = 00 - SYS_FN, 01 - SYS_FN, 10 - HDD1/2, 11 - CMOS
|
||||
HDD_C3 - 0 - HD_CS1, 1 HD_CS3 / 0 CMOS_DAT, 1 - CMOS_ADR
|
||||
|
||||
HDD_C[3..0] = 0001, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set 1.44/720
|
||||
HDD_C[3..0] = 1001, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set 320/312 lines
|
||||
HDD_C[3..0] = 0011, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set HDD1/HDD2
|
||||
HDD_C[3..0] = 1011, FDD_C[2..1] = 00; -> FDD_C0 = 0 -> soft_reset!
|
||||
HDD_C[3..0] = X101, FDD_C[2..1] = XX; -> HDD1/2 rd/wr
|
||||
|
||||
%
|
||||
|
||||
SOFT_RESET = !((HDD_C[] == B"1011") & (FDD_C[] == B"000"));
|
||||
SOFT_RESET2 = !((HDD_C[] == B"1011") & (FDD_C[] == B"001"));
|
||||
|
||||
-- FDD switch
|
||||
|
||||
-- NFDD_1440 = EXP(FDD_1440 & S720 & /RESET);
|
||||
-- FDD_1440 = EXP(NFDD_1440 & S144);
|
||||
FDD_1440 = 10K_D0;
|
||||
NFDD_1440 = !10K_D0;
|
||||
|
||||
S144 = EXP((HDD_C[] == B"0001") & (FDD_C[] == B"001"));
|
||||
S720 = EXP((HDD_C[] == B"0001") & (FDD_C[] == B"000"));
|
||||
|
||||
-- Screen Switch
|
||||
|
||||
T320 = EXP(NT320 & S320 & /RESET);
|
||||
NT320 = EXP(T320 & S312);
|
||||
|
||||
S312 = EXP((HDD_C[] == B"1001") & (FDD_C[] == B"001"));
|
||||
S320 = EXP((HDD_C[] == B"1001") & (FDD_C[] == B"000"));
|
||||
|
||||
-- HDD Switch
|
||||
|
||||
-- THDD = EXP(NTHDD & SHDD2 & /RESET);
|
||||
-- NTHDD = EXP(THDD & SHDD1);
|
||||
|
||||
THDD = EXP(NTHDD & NO_HDD & SHDD2 & /RESET & SOFT_RESET2);
|
||||
NTHDD = EXP(THDD & NO_HDD & SHDD1 & /RESET & SOFT_RESET2);
|
||||
NO_HDD = EXP(NTHDD & THDD & SHDD1 & SHDD2);
|
||||
|
||||
SHDD2 = EXP((HDD_C[] == B"0011") & (FDD_C[] == B"001"));
|
||||
SHDD1 = EXP((HDD_C[] == B"0011") & (FDD_C[] == B"000"));
|
||||
|
||||
-- Control signals
|
||||
|
||||
WR_PDOS = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2);
|
||||
/WG_WR = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X00")),HDD_CLK,,FDD_C2);
|
||||
/WG_RD = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X10")),HDD_CLK,,FDD_C2);
|
||||
|
||||
CMOS_DWR = DFF(!((HDD_C[] == B"1110") & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2);
|
||||
CMOS_AS =!DFF(!((HDD_C[] == B"0110") & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2);
|
||||
CMOS_DRD = DFF(!((HDD_C[] == B"1110") & (FDD_C[] == B"X10")),HDD_CLK,,FDD_C2);
|
||||
|
||||
-- HD_DIR = !HDD_C1; -- ????????????
|
||||
HD_DIR = XHD_RD;
|
||||
|
||||
-- HD_CS = GND;
|
||||
-- HD_CS = CTV8M;
|
||||
HD_CS = (CTV8M and /RESET);
|
||||
|
||||
|
||||
-- HD_CS = !/RESET;
|
||||
|
||||
-- XHD_RES = VCC;
|
||||
|
||||
-- XHD_RES = DFF(PW_GOOD,SINC_V,,);
|
||||
XHD_RES = DFF(PW_GOOD,SINC_V,EPM_RES,);
|
||||
|
||||
-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),CLK42,,);
|
||||
-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),CLK42,,);
|
||||
|
||||
-- HDD_CLK = EXP(EXP(HDD_C0));
|
||||
HDD_CLK = 10K_CLK;
|
||||
|
||||
-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1 or !HDD_CLK),CLK42,,HDD_C0);
|
||||
-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1 or !HDD_CLK),CLK42,,HDD_C0);
|
||||
-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,HDD_C0);
|
||||
-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,HDD_C0);
|
||||
XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,(HDD_C0 and /RESET));
|
||||
XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,(HDD_C0 and /RESET));
|
||||
|
||||
-- XHD1_CS1 = DFF(!((HDD_C[] == B"010X") & NTHDD),CLK42,,);
|
||||
-- XHD1_CS2 = DFF(!((HDD_C[] == B"110X") & NTHDD),CLK42,,);
|
||||
|
||||
-- XHD2_CS1 = DFF(!((HDD_C[] == B"010X") & THDD),CLK42,,);
|
||||
-- XHD2_CS2 = DFF(!((HDD_C[] == B"110X") & THDD),CLK42,,);
|
||||
|
||||
-- XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,);
|
||||
-- XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,);
|
||||
XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,/RESET);
|
||||
XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,/RESET);
|
||||
|
||||
-- XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,);
|
||||
-- XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,);
|
||||
XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,/RESET);
|
||||
XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,/RESET);
|
||||
|
||||
|
||||
END;
|
||||
|
||||
@ -1,699 +0,0 @@
|
||||
--
|
||||
-- Copyright (C) 1988-2000 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
--
|
||||
CHIP SP2_MAX
|
||||
BEGIN
|
||||
DEVICE = EPM7128STC100-10;
|
||||
|UNUSED1: INPUT_PIN = 1; -- 7064 N.C.
|
||||
|UNUSED2: INPUT_PIN = 2; -- 7064 N.C.
|
||||
-- |VCCIO
|
||||
-- |#TDI
|
||||
|UNUSED5: INPUT_PIN = 5; -- 7064 N.C.
|
||||
|CMOS_AS : OUTPUT_PIN = 6;
|
||||
|UNUSED7: INPUT_PIN = 7; -- 7064 N.C.
|
||||
|WR_PDOS : OUTPUT_PIN = 8;
|
||||
|WD : INPUT_PIN = 9;
|
||||
|
||||
|WSTB : INPUT_PIN = 10;
|
||||
-- |GND
|
||||
|TR43 : INPUT_PIN = 12;
|
||||
|CLK_WG : OUTPUT_PIN = 13;
|
||||
|FDAT : OUTPUT_PIN = 14;
|
||||
-- |#TMS
|
||||
|QDAT : OUTPUT_PIN = 16;
|
||||
|XA0 : INPUT_PIN = 17;
|
||||
-- |VCCIO
|
||||
|SINC_2 : OUTPUT_PIN = 19;
|
||||
|
||||
|SINC_1 : OUTPUT_PIN = 20;
|
||||
|XA1 : INPUT_PIN = 21;
|
||||
|UNUSED22: INPUT_PIN = 22; -- 7064 N.C.
|
||||
|XA2 : INPUT_PIN = 23;
|
||||
|UNUSED24: INPUT_PIN = 24; -- 7064 N.C.
|
||||
|RSTB : INPUT_PIN = 25;
|
||||
-- |GND
|
||||
|UNUSED27: INPUT_PIN = 27; -- 7064 N.C.
|
||||
|UNUSED28: INPUT_PIN = 28; -- 7064 N.C.
|
||||
|SR : INPUT_PIN = 29;
|
||||
|
||||
|SL : INPUT_PIN = 30;
|
||||
|CLK14 : OUTPUT_PIN = 31;
|
||||
|CLKZZ : BIDIR_PIN = 32;
|
||||
|UNUSED33 : INPUT_PIN = 33; -- be careful! at 3000 family the pin 33 is GND
|
||||
-- |VCCIO
|
||||
|AUD : OUTPUT_PIN = 35;
|
||||
|TG42_BUF : OUTPUT_PIN = 36;
|
||||
|XACS : INPUT_PIN = 37;
|
||||
-- |GND
|
||||
-- |VCCINT
|
||||
|
||||
|HDD_C3 : INPUT_PIN = 40;
|
||||
|HDD_C2 : INPUT_PIN = 41;
|
||||
|HDD_C1 : INPUT_PIN = 42;
|
||||
-- |GND
|
||||
|FDD_C0 : INPUT_PIN = 44;
|
||||
|FDD_C1 : INPUT_PIN = 45;
|
||||
|FDD_C2 : INPUT_PIN = 46;
|
||||
|HDD_C0 : INPUT_PIN = 47;
|
||||
|HD_DIR : OUTPUT_PIN = 48;
|
||||
|UNUSED49: INPUT_PIN = 49; -- 7064 N.C.
|
||||
|
||||
|UNUSED50: INPUT_PIN = 50; -- 7064 N.C.
|
||||
-- |VCCIO
|
||||
|HD_CS : OUTPUT_PIN = 52;
|
||||
|UNUSED53 : INPUT_PIN = 53; -- 7064 N.C.
|
||||
|/CONF_X : BIDIR_PIN = 54;
|
||||
|UNUSED55: INPUT_PIN = 55; -- 7064 N.C.
|
||||
|10K_CLK : OUTPUT_PIN = 56;
|
||||
|WR_CNF : INPUT_PIN = 57;
|
||||
|10K_D0 : OUTPUT_PIN = 58;
|
||||
-- |GND
|
||||
|
||||
|D0 : INPUT_PIN = 60;
|
||||
|VGA_IN : INPUT_PIN = 61;
|
||||
-- |#TCK
|
||||
|UNUSED63: INPUT_PIN = 63;
|
||||
|SINC_V : OUTPUT_PIN = 64;
|
||||
|UNUSED65 : INPUT_PIN = 65; -- be careful! at 3000 family the pin 33 is GND
|
||||
-- |VCCIO
|
||||
|SINC : OUTPUT_PIN = 67;
|
||||
|SINC_H : OUTPUT_PIN = 68;
|
||||
|SINC_IN : INPUT_PIN = 69;
|
||||
|
||||
|UNUSED70: INPUT_PIN = 70; -- 7064 N.C.
|
||||
|XHD_RES : OUTPUT_PIN = 71;
|
||||
|UNUSED72: INPUT_PIN = 72; -- 7064 N.C.
|
||||
-- |#TDO
|
||||
-- |GND
|
||||
|XHD_WR : OUTPUT_PIN = 75;
|
||||
|XHD_RD : OUTPUT_PIN = 76;
|
||||
|UNUSED77: INPUT_PIN = 77; -- 7064 N.C.
|
||||
|UNUSED78 : INPUT_PIN = 78; -- 7064 N.C.
|
||||
|XHD1_CS1 : OUTPUT_PIN = 79;
|
||||
|
||||
|XHD1_CS2 : OUTPUT_PIN = 80;
|
||||
|XHD2_CS1 : OUTPUT_PIN = 81;
|
||||
-- |VCCIO
|
||||
|XHD2_CS2 : OUTPUT_PIN = 83;
|
||||
|BEEP : OUTPUT_PIN = 84;
|
||||
|TG42_OUT : OUTPUT_PIN = 85;
|
||||
-- |GND
|
||||
|TG42_IN : INPUT_PIN = 87;
|
||||
|XHR_RDY : INPUT_PIN = 88;
|
||||
|EPM_RES : INPUT_PIN = 89;
|
||||
|
||||
|PW_GOOD : INPUT_PIN = 90;
|
||||
-- |VCCINT
|
||||
|RDAT : INPUT_PIN = 92;
|
||||
|/WG_WR : OUTPUT_PIN = 93;
|
||||
|STE : INPUT_PIN = 94;
|
||||
-- |GND
|
||||
|DENS_X : OUTPUT_PIN = 96;
|
||||
|/WG_RD : OUTPUT_PIN = 97;
|
||||
|WDAT : OUTPUT_PIN = 98;
|
||||
|CMOS_DRD : OUTPUT_PIN = 99;
|
||||
|CMOS_DWR : OUTPUT_PIN = 100;
|
||||
END;
|
||||
|
||||
DEFAULT_DEVICES
|
||||
BEGIN
|
||||
AUTO_DEVICE = EPM7256SQC208-7;
|
||||
AUTO_DEVICE = EPM7256SRC208-7;
|
||||
AUTO_DEVICE = EPM7192SQC160-7;
|
||||
AUTO_DEVICE = EPM7160SQC160-6;
|
||||
AUTO_DEVICE = EPM7160STC100-6;
|
||||
AUTO_DEVICE = EPM7160SLC84-6;
|
||||
AUTO_DEVICE = EPM7128SQC160-6;
|
||||
AUTO_DEVICE = EPM7128STC100-6;
|
||||
AUTO_DEVICE = EPM7128SQC100-6;
|
||||
AUTO_DEVICE = EPM7128SLC84-6;
|
||||
AUTO_DEVICE = EPM7064STC100-5;
|
||||
AUTO_DEVICE = EPM7064SLC84-5;
|
||||
AUTO_DEVICE = EPM7064STC44-5;
|
||||
AUTO_DEVICE = EPM7064SLC44-5;
|
||||
AUTO_DEVICE = EPM7032STC44-5;
|
||||
AUTO_DEVICE = EPM7032SLC44-5;
|
||||
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
|
||||
END;
|
||||
|
||||
TIMING_POINT
|
||||
BEGIN
|
||||
DEVICE_FOR_TIMING_SYNTHESIS = EPM7128STC100-10;
|
||||
FREQUENCY = 100MHz;
|
||||
MAINTAIN_STABLE_SYNTHESIS = OFF;
|
||||
CUT_ALL_CLEAR_PRESET = ON;
|
||||
CUT_ALL_BIDIR = ON;
|
||||
END;
|
||||
|
||||
IGNORED_ASSIGNMENTS
|
||||
BEGIN
|
||||
FIT_IGNORE_TIMING = ON;
|
||||
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
|
||||
IGNORE_DEVICE_ASSIGNMENTS = OFF;
|
||||
IGNORE_LC_ASSIGNMENTS = OFF;
|
||||
IGNORE_PIN_ASSIGNMENTS = OFF;
|
||||
IGNORE_CHIP_ASSIGNMENTS = OFF;
|
||||
IGNORE_TIMING_ASSIGNMENTS = OFF;
|
||||
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
|
||||
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
|
||||
END;
|
||||
|
||||
LOGIC_OPTIONS
|
||||
BEGIN
|
||||
|LR_T1 : TURBO_BIT = ON;
|
||||
|LR_T0 : TURBO_BIT = ON;
|
||||
|CLK_WG : TURBO_BIT = ON;
|
||||
|TG42_BUF : STYLE = WYSIWYG;
|
||||
|TG42_OUT : STYLE = WYSIWYG;
|
||||
|XHD_RD : TURBO_BIT = OFF;
|
||||
|XHD_RES : TURBO_BIT = OFF;
|
||||
|XHD_WR : TURBO_BIT = OFF;
|
||||
|XHD1_CS1 : TURBO_BIT = OFF;
|
||||
|XHD1_CS2 : TURBO_BIT = OFF;
|
||||
|XHD2_CS1 : TURBO_BIT = OFF;
|
||||
|XHD2_CS2 : TURBO_BIT = OFF;
|
||||
|10K_CLK : TURBO_BIT = OFF;
|
||||
|10K_D0 : TURBO_BIT = OFF;
|
||||
|REG_P0 : TURBO_BIT = ON;
|
||||
|REG_P1 : TURBO_BIT = ON;
|
||||
|REG_P2 : TURBO_BIT = ON;
|
||||
|TG42_BUF : TURBO_BIT = ON;
|
||||
|TG42_OUT : TURBO_BIT = ON;
|
||||
|STWG0 : TURBO_BIT = ON;
|
||||
|STWG1 : TURBO_BIT = ON;
|
||||
|STWG2 : TURBO_BIT = ON;
|
||||
|XCT0 : TURBO_BIT = ON;
|
||||
|XCT1 : TURBO_BIT = ON;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_DEVICE_OPTIONS
|
||||
BEGIN
|
||||
MULTIVOLT_IO = OFF;
|
||||
SECURITY_BIT = ON;
|
||||
MAX7000B_ENABLE_VREFB = OFF;
|
||||
MAX7000B_ENABLE_VREFA = OFF;
|
||||
MAX7000B_VCCIO_IOBANK2 = 3.3V;
|
||||
MAX7000B_VCCIO_IOBANK1 = 3.3V;
|
||||
CONFIG_EPROM_PULLUP_RESISTOR = ON;
|
||||
CONFIG_EPROM_USER_CODE = FFFFFFFF;
|
||||
FLEX_CONFIGURATION_EPROM = AUTO;
|
||||
MAX7000AE_ENABLE_JTAG = ON;
|
||||
MAX7000AE_USER_CODE = FFFFFFFF;
|
||||
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
|
||||
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
|
||||
FLEX6000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
|
||||
MAX7000S_ENABLE_JTAG = ON;
|
||||
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
|
||||
MAX7000S_USER_CODE = FFFF;
|
||||
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
|
||||
FLEX10K_JTAG_USER_CODE = 7F;
|
||||
ENABLE_INIT_DONE_OUTPUT = OFF;
|
||||
ENABLE_CHIP_WIDE_OE = OFF;
|
||||
ENABLE_CHIP_WIDE_RESET = OFF;
|
||||
nCEO = UNRESERVED;
|
||||
CLKUSR = UNRESERVED;
|
||||
ADD17 = UNRESERVED;
|
||||
ADD16 = UNRESERVED;
|
||||
ADD15 = UNRESERVED;
|
||||
ADD14 = UNRESERVED;
|
||||
ADD13 = UNRESERVED;
|
||||
ADD0_TO_ADD12 = UNRESERVED;
|
||||
SDOUT = RESERVED_DRIVES_OUT;
|
||||
RDCLK = UNRESERVED;
|
||||
RDYnBUSY = UNRESERVED;
|
||||
nWS_nRS_nCS_CS = UNRESERVED;
|
||||
DATA1_TO_DATA7 = UNRESERVED;
|
||||
DATA0 = RESERVED_TRI_STATED;
|
||||
FLEX8000_ENABLE_JTAG = OFF;
|
||||
CONFIG_SCHEME = ACTIVE_SERIAL;
|
||||
DISABLE_TIME_OUT = OFF;
|
||||
ENABLE_DCLK_OUTPUT = OFF;
|
||||
RELEASE_CLEARS = OFF;
|
||||
AUTO_RESTART = OFF;
|
||||
USER_CLOCK = OFF;
|
||||
RESERVED_PINS_PERCENT = 0;
|
||||
RESERVED_LCELLS_PERCENT = 0;
|
||||
END;
|
||||
|
||||
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
|
||||
BEGIN
|
||||
STYLE = NORMAL;
|
||||
AUTO_GLOBAL_CLEAR = OFF;
|
||||
AUTO_GLOBAL_CLOCK = OFF;
|
||||
DEVICE_FAMILY = MAX7000S;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
|
||||
AUTO_IMPLEMENT_IN_EAB = OFF;
|
||||
AUTO_OPEN_DRAIN_PINS = ON;
|
||||
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
|
||||
AUTO_REGISTER_PACKING = OFF;
|
||||
AUTO_FAST_IO = OFF;
|
||||
AUTO_GLOBAL_OE = ON;
|
||||
AUTO_GLOBAL_PRESET = ON;
|
||||
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
|
||||
OPTIMIZE_FOR_SPEED = 5;
|
||||
END;
|
||||
|
||||
COMPILER_PROCESSING_CONFIGURATION
|
||||
BEGIN
|
||||
FITTER_SETTINGS = ADVANCED;
|
||||
USE_QUARTUS_FITTER = OFF;
|
||||
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
|
||||
SMART_RECOMPILE = OFF;
|
||||
GENERATE_AHDL_TDO_FILE = OFF;
|
||||
RPT_FILE_USER_ASSIGNMENTS = ON;
|
||||
RPT_FILE_LCELL_INTERCONNECT = ON;
|
||||
RPT_FILE_HIERARCHY = ON;
|
||||
RPT_FILE_EQUATIONS = ON;
|
||||
LINKED_SNF_EXTRACTOR = OFF;
|
||||
OPTIMIZE_TIMING_SNF = OFF;
|
||||
TIMING_SNF_EXTRACTOR = ON;
|
||||
FUNCTIONAL_SNF_EXTRACTOR = OFF;
|
||||
DESIGN_DOCTOR_RULES = EPLD;
|
||||
DESIGN_DOCTOR = OFF;
|
||||
END;
|
||||
|
||||
COMPILER_INTERFACES_CONFIGURATION
|
||||
BEGIN
|
||||
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
|
||||
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
|
||||
EDIF_BUS_DELIMITERS = [];
|
||||
EDIF_FLATTEN_BUS = OFF;
|
||||
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
|
||||
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
|
||||
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
|
||||
EDIF_OUTPUT_USE_EDC = OFF;
|
||||
EDIF_INPUT_USE_LMF2 = OFF;
|
||||
EDIF_INPUT_USE_LMF1 = OFF;
|
||||
EDIF_OUTPUT_GND = GND;
|
||||
EDIF_OUTPUT_VCC = VCC;
|
||||
EDIF_INPUT_GND = GND;
|
||||
EDIF_INPUT_VCC = VCC;
|
||||
EDIF_OUTPUT_EDC_FILE = *.edc;
|
||||
EDIF_INPUT_LMF2 = *.lmf;
|
||||
EDIF_INPUT_LMF1 = *.lmf;
|
||||
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
|
||||
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
|
||||
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
|
||||
VHDL_FLATTEN_BUS = OFF;
|
||||
VERILOG_FLATTEN_BUS = OFF;
|
||||
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
|
||||
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
|
||||
VHDL_WRITER_VERSION = VHDL87;
|
||||
VHDL_READER_VERSION = VHDL87;
|
||||
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
|
||||
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
|
||||
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
|
||||
SYNOPSYS_DESIGNWARE = OFF;
|
||||
SYNOPSYS_COMPILER = DESIGN;
|
||||
USE_SYNOPSYS_SYNTHESIS = OFF;
|
||||
VHDL_NETLIST_WRITER = OFF;
|
||||
VERILOG_NETLIST_WRITER = OFF;
|
||||
XNF_GENERATE_AHDL_TDX_FILE = ON;
|
||||
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
|
||||
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
|
||||
EDIF_OUTPUT_VERSION = 200;
|
||||
EDIF_NETLIST_WRITER = OFF;
|
||||
END;
|
||||
|
||||
CUSTOM_DESIGN_DOCTOR_RULES
|
||||
BEGIN
|
||||
MASTER_RESET = OFF;
|
||||
EXPANDER_NETWORKS = ON;
|
||||
RACE_CONDITIONS = ON;
|
||||
DELAY_CHAINS = ON;
|
||||
ASYNCHRONOUS_INPUTS = ON;
|
||||
PRESET_CLEAR_NETWORKS = ON;
|
||||
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
|
||||
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
|
||||
MULTI_CLOCK_NETWORKS = ON;
|
||||
MULTI_LEVEL_CLOCKS = ON;
|
||||
GATED_CLOCKS = ON;
|
||||
RIPPLE_CLOCKS = ON;
|
||||
END;
|
||||
|
||||
SIMULATOR_CONFIGURATION
|
||||
BEGIN
|
||||
END_TIME = 25.0us;
|
||||
BIDIR_PIN = STRONG;
|
||||
START_TIME = 0.0ns;
|
||||
GLITCH_TIME = 0.0ns;
|
||||
GLITCH = OFF;
|
||||
OSCILLATION_TIME = 0.0ns;
|
||||
OSCILLATION = OFF;
|
||||
CHECK_OUTPUTS = OFF;
|
||||
SETUP_HOLD = OFF;
|
||||
USE_DEVICE = OFF;
|
||||
END;
|
||||
|
||||
TIMING_ANALYZER_CONFIGURATION
|
||||
BEGIN
|
||||
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
|
||||
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
|
||||
LIST_PATH_FREQUENCY = 10MHz;
|
||||
LIST_PATH_COUNT = 10;
|
||||
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
|
||||
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
|
||||
INCLUDE_PATHS_LESS_THAN = OFF;
|
||||
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
|
||||
INCLUDE_PATHS_GREATER_THAN = OFF;
|
||||
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
|
||||
CELL_WIDTH = 18;
|
||||
LIST_ONLY_LONGEST_PATH = ON;
|
||||
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
|
||||
CUT_OFF_IO_PIN_FEEDBACK = ON;
|
||||
AUTO_RECALCULATE = OFF;
|
||||
END;
|
||||
|
||||
OTHER_CONFIGURATION
|
||||
BEGIN
|
||||
LAST_MAXPLUS2_VERSION = 10.0;
|
||||
ROW_PINS_LCELL_INSERT = ON;
|
||||
CARRY_OUT_PINS_LCELL_INSERT = OFF;
|
||||
NORMAL_LCELL_INSERT = ON;
|
||||
EXPLICIT_FAMILY = 1;
|
||||
FLEX_10K_52_COLUMNS = 40;
|
||||
DEFAULT_9K_EXP_PER_LCELL = 1/2;
|
||||
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
|
||||
LCELLS_PER_ROW_PERCENT = 100;
|
||||
FAN_IN_PER_LCELL_PERCENT = 100;
|
||||
EXP_PER_LCELL_PERCENT = 100;
|
||||
ROW_PINS_PERCENT = 50;
|
||||
ORIGINAL_MAXPLUS2_VERSION = 9.6;
|
||||
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
|
||||
BEGIN
|
||||
TURBO_BIT = ON;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
||||
BEGIN
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = ON;
|
||||
REFACTORIZATION = ON;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
||||
BEGIN
|
||||
TURBO_BIT = ON;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
XOR_SYNTHESIS = ON;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = ON;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
MINIMIZATION = FULL;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
||||
BEGIN
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
REGISTER_OPTIMIZATION = ON;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = ON;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = ON;
|
||||
REDUCE_LOGIC = ON;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
CARRY_CHAIN = AUTO;
|
||||
CASCADE_CHAIN = AUTO;
|
||||
MINIMIZATION = FULL;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = ON;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = ON;
|
||||
SOFT_BUFFER_INSERTION = OFF;
|
||||
FAST_IO = OFF;
|
||||
IGNORE_SOFT_BUFFERS = OFF;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = ON;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN = IGNORE;
|
||||
CASCADE_CHAIN = IGNORE;
|
||||
END;
|
||||
|
||||
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
||||
BEGIN
|
||||
REGISTER_OPTIMIZATION = OFF;
|
||||
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
||||
RESYNTHESIZE_NETWORK = OFF;
|
||||
MULTI_LEVEL_FACTORING = OFF;
|
||||
SUBFACTOR_EXTRACTION = OFF;
|
||||
REFACTORIZATION = OFF;
|
||||
NOT_GATE_PUSH_BACK = ON;
|
||||
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
||||
REDUCE_LOGIC = OFF;
|
||||
DECOMPOSE_GATES = OFF;
|
||||
SOFT_BUFFER_INSERTION = ON;
|
||||
IGNORE_SOFT_BUFFERS = ON;
|
||||
PARALLEL_EXPANDERS = OFF;
|
||||
TURBO_BIT = OFF;
|
||||
XOR_SYNTHESIS = OFF;
|
||||
SLOW_SLEW_RATE = OFF;
|
||||
MINIMIZATION = PARTIAL;
|
||||
CARRY_CHAIN_LENGTH = 32;
|
||||
CARRY_CHAIN = MANUAL;
|
||||
CASCADE_CHAIN_LENGTH = 2;
|
||||
CASCADE_CHAIN = MANUAL;
|
||||
END;
|
||||
|
||||
@ -1,499 +0,0 @@
|
||||
|
||||
TITLE "SINC_controller";
|
||||
|
||||
PARAMETERS
|
||||
(
|
||||
G_MODE = 1, -- 1 on LCELL, 0 - on EXP
|
||||
|
||||
NUM = "NO",
|
||||
NUMBER1 = B"00100000X", -- 0 - sinc
|
||||
NUMBER2 = B"00110111X", -- 7
|
||||
NUMBER3 = B"01001101X", -- D
|
||||
NUMBER4 = B"01010010X", -- 2
|
||||
NUMBER5 = B"00100000X", --
|
||||
NUMBER6 = B"00100000X", --
|
||||
NUMBER7 = B"00100000X" --
|
||||
);
|
||||
|
||||
SUBDESIGN SP2_MAX
|
||||
(
|
||||
|
||||
TG42_IN : INPUT;
|
||||
TG42_OUT : OUTPUT;
|
||||
TG42_BUF : OUTPUT;
|
||||
CLKZZ : BIDIR;
|
||||
CLK14 : OUTPUT;
|
||||
|
||||
AUD : OUTPUT; -- clk for timers
|
||||
BEEP : OUTPUT;
|
||||
|
||||
CMOS_DRD : OUTPUT;
|
||||
CMOS_AS : OUTPUT;
|
||||
CMOS_DWR : OUTPUT;
|
||||
|
||||
WR_PDOS : OUTPUT;
|
||||
WD : INPUT;
|
||||
WSTB : INPUT;
|
||||
SR,SL : INPUT;
|
||||
RSTB : INPUT;
|
||||
TR43 : INPUT;
|
||||
CLK_WG : OUTPUT;
|
||||
FDAT : OUTPUT;
|
||||
QDAT : OUTPUT;
|
||||
RDAT : INPUT;
|
||||
/WG_WR : OUTPUT;
|
||||
/WG_RD : OUTPUT;
|
||||
STE : INPUT;
|
||||
DENS_X : OUTPUT;
|
||||
WDAT : OUTPUT;
|
||||
|
||||
|
||||
-- XA[2..0] : BIDIR;
|
||||
XA[2..0] : INPUT;
|
||||
XACS : INPUT;
|
||||
-- SINC_1 : OUTPUT;
|
||||
SINC_1 : BIDIR;
|
||||
SINC_2 : BIDIR;
|
||||
|
||||
HDD_C[3..0] : INPUT;
|
||||
FDD_C[2..0] : INPUT;
|
||||
|
||||
HD_DIR : OUTPUT;
|
||||
HD_CS : OUTPUT;
|
||||
|
||||
/CONF_X : BIDIR;
|
||||
10K_CLK : OUTPUT;
|
||||
WR_CNF : INPUT;
|
||||
10K_D0 : OUTPUT;
|
||||
D0 : INPUT;
|
||||
|
||||
VGA_IN : INPUT;
|
||||
-- WR_COL : INPUT;
|
||||
SINC_V : OUTPUT;
|
||||
SINC_H : OUTPUT;
|
||||
SINC : OUTPUT;
|
||||
SINC_IN : INPUT;
|
||||
|
||||
XHD_RES : OUTPUT;
|
||||
XHD_WR : OUTPUT;
|
||||
XHD_RD : OUTPUT;
|
||||
|
||||
XHD1_CS[2..1] : OUTPUT;
|
||||
XHD2_CS[2..1] : OUTPUT;
|
||||
XHR_RDY : INPUT;
|
||||
|
||||
EPM_RES : INPUT;
|
||||
PW_GOOD : INPUT;
|
||||
|
||||
UNUSED65 : INPUT; -- was GND65, hack for 3000 family
|
||||
UNUSED33 : INPUT; -- was GND33, hack for 3000 family
|
||||
UNUSED1 : INPUT;
|
||||
UNUSED2 : INPUT;
|
||||
UNUSED5 : INPUT;
|
||||
UNUSED7 : INPUT;
|
||||
UNUSED22 : INPUT;
|
||||
UNUSED24 : INPUT;
|
||||
UNUSED27 : INPUT;
|
||||
UNUSED28 : INPUT;
|
||||
UNUSED49 : INPUT;
|
||||
UNUSED50 : INPUT;
|
||||
UNUSED53 : INPUT;
|
||||
UNUSED55 : INPUT;
|
||||
UNUSED63 : INPUT;
|
||||
UNUSED70 : INPUT;
|
||||
UNUSED72 : INPUT;
|
||||
UNUSED77 : INPUT;
|
||||
UNUSED78 : INPUT;
|
||||
|
||||
|
||||
|
||||
)
|
||||
VARIABLE
|
||||
|
||||
XCT[2..0] : DFF;
|
||||
CNF_ON : NODE;
|
||||
CNF_OFF : NODE;
|
||||
|
||||
CLK42 : NODE;
|
||||
|
||||
CT[3..0] : DFF;
|
||||
CTH[5..0] : DFF;
|
||||
CTV[8..0] : DFFE;
|
||||
|
||||
SINC_HT : DFF;
|
||||
SINC_VT : DFFE;
|
||||
|
||||
TURBING : NODE;
|
||||
FDD_1440 : NODE;
|
||||
NFDD_1440 : NODE;
|
||||
|
||||
CT_WG : NODE;
|
||||
CT_WG1 : NODE;
|
||||
|
||||
STWG[2..0] : DFF;
|
||||
CLK_PRC : NODE;
|
||||
WGR[4..0] : DFF;
|
||||
RDAT_X : NODE;
|
||||
|
||||
REG_P[2..0] : DFF;
|
||||
|
||||
/RESET : NODE;
|
||||
|
||||
|
||||
S144,S720 : NODE;
|
||||
|
||||
SHDD1,SHDD2 : NODE;
|
||||
THDD : NODE;
|
||||
NTHDD : NODE;
|
||||
|
||||
NO_HDD : NODE;
|
||||
|
||||
S320,S312 : NODE;
|
||||
T320 : NODE;
|
||||
NT320 : NODE;
|
||||
|
||||
SOFT_RESET : NODE;
|
||||
SOFT_RESET2 : NODE;
|
||||
|
||||
HDD_CLK : NODE;
|
||||
|
||||
LR_T[1..0] : DFF;
|
||||
|
||||
EXP_X : NODE;
|
||||
EXP_Y : NODE;
|
||||
|
||||
CTV8M : DFF;
|
||||
|
||||
CTV8C : NODE;
|
||||
|
||||
FN_NUM : NODE;
|
||||
|
||||
BEGIN
|
||||
|
||||
/RESET = DFF((EPM_RES & XHD_RES),!CT3,SOFT_RESET,);
|
||||
|
||||
-- /RESET = (EXP(!EPM_RES & EXP(EXP(EXP(EPM_RES)))) & SOFT_RESET);
|
||||
|
||||
EXP_X = EXP(TG42_IN);
|
||||
EXP_Y = EXP(TG42_IN);
|
||||
|
||||
IF (G_MODE == 0) GENERATE
|
||||
TG42_OUT = LCELL(EXP_X);
|
||||
ELSE GENERATE
|
||||
TG42_OUT = LCELL(TG42_BUF);
|
||||
END GENERATE;
|
||||
|
||||
TG42_BUF = LCELL(!TG42_IN);
|
||||
|
||||
CLK42 = TG42_IN;
|
||||
|
||||
-- CT[].clk = CLK14;
|
||||
CT[].clk = XCT1;
|
||||
CT[] = CT[] + 1;
|
||||
|
||||
-- === horizontal sinc =====
|
||||
|
||||
CTH[].clk = !CT3;
|
||||
SINC_HT.clk = !CT3;
|
||||
|
||||
IF !((CTH[] == B"XXXX11") & SINC_HT) THEN
|
||||
CTH[] = CTH[] + 1;
|
||||
ELSE
|
||||
CTH[] = GND;
|
||||
END IF;
|
||||
|
||||
-- SINC_1 = CTH5;
|
||||
SINC_1 = TRI(CTH5,VCC);
|
||||
SINC_2 = TRI(CTV8,VCC);
|
||||
|
||||
SINC_HT.d = (CTH[] == B"1101XX");
|
||||
|
||||
SINC_H = SINC_HT;
|
||||
|
||||
-- === vertical sinc =======
|
||||
|
||||
-- CTV[].clk = !CT3;
|
||||
-- SINC_VT.clk = !CT3;
|
||||
|
||||
CTV[].clk = SINC_HT;
|
||||
SINC_VT.clk = SINC_HT;
|
||||
|
||||
CTV8M.clk = SINC_HT;
|
||||
|
||||
-- CTV[].ena = (CTH[] == B"110111");
|
||||
-- SINC_VT.ena = (CTH[] == B"110111");
|
||||
CTV[].ena = VCC;
|
||||
SINC_VT.ena = VCC;
|
||||
|
||||
-- IF (CTV[] == B"100111111") THEN
|
||||
|
||||
IF (NUM == "YES") GENERATE
|
||||
|
||||
FN_NUM =(
|
||||
(CTV[8..0] == NUMBER1) or
|
||||
(CTV[8..0] == NUMBER2) or
|
||||
(CTV[8..0] == NUMBER3) or
|
||||
(CTV[8..0] == NUMBER4) or
|
||||
(CTV[8..0] == NUMBER5) or
|
||||
(CTV[8..0] == NUMBER6) or
|
||||
(CTV[8..0] == NUMBER7)
|
||||
) & !NO_HDD;
|
||||
|
||||
ELSE GENERATE
|
||||
|
||||
FN_NUM = GND;
|
||||
|
||||
END GENERATE;
|
||||
|
||||
|
||||
IF EXP((CTV[] == B"XXXXXXX11") & SINC_VT) THEN
|
||||
|
||||
(CTV[8..0]) = ((CTV[8..0]) + 1) xor (CTV8M,B"00000000");
|
||||
CTV8M = FN_NUM;
|
||||
|
||||
ELSE
|
||||
CTV[7..0] = GND;
|
||||
CTV8M = GND;
|
||||
CTV8 = GND;
|
||||
END IF;
|
||||
|
||||
SINC_VT.d = ((CTV[8..0] == B"1001111XX") or ((CTV[8..0] == B"1001101XX")) & NT320);
|
||||
|
||||
SINC_V = SINC_VT;
|
||||
|
||||
SINC = SINC_V xor SINC_H;
|
||||
|
||||
-- =============================
|
||||
|
||||
-- =========================================
|
||||
-- divide by 6
|
||||
|
||||
XCT[].clk = (TG42_IN xor !XCT1);
|
||||
XCT[].d = XCT[] + 1;
|
||||
|
||||
-- CLKZZ = 14 MHz
|
||||
|
||||
CLKZZ = TRI(XCT1,CNF_OFF);
|
||||
CLK14 = DFF(!CLK14,XCT0,,);
|
||||
|
||||
-- test exists
|
||||
|
||||
-- CNF_OFF = EXP(CNF_ON & /RESET);
|
||||
-- CNF_ON = EXP(CNF_OFF & XACS);
|
||||
|
||||
CNF_OFF = DFF(GND,GND,XACS,/RESET);
|
||||
CNF_ON = !CNF_OFF;
|
||||
|
||||
-- =========================================
|
||||
|
||||
-- ======== FDD controller ==================
|
||||
|
||||
TURBING = EXP(EXP(TURBING & !WSTB & !RSTB) & !STE & NFDD_1440);
|
||||
-- TURBING = GND;
|
||||
|
||||
CT_WG = TFF(VCC,(XCT1 xor (CT_WG & TURBING)),,);
|
||||
|
||||
STWG[].clk = (CT_WG xor STWG2);
|
||||
STWG[].d = STWG[] + 1;
|
||||
|
||||
CLK_WG = STWG2;
|
||||
|
||||
-- CLK_PRC = STWG0;
|
||||
CLK_PRC = CT_WG;
|
||||
|
||||
CT_WG1 = EXP(EXP(XCT1 & FDD_1440) & EXP(CT0 & NFDD_1440));
|
||||
|
||||
WGR[].clk = CT_WG1;
|
||||
|
||||
IF !FDAT THEN
|
||||
TABLE WGR[3..0] => WGR[3..0].d;
|
||||
0 => 4; 1 => 5; 2 => 4; 3 => 5;
|
||||
4 => 6; 5 => 7; 6 => 8; 7 => 8;
|
||||
8 => 9; 9 => 9; 10 => 10; 11 => 11;
|
||||
12 => 12; 13 => 13; 14 => 14; 15 => 15;
|
||||
END TABLE;
|
||||
WGR4.d = WGR4;
|
||||
ELSE
|
||||
IF WGR[3..0] == 0 THEN
|
||||
WGR[3..0].d = 3;
|
||||
WGR4.d = WGR4;
|
||||
ELSE
|
||||
WGR[].d = WGR[] + 1;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
QDAT = WGR4;
|
||||
RDAT_X = EXP(EXP(RDAT_X & EXP(!RDAT & !CT_WG1)) & EXP(RDAT & !CT_WG1));
|
||||
-- FDAT = DFF((RDAT_X or !DFF(RDAT_X,CT_WG1,,)),CT_WG1,,);
|
||||
FDAT = DFF((RDAT_X or EXP(DFF(RDAT_X,CT_WG1,,))),CT_WG1,,);
|
||||
-- ==========================================================
|
||||
-- now not complete!
|
||||
|
||||
AUD = CT3;
|
||||
BEEP = GND;
|
||||
|
||||
-- /CONF_X = TRI(GND,!/RESET);
|
||||
|
||||
/CONF_X = OPNDRN(/RESET);
|
||||
|
||||
-- 10K_CLK = WR_CNF; -- now not protect!
|
||||
|
||||
10K_CLK = DFF((WR_CNF & CNF_OFF) or ((HDD_C0 or FDD_C2) & CNF_ON),CLK42,,);
|
||||
|
||||
10K_D0 = DFFE(D0,10K_CLK,S720,(S144 & /RESET),CNF_OFF);
|
||||
|
||||
DENS_X = VCC;
|
||||
|
||||
-- === now NOT PRECOMP! =====
|
||||
|
||||
-- WDAT = WD;
|
||||
|
||||
WDAT = REG_P2;
|
||||
|
||||
REG_P[].clk = !CLK_PRC;
|
||||
|
||||
-- CASE WD IS
|
||||
-- WHEN 1 => REG_P[].d = (GND,SL,!(SL or SR),SR);
|
||||
-- WHEN 0 => REG_P[].d = (EXP(EXP(REG_P2)),REG_P[1..0],GND);
|
||||
-- END CASE;
|
||||
|
||||
-- CASE (DFF(WD,CLK_WG,,),DFF((SL & TR43),CLK_WG,,),DFF((SR & TR43),CLK_WG,,)) IS
|
||||
|
||||
LR_T[].clk = STWG2;
|
||||
-- LR_T[].clk = CLK_WG;
|
||||
|
||||
LR_T[].d = ((WD & !(SL & TR43)),(WD & !(SR & TR43)));
|
||||
|
||||
CASE LR_T[] IS
|
||||
WHEN 0 => REG_P[1..0] = (REG_P[1..0] - 1) & EXP(REG_P[1..0] == 0);
|
||||
REG_P[2] = EXP(EXP(REG_P[1..0] == 1));
|
||||
-- REG_P[2] = (REG_P[1..0] == 1);
|
||||
WHEN 1 => REG_P[1..0] = 1; REG_P[2] = GND;
|
||||
WHEN 2 => REG_P[1..0] = 3; REG_P[2] = GND;
|
||||
WHEN 3 => REG_P[1..0] = 2; REG_P[2] = GND;
|
||||
END CASE;
|
||||
%
|
||||
CASE (WD,DFF((SL & TR43),CLK_WG,,),DFF((SR & TR43),CLK_WG,,)) IS
|
||||
WHEN B"0XX" => REG_P[1..0] = (REG_P[1..0] - 1) & EXP(REG_P[1..0] == 0);
|
||||
WHEN B"100" => REG_P[1..0] = 2;
|
||||
WHEN B"110" => REG_P[1..0] = 1;
|
||||
WHEN B"101" => REG_P[1..0] = 3;
|
||||
WHEN B"111" => REG_P[1..0] = 2;
|
||||
END CASE;
|
||||
%
|
||||
|
||||
%
|
||||
CASE WD IS
|
||||
WHEN 0 => REG_P[3] = EXP(EXP(REG_P[1..0] == 1));
|
||||
WHEN 1 => REG_P[3] = GND;
|
||||
END CASE;
|
||||
%
|
||||
|
||||
-- === Port Controls ====================================
|
||||
%
|
||||
FDD_C0 - 0 - WG93 / 1 - kmps/ p_dos
|
||||
FDD_C1 - 0 - write / 1 - read
|
||||
FDD_C2 - 0 - no / 1 - CS_WG/ strobe
|
||||
|
||||
HDD_C0 - strobe
|
||||
HDD_C[2..1] = 00 - SYS_FN, 01 - SYS_FN, 10 - HDD1/2, 11 - CMOS
|
||||
HDD_C3 - 0 - HD_CS1, 1 HD_CS3 / 0 CMOS_DAT, 1 - CMOS_ADR
|
||||
|
||||
HDD_C[3..0] = 0001, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set 1.44/720
|
||||
HDD_C[3..0] = 1001, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set 320/312 lines
|
||||
HDD_C[3..0] = 0011, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set HDD1/HDD2
|
||||
HDD_C[3..0] = 1011, FDD_C[2..1] = 00; -> FDD_C0 = 0 -> soft_reset!
|
||||
HDD_C[3..0] = X101, FDD_C[2..1] = XX; -> HDD1/2 rd/wr
|
||||
|
||||
%
|
||||
|
||||
SOFT_RESET = !((HDD_C[] == B"1011") & (FDD_C[] == B"000"));
|
||||
SOFT_RESET2 = !((HDD_C[] == B"1011") & (FDD_C[] == B"001"));
|
||||
|
||||
-- FDD switch
|
||||
|
||||
-- NFDD_1440 = EXP(FDD_1440 & S720 & /RESET);
|
||||
-- FDD_1440 = EXP(NFDD_1440 & S144);
|
||||
FDD_1440 = 10K_D0;
|
||||
NFDD_1440 = !10K_D0;
|
||||
|
||||
S144 = EXP((HDD_C[] == B"0001") & (FDD_C[] == B"001"));
|
||||
S720 = EXP((HDD_C[] == B"0001") & (FDD_C[] == B"000"));
|
||||
|
||||
-- Screen Switch
|
||||
|
||||
T320 = EXP(NT320 & S320 & /RESET);
|
||||
NT320 = EXP(T320 & S312);
|
||||
|
||||
S312 = EXP((HDD_C[] == B"1001") & (FDD_C[] == B"001"));
|
||||
S320 = EXP((HDD_C[] == B"1001") & (FDD_C[] == B"000"));
|
||||
|
||||
-- HDD Switch
|
||||
|
||||
-- THDD = EXP(NTHDD & SHDD2 & /RESET);
|
||||
-- NTHDD = EXP(THDD & SHDD1);
|
||||
|
||||
THDD = EXP(NTHDD & NO_HDD & SHDD2 & /RESET & SOFT_RESET2);
|
||||
NTHDD = EXP(THDD & NO_HDD & SHDD1 & /RESET & SOFT_RESET2);
|
||||
NO_HDD = EXP(NTHDD & THDD & SHDD1 & SHDD2);
|
||||
|
||||
SHDD2 = EXP((HDD_C[] == B"0011") & (FDD_C[] == B"001"));
|
||||
SHDD1 = EXP((HDD_C[] == B"0011") & (FDD_C[] == B"000"));
|
||||
|
||||
-- Control signals
|
||||
|
||||
WR_PDOS = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2);
|
||||
/WG_WR = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X00")),HDD_CLK,,FDD_C2);
|
||||
/WG_RD = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X10")),HDD_CLK,,FDD_C2);
|
||||
|
||||
CMOS_DWR = DFF(!((HDD_C[] == B"1110") & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2);
|
||||
CMOS_AS =!DFF(!((HDD_C[] == B"0110") & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2);
|
||||
CMOS_DRD = DFF(!((HDD_C[] == B"1110") & (FDD_C[] == B"X10")),HDD_CLK,,FDD_C2);
|
||||
|
||||
-- HD_DIR = !HDD_C1; -- ????????????
|
||||
HD_DIR = XHD_RD;
|
||||
|
||||
-- HD_CS = GND;
|
||||
-- HD_CS = CTV8M;
|
||||
HD_CS = (CTV8M and /RESET);
|
||||
|
||||
|
||||
-- HD_CS = !/RESET;
|
||||
|
||||
-- XHD_RES = VCC;
|
||||
|
||||
-- XHD_RES = DFF(PW_GOOD,SINC_V,,);
|
||||
XHD_RES = DFF(PW_GOOD,SINC_V,EPM_RES,);
|
||||
|
||||
-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),CLK42,,);
|
||||
-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),CLK42,,);
|
||||
|
||||
-- HDD_CLK = EXP(EXP(HDD_C0));
|
||||
HDD_CLK = 10K_CLK;
|
||||
|
||||
-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1 or !HDD_CLK),CLK42,,HDD_C0);
|
||||
-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1 or !HDD_CLK),CLK42,,HDD_C0);
|
||||
-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,HDD_C0);
|
||||
-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,HDD_C0);
|
||||
XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,(HDD_C0 and /RESET));
|
||||
XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,(HDD_C0 and /RESET));
|
||||
|
||||
-- XHD1_CS1 = DFF(!((HDD_C[] == B"010X") & NTHDD),CLK42,,);
|
||||
-- XHD1_CS2 = DFF(!((HDD_C[] == B"110X") & NTHDD),CLK42,,);
|
||||
|
||||
-- XHD2_CS1 = DFF(!((HDD_C[] == B"010X") & THDD),CLK42,,);
|
||||
-- XHD2_CS2 = DFF(!((HDD_C[] == B"110X") & THDD),CLK42,,);
|
||||
|
||||
-- XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,);
|
||||
-- XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,);
|
||||
XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,/RESET);
|
||||
XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,/RESET);
|
||||
|
||||
-- XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,);
|
||||
-- XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,);
|
||||
XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,/RESET);
|
||||
XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,/RESET);
|
||||
|
||||
|
||||
END;
|
||||
|
||||
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Reference in New Issue
Block a user