Tolik-Trek/Sprinter-BIOS
1
0
Fork 0
mirror of https://github.com/Tolik-Trek/Sprinter-BIOS.git synced 2026-06-15 01:11:47 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

Переход на относительные URL подмодулей

Browse Source
This commit is contained in:
Анатолий Белянский 2026-05-16 20:21:50 +10:00 committed by Tolik
parent edfe87f12e
commit c306fb606c
275 changed files with 19757 additions and 55893 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Shared_Includes

@ -1 +1 @@
Subproject commit 2fec6202f716cfa3ed48fb9bfd79d1081cc2721b
Subproject commit 591d3212c9341f17d6dd034bf2b8da91bd2f6107

0
src/ZX_ROMS/new/SP_128.bin → ZX_ROMS/new/SP_128.bin
View File

0
src/ZX_ROMS/new/SP_TRDOS.bin → ZX_ROMS/new/SP_TRDOS.bin
View File

0
src/ZX_ROMS/new/SP__48.bin → ZX_ROMS/new/SP__48.bin
View File

0
src/ZX_ROMS/new/ZX_EXP.bin → ZX_ROMS/new/ZX_EXP.bin
View File

0
src/ZX_ROMS/new/ZX_EXP2.bin → ZX_ROMS/new/ZX_EXP2.bin
View File

466
src/bin/bmp_extract.dpr → bin/bmp_extract.dpr
View File

@ -1,233 +1,233 @@
program bmp_extract;
{$APPTYPE CONSOLE}
uses
SysUtils;
const
RGB3 = 3;
RGB4 = 4;
type
BITMAPFILEHEADER = packed record
bfType: word;
bfSize: longint;
bfReserved1: word;
bfReserved2: word;
bfOffBits: longint;
end;
BITMAPINFOHEADER = packed record
biSize: longint;
biWidth: longint;
biHeight: longint;
biPlanes: word;
biBitCount: word;
biCompression: longint;
biSizeImage: longint;
biXPelsPerMeter: longint;
biYPelsPerMeter: longint;
biClrUsed: longint;
biClrImportant: longint;
end;
RGBQUAD = record
rgbBlue: byte;
rgbGreen: byte;
rgbRed: byte;
rgbReserved: byte;
end;
procedure MsgHelp;
begin
writeln('Usage:');
writeln(' bmp_extract.exe <BMP FILE> <params> ...');
writeln('<params>:');
writeln(' /pn <file name> - output palette file-name');
writeln(' /dn <file name> - output data file-name');
writeln(' /pt <3 or 4> - palette type');
writeln;
end;
procedure MsgWrong;
begin
writeln('Unsupported BMP format');
writeln('Accept only 128x72 px, 8-bit colors, no compression');
writeln;
end;
procedure SavePalette(var buf: array of byte; fn: string; pal_type: longint);
var
f: file of byte;
i: longint;
buf4: array [0..3] of byte;
begin
{$I-}
AssignFile(f, fn);
rewrite(f);
case pal_type of
RGB3:
for i:= 0 to 255 do
begin
move(buf[i*4], buf4[0], 4);
BlockWrite(f, buf4[0], 3);
end;
RGB4:
BlockWrite(f, buf[0], length(buf));
end;
CloseFile(f);
{$I+}
IOResult;
end;
procedure SaveBuf(var buf: array of byte; fn: string);
var
f: file of byte;
begin
{$I-}
AssignFile(f, fn);
rewrite(f);
BlockWrite(f, buf[0], length(buf));
CloseFile(f);
{$I+}
IOResult;
end;
function PalTypeToStr(t: longint): string;
begin
case t of
RGB3: result:= 'RGB3';
RGB4: result:= 'RGB4';
else result:= 'RGB unknown';
end;
end;
var
TFileHeader: BITMAPFILEHEADER;
TInfoHeader: BITMAPINFOHEADER;
f: file of byte;
bmp_file_name, pal_file_name, dat_file_name: string;
i: longint;
pal_type: byte;
buf: array of byte;
begin
ExitCode:= 0;
writeln('Extractor BMP-files for Sprinter BIOS logo');
writeln('Copyright (c) 2022 Sprinter Team');
// default params
bmp_file_name:= 'logo.bmp';
pal_file_name:= 'logo_pal.bin';
dat_file_name:= 'logo_dat.bin';
pal_type:= RGB4;
if ParamStr(1) = '/?' then
begin
MsgHelp;
exit;
end;
// override params
if ParamStr(1) <> '' then
bmp_file_name:= ParamStr(1);
for i:= 2 to ParamCount do
begin
// palette file name
if LowerCase(ParamStr(i)) = '/pn' then
pal_file_name:= trim(ParamStr(i+1));
// data file name
if LowerCase(ParamStr(i)) = '/dn' then
dat_file_name:= trim(ParamStr(i+1));
if (LowerCase(ParamStr(i)) = '/pt') and (ParamStr(i+1) = '3') then
pal_type:= RGB3;
end;
// ---------------------------------------------------------------------------
AssignFile(f, bmp_file_name);
{$I-}
Reset(f);
{$I+}
i:= IOResult;
if i <> 0 then
begin
writeln('IO error ', i, ' during open ['+bmp_file_name+'] file');
MsgHelp;
ExitCode:= 1;
exit;
end;
{$I-}
BlockRead(f, TFileHeader, SizeOf(TFileHeader));
BlockRead(f, TInfoHeader, SizeOf(TInfoHeader));
{$I+}
i:= IOResult;
if i <> 0 then
begin
writeln('IO error ', i, ' during open ['+bmp_file_name+'] file');
ExitCode:= 1;
exit;
end;
// writeln('FILE, ', SizeOf(TFileHeader));
// writeln('bfType: ', TFileHeader.bfType);
// writeln('bfSize: ', TFileHeader.bfSize);
// writeln('bfReserved1: ', TFileHeader.bfReserved1);
// writeln('bfReserved2: ', TFileHeader.bfReserved2);
// writeln('bfOffBits: ', TFileHeader.bfOffBits);
//
// writeln('INFO, ', SizeOf(TInfoHeader));
// writeln('biSize: ', TInfoHeader.biSize);
// writeln('biWidth: ', TInfoHeader.biWidth);
// writeln('biHeight: ', TInfoHeader.biHeight);
// writeln('biPlanes: ', TInfoHeader.biPlanes);
// writeln('biBitCount: ', TInfoHeader.biBitCount);
// writeln('biCompression: ', TInfoHeader.biCompression);
// writeln('biSizeImage: ', TInfoHeader.biSizeImage);
// writeln('biXPelsPerMeter: ', TInfoHeader.biXPelsPerMeter);
// writeln('biYPelsPerMeter: ', TInfoHeader.biYPelsPerMeter);
// writeln('biClrUsed: ', TInfoHeader.biClrUsed);
// writeln('biClrImportant: ', TInfoHeader.biClrImportant);
// check acceptable bmp format
if (TFileHeader.bfType <> $4D42)
or (TInfoHeader.biWidth <> 128)
or (TInfoHeader.biHeight <> 72)
or (TInfoHeader.biBitCount <> 8)
or (TInfoHeader.biCompression <> 0)
then
begin
MsgWrong;
ExitCode:= 1;
exit;
end;
with TInfoHeader do
writeln('File ['+bmp_file_name+'], found ',biBitCount,' bit BMP ',biWidth,'x',biHeight,', output '+PalTypeToStr(pal_type)+' ['+pal_file_name+'] and ['+dat_file_name+']');
// make palette
SetLength(buf, 1024);
FillChar(buf[0], length(buf), 0);
BlockRead(f, buf[0], (TFileHeader.bfOffBits - SizeOf(TFileHeader) - SizeOf(TInfoHeader)) );
SavePalette(buf, pal_file_name, pal_type);
// make data
SetLength(buf, TInfoHeader.biWidth * TInfoHeader.biHeight);
FillChar(buf[0], length(buf), 0);
BlockRead(f, buf[0], length(buf));
SaveBuf(buf, dat_file_name);
CloseFile(f);
writeln('Done.');
end.
program bmp_extract;
{$APPTYPE CONSOLE}
uses
SysUtils;
const
RGB3 = 3;
RGB4 = 4;
type
BITMAPFILEHEADER = packed record
bfType: word;
bfSize: longint;
bfReserved1: word;
bfReserved2: word;
bfOffBits: longint;
end;
BITMAPINFOHEADER = packed record
biSize: longint;
biWidth: longint;
biHeight: longint;
biPlanes: word;
biBitCount: word;
biCompression: longint;
biSizeImage: longint;
biXPelsPerMeter: longint;
biYPelsPerMeter: longint;
biClrUsed: longint;
biClrImportant: longint;
end;
RGBQUAD = record
rgbBlue: byte;
rgbGreen: byte;
rgbRed: byte;
rgbReserved: byte;
end;
procedure MsgHelp;
begin
writeln('Usage:');
writeln(' bmp_extract.exe <BMP FILE> <params> ...');
writeln('<params>:');
writeln(' /pn <file name> - output palette file-name');
writeln(' /dn <file name> - output data file-name');
writeln(' /pt <3 or 4> - palette type');
writeln;
end;
procedure MsgWrong;
begin
writeln('Unsupported BMP format');
writeln('Accept only 128x72 px, 8-bit colors, no compression');
writeln;
end;
procedure SavePalette(var buf: array of byte; fn: string; pal_type: longint);
var
f: file of byte;
i: longint;
buf4: array [0..3] of byte;
begin
{$I-}
AssignFile(f, fn);
rewrite(f);
case pal_type of
RGB3:
for i:= 0 to 255 do
begin
move(buf[i*4], buf4[0], 4);
BlockWrite(f, buf4[0], 3);
end;
RGB4:
BlockWrite(f, buf[0], length(buf));
end;
CloseFile(f);
{$I+}
IOResult;
end;
procedure SaveBuf(var buf: array of byte; fn: string);
var
f: file of byte;
begin
{$I-}
AssignFile(f, fn);
rewrite(f);
BlockWrite(f, buf[0], length(buf));
CloseFile(f);
{$I+}
IOResult;
end;
function PalTypeToStr(t: longint): string;
begin
case t of
RGB3: result:= 'RGB3';
RGB4: result:= 'RGB4';
else result:= 'RGB unknown';
end;
end;
var
TFileHeader: BITMAPFILEHEADER;
TInfoHeader: BITMAPINFOHEADER;
f: file of byte;
bmp_file_name, pal_file_name, dat_file_name: string;
i: longint;
pal_type: byte;
buf: array of byte;
begin
ExitCode:= 0;
writeln('Extractor BMP-files for Sprinter BIOS logo');
writeln('Copyright (c) 2022 Sprinter Team');
// default params
bmp_file_name:= 'logo.bmp';
pal_file_name:= 'logo_pal.bin';
dat_file_name:= 'logo_dat.bin';
pal_type:= RGB4;
if ParamStr(1) = '/?' then
begin
MsgHelp;
exit;
end;
// override params
if ParamStr(1) <> '' then
bmp_file_name:= ParamStr(1);
for i:= 2 to ParamCount do
begin
// palette file name
if LowerCase(ParamStr(i)) = '/pn' then
pal_file_name:= trim(ParamStr(i+1));
// data file name
if LowerCase(ParamStr(i)) = '/dn' then
dat_file_name:= trim(ParamStr(i+1));
if (LowerCase(ParamStr(i)) = '/pt') and (ParamStr(i+1) = '3') then
pal_type:= RGB3;
end;
// ---------------------------------------------------------------------------
AssignFile(f, bmp_file_name);
{$I-}
Reset(f);
{$I+}
i:= IOResult;
if i <> 0 then
begin
writeln('IO error ', i, ' during open ['+bmp_file_name+'] file');
MsgHelp;
ExitCode:= 1;
exit;
end;
{$I-}
BlockRead(f, TFileHeader, SizeOf(TFileHeader));
BlockRead(f, TInfoHeader, SizeOf(TInfoHeader));
{$I+}
i:= IOResult;
if i <> 0 then
begin
writeln('IO error ', i, ' during open ['+bmp_file_name+'] file');
ExitCode:= 1;
exit;
end;
// writeln('FILE, ', SizeOf(TFileHeader));
// writeln('bfType: ', TFileHeader.bfType);
// writeln('bfSize: ', TFileHeader.bfSize);
// writeln('bfReserved1: ', TFileHeader.bfReserved1);
// writeln('bfReserved2: ', TFileHeader.bfReserved2);
// writeln('bfOffBits: ', TFileHeader.bfOffBits);
//
// writeln('INFO, ', SizeOf(TInfoHeader));
// writeln('biSize: ', TInfoHeader.biSize);
// writeln('biWidth: ', TInfoHeader.biWidth);
// writeln('biHeight: ', TInfoHeader.biHeight);
// writeln('biPlanes: ', TInfoHeader.biPlanes);
// writeln('biBitCount: ', TInfoHeader.biBitCount);
// writeln('biCompression: ', TInfoHeader.biCompression);
// writeln('biSizeImage: ', TInfoHeader.biSizeImage);
// writeln('biXPelsPerMeter: ', TInfoHeader.biXPelsPerMeter);
// writeln('biYPelsPerMeter: ', TInfoHeader.biYPelsPerMeter);
// writeln('biClrUsed: ', TInfoHeader.biClrUsed);
// writeln('biClrImportant: ', TInfoHeader.biClrImportant);
// check acceptable bmp format
if (TFileHeader.bfType <> $4D42)
or (TInfoHeader.biWidth <> 128)
or (TInfoHeader.biHeight <> 72)
or (TInfoHeader.biBitCount <> 8)
or (TInfoHeader.biCompression <> 0)
then
begin
MsgWrong;
ExitCode:= 1;
exit;
end;
with TInfoHeader do
writeln('File ['+bmp_file_name+'], found ',biBitCount,' bit BMP ',biWidth,'x',biHeight,', output '+PalTypeToStr(pal_type)+' ['+pal_file_name+'] and ['+dat_file_name+']');
// make palette
SetLength(buf, 1024);
FillChar(buf[0], length(buf), 0);
BlockRead(f, buf[0], (TFileHeader.bfOffBits - SizeOf(TFileHeader) - SizeOf(TInfoHeader)) );
SavePalette(buf, pal_file_name, pal_type);
// make data
SetLength(buf, TInfoHeader.biWidth * TInfoHeader.biHeight);
FillChar(buf[0], length(buf), 0);
BlockRead(f, buf[0], length(buf));
SaveBuf(buf, dat_file_name);
CloseFile(f);
writeln('Done.');
end.

0
src/bin/bmp_extract.exe → bin/bmp_extract.exe
View File

0
src/bin/hrust.exe → bin/hrust.exe
View File

0
src/bin/mhmt → bin/mhmt
View File

20
src/bios/BIOS.asm → bios/BIOS.asm
View File

@ -16,7 +16,7 @@
;---------------------------------------;
;-----------[Shared Includes]-----------
INCLUDE 'src/bios/shared/includes.inc' ; Includes
INCLUDE 'bios/shared/includes.inc' ; Includes
;---------------------------------------
@ -41,16 +41,14 @@
print ()
if detected_os == "Windows" then
pack_prog = "src\\bin\\hrust.exe Build\\Bin\\temp\\MAIN.PAK Build\\Bin\\temp\\MAIN.BIN"
elseif detected_os == "MacOS" then
pack_prog = "src/bin/mhmt -hst -zxh Build/Bin/temp/MAIN.BIN Build/Bin/temp/MAIN.PAK"
elseif detected_os == "Linux" then
pack_prog = "src/bin/mhmt -hst -zxh Build/Bin/temp/MAIN.BIN Build/Bin/temp/MAIN.PAK"
pack_prog = "bin\\hrust.exe Build\\Bin\\temp\\MAIN.PAK Build\\Bin\\temp\\MAIN.BIN"
else
pack_prog = "bin/mhmt -hst -zxh Build/Bin/temp/MAIN.BIN Build/Bin/temp/MAIN.PAK"
end
-- ª®¬¯¨«ïæ¨ï ¤«ï ¯®«ã祭¨ï ᦠ⮣® ä ©«  MAIN ¨ 宫®á⮩ ¯à®å®¤ Set_Pictures.asm
if (os.execute("sjasmplus -DPREBUILD=1 -Wall --msg=war --nologo --syntax=w --fullpath --lst=Build/Prebuilds.LST SRC/BIOS/ROM/SETUP/MAIN.ASM")) then
if (os.execute("sjasmplus -DPREBUILD=1 -Wall --msg=war --nologo --syntax=w --fullpath --lst=Build/Prebuilds.LST BIOS/ROM/SETUP/MAIN.ASM")) then
print("--[ MAIN.ASM Prebuild DONE ]--")
if (os.execute(pack_prog)) then
print("--[ Hrusting MAIN.BIN DONE ]--")
@ -71,7 +69,7 @@
;----------[MAIN's referenses]----------; Š®¬¯¨«ïæ¨ï ¤«ï ¯®«ã祭¨ï  ¤à¥á®¢ ¬¥â®ª ¨ ¯à®æ¥¤ãà
MMU 2 e, 18 ; áâà ­¨æ  18 ¢ ¡ ­ªã 2 ¨ ¯à®¢¥àª  ­  £à ­¨æë.
ORG COMPILE_ADDR.MAIN
INCLUDE 'src/bios/ROM/SETUP/MAIN.asm'
INCLUDE 'bios/ROM/SETUP/MAIN.asm'
;---------------------------------------
ENDIF
@ -83,7 +81,7 @@
DEFINE+ IsInBIOS 1
OUTPUT 'Build/Bin/EXP.BIN'
ShowInfo 'EXP block Start', 0 ; !!!!! test
INCLUDE 'src/bios/EXP/EXP.asm'
INCLUDE 'bios/EXP/EXP.asm'
ShowInfo 'EXP block End', 0 ; !!!!! test
OUTEND
;---------------------------------------
@ -97,7 +95,7 @@
DEFINE+ IsInBIOS 0
OUTPUT 'Build/Bin/ROM.BIN'
ShowInfo 'ROM block Start', 0 ; !!!!! test
INCLUDE 'src/bios/ROM/ROM.asm'
INCLUDE 'bios/ROM/ROM.asm'
ShowInfo 'ROM block End', 0 ; !!!!! test
OUTEND
UNDEFINE IsInBIOS
@ -135,7 +133,7 @@
MMU 1 e, 1 ; áâà ­¨æ  1 ¢ ¡ ­ªã 1 ¨ ¯à®¢¥àª  ­  £à ­¨æë.
ORG ROM_MAP.LOGO
OUTPUT 'Build/Bin/LOGO.BIN'
INCLUDE 'src/bios/logo/Set_Pictures.asm'
INCLUDE 'bios/logo/Set_Pictures.asm'
OUTEND
;---------------------------------------
;

12
src/bios/BUILD.a80 → bios/BUILD.a80
View File

@ -2,7 +2,7 @@
;------------[LUA functions]------------;
includelua 'Shared_Includes/LUA/Functions.lua'
;---------------------------------------;
DEFINE PICTURE_FILE './src/bios/logo/psfathers.bmp'
DEFINE PICTURE_FILE './bios/logo/psfathers.bmp'
LUA PASS1
@ -20,8 +20,8 @@
*/
INCLUDE 'shared/defines.inc'
DEFINE IMG_RECOVERY 'src/bios/shared/recovery.img'
;DEFINE IMG_RECOVERY 'src/bios/shared/recovery_tst.img'
DEFINE IMG_RECOVERY 'bios/shared/recovery.img'
;DEFINE IMG_RECOVERY 'bios/shared/recovery_tst.img'
;
;[--------------------------------------------------------------------------]
@ -32,9 +32,9 @@
ENDM
;[--------------------------------------------------------------------------]
DEFINE SP_128_BIN INCBIN 'src/ZX_ROMS/NEW/SP_128.BIN'
DEFINE SP__48_BIN INCBIN 'src/ZX_ROMS/NEW/SP__48.BIN'
DEFINE SP_TRDOS_BIN INCBIN 'src/ZX_ROMS/NEW/SP_TRDOS.BIN'
DEFINE SP_128_BIN INCBIN 'ZX_ROMS/NEW/SP_128.BIN'
DEFINE SP__48_BIN INCBIN 'ZX_ROMS/NEW/SP__48.BIN'
DEFINE SP_TRDOS_BIN INCBIN 'ZX_ROMS/NEW/SP_TRDOS.BIN'
;[--------------------------------------------------------------------------]
MACRO ROM_BUILD bitstream

1546
src/bios/exp/BIOS_FUNC.asm → bios/exp/BIOS_FUNC.asm
View File

File diff suppressed because it is too large Load Diff

0
src/bios/exp/DCP.ASM → bios/exp/DCP.ASM
View File

3278
src/bios/exp/EXP.asm → bios/exp/EXP.asm
View File

File diff suppressed because it is too large Load Diff

1560
src/bios/exp/EXTENDED/FDD_DRIVER.asm → bios/exp/EXTENDED/FDD_DRIVER.asm
View File

File diff suppressed because it is too large Load Diff

1874
src/bios/exp/EXTENDED/IDE/ATAPI_DRV.ASM → bios/exp/EXTENDED/IDE/ATAPI_DRV.ASM
View File

File diff suppressed because it is too large Load Diff

1468
src/bios/exp/EXTENDED/IDE/ATA_DRV.ASM → bios/exp/EXTENDED/IDE/ATA_DRV.ASM
View File

File diff suppressed because it is too large Load Diff

0
src/bios/exp/EXTENDED/IDE/shared.asm → bios/exp/EXTENDED/IDE/shared.asm
View File

0
src/bios/exp/EXTENDED/RAM_DISK_DRIVER.asm → bios/exp/EXTENDED/RAM_DISK_DRIVER.asm
View File

346
src/bios/exp/FONT.ASM → bios/exp/FONT.ASM
View File

@ -1,174 +1,174 @@
; ‡­ ª®£¥­¥à â®à
LUA PASS1
fL = {}
for i = 1,16 do
fL[i]={}
end
-- 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
fL[1][1] = " -------- -######- -######- -##-##-- ---#---- --###--- ---#---- -------- ######## -------- ######## ----#### --####-- --###### -####### ---##--- "
fL[2][1] = " -------- #------# ######## #######- --###--- -#####-- ---#---- -------- ######## --####-- ##----## -----### -##--##- --##--## -##---## ##-##-## "
fL[3][1] = " -------- #-#--#-# ##-##-## #######- -#####-- --###--- --###--- ---##--- ###--### -##--##- #--##--# ----#### -##--##- --###### -####### --####-- "
fL[4][1] = " -------- #------# ######## #######- #######- #######- -#####-- --####-- ##----## -#----#- #-####-# -#####-# -##--##- --##---- -##---## ###--### "
fL[5][1] = " -------- #-####-# ##----## -#####-- -#####-- #######- #######- --####-- ##----## -#----#- #-####-# ##--##-- --####-- --##---- -##---## ###--### "
fL[6][1] = " -------- #--##--# ###--### --###--- --###--- ##-#-##- -#####-- ---##--- ###--### -##--##- #--##--# ##--##-- ---##--- -###---- -##--### --####-- "
fL[7][1] = " -------- #------# ######## ---#---- ---#---- ---#---- ---#---- -------- ######## --####-- ##----## ##--##-- -######- ####---- ###--##- ##-##-## "
fL[8][1] = " -------- -######- -######- -------- -------- --###--- --###--- -------- ######## -------- ######## -####--- ---##--- ###----- ##------ ---##--- "
-- 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
fL[1][2] = " #------- ------#- ---##--- -##--##- -####### --#####- -------- ---##--- ---##--- ---##--- -------- -------- -------- -------- -------- -------- "
fL[2][2] = " ###----- ----###- --####-- -##--##- ##-##-## -##---## -------- --####-- --####-- ---##--- ---##--- --##---- -------- --#--#-- ---##--- ######## "
fL[3][2] = " #####--- --#####- -######- -##--##- ##-##-## --###--- -------- -######- -######- ---##--- ----##-- -##----- ##------ -##--##- --####-- ######## "
fL[4][2] = " #######- #######- ---##--- -##--##- -####-## -##-##-- -------- ---##--- ---##--- ---##--- #######- #######- ##------ ######## -######- -######- "
fL[5][2] = " #####--- --#####- ---##--- -##--##- ---##-## -##-##-- -######- -######- ---##--- -######- ----##-- -##----- ##------ -##--##- ######## --####-- "
fL[6][2] = " ###----- ----###- -######- -------- ---##-## --###--- -######- --####-- ---##--- --####-- ---##--- --##---- #######- --#--#-- ######## ---##--- "
fL[7][2] = " #------- ------#- --####-- -##--##- ---##-## ##--##-- -######- ---##--- ---##--- ---##--- -------- -------- -------- -------- -------- -------- "
fL[8][2] = " -------- -------- ---##--- -------- -------- -####--- -------- ######## -------- -------- -------- -------- -------- -------- -------- -------- "
-- 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
fL[1][3] = " -------- --##---- -##-##-- -##-##-- --##---- -------- --###--- -##----- ---##--- -##----- -------- -------- -------- -------- -------- -----##- "
fL[2][3] = " -------- -####--- -##-##-- -##-##-- -#####-- ##---##- -##-##-- -##----- --##---- --##---- -##--##- --##---- -------- -------- -------- ----##-- "
fL[3][3] = " -------- -####--- -##-##-- #######- ##------ ##--##-- --###--- ##------ -##----- ---##--- --####-- --##---- -------- -------- -------- ---##--- "
fL[4][3] = " -------- --##---- -------- -##-##-- -####--- ---##--- -###-##- -------- -##----- ---##--- ######## ######-- -------- ######-- -------- --##---- "
fL[5][3] = " -------- --##---- -------- #######- ----##-- --##---- ##-###-- -------- -##----- ---##--- --####-- --##---- -------- -------- -------- -##----- "
fL[6][3] = " -------- -------- -------- -##-##-- #####--- -##--##- ##--##-- -------- --##---- --##---- -##--##- --##---- --##---- -------- --##---- ##------ "
fL[7][3] = " -------- --##---- -------- -##-##-- --##---- ##---##- -###-##- -------- ---##--- -##----- -------- -------- --##---- -------- --##---- #------- "
fL[8][3] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -##----- -------- -------- -------- "
-- 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
fL[1][4] = " -#####-- --##---- -####--- -####--- ---###-- ######-- --###--- ######-- -####--- -####--- -------- -------- ---##--- -------- -##----- -####--- "
fL[2][4] = " ##---##- -###---- ##--##-- ##--##-- --####-- ##------ -##----- ##--##-- ##--##-- ##--##-- --##---- --##---- --##---- -------- --##---- ##--##-- "
fL[3][4] = " ##--###- --##---- ----##-- ----##-- -##-##-- #####--- ##------ ----##-- ##--##-- ##--##-- --##---- --##---- -##----- ######-- ---##--- ----##-- "
fL[4][4] = " ##-####- --##---- --###--- --###--- ##--##-- ----##-- #####--- ---##--- -####--- -#####-- -------- -------- ##------ -------- ----##-- ---##--- "
fL[5][4] = " ####-##- --##---- -##----- ----##-- #######- ----##-- ##--##-- --##---- ##--##-- ----##-- -------- -------- -##----- -------- ---##--- --##---- "
fL[6][4] = " ###--##- --##---- ##--##-- ##--##-- ----##-- ##--##-- ##--##-- --##---- ##--##-- ---##--- --##---- --##---- --##---- ######-- --##---- -------- "
fL[7][4] = " -#####-- ######-- ######-- -####--- ---####- -####--- -####--- --##---- -####--- -###---- --##---- --##---- ---##--- -------- -##----- --##---- "
fL[8][4] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -##----- -------- -------- -------- -------- "
-- 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
fL[1][5] = " -#####-- --##---- ######-- --####-- #####--- #######- #######- --####-- ##--##-- -####--- ---####- ###--##- ####---- ##---##- ##---##- --###--- "
fL[2][5] = " ##---##- -####--- -##--##- -##--##- -##-##-- -##---#- -##---#- -##--##- ##--##-- --##---- ----##-- -##--##- -##----- ###-###- ###--##- -##-##-- "
fL[3][5] = " ##-####- ##--##-- -##--##- ##------ -##--##- -##-#--- -##-#--- ##------ ##--##-- --##---- ----##-- -##-##-- -##----- #######- ####-##- ##---##- "
fL[4][5] = " ##-####- ##--##-- -#####-- ##------ -##--##- -####--- -####--- ##------ ######-- --##---- ----##-- -####--- -##----- #######- ##-####- ##---##- "
fL[5][5] = " ##-####- ######-- -##--##- ##------ -##--##- -##-#--- -##-#--- ##--###- ##--##-- --##---- ##--##-- -##-##-- -##---#- ##-#-##- ##--###- ##---##- "
fL[6][5] = " ##------ ##--##-- -##--##- -##--##- -##-##-- -##---#- -##----- -##--##- ##--##-- --##---- ##--##-- -##--##- -##--##- ##---##- ##---##- -##-##-- "
fL[7][5] = " -####--- ##--##-- ######-- --####-- #####--- #######- ####---- --#####- ##--##-- -####--- -####--- ###--##- #######- ##---##- ##---##- --###--- "
fL[8][5] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
-- 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
fL[1][6] = " ######-- -####--- ######-- -####--- ######-- ##--##-- ##--##-- ##---##- ##---##- ##--##-- #######- -####--- ##------ -####--- ---#---- -------- "
fL[2][6] = " -##--##- ##--##-- -##--##- ##--##-- #-##-#-- ##--##-- ##--##-- ##---##- ##---##- ##--##-- ##---##- -##----- -##----- ---##--- --###--- -------- "
fL[3][6] = " -##--##- ##--##-- -##--##- -##----- --##---- ##--##-- ##--##-- ##---##- -##-##-- ##--##-- #---##-- -##----- --##---- ---##--- -##-##-- -------- "
fL[4][6] = " -#####-- ##--##-- -#####-- --##---- --##---- ##--##-- ##--##-- ##-#-##- --###--- -####--- ---##--- -##----- ---##--- ---##--- ##---##- -------- "
fL[5][6] = " -##----- ##-###-- -##-##-- ---##--- --##---- ##--##-- ##--##-- #######- --###--- --##---- --##--#- -##----- ----##-- ---##--- -------- -------- "
fL[6][6] = " -##----- -####--- -##--##- ##--##-- --##---- ##--##-- -####--- ###-###- -##-##-- --##---- -##--##- -##----- -----##- ---##--- -------- -------- "
fL[7][6] = " ####---- ---###-- ###--##- -####--- -####--- ######-- --##---- ##---##- ##---##- -####--- #######- -####--- ------#- -####--- -------- -------- "
fL[8][6] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ######## "
-- 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
fL[1][7] = " --##---- -------- ###----- -------- ---###-- -------- --###--- -------- ###----- --##---- ----##-- ###----- -###---- -------- -------- -------- "
fL[2][7] = " --##---- -------- -##----- -------- ----##-- -------- -##-##-- -------- -##----- -------- -------- -##----- --##---- -------- -------- -------- "
fL[3][7] = " ---##--- -####--- -##----- -####--- ----##-- -####--- -##----- -###-##- -##-##-- -###---- ----##-- -##--##- --##---- ##--##-- #####--- -####--- "
fL[4][7] = " -------- ----##-- -#####-- ##--##-- -#####-- ##--##-- ####---- ##--##-- -###-##- --##---- ----##-- -##-##-- --##---- #######- ##--##-- ##--##-- "
fL[5][7] = " -------- -#####-- -##--##- ##------ ##--##-- ######-- -##----- ##--##-- -##--##- --##---- ----##-- -####--- --##---- #######- ##--##-- ##--##-- "
fL[6][7] = " -------- ##--##-- -##--##- ##--##-- ##--##-- ##------ -##----- -#####-- -##--##- --##---- ##--##-- -##-##-- --##---- ##-#-##- ##--##-- ##--##-- "
fL[7][7] = " -------- -###-##- ##-###-- -####--- -###-##- -####--- ####---- ----##-- ###--##- -####--- ##--##-- ###--##- -####--- ##---##- ##--##-- -####--- "
fL[8][7] = " -------- -------- -------- -------- -------- -------- -------- #####--- -------- -------- -####--- -------- -------- -------- -------- -------- "
-- 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
fL[1][8] = " -------- -------- -------- -------- ---#---- -------- -------- -------- -------- -------- -------- ---###-- ---##--- ###----- -###-##- -------- "
fL[2][8] = " -------- -------- -------- -------- --##---- -------- -------- -------- -------- -------- -------- --##---- ---##--- --##---- ##-###-- ---#---- "
fL[3][8] = " ##-###-- -###-##- ##-###-- -#####-- -#####-- ##--##-- ##--##-- ##---##- ##---##- ##--##-- ######-- --##---- ---##--- --##---- -------- --###--- "
fL[4][8] = " -##--##- ##--##-- -###-##- ##------ --##---- ##--##-- ##--##-- ##-#-##- -##-##-- ##--##-- #--##--- ###----- -------- ---###-- -------- -##-##-- "
fL[5][8] = " -##--##- ##--##-- -##--##- -####--- --##---- ##--##-- ##--##-- #######- --###--- ##--##-- --##---- --##---- ---##--- --##---- -------- ##---##- "
fL[6][8] = " -#####-- -#####-- -##----- ----##-- --##-#-- ##--##-- -####--- #######- -##-##-- -#####-- -##--#-- --##---- ---##--- --##---- -------- ##---##- "
fL[7][8] = " -##----- ----##-- ####---- #####--- ---##--- -###-##- --##---- -##-##-- ##---##- ----##-- ######-- ---###-- ---##--- ###----- -------- #######- "
fL[8][8] = " ####---- ---####- -------- -------- -------- -------- -------- -------- -------- #####--- -------- -------- -------- -------- -------- -------- "
-- 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
fL[1][9] = " ----###- ######-- #####--- ######-- -######- ######-- ##-##-## --####-- ##---##- ##-#-##- ##---##- -----##- ##---##- ##---##- -#####-- #######- "
fL[2][9] = " ---####- ##------ ##--##-- ##------ -##--##- ##------ ##-##-## -##--##- ##---##- ##---##- ##--##-- ----###- ###-###- ##---##- ##---##- ##---##- "
fL[3][9] = " --##-##- ##------ ##--##-- ##------ -##--##- ##------ -######- -----##- ##--###- ##--###- ##-##--- ---####- #######- ##---##- ##---##- ##---##- "
fL[4][9] = " -##--##- ######-- ######-- ##------ -##--##- #####--- ---##--- --####-- ##-####- ##-####- #####--- --##-##- ##-#-##- #######- ##---##- ##---##- "
fL[5][9] = " #######- ##---##- ##---##- ##------ -##--##- ##------ -######- -----##- ####-##- ####-##- ##--##-- -##--##- ##---##- ##---##- ##---##- ##---##- "
fL[6][9] = " ##---##- ##---##- ##---##- ##------ -##--##- ##------ ##-##-## ##---##- ###--##- ###--##- ##---##- ##---##- ##---##- ##---##- ##---##- ##---##- "
fL[7][9] = " ##---##- ######-- ######-- ##------ ######## #######- ##-##-## -#####-- ##---##- ##---##- ##---##- ##---##- ##---##- ##---##- -#####-- ##---##- "
fL[8][9] = " -------- -------- -------- -------- ##----## -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
-- 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
fL[1][10] = " ######-- -#####-- ######-- ##---##- ---##--- ##----## ##--##-- ##---##- ##-#-##- ##-#-##- ####---- ##----#- ##------ -#####-- ##--###- -######- "
fL[2][10] = " ##---##- ##---##- --##---- ##---##- -######- -##--##- ##--##-- ##---##- ##-#-##- ##-#-##- --##---- ##----#- ##------ ##---##- ##-##-## ##---##- "
fL[3][10] = " ##---##- ##------ --##---- ##---##- ##-##-## --####-- ##--##-- ##---##- ##-#-##- ##-#-##- --##---- ##----#- ##------ -----##- ##-##-## ##---##- "
fL[4][10] = " ######-- ##------ --##---- -######- ##-##-## ---##--- ##--##-- -######- ##-#-##- ##-#-##- --#####- ####--#- ######-- ---####- #####-## -######- "
fL[5][10] = " ##------ ##------ --##---- -----##- ##-##-## --####-- ##--##-- -----##- ##-#-##- ##-#-##- --##--## ##-##-#- ##---##- -----##- ##-##-## --##-##- "
fL[6][10] = " ##------ ##---##- --##---- ##---##- -######- -##--##- ##--##-- -----##- ##-#-##- ##-#-##- --##--## ##-##-#- ##---##- ##---##- ##-##-## -##--##- "
fL[7][10] = " ##------ -#####-- --##---- -#####-- ---##--- ##----## #######- -----##- #######- ######## --#####- ####--#- ######-- -#####-- ##--###- ##---##- "
fL[8][10] = " -------- -------- -------- -------- -------- -------- -----##- -------- -------- ------## -------- -------- -------- -------- -------- -------- "
-- A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF
fL[1][11] = " -------- -----#-- -------- -------- -------- -------- -------- -------- -------- --##---- -------- -------- -------- -------- -------- -------- "
fL[2][11] = " -------- -####--- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
fL[3][11] = " -####--- ##------ #####--- ######-- -######- -####--- ##-##-## -####--- ##--##-- ##--##-- ##--##-- ----###- ##---##- ##--##-- -####--- ######-- "
fL[4][11] = " ----##-- #####--- ##--##-- ##------ -##--##- ##--##-- -######- ##--##-- ##--##-- ##--##-- ##-##--- ---####- ###-###- ##--##-- ##--##-- ##--##-- "
fL[5][11] = " -#####-- ##--##-- #####--- ##------ -##--##- ######-- ---##--- ---##--- ##-###-- ##-###-- ####---- --##-##- ##-#-##- ######-- ##--##-- ##--##-- "
fL[6][11] = " ##--##-- ##--##-- ##---##- ##------ -##--##- ##------ -######- ##--##-- ###-##-- ###-##-- ##--##-- -##--##- ##---##- ##--##-- ##--##-- ##--##-- "
fL[7][11] = " -######- -####--- ######-- ##------ ######## -#####-- ##-##-## -####--- ##--##-- ##--##-- ##--##-- ##---##- ##---##- ##--##-- -####--- ##--##-- "
fL[8][11] = " -------- -------- -------- -------- ##----## -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
-- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
fL[1][12] = " --#---#- -#-#-#-# ##-##-## ---#---- ---#---- ---#---- ---#-#-- -------- -------- ---#-#-- ---#-#-- -------- ---#-#-- ---#-#-- ---#---- -------- "
fL[2][12] = " #---#--- #-#-#-#- -###-### ---#---- ---#---- ---#---- ---#-#-- -------- -------- ---#-#-- ---#-#-- -------- ---#-#-- ---#-#-- ---#---- -------- "
fL[3][12] = " --#---#- -#-#-#-# ##-##-## ---#---- ---#---- ####---- ---#-#-- -------- ####---- ####-#-- ---#-#-- ######-- ####-#-- ---#-#-- ####---- -------- "
fL[4][12] = " #---#--- #-#-#-#- ###-###- ---#---- ---#---- ---#---- ---#-#-- -------- ---#---- -----#-- ---#-#-- -----#-- -----#-- ---#-#-- ---#---- -------- "
fL[5][12] = " --#---#- -#-#-#-# ##-##-## ---#---- ####---- ####---- ####-#-- ######-- ####---- ####-#-- ---#-#-- ####-#-- ######-- ######-- ####---- ####---- "
fL[6][12] = " #---#--- #-#-#-#- -###-### ---#---- ---#---- ---#---- ---#-#-- ---#-#-- ---#---- ---#-#-- ---#-#-- ---#-#-- -------- -------- -------- ---#---- "
fL[7][12] = " --#---#- -#-#-#-# ##-##-## ---#---- ---#---- ---#---- ---#-#-- ---#-#-- ---#---- ---#-#-- ---#-#-- ---#-#-- -------- -------- -------- ---#---- "
fL[8][12] = " #---#--- #-#-#-#- ###-###- ---#---- ---#---- ---#---- ---#-#-- ---#-#-- ---#---- ---#-#-- ---#-#-- ---#-#-- -------- -------- -------- ---#---- "
-- C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF
fL[1][13] = " ---#---- ---#---- -------- ---#---- -------- ---#---- ---#---- ---#-#-- ---#-#-- -------- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#---- "
fL[2][13] = " ---#---- ---#---- -------- ---#---- -------- ---#---- ---#---- ---#-#-- ---#-#-- -------- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#---- "
fL[3][13] = " ---#---- ---#---- -------- ---#---- -------- ---#---- ---##### ---#-#-- ---#-### ---##### ####-### ######## ---#-### ######## ####-### ######## "
fL[4][13] = " ---#---- ---#---- -------- ---#---- -------- ---#---- ---#---- ---#-#-- ---#---- ---#---- -------- -------- ---#---- -------- -------- -------- "
fL[5][13] = " ---##### ######## ######## ---##### ######## ######## ---##### ---#-### ---##### ---#-### ######## ####-### ---#-### ######## ####-### ######## "
fL[6][13] = " -------- -------- ---#---- ---#---- -------- ---#---- ---#---- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#-#-- -------- ---#-#-- -------- "
fL[7][13] = " -------- -------- ---#---- ---#---- -------- ---#---- ---#---- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#-#-- -------- ---#-#-- -------- "
fL[8][13] = " -------- -------- ---#---- ---#---- -------- ---#---- ---#---- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#-#-- -------- ---#-#-- -------- "
-- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
fL[1][14] = " ---#-#-- -------- -------- ---#-#-- ---#---- -------- -------- ---#-#-- ---#---- ---#---- -------- ######## -------- ####---- ----#### ######## "
fL[2][14] = " ---#-#-- -------- -------- ---#-#-- ---#---- -------- -------- ---#-#-- ---#---- ---#---- -------- ######## -------- ####---- ----#### ######## "
fL[3][14] = " ---#-#-- ######## -------- ---#-#-- ---##### ---##### -------- ---#-#-- ######## ---#---- -------- ######## -------- ####---- ----#### ######## "
fL[4][14] = " ---#-#-- -------- -------- ---#-#-- ---#---- ---#---- -------- ---#-#-- ---#---- ---#---- -------- ######## -------- ####---- ----#### ######## "
fL[5][14] = " ######## ######## ######## ---##### ---##### ---##### ---##### ######## ######## ####---- ---##### ######## ######## ####---- ----#### -------- "
fL[6][14] = " -------- ---#---- ---#-#-- -------- -------- ---#---- ---#-#-- ---#-#-- ---#---- -------- ---#---- ######## ######## ####---- ----#### -------- "
fL[7][14] = " -------- ---#---- ---#-#-- -------- -------- ---#---- ---#-#-- ---#-#-- ---#---- -------- ---#---- ######## ######## ####---- ----#### -------- "
fL[8][14] = " -------- ---#---- ---#-#-- -------- -------- ---#---- ---#-#-- ---#-#-- ---#---- -------- ---#---- ######## ######## ####---- ----#### -------- "
-- F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
fL[1][15] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
fL[2][15] = " -------- -------- -------- -------- ---##--- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
fL[3][15] = " #####--- -####--- ######-- ##--##-- -######- ##---##- ##--##-- ##--##-- ##-#-##- ##-#-##- ####---- ##----#- ##------ -#####-- ##--###- -#####-- "
fL[4][15] = " ##--##-- ##--##-- --##---- ##--##-- ##-##-## -##-##-- ##--##-- ##--##-- ##-#-##- ##-#-##- --##---- ##----#- ##------ ##---##- ##-##-## ##--##-- "
fL[5][15] = " ##--##-- ##------ --##---- -#####-- ##-##-## --###--- ##--##-- -#####-- ##-#-##- ##-#-##- --#####- ####--#- #####--- ---####- #####-## -#####-- "
fL[6][15] = " #####--- ##--##-- --##---- ----##-- -######- -##-##-- ##--##-- ----##-- ##-#-##- ##-#-##- --##--## ##-##-#- ##--##-- ##---##- ##-##-## -##-##-- "
fL[7][15] = " ##------ -####--- --##---- ##--##-- ---##--- ##---##- #######- ----##-- #######- ######## --#####- ####--#- #####--- -#####-- ##--###- ##--##-- "
fL[8][15] = " ##------ -------- -------- -####--- ---##--- -------- -----##- -------- -------- ------## -------- -------- -------- -------- -------- -------- "
-- E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF
fL[1][16] = " -#--#--- -#--#--- -##----- ---##--- ----#--- ---#---- --##---- -------- -##----- -------- -------- ---##### #-#----- -##----- -------- -------- "
fL[2][16] = " ######-- -------- --##---- --##---- ---#-#-- ---#---- --##---- -------- #--#---- -------- -------- ---#---- ##-#---- #--#---- -------- -------- "
fL[3][16] = " ##------ -####--- ---##--- -##----- ---#---- ---#---- -------- -##--#-- #--#---- -------- -------- ---#---- #--#---- --#----- --####-- -------- "
fL[4][16] = " #####--- ##--##-- --##---- --##---- ---#---- ---#---- ######-- #--##--- -##----- --##---- -------- #--#---- #--#---- -#------ --####-- -------- "
fL[5][16] = " ##------ ######-- -##----- ---##--- ---#---- ---#---- -------- -------- -------- --##---- --##---- -#-#---- #--#---- ####---- --####-- -------- "
fL[6][16] = " ##------ ##------ -------- -------- ---#---- -#-#---- --##---- -##--#-- -------- -------- -------- --##---- -------- -------- --####-- -------- "
fL[7][16] = " #######- -#####-- -####--- -####--- ---#---- --#----- --##---- #--##--- -------- -------- -------- ---#---- -------- -------- -------- -------- "
fL[8][16] = " -------- -------- -------- -------- ---#---- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
ENDLUA
LUA ALLPASS
for i = 1, 8 do
for j = 1, 16, 1 do
_pc(" DG " .. fL[i][j])
end
end
ENDLUA
;
/*
‹¨­¨ï 256 ¡ ©â®¢ ¢ Ž‡“ áâ ­®¢¨âáï á⮫¡¨ª®¬ ¢ ¢¨¤¥®¯ ¬ïâ¨.
‘«¥¢  ­ ¯à ¢® ¯¥à¥å®¤¨â ᢥàåã ¢­¨§. <EFBFBD>¥à¢ ï «¨­¨ï - ¯¥à¢ë© á⮫¡¨ª.
; ‡­ ª®£¥­¥à â®à
LUA PASS1
fL = {}
for i = 1,16 do
fL[i]={}
end
-- 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
fL[1][1] = " -------- -######- -######- -##-##-- ---#---- --###--- ---#---- -------- ######## -------- ######## ----#### --####-- --###### -####### ---##--- "
fL[2][1] = " -------- #------# ######## #######- --###--- -#####-- ---#---- -------- ######## --####-- ##----## -----### -##--##- --##--## -##---## ##-##-## "
fL[3][1] = " -------- #-#--#-# ##-##-## #######- -#####-- --###--- --###--- ---##--- ###--### -##--##- #--##--# ----#### -##--##- --###### -####### --####-- "
fL[4][1] = " -------- #------# ######## #######- #######- #######- -#####-- --####-- ##----## -#----#- #-####-# -#####-# -##--##- --##---- -##---## ###--### "
fL[5][1] = " -------- #-####-# ##----## -#####-- -#####-- #######- #######- --####-- ##----## -#----#- #-####-# ##--##-- --####-- --##---- -##---## ###--### "
fL[6][1] = " -------- #--##--# ###--### --###--- --###--- ##-#-##- -#####-- ---##--- ###--### -##--##- #--##--# ##--##-- ---##--- -###---- -##--### --####-- "
fL[7][1] = " -------- #------# ######## ---#---- ---#---- ---#---- ---#---- -------- ######## --####-- ##----## ##--##-- -######- ####---- ###--##- ##-##-## "
fL[8][1] = " -------- -######- -######- -------- -------- --###--- --###--- -------- ######## -------- ######## -####--- ---##--- ###----- ##------ ---##--- "
-- 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
fL[1][2] = " #------- ------#- ---##--- -##--##- -####### --#####- -------- ---##--- ---##--- ---##--- -------- -------- -------- -------- -------- -------- "
fL[2][2] = " ###----- ----###- --####-- -##--##- ##-##-## -##---## -------- --####-- --####-- ---##--- ---##--- --##---- -------- --#--#-- ---##--- ######## "
fL[3][2] = " #####--- --#####- -######- -##--##- ##-##-## --###--- -------- -######- -######- ---##--- ----##-- -##----- ##------ -##--##- --####-- ######## "
fL[4][2] = " #######- #######- ---##--- -##--##- -####-## -##-##-- -------- ---##--- ---##--- ---##--- #######- #######- ##------ ######## -######- -######- "
fL[5][2] = " #####--- --#####- ---##--- -##--##- ---##-## -##-##-- -######- -######- ---##--- -######- ----##-- -##----- ##------ -##--##- ######## --####-- "
fL[6][2] = " ###----- ----###- -######- -------- ---##-## --###--- -######- --####-- ---##--- --####-- ---##--- --##---- #######- --#--#-- ######## ---##--- "
fL[7][2] = " #------- ------#- --####-- -##--##- ---##-## ##--##-- -######- ---##--- ---##--- ---##--- -------- -------- -------- -------- -------- -------- "
fL[8][2] = " -------- -------- ---##--- -------- -------- -####--- -------- ######## -------- -------- -------- -------- -------- -------- -------- -------- "
-- 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
fL[1][3] = " -------- --##---- -##-##-- -##-##-- --##---- -------- --###--- -##----- ---##--- -##----- -------- -------- -------- -------- -------- -----##- "
fL[2][3] = " -------- -####--- -##-##-- -##-##-- -#####-- ##---##- -##-##-- -##----- --##---- --##---- -##--##- --##---- -------- -------- -------- ----##-- "
fL[3][3] = " -------- -####--- -##-##-- #######- ##------ ##--##-- --###--- ##------ -##----- ---##--- --####-- --##---- -------- -------- -------- ---##--- "
fL[4][3] = " -------- --##---- -------- -##-##-- -####--- ---##--- -###-##- -------- -##----- ---##--- ######## ######-- -------- ######-- -------- --##---- "
fL[5][3] = " -------- --##---- -------- #######- ----##-- --##---- ##-###-- -------- -##----- ---##--- --####-- --##---- -------- -------- -------- -##----- "
fL[6][3] = " -------- -------- -------- -##-##-- #####--- -##--##- ##--##-- -------- --##---- --##---- -##--##- --##---- --##---- -------- --##---- ##------ "
fL[7][3] = " -------- --##---- -------- -##-##-- --##---- ##---##- -###-##- -------- ---##--- -##----- -------- -------- --##---- -------- --##---- #------- "
fL[8][3] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -##----- -------- -------- -------- "
-- 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
fL[1][4] = " -#####-- --##---- -####--- -####--- ---###-- ######-- --###--- ######-- -####--- -####--- -------- -------- ---##--- -------- -##----- -####--- "
fL[2][4] = " ##---##- -###---- ##--##-- ##--##-- --####-- ##------ -##----- ##--##-- ##--##-- ##--##-- --##---- --##---- --##---- -------- --##---- ##--##-- "
fL[3][4] = " ##--###- --##---- ----##-- ----##-- -##-##-- #####--- ##------ ----##-- ##--##-- ##--##-- --##---- --##---- -##----- ######-- ---##--- ----##-- "
fL[4][4] = " ##-####- --##---- --###--- --###--- ##--##-- ----##-- #####--- ---##--- -####--- -#####-- -------- -------- ##------ -------- ----##-- ---##--- "
fL[5][4] = " ####-##- --##---- -##----- ----##-- #######- ----##-- ##--##-- --##---- ##--##-- ----##-- -------- -------- -##----- -------- ---##--- --##---- "
fL[6][4] = " ###--##- --##---- ##--##-- ##--##-- ----##-- ##--##-- ##--##-- --##---- ##--##-- ---##--- --##---- --##---- --##---- ######-- --##---- -------- "
fL[7][4] = " -#####-- ######-- ######-- -####--- ---####- -####--- -####--- --##---- -####--- -###---- --##---- --##---- ---##--- -------- -##----- --##---- "
fL[8][4] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -##----- -------- -------- -------- -------- "
-- 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
fL[1][5] = " -#####-- --##---- ######-- --####-- #####--- #######- #######- --####-- ##--##-- -####--- ---####- ###--##- ####---- ##---##- ##---##- --###--- "
fL[2][5] = " ##---##- -####--- -##--##- -##--##- -##-##-- -##---#- -##---#- -##--##- ##--##-- --##---- ----##-- -##--##- -##----- ###-###- ###--##- -##-##-- "
fL[3][5] = " ##-####- ##--##-- -##--##- ##------ -##--##- -##-#--- -##-#--- ##------ ##--##-- --##---- ----##-- -##-##-- -##----- #######- ####-##- ##---##- "
fL[4][5] = " ##-####- ##--##-- -#####-- ##------ -##--##- -####--- -####--- ##------ ######-- --##---- ----##-- -####--- -##----- #######- ##-####- ##---##- "
fL[5][5] = " ##-####- ######-- -##--##- ##------ -##--##- -##-#--- -##-#--- ##--###- ##--##-- --##---- ##--##-- -##-##-- -##---#- ##-#-##- ##--###- ##---##- "
fL[6][5] = " ##------ ##--##-- -##--##- -##--##- -##-##-- -##---#- -##----- -##--##- ##--##-- --##---- ##--##-- -##--##- -##--##- ##---##- ##---##- -##-##-- "
fL[7][5] = " -####--- ##--##-- ######-- --####-- #####--- #######- ####---- --#####- ##--##-- -####--- -####--- ###--##- #######- ##---##- ##---##- --###--- "
fL[8][5] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
-- 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
fL[1][6] = " ######-- -####--- ######-- -####--- ######-- ##--##-- ##--##-- ##---##- ##---##- ##--##-- #######- -####--- ##------ -####--- ---#---- -------- "
fL[2][6] = " -##--##- ##--##-- -##--##- ##--##-- #-##-#-- ##--##-- ##--##-- ##---##- ##---##- ##--##-- ##---##- -##----- -##----- ---##--- --###--- -------- "
fL[3][6] = " -##--##- ##--##-- -##--##- -##----- --##---- ##--##-- ##--##-- ##---##- -##-##-- ##--##-- #---##-- -##----- --##---- ---##--- -##-##-- -------- "
fL[4][6] = " -#####-- ##--##-- -#####-- --##---- --##---- ##--##-- ##--##-- ##-#-##- --###--- -####--- ---##--- -##----- ---##--- ---##--- ##---##- -------- "
fL[5][6] = " -##----- ##-###-- -##-##-- ---##--- --##---- ##--##-- ##--##-- #######- --###--- --##---- --##--#- -##----- ----##-- ---##--- -------- -------- "
fL[6][6] = " -##----- -####--- -##--##- ##--##-- --##---- ##--##-- -####--- ###-###- -##-##-- --##---- -##--##- -##----- -----##- ---##--- -------- -------- "
fL[7][6] = " ####---- ---###-- ###--##- -####--- -####--- ######-- --##---- ##---##- ##---##- -####--- #######- -####--- ------#- -####--- -------- -------- "
fL[8][6] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ######## "
-- 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
fL[1][7] = " --##---- -------- ###----- -------- ---###-- -------- --###--- -------- ###----- --##---- ----##-- ###----- -###---- -------- -------- -------- "
fL[2][7] = " --##---- -------- -##----- -------- ----##-- -------- -##-##-- -------- -##----- -------- -------- -##----- --##---- -------- -------- -------- "
fL[3][7] = " ---##--- -####--- -##----- -####--- ----##-- -####--- -##----- -###-##- -##-##-- -###---- ----##-- -##--##- --##---- ##--##-- #####--- -####--- "
fL[4][7] = " -------- ----##-- -#####-- ##--##-- -#####-- ##--##-- ####---- ##--##-- -###-##- --##---- ----##-- -##-##-- --##---- #######- ##--##-- ##--##-- "
fL[5][7] = " -------- -#####-- -##--##- ##------ ##--##-- ######-- -##----- ##--##-- -##--##- --##---- ----##-- -####--- --##---- #######- ##--##-- ##--##-- "
fL[6][7] = " -------- ##--##-- -##--##- ##--##-- ##--##-- ##------ -##----- -#####-- -##--##- --##---- ##--##-- -##-##-- --##---- ##-#-##- ##--##-- ##--##-- "
fL[7][7] = " -------- -###-##- ##-###-- -####--- -###-##- -####--- ####---- ----##-- ###--##- -####--- ##--##-- ###--##- -####--- ##---##- ##--##-- -####--- "
fL[8][7] = " -------- -------- -------- -------- -------- -------- -------- #####--- -------- -------- -####--- -------- -------- -------- -------- -------- "
-- 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
fL[1][8] = " -------- -------- -------- -------- ---#---- -------- -------- -------- -------- -------- -------- ---###-- ---##--- ###----- -###-##- -------- "
fL[2][8] = " -------- -------- -------- -------- --##---- -------- -------- -------- -------- -------- -------- --##---- ---##--- --##---- ##-###-- ---#---- "
fL[3][8] = " ##-###-- -###-##- ##-###-- -#####-- -#####-- ##--##-- ##--##-- ##---##- ##---##- ##--##-- ######-- --##---- ---##--- --##---- -------- --###--- "
fL[4][8] = " -##--##- ##--##-- -###-##- ##------ --##---- ##--##-- ##--##-- ##-#-##- -##-##-- ##--##-- #--##--- ###----- -------- ---###-- -------- -##-##-- "
fL[5][8] = " -##--##- ##--##-- -##--##- -####--- --##---- ##--##-- ##--##-- #######- --###--- ##--##-- --##---- --##---- ---##--- --##---- -------- ##---##- "
fL[6][8] = " -#####-- -#####-- -##----- ----##-- --##-#-- ##--##-- -####--- #######- -##-##-- -#####-- -##--#-- --##---- ---##--- --##---- -------- ##---##- "
fL[7][8] = " -##----- ----##-- ####---- #####--- ---##--- -###-##- --##---- -##-##-- ##---##- ----##-- ######-- ---###-- ---##--- ###----- -------- #######- "
fL[8][8] = " ####---- ---####- -------- -------- -------- -------- -------- -------- -------- #####--- -------- -------- -------- -------- -------- -------- "
-- 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
fL[1][9] = " ----###- ######-- #####--- ######-- -######- ######-- ##-##-## --####-- ##---##- ##-#-##- ##---##- -----##- ##---##- ##---##- -#####-- #######- "
fL[2][9] = " ---####- ##------ ##--##-- ##------ -##--##- ##------ ##-##-## -##--##- ##---##- ##---##- ##--##-- ----###- ###-###- ##---##- ##---##- ##---##- "
fL[3][9] = " --##-##- ##------ ##--##-- ##------ -##--##- ##------ -######- -----##- ##--###- ##--###- ##-##--- ---####- #######- ##---##- ##---##- ##---##- "
fL[4][9] = " -##--##- ######-- ######-- ##------ -##--##- #####--- ---##--- --####-- ##-####- ##-####- #####--- --##-##- ##-#-##- #######- ##---##- ##---##- "
fL[5][9] = " #######- ##---##- ##---##- ##------ -##--##- ##------ -######- -----##- ####-##- ####-##- ##--##-- -##--##- ##---##- ##---##- ##---##- ##---##- "
fL[6][9] = " ##---##- ##---##- ##---##- ##------ -##--##- ##------ ##-##-## ##---##- ###--##- ###--##- ##---##- ##---##- ##---##- ##---##- ##---##- ##---##- "
fL[7][9] = " ##---##- ######-- ######-- ##------ ######## #######- ##-##-## -#####-- ##---##- ##---##- ##---##- ##---##- ##---##- ##---##- -#####-- ##---##- "
fL[8][9] = " -------- -------- -------- -------- ##----## -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
-- 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
fL[1][10] = " ######-- -#####-- ######-- ##---##- ---##--- ##----## ##--##-- ##---##- ##-#-##- ##-#-##- ####---- ##----#- ##------ -#####-- ##--###- -######- "
fL[2][10] = " ##---##- ##---##- --##---- ##---##- -######- -##--##- ##--##-- ##---##- ##-#-##- ##-#-##- --##---- ##----#- ##------ ##---##- ##-##-## ##---##- "
fL[3][10] = " ##---##- ##------ --##---- ##---##- ##-##-## --####-- ##--##-- ##---##- ##-#-##- ##-#-##- --##---- ##----#- ##------ -----##- ##-##-## ##---##- "
fL[4][10] = " ######-- ##------ --##---- -######- ##-##-## ---##--- ##--##-- -######- ##-#-##- ##-#-##- --#####- ####--#- ######-- ---####- #####-## -######- "
fL[5][10] = " ##------ ##------ --##---- -----##- ##-##-## --####-- ##--##-- -----##- ##-#-##- ##-#-##- --##--## ##-##-#- ##---##- -----##- ##-##-## --##-##- "
fL[6][10] = " ##------ ##---##- --##---- ##---##- -######- -##--##- ##--##-- -----##- ##-#-##- ##-#-##- --##--## ##-##-#- ##---##- ##---##- ##-##-## -##--##- "
fL[7][10] = " ##------ -#####-- --##---- -#####-- ---##--- ##----## #######- -----##- #######- ######## --#####- ####--#- ######-- -#####-- ##--###- ##---##- "
fL[8][10] = " -------- -------- -------- -------- -------- -------- -----##- -------- -------- ------## -------- -------- -------- -------- -------- -------- "
-- A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF
fL[1][11] = " -------- -----#-- -------- -------- -------- -------- -------- -------- -------- --##---- -------- -------- -------- -------- -------- -------- "
fL[2][11] = " -------- -####--- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
fL[3][11] = " -####--- ##------ #####--- ######-- -######- -####--- ##-##-## -####--- ##--##-- ##--##-- ##--##-- ----###- ##---##- ##--##-- -####--- ######-- "
fL[4][11] = " ----##-- #####--- ##--##-- ##------ -##--##- ##--##-- -######- ##--##-- ##--##-- ##--##-- ##-##--- ---####- ###-###- ##--##-- ##--##-- ##--##-- "
fL[5][11] = " -#####-- ##--##-- #####--- ##------ -##--##- ######-- ---##--- ---##--- ##-###-- ##-###-- ####---- --##-##- ##-#-##- ######-- ##--##-- ##--##-- "
fL[6][11] = " ##--##-- ##--##-- ##---##- ##------ -##--##- ##------ -######- ##--##-- ###-##-- ###-##-- ##--##-- -##--##- ##---##- ##--##-- ##--##-- ##--##-- "
fL[7][11] = " -######- -####--- ######-- ##------ ######## -#####-- ##-##-## -####--- ##--##-- ##--##-- ##--##-- ##---##- ##---##- ##--##-- -####--- ##--##-- "
fL[8][11] = " -------- -------- -------- -------- ##----## -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
-- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
fL[1][12] = " --#---#- -#-#-#-# ##-##-## ---#---- ---#---- ---#---- ---#-#-- -------- -------- ---#-#-- ---#-#-- -------- ---#-#-- ---#-#-- ---#---- -------- "
fL[2][12] = " #---#--- #-#-#-#- -###-### ---#---- ---#---- ---#---- ---#-#-- -------- -------- ---#-#-- ---#-#-- -------- ---#-#-- ---#-#-- ---#---- -------- "
fL[3][12] = " --#---#- -#-#-#-# ##-##-## ---#---- ---#---- ####---- ---#-#-- -------- ####---- ####-#-- ---#-#-- ######-- ####-#-- ---#-#-- ####---- -------- "
fL[4][12] = " #---#--- #-#-#-#- ###-###- ---#---- ---#---- ---#---- ---#-#-- -------- ---#---- -----#-- ---#-#-- -----#-- -----#-- ---#-#-- ---#---- -------- "
fL[5][12] = " --#---#- -#-#-#-# ##-##-## ---#---- ####---- ####---- ####-#-- ######-- ####---- ####-#-- ---#-#-- ####-#-- ######-- ######-- ####---- ####---- "
fL[6][12] = " #---#--- #-#-#-#- -###-### ---#---- ---#---- ---#---- ---#-#-- ---#-#-- ---#---- ---#-#-- ---#-#-- ---#-#-- -------- -------- -------- ---#---- "
fL[7][12] = " --#---#- -#-#-#-# ##-##-## ---#---- ---#---- ---#---- ---#-#-- ---#-#-- ---#---- ---#-#-- ---#-#-- ---#-#-- -------- -------- -------- ---#---- "
fL[8][12] = " #---#--- #-#-#-#- ###-###- ---#---- ---#---- ---#---- ---#-#-- ---#-#-- ---#---- ---#-#-- ---#-#-- ---#-#-- -------- -------- -------- ---#---- "
-- C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF
fL[1][13] = " ---#---- ---#---- -------- ---#---- -------- ---#---- ---#---- ---#-#-- ---#-#-- -------- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#---- "
fL[2][13] = " ---#---- ---#---- -------- ---#---- -------- ---#---- ---#---- ---#-#-- ---#-#-- -------- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#---- "
fL[3][13] = " ---#---- ---#---- -------- ---#---- -------- ---#---- ---##### ---#-#-- ---#-### ---##### ####-### ######## ---#-### ######## ####-### ######## "
fL[4][13] = " ---#---- ---#---- -------- ---#---- -------- ---#---- ---#---- ---#-#-- ---#---- ---#---- -------- -------- ---#---- -------- -------- -------- "
fL[5][13] = " ---##### ######## ######## ---##### ######## ######## ---##### ---#-### ---##### ---#-### ######## ####-### ---#-### ######## ####-### ######## "
fL[6][13] = " -------- -------- ---#---- ---#---- -------- ---#---- ---#---- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#-#-- -------- ---#-#-- -------- "
fL[7][13] = " -------- -------- ---#---- ---#---- -------- ---#---- ---#---- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#-#-- -------- ---#-#-- -------- "
fL[8][13] = " -------- -------- ---#---- ---#---- -------- ---#---- ---#---- ---#-#-- -------- ---#-#-- -------- ---#-#-- ---#-#-- -------- ---#-#-- -------- "
-- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
fL[1][14] = " ---#-#-- -------- -------- ---#-#-- ---#---- -------- -------- ---#-#-- ---#---- ---#---- -------- ######## -------- ####---- ----#### ######## "
fL[2][14] = " ---#-#-- -------- -------- ---#-#-- ---#---- -------- -------- ---#-#-- ---#---- ---#---- -------- ######## -------- ####---- ----#### ######## "
fL[3][14] = " ---#-#-- ######## -------- ---#-#-- ---##### ---##### -------- ---#-#-- ######## ---#---- -------- ######## -------- ####---- ----#### ######## "
fL[4][14] = " ---#-#-- -------- -------- ---#-#-- ---#---- ---#---- -------- ---#-#-- ---#---- ---#---- -------- ######## -------- ####---- ----#### ######## "
fL[5][14] = " ######## ######## ######## ---##### ---##### ---##### ---##### ######## ######## ####---- ---##### ######## ######## ####---- ----#### -------- "
fL[6][14] = " -------- ---#---- ---#-#-- -------- -------- ---#---- ---#-#-- ---#-#-- ---#---- -------- ---#---- ######## ######## ####---- ----#### -------- "
fL[7][14] = " -------- ---#---- ---#-#-- -------- -------- ---#---- ---#-#-- ---#-#-- ---#---- -------- ---#---- ######## ######## ####---- ----#### -------- "
fL[8][14] = " -------- ---#---- ---#-#-- -------- -------- ---#---- ---#-#-- ---#-#-- ---#---- -------- ---#---- ######## ######## ####---- ----#### -------- "
-- F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
fL[1][15] = " -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
fL[2][15] = " -------- -------- -------- -------- ---##--- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
fL[3][15] = " #####--- -####--- ######-- ##--##-- -######- ##---##- ##--##-- ##--##-- ##-#-##- ##-#-##- ####---- ##----#- ##------ -#####-- ##--###- -#####-- "
fL[4][15] = " ##--##-- ##--##-- --##---- ##--##-- ##-##-## -##-##-- ##--##-- ##--##-- ##-#-##- ##-#-##- --##---- ##----#- ##------ ##---##- ##-##-## ##--##-- "
fL[5][15] = " ##--##-- ##------ --##---- -#####-- ##-##-## --###--- ##--##-- -#####-- ##-#-##- ##-#-##- --#####- ####--#- #####--- ---####- #####-## -#####-- "
fL[6][15] = " #####--- ##--##-- --##---- ----##-- -######- -##-##-- ##--##-- ----##-- ##-#-##- ##-#-##- --##--## ##-##-#- ##--##-- ##---##- ##-##-## -##-##-- "
fL[7][15] = " ##------ -####--- --##---- ##--##-- ---##--- ##---##- #######- ----##-- #######- ######## --#####- ####--#- #####--- -#####-- ##--###- ##--##-- "
fL[8][15] = " ##------ -------- -------- -####--- ---##--- -------- -----##- -------- -------- ------## -------- -------- -------- -------- -------- -------- "
-- E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF
fL[1][16] = " -#--#--- -#--#--- -##----- ---##--- ----#--- ---#---- --##---- -------- -##----- -------- -------- ---##### #-#----- -##----- -------- -------- "
fL[2][16] = " ######-- -------- --##---- --##---- ---#-#-- ---#---- --##---- -------- #--#---- -------- -------- ---#---- ##-#---- #--#---- -------- -------- "
fL[3][16] = " ##------ -####--- ---##--- -##----- ---#---- ---#---- -------- -##--#-- #--#---- -------- -------- ---#---- #--#---- --#----- --####-- -------- "
fL[4][16] = " #####--- ##--##-- --##---- --##---- ---#---- ---#---- ######-- #--##--- -##----- --##---- -------- #--#---- #--#---- -#------ --####-- -------- "
fL[5][16] = " ##------ ######-- -##----- ---##--- ---#---- ---#---- -------- -------- -------- --##---- --##---- -#-#---- #--#---- ####---- --####-- -------- "
fL[6][16] = " ##------ ##------ -------- -------- ---#---- -#-#---- --##---- -##--#-- -------- -------- -------- --##---- -------- -------- --####-- -------- "
fL[7][16] = " #######- -#####-- -####--- -####--- ---#---- --#----- --##---- #--##--- -------- -------- -------- ---#---- -------- -------- -------- -------- "
fL[8][16] = " -------- -------- -------- -------- ---#---- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- "
ENDLUA
LUA ALLPASS
for i = 1, 8 do
for j = 1, 16, 1 do
_pc(" DG " .. fL[i][j])
end
end
ENDLUA
;
/*
‹¨­¨ï 256 ¡ ©â®¢ ¢ Ž‡“ áâ ­®¢¨âáï á⮫¡¨ª®¬ ¢ ¢¨¤¥®¯ ¬ïâ¨.
‘«¥¢  ­ ¯à ¢® ¯¥à¥å®¤¨â ᢥàåã ¢­¨§. <EFBFBD>¥à¢ ï «¨­¨ï - ¯¥à¢ë© á⮫¡¨ª.
*/

1762
src/bios/exp/FUNC_4x.ASM → bios/exp/FUNC_4x.ASM
View File

File diff suppressed because it is too large Load Diff

190
src/bios/exp/FUNC_5x.asm → bios/exp/FUNC_5x.asm
View File

@ -1,96 +1,96 @@
;
; It's disk drive BIOS extender for functions 5xh.
;---------------------------------------------------------------
;Version! Description
;---------------------------------------------------------------
; 2.32 ! Removed `DI' Disabled Interupt instruction in HDRIVER6
; ! function load sectors.
; ! Fixed bug waiting slave device in AUTOIDE.
;
;INT_ADRESS EQU #C124
;INT_PAGE EQU #C126
;INT_ID EQU #C127
;BIOS EQU #3FD0
; DS #3FD0,#FF
DRV_VERSION:
LD HL,0
LD BC,0
LD DE,Disk_subsystem_ver_hex
AND A
RET
;
;
DRV_LIST:
IN A,(SLOT3)
PUSH AF
PUSH IY
LD A,SYS_PAGE
OUT (SLOT3),A ; !TODO ᤥ« âì áâàãªâãன
XOR A
LD (IX+0),#04 ; DB 0 ;LEN ;!HARDCODE
LD (IX+1),#02 ; DB 0 ;FDD COUNT
LD (IX+2),A ; DB 0 ;HDD COUNT
LD (IX+3),A ; DB 0 ;CDROM COUNT
; ; BLOCK 13,0 ;RESERVED ;!TODO ᤥ« âì RAMDRIVE âãâ?
LD (IX+4),A ; END FLAG
DEC A
;Calculating FDD devices
; A=#FF
; LD HL,SYS_PAGE.FDD_TABLE
; CALL .CHECK_FDD
; LD HL,SYS_PAGE.FDD_1_TABLE
; CALL .CHECK_FDD
; A=#FF
;Calculating IDE devices IDE TYPE 1-HDD, 2-CD-ROM
LD IY,IDE.INIT_TBL_IDE0
LD DE,IDE.HDD_INIT_TABLE
LD B,4 ; !HARDCODE ª®«-¢® IDE ãáâனáâ¢
.CHECK_IDE:
LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM
CP #FF
JR Z,.NEXT_IDE
CP IDE.Device.HDD
JR NZ,.NOT_HDD
INC (IX+2)
.NOT_HDD:
CP IDE.Device.ATAPI
JR NZ,.NEXT_IDE
INC (IX+3)
.NEXT_IDE:
ADD IY,DE
DJNZ .CHECK_IDE
;
.check_exit:
POP IY
POP AF
OUT (SLOT3),A
XOR A
RET
;
; A=#FF
; .CHECK_FDD:
; INC (IX+1)
; LD B,8
; .TFD0: CP (HL)
; INC HL
; RET NZ
; DJNZ .TFD0
; DEC (IX+1)
; RET
; ;
INCLUDE 'EXTENDED/FDD_DRIVER.asm'
INCLUDE 'EXTENDED/RAM_DISK_DRIVER.asm'
INCLUDE 'EXTENDED/IDE/ATA_DRV.asm'
INCLUDE 'EXTENDED/IDE/ATAPI_DRV.asm'
INCLUDE 'EXTENDED/IDE/SHARED.asm'
;DISPLAY " EXTENDED end addr: ", /A, $
;
; It's disk drive BIOS extender for functions 5xh.
;---------------------------------------------------------------
;Version! Description
;---------------------------------------------------------------
; 2.32 ! Removed `DI' Disabled Interupt instruction in HDRIVER6
; ! function load sectors.
; ! Fixed bug waiting slave device in AUTOIDE.
;
;INT_ADRESS EQU #C124
;INT_PAGE EQU #C126
;INT_ID EQU #C127
;BIOS EQU #3FD0
; DS #3FD0,#FF
DRV_VERSION:
LD HL,0
LD BC,0
LD DE,Disk_subsystem_ver_hex
AND A
RET
;
;
DRV_LIST:
IN A,(SLOT3)
PUSH AF
PUSH IY
LD A,SYS_PAGE
OUT (SLOT3),A ; !TODO ᤥ« âì áâàãªâãன
XOR A
LD (IX+0),#04 ; DB 0 ;LEN ;!HARDCODE
LD (IX+1),#02 ; DB 0 ;FDD COUNT
LD (IX+2),A ; DB 0 ;HDD COUNT
LD (IX+3),A ; DB 0 ;CDROM COUNT
; ; BLOCK 13,0 ;RESERVED ;!TODO ᤥ« âì RAMDRIVE âãâ?
LD (IX+4),A ; END FLAG
DEC A
;Calculating FDD devices
; A=#FF
; LD HL,SYS_PAGE.FDD_TABLE
; CALL .CHECK_FDD
; LD HL,SYS_PAGE.FDD_1_TABLE
; CALL .CHECK_FDD
; A=#FF
;Calculating IDE devices IDE TYPE 1-HDD, 2-CD-ROM
LD IY,IDE.INIT_TBL_IDE0
LD DE,IDE.HDD_INIT_TABLE
LD B,4 ; !HARDCODE ª®«-¢® IDE ãáâனáâ¢
.CHECK_IDE:
LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM
CP #FF
JR Z,.NEXT_IDE
CP IDE.Device.HDD
JR NZ,.NOT_HDD
INC (IX+2)
.NOT_HDD:
CP IDE.Device.ATAPI
JR NZ,.NEXT_IDE
INC (IX+3)
.NEXT_IDE:
ADD IY,DE
DJNZ .CHECK_IDE
;
.check_exit:
POP IY
POP AF
OUT (SLOT3),A
XOR A
RET
;
; A=#FF
; .CHECK_FDD:
; INC (IX+1)
; LD B,8
; .TFD0: CP (HL)
; INC HL
; RET NZ
; DJNZ .TFD0
; DEC (IX+1)
; RET
; ;
INCLUDE 'EXTENDED/FDD_DRIVER.asm'
INCLUDE 'EXTENDED/RAM_DISK_DRIVER.asm'
INCLUDE 'EXTENDED/IDE/ATA_DRV.asm'
INCLUDE 'EXTENDED/IDE/ATAPI_DRV.asm'
INCLUDE 'EXTENDED/IDE/SHARED.asm'
;DISPLAY " EXTENDED end addr: ", /A, $
;

0
src/bios/exp/FUNC_CMOS.ASM → bios/exp/FUNC_CMOS.ASM
View File

0
src/bios/exp/FUNC_FOR_TRDOS.ASM → bios/exp/FUNC_FOR_TRDOS.ASM
View File

4808
src/bios/exp/FUNC_LOW_PRINT.ASM → bios/exp/FUNC_LOW_PRINT.ASM
View File

File diff suppressed because it is too large Load Diff

2262
src/bios/exp/FUNC_RAM_ROM_DRV.ASM → bios/exp/FUNC_RAM_ROM_DRV.ASM
View File

File diff suppressed because it is too large Load Diff

2290
src/bios/exp/FUNC_SCREEN.ASM → bios/exp/FUNC_SCREEN.ASM
View File

File diff suppressed because it is too large Load Diff

1272
src/bios/exp/FUNC_SERVICE.asm → bios/exp/FUNC_SERVICE.asm
View File

File diff suppressed because it is too large Load Diff

0
src/bios/exp/FUNC_SYS.ASM → bios/exp/FUNC_SYS.ASM
View File

0
src/bios/exp/ZX_MEM.TXT → bios/exp/ZX_MEM.TXT
View File

8
src/bios/loader/bitstream_header.inc → bios/loader/bitstream_header.inc
View File

@ -1,5 +1,5 @@
; Header of bitstream which non packed
DB #FF,#FF,#62,#7B,#39,#00;,#FF,#FF ; 1k30
; Packed:
;DB #FF,#FF,#62,#7B,#3C,#00;,#01,#FF ; 1k50
; Header of bitstream which non packed
DB #FF,#FF,#62,#7B,#39,#00;,#FF,#FF ; 1k30
; Packed:
;DB #FF,#FF,#62,#7B,#3C,#00;,#01,#FF ; 1k50
;

338
src/bios/loader/loader.asm → bios/loader/loader.asm
View File

@ -1,169 +1,169 @@
;
;**********************************;
; ACEX Loading program ;
;**********************************;
MACRO Conf_loader altera_chip
.START: DI
LD BC,#FF*256 + Z84.SYS.Control
XOR A ; Z84.REG.WaitState_Ctrl - register - waits
OUT (C),A ; Z84.SYS.Control
INC C ; LD BC,#FFEF
LD A,4 ; Memory waits set to 1
OUT (C),A ; Z84.SYS.Data
DEC C ; Z84.SYS.Control
DEC A ; LD A,3 - 3-nd register - boundaries
OUT (C),A ; Z84.REG.Misc_Ctrl
INC C ; cs0 enable, cs1 enable, 32-Bit CRC disable, reset output enable, Clock Divide-by-two
OUT (C),A ; Z84.SYS.Data
DEC C ; Z84.SYS.Control
DEC A ; LD A,2 - Z84.REG..CS_Boundary 2-nd register - boundaries
OUT (C),A ; Z84.SYS.Data
INC C
LD A,#FE ; boundaries FFFF..F000 - CS1
OUT (C),A ; EFFF..0000 - CS0
JR .LOOP_S1
;**************************************
BLOCK #38-$,#FF
JP 0
;**************************************
.LOOP_S1:
LD HL,#FEF0 ; !HARDCODE
LD DE,.STRING
.LOOP_S:
LD A,(DE)
CP (HL)
JR NZ,.NO_CNF_RAM
INC E
INC L
JR NZ,.LOOP_S ; !!!!! ¯à¨¢ï§ª  ª  ¤à¥áã ¢ HL
; !TODO ã¡à âì ¢¥©âë ¤«ï ªíè ?
LD BC,#FF*256 + Z84.SYS.Control
LD A,Z84.REG.CS_Boundary
OUT (C),A ; 0 register - waits
INC C
LD A,#F0
OUT (C),A ; boundaries FFFF..1000 - CS1
; ; 0FFF..0000 - CS0
LD HL,#1000 ; !!!!! Load bitstream from Fast-RAM
JR .NEW_SHM
;**************************************
BLOCK #66-$,#FF
JP 0
;**************************************
.NO_CNF_RAM:
LD HL,#0100 ; !!!!! Load bitstream from ROM
.NEW_SHM:
;--------------[conf check]-------------
LD A,H ; á®å࠭塞 áâ à訩  ¤à¥á ­ ç «  ª®­äë,
; ­ ç «® ª®­äë ¤®«¦­® ¡ëâì á ¬« ¤è¨¬  ¤à¥á®¬ = 0
EXX
LD L,0
LD H,A
EX AF,AF'
; ¢ HL  ¤à¥á ¯¥à¢®£® ¡ ©â  ª®­äë
LD DE,.Conf_header
LD B,.Conf_header.length
.conf_header_loop:
LD A,(DE)
CP (HL)
JR NZ,.Conf_Packed
INC DE
INC L
DJNZ .conf_header_loop
;XOR A
JR .exit_conf_check
.Conf_Packed:
SCF
.exit_conf_check:
EX AF,AF'
EXX
;---------------------------------------
LD DE,#FE00 ;!HARDCODE ; !!!!! Check flag "don't erase fast-ram bitstream" - "IM"
LD A,(#FEE0)
CP "I"
JR NZ,.ONES_CONFIG
LD A,(#FEE1)
CP "M"
JR NZ,.ONES_CONFIG
DEC D ; multiple config!
.ONES_CONFIG:
LD IY,SP2000_Loader_Flag
;LD IX,#FFFD
LD IX,ACEX.Config_ID.Sp2000
.LOOP1:
LD A,(HL)
ex af,AF'
ld b,1
jr nc,.no_packed_loop
ex af,AF'
LD B,A ; save byte to B to check later if we worked with zero
OR A
JR NZ,.LOOP1A
INC HL
LD C,(HL) ; set counter
jr .LOOP1A
.no_packed_loop:
ex af,AF'
.LOOP1A:
;---[Sending bits to Altera]---[v]
DUP 7
LD (DE),A
RRCA
EDUP
LD (DE),A
;------------------------------[^]
INC E
LD A,B ; was it zero?
OR A
JR NZ,.LOOP1E
; it was zero so we need to decrement counter
DEC C
JR NZ,.LOOP1A
; end of the counter reached
.LOOP1E:
INC HL
JR .LOOP1
.STRING: DB ACEX.RELOAD_STRING
.Conf_header: include 'src/bios/Loader/bitstream_header.inc'
.Conf_header.length EQU $-.Conf_header
;----------------------;
BLOCK #FE-$,#FF
; <20>â®, ᪮॥ ¢á¥£®, à㤨¬¥­â, â®â á ¬ë© ¡ ©â ®¯¨á â¥«ï ª®­äë,
; ª®â®àë© ¨é¥â § £àã§ç¨ª ¤«ï Sp97 ¯® áâ à®¬ã  ¤à¥áã #C090.
; ‚®âª­ã« ¥£® ¢ ª®­æ¥ § £àã§ç¨ª , ¬®¦¥â ¯®â®¬ ¯à¨£®¤¨âáï.
.DEF_SYM: DW ACEX.Config_ID.Sp2000
;------------------------------[Loader end]
DEFINE Altera_Chip altera_chip
LUA
local file_path = 'Build/ACEX/'
local file_ext = '.BIN'
local altera_ver = sj.get_define("Altera_Chip")
sj.insert_define("Altera_File", '"' .. file_path .. altera_ver .. file_ext .. '"')
ENDLUA
UNDEFINE Altera_Chip
INCBIN Altera_File
UNDEFINE Altera_File
ENDM
;
;
;**********************************;
; ACEX Loading program ;
;**********************************;
MACRO Conf_loader altera_chip
.START: DI
LD BC,#FF*256 + Z84.SYS.Control
XOR A ; Z84.REG.WaitState_Ctrl - register - waits
OUT (C),A ; Z84.SYS.Control
INC C ; LD BC,#FFEF
LD A,4 ; Memory waits set to 1
OUT (C),A ; Z84.SYS.Data
DEC C ; Z84.SYS.Control
DEC A ; LD A,3 - 3-nd register - boundaries
OUT (C),A ; Z84.REG.Misc_Ctrl
INC C ; cs0 enable, cs1 enable, 32-Bit CRC disable, reset output enable, Clock Divide-by-two
OUT (C),A ; Z84.SYS.Data
DEC C ; Z84.SYS.Control
DEC A ; LD A,2 - Z84.REG..CS_Boundary 2-nd register - boundaries
OUT (C),A ; Z84.SYS.Data
INC C
LD A,#FE ; boundaries FFFF..F000 - CS1
OUT (C),A ; EFFF..0000 - CS0
JR .LOOP_S1
;**************************************
BLOCK #38-$,#FF
JP 0
;**************************************
.LOOP_S1:
LD HL,#FEF0 ; !HARDCODE
LD DE,.STRING
.LOOP_S:
LD A,(DE)
CP (HL)
JR NZ,.NO_CNF_RAM
INC E
INC L
JR NZ,.LOOP_S ; !!!!! ¯à¨¢ï§ª  ª  ¤à¥áã ¢ HL
; !TODO ã¡à âì ¢¥©âë ¤«ï ªíè ?
LD BC,#FF*256 + Z84.SYS.Control
LD A,Z84.REG.CS_Boundary
OUT (C),A ; 0 register - waits
INC C
LD A,#F0
OUT (C),A ; boundaries FFFF..1000 - CS1
; ; 0FFF..0000 - CS0
LD HL,#1000 ; !!!!! Load bitstream from Fast-RAM
JR .NEW_SHM
;**************************************
BLOCK #66-$,#FF
JP 0
;**************************************
.NO_CNF_RAM:
LD HL,#0100 ; !!!!! Load bitstream from ROM
.NEW_SHM:
;--------------[conf check]-------------
LD A,H ; á®å࠭塞 áâ à訩  ¤à¥á ­ ç «  ª®­äë,
; ­ ç «® ª®­äë ¤®«¦­® ¡ëâì á ¬« ¤è¨¬  ¤à¥á®¬ = 0
EXX
LD L,0
LD H,A
EX AF,AF'
; ¢ HL  ¤à¥á ¯¥à¢®£® ¡ ©â  ª®­äë
LD DE,.Conf_header
LD B,.Conf_header.length
.conf_header_loop:
LD A,(DE)
CP (HL)
JR NZ,.Conf_Packed
INC DE
INC L
DJNZ .conf_header_loop
;XOR A
JR .exit_conf_check
.Conf_Packed:
SCF
.exit_conf_check:
EX AF,AF'
EXX
;---------------------------------------
LD DE,#FE00 ;!HARDCODE ; !!!!! Check flag "don't erase fast-ram bitstream" - "IM"
LD A,(#FEE0)
CP "I"
JR NZ,.ONES_CONFIG
LD A,(#FEE1)
CP "M"
JR NZ,.ONES_CONFIG
DEC D ; multiple config!
.ONES_CONFIG:
LD IY,SP2000_Loader_Flag
;LD IX,#FFFD
LD IX,ACEX.Config_ID.Sp2000
.LOOP1:
LD A,(HL)
ex af,AF'
ld b,1
jr nc,.no_packed_loop
ex af,AF'
LD B,A ; save byte to B to check later if we worked with zero
OR A
JR NZ,.LOOP1A
INC HL
LD C,(HL) ; set counter
jr .LOOP1A
.no_packed_loop:
ex af,AF'
.LOOP1A:
;---[Sending bits to Altera]---[v]
DUP 7
LD (DE),A
RRCA
EDUP
LD (DE),A
;------------------------------[^]
INC E
LD A,B ; was it zero?
OR A
JR NZ,.LOOP1E
; it was zero so we need to decrement counter
DEC C
JR NZ,.LOOP1A
; end of the counter reached
.LOOP1E:
INC HL
JR .LOOP1
.STRING: DB ACEX.RELOAD_STRING
.Conf_header: include 'bios/Loader/bitstream_header.inc'
.Conf_header.length EQU $-.Conf_header
;----------------------;
BLOCK #FE-$,#FF
; <20>â®, ᪮॥ ¢á¥£®, à㤨¬¥­â, â®â á ¬ë© ¡ ©â ®¯¨á â¥«ï ª®­äë,
; ª®â®àë© ¨é¥â § £àã§ç¨ª ¤«ï Sp97 ¯® áâ à®¬ã  ¤à¥áã #C090.
; ‚®âª­ã« ¥£® ¢ ª®­æ¥ § £àã§ç¨ª , ¬®¦¥â ¯®â®¬ ¯à¨£®¤¨âáï.
.DEF_SYM: DW ACEX.Config_ID.Sp2000
;------------------------------[Loader end]
DEFINE Altera_Chip altera_chip
LUA
local file_path = 'Build/ACEX/'
local file_ext = '.BIN'
local altera_ver = sj.get_define("Altera_Chip")
sj.insert_define("Altera_File", '"' .. file_path .. altera_ver .. file_ext .. '"')
ENDLUA
UNDEFINE Altera_Chip
INCBIN Altera_File
UNDEFINE Altera_File
ENDM
;

0
src/bios/logo/Projects/LOGO.PAK → bios/logo/Projects/LOGO.PAK
View File

0
src/bios/logo/Projects/LOGO.bmp → bios/logo/Projects/LOGO.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 10 KiB

After

Width:  |  Height:  |  Size: 10 KiB

0
src/bios/logo/Projects/MAIN.xcf → bios/logo/Projects/MAIN.xcf
View File

0
src/bios/logo/Projects/NY_Kokoshnik.PAK → bios/logo/Projects/NY_Kokoshnik.PAK
View File

0
src/bios/logo/Projects/NY_Kokoshnik.bmp → bios/logo/Projects/NY_Kokoshnik.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 3.0 KiB

After

Width:  |  Height:  |  Size: 3.0 KiB

0
src/bios/logo/Projects/NY_mustache.PAK → bios/logo/Projects/NY_mustache.PAK
View File

0
src/bios/logo/Projects/NY_mustache.bmp → bios/logo/Projects/NY_mustache.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 1.3 KiB

After

Width:  |  Height:  |  Size: 1.3 KiB

0
src/bios/logo/Projects/test.png → bios/logo/Projects/test.png
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 8.9 KiB

After

Width:  |  Height:  |  Size: 8.9 KiB

4
src/bios/logo/Set_Pictures.asm → bios/logo/Set_Pictures.asm
View File

@ -101,8 +101,8 @@ days_table:
.November EQU 0
.December: DZ 31
NewYear: INCLUDE './src/bios/logo/use/New_Year.inc'
;.March8: INCLUDE './src/bios/logo/use/March_8.inc'
NewYear: INCLUDE './bios/logo/use/New_Year.inc'
;.March8: INCLUDE './bios/logo/use/March_8.inc'
ENDIF

8
src/bios/logo/clean.cmd → bios/logo/clean.cmd
View File

@ -1,4 +1,4 @@
@echo off
del *.bin /s
del *.lst /s
del *.log /s
@echo off
del *.bin /s
del *.lst /s
del *.log /s

8
src/bios/logo/compile.log → bios/logo/compile.log
View File

@ -1,4 +1,4 @@
Extractor BMP-files for Sprinter BIOS logo
Copyright (c) 2022 Sprinter Team
File [psfathers.bmp], found 8 bit BMP 128x72, output RGB4 [LOGO_PAL.BIN] and [LOGO_DAT.BIN]
Done.
Extractor BMP-files for Sprinter BIOS logo
Copyright (c) 2022 Sprinter Team
File [psfathers.bmp], found 8 bit BMP 128x72, output RGB4 [LOGO_PAL.BIN] and [LOGO_DAT.BIN]
Done.

46
src/bios/logo/make.cmd → bios/logo/make.cmd
View File

@ -1,23 +1,23 @@
rem @echo off
set BIN=..\..\bin
set LOG=compile.log
for /F %%i in ('date /t') do set mydate=%%i
for /F %%i in ('time /t') do set mytime=%%i
set mydt=%mydate% %mytime%
rem set LOGO_FILE=peters.bmp
set LOGO_FILE=psfathers.bmp
echo 5. [1/1] BMP LOGO
echo %mydt%: [1/1] BMP LOGO > %LOG%
%BIN%\bmp_extract.exe %LOGO_FILE% /pn LOGO_PAL.BIN /dn LOGO_DAT.BIN /pt 4 >> %LOG%
if errorlevel 1 goto error
goto quit
:error
echo ERROR during compile BMP LOGO
pause 0
exit 3
:quit
rem @echo off
set BIN=..\..\bin
set LOG=compile.log
for /F %%i in ('date /t') do set mydate=%%i
for /F %%i in ('time /t') do set mytime=%%i
set mydt=%mydate% %mytime%
rem set LOGO_FILE=peters.bmp
set LOGO_FILE=psfathers.bmp
echo 5. [1/1] BMP LOGO
echo %mydt%: [1/1] BMP LOGO > %LOG%
%BIN%\bmp_extract.exe %LOGO_FILE% /pn LOGO_PAL.BIN /dn LOGO_DAT.BIN /pt 4 >> %LOG%
if errorlevel 1 goto error
goto quit
:error
echo ERROR during compile BMP LOGO
pause 0
exit 3
:quit

0
src/bios/logo/peters.bmp → bios/logo/peters.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 10 KiB

After

Width:  |  Height:  |  Size: 10 KiB

0
src/bios/logo/pfathers.bmp → bios/logo/pfathers.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 10 KiB

After

Width:  |  Height:  |  Size: 10 KiB

0
src/bios/logo/psclean.bmp → bios/logo/psclean.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 10 KiB

After

Width:  |  Height:  |  Size: 10 KiB

0
src/bios/logo/psfathers.bmp → bios/logo/psfathers.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 10 KiB

After

Width:  |  Height:  |  Size: 10 KiB

0
src/bios/logo/use/LOGO.bmp → bios/logo/use/LOGO.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 10 KiB

After

Width:  |  Height:  |  Size: 10 KiB

0
src/bios/logo/use/NY_Kokoshnik.bmp → bios/logo/use/NY_Kokoshnik.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 3.0 KiB

After

Width:  |  Height:  |  Size: 3.0 KiB

0
src/bios/logo/use/NY_Kokoshnik_DAT.BIN → bios/logo/use/NY_Kokoshnik_DAT.BIN
View File

0
src/bios/logo/use/NY_mustache.bmp → bios/logo/use/NY_mustache.bmp
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 1.3 KiB

After

Width:  |  Height:  |  Size: 1.3 KiB

0
src/bios/logo/use/NY_mustache_DAT.BIN → bios/logo/use/NY_mustache_DAT.BIN
View File

16
bios/logo/use/New_Year.inc Normal file
View File

@ -0,0 +1,16 @@
MODULE _mNewYear
LUA PASS1
make_pic_files ("./bios/logo/use/NY_Kokoshnik", 0, 1)
make_pic_files ("./bios/logo/use/NY_mustache", 0, 1)
print()
ENDLUA
BYTE 2 ; ª®«¨ç¥á⢮ á¯à ©â®¢
EasterTable 48, 42, 13, 2, sprite1
EasterTable 37, 6, 69, 26, sprite2
sprite1: INCBIN './bios/logo/use/NY_Kokoshnik_DAT.bin'
sprite2: INCBIN './bios/logo/use/NY_mustache_DAT.bin'
ENDMODULE
;

30
src/bios/mem_map.txt → bios/mem_map.txt
View File

@ -1,16 +1,16 @@
#10 - EXTENSION
#11 - LOGO #2800 bytes
#12 - sp_128
#13 - sp_48
#14 - sp_trd
#15 - ROM Disk Recovery
#16 - ROM Disk Recovery
#17 - ROM Disk Recovery
#18 - BIOS
#19 - ROM Disk Recovery
#1A - ROM Disk Recovery
#1B - ROM Disk Recovery
#1C - Loader #100 bytes, bitstream #3F00 bytes
#1D - Bitstream #4000 bytes
#1E - Bitstream #4000 bytes
#10 - EXTENSION
#11 - LOGO #2800 bytes
#12 - sp_128
#13 - sp_48
#14 - sp_trd
#15 - ROM Disk Recovery
#16 - ROM Disk Recovery
#17 - ROM Disk Recovery
#18 - BIOS
#19 - ROM Disk Recovery
#1A - ROM Disk Recovery
#1B - ROM Disk Recovery
#1C - Loader #100 bytes, bitstream #3F00 bytes
#1D - Bitstream #4000 bytes
#1E - Bitstream #4000 bytes
#1F - Bitstream #4000 bytes

10
src/bios/rom/BIOS.inc → bios/rom/BIOS.inc
View File

@ -1,5 +1,5 @@
;WITH_BUILD EQU 1 ;BIOS NUMBER INCLUDED BUILD NUMBER
TEST_Build EQU 0
Logo_X_size EQU 128
Logo_Y_size EQU 72
;WITH_2IDE EQU 1 ;SECONDARY IDE
;WITH_BUILD EQU 1 ;BIOS NUMBER INCLUDED BUILD NUMBER
TEST_Build EQU 0
Logo_X_size EQU 128
Logo_Y_size EQU 72
;WITH_2IDE EQU 1 ;SECONDARY IDE

144
src/bios/rom/MEM_MAP.inc → bios/rom/MEM_MAP.inc
View File

@ -1,72 +1,72 @@
;
; ÛÛÛÛÛÛ» ÛÛÛÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛÛÛ» ÛÛÛÛÛÛ»
; ÛÛÉÍÍÛÛ»ÛÛÉÍÍÍÛÛ»ÛÛÛÛ» ÛÛÛÛº ÛÛÛÛ» ÛÛÛÛºÛÛÉÍÍÛÛ»ÛÛÉÍÍÛÛ»
; ÛÛÛÛÛÛɼÛÛº ÛÛºÛÛÉÛÛÛÛÉÛÛº ÛÛÉÛÛÛÛÉÛÛºÛÛÛÛÛÛÛºÛÛÛÛÛÛɼ
; ÛÛÉÍÍÛÛ»ÛÛº ÛÛºÛÛºÈÛÛɼÛÛº ÛÛºÈÛÛɼÛÛºÛÛÉÍÍÛÛºÛÛÉÍÍͼ
; ÛÛº ÛÛºÈÛÛÛÛÛÛɼÛÛº Èͼ ÛÛº ÛÛº Èͼ ÛÛºÛÛº ÛÛºÛÛº
; Èͼ Èͼ ÈÍÍÍÍͼ Èͼ Èͼ Èͼ ÈͼÈͼ ÈͼÈͼ
;
ROM_MAP:
.EXP EQU 0
.EXP.STACK EQU #C000
.ROM EQU 0
.LOADER EQU 0
.LOGO EQU 0
IF PACKED_MAIN
.SETUP EQU #1000
ELSE
.SETUP EQU BLOCK_Setup
ENDIF
;
;
; ÛÛÛ» ÛÛÛ»ÛÛÛÛÛÛÛ»ÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛÛÛ» ÛÛÛÛÛÛ»
; ÛÛÛÛ» ÛÛÛÛºÛÛÉÍÍÍͼÛÛÛÛ» ÛÛÛÛº ÛÛÛÛ» ÛÛÛÛºÛÛÉÍÍÛÛ»ÛÛÉÍÍÛÛ»
; ÛÛÉÛÛÛÛÉÛÛºÛÛÛÛÛ» ÛÛÉÛÛÛÛÉÛÛº ÛÛÉÛÛÛÛÉÛÛºÛÛÛÛÛÛÛºÛÛÛÛÛÛɼ
; ÛÛºÈÛÛɼÛÛºÛÛÉÍͼ ÛÛºÈÛÛɼÛÛº ÛÛºÈÛÛɼÛÛºÛÛÉÍÍÛÛºÛÛÉÍÍͼ
; ÛÛº Èͼ ÛÛºÛÛÛÛÛÛÛ»ÛÛº Èͼ ÛÛº ÛÛº Èͼ ÛÛºÛÛº ÛÛºÛÛº
; Èͼ ÈͼÈÍÍÍÍÍͼÈͼ Èͼ Èͼ ÈͼÈͼ ÈͼÈͼ
;
MEM_MAP:
.SETUP EQU COMPILE_ADDR.SETUP
;.ID_Version EQU COMPILE_ADDR.EXP + #C0
;
; ÛÛÛÛÛÛ» ÛÛÛÛÛÛ» ÛÛÛÛÛÛ» ÛÛÛÛÛÛÛ»
; ÛÛÉÍÍÍÛÛ»ÛÛÉÍÍÛÛ»ÛÛÉÍÍÍͼ ÛÛÉÍÍÍͼ
; ÛÛº ÛÛºÛÛÛÛÛÛɼÛÛº ÛÛÛ»ÛÛÛÛÛÛÛ»
; ÛÛº ÛÛºÛÛÉÍÍÛÛ»ÛÛº ÛÛºÈÍÍÍÍÛÛº
; ÈÛÛÛÛÛÛɼÛÛº ÛÛºÈÛÛÛÛÛÛɼÛÛÛÛÛÛÛº
; ÈÍÍÍÍͼ Èͼ Èͼ ÈÍÍÍÍͼ ÈÍÍÍÍÍͼ
;
COMPILE_ADDR:
.EXP EQU 0
.ROM EQU 0
.LOADER EQU 0
.MAIN EQU #8000
.SETUP EQU #8000
.DEPACK EQU #D000
.SETUP_STARTER EQU .SETUP + SETUP_MAIN.Size ;#C000
;
; ÛÛÛÛÛÛ» ÛÛÛÛÛÛÛ»ÛÛÛÛÛÛ» ÛÛÛÛÛ» ÛÛÛÛÛÛ»ÛÛ» ÛÛ»ÛÛÛÛÛÛÛ»ÛÛÛÛÛÛ»
; ÛÛÉÍÍÛÛ»ÛÛÉÍÍÍͼÛÛÉÍÍÛÛ»ÛÛÉÍÍÛÛ»ÛÛÉÍÍÍͼÛÛº ÛÛɼÛÛÉÍÍÍͼÛÛÉÍÍÛÛ»
; ÛÛº ÛÛºÛÛÛÛÛ» ÛÛÛÛÛÛɼÛÛÛÛÛÛÛºÛÛº ÛÛÛÛÛɼ ÛÛÛÛÛ» ÛÛÛÛÛÛɼ
; ÛÛº ÛÛºÛÛÉÍͼ ÛÛÉÍÍͼ ÛÛÉÍÍÛÛºÛÛº ÛÛÉÍÛÛ» ÛÛÉÍͼ ÛÛÉÍÍÛÛ»
; ÛÛÛÛÛÛɼÛÛÛÛÛÛÛ»ÛÛº ÛÛº ÛÛºÈÛÛÛÛÛÛ»ÛÛº ÛÛ»ÛÛÛÛÛÛÛ»ÛÛº ÛÛº
; ÈÍÍÍÍͼ ÈÍÍÍÍÍͼÈͼ Èͼ Èͼ ÈÍÍÍÍͼÈͼ ÈͼÈÍÍÍÍÍͼÈͼ Èͼ
;
IF PACKED_MAIN
IFNDEF PREBUILD ; ­¥¨§¢¥áâ­ë¥ ¬¥âª¨ ¯à¨ ¯à¥ª®¬¯¨«ï樨 MAIN.BIN
DEPACKER:
.Addr EQU SETUP_MAIN.Depacker
.WorkAddr EQU COMPILE_ADDR.DEPACK
.PackedMAIN EQU UnPacker.PackedMAIN
.UnpackAddr EQU COMPILE_ADDR.MAIN
.CodeLength EQU UnPacker.Length
.UnpackedEXECaddr EQU MAIN_START
.Length EQU DEPACK_DATA.length
;Depacker_start EQU #D000
;Depacked_logo_start EQU #D900
ENDIF
ENDIF
;
; ÛÛÛÛÛÛ» ÛÛÛÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛÛÛ» ÛÛÛÛÛÛ»
; ÛÛÉÍÍÛÛ»ÛÛÉÍÍÍÛÛ»ÛÛÛÛ» ÛÛÛÛº ÛÛÛÛ» ÛÛÛÛºÛÛÉÍÍÛÛ»ÛÛÉÍÍÛÛ»
; ÛÛÛÛÛÛɼÛÛº ÛÛºÛÛÉÛÛÛÛÉÛÛº ÛÛÉÛÛÛÛÉÛÛºÛÛÛÛÛÛÛºÛÛÛÛÛÛɼ
; ÛÛÉÍÍÛÛ»ÛÛº ÛÛºÛÛºÈÛÛɼÛÛº ÛÛºÈÛÛɼÛÛºÛÛÉÍÍÛÛºÛÛÉÍÍͼ
; ÛÛº ÛÛºÈÛÛÛÛÛÛɼÛÛº Èͼ ÛÛº ÛÛº Èͼ ÛÛºÛÛº ÛÛºÛÛº
; Èͼ Èͼ ÈÍÍÍÍͼ Èͼ Èͼ Èͼ ÈͼÈͼ ÈͼÈͼ
;
ROM_MAP:
.EXP EQU 0
.EXP.STACK EQU #C000
.ROM EQU 0
.LOADER EQU 0
.LOGO EQU 0
IF PACKED_MAIN
.SETUP EQU #1000
ELSE
.SETUP EQU BLOCK_Setup
ENDIF
;
;
; ÛÛÛ» ÛÛÛ»ÛÛÛÛÛÛÛ»ÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛ» ÛÛÛÛÛ» ÛÛÛÛÛÛ»
; ÛÛÛÛ» ÛÛÛÛºÛÛÉÍÍÍͼÛÛÛÛ» ÛÛÛÛº ÛÛÛÛ» ÛÛÛÛºÛÛÉÍÍÛÛ»ÛÛÉÍÍÛÛ»
; ÛÛÉÛÛÛÛÉÛÛºÛÛÛÛÛ» ÛÛÉÛÛÛÛÉÛÛº ÛÛÉÛÛÛÛÉÛÛºÛÛÛÛÛÛÛºÛÛÛÛÛÛɼ
; ÛÛºÈÛÛɼÛÛºÛÛÉÍͼ ÛÛºÈÛÛɼÛÛº ÛÛºÈÛÛɼÛÛºÛÛÉÍÍÛÛºÛÛÉÍÍͼ
; ÛÛº Èͼ ÛÛºÛÛÛÛÛÛÛ»ÛÛº Èͼ ÛÛº ÛÛº Èͼ ÛÛºÛÛº ÛÛºÛÛº
; Èͼ ÈͼÈÍÍÍÍÍͼÈͼ Èͼ Èͼ ÈͼÈͼ ÈͼÈͼ
;
MEM_MAP:
.SETUP EQU COMPILE_ADDR.SETUP
;.ID_Version EQU COMPILE_ADDR.EXP + #C0
;
; ÛÛÛÛÛÛ» ÛÛÛÛÛÛ» ÛÛÛÛÛÛ» ÛÛÛÛÛÛÛ»
; ÛÛÉÍÍÍÛÛ»ÛÛÉÍÍÛÛ»ÛÛÉÍÍÍͼ ÛÛÉÍÍÍͼ
; ÛÛº ÛÛºÛÛÛÛÛÛɼÛÛº ÛÛÛ»ÛÛÛÛÛÛÛ»
; ÛÛº ÛÛºÛÛÉÍÍÛÛ»ÛÛº ÛÛºÈÍÍÍÍÛÛº
; ÈÛÛÛÛÛÛɼÛÛº ÛÛºÈÛÛÛÛÛÛɼÛÛÛÛÛÛÛº
; ÈÍÍÍÍͼ Èͼ Èͼ ÈÍÍÍÍͼ ÈÍÍÍÍÍͼ
;
COMPILE_ADDR:
.EXP EQU 0
.ROM EQU 0
.LOADER EQU 0
.MAIN EQU #8000
.SETUP EQU #8000
.DEPACK EQU #D000
.SETUP_STARTER EQU .SETUP + SETUP_MAIN.Size ;#C000
;
; ÛÛÛÛÛÛ» ÛÛÛÛÛÛÛ»ÛÛÛÛÛÛ» ÛÛÛÛÛ» ÛÛÛÛÛÛ»ÛÛ» ÛÛ»ÛÛÛÛÛÛÛ»ÛÛÛÛÛÛ»
; ÛÛÉÍÍÛÛ»ÛÛÉÍÍÍͼÛÛÉÍÍÛÛ»ÛÛÉÍÍÛÛ»ÛÛÉÍÍÍͼÛÛº ÛÛɼÛÛÉÍÍÍͼÛÛÉÍÍÛÛ»
; ÛÛº ÛÛºÛÛÛÛÛ» ÛÛÛÛÛÛɼÛÛÛÛÛÛÛºÛÛº ÛÛÛÛÛɼ ÛÛÛÛÛ» ÛÛÛÛÛÛɼ
; ÛÛº ÛÛºÛÛÉÍͼ ÛÛÉÍÍͼ ÛÛÉÍÍÛÛºÛÛº ÛÛÉÍÛÛ» ÛÛÉÍͼ ÛÛÉÍÍÛÛ»
; ÛÛÛÛÛÛɼÛÛÛÛÛÛÛ»ÛÛº ÛÛº ÛÛºÈÛÛÛÛÛÛ»ÛÛº ÛÛ»ÛÛÛÛÛÛÛ»ÛÛº ÛÛº
; ÈÍÍÍÍͼ ÈÍÍÍÍÍͼÈͼ Èͼ Èͼ ÈÍÍÍÍͼÈͼ ÈͼÈÍÍÍÍÍͼÈͼ Èͼ
;
IF PACKED_MAIN
IFNDEF PREBUILD ; ­¥¨§¢¥áâ­ë¥ ¬¥âª¨ ¯à¨ ¯à¥ª®¬¯¨«ï樨 MAIN.BIN
DEPACKER:
.Addr EQU SETUP_MAIN.Depacker
.WorkAddr EQU COMPILE_ADDR.DEPACK
.PackedMAIN EQU UnPacker.PackedMAIN
.UnpackAddr EQU COMPILE_ADDR.MAIN
.CodeLength EQU UnPacker.Length
.UnpackedEXECaddr EQU MAIN_START
.Length EQU DEPACK_DATA.length
;Depacker_start EQU #D000
;Depacked_logo_start EQU #D900
ENDIF
ENDIF

892
src/bios/rom/ROM.asm → bios/rom/ROM.asm
View File

@ -1,447 +1,447 @@
;
; MODULE ROM_PART
DISPLAY "\r\n/=====================[ROM part]=====================\\"
;------------[Begin of ROM]-------------
ROM_START:
DI
HALT
;---------------------------------------
;--------------[checksum]---------------
_mInfoBLOCK 4-$,#FF
Check_Sum:
DB #FF,#FF,#FF,#FF ; ¬¥áâ® ¤«ï ª®­â஫쭮© á㬬ë
;---------------------------------------
_mInfoBLOCK #10-$,#FF
RET
;---------------------------------------
;!TODO ¯à¨ªàãâ¨âì ª ROM.BIOS
;----------------[int]------------------
_mInfoBLOCK #38-$,#FF
; INT: PUSH BC
; PUSH AF
; LD C,SLOT3
; IN B,(C)
; LD A,SYS_PAGE
; OUT (C),A
; LD A,(SYS_PAGE.INT_ID)
; CP #AA
; JR Z,YESINT
; OUT (C),B
; JR NOINT
; YESINT: PUSH HL
; LD HL,(SYS_PAGE.INT_ADRESS)
; LD A,H
; OR L
; LD A,(SYS_PAGE.INT_PAGE)
; OUT (C),B
; CALL NZ,EXTINT
; POP HL
; NOINT: POP AF
; POP BC
EI
RETI
;---------------------------------------
;----------------[NMI]------------------
_mInfoBLOCK #66-$,#FF
NMI: RETN
;---------------------------------------
; ;----------------[int]------------------
; EXTINT: OR A
; RET Z
; ;LD C,SLOT1
; BIT 7,H
; JR Z,.L2
; LD C,SLOT2
; BIT 6,H
; JR Z,.L1
; LD C,SLOT3
; .L1: IN B,(C)
; PUSH BC
; OUT (C),A
; CALL .JPHL
; POP BC
; OUT (C),B
; RET
; ; ¯à®¢¥àª  ­  ­ã«¥¢®© á«®â
; .L2: BIT 6,H
; LD C,SLOT1
; JR NZ,.L1 ; ¯à®¤®«¦ ¥¬ ¥á«¨ ­¥­ã«¥¢®© á«®â
; ; ‚Ž’ ’“’ ŒŽ†<C5BD>Ž ‚‹“<E280B9>ˆ’œ <20><>Ž–…„“<E2809E>“ „‹Ÿ <20>Ž„‘’€<E28099>Ž‚Šˆ ‘’<E28098>€<EFBFBD>ˆ–› ‚ SLOT0 ˆ
; ; <20>…<EFBFBD>…•Ž„ <20>Ž <20><>…<EFBFBD>›‚€<E2809A>ˆž ‚ Ž<><C5BD>€<EFBFBD>Ž’—ˆŠ <20>Ž‹œ‡Ž‚€’…‹Ÿ —…<E28094>…‡ ¯à®æ¥¤ãàã ­  áâíª, ­ ¯à¨¬¥à
; IF TEST_INT
; LD HL,-.stackDepth - .switchProcedure.size + .patch+2
; ADD HL,SP
; PUSH HL
; LD HL,-.stackDepth - .switchProcedure.size ; memory stack use!
; ADD HL,SP ; stack
; PUSH HL ;  ¤à¥á ¯à®£à ¬¬ë .readProcedure
; LD DE,.switchProcedure ; ¯¥à¥­¥á⨠¯à®£à ¬¬ã ­  á⥪
; EX DE,HL
; LD BC,.switchProcedure.size
; LDIR
; RET
; ; ¯à®æ¥¤ãà , ¯¥à¥­®á¨¬ ï ­  á⥪ ¤«ï ¢ë§®¢  ¯à¥à뢠­¨ï ¯®«ì§®¢ â¥«ï ¨§ SLOT0
; ; ®áâ®à®¦­¥¥ á PUSH, ¥á«¨ ­ ¤® ¬­®£®, ⮠㢥«¨ç¨¢ © .stackDepth
; .switchProcedure:
; DEC DE
; POP HL
; LD (HL),E
; INC HL
; LD (HL),D
; LD C,SLOT0
; IN B,(C)
; PUSH BC
; OUT (C),A
; XOR A
; OUT (SYS_PORT.RAM),A
; .patch EQU $+1-.switchProcedure
; CALL .JPHL
; DI
; XOR A
; OUT (SYS_PORT.ROM),A
; POP BC
; OUT (C),B
; RET
; .JPHL: JP (HL)
; .stackDepth EQU 32 ; à ááâ®ï­¨¥ ®â ª®­æ  ¯à®æ¥¤ãàë ¤® ¢¥à設ë á⥪ .
; .switchProcedure.size EQU $-.switchProcedure
; ELSE
; SCF
; RET
; .JPHL: JP (HL)
; ENDIF
;---------------------------------------
/*
*/
;
; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ [___FOR ZX-MODE___] _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ;
;
;----------------------------[ FOR ZX-MODE ]----------------------------;
;!HARDCODE ­  íâ®â  ¤à¥á #‘0 ¯à룠¥â ¢ vROM Basic-48 ¯®  ¤à¥áã #3CF0
; ¬®¦­® ¯®¯à®¡®¢ âì ¯¥à¥¤¥« âì íâ®â  ¤à¥á â ¬
_mInfoBLOCK #C0-$,#FF
; ‚室 ç¥à¥§ USR 15600
RET_FROM_BIOS_TO_BASIC48:
CALL CH_2
CALL COMAND_LINE ; ‚›<E2809A>Ž‹<C5BD>…<EFBFBD>ˆ… ŠŽŒ€<C592>„›, …‘‹ˆ …‘’œ
; ‚室 ¡¥§ ª®¬ ­¤ë
JP _SW_ROM_1 ; ‚Ž‡‚<E280A1>€’ ‚ << MAIN MENU >>
INCLUDE 'ZX/ZX_FUNC.ASM'
INCLUDE 'ZX/ZX_MENU.ASM'
;-----------------------------------------------------------------------;
; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ;
;
;-------------[#1000 SETUP]-------------
ShowInfo 'Setup block of ROM start', 0 ; !!!!! test
BLOCK_Setup EQU $
;
IF PACKED_MAIN
BLOCK ROM_MAP.SETUP-$,#FF
DISP COMPILE_ADDR.SETUP
; Depacker version
SETUP_MAIN:
LD HL,DEPACKER.UnpackedEXECaddr; â®çª  ¢å®¤  ¢ à á¯ ª®¢ ­­®¬ ª®¤¥
PUSH HL
LD DE,DEPACKER.WorkAddr ;  ¤à¥á ¯à®æ¥¤ãàë ¤¥¯ ª¥à 
PUSH DE
LD HL,DEPACKER.Addr
LD BC,DEPACKER.Length
LDIR
LD HL,DEPACKER.PackedMAIN ; £¤¥  à娢
LD DE,DEPACKER.UnpackAddr ; ªã¤  à á¯ ª®¢ë¢ âì
RET
.Depacker EQU $
ENT
;-----------------[v]
DEPACK_DATA:
DISP DEPACKER.WorkAddr
MODULE UnPacker
INCLUDE 'src/bios/ROM/SETUP/DEHRUST.asm' ; !TODO ᤥ« âì ­  LUA  ¢â®¢ë¡®à ¤¥ª®¬¯à¥áá®à  ¨ ª®¬¯à¥áá®à 
PackedMAIN: INCBIN 'Build/Bin/temp/MAIN.PAK'
ENDMODULE
ENT
DEPACK_DATA.length EQU $-DEPACK_DATA
;-----------------[^]
ELSE
DISP COMPILE_ADDR.SETUP
ShowInfo 'Setup block DISP start', 1 ; !!!!! test
SETUP_MAIN: INCLUDE 'src/bios/ROM/SETUP/Main.asm'
SETUP_MAIN.Size EQU $-SETUP_MAIN
ShowInfo 'Setup block DISP end', 1 ; !!!!! test
ENT
ENDIF
ASSERT ($ + Setup_Starter.Size) < (STACK - STACK.Size), "WARNING: Stack area overlaps code..."
ShowInfo 'Setup block of ROM end', 0 ; !!!!! test
BLOCK_Setup.Length EQU $-BLOCK_Setup
;---------------------------------------
;
;
; !FIXIT ᤥ« âì í⨠䨪á¨à®¢ ­­ë¥  ¤à¥á  ®â¤¥«ì­ë¬ ä ©«®¬ ¨ á IF/ELSE ¨ ¯®¤ª«îç âì ¨å ¯®â®¬ ªã¤  ­ ¤®.
;----------------------------------------------------------------------;
; BLOCK #3CC0-$,255
; no-magics!
;MAGIC_1: ; ‡€ƒ‹“˜Š€ „‹Ÿ MAGIC
; PUSH AF
; LD A,ROM.EXT
; OUT (SYS_PORT.OFF),A
; POP AF
; JP MAGIC_1
;MAGIC_3:
; PUSH AF
; LD A,ROM.EXT
; OUT (SYS_PORT.OFF),A
; POP AF
; RETN
;MAGIC_2:
;; CALL MG_BEGIN
; JR MAGIC_3
;*************************
_mInfoBLOCK #3CE0-$,#FF ;!TEST 0
_SW_ROM_1 EQU SW_ROM_1
LD HL,#259F ;!HARDCODE Show Main Menu in BASIC-128
PUSH HL
LD HL,#5B00 ;!HARDCODE
LD A,(HL)
CP #F5 ; #F5 - ®¯ª®¤ 'PUSH AF'. <20>஢¥àï¥âáï ¢ #5B00
JR Z,_JP_HL_48 ; ‚Ž‡‚<E280A1>€’ Š Œ…<C592>ž BASIC128
POP HL
JR _SW_ROM_1 ; <20><>Ž‘’Ž‰ ‚Ž‡‚<E280A1>€’
;*************************
_mInfoBLOCK #3CF0-$,#FF ;!TEST 0
;JMP_48:
; LD HL,00h
; JR _JP_HL_48
;
; NOP
; NOP
; NOP
;***************************************
_mInfoBLOCK #3CF8-$,#FF ;!TEST 0
; no basic-48!
_JP_HL_48 EQU JP_HL_48
PUSH HL
_SW_ROM EQU SW_ROM
PUSH AF
LD A,ROM.BIOS
OUT (SYS_PORT.RAM),A
POP AF
RET
;***************************************
;----------------------------------------------------------------------;
;
;!TODO ᯥªâà㬮¢áª¨¥ ã⨫¨âë
;----------------------------------------------------------------------;
; _mInfoBLOCK #3CFA-$,#FF
; LD A,0 ;!HARDCODE
; OUT (SYS_PORT.OFF),A
; POP AF
;----------------------------------------------------------------------;
;
;
;----------------------------------------------------------------------;
_mInfoBLOCK #3D00-$,#FF
;DOS_ON:
NOP
RET
;***************************************
;***************************************
; BLOCK #3D02-$,FF
; !TODO ¬®¦­® ®¯à¨å®¤®¢ âì âãâ 17 ¡ ©â®¢
;
;***************************************
;***************************************
_mInfoBLOCK #3D13-$,#FF
NOP
CALL ToBIOS_FromEXT
JP DOS_OFF
;***************************************
;***************************************
; BLOCK #3D17-$,FF
; !TODO ¬®¦­® ®¯à¨å®¤®¢ âì âãâ 233 ¡ ©â 
;
;***************************************
;***************************************
_mInfoBLOCK #3E00-$,#FF
;DOS_OFF:
PUSH AF
LD A,R
DI
PUSH AF
PUSH BC
;
LD BC,(#5BFF) ; !HARDCODE
LD A,#C9 ; Opcode RET
LD (#5BFF),A ; !HARDCODE
CALL #5BFF ; !HARDCODE
LD (#5BFF),BC ; !HARDCODE
;
POP BC
POP AF
JP PO,.no_EI
EI
.no_EI: POP AF
RET
;***************************************
;***************************************
; BLOCK #3E16-$,FF
; !TODO ¬®¦­® ®¯à¨å®¤®¢ âì âãâ 10 ¡ ©â®¢
;
;***************************************
;
;
;---------------------------------------
; _mInfoBLOCK #3FC6-$,#FF
; ¨«¨ ¬®¦­® ¤®¡ ¢¨âì ä㭪樨
; TRDOS_HD_CMD:
; ; LD A,C
; ; OR #40
; ; LD C,A
; POP AF
; SET 6,C
; RST_to_BIOS
; JR RET_TO_TRDOS
;---------------------------------------
;
;--------------[GOTO BIOS]--------------
_mInfoBLOCK #3FD0-$,#FF
;ToBIOS_FromEXT: call BIOS from EXTENSION
PUSH AF
LD A,ROM.BIOS ; set BIOS to slot0
OUT (SYS_PORT.ROM),A
POP AF
RET
;---------------------------------------
;--------[ From TR-DOS to HDD part2]--------
_mInfoBLOCK #3FD8-$,#FF
TRDOS_HD_CMD:
POP AF
SET 6,C
RST_to_BIOS
JR RET_TO_TRDOS
;---------------------------------------
;!FIXIT ®áâ âª¨ ®â â¥á⮢ ˆ¢ ­  á® §¢ãª®¢®© ª à⮩
;-------------[SND_TEST_RET]-------------
_mInfoBLOCK #3FE0-$,#FF
; SND_TEST_RET:
; LD A,ROM.BIOS
; OUT (SYS_PORT.RAM),A
; ;JP SOUND_TEST
; JP #0000
;---------------------------------------
;------------[Portal to EXT]------------
; â®çª  ¢å®¤ /¢ë室  ¤«ï ä㭪権 ¨§ BIOS
_mInfoBLOCK #3FE8-$,#FF
RET_TO_BIOS: ;RET_TO_EXP:
PUSH AF
LD A,ROM.BIOS
OUT (SYS_PORT.ROM),A ; from BIOS EXTENSION_FNs
POP AF
RET
; JP HDD_FN_5x
;---------------------------------------
;!FIXIT Œ®¦­® ¯®¯à ¢¨âì ­®¬¥à  ä㭪権 ¯à¨ ¢ë§®¢ å ¨§ TR-DOS ¨ ¯à룠âì áࠧ㠢 BIOS
;-------[ From TR-DOS to API 4x ]-------
_mInfoBLOCK #3FF0-$,#FF
RET_TO_TRDOS:
PUSH AF
DI
LD A,ROM.BIOS
OUT (SYS_PORT.RAM),A
JR TRDOS_HD_CMD ; âãâ ­¥ 墠⨫® ¬¥áâ  ¢ 1 ¡ ©â, ç⮡ áà §ã ᤥ« âì JP
;---------------------------------------
;-----[???????????????????????????]-----
_mInfoBLOCK #3FF8-$,#FF
; PUSH AF
; LD A,ROM.BIOS
; OUT (SYS_PORT.RAM),A
; JP #0000
;---------------------------------------
_mInfoBLOCK #4000-$,#FF
;=======================================
IFNDEF PREBUILD
DISPLAY ' -------------------[Main.asm]-------------------'
DISPLAY 'End code address: ',/A,MAIN_END_CODE_ADDRESS
DISPLAY 'Code size: ',/A,MAIN_END_CODE_ADDRESS + 1 - COMPILE_ADDR.MAIN
DISPLAY 'End buffers address: ',/A,memBUFFER.End - 1
DISPLAY 'Free memory: ',/A,#C000 - (memBUFFER.End-1) - STACK.Size
DISPLAY 'Unused bytes before INT_POINTER: ',/A,INT_POINTER-before_intPointer
ENDIF
; ENDMODULE ;ROM_PART
;
DISPLAY ' '
;
; MODULE ROM_PART
DISPLAY "\r\n/=====================[ROM part]=====================\\"
;------------[Begin of ROM]-------------
ROM_START:
DI
HALT
;---------------------------------------
;--------------[checksum]---------------
_mInfoBLOCK 4-$,#FF
Check_Sum:
DB #FF,#FF,#FF,#FF ; ¬¥áâ® ¤«ï ª®­â஫쭮© á㬬ë
;---------------------------------------
_mInfoBLOCK #10-$,#FF
RET
;---------------------------------------
;!TODO ¯à¨ªàãâ¨âì ª ROM.BIOS
;----------------[int]------------------
_mInfoBLOCK #38-$,#FF
; INT: PUSH BC
; PUSH AF
; LD C,SLOT3
; IN B,(C)
; LD A,SYS_PAGE
; OUT (C),A
; LD A,(SYS_PAGE.INT_ID)
; CP #AA
; JR Z,YESINT
; OUT (C),B
; JR NOINT
; YESINT: PUSH HL
; LD HL,(SYS_PAGE.INT_ADRESS)
; LD A,H
; OR L
; LD A,(SYS_PAGE.INT_PAGE)
; OUT (C),B
; CALL NZ,EXTINT
; POP HL
; NOINT: POP AF
; POP BC
EI
RETI
;---------------------------------------
;----------------[NMI]------------------
_mInfoBLOCK #66-$,#FF
NMI: RETN
;---------------------------------------
; ;----------------[int]------------------
; EXTINT: OR A
; RET Z
; ;LD C,SLOT1
; BIT 7,H
; JR Z,.L2
; LD C,SLOT2
; BIT 6,H
; JR Z,.L1
; LD C,SLOT3
; .L1: IN B,(C)
; PUSH BC
; OUT (C),A
; CALL .JPHL
; POP BC
; OUT (C),B
; RET
; ; ¯à®¢¥àª  ­  ­ã«¥¢®© á«®â
; .L2: BIT 6,H
; LD C,SLOT1
; JR NZ,.L1 ; ¯à®¤®«¦ ¥¬ ¥á«¨ ­¥­ã«¥¢®© á«®â
; ; ‚Ž’ ’“’ ŒŽ†<C5BD>Ž ‚‹“<E280B9>ˆ’œ <20><>Ž–…„“<E2809E>“ „‹Ÿ <20>Ž„‘’€<E28099>Ž‚Šˆ ‘’<E28098>€<EFBFBD>ˆ–› ‚ SLOT0 ˆ
; ; <20>…<EFBFBD>…•Ž„ <20>Ž <20><>…<EFBFBD>›‚€<E2809A>ˆž ‚ Ž<><C5BD>€<EFBFBD>Ž’—ˆŠ <20>Ž‹œ‡Ž‚€’…‹Ÿ —…<E28094>…‡ ¯à®æ¥¤ãàã ­  áâíª, ­ ¯à¨¬¥à
; IF TEST_INT
; LD HL,-.stackDepth - .switchProcedure.size + .patch+2
; ADD HL,SP
; PUSH HL
; LD HL,-.stackDepth - .switchProcedure.size ; memory stack use!
; ADD HL,SP ; stack
; PUSH HL ;  ¤à¥á ¯à®£à ¬¬ë .readProcedure
; LD DE,.switchProcedure ; ¯¥à¥­¥á⨠¯à®£à ¬¬ã ­  á⥪
; EX DE,HL
; LD BC,.switchProcedure.size
; LDIR
; RET
; ; ¯à®æ¥¤ãà , ¯¥à¥­®á¨¬ ï ­  á⥪ ¤«ï ¢ë§®¢  ¯à¥à뢠­¨ï ¯®«ì§®¢ â¥«ï ¨§ SLOT0
; ; ®áâ®à®¦­¥¥ á PUSH, ¥á«¨ ­ ¤® ¬­®£®, ⮠㢥«¨ç¨¢ © .stackDepth
; .switchProcedure:
; DEC DE
; POP HL
; LD (HL),E
; INC HL
; LD (HL),D
; LD C,SLOT0
; IN B,(C)
; PUSH BC
; OUT (C),A
; XOR A
; OUT (SYS_PORT.RAM),A
; .patch EQU $+1-.switchProcedure
; CALL .JPHL
; DI
; XOR A
; OUT (SYS_PORT.ROM),A
; POP BC
; OUT (C),B
; RET
; .JPHL: JP (HL)
; .stackDepth EQU 32 ; à ááâ®ï­¨¥ ®â ª®­æ  ¯à®æ¥¤ãàë ¤® ¢¥à設ë á⥪ .
; .switchProcedure.size EQU $-.switchProcedure
; ELSE
; SCF
; RET
; .JPHL: JP (HL)
; ENDIF
;---------------------------------------
/*
*/
;
; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ [___FOR ZX-MODE___] _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ;
;
;----------------------------[ FOR ZX-MODE ]----------------------------;
;!HARDCODE ­  íâ®â  ¤à¥á #‘0 ¯à룠¥â ¢ vROM Basic-48 ¯®  ¤à¥áã #3CF0
; ¬®¦­® ¯®¯à®¡®¢ âì ¯¥à¥¤¥« âì íâ®â  ¤à¥á â ¬
_mInfoBLOCK #C0-$,#FF
; ‚室 ç¥à¥§ USR 15600
RET_FROM_BIOS_TO_BASIC48:
CALL CH_2
CALL COMAND_LINE ; ‚›<E2809A>Ž‹<C5BD>…<EFBFBD>ˆ… ŠŽŒ€<C592>„›, …‘‹ˆ …‘’œ
; ‚室 ¡¥§ ª®¬ ­¤ë
JP _SW_ROM_1 ; ‚Ž‡‚<E280A1>€’ ‚ << MAIN MENU >>
INCLUDE 'ZX/ZX_FUNC.ASM'
INCLUDE 'ZX/ZX_MENU.ASM'
;-----------------------------------------------------------------------;
; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ;
;
;-------------[#1000 SETUP]-------------
ShowInfo 'Setup block of ROM start', 0 ; !!!!! test
BLOCK_Setup EQU $
;
IF PACKED_MAIN
BLOCK ROM_MAP.SETUP-$,#FF
DISP COMPILE_ADDR.SETUP
; Depacker version
SETUP_MAIN:
LD HL,DEPACKER.UnpackedEXECaddr; â®çª  ¢å®¤  ¢ à á¯ ª®¢ ­­®¬ ª®¤¥
PUSH HL
LD DE,DEPACKER.WorkAddr ;  ¤à¥á ¯à®æ¥¤ãàë ¤¥¯ ª¥à 
PUSH DE
LD HL,DEPACKER.Addr
LD BC,DEPACKER.Length
LDIR
LD HL,DEPACKER.PackedMAIN ; £¤¥  à娢
LD DE,DEPACKER.UnpackAddr ; ªã¤  à á¯ ª®¢ë¢ âì
RET
.Depacker EQU $
ENT
;-----------------[v]
DEPACK_DATA:
DISP DEPACKER.WorkAddr
MODULE UnPacker
INCLUDE 'bios/ROM/SETUP/DEHRUST.asm' ; !TODO ᤥ« âì ­  LUA  ¢â®¢ë¡®à ¤¥ª®¬¯à¥áá®à  ¨ ª®¬¯à¥áá®à 
PackedMAIN: INCBIN 'Build/Bin/temp/MAIN.PAK'
ENDMODULE
ENT
DEPACK_DATA.length EQU $-DEPACK_DATA
;-----------------[^]
ELSE
DISP COMPILE_ADDR.SETUP
ShowInfo 'Setup block DISP start', 1 ; !!!!! test
SETUP_MAIN: INCLUDE 'bios/ROM/SETUP/Main.asm'
SETUP_MAIN.Size EQU $-SETUP_MAIN
ShowInfo 'Setup block DISP end', 1 ; !!!!! test
ENT
ENDIF
ASSERT ($ + Setup_Starter.Size) < (STACK - STACK.Size), "WARNING: Stack area overlaps code..."
ShowInfo 'Setup block of ROM end', 0 ; !!!!! test
BLOCK_Setup.Length EQU $-BLOCK_Setup
;---------------------------------------
;
;
; !FIXIT ᤥ« âì í⨠䨪á¨à®¢ ­­ë¥  ¤à¥á  ®â¤¥«ì­ë¬ ä ©«®¬ ¨ á IF/ELSE ¨ ¯®¤ª«îç âì ¨å ¯®â®¬ ªã¤  ­ ¤®.
;----------------------------------------------------------------------;
; BLOCK #3CC0-$,255
; no-magics!
;MAGIC_1: ; ‡€ƒ‹“˜Š€ „‹Ÿ MAGIC
; PUSH AF
; LD A,ROM.EXT
; OUT (SYS_PORT.OFF),A
; POP AF
; JP MAGIC_1
;MAGIC_3:
; PUSH AF
; LD A,ROM.EXT
; OUT (SYS_PORT.OFF),A
; POP AF
; RETN
;MAGIC_2:
;; CALL MG_BEGIN
; JR MAGIC_3
;*************************
_mInfoBLOCK #3CE0-$,#FF ;!TEST 0
_SW_ROM_1 EQU SW_ROM_1
LD HL,#259F ;!HARDCODE Show Main Menu in BASIC-128
PUSH HL
LD HL,#5B00 ;!HARDCODE
LD A,(HL)
CP #F5 ; #F5 - ®¯ª®¤ 'PUSH AF'. <20>஢¥àï¥âáï ¢ #5B00
JR Z,_JP_HL_48 ; ‚Ž‡‚<E280A1>€’ Š Œ…<C592>ž BASIC128
POP HL
JR _SW_ROM_1 ; <20><>Ž‘’Ž‰ ‚Ž‡‚<E280A1>€’
;*************************
_mInfoBLOCK #3CF0-$,#FF ;!TEST 0
;JMP_48:
; LD HL,00h
; JR _JP_HL_48
;
; NOP
; NOP
; NOP
;***************************************
_mInfoBLOCK #3CF8-$,#FF ;!TEST 0
; no basic-48!
_JP_HL_48 EQU JP_HL_48
PUSH HL
_SW_ROM EQU SW_ROM
PUSH AF
LD A,ROM.BIOS
OUT (SYS_PORT.RAM),A
POP AF
RET
;***************************************
;----------------------------------------------------------------------;
;
;!TODO ᯥªâà㬮¢áª¨¥ ã⨫¨âë
;----------------------------------------------------------------------;
; _mInfoBLOCK #3CFA-$,#FF
; LD A,0 ;!HARDCODE
; OUT (SYS_PORT.OFF),A
; POP AF
;----------------------------------------------------------------------;
;
;
;----------------------------------------------------------------------;
_mInfoBLOCK #3D00-$,#FF
;DOS_ON:
NOP
RET
;***************************************
;***************************************
; BLOCK #3D02-$,FF
; !TODO ¬®¦­® ®¯à¨å®¤®¢ âì âãâ 17 ¡ ©â®¢
;
;***************************************
;***************************************
_mInfoBLOCK #3D13-$,#FF
NOP
CALL ToBIOS_FromEXT
JP DOS_OFF
;***************************************
;***************************************
; BLOCK #3D17-$,FF
; !TODO ¬®¦­® ®¯à¨å®¤®¢ âì âãâ 233 ¡ ©â 
;
;***************************************
;***************************************
_mInfoBLOCK #3E00-$,#FF
;DOS_OFF:
PUSH AF
LD A,R
DI
PUSH AF
PUSH BC
;
LD BC,(#5BFF) ; !HARDCODE
LD A,#C9 ; Opcode RET
LD (#5BFF),A ; !HARDCODE
CALL #5BFF ; !HARDCODE
LD (#5BFF),BC ; !HARDCODE
;
POP BC
POP AF
JP PO,.no_EI
EI
.no_EI: POP AF
RET
;***************************************
;***************************************
; BLOCK #3E16-$,FF
; !TODO ¬®¦­® ®¯à¨å®¤®¢ âì âãâ 10 ¡ ©â®¢
;
;***************************************
;
;
;---------------------------------------
; _mInfoBLOCK #3FC6-$,#FF
; ¨«¨ ¬®¦­® ¤®¡ ¢¨âì ä㭪樨
; TRDOS_HD_CMD:
; ; LD A,C
; ; OR #40
; ; LD C,A
; POP AF
; SET 6,C
; RST_to_BIOS
; JR RET_TO_TRDOS
;---------------------------------------
;
;--------------[GOTO BIOS]--------------
_mInfoBLOCK #3FD0-$,#FF
;ToBIOS_FromEXT: call BIOS from EXTENSION
PUSH AF
LD A,ROM.BIOS ; set BIOS to slot0
OUT (SYS_PORT.ROM),A
POP AF
RET
;---------------------------------------
;--------[ From TR-DOS to HDD part2]--------
_mInfoBLOCK #3FD8-$,#FF
TRDOS_HD_CMD:
POP AF
SET 6,C
RST_to_BIOS
JR RET_TO_TRDOS
;---------------------------------------
;!FIXIT ®áâ âª¨ ®â â¥á⮢ ˆ¢ ­  á® §¢ãª®¢®© ª à⮩
;-------------[SND_TEST_RET]-------------
_mInfoBLOCK #3FE0-$,#FF
; SND_TEST_RET:
; LD A,ROM.BIOS
; OUT (SYS_PORT.RAM),A
; ;JP SOUND_TEST
; JP #0000
;---------------------------------------
;------------[Portal to EXT]------------
; â®çª  ¢å®¤ /¢ë室  ¤«ï ä㭪権 ¨§ BIOS
_mInfoBLOCK #3FE8-$,#FF
RET_TO_BIOS: ;RET_TO_EXP:
PUSH AF
LD A,ROM.BIOS
OUT (SYS_PORT.ROM),A ; from BIOS EXTENSION_FNs
POP AF
RET
; JP HDD_FN_5x
;---------------------------------------
;!FIXIT Œ®¦­® ¯®¯à ¢¨âì ­®¬¥à  ä㭪権 ¯à¨ ¢ë§®¢ å ¨§ TR-DOS ¨ ¯à룠âì áࠧ㠢 BIOS
;-------[ From TR-DOS to API 4x ]-------
_mInfoBLOCK #3FF0-$,#FF
RET_TO_TRDOS:
PUSH AF
DI
LD A,ROM.BIOS
OUT (SYS_PORT.RAM),A
JR TRDOS_HD_CMD ; âãâ ­¥ 墠⨫® ¬¥áâ  ¢ 1 ¡ ©â, ç⮡ áà §ã ᤥ« âì JP
;---------------------------------------
;-----[???????????????????????????]-----
_mInfoBLOCK #3FF8-$,#FF
; PUSH AF
; LD A,ROM.BIOS
; OUT (SYS_PORT.RAM),A
; JP #0000
;---------------------------------------
_mInfoBLOCK #4000-$,#FF
;=======================================
IFNDEF PREBUILD
DISPLAY ' -------------------[Main.asm]-------------------'
DISPLAY 'End code address: ',/A,MAIN_END_CODE_ADDRESS
DISPLAY 'Code size: ',/A,MAIN_END_CODE_ADDRESS + 1 - COMPILE_ADDR.MAIN
DISPLAY 'End buffers address: ',/A,memBUFFER.End - 1
DISPLAY 'Free memory: ',/A,#C000 - (memBUFFER.End-1) - STACK.Size
DISPLAY 'Unused bytes before INT_POINTER: ',/A,INT_POINTER-before_intPointer
ENDIF
; ENDMODULE ;ROM_PART
;
DISPLAY ' '
DISPLAY 'FIX printer init!!!!!!!!'

0
src/bios/rom/SETUP/AUTOIDE.asm → bios/rom/SETUP/AUTOIDE.asm
View File

0
src/bios/rom/SETUP/IM2_INT.asm → bios/rom/SETUP/IM2_INT.asm
View File

1578
src/bios/rom/SETUP/KEY.asm → bios/rom/SETUP/KEY.asm
View File

File diff suppressed because it is too large Load Diff

3914
src/bios/rom/SETUP/MAIN.asm → bios/rom/SETUP/MAIN.asm
View File

File diff suppressed because it is too large Load Diff

2182
src/bios/rom/SETUP/SETTINGS.asm → bios/rom/SETUP/SETTINGS.asm
View File

File diff suppressed because it is too large Load Diff

1310
src/bios/rom/SETUP/VIDEO_IO.asm → bios/rom/SETUP/VIDEO_IO.asm
View File

File diff suppressed because it is too large Load Diff

1836
src/bios/rom/SETUP/messages.z80 → bios/rom/SETUP/messages.z80
View File

File diff suppressed because it is too large Load Diff

326
src/bios/rom/SETUP/startup_sound.asm → bios/rom/SETUP/startup_sound.asm
View File

@ -1,164 +1,164 @@
; CODE BY €«¥ªá ­¤à -=TmK deMarche=-
; play frame
; use: af,hl,de,bc 251
STARTUP_SOUND: LD HL,.BYTE_POS
LD A,(HL)
LD C,SP_SND.AY
;
AND A
JR NZ,.no_init
;
LD DE,7*256 + %0011'1011
LD B,high SP_SND.AY.CTRL
OUT (C),D
LD B,high SP_SND.AY.DATA
OUT (C),E
;
.no_init: CP .volDataSize
JR C,.play
;-- mus off
.mute: XOR A
LD E,A
.offLp: CALL .set_regs
CP 14
JR NZ,.offLp
;
LD A,7
DEC E
CALL .set_regs
RET
;
.play: ;
;--- set tone
LD HL,(.WORD_TONE)
;A=0
LD A,4 ;REG C
.playToneLp: LD B,high SP_SND.AY.CTRL
OUT (C),A
LD B,high SP_SND.AY.DATA + 1
OUTI
INC A
CP 6
JR NZ,.playToneLp
;
LD (.WORD_TONE),HL
;--- set volume
.playVol: LD HL,(.WORD_VOL)
LD A,10
LD E,(HL)
INC HL
.playVolLp: CALL .set_regs
;
LD (.WORD_VOL),HL
LD HL,.BYTE_POS
INC (HL)
RET
; ;
.set_regs: LD B,high SP_SND.AY.CTRL
OUT (C),A
LD B,high SP_SND.AY.DATA
OUT (C),E
INC A
RET
;-----------------------------------------------------------------------
.BYTE_POS: DB 0
.WORD_VOL: DW .volData
.WORD_TONE: DW .toneData
;-----------------------------------------------------------------------
.toneData: DW #022, #044, #088, #110, #220, #440
DW #880, #440, #220, #110, #088, #044
DW #022, #044, #088, #110, #220, #440
DW #880, #440, #220, #110, #088, #044
DW #022
.volData: DB #02, #04, #06, #08, #0A, #0C
DB #0E, #0D, #0C, #0B, #0A, #09
DB #08, #07, #06, #05, #04, #03
DB #02, #06, #08, #0A, #0C, #0E
DB #0F
.volDataSize EQU $ - .volData
.codeEnd: DISPLAY "StartUp Sound size: ",/A,.codeEnd - STARTUP_SOUND
/*
; CODE BY €«¥ªá ­¤à -=TmK deMarche=-
; play frame
; use: af,hl,de,bc 251
STARTUP_SOUND: LD HL,.BYTE_POS
LD A,(HL)
LD C,SP_SND.AY
;
AND A
JR NZ,.no_init
;
LD DE,7*256 + %0011'1011
LD B,high SP_SND.AY.CTRL
OUT (C),D
LD B,high SP_SND.AY.DATA
OUT (C),E
;
.no_init: CP .volDataSize
JR C,.play
;-- mus off
.mute: XOR A
LD E,A
.offLp: CALL .set_regs
CP 14
JR NZ,.offLp
;
LD A,7
DEC E
CALL .set_regs
RET
;
.play: ;
;--- set tone
LD HL,(.WORD_TONE)
;A=0
LD A,4 ;REG C
.playToneLp: LD B,high SP_SND.AY.CTRL
OUT (C),A
LD B,high SP_SND.AY.DATA + 1
OUTI
INC A
CP 6
JR NZ,.playToneLp
;
LD (.WORD_TONE),HL
;--- set volume
.playVol: LD HL,(.WORD_VOL)
LD A,10
LD E,(HL)
INC HL
.playVolLp: CALL .set_regs
;
LD (.WORD_VOL),HL
LD HL,.BYTE_POS
INC (HL)
RET
; ;
.set_regs: LD B,high SP_SND.AY.CTRL
OUT (C),A
LD B,high SP_SND.AY.DATA
OUT (C),E
INC A
RET
;-----------------------------------------------------------------------
.BYTE_POS: DB 0
.WORD_VOL: DW .volData
.WORD_TONE: DW .toneData
;-----------------------------------------------------------------------
.toneData: DW #022, #044, #088, #110, #220, #440
DW #880, #440, #220, #110, #088, #044
DW #022, #044, #088, #110, #220, #440
DW #880, #440, #220, #110, #088, #044
DW #022
.volData: DB #02, #04, #06, #08, #0A, #0C
DB #0E, #0D, #0C, #0B, #0A, #09
DB #08, #07, #06, #05, #04, #03
DB #02, #06, #08, #0A, #0C, #0E
DB #0F
.volDataSize EQU $ - .volData
.codeEnd: DISPLAY "StartUp Sound size: ",/A,.codeEnd - STARTUP_SOUND
; CODE BY €«¥ªá ­¤à -=TmK deMarche=-
; play frame
; use: af,hl,de,bc 251
STARTUP_SOUND: LD HL,.BYTE_POS
LD A,(HL)
LD C,SP_SND.AY
;
AND A
JR NZ,.no_init
;
LD DE,7*256 + %0011'1011
LD B,high SP_SND.AY.CTRL
OUT (C),D
LD B,high SP_SND.AY.DATA
OUT (C),E
;
.no_init: CP .volDataSize
JR C,.play
;-- mus off
.mute: XOR A
LD E,A
.offLp: CALL .set_regs
CP 14
JR NZ,.offLp
;
LD A,7
DEC E
CALL .set_regs
RET
;
.play: ;
;--- set tone
LD HL,(.WORD_TONE)
;A=0
LD A,4 ;REG C
.playToneLp: LD B,high SP_SND.AY.CTRL
OUT (C),A
LD B,high SP_SND.AY.DATA + 1
OUTI
INC A
CP 6
JR NZ,.playToneLp
;
LD (.WORD_TONE),HL
;--- set volume
.playVol: LD HL,(.WORD_VOL)
LD A,10
LD E,(HL)
INC HL
.playVolLp: CALL .set_regs
;
LD (.WORD_VOL),HL
LD HL,.BYTE_POS
INC (HL)
RET
; ;
.set_regs: LD B,high SP_SND.AY.CTRL
OUT (C),A
LD B,high SP_SND.AY.DATA
OUT (C),E
INC A
RET
;-----------------------------------------------------------------------
.BYTE_POS: DB 0
.WORD_VOL: DW .volData
.WORD_TONE: DW .toneData
;-----------------------------------------------------------------------
.toneData: DW #022, #044, #088, #110, #220, #440
DW #880, #440, #220, #110, #088, #044
DW #022, #044, #088, #110, #220, #440
DW #880, #440, #220, #110, #088, #044
DW #022
.volData: DB #02, #04, #06, #08, #0A, #0C
DB #0E, #0D, #0C, #0B, #0A, #09
DB #08, #07, #06, #05, #04, #03
DB #02, #06, #08, #0A, #0C, #0E
DB #0F
.volDataSize EQU $ - .volData
.codeEnd: DISPLAY "StartUp Sound size: ",/A,.codeEnd - STARTUP_SOUND
/*
; CODE BY €«¥ªá ­¤à -=TmK deMarche=-
; play frame
; use: af,hl,de,bc 251
STARTUP_SOUND: LD HL,.BYTE_POS
LD A,(HL)
LD C,SP_SND.AY
;
AND A
JR NZ,.no_init
;
LD DE,7*256 + %0011'1011
LD B,high SP_SND.AY.CTRL
OUT (C),D
LD B,high SP_SND.AY.DATA
OUT (C),E
;
.no_init: CP .volDataSize
JR C,.play
;-- mus off
.mute: XOR A
LD E,A
.offLp: CALL .set_regs
CP 14
JR NZ,.offLp
;
LD A,7
DEC E
CALL .set_regs
RET
;
.play: ;
;--- set tone
LD HL,(.WORD_TONE)
;A=0
LD A,4 ;REG C
.playToneLp: LD B,high SP_SND.AY.CTRL
OUT (C),A
LD B,high SP_SND.AY.DATA + 1
OUTI
INC A
CP 6
JR NZ,.playToneLp
;
LD (.WORD_TONE),HL
;--- set volume
.playVol: LD HL,(.WORD_VOL)
LD A,10
LD E,(HL)
INC HL
.playVolLp: CALL .set_regs
;
LD (.WORD_VOL),HL
LD HL,.BYTE_POS
INC (HL)
RET
; ;
.set_regs: LD B,high SP_SND.AY.CTRL
OUT (C),A
LD B,high SP_SND.AY.DATA
OUT (C),E
INC A
RET
;-----------------------------------------------------------------------
.BYTE_POS: DB 0
.WORD_VOL: DW .volData
.WORD_TONE: DW .toneData
;-----------------------------------------------------------------------
.toneData: DW #022, #044, #088, #110, #220, #440
DW #880, #440, #220, #110, #088, #044
DW #022, #044, #088, #110, #220, #440
DW #880, #440, #220, #110, #088, #044
DW #022
.volData: DB #02, #04, #06, #08, #0A, #0C
DB #0E, #0D, #0C, #0B, #0A, #09
DB #08, #07, #06, #05, #04, #03
DB #02, #06, #08, #0A, #0C, #0E
DB #0F
.volDataSize EQU $ - .volData
.codeEnd: DISPLAY "StartUp Sound size: ",/A,.codeEnd - STARTUP_SOUND
*/

0
src/bios/rom/ZX/ZX_FUNC.ASM → bios/rom/ZX/ZX_FUNC.ASM
View File

1504
src/bios/rom/ZX/ZX_MENU.ASM → bios/rom/ZX/ZX_MENU.ASM
View File

File diff suppressed because it is too large Load Diff

0
src/bios/rom/_not_used/DEHRUST.asm → bios/rom/_not_used/DEHRUST.asm
View File

0
src/bios/rom/_not_used/EasterSprites.asm → bios/rom/_not_used/EasterSprites.asm
View File

314
src/bios/rom/_not_used/LZ4_DEC.asm → bios/rom/_not_used/LZ4_DEC.asm
View File

@ -1,157 +1,157 @@
;------------------------------------------------------------------------------
;hl=src de=dst
lz4decrunch:
ld bc,7
add hl,bc
ld c,(hl)
inc hl
ld b,(hl) ;„q„u„‚„v„} „t„r„p „q„p„z„„„p „y„x „x„p„s„€„|„€„r„{„p - „‚„p„x„}„u„‚
inc hl
inc hl
inc hl ;„~„p„‰„p„|„€ „ƒ„w„p„„„<E2809E>„‡ „t„p„~„~„<>„‡ „ƒ„€ „ƒ„}„u„‹„u„~„y„‘ #0B
ld a,l
add a,c
ld (.endL+1),a
ld a,h
adc a,b
ld (.endH+1),a ;„K„€„~„u„‰„~„<>„z „p„t„‚„u„ƒ „ƒ„w„p„„„<E2809E>„‡ „t„p„~„~„<>„‡
.loop:
ld a,(hl)
inc hl
ld (.litteral+1),a
and #F0
jr z,.copy ;„E„ƒ„|„y „t„|„y„~„p „‚„p„r„~„p 0, „ƒ„{„€„<E282AC>„y„‚„€„r„p„„„Ž „…„w„u „<>„u„‚„u„t„p„~„~„<>„u „t„p„~„~„<>„u
rrca
rrca
rrca
rrca
ld b,0
ld c,a
cp #0F
call z,.getlength ;„E„ƒ„|„y „t„|„y„~„p #0F, „„„€ „<>„€„|„…„‰„y„„„Ž „t„€„<E282AC>„€„|„~„y„„„u„|„Ž„~„…„<E280A6> „t„|„y„~„…
ldir ;„P„u„‚„u„t„p„‰„p „~„p„‰„y„~„p„u„„„ƒ„‘ „ƒ„€ „ƒ„|„u„t„…„<E280A6>„‹„u„z „y„~„†„€„‚„}„p„ˆ„y„y „€ „t„|„y„~„u
.copy:
ld a,l ;„t„€„ƒ„„„y„s„|„y „|„y „ƒ„w„p„„„<E2809E>„u „t„p„~„~„<>„u „{„€„~„u„‰„~„€„s„€ „p„t„‚„u„ƒ„p
.endL:
sub #FF
ld a,h
.endH:
sbc a,#FF
ret nc ;„^„†„†„u„{„„„y„r„~„p„‘ „<>„‚„€„r„u„‚„{„p zf=1
ld c,(hl)
inc hl
ld b,(hl) ;bc=2byte „X„„„u„~„y„u „x„~„p„‰„u„~„y„‘ „ƒ„}„u„‹„u„~„y„‘
inc hl
.litteral:
ld a,0 ;litteral „<>„u„‚„u„<75>„y„ƒ„p„„„Ž „x„t„u„ƒ„Ž
and #0F
add a,#04 ;cf=0
push hl
ld h,d
ld l,e
sbc hl,bc ;hl=de-bc „I„ƒ„<C692>„€„|„Ž„x„…„z„„„u „t„p„~„~„<>„u, „{„€„„„€„‚„<E2809A>„u „…„w„u „q„<71>„|„y „‚„p„ƒ„Š„y„‚„u„~„<>, „r „{„p„‰„u„ƒ„„„r„u „y„ƒ„„„€„‰„~„y„{„p „<>„u„‚„u„t„p„‰„y
ld b,0
ld c,a
cp #0F+#04
ex (sp),hl
call z,.getlength
ex (sp),hl
ldir ;„K„€„<E282AC>„y„‚„€„r„p„„„Ž „<>„u„‚„u„~„€„ƒ „…„w„u „‚„p„x„r„u„‚„~„…„„„<E2809E>„‡ „t„p„~„~„<>„‡
pop hl
jp .loop
.getlength: ;„P„€„|„…„‰„y„„„Ž „t„|„y„~„… „q„p„z„„„p „<>„u„‚„u„r„€„t„p („q„€„|„Ž„Š„u) bc=„„„u„{„…„‹„p„‘ „ƒ„…„}„}„p „<>„u„‚„u„r„€„t„p
ld a,(hl)
inc hl
cp #FF ;#FF „…„t„r„p„y„r„p„u„„„ƒ„‘ „{„p„{ „x„~„p„{, „x„p „{„€„„„€„‚„<E2809A>„} „ƒ„|„u„t„…„u„„ „y„~„†„€„‚„}„p„ˆ„y„‘ „€ „t„|„y„~„u
jr nz,.addlen
inc b
dec bc ;bc += 255
jr .getlength
.addlen:
add a,c
ld c,a
adc a,b
sub c
ld b,a ;bc=„t„|„y„~„p „<>„u„‚„u„t„p„r„p„u„}„€„s„€ „q„p„z„„„p
ret
;------------------------------------------------------------------------------
;in: hl=„~„p„‰„p„|„Ž„~„<>„z „p„t„‚„u„ƒ bc=„t„|„y„~„p
;out: bcde=„‚„u„x„…„|„Ž„„„p„„
crc32:
push hl
push bc
ld de,#FFFF ; 0xFFFFFFFF ? „~„p„‰„p„|„Ž„~„€„u „x„~„p„‰„u„~„y„u CRC32, „y„ƒ„<C692>„€„|„Ž„x„…„u„}„€„s„€ „r ZIP
ld h,d
ld l,e
ld c,#20 ;„ƒ„€„{„‚„p„‹„u„~„y„u
exx
pop hl
dec hl
inc h
inc l
ld b,l
ld c,h
pop hl
.loop1:
ld a,(hl)
inc hl
exx
xor e
ld b,8
.loop2:
srl h
rr l
rr d
rra
jp nc,.skip
ld e,a
ld a,h
xor #ED
ld h,a
ld a,l
xor #B8
ld l,a
ld a,d
xor #83
ld d,a
ld a,e
; xor #20
xor c
.skip:
djnz .loop2
ld e,a
exx
djnz .loop1
dec c
jp nz,.loop1
exx
ld a,h ;CRC32, „y„ƒ„<C692>„€„|„Ž„x„…„u„}„<>„z „r ZIP, „<>„‚„y„~„y„}„p„u„„ xor „ƒ 0xFFFFFFFF „r „{„€„~„ˆ„u
cpl
ld b,a
ld a,l
cpl
ld c,a
ld a,d
cpl
ld d,a
ld a,e
cpl
ld e,a
ret
;------------------------------------------------------------------------------
;hl=src de=dst
lz4decrunch:
ld bc,7
add hl,bc
ld c,(hl)
inc hl
ld b,(hl) ;„q„u„‚„v„} „t„r„p „q„p„z„„„p „y„x „x„p„s„€„|„€„r„{„p - „‚„p„x„}„u„‚
inc hl
inc hl
inc hl ;„~„p„‰„p„|„€ „ƒ„w„p„„„<E2809E>„‡ „t„p„~„~„<>„‡ „ƒ„€ „ƒ„}„u„‹„u„~„y„‘ #0B
ld a,l
add a,c
ld (.endL+1),a
ld a,h
adc a,b
ld (.endH+1),a ;„K„€„~„u„‰„~„<>„z „p„t„‚„u„ƒ „ƒ„w„p„„„<E2809E>„‡ „t„p„~„~„<>„‡
.loop:
ld a,(hl)
inc hl
ld (.litteral+1),a
and #F0
jr z,.copy ;„E„ƒ„|„y „t„|„y„~„p „‚„p„r„~„p 0, „ƒ„{„€„<E282AC>„y„‚„€„r„p„„„Ž „…„w„u „<>„u„‚„u„t„p„~„~„<>„u „t„p„~„~„<>„u
rrca
rrca
rrca
rrca
ld b,0
ld c,a
cp #0F
call z,.getlength ;„E„ƒ„|„y „t„|„y„~„p #0F, „„„€ „<>„€„|„…„‰„y„„„Ž „t„€„<E282AC>„€„|„~„y„„„u„|„Ž„~„…„<E280A6> „t„|„y„~„…
ldir ;„P„u„‚„u„t„p„‰„p „~„p„‰„y„~„p„u„„„ƒ„‘ „ƒ„€ „ƒ„|„u„t„…„<E280A6>„‹„u„z „y„~„†„€„‚„}„p„ˆ„y„y „€ „t„|„y„~„u
.copy:
ld a,l ;„t„€„ƒ„„„y„s„|„y „|„y „ƒ„w„p„„„<E2809E>„u „t„p„~„~„<>„u „{„€„~„u„‰„~„€„s„€ „p„t„‚„u„ƒ„p
.endL:
sub #FF
ld a,h
.endH:
sbc a,#FF
ret nc ;„^„†„†„u„{„„„y„r„~„p„‘ „<>„‚„€„r„u„‚„{„p zf=1
ld c,(hl)
inc hl
ld b,(hl) ;bc=2byte „X„„„u„~„y„u „x„~„p„‰„u„~„y„‘ „ƒ„}„u„‹„u„~„y„‘
inc hl
.litteral:
ld a,0 ;litteral „<>„u„‚„u„<75>„y„ƒ„p„„„Ž „x„t„u„ƒ„Ž
and #0F
add a,#04 ;cf=0
push hl
ld h,d
ld l,e
sbc hl,bc ;hl=de-bc „I„ƒ„<C692>„€„|„Ž„x„…„z„„„u „t„p„~„~„<>„u, „{„€„„„€„‚„<E2809A>„u „…„w„u „q„<71>„|„y „‚„p„ƒ„Š„y„‚„u„~„<>, „r „{„p„‰„u„ƒ„„„r„u „y„ƒ„„„€„‰„~„y„{„p „<>„u„‚„u„t„p„‰„y
ld b,0
ld c,a
cp #0F+#04
ex (sp),hl
call z,.getlength
ex (sp),hl
ldir ;„K„€„<E282AC>„y„‚„€„r„p„„„Ž „<>„u„‚„u„~„€„ƒ „…„w„u „‚„p„x„r„u„‚„~„…„„„<E2809E>„‡ „t„p„~„~„<>„‡
pop hl
jp .loop
.getlength: ;„P„€„|„…„‰„y„„„Ž „t„|„y„~„… „q„p„z„„„p „<>„u„‚„u„r„€„t„p („q„€„|„Ž„Š„u) bc=„„„u„{„…„‹„p„‘ „ƒ„…„}„}„p „<>„u„‚„u„r„€„t„p
ld a,(hl)
inc hl
cp #FF ;#FF „…„t„r„p„y„r„p„u„„„ƒ„‘ „{„p„{ „x„~„p„{, „x„p „{„€„„„€„‚„<E2809A>„} „ƒ„|„u„t„…„u„„ „y„~„†„€„‚„}„p„ˆ„y„‘ „€ „t„|„y„~„u
jr nz,.addlen
inc b
dec bc ;bc += 255
jr .getlength
.addlen:
add a,c
ld c,a
adc a,b
sub c
ld b,a ;bc=„t„|„y„~„p „<>„u„‚„u„t„p„r„p„u„}„€„s„€ „q„p„z„„„p
ret
;------------------------------------------------------------------------------
;in: hl=„~„p„‰„p„|„Ž„~„<>„z „p„t„‚„u„ƒ bc=„t„|„y„~„p
;out: bcde=„‚„u„x„…„|„Ž„„„p„„
crc32:
push hl
push bc
ld de,#FFFF ; 0xFFFFFFFF ? „~„p„‰„p„|„Ž„~„€„u „x„~„p„‰„u„~„y„u CRC32, „y„ƒ„<C692>„€„|„Ž„x„…„u„}„€„s„€ „r ZIP
ld h,d
ld l,e
ld c,#20 ;„ƒ„€„{„‚„p„‹„u„~„y„u
exx
pop hl
dec hl
inc h
inc l
ld b,l
ld c,h
pop hl
.loop1:
ld a,(hl)
inc hl
exx
xor e
ld b,8
.loop2:
srl h
rr l
rr d
rra
jp nc,.skip
ld e,a
ld a,h
xor #ED
ld h,a
ld a,l
xor #B8
ld l,a
ld a,d
xor #83
ld d,a
ld a,e
; xor #20
xor c
.skip:
djnz .loop2
ld e,a
exx
djnz .loop1
dec c
jp nz,.loop1
exx
ld a,h ;CRC32, „y„ƒ„<C692>„€„|„Ž„x„…„u„}„<>„z „r ZIP, „<>„‚„y„~„y„}„p„u„„ xor „ƒ 0xFFFFFFFF „r „{„€„~„ˆ„u
cpl
ld b,a
ld a,l
cpl
ld c,a
ld a,d
cpl
ld d,a
ld a,e
cpl
ld e,a
ret

176
src/bios/rom/_not_used/Logo_Depacker.asm → bios/rom/_not_used/Logo_Depacker.asm
View File

@ -1,89 +1,89 @@
CALL #E1D2
DI
LD (RelocatedCode.SPsave),SP
LD HL,.START
LD DE,#D800
LD BC,.END-.START
PUSH DE
LDIR
LD HL,#E1D1
LD DE,#FFFF
LD BC,#0850
RET
RelocatedCode:
.START:
LDDR
LD HL,#F7B0
LD DE,#D900
LD B,#00
LD A,(HL)
BIT 7,A
JR NZ,#D94A
AND #0F
LD B,A
RLD
ADD A,#03
LD C,A
INC HL
LD A,E
SUB (HL)
INC HL
LD SP,HL
LD H,(HL)
LD L,A
LD A,D
SBC A,B
LD B,H
LD H,A
LD A,B
LD B,#00
LDIR
LD H,B
LD L,C
ADD HL,SP
JR #D929
AND #7F
JR Z,#D967
INC HL
BIT 6,A
JR NZ,#D958
LD C,A
LDIR
JR #D928
AND #3F
ADD A,#03
LD B,A
LD A,(HL)
INC HL
LD C,(HL)
LD (DE),A
INC DE
DJNZ #D960
LD A,C
JR #D929
LD SP,#D85B
LD B,#03
POP HL
DEC SP
POP AF
LD (HL),A
DJNZ #D96C
.SPsave+1: LD SP,#0000
DI
RET
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
.END EQU $
; Š à⨭ª  ­  áâ à⮢®¬ íªà ­¥ á«¥¢  ᢥàåã
CALL #E1D2
DI
LD (RelocatedCode.SPsave),SP
LD HL,.START
LD DE,#D800
LD BC,.END-.START
PUSH DE
LDIR
LD HL,#E1D1
LD DE,#FFFF
LD BC,#0850
RET
RelocatedCode:
.START:
LDDR
LD HL,#F7B0
LD DE,#D900
LD B,#00
LD A,(HL)
BIT 7,A
JR NZ,#D94A
AND #0F
LD B,A
RLD
ADD A,#03
LD C,A
INC HL
LD A,E
SUB (HL)
INC HL
LD SP,HL
LD H,(HL)
LD L,A
LD A,D
SBC A,B
LD B,H
LD H,A
LD A,B
LD B,#00
LDIR
LD H,B
LD L,C
ADD HL,SP
JR #D929
AND #7F
JR Z,#D967
INC HL
BIT 6,A
JR NZ,#D958
LD C,A
LDIR
JR #D928
AND #3F
ADD A,#03
LD B,A
LD A,(HL)
INC HL
LD C,(HL)
LD (DE),A
INC DE
DJNZ #D960
LD A,C
JR #D929
LD SP,#D85B
LD B,#03
POP HL
DEC SP
POP AF
LD (HL),A
DJNZ #D96C
.SPsave+1: LD SP,#0000
DI
RET
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
.END EQU $
; Š à⨭ª  ­  áâ à⮢®¬ íªà ­¥ á«¥¢  ᢥàåã
INCBIN 'SP_LOGO.BIN'

0
src/bios/rom/_not_used/ayfxplay.asm → bios/rom/_not_used/ayfxplay.asm
View File

0
src/bios/rom/_not_used/netherworld_8.afx → bios/rom/_not_used/netherworld_8.afx
View File

344
src/bios/shared/CompMacro.asm → bios/shared/CompMacro.asm
View File

@ -1,172 +1,172 @@
;
MACRO ShowInfo text, in_disp
/*
DISPLAY ' '
DISPLAY '[*] ', text
IF in_disp
DISPLAY 'ROM:'
DISPLAY ' ORG: ',/H, $$$
DISPLAY ' PAGE: ',/H, $$$$
DISPLAY 'MEM:'
DISPLAY ' DISP: ',/H, $
DISPLAY ' PAGE: ',/H, $$
ELSE
DISPLAY 'ROM:'
DISPLAY ' ORG: ',/H, $
DISPLAY ' PAGE: ',/H, $$
ENDIF
DISPLAY '[X]'
DISPLAY ' '
*/
ENDM
;
;
; ‚室: è¨à¨­  á¯à ©â , ¢ëá®â , ª®®à¤¨­ â  X, ª®®à¤¨­ â  Y,  ¤à¥á á¯à ©â  ¢ ¯ ¬ïâ¨
MACRO EasterTable width, height, Xcoord, Ycoord, addr
WORD addr ;  ¤à¥á á¯à ©â  ¢ ¯ ¬ïâ¨
WORD width ; ˜¨à¨­ 
BYTE height+Ycoord ; ‚ëá®â  + Y coord
WORD Xcoord+#4040 ; X coord ; !HARDCODE ¨á¯à ¢¨âì ­  ¬¥âªã #4040 -  ¤à¥á «®£®
BYTE Ycoord ; Y coord
ENDM
;
;
MACRO _mRECOVERYrdChooseTYPE vers
IF vers = 1
; ¥á«¨ RECOVERY ­¥ ¯®¤à §ã¬¥¢ ¥â 90% ¡¥§®¯ á­®áâì ¯®«ì§®¢ â¥«ì᪨å à ¬¤¨áª®¢
; â® ¢ë¡¨à ¥¬ íâ®â ¢ à¨ ­â, ®­ èãáâ॥, ¯®¤ RECOVERY ¢á¥£¤  ¢ë¡¨à ¥âáï RAM Disk 15
;
ELSEIF vers = 2
; ˆé¥¬ ᢮¡®¤­ë© à ¬¤¨áª
LD B,SYS_PAGE.RAMD_KEYS.NUM
.getRDidLoop: LD A,B
DEC A
LD (RECOVERYstart.RDkey),A
PUSH BC
LD B,ROM_DISK.Pages.Size
CALL EMM.GetMemRMD
POP BC
JR NC,RECOVERYstart.IMGread ; ᢮¡®¤­ë© à ¬¤¨áª ­ ©¤¥­, ¢ë室¨¬ ¨§ 横« 
DEC A
JR Z,RECOVERYstart.FreeMem ; ®è¨¡ª  - ­¥¤®áâ â®ç­® ¯ ¬ïâ¨, ¢ë§ë¢ ¥¬ ®ç¨áâªã ¯ ¬ïâ¨
DJNZ .getRDidLoop
;
ELSE
ASSERT 0, Invalid 'RECOVERYrdChooseTYPE' variant - RECOVERYrdChooseTYPE
ENDIF
ENDM
;
MACRO _mRECOVERYmountTYPE vers
IF vers = 1 ; <20>®«¥¥ ¡ëáâàë©, ­® § å à¤ª®¦¥­­ë© ¢ à¨ ­â
LD HL,TEMP
CALL EMM.GetMemBlkPages ; ª¨¤ ¥¬ ¢ ¡ãä¥à ­®¬¥à  áâà ­¨æ RAM disk
IN A,(SLOT3)
LD (.slot3save),A
LD HL,ROM_DISK.Pages.Number
LD B,0
LD C,(HL)
INC C
LD DE,TEMP+ROM_DISK.Pages.Size
LDIR ; ª¨¤ ¥¬ ¤ «ìè¥ ¢ ¡ãä¥à ­®¬¥à  áâà ­¨æ ROM disk
LD IY,TEMP+ROM_DISK.Pages.Size ; ROM_DISK.Pages.Number
LD IX,TEMP
LD B,(IY+0)
LD A,R
PUSH AF
DI
.loopIMGtoRAM: PUSH BC
INC IY
LD A,(IY+0)
OUT (ROM.SLOT0),A
LD A,(IX+0)
OUT (SLOT3),A
INC IX
LD HL,0
LD DE,#C000
LD BC,#4000
LDIR
POP BC
DJNZ .loopIMGtoRAM
.slot3save+*: LD A,0
OUT (SLOT3),A
XOR A
OUT (ROM.SLOT0),A
OUT (SYS_PORT.ROM),A
POP AF
JP PO,.noInterrupts
EI
.noInterrupts:
;
ELSEIF vers = 2 ; ¬¥­¥¥ ¡ëáâàë©, ­® ¡®«¥¥ ¯à ¢¨«ì­ë© ¢ à¨ ­â ç¥à¥§ ä㭪樨 ¡¨®á 
LD (.ramdskID),A
LD DE,0 ; ­®¬¥à ᥪâ®à 
LD B,(ROM_DISK.Pages.Size * #4000)/512 ; áçñâ稪 - ª®«-¢  ᥪâ®à®¢ ¯® 512 ª¡
.loop:
;read rom disk
PUSH BC
LD A,1 ;à §¬¥à ᥪâ®à  256
EX AF,AF'
LD A,#46 ;ç⥭¨¥ ¨§ ROM-Disk
EX AF,AF'
LD HL,TEMP ; ¤à¥á ¡ãä¥à  ¤ ­­ëå
LD B,2 ;ç¨á«® ᥪâ®à®¢
CALL BLK_RD_WR
;write to ram disk
PUSH DE ;­®¬¥à ᥪâ®à 
DEC DE
DEC DE
.ramdskID+*: LD A,0 ;¨¤¥­â¨ä¨ª â®à ¡«®ª 
EX AF,AF'
LD A,#FF ;§ ¯¨áì ¢ RAM-Disk
EX AF,AF'
LD HL,TEMP ; ¤à¥á ¡ãä¥à  ¤ ­­ëå
LD B,2 ;ç¨á«® ᥪâ®à®¢
CALL BLK_RD_WR
POP DE ;­®¬¥à ᥪâ®à 
POP BC
DJNZ .loop
;
ELSE
ASSERT 0, Invalid 'RECOVERYmountTYPE' variant - RECOVERYmountTYPE
ENDIF
ENDM
;
;
MACRO RST_to_BIOS
IF (IsInBIOS = 0) && ($ < #4000)
CALL ToBIOS_FromEXT
ELSE
RST ToBIOS_18
ENDIF
ENDM
;
;
MACRO JP_to_BIOS
IF (IsInBIOS = 0) && ($ < #4000)
JP ToBIOS_FromEXT
ELSE
JP ToBIOS_18
ENDIF
ENDM
;
;
MACRO ShowInfo text, in_disp
/*
DISPLAY ' '
DISPLAY '[*] ', text
IF in_disp
DISPLAY 'ROM:'
DISPLAY ' ORG: ',/H, $$$
DISPLAY ' PAGE: ',/H, $$$$
DISPLAY 'MEM:'
DISPLAY ' DISP: ',/H, $
DISPLAY ' PAGE: ',/H, $$
ELSE
DISPLAY 'ROM:'
DISPLAY ' ORG: ',/H, $
DISPLAY ' PAGE: ',/H, $$
ENDIF
DISPLAY '[X]'
DISPLAY ' '
*/
ENDM
;
;
; ‚室: è¨à¨­  á¯à ©â , ¢ëá®â , ª®®à¤¨­ â  X, ª®®à¤¨­ â  Y,  ¤à¥á á¯à ©â  ¢ ¯ ¬ïâ¨
MACRO EasterTable width, height, Xcoord, Ycoord, addr
WORD addr ;  ¤à¥á á¯à ©â  ¢ ¯ ¬ïâ¨
WORD width ; ˜¨à¨­ 
BYTE height+Ycoord ; ‚ëá®â  + Y coord
WORD Xcoord+#4040 ; X coord ; !HARDCODE ¨á¯à ¢¨âì ­  ¬¥âªã #4040 -  ¤à¥á «®£®
BYTE Ycoord ; Y coord
ENDM
;
;
MACRO _mRECOVERYrdChooseTYPE vers
IF vers = 1
; ¥á«¨ RECOVERY ­¥ ¯®¤à §ã¬¥¢ ¥â 90% ¡¥§®¯ á­®áâì ¯®«ì§®¢ â¥«ì᪨å à ¬¤¨áª®¢
; â® ¢ë¡¨à ¥¬ íâ®â ¢ à¨ ­â, ®­ èãáâ॥, ¯®¤ RECOVERY ¢á¥£¤  ¢ë¡¨à ¥âáï RAM Disk 15
;
ELSEIF vers = 2
; ˆé¥¬ ᢮¡®¤­ë© à ¬¤¨áª
LD B,SYS_PAGE.RAMD_KEYS.NUM
.getRDidLoop: LD A,B
DEC A
LD (RECOVERYstart.RDkey),A
PUSH BC
LD B,ROM_DISK.Pages.Size
CALL EMM.GetMemRMD
POP BC
JR NC,RECOVERYstart.IMGread ; ᢮¡®¤­ë© à ¬¤¨áª ­ ©¤¥­, ¢ë室¨¬ ¨§ 横« 
DEC A
JR Z,RECOVERYstart.FreeMem ; ®è¨¡ª  - ­¥¤®áâ â®ç­® ¯ ¬ïâ¨, ¢ë§ë¢ ¥¬ ®ç¨áâªã ¯ ¬ïâ¨
DJNZ .getRDidLoop
;
ELSE
ASSERT 0, Invalid 'RECOVERYrdChooseTYPE' variant - RECOVERYrdChooseTYPE
ENDIF
ENDM
;
MACRO _mRECOVERYmountTYPE vers
IF vers = 1 ; <20>®«¥¥ ¡ëáâàë©, ­® § å à¤ª®¦¥­­ë© ¢ à¨ ­â
LD HL,TEMP
CALL EMM.GetMemBlkPages ; ª¨¤ ¥¬ ¢ ¡ãä¥à ­®¬¥à  áâà ­¨æ RAM disk
IN A,(SLOT3)
LD (.slot3save),A
LD HL,ROM_DISK.Pages.Number
LD B,0
LD C,(HL)
INC C
LD DE,TEMP+ROM_DISK.Pages.Size
LDIR ; ª¨¤ ¥¬ ¤ «ìè¥ ¢ ¡ãä¥à ­®¬¥à  áâà ­¨æ ROM disk
LD IY,TEMP+ROM_DISK.Pages.Size ; ROM_DISK.Pages.Number
LD IX,TEMP
LD B,(IY+0)
LD A,R
PUSH AF
DI
.loopIMGtoRAM: PUSH BC
INC IY
LD A,(IY+0)
OUT (ROM.SLOT0),A
LD A,(IX+0)
OUT (SLOT3),A
INC IX
LD HL,0
LD DE,#C000
LD BC,#4000
LDIR
POP BC
DJNZ .loopIMGtoRAM
.slot3save+*: LD A,0
OUT (SLOT3),A
XOR A
OUT (ROM.SLOT0),A
OUT (SYS_PORT.ROM),A
POP AF
JP PO,.noInterrupts
EI
.noInterrupts:
;
ELSEIF vers = 2 ; ¬¥­¥¥ ¡ëáâàë©, ­® ¡®«¥¥ ¯à ¢¨«ì­ë© ¢ à¨ ­â ç¥à¥§ ä㭪樨 ¡¨®á 
LD (.ramdskID),A
LD DE,0 ; ­®¬¥à ᥪâ®à 
LD B,(ROM_DISK.Pages.Size * #4000)/512 ; áçñâ稪 - ª®«-¢  ᥪâ®à®¢ ¯® 512 ª¡
.loop:
;read rom disk
PUSH BC
LD A,1 ;à §¬¥à ᥪâ®à  256
EX AF,AF'
LD A,#46 ;ç⥭¨¥ ¨§ ROM-Disk
EX AF,AF'
LD HL,TEMP ; ¤à¥á ¡ãä¥à  ¤ ­­ëå
LD B,2 ;ç¨á«® ᥪâ®à®¢
CALL BLK_RD_WR
;write to ram disk
PUSH DE ;­®¬¥à ᥪâ®à 
DEC DE
DEC DE
.ramdskID+*: LD A,0 ;¨¤¥­â¨ä¨ª â®à ¡«®ª 
EX AF,AF'
LD A,#FF ;§ ¯¨áì ¢ RAM-Disk
EX AF,AF'
LD HL,TEMP ; ¤à¥á ¡ãä¥à  ¤ ­­ëå
LD B,2 ;ç¨á«® ᥪâ®à®¢
CALL BLK_RD_WR
POP DE ;­®¬¥à ᥪâ®à 
POP BC
DJNZ .loop
;
ELSE
ASSERT 0, Invalid 'RECOVERYmountTYPE' variant - RECOVERYmountTYPE
ENDIF
ENDM
;
;
MACRO RST_to_BIOS
IF (IsInBIOS = 0) && ($ < #4000)
CALL ToBIOS_FromEXT
ELSE
RST ToBIOS_18
ENDIF
ENDM
;
;
MACRO JP_to_BIOS
IF (IsInBIOS = 0) && ($ < #4000)
JP ToBIOS_FromEXT
ELSE
JP ToBIOS_18
ENDIF
ENDM
;

2
src/bios/shared/DEFINES.INC → bios/shared/DEFINES.INC
View File

@ -10,7 +10,7 @@ RELEASEhotFIX EQU 2 ;
DEFINE SP2000_Loader_Flag #0107 ;
DEFINE IDE_Optimization 1 ; á«¥£ª  ®¯â¨¬¨§¨àã¥â ­¥ª®â®àë¥ ¯à®æ¥¤ãàë à ¡®âë á HDD
DEFINE NeedSafePort_Y 1 ; ¥á«¨ 0, â® ¢ ०¨¬¥ ¡¥§  ªá¥«ï ­¥ª®â®àë¥ ¯à®æ¥¤ãàë ¬®£ãâ § áà âì íªà ­
DEFINE PICTURE_FILE './src/bios/logo/psfathers.bmp' ;
DEFINE PICTURE_FILE './bios/logo/psfathers.bmp' ;
DEFINE StandartCGApallete 1 ; <20>®¤ª«îç âì ¯ «¨âàã ¨§ standart_colors.inc
DEFINE BitStream_SizeInPages 4 ;
DEFINE USE_E1_SCANCODE 0 ;

0
src/bios/shared/RECOVERY.IMG → bios/shared/RECOVERY.IMG
View File

118
src/bios/shared/VERSION.inc → bios/shared/VERSION.inc
View File

@ -1,60 +1,60 @@
;栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩<EFBFBD>;
; ============[For EXP part]=============
; ------[Version of BIOS "VER.MOD"]------
EXP_ID:
.VER EQU SET_EXPID_VER ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
.MOD EQU SET_EXPID_MOD ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
BIOS_ver_hex EQU EXP_ID.VER*256+EXP_ID.MOD
DEFINE BIOS_ver_string '0'+EXP_ID.VER, '.', '0'+EXP_ID.MOD/10, '0'+EXP_ID.MOD-(EXP_ID.MOD/10)*10
IF BETA_BUILD > 0
IF BETA_RC > 0
DEFINE BETA_str_ver "RC","0"+BETA_RC
ELSE
DEFINE BETA_str_ver "BETA ","0"+BETA_BUILD
ENDIF
ENDIF
;---------------------------------------
DEFINE BoardID_start #5283
DEFINE BoardID_end #47E8
DEFINE MotherBoardID #0000
DEFINE MotherBoardType #00 ; !TODO 0 - Legacy, 1 - DX, 2 - Max
;=======================================
;栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩<EFBFBD>;
; ============[For ROM part]=============
; -[Version of disk subsystem "VER.MOD"]-
ROM_ID:
.VER EQU 2 ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
.MOD EQU 56 ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
Disk_subsystem_ver_hex EQU ROM_ID.VER*256+ROM_ID.MOD
DEFINE Disk_subsystem_ver_txt '0'+ROM_ID.VER, '.', '0'+ROM_ID.MOD/10, '0'+ROM_ID.MOD-(ROM_ID.MOD/10)*10
;---------------------------------------
IF RELEASEhotFIX != 0
IF RELEASEhotFIX > 9
DEFINE ReleaseHotFix ' Hotfix ', '0' + RELEASEhotFIX/10, '0' + (RELEASEhotFIX - (RELEASEhotFIX/10)*10)
ELSE
DEFINE ReleaseHotFix ' Hotfix ', '0' + RELEASEhotFIX
ENDIF
ELSE
DEFINE ReleaseHotFix ""
ENDIF
;栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩<EFBFBD>;
; ============[For CNF part]=============
CNF_ID:
.VER EQU 3 ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
.MOD EQU 05 ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
bitstream_ver_hex EQU CNF_ID.VER*256+CNF_ID.MOD
DEFINE bitstream_ver_string '0'+CNF_ID.VER, '.', '0'+CNF_ID.MOD/10, '0'+CNF_ID.MOD-(CNF_ID.MOD/10)*10
;---------------------------------------
;栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩<EFBFBD>;
;=======================================
DEFINE SPTeam_year BUILD_YEAR
DEFINE SetupVer '1.60'
;---------------------------------------
;栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩<EFBFBD>;
; ============[For EXP part]=============
; ------[Version of BIOS "VER.MOD"]------
EXP_ID:
.VER EQU SET_EXPID_VER ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
.MOD EQU SET_EXPID_MOD ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
BIOS_ver_hex EQU EXP_ID.VER*256+EXP_ID.MOD
DEFINE BIOS_ver_string '0'+EXP_ID.VER, '.', '0'+EXP_ID.MOD/10, '0'+EXP_ID.MOD-(EXP_ID.MOD/10)*10
IF BETA_BUILD > 0
IF BETA_RC > 0
DEFINE BETA_str_ver "RC","0"+BETA_RC
ELSE
DEFINE BETA_str_ver "BETA ","0"+BETA_BUILD
ENDIF
ENDIF
;---------------------------------------
DEFINE BoardID_start #5283
DEFINE BoardID_end #47E8
DEFINE MotherBoardID #0000
DEFINE MotherBoardType #00 ; !TODO 0 - Legacy, 1 - DX, 2 - Max
;=======================================
;栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩<EFBFBD>;
; ============[For ROM part]=============
; -[Version of disk subsystem "VER.MOD"]-
ROM_ID:
.VER EQU 2 ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
.MOD EQU 56 ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
Disk_subsystem_ver_hex EQU ROM_ID.VER*256+ROM_ID.MOD
DEFINE Disk_subsystem_ver_txt '0'+ROM_ID.VER, '.', '0'+ROM_ID.MOD/10, '0'+ROM_ID.MOD-(ROM_ID.MOD/10)*10
;---------------------------------------
IF RELEASEhotFIX != 0
IF RELEASEhotFIX > 9
DEFINE ReleaseHotFix ' Hotfix ', '0' + RELEASEhotFIX/10, '0' + (RELEASEhotFIX - (RELEASEhotFIX/10)*10)
ELSE
DEFINE ReleaseHotFix ' Hotfix ', '0' + RELEASEhotFIX
ENDIF
ELSE
DEFINE ReleaseHotFix ""
ENDIF
;栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩<EFBFBD>;
; ============[For CNF part]=============
CNF_ID:
.VER EQU 3 ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
.MOD EQU 05 ; <EFBFBD><EFBFBD>ム ▲珀┬ <EFBFBD>㍼碎 矣<EFBFBD>!
bitstream_ver_hex EQU CNF_ID.VER*256+CNF_ID.MOD
DEFINE bitstream_ver_string '0'+CNF_ID.VER, '.', '0'+CNF_ID.MOD/10, '0'+CNF_ID.MOD-(CNF_ID.MOD/10)*10
;---------------------------------------
;栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩栩<EFBFBD>;
;=======================================
DEFINE SPTeam_year BUILD_YEAR
DEFINE SetupVer '1.60'
;---------------------------------------
;ﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛﾛ;

34
src/bios/shared/includes.inc → bios/shared/includes.inc
View File

@ -1,17 +1,17 @@
;
;---------[All shared includes]---------
INCLUDE 'src/bios/shared/DEFINES.INC' ; Shared defines
INCLUDE 'Shared_Includes/structures/FileSystem.inc'
INCLUDE 'Shared_Includes/structures/ATA_ATAPI.inc'
INCLUDE 'src/bios/Loader/Loader.asm' ; Bitstream loader as macros
INCLUDE 'src/bios/shared/CompMacro.asm' ; ¬ ªà®áë
INCLUDE 'Shared_Includes/constants/SP2000.inc' ; ª®­áâ ­âë
INCLUDE 'Shared_Includes/constants/zx_char_codes.inc' ; ª®­áâ ­âë
INCLUDE 'Shared_Includes/constants/zx_vars.inc' ;
INCLUDE 'Shared_Includes/macroses/macros.z80'
INCLUDE 'src/bios/ROM/MEM_MAP.inc' ; ª àâ  ¯ ¬ïâ¨
INCLUDE 'src/bios/shared/VERSION.inc' ; ‚¥àá¨ï EXP ¨ ROM
INCLUDE 'Shared_Includes/constants/BIOS_EQU.inc'
INCLUDE 'src/bios/ROM/BIOS.inc'
;---------------------------------------
;
;
;---------[All shared includes]---------
INCLUDE 'bios/shared/DEFINES.INC' ; Shared defines
INCLUDE 'Shared_Includes/structures/FileSystem.inc'
INCLUDE 'Shared_Includes/structures/ATA_ATAPI.inc'
INCLUDE 'bios/Loader/Loader.asm' ; Bitstream loader as macros
INCLUDE 'bios/shared/CompMacro.asm' ; ¬ ªà®áë
INCLUDE 'Shared_Includes/constants/SP2000.inc' ; ª®­áâ ­âë
INCLUDE 'Shared_Includes/constants/zx_char_codes.inc' ; ª®­áâ ­âë
INCLUDE 'Shared_Includes/constants/zx_vars.inc' ;
INCLUDE 'Shared_Includes/macroses/macros.z80'
INCLUDE 'bios/ROM/MEM_MAP.inc' ; ª àâ  ¯ ¬ïâ¨
INCLUDE 'bios/shared/VERSION.inc' ; ‚¥àá¨ï EXP ¨ ROM
INCLUDE 'Shared_Includes/constants/BIOS_EQU.inc'
INCLUDE 'bios/ROM/BIOS.inc'
;---------------------------------------
;

524
src/doc/CDLOADER.TXT → doc/CDLOADER.TXT
View File

@ -1,262 +1,262 @@
RETTR PUSH BC
LD DE,DIR
LD HL,0
LD IX,#0010
LD BC,#0105
LD A,(DRIVE)
RST #18
POP BC
JR C,CDAGAA
LD HL,DIR
LD A,(HL)
INC HL
CP #01
JR NZ,UNKCD
LD A,(HL)
INC HL
CP "C"
JR NZ,UNKCD
LD A,(HL)
INC HL
CP "D"
JR NZ,UNKCD
LD HL,DIR+#009E
LD DE,ROOTDIR
LDI
LDI
LDI
LDI
LD HL,DIR+#00A6
LD DE,ROOTLEN
LDI
LDI
LDI
LDI
POP AF
OUT (PAGE3),A
LD HL,0
LD (FATCASH),HL
XOR A
RET
LOADDIR XOR A
LD HL,0
LD IX,0
LD B,0
CALL MOVE_FP
LD A,DIRPAGE
CALL BANK
PUSH AF
LD B,3
LOADFFF PUSH BC
LD HL,#C000
LD DE,#C001
LD BC,#3FFF
LD (HL),L
LDIR
LD A,(DRIVE)
LD (IY+FDRV),A
; LD C,(IY+LEN1)
LD C,(IY+LEN2)
LD B,(IY+LEN3)
LD E,(IY+LEN4)
LD D,0
SRL D
RR E
RR B
RR C
SRL D
RR E
RR B
RR C
SRL D
RR E
RR B
RR C
LD E,(IY+CLU1)
LD D,(IY+CLU2)
LD L,(IY+CLU3)
LD H,(IY+CLU4)
LD HX,D
LD LX,E
LD B,C
LD A,B
OR A
JR Z,ERRLEND
CP #08
JR C,NORLEND
LD B,8
NORLEND LD A,(DRIVE)
LD C,5
LD DE,DIR
RST #18
POP BC
JR NC,LOADMMM
DEC B
JP NZ,LOADFFF
POP AF
OUT (PAGE3),A
SCF
LD A,20
RET
ERRLEND POP BC
POP AF
OUT (PAGE3),A
SCF
LD A,20
RET
LOADMMM POP AF
OUT (PAGE3),A
CALL CORRDIR
AND A
RET
CORRDIR LD A,DIRPAGE
CALL BANK
PUSH AF
LD HL,DIR
LD DE,DIR
CORRL1 PUSH DE
LD C,(HL)
LD B,0
LD DE,ENTRYBF
LDIR
POP DE
PUSH HL
LD HL,FCDFLEN
LD C,(HL)
LD B,0
ADD HL,BC
INC HL
LD (HL),0
SBC HL,BC
PUSH DE
CALL MASK
POP HL
LD BC,11
ADD HL,BC
LD A,(FCDFLAG)
AND 2
LD A,#00 ;ATTRIBUT FILE
JR Z,CORRL0
LD A,#10 ;ATTRIBUT DIRECTORY
CORRL0 LD (HL),A
INC HL
XOR A
LD B,8
FILLCDN LD (HL),A
INC HL
DJNZ FILLCDN
LD A,(FCDSEC+2)
LD (HL),A
INC HL
LD A,(FCDSEC+3)
LD (HL),A
INC HL
LD DE,#0000 ;TIME
LD (HL),E
INC HL
LD (HL),D
INC HL
LD DE,#0000 ;DATE
LD (HL),E
INC HL
LD (HL),D
INC HL
LD DE,(FCDSEC)
LD (HL),E
INC HL
LD (HL),D
INC HL
EX DE,HL
LD HL,FCDLEN
LDI
LDI
LDI
LDI
POP HL
BIT 7,H
JR Z,CORRL2
LD A,(HL)
OR A
JP NZ,CORRL1
LD L,0
INC H
JR Z,CORRL2
LD A,(HL)
OR A
JP NZ,CORRL1
CORRL2 XOR A
LD (DE),A
LD DE,(ROOTDIR+0)
LD L,(IY+CLU1)
LD H,(IY+CLU2)
AND A
SBC HL,DE
JR NZ,CORRL6
LD DE,(ROOTDIR+2)
LD L,(IY+CLU3)
LD H,(IY+CLU4)
AND A
SBC HL,DE
JR NZ,CORRL6
LD HL,DIR
LD A,(HL)
CP " "
JR NZ,CORRL4
LD (HL),#E5
LD BC,#0020
ADD HL,BC
LD A,(HL)
CP " "
JR NZ,CORRL4
LD (HL),#E5
JR CORRL4
CORRL6 LD HL,DIR
LD A,(HL)
CP " "
JR NZ,CORRL4
LD (HL),"."
LD BC,#0020
ADD HL,BC
LD A,(HL)
CP " "
JR NZ,CORRL4
LD (HL),"."
INC HL
LD (HL),"."
CORRL4 POP AF
OUT (PAGE3),A
AND A
RET
ENTRYBF
DEFB #00 ;Entry lenght
DEFB #00 ;XAR in LBN
FCDSEC DEFW #00,#00 ;Start sector (Intel)
DEFW #00,#00 ;Start sector (Motorola)
FCDLEN DEFW #00,#00 ;Lenght file (Intel)
DEFW #00,#00 ;Lenght file (Motorola)
FCDYEAR DEFB #00 ;Year
FCDMOUN DEFB #00 ;Mount
FCDDAY DEFB #00 ;Day
FCDHOUR DEFB #00 ;Hour
FCDMIN DEFB #00 ;Minute
FCDSECN DEFB #00 ;Second
DEFB #00 ;Reserve
FCDFLAG DEFB #00 ;Flag
DEFB #00 ;Interlive size
DEFB #00 ;Interlive skip factor
DEFW #0000 ;Volume Set Sequence (Intel)
DEFW #0000 ;Volume Set Sequence (Motorola)
FCDFLEN DEFB #00
DEFSA EQU $-ENTRYBF
FCDNAME DEFS #100-DEFSA
ROOTDIR DEFW 0,0
ROOTLEN DEFW 0,0
RETTR PUSH BC
LD DE,DIR
LD HL,0
LD IX,#0010
LD BC,#0105
LD A,(DRIVE)
RST #18
POP BC
JR C,CDAGAA
LD HL,DIR
LD A,(HL)
INC HL
CP #01
JR NZ,UNKCD
LD A,(HL)
INC HL
CP "C"
JR NZ,UNKCD
LD A,(HL)
INC HL
CP "D"
JR NZ,UNKCD
LD HL,DIR+#009E
LD DE,ROOTDIR
LDI
LDI
LDI
LDI
LD HL,DIR+#00A6
LD DE,ROOTLEN
LDI
LDI
LDI
LDI
POP AF
OUT (PAGE3),A
LD HL,0
LD (FATCASH),HL
XOR A
RET
LOADDIR XOR A
LD HL,0
LD IX,0
LD B,0
CALL MOVE_FP
LD A,DIRPAGE
CALL BANK
PUSH AF
LD B,3
LOADFFF PUSH BC
LD HL,#C000
LD DE,#C001
LD BC,#3FFF
LD (HL),L
LDIR
LD A,(DRIVE)
LD (IY+FDRV),A
; LD C,(IY+LEN1)
LD C,(IY+LEN2)
LD B,(IY+LEN3)
LD E,(IY+LEN4)
LD D,0
SRL D
RR E
RR B
RR C
SRL D
RR E
RR B
RR C
SRL D
RR E
RR B
RR C
LD E,(IY+CLU1)
LD D,(IY+CLU2)
LD L,(IY+CLU3)
LD H,(IY+CLU4)
LD HX,D
LD LX,E
LD B,C
LD A,B
OR A
JR Z,ERRLEND
CP #08
JR C,NORLEND
LD B,8
NORLEND LD A,(DRIVE)
LD C,5
LD DE,DIR
RST #18
POP BC
JR NC,LOADMMM
DEC B
JP NZ,LOADFFF
POP AF
OUT (PAGE3),A
SCF
LD A,20
RET
ERRLEND POP BC
POP AF
OUT (PAGE3),A
SCF
LD A,20
RET
LOADMMM POP AF
OUT (PAGE3),A
CALL CORRDIR
AND A
RET
CORRDIR LD A,DIRPAGE
CALL BANK
PUSH AF
LD HL,DIR
LD DE,DIR
CORRL1 PUSH DE
LD C,(HL)
LD B,0
LD DE,ENTRYBF
LDIR
POP DE
PUSH HL
LD HL,FCDFLEN
LD C,(HL)
LD B,0
ADD HL,BC
INC HL
LD (HL),0
SBC HL,BC
PUSH DE
CALL MASK
POP HL
LD BC,11
ADD HL,BC
LD A,(FCDFLAG)
AND 2
LD A,#00 ;ATTRIBUT FILE
JR Z,CORRL0
LD A,#10 ;ATTRIBUT DIRECTORY
CORRL0 LD (HL),A
INC HL
XOR A
LD B,8
FILLCDN LD (HL),A
INC HL
DJNZ FILLCDN
LD A,(FCDSEC+2)
LD (HL),A
INC HL
LD A,(FCDSEC+3)
LD (HL),A
INC HL
LD DE,#0000 ;TIME
LD (HL),E
INC HL
LD (HL),D
INC HL
LD DE,#0000 ;DATE
LD (HL),E
INC HL
LD (HL),D
INC HL
LD DE,(FCDSEC)
LD (HL),E
INC HL
LD (HL),D
INC HL
EX DE,HL
LD HL,FCDLEN
LDI
LDI
LDI
LDI
POP HL
BIT 7,H
JR Z,CORRL2
LD A,(HL)
OR A
JP NZ,CORRL1
LD L,0
INC H
JR Z,CORRL2
LD A,(HL)
OR A
JP NZ,CORRL1
CORRL2 XOR A
LD (DE),A
LD DE,(ROOTDIR+0)
LD L,(IY+CLU1)
LD H,(IY+CLU2)
AND A
SBC HL,DE
JR NZ,CORRL6
LD DE,(ROOTDIR+2)
LD L,(IY+CLU3)
LD H,(IY+CLU4)
AND A
SBC HL,DE
JR NZ,CORRL6
LD HL,DIR
LD A,(HL)
CP " "
JR NZ,CORRL4
LD (HL),#E5
LD BC,#0020
ADD HL,BC
LD A,(HL)
CP " "
JR NZ,CORRL4
LD (HL),#E5
JR CORRL4
CORRL6 LD HL,DIR
LD A,(HL)
CP " "
JR NZ,CORRL4
LD (HL),"."
LD BC,#0020
ADD HL,BC
LD A,(HL)
CP " "
JR NZ,CORRL4
LD (HL),"."
INC HL
LD (HL),"."
CORRL4 POP AF
OUT (PAGE3),A
AND A
RET
ENTRYBF
DEFB #00 ;Entry lenght
DEFB #00 ;XAR in LBN
FCDSEC DEFW #00,#00 ;Start sector (Intel)
DEFW #00,#00 ;Start sector (Motorola)
FCDLEN DEFW #00,#00 ;Lenght file (Intel)
DEFW #00,#00 ;Lenght file (Motorola)
FCDYEAR DEFB #00 ;Year
FCDMOUN DEFB #00 ;Mount
FCDDAY DEFB #00 ;Day
FCDHOUR DEFB #00 ;Hour
FCDMIN DEFB #00 ;Minute
FCDSECN DEFB #00 ;Second
DEFB #00 ;Reserve
FCDFLAG DEFB #00 ;Flag
DEFB #00 ;Interlive size
DEFB #00 ;Interlive skip factor
DEFW #0000 ;Volume Set Sequence (Intel)
DEFW #0000 ;Volume Set Sequence (Motorola)
FCDFLEN DEFB #00
DEFSA EQU $-ENTRYBF
FCDNAME DEFS #100-DEFSA
ROOTDIR DEFW 0,0
ROOTLEN DEFW 0,0

58
src/doc/SETUP.REV → doc/SETUP.REV
View File

@ -1,30 +1,30 @@
;---------------------------------------------------------------
;Rev Date Name Description
;---------------------------------------------------------------
;Изменения в build'e 2.53
;R06 16-02-2002 DNS Add CMOS install routine. Disabled TRDOS install routine.
;Изменения в build'e 2.52
;R05 28-01-2002 DNS Add new items to SETUP Utility for screen position.
;Изменения в build'e 2.51
;R04 14-09-2001 DNS Added procedure GET_BOARD_NUMBER and
Removed 2 IDE (if with_2ide)
;Изменения в build'e 2.50
;R03a 02-08-2001 DNS ADD BUILD-IN CD DRIVER (Not release)
;R03 30-07-2001 DNS Developed a new IDE DETECT routine and fixied any bugs
;R02 25-07-2001 DNS Add Secondary IDE
;Изменения в build'e 2.48
;R01 23-04-2001 DNS Removed procedure GET_ID and make new which
; will be take Model Name.
;R00 xx-xx-2000 DNS New BIOS for Sp2000 build 2.48
;---------------------------------------------------------------
;Revisions:
;R01 - Функция GET_ID на платах Sprinter97, получала даты создания и
; прошивки ПЗУ, на платах Sp2000 было введино понятие модели.
;R02 - Автодетект 4х устройств
;R03 - Добавлена работа всех функций со вторым IDE каналам, работает
; нестабильно, возможно железо, начата работа над чтением с CD,
; исправлена ошибка (при определении CDROMа не указывался признак
; MASTER/SLAVE в параметрах IDE(#FE:#C1C0-#C1CF).
;R04 - Добавлен вывод номера платы (функция #ED) при старте компьютера,
; работа со вторым IDE перенесена в условную компиляцию (if with_2ide)
;---------------------------------------------------------------
;Rev Date Name Description
;---------------------------------------------------------------
;Изменения в build'e 2.53
;R06 16-02-2002 DNS Add CMOS install routine. Disabled TRDOS install routine.
;Изменения в build'e 2.52
;R05 28-01-2002 DNS Add new items to SETUP Utility for screen position.
;Изменения в build'e 2.51
;R04 14-09-2001 DNS Added procedure GET_BOARD_NUMBER and
Removed 2 IDE (if with_2ide)
;Изменения в build'e 2.50
;R03a 02-08-2001 DNS ADD BUILD-IN CD DRIVER (Not release)
;R03 30-07-2001 DNS Developed a new IDE DETECT routine and fixied any bugs
;R02 25-07-2001 DNS Add Secondary IDE
;Изменения в build'e 2.48
;R01 23-04-2001 DNS Removed procedure GET_ID and make new which
; will be take Model Name.
;R00 xx-xx-2000 DNS New BIOS for Sp2000 build 2.48
;---------------------------------------------------------------
;Revisions:
;R01 - Функция GET_ID на платах Sprinter97, получала даты создания и
; прошивки ПЗУ, на платах Sp2000 было введино понятие модели.
;R02 - Автодетект 4х устройств
;R03 - Добавлена работа всех функций со вторым IDE каналам, работает
; нестабильно, возможно железо, начата работа над чтением с CD,
; исправлена ошибка (при определении CDROMа не указывался признак
; MASTER/SLAVE в параметрах IDE(#FE:#C1C0-#C1CF).
;R04 - Добавлен вывод номера платы (функция #ED) при старте компьютера,
; работа со вторым IDE перенесена в условную компиляцию (if with_2ide)
;----------------------------------------------------------------

242
src/doc/_BIOS.REV → doc/_BIOS.REV
View File

@ -1,121 +1,121 @@
;---------------------------------------------------------------
;Rev Date Name Description
;---------------------------------------------------------------
;‚¥àá¨ï 3.04
;R0046 16.06.2003 IM ˆá¯à ¢«¥­¨ï ¤«ï ᮢ¬¥á⨬®á⨠video á Sp2000
;R0046 13.06.2003 IM ˆá¯à ¢«¥­¨ï £«îª®¢ ¢ ०¨¬¥ ZX
;R0046 02.06.2003 IM ˆá¯à ¢«¥­¨ï ¤«ï ¢¨¤¥®-Ž‡“ AS7C1024A-JC12
;‚¥àá¨ï 3.03
;R0045 05.02.2003 IM ˆá¯à ¢«¥­¨ï ¤«ï ¢¨¤¥®-Ž‡“ AS7C1024-JC12
;‚¥àá¨ï 3.02
;R0044 01.10.2002 IM „®¡ ¢«¥­¨ï ¢ ¯à®è¨¢ª¥
;‚¥àá¨ï 3.00.253 (10.04.2002) UPDATE01
;R0043 01.04.2002 IM <20>¥à¥ª®¬¯¨«¥­  ¯à®è¨¢ª  ¤«ï <20>‹Œ ¤«ï SIMM
;R0042 10.03.2002 DNS Setup 253
;‚¥àá¨ï 2.17.252 (03.03.2002) UPDATE-beta-version
;R0041 03-03-2002 IM <20>®¤¯à ¢«¥­ë æ¢¥â  ¢ ä㭪樨 CGA ¯ «¨âàë
;R0040 02-03-2002 IM ˆá¯à ¢«¥­ £«îª ä㭪樨 ¢ë¤ ç¨ ¯®à⮢
;R0039 02-03-2002 IM „®¡ ¢«¥­ë ç⥭¨¥ ¯ «¨âàë ¨ ⥪á⮢ ï CGA ¯ «¨âà 
;‚¥àá¨ï 2.16.252 (27.02.2002) WORK
;R0038 27-02-2002 IM ‘®®¡é¥­¨¥ ®¡ ®âáãâá⢨¨ Spectrum-ROM
;R0037 26-02-2002 IM †¥á⪮ § ªà¥¯«¥­ë áâà ­¨æë 41h..47h §  Spectrum.ROM
;R0036 25-02-2002 IM „®¡ ¢«¥­ ¢­ãâ७­¨© ¯®àâ ¤«ï ¢®§¢à â  ¢ ZX/FN
;R0035 22-02-2002 IM ‚ BIOS ¤®¡ ¢«¥­  äã­ªæ¨ï ãáâ ­®¢ª¨ Original-INT
;R0034 21-02-2002 IM „®¡ ¢«¥­  äã­ªæ¨ï BIOS, ¯¥à¥ª«îç îé ï 720/1.44
;‚¥àá¨ï 2.15.252 (18.02.2002) WORK
;R0033 18-02-2002 IM ˆá¯à ¢«¥­¨¥ ¤«ï ISA
;R0032 12-02-2002 IM „®¡ ¢«¥­  äã­ªæ¨ï ç⥭¨ï ROM-Disk- 
;R0031 12-02-2002 IM ˆá¯à ¢«¥­  äã­ªæ¨ï BIOS ç⥭¨ï/§ ¯¨á¨ RAM-Disk-®¢
;R0030 12-02-2002 IM ˆá¯à ¢«¥­  á奬  COVOX-Blaster- 
;R0029 08-02-2002 IM <20>®«­®áâìî ¨§¬¥­¥­a á奬  ¤®áâ㯠 ª <20>‡“/Fast-RAM/ISA
;‚¥àá¨ï 2.14.252 (01.02.2002) WORK
;R0028 01-02-2002 DNS „®¡ ¢«¥­ ᤢ¨£ íªà ­  ¢ setup
;‚¥àá¨ï 2.13.251 (10.11.2002) WORK
;R0027 23-01-2002 IM COVOX-Blaster 16bit, 110khz, stereo
;R0026 17-01-2002 IM ˆá¯à ¢«¥­  ®è¨¡ª  ¢ ä㭪樨 FN_PIC1
;‚¥àá¨ï 2.12.251 (10.11.2002) RELEASE
;R0025 10-01-2002 IM ‘¬¥é¥­ íªà ­ ­  1 §­ ª®¬¥áâ® ¢«¥¢®
;‚¥àá¨ï 2.11.251 (08.01.2002) WORK
;R0024 10-01-2002 IM ˆá¯à ¢«¥­¨¥ ¯à¥¤ë¤ã饣® ¨á¯à ¢«¥­¨ï
;R0023 08-01-2002 IM ˆá¯à ¢«¥­¨ï ¢ BIOS-¥ (¯¥à¥§ £à㧪  <20>‹Œ)
;R0022 08-01-2002 IM à §¡®àª¨ á FDD
;‚¥àá¨ï 2.10.251 (25.12.2001) RELEASE
;R0020 23-12-2001 IM ª®à४æ¨ï ᨭåà®­¨§ æ¨¨ ¢ <20>‹Œ
;R0019 20-12-2001 IM ã¡à ­® R0018 - NMI
;‚¥àá¨ï 2.09.251 (18.12.2001) WORK (for Denis only!)
;R0018 18-12-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ (¤®¡ ¢«¥­ NMI)
;R0017 17-12-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ (¨á¯à ¢«¥­¨ï ¤«ï SIMM)
;R0016 15-12-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ (¨á¯à ¢«¥­¨ï SINC)
;R0015 14-12-2001 IM ¤®¡ ¢«¥­ ¯ã­ªâ "L" ¢ Post
;R0014 19-11-2001 IM ®¡¥§£«î祭 ï ¯à®è¨¢ª  ¤«ï Winbond
;R0013 18-11-2001 IM ¢®§¢à é¥­ áâ àë© copyright ¢ Basic128
;‚¥àá¨ï 2.08.251 (17.11.2001) WORK
;R0012 17-11-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 17-­®ï-2001
;‚¥àá¨ï 2.07.251 (11.11.2001) WORK
;R0011 11-11-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 11-­®ï-2001
;‚¥àá¨ï 2.06.251 (07.11.2001) WORK
;R0010 07-11-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 07-­®ï-2001
;‚¥àá¨ï 2.06.251 (05.11.2001) WORK
;R0009 05-11-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 05-­®ï-2001
;‚¥àá¨ï 2.05.251 (xx.xx.2001) WORK
;R0008 xx-xx-2001 IM -- ®¯¨á ­¨¥ ¨§¬¥­¥­¨© --
;‚¥àá¨ï 2.04.251 (27.10.2001) RELEASE
;R0007 27-10-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 27-®ªâ-2001
;R0006 12-10-2001 IM ¯¥à¥ª®¯ ­  ¯à®è¨¢ª  <20>‹Œ ®â 12-®ªâ-2001
;‚¥àá¨ï 2.04.250 (04.10.2001) WORK
;R0005 04-10-2001 DNS ¢áâ ¢«¥­ ­®¢ë© ROM.BIN ®â 4-®ªâ-2001
;‚¥àá¨ï 2.04.249 (22.09.2001) WORK
;R0004 22-09-2001 DNS ¢áâ ¢«¥­ ­®¢ë© ROM.BIN ®â ...å¬.. ­¥ ¯®¬­î..
;R0003 22-09-2001 IM ¨á¯à ¢«¥­¨¥ ­ §¢ ­¨© ¢ ¬¥­î "Hardware"
;R0002 22-09-2001 IM ¢áâ ¢«¥­ ­®¬¥à <20>‡“ ¨ äã­ªæ¨ï ¡¨®á  ¤«ï ­¥£® 0EDh
;R0001 22-09-2001 IM ¤®¡ ¢«¥­  äã­ªæ¨ï GOTO Spectrum 0FBh
;‚¥àá¨ï 2.03.248 (08.06.2001) WORK
;---------------------------------------------------------------
;Revisions:
;R0044 - ‚¢¥¤¥­ë ¡¨âë ¯®àâ  ã¯à ¢«¥­¨ï ã¯à ¢«¥­¨ï:
; ¡¨â ¢ëª«î祭¨ï RESET
; ¡¨â ¢ª«î祭¨ï NMI ¯® <alt>+<F12>
; ¡¨â ®âª«î祭¨ï ZX-screen (ᮢ¬¥é¥­ á ¡¨â®¬ Sprinter/Spectrum)
;R0036 - ‘¯¥æ-äã­ªæ¨ï ¤«ï sprinter.exe “áâ ­®¢ª  ¢­ãâ७­¥£® ¯®àâ  EE
; ¢ ­¥ 0 ¯à¨¢®¤¨â ª ¯¥à¥å®¤ã ¢ ãáâ ­®¢«¥­­ãî áâà ­¨æã ¨ ¯à®¤®«¦¥­¨î
; à ¡®âë ¯à®£à ¬¬ë, ãáâ ­®¢¨¢è¥© ¯¥à¥å¢ â
;R0033 - ‚ ०¨¬¥ Sprinter ¢¢¥¤¥­ áâ àë© ¤®áâ㯠ª ISA ç¥à¥§ ¯®àâ 1FFD ¨
; PAGE3=D0..DF
;R0031 - ‚ ä㭪樨 ç⥭¨ï/§ ¯¨á¨ RAM-Disk-®¢ ¡ë« ¦¥á⮪¨© £«îª...
; ®­  ¢®®¡é¥ ­¥ à ¡®â « 
;R0030 - “¡à ­ë á¡®¨ ¯à¨ ¯à®¨£à뢠­¨¨ ¢ ०¨¬¥ á ¯à¥à뢠­¨ï¬¨, ª®£¤ 
; ¢ CBL § ¯¨á뢠îâáï «¨è­¨¥ ¨«¨ ­¥¤®§ ¯¨á뢠îâáï ¡ ©âë...
; ¯® ¯à¥à뢠­¨î CBL ¢­ãâ७­¨© áç¥â稪 ãáâ ­ ¢«¨¢ ¥âáï ­  00h ¨«¨ 80h
;R0029 - ‚¢¥¤¥­® à §¤¥«¥­¨¥ Sprinter ¨ Spectrum ०¨¬®¢.
; ‚ ०¨¬¥ Spectrum ¨ Sprinter-ZX ¢á¥ <20>‡“ ­ å®¤ïâáï ¢ Ž‡“
; ˆ§¬¥­¥­ ¤®áâ㯠ª <20>‡“ ¨ Fast-RAM ¤®áâ㯠áâ « ¡ëáâ॥. ˆ§¬¥­¨« áì
;  ¤à¥á æ¨ï áâà ­¨æ Fast-RAM ¨ ROM. €¤à¥áãîâáï ç¥à¥§ ¯®àâ 5F ¢ ०¨¬¥
; SYSTEM-on. ‚¢¥¤¥­ ¯®«­ë© § ¯à¥â ¤®áâ㯠 ª RAM ¢® ¢à¥¬ï à ¡®âë á <20>‡“
; Ž‡“ ¢ íâ®â ¬®¬¥­â ᢮¡®¤­® ¤«ï ¤à㣨å ä㭪権 (¯®âॡã¥âáï ¤«ï DMA)
; ‘ª®à®áâì à ¡®âë ¢ Fast-RAM ¢ë¢¥¤¥­  ­  ¬ ªá¨¬ã¬ (¡¥§ ¢ ©â®¢).
; ‚모­ãâë <20>‡“ Spectrum-  ¨§ BIOS.
;R0026 - ˆá¯à ¢«¥­  ®è¨¡ª  ¢ ä㭪樨 FN_PIC1. <20>뫨 ­¥¢¥à­ ï ®âà ¡®âª 
; ­®¬¥à  ®ª­  ¨ ­¥á®åà ­¥­¨¥ ¯®àâ  RGADR.
;R0024 - ¯®á«¥¤á⢨ï R0023, ¢ ’ãà¡® ¢®§­¨ª«® § ­¨¦¥­¨¥ ᪮à®á⨠¨§-§ 
; ¯¥à¥ª«î祭¨ï ã¯à ¢«ïî饣® ॣ¨áâà  ­  boundary ¢¬¥áâ® wait
;R0023 - ®¡­ à㦥­  ¨ ãáâà ­¥­  ®è¨¡ª  ¢ ¯à®£à ¬¬¥ ¯¥à¥§ £à㧪¨ <20>‹Œ ¨§¢­¥
; (ç¥à¥§ Š<>˜) ¡ë« ­¥¢¥à­® ¨­¨æ¨ «¨§¨à®¢ ­ boundary-ॣ¨áâà Z84C15
;R0022 - ã¡à ­ £«îª à ¡®âë á FDD, ¢®§­¨ªè¨© ¯®á«¥ ª®à४â¨à®¢ª¨ à ¡®âë á
; SIMM- ¬¨ (¯®¤ ¢ ¥¬ë¥ ­  FDD ¤ ­­ë¥ ®¡à뢠«¨áì à ­ìè¥ ¢à¥¬¥­¨)
;R0020 - ã¡à ­ £«îª ­¥á®¢¬¥á⨬®á⨠¯à®è¨¢ª¨ "áâ à®©" ¨ "­®¢®©" ¯ à⨩ ¯« â
;R0018 - "¤¨ª¨©" NMI - ¯® alt+F12 ¯à®áâ® ¯®¤ ¥âáï NMI, ­¨ç¥£® ¡®«¥¥ ­¥
; ®âá«¥¦¨¢ ¥âáï
;R0017 - ¢¢¥¤¥­ë § ¤¥à¦ª¨ (input delay in MAX+) ¤«ï ¢¢®¤  ¤ ­­ëå á SIMM- ,
; ¨§¬¥­¥­  ¢à¥¬ï­ª  ᨣ­ «  /WE ­  SIMM
;R0016 - „®¡ ¢«¥­  á奬  ¯®¤ ¢«¥­¨ï ¤¦¨ââ¥à  áâà®ç­®© ᨭåà®­¨§ æ¨¨
; ¤ ¢¨âáï ¤¦¨ââ¥à +/- 0.25¬ªá
;R0015 - <20>¥à¥¤ § £à㧪®© <20>‹Œ § ¦¨£ ¥âáï "L" ­  ¨­¤¨ª â®à¥ Post-Tester-a
;R0014 - ã¡à ­ £«îª ¯®¤ ¬¥­î help ­  Winbond- å (¯à®¢¥à¨âì!)
;R0012 - § ªà¥¯«¥­® ¨á¯à ¢«¥­¨¥ ¤«ï ISA, ¢¨¤¥®-Ž‡“ ã«ãç襭¨¥ ¤«ï UMC
;R0011 - § ªà¥¯«¥­® ¨á¯à ¢«¥­¨¥ ¤«ï ISA, ¯® ¢¨¤¥®-Ž‡“ ®âª â ¤® 2.04 ¢¥àᨨ
;R0010 - ¤®¯®«­¨â¥«ì­®¥ 㤠«¥­¨¥ £«îª®¢ á ¢¨¤¥®-Ž‡“
;R0009 - ç áâ¨ç­®¥ 㤠«¥­¨¥ £«îª®¢ á ¢¨¤¥®-Ž‡“
;R0007 - ¨á¯à ¢«¥­¨¥ ¬­®¦¥á⢥­­ëå £«îª®¢ ¯à¨ à ¡®â¥ á SIMM ¬¥â®¤®¬
; ¯¥à¥ª®¬¯¨«ï樨 á ­®¢ë¬¨ ®¯æ¨ï¬¨ MAX-Plus.
;R0006 - ¤®¯®«­¨â¥«ì­®¥ ¨á¯à ¢«¥­¨¥ £«îª®¢ ¯à¨ à ¡®â¥ á SIMM.
;
;---------------------------------------------------------------
;Rev Date Name Description
;---------------------------------------------------------------
;‚¥àá¨ï 3.04
;R0046 16.06.2003 IM ˆá¯à ¢«¥­¨ï ¤«ï ᮢ¬¥á⨬®á⨠video á Sp2000
;R0046 13.06.2003 IM ˆá¯à ¢«¥­¨ï £«îª®¢ ¢ ०¨¬¥ ZX
;R0046 02.06.2003 IM ˆá¯à ¢«¥­¨ï ¤«ï ¢¨¤¥®-Ž‡“ AS7C1024A-JC12
;‚¥àá¨ï 3.03
;R0045 05.02.2003 IM ˆá¯à ¢«¥­¨ï ¤«ï ¢¨¤¥®-Ž‡“ AS7C1024-JC12
;‚¥àá¨ï 3.02
;R0044 01.10.2002 IM „®¡ ¢«¥­¨ï ¢ ¯à®è¨¢ª¥
;‚¥àá¨ï 3.00.253 (10.04.2002) UPDATE01
;R0043 01.04.2002 IM <20>¥à¥ª®¬¯¨«¥­  ¯à®è¨¢ª  ¤«ï <20>‹Œ ¤«ï SIMM
;R0042 10.03.2002 DNS Setup 253
;‚¥àá¨ï 2.17.252 (03.03.2002) UPDATE-beta-version
;R0041 03-03-2002 IM <20>®¤¯à ¢«¥­ë æ¢¥â  ¢ ä㭪樨 CGA ¯ «¨âàë
;R0040 02-03-2002 IM ˆá¯à ¢«¥­ £«îª ä㭪樨 ¢ë¤ ç¨ ¯®à⮢
;R0039 02-03-2002 IM „®¡ ¢«¥­ë ç⥭¨¥ ¯ «¨âàë ¨ ⥪á⮢ ï CGA ¯ «¨âà 
;‚¥àá¨ï 2.16.252 (27.02.2002) WORK
;R0038 27-02-2002 IM ‘®®¡é¥­¨¥ ®¡ ®âáãâá⢨¨ Spectrum-ROM
;R0037 26-02-2002 IM †¥á⪮ § ªà¥¯«¥­ë áâà ­¨æë 41h..47h §  Spectrum.ROM
;R0036 25-02-2002 IM „®¡ ¢«¥­ ¢­ãâ७­¨© ¯®àâ ¤«ï ¢®§¢à â  ¢ ZX/FN
;R0035 22-02-2002 IM ‚ BIOS ¤®¡ ¢«¥­  äã­ªæ¨ï ãáâ ­®¢ª¨ Original-INT
;R0034 21-02-2002 IM „®¡ ¢«¥­  äã­ªæ¨ï BIOS, ¯¥à¥ª«îç îé ï 720/1.44
;‚¥àá¨ï 2.15.252 (18.02.2002) WORK
;R0033 18-02-2002 IM ˆá¯à ¢«¥­¨¥ ¤«ï ISA
;R0032 12-02-2002 IM „®¡ ¢«¥­  äã­ªæ¨ï ç⥭¨ï ROM-Disk- 
;R0031 12-02-2002 IM ˆá¯à ¢«¥­  äã­ªæ¨ï BIOS ç⥭¨ï/§ ¯¨á¨ RAM-Disk-®¢
;R0030 12-02-2002 IM ˆá¯à ¢«¥­  á奬  COVOX-Blaster- 
;R0029 08-02-2002 IM <20>®«­®áâìî ¨§¬¥­¥­a á奬  ¤®áâ㯠 ª <20>‡“/Fast-RAM/ISA
;‚¥àá¨ï 2.14.252 (01.02.2002) WORK
;R0028 01-02-2002 DNS „®¡ ¢«¥­ ᤢ¨£ íªà ­  ¢ setup
;‚¥àá¨ï 2.13.251 (10.11.2002) WORK
;R0027 23-01-2002 IM COVOX-Blaster 16bit, 110khz, stereo
;R0026 17-01-2002 IM ˆá¯à ¢«¥­  ®è¨¡ª  ¢ ä㭪樨 FN_PIC1
;‚¥àá¨ï 2.12.251 (10.11.2002) RELEASE
;R0025 10-01-2002 IM ‘¬¥é¥­ íªà ­ ­  1 §­ ª®¬¥áâ® ¢«¥¢®
;‚¥àá¨ï 2.11.251 (08.01.2002) WORK
;R0024 10-01-2002 IM ˆá¯à ¢«¥­¨¥ ¯à¥¤ë¤ã饣® ¨á¯à ¢«¥­¨ï
;R0023 08-01-2002 IM ˆá¯à ¢«¥­¨ï ¢ BIOS-¥ (¯¥à¥§ £à㧪  <20>‹Œ)
;R0022 08-01-2002 IM à §¡®àª¨ á FDD
;‚¥àá¨ï 2.10.251 (25.12.2001) RELEASE
;R0020 23-12-2001 IM ª®à४æ¨ï ᨭåà®­¨§ æ¨¨ ¢ <20>‹Œ
;R0019 20-12-2001 IM ã¡à ­® R0018 - NMI
;‚¥àá¨ï 2.09.251 (18.12.2001) WORK (for Denis only!)
;R0018 18-12-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ (¤®¡ ¢«¥­ NMI)
;R0017 17-12-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ (¨á¯à ¢«¥­¨ï ¤«ï SIMM)
;R0016 15-12-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ (¨á¯à ¢«¥­¨ï SINC)
;R0015 14-12-2001 IM ¤®¡ ¢«¥­ ¯ã­ªâ "L" ¢ Post
;R0014 19-11-2001 IM ®¡¥§£«î祭 ï ¯à®è¨¢ª  ¤«ï Winbond
;R0013 18-11-2001 IM ¢®§¢à é¥­ áâ àë© copyright ¢ Basic128
;‚¥àá¨ï 2.08.251 (17.11.2001) WORK
;R0012 17-11-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 17-­®ï-2001
;‚¥àá¨ï 2.07.251 (11.11.2001) WORK
;R0011 11-11-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 11-­®ï-2001
;‚¥àá¨ï 2.06.251 (07.11.2001) WORK
;R0010 07-11-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 07-­®ï-2001
;‚¥àá¨ï 2.06.251 (05.11.2001) WORK
;R0009 05-11-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 05-­®ï-2001
;‚¥àá¨ï 2.05.251 (xx.xx.2001) WORK
;R0008 xx-xx-2001 IM -- ®¯¨á ­¨¥ ¨§¬¥­¥­¨© --
;‚¥àá¨ï 2.04.251 (27.10.2001) RELEASE
;R0007 27-10-2001 IM ¨§¬¥­¥­  ¯à®è¨¢ª  <20>‹Œ ®â 27-®ªâ-2001
;R0006 12-10-2001 IM ¯¥à¥ª®¯ ­  ¯à®è¨¢ª  <20>‹Œ ®â 12-®ªâ-2001
;‚¥àá¨ï 2.04.250 (04.10.2001) WORK
;R0005 04-10-2001 DNS ¢áâ ¢«¥­ ­®¢ë© ROM.BIN ®â 4-®ªâ-2001
;‚¥àá¨ï 2.04.249 (22.09.2001) WORK
;R0004 22-09-2001 DNS ¢áâ ¢«¥­ ­®¢ë© ROM.BIN ®â ...å¬.. ­¥ ¯®¬­î..
;R0003 22-09-2001 IM ¨á¯à ¢«¥­¨¥ ­ §¢ ­¨© ¢ ¬¥­î "Hardware"
;R0002 22-09-2001 IM ¢áâ ¢«¥­ ­®¬¥à <20>‡“ ¨ äã­ªæ¨ï ¡¨®á  ¤«ï ­¥£® 0EDh
;R0001 22-09-2001 IM ¤®¡ ¢«¥­  äã­ªæ¨ï GOTO Spectrum 0FBh
;‚¥àá¨ï 2.03.248 (08.06.2001) WORK
;---------------------------------------------------------------
;Revisions:
;R0044 - ‚¢¥¤¥­ë ¡¨âë ¯®àâ  ã¯à ¢«¥­¨ï ã¯à ¢«¥­¨ï:
; ¡¨â ¢ëª«î祭¨ï RESET
; ¡¨â ¢ª«î祭¨ï NMI ¯® <alt>+<F12>
; ¡¨â ®âª«î祭¨ï ZX-screen (ᮢ¬¥é¥­ á ¡¨â®¬ Sprinter/Spectrum)
;R0036 - ‘¯¥æ-äã­ªæ¨ï ¤«ï sprinter.exe “áâ ­®¢ª  ¢­ãâ७­¥£® ¯®àâ  EE
; ¢ ­¥ 0 ¯à¨¢®¤¨â ª ¯¥à¥å®¤ã ¢ ãáâ ­®¢«¥­­ãî áâà ­¨æã ¨ ¯à®¤®«¦¥­¨î
; à ¡®âë ¯à®£à ¬¬ë, ãáâ ­®¢¨¢è¥© ¯¥à¥å¢ â
;R0033 - ‚ ०¨¬¥ Sprinter ¢¢¥¤¥­ áâ àë© ¤®áâ㯠ª ISA ç¥à¥§ ¯®àâ 1FFD ¨
; PAGE3=D0..DF
;R0031 - ‚ ä㭪樨 ç⥭¨ï/§ ¯¨á¨ RAM-Disk-®¢ ¡ë« ¦¥á⮪¨© £«îª...
; ®­  ¢®®¡é¥ ­¥ à ¡®â « 
;R0030 - “¡à ­ë á¡®¨ ¯à¨ ¯à®¨£à뢠­¨¨ ¢ ०¨¬¥ á ¯à¥à뢠­¨ï¬¨, ª®£¤ 
; ¢ CBL § ¯¨á뢠îâáï «¨è­¨¥ ¨«¨ ­¥¤®§ ¯¨á뢠îâáï ¡ ©âë...
; ¯® ¯à¥à뢠­¨î CBL ¢­ãâ७­¨© áç¥â稪 ãáâ ­ ¢«¨¢ ¥âáï ­  00h ¨«¨ 80h
;R0029 - ‚¢¥¤¥­® à §¤¥«¥­¨¥ Sprinter ¨ Spectrum ०¨¬®¢.
; ‚ ०¨¬¥ Spectrum ¨ Sprinter-ZX ¢á¥ <20>‡“ ­ å®¤ïâáï ¢ Ž‡“
; ˆ§¬¥­¥­ ¤®áâ㯠ª <20>‡“ ¨ Fast-RAM ¤®áâ㯠áâ « ¡ëáâ॥. ˆ§¬¥­¨« áì
;  ¤à¥á æ¨ï áâà ­¨æ Fast-RAM ¨ ROM. €¤à¥áãîâáï ç¥à¥§ ¯®àâ 5F ¢ ०¨¬¥
; SYSTEM-on. ‚¢¥¤¥­ ¯®«­ë© § ¯à¥â ¤®áâ㯠 ª RAM ¢® ¢à¥¬ï à ¡®âë á <20>‡“
; Ž‡“ ¢ íâ®â ¬®¬¥­â ᢮¡®¤­® ¤«ï ¤à㣨å ä㭪権 (¯®âॡã¥âáï ¤«ï DMA)
; ‘ª®à®áâì à ¡®âë ¢ Fast-RAM ¢ë¢¥¤¥­  ­  ¬ ªá¨¬ã¬ (¡¥§ ¢ ©â®¢).
; ‚모­ãâë <20>‡“ Spectrum-  ¨§ BIOS.
;R0026 - ˆá¯à ¢«¥­  ®è¨¡ª  ¢ ä㭪樨 FN_PIC1. <20>뫨 ­¥¢¥à­ ï ®âà ¡®âª 
; ­®¬¥à  ®ª­  ¨ ­¥á®åà ­¥­¨¥ ¯®àâ  RGADR.
;R0024 - ¯®á«¥¤á⢨ï R0023, ¢ ’ãà¡® ¢®§­¨ª«® § ­¨¦¥­¨¥ ᪮à®á⨠¨§-§ 
; ¯¥à¥ª«î祭¨ï ã¯à ¢«ïî饣® ॣ¨áâà  ­  boundary ¢¬¥áâ® wait
;R0023 - ®¡­ à㦥­  ¨ ãáâà ­¥­  ®è¨¡ª  ¢ ¯à®£à ¬¬¥ ¯¥à¥§ £à㧪¨ <20>‹Œ ¨§¢­¥
; (ç¥à¥§ Š<>˜) ¡ë« ­¥¢¥à­® ¨­¨æ¨ «¨§¨à®¢ ­ boundary-ॣ¨áâà Z84C15
;R0022 - ã¡à ­ £«îª à ¡®âë á FDD, ¢®§­¨ªè¨© ¯®á«¥ ª®à४â¨à®¢ª¨ à ¡®âë á
; SIMM- ¬¨ (¯®¤ ¢ ¥¬ë¥ ­  FDD ¤ ­­ë¥ ®¡à뢠«¨áì à ­ìè¥ ¢à¥¬¥­¨)
;R0020 - ã¡à ­ £«îª ­¥á®¢¬¥á⨬®á⨠¯à®è¨¢ª¨ "áâ à®©" ¨ "­®¢®©" ¯ à⨩ ¯« â
;R0018 - "¤¨ª¨©" NMI - ¯® alt+F12 ¯à®áâ® ¯®¤ ¥âáï NMI, ­¨ç¥£® ¡®«¥¥ ­¥
; ®âá«¥¦¨¢ ¥âáï
;R0017 - ¢¢¥¤¥­ë § ¤¥à¦ª¨ (input delay in MAX+) ¤«ï ¢¢®¤  ¤ ­­ëå á SIMM- ,
; ¨§¬¥­¥­  ¢à¥¬ï­ª  ᨣ­ «  /WE ­  SIMM
;R0016 - „®¡ ¢«¥­  á奬  ¯®¤ ¢«¥­¨ï ¤¦¨ââ¥à  áâà®ç­®© ᨭåà®­¨§ æ¨¨
; ¤ ¢¨âáï ¤¦¨ââ¥à +/- 0.25¬ªá
;R0015 - <20>¥à¥¤ § £à㧪®© <20>‹Œ § ¦¨£ ¥âáï "L" ­  ¨­¤¨ª â®à¥ Post-Tester-a
;R0014 - ã¡à ­ £«îª ¯®¤ ¬¥­î help ­  Winbond- å (¯à®¢¥à¨âì!)
;R0012 - § ªà¥¯«¥­® ¨á¯à ¢«¥­¨¥ ¤«ï ISA, ¢¨¤¥®-Ž‡“ ã«ãç襭¨¥ ¤«ï UMC
;R0011 - § ªà¥¯«¥­® ¨á¯à ¢«¥­¨¥ ¤«ï ISA, ¯® ¢¨¤¥®-Ž‡“ ®âª â ¤® 2.04 ¢¥àᨨ
;R0010 - ¤®¯®«­¨â¥«ì­®¥ 㤠«¥­¨¥ £«îª®¢ á ¢¨¤¥®-Ž‡“
;R0009 - ç áâ¨ç­®¥ 㤠«¥­¨¥ £«îª®¢ á ¢¨¤¥®-Ž‡“
;R0007 - ¨á¯à ¢«¥­¨¥ ¬­®¦¥á⢥­­ëå £«îª®¢ ¯à¨ à ¡®â¥ á SIMM ¬¥â®¤®¬
; ¯¥à¥ª®¬¯¨«ï樨 á ­®¢ë¬¨ ®¯æ¨ï¬¨ MAX-Plus.
;R0006 - ¤®¯®«­¨â¥«ì­®¥ ¨á¯à ¢«¥­¨¥ £«îª®¢ ¯à¨ à ¡®â¥ á SIMM.
;

306
src/doc/changes.txt → doc/changes.txt
View File

@ -1,154 +1,154 @@
TODO:
-? ¯ã­ªâ ¢ á¥â ¯¥ "á®åà ­ïâì áâà ­¨æë ᯥªâà㬠 ¯à¨ ¯¥à¥§ £à㧪¥"
- ç¨áâ¨âì ¡ãä¥à ª« ¢ë ­¥ ¢âã¯ãî,   ª ª¨¬¨-­¨¡ã¤ì ª®¬ ­¤ ¬¨ ¤«ï íâ¨å ¢á直å SIO/PIO, ¥á«¨ ¥áâì
Done:
+ ­¥¬­®£® ¤®à ¡®â ­  á¨á⥬  ¯¥à¥å¢ â  à¥á¥â  ¤«ï ãáâà ­¥­¨ï ­¥ª®â®àëå £«îª®¢ ¨ ­  ¡ã¤ã饥
+ ¢ á¥â ¯ à ¡®â ¥â á®åà ­¥­¨¥ ­ áâ஥ª HDD "Setup" ¯®á«¥ ¯¥à¢®£® 㤠筮£®  ¢â®¤¥â¥ªâ 
+ ‘¤¥« ­ ã­¨¢¥àá «ì­ë© § £àã§ç¨ª ¡¨âáâਬ  ¤«ï 1k30 ¨ 1k50
+ €ªâ¨¢¨à®¢ ­ ¢â®à®© ª ­ « IDE
+ <09>㬥à æ¨ï ãáâனá⢠IDE ¯¥à¥¤¥« ­  á ¯®á«¥¤®¢ â¥«ì­®© ­  䨧¨ç¥áªãî
+ ‚ë¡®à § £à㧮筮£® IDE ¨§¬¥­ñ­ á ¯®á«¥¤®¢ â¥«ì­®£® ­  䨧¨ç¥áª¨©
+ „®¡ ¢«¥­  ¢®§¬®¦­®áâì ãáâ ­®¢ª¨ IDE á® ¢â®à®£® ª ­ «  ¢ ª ç¥á⢥ ®á­®¢­®£® ¨  «ìâ¥à­ â¨¢­®£® § £à㧮筮£® ¤¨áª 
+ “¡à ­® § «¨¯ ­¨¥ ª« ¢¨è ¯à¨ à¥á¥â¥ ¯® Ctrl+Alt+Del
+ <09>ਠ­¥ª®à४â­ëå §­ ç¥­¨ïå ¤ âë ¨ ¢à¥¬¥­¨ ¢ CMOS ¤ ­­ë¥ § ¬¥­ïîâáï ­  ¤¥ä®«â­ë¥ §­ ç¥­¨ï, ¢ë¢®¤¨âáï á®®¡é¥­¨¥ ®¡ ®è¨¡ª¥
+ ‚ Setup ¤®¡ ¢«¥­ ¢ë¡®à ०¨¬  à §¢ñà⪨ (--------/Scorpion/Pentagon/Spectrum)
+ ‚ Setup ¤®¡ ¢«¥­ ¢ë¡®à ¢¥à⨪ «ì­®© ᨭåà®­¨§ æ¨¨ (--------/312 50ƒæ/320 49ƒæ)
+ „®¡ ¢«¥­  § £à㧪  á¨á⥬ë á RAM Disk
+ ˆá¯à ¢«¥­ ¡ £ á® á⥪®¬ ¢ BLK_TO_RAMD ¨ ¥éñ ­¥áª®«ìª® ¡ £®¢ ¢ ¯à®æ¥¤ãà å ç⥭¨ï á <20>€Œ-„ˆ‘Š€
+ „®¡ ¢«¥­  § £à㧪  RECOVERY á ROM-Disk ¢ <20>‡“
+ <09>ਠ宫®¤­®¬ áâ à⥠ãáâ ­ ¢«¨¢ ¥âáï ¨­â ¯¥­â £®­  (  ­¥ ᪮௨®­ ), ¥á«¨ ¢ CMOS ­¥ § ¤ ­® ¨­®¥
+ ”ã­ªæ¨ï <20>ˆŽ‘ FN_SINC (#F2) ¯à¨ 㤠筮¬ § ¢¥à襭¨¨ ­¥ á¡à á뢠«  ä« £ CF ­  ¢ë室¥ - ¨á¯à ¢«¥­®
+ <09>®¢ ï äã­ªæ¨ï GET_RAMD_NUM
+ „®¡ ¢«¥­ë¥ ¤®¯®«­¨â¥«ì­ë¥ ®¯æ¨¨ ¢ äã­ªæ¨î <20>ˆŽ‘ FN_SINC (#F2), bit7 ॣ¨áâà  A ⥯¥àì ®â¢¥ç ¥â §  ¯¥à¥ª«î祭¨¥ áâ à®£®/­®¢®£®
¢ à¨ ­â  à ¡®âë ä㭪樨 (¤«ï á®åà ­¥­¨ï ᮢ¬¥á⨬®á⨠ᮠáâ à묨 ¯à®£à ¬¬ ¬¨)
+ <09>®¢®¥ «®£® ¯à¨ áâ àâ¥, à §à¥è¥­¨¥ ¨§¬¥­¥­® á 256å64 16 梥⮢ ­  128å72 256 梥⮢
+ ˆ§¬¥­¥­  ¯à®æ¥¤ãà  ¢ë¢®¤  «®£®â¨¯ , «®£®â¨¯ ¯¥à¥­¥áñ­ ¢ ¤àã£ãî áâà ­¨æã <20>‡“
+ ‘¬¥­  ï§ëª , à §¢ñà⪨ ¨ ¨­â  ¯à®¨á室¨â ¢ Setup áà §ã
+ ˆ§¬¥­¥­ë ­¥ª®â®àë¥ ­ ¤¯¨á¨ ¨ ¯®¯à ¢«¥­  áâàãªâãà  SETUP
+ „®¤¥« ­  äã­ªæ¨ï FN_RESET
+ „®¤¥« ­  äã­ªæ¨ï DCP_CONFIG - äã­ªæ¨ï ã¯à ¢«¥­¨ï ¤¥è¨äà â®à®¬ ¯®à⮢
+ “¡à ­® § ¤¢®¥­¨¥ ä㭪権 4å
+ ”㭪樨 5å ¯¥à¥­¥á¥­ë ¨§ 0 ¢ 8 áâà ­¨æã <20>‡“
+ ˆ§¬¥­¥­  äã­ªæ¨ï ¨­¨æ¨ «¨§ æ¨¨ DCP, ®á¢®¡®¤¨«®áì ®ª®«® 4,5 ª¡
+ ’¥¯¥àì § à¥§¥à¢¨à®¢ ­­ë¥ ¯®¤ ०¨¬ ᯥªâà㬠 áâà ­¨æë ¬®¦­® «¥£ª® ®á¢®¡®¤¨âì, ­®¬¥à ¡«®ª  - 1
+ „®¡ ¢«¥­ë ®¡à §ë <20>‡“ ZX-Sprinter ¤«ï § ¯ã᪠ ०¨¬  ᯥªâà㬠 ¡¥§ § £à㧪¨ DSS
+ ‘âà ­¨æ  BIOS ᮢ¬¥á⨬  á  ¤ ¯â¨à®¢ ­­ë¬¨ ®¡à § ¬¨ <20>‡“ ᯥªâà㬠. ’¥¯¥àì ®â¤¥«ì­ë¥ áâà ­¨æë ®à¨£¨­ «ì­ëå SP_EXP ¨ SP_EXP2
­¥ âॡãîâáï.
+ ˆá¯à ¢«¥­ ¡ £ ¢ ०¨¬¥ ᯥªâà㬠. <20>ਠ¢ë¡®à¥ Clear RAM ¢ ¬¥­î ¨ ¯®á«¥¤ãî騬 ¢ë室®¬ ¢ „Ž‘ ¯® CAD § ¢¨á «®,
¯®â®¬ã çâ® ¢ë§ë¢ « áì ¯à®æ¥¤ãà  FullInit ¤«ï ®ç¨á⪨ ¯ ¬ïâ¨. ’¥¯¥àì ¢¬¥áâ¥ á ®ç¨á⪮© ¯ ¬ï⨠á¡à á뢠¥âáï ¯¥à¥å¢ â à¥á¥â 
+ <09>®¯à ¢«¥­ë ¡ãä¥àë, ®¯â¨¬¨§¨à®¢ ­ë ­¥ª®â®àë¥ ¯à®æ¥¤ãàë, ®á¢®¡®¦¤¥­® ¡¡®«ìè¥ 1,5 ª¡ Ž‡“ ¤«ï à ¡®âë BIOS ¢® ¢à¥¬ï áâ àâ 
+ <09> ©¤¥­® ­¥áª®«ìª® ¤à¥¢­¨å ¬¥«ª¨å ®£à¥å®¢ copy/paste, ¯à¨ à ¡®â¥ ¡ë«® ­¥§ ¬¥â­®, ­® ¯à¨ïâ­®, çâ® ­ è«¨áì
+ <09>®¯à ¢«¥­ ¬ «®¢¥à®ïâ­ë©, ­® ¢®§¬®¦­ë© £«îª á ¯¥à¥¯®«­¥­¨¥¬ á⥪  ¯à¨ ¢å®¤¥-¢ë室¥ ¨§ SETUP
+ <09>®á⥯¥­­ë© à¥ä ªâ®à¨­£ ª®¤ )))
+ ‚ᥣ® ¨ ­¥ ¢á¯®¬­¨âì 㦥...
====================================================================================================================================================================================================================
<EFBFBD>®¢®¥ ®¯¨á ­¨¥ ä㭪樨 <20>ˆŽ‘ FN_SINC (#F2)
LD A,sync_mode ; ०¨¬ ᨭåà®­¨§ æ¨¨
; Reg A bit7 = 0 - ०¨¬ ®ç¨á⪨ íªà ­  ¨ ãáâ ­®¢ª¨ INT
; A=0 ०¨¬ ¯® 㬮«ç ­¨î - ¨á¯®«ì§ã¥âáï ¤«ï ®ç¨á⪨
; áâà ­¨æ ०¨¬  (®âª«î祭¨ï ¢ë¢®¤  ¢á¥å ®ª®­)
; ãáâ ­®¢ª  INT ¨§ á¨á⥬­®© ¯¥à¥¬¥­­®©
; A=1 ०¨¬ Scorpion
; ¯®«®¦¥­¨¥ INT- , ª ª ¢ Scorpion-256
; A=2 ०¨¬ Pentagon
; ¯®«®¦¥­¨¥ INT-a ª ª ¢ Pentagon-128
; A=3 ०¨¬ Spectrum
; ¯®«®¦¥­¨¥ INT-a ª ª ¢ ®à¨£¨­ «ì­®¬ ZX Spectrum
; A=4 ãáâ ­®¢ª  INT ¨§ ­ áâ஥ª ¯®«ì§®¢ â¥«ï ¢ CMOS
;
; Reg A bit7 = 1 - ०¨¬ ãáâ ­®¢ª¨ ¢¥à⨪ «ì­®© ᨭåà®­¨§ æ¨¨ ¨/¨«¨ wait
; bit1,bit0:
; %00 - ᨭåà  ¢ëáâ ¢«ï¥âáï ¨§ á¨á⥬­®© ¯¥à¥¬¥­­®©
; %01 - ᨭåà  ¢ëáâ ¢«ï¥âáï ¨§ CMOS
; %10 - ᨭåà  320 lines 49 Hz
; %11 - ᨭåà  312 lines 50 Hz
; bit2:
; %0 - ¨£­®à¨à®¢ âì bit1..bit0
; %1 - ­¥ ¨£­®à¨à®¢ âì bit1..bit0
;
; bit3:
; %0 - no waits (port all_mode bit2 set)
; %1 - original waits (port all_mode bit2 res)
; bit4:
; %0 - ¨£­®à¨à®¢ âì bit3
; %1 - ­¥ ¨£­®à¨à®¢ âì bit3
;
; bit5,bit6 - reserved
;
DRV_GET_PAR: ; ¯®«ãç¨âì ¯ à ¬¥âàë ­®á¨â¥«ï
LD A,drv_type ; ¡¨â 0..3 - ­®¬¥à ãáâனá⢠
; ¡¨â 4..7 - ⨯ ãáâனá⢠
; 0 - ¤¨áª®¢®¤
; 6 - ram-disk
; 8 - HDD
; C - CD-ROM
LD C,#58 ;
RST ToBIOS ; NC - ­®à¬ «ì­®¥ § ¢¥à襭¨¥
; L - ç¨á«® ᥪâ®à®¢ (­  楫¨­¤à)
; H - ç¨á«® £®«®¢®ª
; DE - ª®«¨ç¥á⢮ 樫¨­¤à®¢
; IX - à §¬¥à ᥪâ®à  ¢ ¡ ©â å
; B - ¤®¯. ¯ à ¬¥âàë:
; FDD:
; ¡¨â7 - ⨯ 1.44/720
; HDD:
; ¡¨â0 - ª ­ « IDE 0/1
; ¡¨â6 - CHS/LBA
;++++++++ ; RMD: ramdrive block id
; ¥á«¨ ¢ HL,DE ¢á¥ FF - ãáâனá⢠ ­¥â
; CF - ­¥â ãáâனá⢠
;
<EFBFBD>®¢®¥ ®¯¨á ­¨¥ ä㭪樨 <20>ˆŽ‘ FN_RESET
FN_RESET: ; ‘¡à®á ¨«¨ ¯¥à¥§ £à㧪 
LD B,res_type ; 1 - à¥áâ àâ, 2 - soft reset, 3 - hard reset, 4 - Reinit spectrum pages
LD C,#FD ; ­®¬¥à ä㭪樨
RST ToBIOS ; CF -> äã­ªæ¨ï ­¥ ¨á¯®«­¥­ , ¢®§¬®¦­ë¥ ¯à¨ç¨­ë:
; ­¥ª®à४⭮¥ §­ ç¥­¨¥ res_type
; ®¤­  ¨§ ZX áâà ­¨æ § ­ïâ  (¯à¨ res_type=4), ⮣¤  ¯®¤ zx ®â¤ áâáï ⮫쪮 ç áâì áâà ­¨æ
; áâ à ï ¢¥àá¨ï BIOS
;
<EFBFBD>®¢®¥ ®¯¨á ­¨¥ ä㭪樨 GET_RAMD_NUM (#9B)
GET_RAMD_NUM: ; ¯®«ãç¨âì ­®¬¥à RAM-Disk-  (0..15) ¯® ¥£® block id
LD A,id_blk ; ¨¤¥­â¨ä¨ª â®à ¡«®ª 
LD C,#9B ; ­®¬¥à ä㭪樨
RST ToBIOS ; NC -> A - ­®¬¥à RAM-Disk-  (0..15).
; CF -> ®è¨¡ª  ¢ ¨¤¥­â¨ä¨ª â®à¥ ¡«®ª  ¨«¨ ¡¨®á ­¨¦¥ 2.55
;
<EFBFBD>®¢®¥ ®¯¨á ­¨¥ ä㭪樨 <20>ˆŽ‘ BLK_RD_WR (#C8)
BLK_RD_WR: ; ç⥭¨¥/§ ¯¨áì ¨§/¢ ¡«®ª( ) ¯ ¬ï⨠ᥪâ®à ¬¨
; ¯® 256 ¡ ©â
LD HL,bufer ;  ¤à¥á ¡ãä¥à  ¤ ­­ëå
LD DE,sector ;  ¡á®«îâ­ë© ­®¬¥à ᥪâ®à  (256b)
LD B,sec_num ; ç¨á«® ᥪâ®à®¢
LD A,id_blk ; ¨¤¥­â¨ä¨ª â®à ¡«®ª  ˆ‹ˆ à §¬¥à ᥪâ®à  (1 - 256b, 2 - 512b) ¯à¨ command = #46
LD A',command ; ª®¬ ­¤  0 - ç⥭¨¥, #FF - § ¯¨áì, #46 ç⥭¨¥ ¨§ ROM-Disk
LD C,#C8 ; ­®¬¥à ä㭪樨
;
s_line_def equ 4
s_line_cmos equ 5
s_lines320 equ 6
s_lines312 equ 7
s_wait_orig equ #18
s_wait_def equ #10
DCP_CONFIG: ; [x] äã­ªæ¨ï ã¯à ¢«¥­¨ï ¤¥è¨äà â®à®¬ ¯®à⮢.
;A - ¥á«¨ ­®«ì, â® ¢ë§®¢ ä㭪樨 ¯¥à¥¨­¨æ¨ «¨§ æ¨¨ ¯®à⮢ PORTS_INIT
;HL -  ¤à¥á
;DE - ¬ áª  - 0 ¨§¬¥­ï¥¬ë¥ ¡¨âë, 1 ­¥¨§¬¥­ï¥¬ë¥
;B - ¯®àâ
;C - #F4 ­®¬¥à ä㭪樨
; !FIXIT ”ã­ªæ¨ï ¯®§¢®«ï¥â ®âªà뢠âì/§ ªà뢠âì ¤®¯®«­¨â¥«ì­ë¥ ¯®àâë ª®¬¯ìîâ¥à .
TODO:
-? ¯ã­ªâ ¢ á¥â ¯¥ "á®åà ­ïâì áâà ­¨æë ᯥªâà㬠 ¯à¨ ¯¥à¥§ £à㧪¥"
- ç¨áâ¨âì ¡ãä¥à ª« ¢ë ­¥ ¢âã¯ãî,   ª ª¨¬¨-­¨¡ã¤ì ª®¬ ­¤ ¬¨ ¤«ï íâ¨å ¢á直å SIO/PIO, ¥á«¨ ¥áâì
Done:
+ ­¥¬­®£® ¤®à ¡®â ­  á¨á⥬  ¯¥à¥å¢ â  à¥á¥â  ¤«ï ãáâà ­¥­¨ï ­¥ª®â®àëå £«îª®¢ ¨ ­  ¡ã¤ã饥
+ ¢ á¥â ¯ à ¡®â ¥â á®åà ­¥­¨¥ ­ áâ஥ª HDD "Setup" ¯®á«¥ ¯¥à¢®£® 㤠筮£®  ¢â®¤¥â¥ªâ 
+ ‘¤¥« ­ ã­¨¢¥àá «ì­ë© § £àã§ç¨ª ¡¨âáâਬ  ¤«ï 1k30 ¨ 1k50
+ €ªâ¨¢¨à®¢ ­ ¢â®à®© ª ­ « IDE
+ <09>㬥à æ¨ï ãáâனá⢠IDE ¯¥à¥¤¥« ­  á ¯®á«¥¤®¢ â¥«ì­®© ­  䨧¨ç¥áªãî
+ ‚ë¡®à § £à㧮筮£® IDE ¨§¬¥­ñ­ á ¯®á«¥¤®¢ â¥«ì­®£® ­  䨧¨ç¥áª¨©
+ „®¡ ¢«¥­  ¢®§¬®¦­®áâì ãáâ ­®¢ª¨ IDE á® ¢â®à®£® ª ­ «  ¢ ª ç¥á⢥ ®á­®¢­®£® ¨  «ìâ¥à­ â¨¢­®£® § £à㧮筮£® ¤¨áª 
+ “¡à ­® § «¨¯ ­¨¥ ª« ¢¨è ¯à¨ à¥á¥â¥ ¯® Ctrl+Alt+Del
+ <09>ਠ­¥ª®à४â­ëå §­ ç¥­¨ïå ¤ âë ¨ ¢à¥¬¥­¨ ¢ CMOS ¤ ­­ë¥ § ¬¥­ïîâáï ­  ¤¥ä®«â­ë¥ §­ ç¥­¨ï, ¢ë¢®¤¨âáï á®®¡é¥­¨¥ ®¡ ®è¨¡ª¥
+ ‚ Setup ¤®¡ ¢«¥­ ¢ë¡®à ०¨¬  à §¢ñà⪨ (--------/Scorpion/Pentagon/Spectrum)
+ ‚ Setup ¤®¡ ¢«¥­ ¢ë¡®à ¢¥à⨪ «ì­®© ᨭåà®­¨§ æ¨¨ (--------/312 50ƒæ/320 49ƒæ)
+ „®¡ ¢«¥­  § £à㧪  á¨á⥬ë á RAM Disk
+ ˆá¯à ¢«¥­ ¡ £ á® á⥪®¬ ¢ BLK_TO_RAMD ¨ ¥éñ ­¥áª®«ìª® ¡ £®¢ ¢ ¯à®æ¥¤ãà å ç⥭¨ï á <20>€Œ-„ˆ‘Š€
+ „®¡ ¢«¥­  § £à㧪  RECOVERY á ROM-Disk ¢ <20>‡“
+ <09>ਠ宫®¤­®¬ áâ à⥠ãáâ ­ ¢«¨¢ ¥âáï ¨­â ¯¥­â £®­  (  ­¥ ᪮௨®­ ), ¥á«¨ ¢ CMOS ­¥ § ¤ ­® ¨­®¥
+ ”ã­ªæ¨ï <20>ˆŽ‘ FN_SINC (#F2) ¯à¨ 㤠筮¬ § ¢¥à襭¨¨ ­¥ á¡à á뢠«  ä« £ CF ­  ¢ë室¥ - ¨á¯à ¢«¥­®
+ <09>®¢ ï äã­ªæ¨ï GET_RAMD_NUM
+ „®¡ ¢«¥­ë¥ ¤®¯®«­¨â¥«ì­ë¥ ®¯æ¨¨ ¢ äã­ªæ¨î <20>ˆŽ‘ FN_SINC (#F2), bit7 ॣ¨áâà  A ⥯¥àì ®â¢¥ç ¥â §  ¯¥à¥ª«î祭¨¥ áâ à®£®/­®¢®£®
¢ à¨ ­â  à ¡®âë ä㭪樨 (¤«ï á®åà ­¥­¨ï ᮢ¬¥á⨬®á⨠ᮠáâ à묨 ¯à®£à ¬¬ ¬¨)
+ <09>®¢®¥ «®£® ¯à¨ áâ àâ¥, à §à¥è¥­¨¥ ¨§¬¥­¥­® á 256å64 16 梥⮢ ­  128å72 256 梥⮢
+ ˆ§¬¥­¥­  ¯à®æ¥¤ãà  ¢ë¢®¤  «®£®â¨¯ , «®£®â¨¯ ¯¥à¥­¥áñ­ ¢ ¤àã£ãî áâà ­¨æã <20>‡“
+ ‘¬¥­  ï§ëª , à §¢ñà⪨ ¨ ¨­â  ¯à®¨á室¨â ¢ Setup áà §ã
+ ˆ§¬¥­¥­ë ­¥ª®â®àë¥ ­ ¤¯¨á¨ ¨ ¯®¯à ¢«¥­  áâàãªâãà  SETUP
+ „®¤¥« ­  äã­ªæ¨ï FN_RESET
+ „®¤¥« ­  äã­ªæ¨ï DCP_CONFIG - äã­ªæ¨ï ã¯à ¢«¥­¨ï ¤¥è¨äà â®à®¬ ¯®à⮢
+ “¡à ­® § ¤¢®¥­¨¥ ä㭪権 4å
+ ”㭪樨 5å ¯¥à¥­¥á¥­ë ¨§ 0 ¢ 8 áâà ­¨æã <20>‡“
+ ˆ§¬¥­¥­  äã­ªæ¨ï ¨­¨æ¨ «¨§ æ¨¨ DCP, ®á¢®¡®¤¨«®áì ®ª®«® 4,5 ª¡
+ ’¥¯¥àì § à¥§¥à¢¨à®¢ ­­ë¥ ¯®¤ ०¨¬ ᯥªâà㬠 áâà ­¨æë ¬®¦­® «¥£ª® ®á¢®¡®¤¨âì, ­®¬¥à ¡«®ª  - 1
+ „®¡ ¢«¥­ë ®¡à §ë <20>‡“ ZX-Sprinter ¤«ï § ¯ã᪠ ०¨¬  ᯥªâà㬠 ¡¥§ § £à㧪¨ DSS
+ ‘âà ­¨æ  BIOS ᮢ¬¥á⨬  á  ¤ ¯â¨à®¢ ­­ë¬¨ ®¡à § ¬¨ <20>‡“ ᯥªâà㬠. ’¥¯¥àì ®â¤¥«ì­ë¥ áâà ­¨æë ®à¨£¨­ «ì­ëå SP_EXP ¨ SP_EXP2
­¥ âॡãîâáï.
+ ˆá¯à ¢«¥­ ¡ £ ¢ ०¨¬¥ ᯥªâà㬠. <20>ਠ¢ë¡®à¥ Clear RAM ¢ ¬¥­î ¨ ¯®á«¥¤ãî騬 ¢ë室®¬ ¢ „Ž‘ ¯® CAD § ¢¨á «®,
¯®â®¬ã çâ® ¢ë§ë¢ « áì ¯à®æ¥¤ãà  FullInit ¤«ï ®ç¨á⪨ ¯ ¬ïâ¨. ’¥¯¥àì ¢¬¥áâ¥ á ®ç¨á⪮© ¯ ¬ï⨠á¡à á뢠¥âáï ¯¥à¥å¢ â à¥á¥â 
+ <09>®¯à ¢«¥­ë ¡ãä¥àë, ®¯â¨¬¨§¨à®¢ ­ë ­¥ª®â®àë¥ ¯à®æ¥¤ãàë, ®á¢®¡®¦¤¥­® ¡¡®«ìè¥ 1,5 ª¡ Ž‡“ ¤«ï à ¡®âë BIOS ¢® ¢à¥¬ï áâ àâ 
+ <09> ©¤¥­® ­¥áª®«ìª® ¤à¥¢­¨å ¬¥«ª¨å ®£à¥å®¢ copy/paste, ¯à¨ à ¡®â¥ ¡ë«® ­¥§ ¬¥â­®, ­® ¯à¨ïâ­®, çâ® ­ è«¨áì
+ <09>®¯à ¢«¥­ ¬ «®¢¥à®ïâ­ë©, ­® ¢®§¬®¦­ë© £«îª á ¯¥à¥¯®«­¥­¨¥¬ á⥪  ¯à¨ ¢å®¤¥-¢ë室¥ ¨§ SETUP
+ <09>®á⥯¥­­ë© à¥ä ªâ®à¨­£ ª®¤ )))
+ ‚ᥣ® ¨ ­¥ ¢á¯®¬­¨âì 㦥...
====================================================================================================================================================================================================================
<EFBFBD>®¢®¥ ®¯¨á ­¨¥ ä㭪樨 <20>ˆŽ‘ FN_SINC (#F2)
LD A,sync_mode ; ०¨¬ ᨭåà®­¨§ æ¨¨
; Reg A bit7 = 0 - ०¨¬ ®ç¨á⪨ íªà ­  ¨ ãáâ ­®¢ª¨ INT
; A=0 ०¨¬ ¯® 㬮«ç ­¨î - ¨á¯®«ì§ã¥âáï ¤«ï ®ç¨á⪨
; áâà ­¨æ ०¨¬  (®âª«î祭¨ï ¢ë¢®¤  ¢á¥å ®ª®­)
; ãáâ ­®¢ª  INT ¨§ á¨á⥬­®© ¯¥à¥¬¥­­®©
; A=1 ०¨¬ Scorpion
; ¯®«®¦¥­¨¥ INT- , ª ª ¢ Scorpion-256
; A=2 ०¨¬ Pentagon
; ¯®«®¦¥­¨¥ INT-a ª ª ¢ Pentagon-128
; A=3 ०¨¬ Spectrum
; ¯®«®¦¥­¨¥ INT-a ª ª ¢ ®à¨£¨­ «ì­®¬ ZX Spectrum
; A=4 ãáâ ­®¢ª  INT ¨§ ­ áâ஥ª ¯®«ì§®¢ â¥«ï ¢ CMOS
;
; Reg A bit7 = 1 - ०¨¬ ãáâ ­®¢ª¨ ¢¥à⨪ «ì­®© ᨭåà®­¨§ æ¨¨ ¨/¨«¨ wait
; bit1,bit0:
; %00 - ᨭåà  ¢ëáâ ¢«ï¥âáï ¨§ á¨á⥬­®© ¯¥à¥¬¥­­®©
; %01 - ᨭåà  ¢ëáâ ¢«ï¥âáï ¨§ CMOS
; %10 - ᨭåà  320 lines 49 Hz
; %11 - ᨭåà  312 lines 50 Hz
; bit2:
; %0 - ¨£­®à¨à®¢ âì bit1..bit0
; %1 - ­¥ ¨£­®à¨à®¢ âì bit1..bit0
;
; bit3:
; %0 - no waits (port all_mode bit2 set)
; %1 - original waits (port all_mode bit2 res)
; bit4:
; %0 - ¨£­®à¨à®¢ âì bit3
; %1 - ­¥ ¨£­®à¨à®¢ âì bit3
;
; bit5,bit6 - reserved
;
DRV_GET_PAR: ; ¯®«ãç¨âì ¯ à ¬¥âàë ­®á¨â¥«ï
LD A,drv_type ; ¡¨â 0..3 - ­®¬¥à ãáâனá⢠
; ¡¨â 4..7 - ⨯ ãáâனá⢠
; 0 - ¤¨áª®¢®¤
; 6 - ram-disk
; 8 - HDD
; C - CD-ROM
LD C,#58 ;
RST ToBIOS ; NC - ­®à¬ «ì­®¥ § ¢¥à襭¨¥
; L - ç¨á«® ᥪâ®à®¢ (­  楫¨­¤à)
; H - ç¨á«® £®«®¢®ª
; DE - ª®«¨ç¥á⢮ 樫¨­¤à®¢
; IX - à §¬¥à ᥪâ®à  ¢ ¡ ©â å
; B - ¤®¯. ¯ à ¬¥âàë:
; FDD:
; ¡¨â7 - ⨯ 1.44/720
; HDD:
; ¡¨â0 - ª ­ « IDE 0/1
; ¡¨â6 - CHS/LBA
;++++++++ ; RMD: ramdrive block id
; ¥á«¨ ¢ HL,DE ¢á¥ FF - ãáâனá⢠ ­¥â
; CF - ­¥â ãáâனá⢠
;
<EFBFBD>®¢®¥ ®¯¨á ­¨¥ ä㭪樨 <20>ˆŽ‘ FN_RESET
FN_RESET: ; ‘¡à®á ¨«¨ ¯¥à¥§ £à㧪 
LD B,res_type ; 1 - à¥áâ àâ, 2 - soft reset, 3 - hard reset, 4 - Reinit spectrum pages
LD C,#FD ; ­®¬¥à ä㭪樨
RST ToBIOS ; CF -> äã­ªæ¨ï ­¥ ¨á¯®«­¥­ , ¢®§¬®¦­ë¥ ¯à¨ç¨­ë:
; ­¥ª®à४⭮¥ §­ ç¥­¨¥ res_type
; ®¤­  ¨§ ZX áâà ­¨æ § ­ïâ  (¯à¨ res_type=4), ⮣¤  ¯®¤ zx ®â¤ áâáï ⮫쪮 ç áâì áâà ­¨æ
; áâ à ï ¢¥àá¨ï BIOS
;
<EFBFBD>®¢®¥ ®¯¨á ­¨¥ ä㭪樨 GET_RAMD_NUM (#9B)
GET_RAMD_NUM: ; ¯®«ãç¨âì ­®¬¥à RAM-Disk-  (0..15) ¯® ¥£® block id
LD A,id_blk ; ¨¤¥­â¨ä¨ª â®à ¡«®ª 
LD C,#9B ; ­®¬¥à ä㭪樨
RST ToBIOS ; NC -> A - ­®¬¥à RAM-Disk-  (0..15).
; CF -> ®è¨¡ª  ¢ ¨¤¥­â¨ä¨ª â®à¥ ¡«®ª  ¨«¨ ¡¨®á ­¨¦¥ 2.55
;
<EFBFBD>®¢®¥ ®¯¨á ­¨¥ ä㭪樨 <20>ˆŽ‘ BLK_RD_WR (#C8)
BLK_RD_WR: ; ç⥭¨¥/§ ¯¨áì ¨§/¢ ¡«®ª( ) ¯ ¬ï⨠ᥪâ®à ¬¨
; ¯® 256 ¡ ©â
LD HL,bufer ;  ¤à¥á ¡ãä¥à  ¤ ­­ëå
LD DE,sector ;  ¡á®«îâ­ë© ­®¬¥à ᥪâ®à  (256b)
LD B,sec_num ; ç¨á«® ᥪâ®à®¢
LD A,id_blk ; ¨¤¥­â¨ä¨ª â®à ¡«®ª  ˆ‹ˆ à §¬¥à ᥪâ®à  (1 - 256b, 2 - 512b) ¯à¨ command = #46
LD A',command ; ª®¬ ­¤  0 - ç⥭¨¥, #FF - § ¯¨áì, #46 ç⥭¨¥ ¨§ ROM-Disk
LD C,#C8 ; ­®¬¥à ä㭪樨
;
s_line_def equ 4
s_line_cmos equ 5
s_lines320 equ 6
s_lines312 equ 7
s_wait_orig equ #18
s_wait_def equ #10
DCP_CONFIG: ; [x] äã­ªæ¨ï ã¯à ¢«¥­¨ï ¤¥è¨äà â®à®¬ ¯®à⮢.
;A - ¥á«¨ ­®«ì, â® ¢ë§®¢ ä㭪樨 ¯¥à¥¨­¨æ¨ «¨§ æ¨¨ ¯®à⮢ PORTS_INIT
;HL -  ¤à¥á
;DE - ¬ áª  - 0 ¨§¬¥­ï¥¬ë¥ ¡¨âë, 1 ­¥¨§¬¥­ï¥¬ë¥
;B - ¯®àâ
;C - #F4 ­®¬¥à ä㭪樨
; !FIXIT ”ã­ªæ¨ï ¯®§¢®«ï¥â ®âªà뢠âì/§ ªà뢠âì ¤®¯®«­¨â¥«ì­ë¥ ¯®àâë ª®¬¯ìîâ¥à .
;

72
src/doc/перехваты ресета.txt → doc/перехваты ресета.txt
View File

@ -1,37 +1,37 @@
‘¥©ç á ¯à¨ áâ à⥠BIOS ®¡à ¡ â뢠îâáï âਠ¢ à¨ ­â  ¯¥à¥å¢ â  Reset:
-------------------------------[‚ à¨ ­â 1]------------------------------
<EFBFBD>®ç⨠áࠧ㠯®á«¥ à¥á¥â  ᯥ樠«ì­ ï ¯à®æ¥¤ãà  ¯à®¢¥àï¥â ¢ áâà ­¨æ¥ #40
¢ ¡ ­ª¥ 3 ¯® ᬥ饭¨î #FFE0 (RESTARTS) ­ «¨ç¨¥ ¯à®£à ¬¬ë ¯¥à¥å¢ â稪 .
<EFBFBD>¥à¢ë¥ 12 ¡ ©â ¯à®£à ¬¬ë ¤®«¦­ë ¡ëâì â ª¨¬¨ ¤«ï ¯¥à¥å¢ â :
ORG #FFE0
RESTARTS_PROG:
LD HL,RESTARTS ; 3
LD B,16 ; 2
.loop:
LD (HL),0 ; 2
INC HL ; 1
DJNZ .loop ; 2
NOP ; 1
NOP ; 1
; ORG #FFEC âãâ à §¬¥é ¥âáï ¯à®£à ¬¬  ¯¥à¥å¢ â稪 ¯®«ì§®¢ â¥«ï
; ®áâ ñâáï 20 ¡ ©â®¢ ­  ¯à®£à ¬¬ã.
<EFBFBD>ਠ¤ ­­®¬ ¢ à¨ ­â¥ § £à㧪¨ ¦¥«¥§® ‘¯à¨­â¥à  ­¥ ¯à®¨­¨æ¨ «¨§¨à®¢ ­®,
­¥ à ¡®â ¥â ¥éñ ¤ ¦¥ ª àâ  ¯®à⮢. ‘ª®à¥¥ ¢á¥£®, â ª®© ¢ à¨ ­â
¯¥à¥å¢ â  - íâ® ­ á«¥¤¨¥ Sp97. Š ª ¢ à¨ ­â, ¥£® ¬®¦­® ¨á¯®«ì§®¢ âì ¢ á«ãç ¥
§ ¯ã᪠ ª®­äë ᨫ쭮 ®â«¨ç î饩áï ®â ⮩, çâ® ®¦¨¤ ¥â BIOS. „«ï í⮣® ­ã¦­®,
ç⮡ ¯à¨ áâ à⥠ «ìâ¥àë ª®­ä  ¯®¤ª«îç «  á«¥¤ãî騥 áâà ­¨æë ¯® ¡ ­ª ¬:
BANK0 - ROM #08
BANK1 - RAM #05
BANK2 - RAM #02
BANK3 - RAM #40
------------------------------------------------------------------------
-------------------------------[‚ à¨ ­â 2]------------------------------
------------------------------------------------------------------------
-------------------------------[‚ à¨ ­â 3]------------------------------
‘¥©ç á ¯à¨ áâ à⥠BIOS ®¡à ¡ â뢠îâáï âਠ¢ à¨ ­â  ¯¥à¥å¢ â  Reset:
-------------------------------[‚ à¨ ­â 1]------------------------------
<EFBFBD>®ç⨠áࠧ㠯®á«¥ à¥á¥â  ᯥ樠«ì­ ï ¯à®æ¥¤ãà  ¯à®¢¥àï¥â ¢ áâà ­¨æ¥ #40
¢ ¡ ­ª¥ 3 ¯® ᬥ饭¨î #FFE0 (RESTARTS) ­ «¨ç¨¥ ¯à®£à ¬¬ë ¯¥à¥å¢ â稪 .
<EFBFBD>¥à¢ë¥ 12 ¡ ©â ¯à®£à ¬¬ë ¤®«¦­ë ¡ëâì â ª¨¬¨ ¤«ï ¯¥à¥å¢ â :
ORG #FFE0
RESTARTS_PROG:
LD HL,RESTARTS ; 3
LD B,16 ; 2
.loop:
LD (HL),0 ; 2
INC HL ; 1
DJNZ .loop ; 2
NOP ; 1
NOP ; 1
; ORG #FFEC âãâ à §¬¥é ¥âáï ¯à®£à ¬¬  ¯¥à¥å¢ â稪 ¯®«ì§®¢ â¥«ï
; ®áâ ñâáï 20 ¡ ©â®¢ ­  ¯à®£à ¬¬ã.
<EFBFBD>ਠ¤ ­­®¬ ¢ à¨ ­â¥ § £à㧪¨ ¦¥«¥§® ‘¯à¨­â¥à  ­¥ ¯à®¨­¨æ¨ «¨§¨à®¢ ­®,
­¥ à ¡®â ¥â ¥éñ ¤ ¦¥ ª àâ  ¯®à⮢. ‘ª®à¥¥ ¢á¥£®, â ª®© ¢ à¨ ­â
¯¥à¥å¢ â  - íâ® ­ á«¥¤¨¥ Sp97. Š ª ¢ à¨ ­â, ¥£® ¬®¦­® ¨á¯®«ì§®¢ âì ¢ á«ãç ¥
§ ¯ã᪠ ª®­äë ᨫ쭮 ®â«¨ç î饩áï ®â ⮩, çâ® ®¦¨¤ ¥â BIOS. „«ï í⮣® ­ã¦­®,
ç⮡ ¯à¨ áâ à⥠ «ìâ¥àë ª®­ä  ¯®¤ª«îç «  á«¥¤ãî騥 áâà ­¨æë ¯® ¡ ­ª ¬:
BANK0 - ROM #08
BANK1 - RAM #05
BANK2 - RAM #02
BANK3 - RAM #40
------------------------------------------------------------------------
-------------------------------[‚ à¨ ­â 2]------------------------------
------------------------------------------------------------------------
-------------------------------[‚ à¨ ­â 3]------------------------------
------------------------------------------------------------------------

568
src/altera/acex/k30/ACCELER.ACF
View File

@ -1,568 +0,0 @@
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
CHIP acceler
BEGIN
DEVICE = EP1K30QC208-3;
END;
DEFAULT_DEVICES
BEGIN
AUTO_DEVICE = EP1K100FC484-1;
AUTO_DEVICE = EP1K100FC256-1;
AUTO_DEVICE = EP1K100QC208-1;
AUTO_DEVICE = EP1K50FC484-1;
AUTO_DEVICE = EP1K50FC256-1;
AUTO_DEVICE = EP1K50QC208-1;
AUTO_DEVICE = EP1K50TC144-1;
AUTO_DEVICE = EP1K30FC256-1;
AUTO_DEVICE = EP1K30QC208-1;
AUTO_DEVICE = EP1K30TC144-1;
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;
TIMING_POINT
BEGIN
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3;
FREQUENCY = 200MHz;
MAINTAIN_STABLE_SYNTHESIS = OFF;
CUT_ALL_CLEAR_PRESET = ON;
CUT_ALL_BIDIR = ON;
END;
IGNORED_ASSIGNMENTS
BEGIN
FIT_IGNORE_TIMING = OFF;
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
IGNORE_DEVICE_ASSIGNMENTS = OFF;
IGNORE_LC_ASSIGNMENTS = OFF;
IGNORE_PIN_ASSIGNMENTS = OFF;
IGNORE_CHIP_ASSIGNMENTS = OFF;
IGNORE_TIMING_ASSIGNMENTS = OFF;
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
END;
GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
MAX7000B_ENABLE_VREFB = OFF;
MAX7000B_ENABLE_VREFA = OFF;
MAX7000B_VCCIO_IOBANK2 = 3.3V;
MAX7000B_VCCIO_IOBANK1 = 3.3V;
CONFIG_EPROM_PULLUP_RESISTOR = ON;
CONFIG_EPROM_USER_CODE = FFFFFFFF;
FLEX_CONFIGURATION_EPROM = AUTO;
MAX7000AE_ENABLE_JTAG = ON;
MAX7000AE_USER_CODE = FFFFFFFF;
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX6000_ENABLE_JTAG = OFF;
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
MULTIVOLT_IO = OFF;
MAX7000S_ENABLE_JTAG = ON;
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
MAX7000S_USER_CODE = FFFF;
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
FLEX10K_JTAG_USER_CODE = 7F;
ENABLE_INIT_DONE_OUTPUT = OFF;
ENABLE_CHIP_WIDE_OE = OFF;
ENABLE_CHIP_WIDE_RESET = OFF;
nCEO = UNRESERVED;
CLKUSR = UNRESERVED;
ADD17 = UNRESERVED;
ADD16 = UNRESERVED;
ADD15 = UNRESERVED;
ADD14 = UNRESERVED;
ADD13 = UNRESERVED;
ADD0_TO_ADD12 = UNRESERVED;
SDOUT = RESERVED_DRIVES_OUT;
RDCLK = UNRESERVED;
RDYnBUSY = UNRESERVED;
nWS_nRS_nCS_CS = UNRESERVED;
DATA1_TO_DATA7 = UNRESERVED;
DATA0 = RESERVED_TRI_STATED;
FLEX8000_ENABLE_JTAG = OFF;
CONFIG_SCHEME = ACTIVE_SERIAL;
DISABLE_TIME_OUT = OFF;
ENABLE_DCLK_OUTPUT = OFF;
RELEASE_CLEARS = OFF;
AUTO_RESTART = OFF;
USER_CLOCK = OFF;
SECURITY_BIT = OFF;
RESERVED_PINS_PERCENT = 0;
RESERVED_LCELLS_PERCENT = 0;
END;
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
STYLE = FAST;
DEVICE_FAMILY = ACEX1K;
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
AUTO_IMPLEMENT_IN_EAB = OFF;
AUTO_OPEN_DRAIN_PINS = ON;
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
AUTO_REGISTER_PACKING = OFF;
AUTO_FAST_IO = OFF;
AUTO_GLOBAL_OE = ON;
AUTO_GLOBAL_PRESET = ON;
AUTO_GLOBAL_CLEAR = ON;
AUTO_GLOBAL_CLOCK = ON;
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
OPTIMIZE_FOR_SPEED = 5;
END;
COMPILER_PROCESSING_CONFIGURATION
BEGIN
USE_QUARTUS_FITTER = ON;
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
FITTER_SETTINGS = NORMAL;
SMART_RECOMPILE = OFF;
GENERATE_AHDL_TDO_FILE = OFF;
RPT_FILE_USER_ASSIGNMENTS = ON;
RPT_FILE_LCELL_INTERCONNECT = ON;
RPT_FILE_HIERARCHY = ON;
RPT_FILE_EQUATIONS = ON;
LINKED_SNF_EXTRACTOR = OFF;
OPTIMIZE_TIMING_SNF = OFF;
TIMING_SNF_EXTRACTOR = ON;
FUNCTIONAL_SNF_EXTRACTOR = OFF;
DESIGN_DOCTOR_RULES = EPLD;
DESIGN_DOCTOR = OFF;
END;
COMPILER_INTERFACES_CONFIGURATION
BEGIN
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
EDIF_BUS_DELIMITERS = [];
EDIF_FLATTEN_BUS = OFF;
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
EDIF_OUTPUT_USE_EDC = OFF;
EDIF_INPUT_USE_LMF2 = OFF;
EDIF_INPUT_USE_LMF1 = OFF;
EDIF_OUTPUT_GND = GND;
EDIF_OUTPUT_VCC = VCC;
EDIF_INPUT_GND = GND;
EDIF_INPUT_VCC = VCC;
EDIF_OUTPUT_EDC_FILE = *.edc;
EDIF_INPUT_LMF2 = *.lmf;
EDIF_INPUT_LMF1 = *.lmf;
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
VHDL_FLATTEN_BUS = OFF;
VERILOG_FLATTEN_BUS = OFF;
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
VHDL_WRITER_VERSION = VHDL87;
VHDL_READER_VERSION = VHDL87;
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
SYNOPSYS_DESIGNWARE = OFF;
SYNOPSYS_COMPILER = DESIGN;
USE_SYNOPSYS_SYNTHESIS = OFF;
VHDL_NETLIST_WRITER = OFF;
VERILOG_NETLIST_WRITER = OFF;
XNF_GENERATE_AHDL_TDX_FILE = ON;
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
EDIF_OUTPUT_VERSION = 200;
EDIF_NETLIST_WRITER = OFF;
END;
CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
MASTER_RESET = OFF;
EXPANDER_NETWORKS = ON;
RACE_CONDITIONS = ON;
DELAY_CHAINS = ON;
ASYNCHRONOUS_INPUTS = ON;
PRESET_CLEAR_NETWORKS = ON;
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
MULTI_CLOCK_NETWORKS = ON;
MULTI_LEVEL_CLOCKS = ON;
GATED_CLOCKS = ON;
RIPPLE_CLOCKS = ON;
END;
SIMULATOR_CONFIGURATION
BEGIN
END_TIME = 5.0us;
BIDIR_PIN = STRONG;
START_TIME = 0.0ns;
GLITCH_TIME = 0.0ns;
GLITCH = OFF;
OSCILLATION_TIME = 0.0ns;
OSCILLATION = OFF;
CHECK_OUTPUTS = OFF;
SETUP_HOLD = OFF;
USE_DEVICE = OFF;
END;
TIMING_ANALYZER_CONFIGURATION
BEGIN
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
LIST_PATH_FREQUENCY = 10MHz;
LIST_PATH_COUNT = 10;
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
INCLUDE_PATHS_LESS_THAN = OFF;
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
INCLUDE_PATHS_GREATER_THAN = OFF;
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
CELL_WIDTH = 18;
LIST_ONLY_LONGEST_PATH = ON;
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
CUT_OFF_IO_PIN_FEEDBACK = ON;
AUTO_RECALCULATE = OFF;
END;
OTHER_CONFIGURATION
BEGIN
LAST_MAXPLUS2_VERSION = 10.0;
ROW_PINS_LCELL_INSERT = ON;
CARRY_OUT_PINS_LCELL_INSERT = OFF;
NORMAL_LCELL_INSERT = ON;
EXPLICIT_FAMILY = 1;
FLEX_10K_52_COLUMNS = 40;
DEFAULT_9K_EXP_PER_LCELL = 1/2;
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
LCELLS_PER_ROW_PERCENT = 100;
FAN_IN_PER_LCELL_PERCENT = 100;
EXP_PER_LCELL_PERCENT = 100;
ROW_PINS_PERCENT = 50;
ORIGINAL_MAXPLUS2_VERSION = 9.6;
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN = IGNORE;
MINIMIZATION = FULL;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN = IGNORE;
MINIMIZATION = FULL;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
PARALLEL_EXPANDERS = ON;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN = IGNORE;
MINIMIZATION = FULL;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
CARRY_CHAIN_LENGTH = 32;
CASCADE_CHAIN_LENGTH = 2;
REGISTER_OPTIMIZATION = ON;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
CARRY_CHAIN = AUTO;
CASCADE_CHAIN = AUTO;
MINIMIZATION = FULL;
IGNORE_SOFT_BUFFERS = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = MANUAL;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = MANUAL;
END;

26
src/altera/acex/k30/ACCELER.INC
View File

@ -1,26 +0,0 @@
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- MAX+plus II Include File
-- Version 10.0 9/14/2000
-- Created: Fri Jan 25 12:59:19 2002
FUNCTION acceler (clk42, /reset, ct[2..0], ras, cas, clk_z80, mc_end, mc_begin, mc_type, mc_write, ai[15..0], di[7..0], /io, /rd, /wr, /mr, /rf, /m1, /iom, dcp[7..0], mdi[15..0], acc_ena, hddr[7..0], hdd_flip)
RETURNS (continue, ao[15..0], do[7..0], mdo[15..0], md[7..0], g_line[7..0], glisser, acc_on, double_cas, acc_dir[7..0]);

374
src/altera/acex/k30/ACCELER.TDF
View File

@ -1,374 +0,0 @@
TITLE "ACCELERATOR";
INCLUDE "lpm_ram_dp";
SUBDESIGN acceler
(
CLK42 : INPUT;
/RESET : INPUT;
CT[2..0] : INPUT;
RAS : INPUT;
CAS : INPUT;
CLK_Z80 : INPUT;
CONTINUE : OUTPUT;
MC_END : INPUT;
MC_BEGIN : INPUT;
MC_TYPE : INPUT;
MC_WRITE : INPUT;
-- MCA[1..0] : INPUT;
AI[15..0] : INPUT;
DI[7..0] : INPUT;
AO[15..0] : OUTPUT;
DO[7..0] : OUTPUT;
/IO : INPUT;
/RD : INPUT;
/WR : INPUT;
/MR : INPUT;
/RF : INPUT;
/M1 : INPUT;
/IOM : INPUT;
DCP[7..0] : INPUT;
MDI[15..0] : INPUT;
MDO[15..0] : OUTPUT;
MD[7..0] : OUTPUT;
G_LINE[7..0]: OUTPUT;
GLISSER : OUTPUT;
ACC_ON : OUTPUT;
ACC_ENA : INPUT;
DOUBLE_CAS : OUTPUT;
HDDR[7..0] : INPUT;
HDD_FLIP : INPUT;
ACC_DIR[7..0] : OUTPUT;
)
VARIABLE
RAM : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8);
DO[7..0] : DFFE;
MDO[15..0] : DFFE;
PRF_CMD : DFFE;
ED_CMD : DFFE;
CB_CMD : DFFE;
ID_CMD : DFFE;
IN_OUT_CMD : DFFE;
CORRECT_1F : NODE;
ACC_BLK : DFF;
RETI : DFFE;
RETN : DFFE;
AA[15..0] : DFFE;
RGACC[7..0] : DFFE;
AGR[7..0] : DFFE;
ACC_CNT[7..0] : DFFE;
START_ACC : NODE;
ACC_END : DFFE;
FN_ACC[2..0]: DFFE;
ACC_MODE[3..0] : DFFE;
MD[7..0] : LCELL;
XMD[7..0] : DFF;
XMDH[7..0] : DFF;
ACC_DIR[7..0] : LCELL;
/M1M : NODE;
ACC_GO : NODE;
ACC_GO_1 : NODE;
RAM_WR : NODE;
STATE_EI : DFFE;
-- HDDR[7..0] : DFFE;
XAGR[7..0] : DFFE;
AAGR[9..0] : DFFE;
XCNT[7..0] : DFFE;
ALT_ACC : NODE;
RAM_ADR[7..0] : NODE;
ACC_C : NODE;
WR_C7 : NODE;
XCNT_AGR[15..0] : NODE;
MDOX[7..0] : DFF;
MDOY[7..0] : DFF;
GLISS_R : DFF;
ACC_TIME : NODE;
BEGIN
ACC_ON = ACC_DIR0;
/M1M = DFF(!/M1,CLK_Z80,/RESET,);
PRF_CMD.clk = /MR;
PRF_CMD.ena = /M1M;
PRF_CMD.d = (DI[] == B"11XX1XX1") &
((DI[] == B"XX00X01X") or -- CB
(DI[] == B"XX01X10X") or -- DD
(DI[] == B"XX10X10X") or -- ED
(DI[] == B"XX11X10X")); -- FD
-- === interrupt === 0 - disable; 1 - enable
STATE_EI.clk = /MR;
STATE_EI.ena = /M1M & !PRF_CMD & (DI[] == B"1111X011");
STATE_EI.d = DI3;
-- RETI comand
ED_CMD.clk = /MR;
ED_CMD.ena = /M1M;
ED_CMD.d = (DI[] == H"ED");
RETI.clk = /MR;
RETI.ena = /M1M;
RETI.d = ED_CMD & (DI[] == H"4D");
-- "1" on the RETI triger is the end of interupt sycle.
RETN.clk = /MR;
RETN.ena = /M1M;
RETN.d = ED_CMD & (DI[] == H"45");
-- The end of NMI sycle.
ACC_BLK.clk = /M1;
ACC_BLK.d = DFF(((/IO & ACC_BLK) or (!ACC_BLK & RETI)),CLK_Z80,,);
ACC_BLK.prn = /RESET & ACC_MODE3;
CB_CMD.clk = /MR;
ID_CMD.clk = /MR;
CB_CMD.ena = /M1M;
ID_CMD.ena = /M1M;
CB_CMD.d = (DI[] == H"CB");
ID_CMD.d = (DI[] == B"11X11101");
IN_OUT_CMD.clk = /MR;
IN_OUT_CMD.ena = /M1M;
IN_OUT_CMD.d = (DI[] == B"1101X011") & !PRF_CMD; -- D3/DB
IN_OUT_CMD.clrn = /IO;
CORRECT_1F = LCELL(IN_OUT_CMD & (DO[] == H"1F") & !/MR & !/RD);
DO[4..3].clrn = !CORRECT_1F;
ACC_GO = DFFE((CAS or START_ACC),CLK42,,(!/MR & /M1),CT1);
ACC_GO_1 = DFF(ACC_GO,CLK42,,);
-- == accelerator number ==
RGACC[].clk = /MR;
RGACC[].ena = DFF((/M1 & /RF & ACC_DIR3),CLK_Z80,,);
RGACC[].d = DI[];
-- == accelerator grafic line ==
AGR[].clk = CLK42;
AGR[].ena = !DFF((/IOM or /WR or !DFF((DCP[] == B"1100X100"),CLK42,,)),CLK42,,) or
!(!ACC_DIR4 or ACC_GO or !ACC_GO_1);
CASE DFF(START_ACC,CLK42,,) IS
WHEN 0 => AGR[].d = AGR[] + 1;
WHEN 1 => AGR[].d = DI[];
END CASE;
AGR[].clrn = /RESET;
G_LINE[] = AGR[];
-- == accelerator counter ==
ACC_C = (!ACC_GO & DFF(((CT0 & !/RD) or (CT1 & !/WR)),CLK42,,));
ACC_CNT[].clk = CLK42;
-- ACC_CNT[].ena = START_ACC or (ACC_C & ACC_DIR2);
ACC_CNT[].ena = LCELL(START_ACC or (ACC_C & ACC_DIR2));
CASE DFF(START_ACC,CLK42,,) IS
WHEN 1 => ACC_CNT[].d = RGACC[];
WHEN 0 => ACC_CNT[].d = ACC_CNT[] - 1;
END CASE;
WR_C7 = DFF((/IOM or DFF(!/IOM,CLK42,,) or /WR or DFF(!(DCP[] == B"1100X111"),CLK42,,)),CLK42,,);
ALT_ACC = DFF(VCC,WR_C7,/RESET,);
(AAGR[].ena,XCNT[].ena,XAGR[].ena) = LCELL(!WR_C7 or (ACC_DIR1 & ACC_C));
(AAGR[].clk,XCNT[].clk,XAGR[].clk) = CLK42;
XCNT_AGR[15..0] = (XCNT[],XAGR[]) + (B"000000",AAGR[]);
CASE !DFF(START_ACC,CLK42,,) IS
WHEN 1 => AAGR[].d = AAGR[];
(XCNT[].d,XAGR[].d) = XCNT_AGR[15..0];
WHEN 0 => AAGR[].d = (AI9,AI8,DI[]);
(XCNT[].d,XAGR[].d) = (B"00",AI[15..10],B"00000000");
END CASE;
-- == accelerator dir ==
START_ACC = LCELL(LCELL(/MR or !/M1 or !/RF or !ACC_BLK) or (!ACC_DIR0 or MC_TYPE));
DOUBLE_CAS= LCELL(ACC_DIR6 & !START_ACC);
ACC_END.clk = CLK42;
ACC_END.ena = !ACC_GO & ACC_GO_1;
ACC_END.prn = /M1;
ACC_END.d = (ACC_CNT[] == 1) or !ACC_DIR2;
CONTINUE = ACC_END;
CASE ACC_MODE[2..0] IS
WHEN 0 => ACC_DIR[] = B"00000000"; % LD B,B %
WHEN 1 => ACC_DIR[] = B"00100101"; % LD C,C % % fill by constant %
WHEN 2 => ACC_DIR[] = B"00001001"; % LD D,D % % load count accelerator %
WHEN 3 => ACC_DIR[] = B"00010101"; % LD E,E % % fill by constant VERTICAL %
WHEN 4 => ACC_DIR[] = B"01000001"; % LD H,H % % duble byte fn %
WHEN 5 => ACC_DIR[] = B"00100111"; % LD L,L % % copy line %
WHEN 6 => ACC_DIR[] = B"00000000"; % HALT %
WHEN 7 => ACC_DIR[] = B"00010111"; % LD A,A % % copy line VERTICAL %
END CASE;
-- == accelerator mode ==
ACC_MODE[].clk = /MR;
ACC_MODE[].ena = DFF((!/M1 & !PRF_CMD &
LCELL((DI[] == B"XXX00X00") or
(DI[] == B"XXX01X01") or
(DI[] == B"XXX10X10") or
(DI[] == B"XXX11X11")) &
LCELL((DI[] == B"010XX0XX") or
(DI[] == B"011XX1XX"))),CLK_Z80,,);
ACC_MODE[].d = (VCC,DI[2..0]);
ACC_MODE[2..0].clrn = /RESET & ACC_ENA;
ACC_MODE[3].clrn = /RESET & !DFF(ACC_MODE3,CLK_Z80,,);
-- == accelerator datas ==
CASE DFFE(AA0,CLK42,,,(CT2 & CT1)) IS
WHEN 0 => MD[] = MDI[7..0];
-- GLISSER = DFF((MDO[7..0] == H"FF"),CLK42,,);
WHEN 1 => MD[] = MDI[15..8];
-- GLISSER = DFF((MDO[15..8] == H"FF"),CLK42,,);
END CASE;
GLISS_R.clk = CLK42;
CASE ACC_DIR1 IS
WHEN 0 => GLISS_R = LCELL(DI[] == H"FF");
WHEN 1 => GLISS_R = LCELL(RAM.q[7..4] == H"F") & LCELL(RAM.q[3..0] == H"F");
END CASE;
GLISSER = GLISS_R;
-- MDO[].clk = !CLK42;
MDO[].clk = CLK42;
MDO[].ena = CAS;
MDOX[].clk = CLK42;
MDOY[].clk = CLK42;
CASE LCELL(MC_END & HDD_FLIP) IS
WHEN 0 => MDOX[7..0] = DI[];
WHEN 1 => MDOX[7..0] = HDDR[];
END CASE;
CASE ACC_DIR6 IS
WHEN 0 => MDOY[7..0] = DI[];
WHEN 1 => MDOY[7..0] = HDDR[];
END CASE;
CASE LCELL(/IO & ACC_DIR1) IS
WHEN 0 => MDO[].d = (MDOY[],MDOX[]);
WHEN 1 => MDO[].d = (RAM.q[7..0],RAM.q[7..0]);
END CASE;
DO[].clk = DFF(MC_END,!CLK42,,);
-- DO[].clk = !CLK42;
DO[].ena = VCC;
-- DO[].ena = DFF(!MC_END,CLK42,,);
DO[].d = MD[];
-- == accelerator functions ==
FN_ACC[].clk = /MR;
FN_ACC[].ena = /M1M;
FN_ACC[].d = LCELL(DI7 & !DI6 & !PRF_CMD) & !(DI[5..3]);
XMDH[].clk = !CLK42;
XMDH[] = MDI[15..8];
XMD[].clk = !CLK42;
CASE FN_ACC[1..0] IS
WHEN 0 =>
XMD[] = MD[]; % BE %
WHEN 1 =>
XMD[] = MD[] or RAM.q[7..0]; % B6 %
WHEN 2 =>
XMD[] = MD[] xor RAM.q[7..0]; % AE %
WHEN 3 =>
XMD[] = MD[] & RAM.q[7..0]; % A6 %
END CASE;
CASE ALT_ACC IS
WHEN 0 => RAM_ADR[] = ACC_CNT[];
WHEN 1 => RAM_ADR[] = XCNT[];
END CASE;
ACC_TIME = LCELL((!ACC_END or !DFFE(ACC_END,CLK42,,,(CT1 & CT2))));
-- RAM_WR = DFF((!/RD & (!ACC_GO & CT0) & ACC_TIME),CLK42,,);
RAM_WR = DFF((!/RD & (!ACC_GO & CT0) & ACC_DIR1),CLK42,,);
RAM.wren = RAM_WR;
RAM.data[] = (XMD[],XMD[]);
-- RAM.wraddress[] = ACC_CNT[];
RAM.wraddress[] = RAM_ADR[];
RAM.wrclock = CLK42;
RAM.wrclken = VCC;
RAM.rden = VCC;
-- RAM.rdaddress[] = ACC_CNT[];
RAM.rdaddress[] = RAM_ADR[];
RAM.rdclock = CLK42;
RAM.rdclken = VCC;
AA[].clk = CLK42;
-- AA[].ena = START_ACC or (ACC_DIR5 & !ACC_GO & ACC_GO_1);
AA[].ena = LCELL(START_ACC or (ACC_DIR5 & !(CAS or START_ACC) & (ACC_GO or (ACC_GO_1 & ACC_DIR6))));
CASE DFF(START_ACC,CLK42,,) IS
WHEN 1 => AA[].d = AI[];
-- WHEN 0 => AA[].d = AA[] + (B"00000000000000",ACC_DIR6,!ACC_DIR6);
WHEN 0 => AA[].d = AA[] + 1;
END CASE;
AO[] = (AA[15..0]);
END;

578
src/altera/acex/k30/AY.ACF
View File

@ -1,578 +0,0 @@
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
CHIP ay
BEGIN
DEVICE = EP1K30QC208-3;
END;
DEFAULT_DEVICES
BEGIN
AUTO_DEVICE = EP1K100FC484-1;
AUTO_DEVICE = EP1K100FC256-1;
AUTO_DEVICE = EP1K100QC208-1;
AUTO_DEVICE = EP1K50FC484-1;
AUTO_DEVICE = EP1K50FC256-1;
AUTO_DEVICE = EP1K50QC208-1;
AUTO_DEVICE = EP1K50TC144-1;
AUTO_DEVICE = EP1K30FC256-1;
AUTO_DEVICE = EP1K30QC208-1;
AUTO_DEVICE = EP1K30TC144-1;
AUTO_DEVICE = EP1K10FC256-1;
AUTO_DEVICE = EP1K10QC208-1;
AUTO_DEVICE = EP1K10TC144-1;
AUTO_DEVICE = EP1K10TC100-1;
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;
TIMING_POINT
BEGIN
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3;
FREQUENCY = 100MHz;
MAINTAIN_STABLE_SYNTHESIS = OFF;
CUT_ALL_CLEAR_PRESET = ON;
CUT_ALL_BIDIR = ON;
END;
IGNORED_ASSIGNMENTS
BEGIN
FIT_IGNORE_TIMING = ON;
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
IGNORE_DEVICE_ASSIGNMENTS = OFF;
IGNORE_LC_ASSIGNMENTS = OFF;
IGNORE_PIN_ASSIGNMENTS = OFF;
IGNORE_CHIP_ASSIGNMENTS = OFF;
IGNORE_TIMING_ASSIGNMENTS = OFF;
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
END;
GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
MAX7000B_ENABLE_VREFB = OFF;
MAX7000B_ENABLE_VREFA = OFF;
MAX7000B_VCCIO_IOBANK2 = 3.3V;
MAX7000B_VCCIO_IOBANK1 = 3.3V;
CONFIG_EPROM_PULLUP_RESISTOR = ON;
CONFIG_EPROM_USER_CODE = FFFFFFFF;
FLEX_CONFIGURATION_EPROM = AUTO;
MAX7000AE_ENABLE_JTAG = ON;
MAX7000AE_USER_CODE = FFFFFFFF;
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX6000_ENABLE_JTAG = OFF;
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
MULTIVOLT_IO = OFF;
MAX7000S_ENABLE_JTAG = ON;
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
MAX7000S_USER_CODE = FFFF;
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
FLEX10K_JTAG_USER_CODE = 7F;
ENABLE_INIT_DONE_OUTPUT = OFF;
ENABLE_CHIP_WIDE_OE = OFF;
ENABLE_CHIP_WIDE_RESET = OFF;
nCEO = UNRESERVED;
CLKUSR = UNRESERVED;
ADD17 = UNRESERVED;
ADD16 = UNRESERVED;
ADD15 = UNRESERVED;
ADD14 = UNRESERVED;
ADD13 = UNRESERVED;
ADD0_TO_ADD12 = UNRESERVED;
SDOUT = RESERVED_DRIVES_OUT;
RDCLK = UNRESERVED;
RDYnBUSY = UNRESERVED;
nWS_nRS_nCS_CS = UNRESERVED;
DATA1_TO_DATA7 = UNRESERVED;
DATA0 = RESERVED_TRI_STATED;
FLEX8000_ENABLE_JTAG = OFF;
CONFIG_SCHEME = ACTIVE_SERIAL;
DISABLE_TIME_OUT = OFF;
ENABLE_DCLK_OUTPUT = OFF;
RELEASE_CLEARS = OFF;
AUTO_RESTART = OFF;
USER_CLOCK = OFF;
SECURITY_BIT = OFF;
RESERVED_PINS_PERCENT = 0;
RESERVED_LCELLS_PERCENT = 0;
END;
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
AUTO_IMPLEMENT_IN_EAB = OFF;
AUTO_OPEN_DRAIN_PINS = ON;
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
AUTO_REGISTER_PACKING = OFF;
DEVICE_FAMILY = ACEX1K;
STYLE = NORMAL;
AUTO_FAST_IO = OFF;
AUTO_GLOBAL_OE = ON;
AUTO_GLOBAL_PRESET = ON;
AUTO_GLOBAL_CLEAR = ON;
AUTO_GLOBAL_CLOCK = ON;
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
OPTIMIZE_FOR_SPEED = 5;
END;
COMPILER_PROCESSING_CONFIGURATION
BEGIN
USE_QUARTUS_FITTER = ON;
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
FITTER_SETTINGS = NORMAL;
SMART_RECOMPILE = OFF;
GENERATE_AHDL_TDO_FILE = OFF;
RPT_FILE_USER_ASSIGNMENTS = ON;
RPT_FILE_LCELL_INTERCONNECT = ON;
RPT_FILE_HIERARCHY = ON;
RPT_FILE_EQUATIONS = ON;
LINKED_SNF_EXTRACTOR = OFF;
OPTIMIZE_TIMING_SNF = OFF;
TIMING_SNF_EXTRACTOR = ON;
FUNCTIONAL_SNF_EXTRACTOR = OFF;
DESIGN_DOCTOR_RULES = EPLD;
DESIGN_DOCTOR = OFF;
END;
COMPILER_INTERFACES_CONFIGURATION
BEGIN
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
EDIF_BUS_DELIMITERS = [];
EDIF_FLATTEN_BUS = OFF;
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
EDIF_OUTPUT_USE_EDC = OFF;
EDIF_INPUT_USE_LMF2 = OFF;
EDIF_INPUT_USE_LMF1 = OFF;
EDIF_OUTPUT_GND = GND;
EDIF_OUTPUT_VCC = VCC;
EDIF_INPUT_GND = GND;
EDIF_INPUT_VCC = VCC;
EDIF_OUTPUT_EDC_FILE = *.edc;
EDIF_INPUT_LMF2 = *.lmf;
EDIF_INPUT_LMF1 = *.lmf;
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
VHDL_FLATTEN_BUS = OFF;
VERILOG_FLATTEN_BUS = OFF;
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
VHDL_WRITER_VERSION = VHDL93;
VHDL_READER_VERSION = VHDL93;
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
SYNOPSYS_DESIGNWARE = OFF;
SYNOPSYS_COMPILER = DESIGN;
USE_SYNOPSYS_SYNTHESIS = OFF;
VHDL_NETLIST_WRITER = OFF;
VERILOG_NETLIST_WRITER = OFF;
XNF_GENERATE_AHDL_TDX_FILE = ON;
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
EDIF_OUTPUT_VERSION = 200;
EDIF_NETLIST_WRITER = OFF;
END;
CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
MASTER_RESET = OFF;
EXPANDER_NETWORKS = ON;
RACE_CONDITIONS = ON;
DELAY_CHAINS = ON;
ASYNCHRONOUS_INPUTS = ON;
PRESET_CLEAR_NETWORKS = ON;
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
MULTI_CLOCK_NETWORKS = ON;
MULTI_LEVEL_CLOCKS = ON;
GATED_CLOCKS = ON;
RIPPLE_CLOCKS = ON;
END;
SIMULATOR_CONFIGURATION
BEGIN
BIDIR_PIN = STRONG;
END_TIME = 0.0ns;
START_TIME = 0.0ns;
GLITCH_TIME = 0.0ns;
GLITCH = OFF;
OSCILLATION_TIME = 0.0ns;
OSCILLATION = OFF;
CHECK_OUTPUTS = OFF;
SETUP_HOLD = OFF;
USE_DEVICE = OFF;
END;
TIMING_ANALYZER_CONFIGURATION
BEGIN
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
LIST_PATH_FREQUENCY = 10MHz;
LIST_PATH_COUNT = 10;
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
INCLUDE_PATHS_LESS_THAN = OFF;
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
INCLUDE_PATHS_GREATER_THAN = OFF;
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
CELL_WIDTH = 18;
LIST_ONLY_LONGEST_PATH = ON;
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
CUT_OFF_IO_PIN_FEEDBACK = ON;
AUTO_RECALCULATE = OFF;
END;
OTHER_CONFIGURATION
BEGIN
ROW_PINS_LCELL_INSERT = ON;
CARRY_OUT_PINS_LCELL_INSERT = OFF;
NORMAL_LCELL_INSERT = ON;
EXPLICIT_FAMILY = 1;
LAST_MAXPLUS2_VERSION = 10.0;
FLEX_10K_52_COLUMNS = 40;
DEFAULT_9K_EXP_PER_LCELL = 1/2;
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
LCELLS_PER_ROW_PERCENT = 100;
FAN_IN_PER_LCELL_PERCENT = 100;
EXP_PER_LCELL_PERCENT = 100;
ROW_PINS_PERCENT = 50;
ORIGINAL_MAXPLUS2_VERSION = 10.0;
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = ON;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = AUTO;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = AUTO;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = MANUAL;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = MANUAL;
END;

26
src/altera/acex/k30/AY.INC
View File

@ -1,26 +0,0 @@
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- MAX+plus II Include File
-- Version 10.0 9/14/2000
-- Created: Sat May 26 07:09:40 2001
FUNCTION ay (/reset, clk42, ay_t[8..0], ay_d_wr, ay_a_wr, d[7..0], beeper)
RETURNS (do[7..0], ay_ch_a[3..0], ay_ch_b[3..0], ay_ch_c[3..0], ay_ch_l[9..0], ay_ch_r[9..0], ay_ch_val);

154
src/altera/acex/k30/AY.MIF
View File

@ -1,154 +0,0 @@
DEPTH = 256; % Memory depth and width are required %
WIDTH = 8; % Enter a decimal number %
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
DATA_RADIX = BIN; % Enter BIN, DEC, HEX, or OCT; unless %
% otherwise specified, radixes = HEX %
-- Specify values for addresses, which can be single address or range
CONTENT
BEGIN
[0..7F] : 00000000;
0 : 00000000 00000000
00000000 00000000
00000000 00000000
00000000 11111111
00000000 00000000
00000000 00000000
00000000 00000000
00000000 00000000
11111111 11111111
11111111 11111111
11111111 11111111
11111111 11111111
11111111 11111111
11111111 11111111
11111111 00000001
00000000 11111111
;
1E : 00000000;
1F : 11111111;
30 : 00000000
00000010
00000011
00000100
00000110
00001000
00001011
00010000
00010110
00100000
00101101
01000000
01011010
10000000
10110100
11111111;
[80..FF]: 00000000;
%
000 - set CX, load & sub 1
001 - load
010 - save, if NZ,reset CX
011 - bit_out
100 - load & sub 1
101 - load & sub C
110 - if CX, save
111 - read states /RESET, AY_F_RES
%
80 :
00010000 -- set C,CX load reg10 & sub C
01010000 -- save reg10 & reset CX if NZ
10110001 -- load reg11 & sub C
01010001 -- save reg11 & reset CX if NZ
00100000 -- set C load reg00 & sub C
11010000 -- save reg10 if CX
00100001 -- load reg01 & sub C
11010001 -- save reg11 if CX
00101000 -- load reg08
01100001 -- set AY_OUT1
00010010 -- set C,CX load reg12 & sub C
01010010 -- save reg12 & reset CX if NZ
10110011 -- load reg13 & sub C
01010011 -- save reg13 & reset CX if NZ
00100010 -- set C load reg02 & sub C
11010010 -- save reg12 if CX
00100011 -- load reg03 & reset CX if NZ
11010011 -- save reg13 if CX
00101001 -- load reg09
01100010 -- set AY_OUT2
00010100 -- set C,CX load reg14 & sub C
01010100 -- save reg14 & reset CX if NZ
10110101 -- load reg15 & sub C
01010101 -- save reg15 & reset CX if NZ
00100100 -- set C load reg04 & sub C
11010100 -- save reg14 if CX
00100101 -- load reg05 & reset CX if NZ
11010101 -- save reg15 if CX
00101010 -- load reg0A
01100011 -- set AY_OUT3
00010111 -- set C,CX load reg17 & dec 1
01010111 -- save reg17 & reset CX if NZ
00100110 -- load reg06 dec 1 ***********
11010111 -- save reg17 if CX
01100100 -- set AY_SH
00000000 -- NOP
00011000 -- set C,CX load reg18 & sub C
01011000 -- save reg18 & reset CX if NZ
10111001 -- load reg19 & sub C
01011001 -- save reg19 & reset CX if NZ
00101011 -- load reg0B & sub 1
11011000 -- save reg18 if CX
00101100 -- load reg0C & sub C
11011001 -- save reg19 if CX
01100101 -- set FORM_CLK
11100000 -- set CX = AY_F_RES
-- 00101011 -- load reg0B & sub 1
-- 11011000 -- save reg18 if CX
-- 00101100 -- load reg0C & sub C
-- 11011001 -- save reg19 if CX
11100001 -- set CX = /RESET
00111111 -- load reg1F - FF ***********
11000111 -- save reg07 if CX
00111110 -- load reg1E - 00 ***********
11001101 -- save reg0D if CX
11001000 -- save reg08 if CX
11001001 -- save reg09 if CX
11001010 -- save reg0a if CX
00100111 -- load reg07 ***********
01100110 -- set keys_bits
00101101 -- load reg0D ***********
01100111 -- set keys_bits SET-FORM-bits
-- 01100000 -- set AY_OUT_ALL
;
END ;

368
src/altera/acex/k30/AY.TDF
View File

@ -1,368 +0,0 @@
TITLE "AY-3-8910";
include "lpm_ram_dq";
include "lpm_add_sub";
SUBDESIGN ay
(
/RESET : INPUT;
CLK42 : INPUT; -- â ªâë 42
AY_T[8..0] : INPUT; -- ¢­¥è­¨© áç¥â稪 ⠪⮢
AY_D_WR : INPUT;
AY_A_WR : INPUT;
D[7..0] : INPUT;
DO[7..0] : OUTPUT;
AY_CH_A[3..0] : OUTPUT;
AY_CH_B[3..0] : OUTPUT;
AY_CH_C[3..0] : OUTPUT;
AY_CH_L[9..0] : OUTPUT;
AY_CH_R[9..0] : OUTPUT;
AY_CH_VAL : OUTPUT; -- chanels data valid
BEEPER : INPUT;
)
VARIABLE
BD[7..0] : DFFE;
BWR : DFFE;
AWR : DFFE;
AY_DI[7..0] : NODE;
AY_DO[7..0] : NODE;
AY_F_RES : NODE;
AY_F_R1 : NODE;
AY_ADR[7..0] : DFF;
AY_AAX[1..0] : DFF;
AY_X_[5..0] : DFFE;
AY_GF[3..0] : DFFE;
AY_OUT[3..1] : DFFE;
AY_OUTS[3..1] : NODE;
AY_CLK1 : NODE;
AY_SH[16..0] : DFFE;
AY_AA[3..0] : DFF;
AY_SH_Q : NODE;
AY_ABLK : NODE;
AY_BBLK : NODE;
AY_AINV : NODE;
AY_BINV : NODE;
AY_ADRX[7..0] : NODE;
AY_CCC[8..0] : DFF;
AY_AX[7..0] : NODE;
AY_C : DFFE;
AY_CX : DFFE;
AY_CXX : DFFE;
AY_WR : NODE;
AY_VA[3..0] : DFFE;
AY_VAR : DFFE;
AY_VX : DFFE;
AY_DAT_WR : DFF;
AY_DAT[7..0] : DFFE;
AY_DQ1[3..0] : DFFE;
AY_DQ2[3..0] : DFFE;
AY_DQ3[3..0] : DFFE;
AY_DQX[3..0] : DFFE;
AY_OUTSX : NODE;
AY_CH_MIX : DFF;
AY_AMP[3..0] : DFF;
AY_DD[7..0] : DFFE;
AY_CH_A[3..0] : DFF;
AY_CH_B[3..0] : DFF;
AY_CH_C[3..0] : DFF;
AY_CH_CS[8..0] : DFF;
AY_CH_LX[10..0] : DFFE;
AY_CH_RX[10..0] : DFFE;
-- AY_CH_L[9..0] : DFF;
-- AY_CH_R[9..0] : DFF;
AY_CH_DIR[7..0] : DFFE;
AY_OUTS1X : NODE;
AY_OUTS2X : NODE;
AY_OUTS3X : NODE;
AY_OUTS1Y : NODE;
-- AY_OUTS2Y : NODE;
AY_OUTS3Y : NODE;
BEGIN
-- ====== AY8910 III version =========
BD[].clk = CLK42;
AWR.clk = CLK42;
BWR.clk = CLK42;
BD[].ena = AY_CCC1;
BWR.ena = AY_CCC1;
AWR.ena = AY_CCC1;
BD[7..5].clrn = !((AY_ADR[3..0] == B"00X1") or -- ch 1,2
(AY_ADR[3..0] == B"0101") or -- ch 3
(AY_ADR[3..0] == B"0110") -- ch shum
);
BD4.clrn = !((AY_ADR[3..0] == B"00X1") or -- ch 1,2
(AY_ADR[3..0] == B"0101") -- ch 3
);
BD[] = D[];
AWR = AY_A_WR;
-- BWR = (AY_D_WR or !(AY_ADR[5..4] == 0));
BWR = AY_D_WR;
AY_CH_DIR[].clk = AY_D_WR;
AY_CH_DIR[].ena = (AY_ADR[] == B"XXX10000");
AY_CH_DIR[].d = D[];
AY_CH_DIR[].clrn= /RESET;
AY_CCC[].clk = CLK42;
AY_CCC[8..0].d = AY_T[];
(AY_AAX[].clk,AY_ADR[].clk) = AY_A_WR;
AY_ADR[].d = D[];
-- Write to 0D register
AY_AAX0.d = (D[3..0] == B"1101");
-- Write to AMP registers 08,09,0A
AY_AAX1.d = (D[3..0] == B"1000") or (D[3..0] == B"1001") or (D[3..0] == B"1010");
-- reset signal for form generator
-- AY_F_RES = DFF(VCC,DFF((!((AY_DO[7..5] == B"111") & AY_CCC1 & !AY_DO0) or AY_F_RES),CLK42,,),LCELL(!(AY_AAX0 or (AY_AAX1 & BD4)) or BWR),);
-- AY_F_R1 = DFF((!(AY_AAX0 or (AY_AAX1)) or BWR),CLK42,,);
AY_F_R1 = DFF((!AY_AAX0 or BWR),CLK42,,);
AY_F_RES = DFF(DFF(VCC,AY_CCC7,AY_F_R1,),AY_CCC7,AY_F_R1,);
AY_X_[].prn = VCC;
-- AY_GF[3..0].clrn = /RESET;
-- AY_GF[3..0].clk = AY_D_WR;
-- AY_GF[3..0].ena = AY_ADR[] == B"XXXX1101";
-- AY_GF[3..0].d = D[3..0];
AY_DAT_WR.clk = CLK42;
CASE AY_CCC[1..0] IS
WHEN B"00" =>
AY_AX[] = (VCC,GND,AY_CCC[7..2]); -- CMD adress
AY_WR = GND;
AY_DI[] = AY_DAT[];
AY_DAT_WR = VCC;
WHEN B"01" =>
AY_AX[] = (B"0000",AY_ADR[3..0]);
AY_WR = !BWR;
AY_DI[] = BD[];
AY_DAT_WR = VCC;
WHEN B"1X" =>
AY_AX[] = (GND,GND,GND,AY_DO[4..0]);
AY_DAT_WR = AY_DO6;
AY_WR = !LCELL(!(AY_DO[7..5] == B"010") &
!((AY_DO[7..5] == B"110") & AY_CXX));
-- !((AY_DO[7..5] == B"110") & AY_CX));
AY_DI[] = AY_DAT[];
END CASE;
AY_DD[].clk = CLK42;
AY_DD[].ena = !AY_CCC1 & !AY_CCC0;
AY_DD[] = AY_DO[];
AY_DO[] = lpm_ram_dq(AY_DI[],AY_AX[],AY_WR,CLK42,CLK42)
WITH (lpm_width=8,lpm_widthad=8,lpm_file="AY.MIF");
-- AY_CX.prn = !DFF((((AY_DO[7..5] == B"00X") & AY_CCC1) & (!AY_DO5 or AY_C)),CLK42,,);
AY_CX.prn = !DFF(((AY_DO[7..5] == B"000") & AY_CCC1),CLK42,,);
AY_CXX.prn = !DFF(((AY_DO[7..5] == B"000") & AY_CCC1),CLK42,,);
AY_C.prn = VCC;
AY_CX.clk = CLK42;
AY_CXX.clk = CLK42;
(AY_CXX.ena,AY_CX.ena) = DFF((((AY_DO[7..5] == B"010") or (AY_DO[7..5] == B"111")) & AY_CCC1),CLK42,,);
IF DFF(((AY_DO[7..5] == B"010")),CLK42,,) THEN
AY_CX = (LCELL(AY_DAT[] == 0) & AY_CX);
-- AY_CXX = (LCELL(AY_DAT[] == 0) & AY_CXX);
-- AY_CX = (LCELL(AY_DAT[] == 0) & AY_CX) or (AY_C & DFF(AY_DO0,CLK42,,));
AY_CXX = (LCELL(AY_DAT[] == 0) & AY_CXX) or (AY_C & DFF(AY_DO0,CLK42,,));
ELSE
AY_CXX = DFF(((!/RESET & AY_DO0) or (!AY_F_RES & !AY_DO0)),CLK42,,);
AY_CX = DFF(((!/RESET & AY_DO0) or (!AY_F_RES & !AY_DO0)),CLK42,,);
END IF;
(AY_C.clk,AY_DAT[].clk) = CLK42;
(AY_C.ena,AY_DAT[].ena) = !DFF(AY_DAT_WR,CLK42,,);
(AY_C,AY_DAT[]) = (GND,AY_DO[]) - (B"00000000",DFF((DFF(!AY_DO5,CLK42,,) or (AY_C & DFF(AY_DO7,CLK42,,))),CLK42,,));
AY_OUT[].clk = CLK42;
AY_AMP[].clk = CLK42;
AY_AMP[] = ((AY_DAT[3..0] or AY_DAT[4]) & (AY_AA[] or !AY_DAT[4]));
AY_DQ1[].clk = CLK42;
AY_OUTS1 = DFF(((AY_DO[7..0] == B"011XX001") & AY_CCC1),CLK42,,);
AY_OUT1.ena = AY_OUTS1;
AY_OUT1 = AY_CX xor AY_OUT1;
AY_DQ1[].ena = AY_OUTS1;
AY_DQ1[] = AY_AMP[] & LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0));
AY_DQ2[].clk = CLK42;
AY_OUTS2 = DFF(((AY_DO[7..0] == B"011XX010") & AY_CCC1),CLK42,,);
AY_OUT2.ena = AY_OUTS2;
AY_OUT2 = AY_CX xor AY_OUT2;
AY_DQ2[].ena = AY_OUTS2;
AY_DQ2[] = AY_AMP[] & LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0));
AY_DQ3[].clk = CLK42;
AY_OUTS3 = DFF(((AY_DO[7..0] == B"011XX011") & AY_CCC1),CLK42,,);
AY_OUT3.ena = AY_OUTS3;
AY_OUT3 = AY_CX xor AY_OUT3;
AY_DQ3[].ena = AY_OUTS3;
AY_DQ3[] = AY_AMP[] & LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0));
AY_OUTSX = DFF((((AY_DO[7..0] == B"011XX01X") or
(AY_DO[7..0] == B"011XX0X1")) & AY_CCC1),CLK42,,);
AY_DQX[].clk = CLK42;
AY_DQX[].ena = AY_OUTSX;
AY_DQX[] = AY_AMP[] & AY_CH_MIX;
AY_DQX[].clrn = !AY_SH_Q;
AY_DQX[].prn = (B"0010") or !DFF((AY_SH_Q & BEEPER),CLK42,,);
AY_CH_MIX.clk = CLK42;
CASE AY_DO[1..0] IS
WHEN 0,1 => AY_CH_MIX = LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0));
WHEN 2 => AY_CH_MIX = LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0));
WHEN 3 => AY_CH_MIX = LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0));
END CASE;
AY_SH_Q = DFF(((AY_DO[7..0] == B"011XX100") & AY_CCC1),CLK42,,);
AY_SH[].clk = CLK42;
AY_SH[].prn = /RESET;
AY_SH[].ena = AY_SH_Q & AY_CXX;
AY_SH[] = ((AY_SH3 xor AY_SH0),AY_SH[16..1]);
AY_VAR.clk = CLK42;
AY_VX.clk = CLK42;
AY_VA[].clk = CLK42;
(AY_VAR.clrn,AY_VA[].clrn) = AY_F_RES;
AY_VX.clrn = AY_F_RES;
(AY_VX.ena,AY_VA[].ena,AY_VAR.ena) = DFF(((AY_DO[7..0] == B"011XX101") & AY_CCC1 & !AY_BBLK & AY_CX),CLK42,,);
(AY_VX,AY_VA[],AY_VAR) = (AY_VX,AY_VA[],AY_VAR) + 1;
AY_X_[].clk = CLK42;
AY_X_[].ena = DFF(((AY_DO[7..0] == B"011XX110") & AY_CCC1),CLK42,,);
AY_X_[] = AY_DAT[5..0];
AY_GF[].clk = CLK42;
AY_GF[].ena = DFF(((AY_DO[7..0] == B"011XX111") & AY_CCC1),CLK42,,);
AY_GF[] = AY_DAT[3..0];
-- block count when 1-st period end
AY_BBLK = DFF((AY_VX & (AY_GF0 or !AY_GF3)),CLK42,,); -- VA_COUNT_STOP
-- set ALL ZERO when 1-st period end
AY_ABLK = DFF((!AY_GF3 & AY_VX),CLK42,,);
-- inverse 2-nd-s periods
AY_BINV = DFF((AY_VX & ((AY_GF[] == B"1X10") or (AY_GF == B"1X01"))),CLK42,,);
-- inverse ALL
AY_AINV = AY_GF2;
AY_AA[].clrn= VCC;
AY_AA[].clk = CLK42;
AY_AA[].d = (AY_VA[] xor AY_BINV xor !AY_AINV) & !AY_ABLK;
%
AY_AA[].clrn= VCC;
AY_AA[].prn = GND;
AY_AA[].clk = CLK42;
AY_AA[] = VCC;
%
AY_CH_A[3..0].clk = AY_CCC7;
AY_CH_B[3..0].clk = AY_CCC7;
AY_CH_C[3..0].clk = AY_CCC7;
AY_CH_A[3..0] = AY_DQ1[3..0];
AY_CH_B[3..0] = AY_DQ2[3..0];
AY_CH_C[3..0] = AY_DQ3[3..0];
DO[7..0] = AY_DD[];
AY_CH_CS[].clk = CLK42;
CASE AY_DQX[] IS
WHEN 15 => AY_CH_CS[] = 360 ;
WHEN 14 => AY_CH_CS[] = 255 ;
WHEN 13 => AY_CH_CS[] = 180 ;
WHEN 12 => AY_CH_CS[] = 127 ;
WHEN 11 => AY_CH_CS[] = 90 ;
WHEN 10 => AY_CH_CS[] = 64 ;
WHEN 9 => AY_CH_CS[] = 45 ;
WHEN 8 => AY_CH_CS[] = 32 ;
WHEN 7 => AY_CH_CS[] = 22 ;
WHEN 6 => AY_CH_CS[] = 16 ;
WHEN 5 => AY_CH_CS[] = 11 ;
WHEN 4 => AY_CH_CS[] = 8 ;
WHEN 3 => AY_CH_CS[] = 6 ;
WHEN 2 => AY_CH_CS[] = 4 ;
WHEN 1 => AY_CH_CS[] = 2 ;
WHEN 0 => AY_CH_CS[] = 0 ;
END CASE;
AY_OUTS1X = DFF(AY_OUTS1,CLK42,,);
AY_OUTS2X = DFF((AY_OUTS2 or AY_SH_Q),CLK42,,);
AY_OUTS3X = DFF(AY_OUTS3,CLK42,,);
AY_OUTS1Y = DFF(AY_OUTS1 or AY_OUTS1X,CLK42,,);
-- AY_OUTS2Y = DFF(AY_OUTS2 or AY_OUTS2X,CLK42,,);
AY_OUTS3Y = DFF(AY_OUTS3 or AY_OUTS3X,CLK42,,);
(AY_CH_LX[].clrn,AY_CH_RX[].clrn) = !DFF((AY_CCC[7..2] == 0),CLK42,,);
(AY_CH_LX[],,) = LPM_ADD_SUB (,AY_CH_LX[],(B"00",AY_CH_CS[]),,,,)
WITH(LPM_WIDTH=11,LPM_REPRESENTATION="UNSIGNED");
(AY_CH_RX[],,) = LPM_ADD_SUB (,AY_CH_RX[],(B"00",AY_CH_CS[]),,,,)
WITH (LPM_WIDTH=11,LPM_REPRESENTATION="UNSIGNED");
AY_CH_LX[].clk = CLK42;
AY_CH_RX[].clk = CLK42;
AY_CH_LX[].ena = DFF(DFF((AY_OUTS1 or AY_OUTS1Y or AY_OUTS2X or AY_OUTS2),CLK42,,),CLK42,,);
AY_CH_RX[].ena = DFF(DFF((AY_OUTS3 or AY_OUTS3Y or AY_OUTS2X or AY_OUTS2),CLK42,,),CLK42,,);
AY_CH_VAL = DFF((AY_CCC[7..2] == B"111100"),CLK42,,);
-- AY_CH_L[].clk = AY_CH_VAL;
-- AY_CH_R[].clk = AY_CH_VAL;
AY_CH_L[] = AY_CH_LX[10..1];
AY_CH_R[] = AY_CH_RX[10..1];
END;

568
src/altera/acex/k30/DCP.ACF
View File

@ -1,568 +0,0 @@
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
CHIP dcp
BEGIN
DEVICE = EP1K30FC256-3;
END;
DEFAULT_DEVICES
BEGIN
AUTO_DEVICE = EP1K100FC484-1;
AUTO_DEVICE = EP1K100FC256-1;
AUTO_DEVICE = EP1K100QC208-1;
AUTO_DEVICE = EP1K50FC484-1;
AUTO_DEVICE = EP1K50FC256-1;
AUTO_DEVICE = EP1K50QC208-1;
AUTO_DEVICE = EP1K50TC144-1;
AUTO_DEVICE = EP1K30FC256-1;
AUTO_DEVICE = EP1K30QC208-1;
AUTO_DEVICE = EP1K30TC144-1;
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;
TIMING_POINT
BEGIN
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30FC256-3;
FREQUENCY = 200MHz;
MAINTAIN_STABLE_SYNTHESIS = OFF;
CUT_ALL_CLEAR_PRESET = ON;
CUT_ALL_BIDIR = ON;
END;
IGNORED_ASSIGNMENTS
BEGIN
FIT_IGNORE_TIMING = OFF;
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
IGNORE_DEVICE_ASSIGNMENTS = OFF;
IGNORE_LC_ASSIGNMENTS = OFF;
IGNORE_PIN_ASSIGNMENTS = OFF;
IGNORE_CHIP_ASSIGNMENTS = OFF;
IGNORE_TIMING_ASSIGNMENTS = OFF;
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
END;
GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
MAX7000B_ENABLE_VREFB = OFF;
MAX7000B_ENABLE_VREFA = OFF;
MAX7000B_VCCIO_IOBANK2 = 3.3V;
MAX7000B_VCCIO_IOBANK1 = 3.3V;
CONFIG_EPROM_PULLUP_RESISTOR = ON;
CONFIG_EPROM_USER_CODE = FFFFFFFF;
FLEX_CONFIGURATION_EPROM = AUTO;
MAX7000AE_ENABLE_JTAG = ON;
MAX7000AE_USER_CODE = FFFFFFFF;
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX6000_ENABLE_JTAG = OFF;
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
MULTIVOLT_IO = OFF;
MAX7000S_ENABLE_JTAG = ON;
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
MAX7000S_USER_CODE = FFFF;
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
FLEX10K_JTAG_USER_CODE = 7F;
ENABLE_INIT_DONE_OUTPUT = OFF;
ENABLE_CHIP_WIDE_OE = OFF;
ENABLE_CHIP_WIDE_RESET = OFF;
nCEO = UNRESERVED;
CLKUSR = UNRESERVED;
ADD17 = UNRESERVED;
ADD16 = UNRESERVED;
ADD15 = UNRESERVED;
ADD14 = UNRESERVED;
ADD13 = UNRESERVED;
ADD0_TO_ADD12 = UNRESERVED;
SDOUT = RESERVED_DRIVES_OUT;
RDCLK = UNRESERVED;
RDYnBUSY = UNRESERVED;
nWS_nRS_nCS_CS = UNRESERVED;
DATA1_TO_DATA7 = UNRESERVED;
DATA0 = RESERVED_TRI_STATED;
FLEX8000_ENABLE_JTAG = OFF;
CONFIG_SCHEME = ACTIVE_SERIAL;
DISABLE_TIME_OUT = OFF;
ENABLE_DCLK_OUTPUT = OFF;
RELEASE_CLEARS = OFF;
AUTO_RESTART = OFF;
USER_CLOCK = OFF;
SECURITY_BIT = OFF;
RESERVED_PINS_PERCENT = 0;
RESERVED_LCELLS_PERCENT = 0;
END;
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
STYLE = FAST;
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
AUTO_IMPLEMENT_IN_EAB = OFF;
AUTO_OPEN_DRAIN_PINS = ON;
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
AUTO_REGISTER_PACKING = OFF;
DEVICE_FAMILY = ACEX1K;
AUTO_FAST_IO = OFF;
AUTO_GLOBAL_OE = ON;
AUTO_GLOBAL_PRESET = ON;
AUTO_GLOBAL_CLEAR = ON;
AUTO_GLOBAL_CLOCK = ON;
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
OPTIMIZE_FOR_SPEED = 5;
END;
COMPILER_PROCESSING_CONFIGURATION
BEGIN
USE_QUARTUS_FITTER = ON;
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
FITTER_SETTINGS = NORMAL;
SMART_RECOMPILE = OFF;
GENERATE_AHDL_TDO_FILE = OFF;
RPT_FILE_USER_ASSIGNMENTS = ON;
RPT_FILE_LCELL_INTERCONNECT = ON;
RPT_FILE_HIERARCHY = ON;
RPT_FILE_EQUATIONS = ON;
LINKED_SNF_EXTRACTOR = OFF;
OPTIMIZE_TIMING_SNF = OFF;
TIMING_SNF_EXTRACTOR = ON;
FUNCTIONAL_SNF_EXTRACTOR = OFF;
DESIGN_DOCTOR_RULES = EPLD;
DESIGN_DOCTOR = OFF;
END;
COMPILER_INTERFACES_CONFIGURATION
BEGIN
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
EDIF_BUS_DELIMITERS = [];
EDIF_FLATTEN_BUS = OFF;
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
EDIF_OUTPUT_USE_EDC = OFF;
EDIF_INPUT_USE_LMF2 = OFF;
EDIF_INPUT_USE_LMF1 = OFF;
EDIF_OUTPUT_GND = GND;
EDIF_OUTPUT_VCC = VCC;
EDIF_INPUT_GND = GND;
EDIF_INPUT_VCC = VCC;
EDIF_OUTPUT_EDC_FILE = *.edc;
EDIF_INPUT_LMF2 = *.lmf;
EDIF_INPUT_LMF1 = *.lmf;
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
VHDL_FLATTEN_BUS = OFF;
VERILOG_FLATTEN_BUS = OFF;
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
VHDL_WRITER_VERSION = VHDL87;
VHDL_READER_VERSION = VHDL87;
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
SYNOPSYS_DESIGNWARE = OFF;
SYNOPSYS_COMPILER = DESIGN;
USE_SYNOPSYS_SYNTHESIS = OFF;
VHDL_NETLIST_WRITER = OFF;
VERILOG_NETLIST_WRITER = OFF;
XNF_GENERATE_AHDL_TDX_FILE = ON;
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
EDIF_OUTPUT_VERSION = 200;
EDIF_NETLIST_WRITER = OFF;
END;
CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
MASTER_RESET = OFF;
EXPANDER_NETWORKS = ON;
RACE_CONDITIONS = ON;
DELAY_CHAINS = ON;
ASYNCHRONOUS_INPUTS = ON;
PRESET_CLEAR_NETWORKS = ON;
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
MULTI_CLOCK_NETWORKS = ON;
MULTI_LEVEL_CLOCKS = ON;
GATED_CLOCKS = ON;
RIPPLE_CLOCKS = ON;
END;
SIMULATOR_CONFIGURATION
BEGIN
END_TIME = 5.0us;
BIDIR_PIN = STRONG;
START_TIME = 0.0ns;
GLITCH_TIME = 0.0ns;
GLITCH = OFF;
OSCILLATION_TIME = 0.0ns;
OSCILLATION = OFF;
CHECK_OUTPUTS = OFF;
SETUP_HOLD = OFF;
USE_DEVICE = OFF;
END;
TIMING_ANALYZER_CONFIGURATION
BEGIN
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
LIST_PATH_FREQUENCY = 10MHz;
LIST_PATH_COUNT = 10;
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
INCLUDE_PATHS_LESS_THAN = OFF;
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
INCLUDE_PATHS_GREATER_THAN = OFF;
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
CELL_WIDTH = 18;
LIST_ONLY_LONGEST_PATH = ON;
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
CUT_OFF_IO_PIN_FEEDBACK = ON;
AUTO_RECALCULATE = OFF;
END;
OTHER_CONFIGURATION
BEGIN
LAST_MAXPLUS2_VERSION = 10.0;
EXPLICIT_FAMILY = 1;
ROW_PINS_LCELL_INSERT = ON;
CARRY_OUT_PINS_LCELL_INSERT = OFF;
NORMAL_LCELL_INSERT = ON;
FLEX_10K_52_COLUMNS = 40;
DEFAULT_9K_EXP_PER_LCELL = 1/2;
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
LCELLS_PER_ROW_PERCENT = 100;
FAN_IN_PER_LCELL_PERCENT = 100;
EXP_PER_LCELL_PERCENT = 100;
ROW_PINS_PERCENT = 50;
ORIGINAL_MAXPLUS2_VERSION = 9.6;
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = ON;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = AUTO;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = AUTO;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = MANUAL;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = MANUAL;
END;

27
src/altera/acex/k30/DCP.INC
View File

@ -1,27 +0,0 @@
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- MAX+plus II Include File
-- Version 10.0 9/14/2000
-- Created: Thu Feb 07 21:14:23 2002
FUNCTION dcp (clk42, /reset, ct[2..0], continue, a[15..0], di[7..0], turbo_hand, /io, /rd, /wr, /mr, /rf, /m1, md[7..0], dos, refresh, g_line[9..0], test_r, acc_on, double_cas, blk_mem)
WITH (UPDATE)
RETURNS (/res, ras, cas, mc_end, mc_begin, mc_type, mc_write, do[7..0], ma[11..0], mca[1..0], clk_z80, turbo, /wait, /iom, /iomm, ra[17..14], page[11..0], type[3..0], cs_rom, cs_ram, v_ram, port, wr_dwg, wr_tm9, wr_awg, rd_kp11, kp11_mix, ga[9..0], graf, sp_scr, sp_sa, scr128, hdd_data, hdd_flip, ram, blk_r, pn4q, dcpp[7..0]);

119
src/altera/acex/k30/DCP.MIF
View File

@ -1,119 +0,0 @@
DEPTH = 256; % Memory depth and width are required %
WIDTH = 16; % Enter a decimal number %
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless %
% otherwise specified, radixes = HEX %
-- Specify values for addresses, which can be single address or range
CONTENT
BEGIN
[0..FF] : 1000;
0 : 1040 % DCP PAGE %;
%
MA[11..0] bit0 - WG_A5
bit1 - WG_A6
bit2 - MUX_KP11, 0 - WG,CMOS 1 - KMPS,TM9
bit3 - RD/WR 0 - WRITE 1 - READ
bit4 - CS_WG93 or WR_TM9
bit5 - HDD/CMOS strobe
bit6,7 - 00 - FDD/Scr switches
01 - HDD Switch/ Reset
10 - HDD1/HDD2
11 - CMOS
bit8 - HDD CS1/CS3 or CMOS data/adr
bit9,10,11 - HDD_A[2..0]
%
10 :
7018 % RD WG93 1F,0F %
7019 % RD WG93 3F %
701A % RD WG93 5F %
701B % RD WG93 7F %
7017 % WR_PDOS FF %
701F % RD_KEYS/ WR_A20 %
7023 % Set 720 %
7027 % Set 1440 %;
-- 18 :
-- 1000 % No_function %
-- 1B : 1000; % ISA_A20 WR %
1C : 71D8 % CMOS_DAT_RD %;
1D : 70D4 % CMOS_ADR_WR %;
1E : 71D4 % CMOS_DAT_WR %;
20 :
60A8 % HD_CS1 ports %
62A8
64A8
66A8
68A8
6AA8
6CA8
6EA8
6DA8 % HD_CS3 3F6 port %
6FA8 % HD_CS3 3F7 port %
7060 % Set HDD1 %
7064 % Set HDD2 %
7120 % Set 320 Lines %
7124 % Set 312 Lines %
7160 % Soft Reset %
7164 % ??? %;
30 :
7000 % slot 1 ports %
7001 % slot 2 ports %
7002 % slot 1 mem %
7003 % slot 2 mem %
;
40 : 4000; % kb read %
52 : 3000; -- AY_D READ
58 : 5000; -- KEMPSTON-Mouse
[80..FF]: C000;
88 : 2000; -- COVOX
89 : 2000; -- COVOX-Mode
8C : 3000; -- AY_D READ
8D : 2000; -- AY_A WRITE
8E : 2000; -- AY_D WRITE
8F : 2000; -- port for ROM_WRITE
-- 80 : 7F 7F 7F 7F 7F 7F 7F 7F % KBD_DAT %;
-- 90 : 7F % PORT FF %;
90 : 3030 3031 2032 2033 2034 2035 2036 2037
2038 2039 203A 203B 203C 203D 203E 203F; % RAM PAGES %
B0 : 2020 2021 2022 2023 2024 2025 2026 2027
2028 2029 202A 202B 202C 202D 202E 202F; % RAM PAGES %
[C0..CF]: 2000 % SYS PORTS COPYES %;
D0 : 2010 2011 2012 2013 2014 2015 2016 2017
2018 2019 201A 201B 201C 201D 201E 201F; % RAM PAGES %
E0 : 2041 2041 2041 2041 2041 2041 2041 2041
2000 2005 2002 2041 20FF 2000 2000 2041; % ROM PAGES %
-- E0 : 41 42 43 44 45 46 47 48 00 05 02 E0 F0 00 00 E8; % ROM PAGES %
F0 : 2000 2001 2002 2003 2004 2005 2006 2007
2008 2009 200A 200B 200C 200D 200E 200F; % RAM PAGES %
END ;

750
src/altera/acex/k30/DCP.TDF
View File

@ -1,750 +0,0 @@
TITLE "DCP";
PARAMETERS
(
UPDATE = 1
);
INCLUDE "lpm_ram_dp";
-- INCLUDE "DC_PORT2";
SUBDESIGN dcp
(
CLK42 : INPUT;
/RESET : INPUT;
/RES : OUTPUT;
CT[2..0] : INPUT;
CONTINUE : INPUT;
RAS : OUTPUT;
CAS : OUTPUT;
MC_END : OUTPUT;
MC_BEGIN : OUTPUT;
MC_TYPE : OUTPUT;
MC_WRITE : OUTPUT;
A[15..0] : INPUT;
DI[7..0] : INPUT;
DO[7..0] : OUTPUT;
MA[11..0] : OUTPUT;
MCA[1..0] : OUTPUT;
TURBO_HAND : INPUT;
CLK_Z80 : OUTPUT;
TURBO : OUTPUT;
/IO : INPUT;
/RD : INPUT;
/WR : INPUT;
/MR : INPUT;
/RF : INPUT;
/M1 : INPUT;
/WAIT : OUTPUT;
/IOM : OUTPUT;
/IOMM : OUTPUT;
MD[7..0] : INPUT;
RA[17..14] : OUTPUT;
PAGE[11..0] : OUTPUT;
TYPE[3..0] : OUTPUT;
CS_ROM : OUTPUT;
CS_RAM : OUTPUT;
V_RAM : OUTPUT;
PORT : OUTPUT;
-- DOS : OUTPUT;
DOS : INPUT;
WR_DWG : OUTPUT;
WR_TM9 : OUTPUT;
WR_AWG : OUTPUT;
RD_KP11 : OUTPUT;
KP11_MIX : OUTPUT;
REFRESH : INPUT;
G_LINE[9..0]: INPUT;
GA[9..0] : OUTPUT;
GRAF : OUTPUT;
SP_SCR : OUTPUT;
SP_SA : OUTPUT;
SCR128 : OUTPUT;
TEST_R : INPUT;
HDD_DATA : OUTPUT;
HDD_FLIP : OUTPUT;
RAM : OUTPUT;
BLK_R : OUTPUT;
PN4Q : OUTPUT;
ACC_ON : INPUT; -- asselerator state - 1 - present
DCPP[7..0] : OUTPUT;
DOUBLE_CAS : INPUT;
BLK_MEM : INPUT;
)
VARIABLE
CLK21 : NODE;
-- DC : DC_PORT2;
CLK84 : NODE;
CLK42X : NODE;
CTZ[1..0] : DFF;
-- CT[2..0] : DFF;
MEM : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="DCP.MIF");
D[7..0] : NODE;
ADR8_MEM : NODE;
MEM_D[15..0]: NODE;
MEM_WR : NODE;
DCP_CX : NODE;
SC_LCELL : NODE;
PG3[5..0] : NODE;
PG0[5..0] : NODE;
MPGS[7..0] : LCELL;
PGS[7..0] : DFF;
-- PGS[7..0] : NODE;
PN[7..0] : DFFE;
SC[7..0] : DFFE;
SYS : DFFE;
CNF[7..0] : DFFE;
AROM16 : DFFE;
TB_SW : DFFE;
CASH_ON : NODE;
NMI_ENA : NODE;
DD[7..0] : DFFE;
STARTING : NODE;
-- DOS_ : NODE;
-- DOS : NODE;
-- DOS_ON_ : NODE;
MC_RQ : NODE;
MC_END : DFFE;
MC_BEGIN : DFFE;
MC_TYPE : DFFE;
MC_WRITE : DFFE;
RAS : DFFE;
CAS : DFFE;
MA_[11..0] : DFFE;
MCA[1..0] : DFFE;
/IOM : DFFE;
/IOMM : DFFE;
/IOMX : DFFE;
/IOMY : DFFE;
WT_CT[3..0] : DFFE;
W_TAB[3..0] : LCELL;
HDD_W[3..0] : NODE;
/IO_WAIT : NODE;
/MR_WAIT : NODE;
MEM_RW : NODE;
IO_RW : NODE;
IO_RWM : NODE;
MA_CT[1..0] : DFFE;
WR_TM9 : DFFE;
RD_KP11 : DFFE;
/RES : NODE;
RFT : DFF;
RFC : DFFE;
GRAF : DFFE;
GRAF_X : NODE;
GA[9..0] : LCELL;
SP_SCR : LCELL;
SP_SA : LCELL;
HDD_FLIP : DFFE;
/IOMZ : DFFE;
HDD_DATA : NODE;
HDD_ENA : NODE;
BLK_C : NODE;
/CASH : NODE;
DCPP[7..0] : DFFE;
PORTS_X : NODE;
NO_IO_WAIT : NODE;
DCP_RES : NODE;
HDD_A[3..0] : DFF;
X_ADR[11..0]: LCELL;
X_MA_[11..0]: LCELL;
WR_AWGX : NODE;
/IOWR : NODE;
RA[17..14] : LCELL;
-- SPR_[1..0] : NODE;
SPR_[1..0] : LCELL;
SYS_ENA : NODE;
BEGIN
%
-- DC.CLK42 = CLK42;
-- DC./RESET = /RESET;
--
-- DC.A[15..0] = A[15..0];
--
-- DC./IO = /IO;
-- DC./WR = /WR;
-- DC./M1 = /M1;
--
-- -- DC./IOM;
-- -- DC./IOMM;
-- -- DC.DCP[7..0];
--
-- DC.DOS = DOS;
-- DC.CNF[1..0]= CNF[4..3];
--
-- DC.SYS = SYS;
--
-- -- DC.PORT_X;
%
-- ==============================================================
%
-- CT[].clk = CLK42;
--
-- IF CT1 THEN
-- CT[1..0] = GND;
-- CT2 = !CT2;
-- ELSE
-- CT[1..0] = CT[1..0]+1;
-- CT2 = CT2;
-- END IF;
%
/RES = DFFE(VCC,CLK42,,,CT0);
-- ==============================================================
-- TURBO = DFFE((TB_SW & TURBO_HAND),CLK42,,/RESET,CLK_Z80);
TURBO = DFF(DFFE((TB_SW & TURBO_HAND),CLK_Z80,,/RESET,!/RF),CLK42,,);
CLK84 = CLK42 xor LCELL(CLK42X);
CLK42X = DFF(!CLK42X,CLK84,,);
CTZ[].clk = CLK84 xor CTZ1;
CTZ[] = CTZ[]+1;
-- CLK_Z80 = CTZ1;
-- CLK_Z80 = DFF((!CLK21 & TURBO) or (TFF((CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,);
-- CLK_Z80 = DFF((CLK21 & TURBO) or (TFF((CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,);
CLK_Z80 = DFF((CLK21 & TURBO) or (TFF((!CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,);
-- CLK_Z80 = DFF((!CLK21 & TURBO) or (TFF((!CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,);
-- ==============================================================
CLK21 = DFF((!CT0 xor CT2),CLK42,,);
-- === Adress Multiplexer =======================================
MA_[].clk = CLK42;
-- MA_[].ena = (CT2 xor CT0);
MA_[].ena = CLK21;
WR_TM9.clk = CLK42;
-- WR_TM9.ena = (CT2 xor CT0);
WR_TM9.ena = CLK21;
WR_TM9.prn = /RES;
RD_KP11.clk = !CLK42;
-- RD_KP11.ena = (CT2 xor CT0);
RD_KP11.ena = CLK21;
RD_KP11.prn = /RES;
RD_KP11.d = !(MA_CT[] == 0);
-- WR_AWGX = DFF((WR_TM9 or CLK21),!CLK42,,);
WR_AWGX = DFF(GND,!WR_TM9,,DFF(WR_AWGX,CLK42,,));
-- WR_TM9 = (!MA_CT1 or (!IO_RW & !PORTS_X));
WR_TM9 = (!MA_CT1 or (!/IO & !PORTS_X));
WR_AWG = WR_AWGX;
KP11_MIX = TFF(VCC,RD_KP11,,);
WR_DWG = !MC_BEGIN;
-- WR_DWG = DFF(!MC_BEGIN,CLK42,,);
-- WR_DWG = LCELL(!MC_BEGIN);
-- MA_CT[].ena = (CT2 xor CT0);
MA_CT[].ena = CLK21;
MA_CT[].clk = CLK42;
IF !LCELL(CT2 & !CT1) THEN
MA_CT[] = MA_CT[]+1;
ELSE
MA_CT[] = GND;
END IF;
%
-- MA_[11..0] bit0 - WG_A5
-- bit1 - WG_A6
-- bit2 - MUX_KP11, 0 - WG,CMOS 1 - KMPS,TM9
-- bit3 - RD/WR 0 - WRITE 1 - READ
-- bit4 - CS_WG93 or WR_TM9
-- bit5 - HDD/CMOS strobe
-- bit7,6 - 00 - not
-- 01 - ????
-- 10 - HDD1/2
-- 11 - CMOS
-- bit8 - HDD CS1/CS3 or CMOS data/adr
-- bit9,10,11 - HDD_A[2..0]
%
CASE A[15..14] IS
WHEN 0 => SP_SCR = GND; SP_SA = GND;
WHEN 1 => SP_SCR = !GRAF; SP_SA = GND;
WHEN 2 => SP_SCR = GND; SP_SA = PG3[1];
WHEN 3 => SP_SCR = !GRAF & LCELL(PG3[] == B"1101X1"); SP_SA = PG3[1];
END CASE;
CASE GRAF IS
WHEN 0 => GA[] = (GND,GND,MEM.q[3..0],A[13..10]);
-- WHEN 1 => GA[] = (VCC,(G_LINE[8..0] + (B"00000",A[13..10])));
WHEN 1 => GA[] = (VCC,G_LINE[8..0]);
END CASE;
CASE (IO_RW,MA_CT0) IS
WHEN 0 => X_ADR[] = (GND,CNF4,PN5,DOS,/WR,A15,A14,A[6..5],A13,A7,A[2]);
WHEN 1 => X_ADR[] = (GND,GND,CNF[4..3],B"01000000");
WHEN 2 => X_ADR[] = (GND,GA3,GA[1..0],A[9..2]);
WHEN 3 => X_ADR[] = (GND,GND,GA[3..2],MEM.q[7..4],GA[7..4]);
END CASE;
CASE IO_RW IS
WHEN 0 => X_MA_[] = (HDD_A[2..0],MEM.q[8..6],((MEM.q[5..4]) & (!/IOMZ,!/IOMY)),/WR,MEM.q2,A[6..5]);
WHEN 1 => X_MA_[] = (HDD_A[2..0],B"00000",/WR,VCC,A[6..5]);
END CASE;
%
-- CASE MA_CT1 IS
---- WHEN 0 => MA_[] = X_ADR[];
-- WHEN 0 => MA_[] = (GND,X_ADR[10..0]);
-- WHEN 1 => MA_[] = (HDD_A[2..0],X_MA_[8..4],/WR,X_MA_[3],A[6..5]);
-- END CASE;
%
CASE (IO_RW,MA_CT1) IS
WHEN B"00" =>
MA_[] = (X_ADR[11..0]);
WHEN B"01" =>
MA_[] = (HDD_A[2..0],MEM.q[8..6],((MEM.q[5..4]) & (!/IOMZ,!/IOMY)),/WR,MEM.q2,A[6..5]);
WHEN B"10" =>
MA_[] = (X_ADR[11..0]);
WHEN B"11" =>
MA_[] = (HDD_A[2..0],B"00000",/WR,VCC,A[6..5]);
END CASE;
MA[] = MA_[];
MCA[].ena = CT2 & CT1;
MCA[].clk = CLK42;
MCA[] = A[1..0]; -- adress for CAS
HDD_A[].clk = CLK42;
CASE (A[14],A[2..0]) IS
WHEN 0 => HDD_A[] = 0;
WHEN 1 => HDD_A[] = 1;
WHEN 2 => HDD_A[] = 2;
WHEN 3 => HDD_A[] = 3;
WHEN 4 => HDD_A[] = 4;
WHEN 5 => HDD_A[] = 5;
WHEN 6 => HDD_A[] = 0;
WHEN 7 => HDD_A[] = 0;
WHEN 8 => HDD_A[] = 0;
WHEN 9 => HDD_A[] = 0;
WHEN 10 => HDD_A[] = 6;
WHEN 11 => HDD_A[] = 7;
WHEN 12 => HDD_A[] = 14;
WHEN 13 => HDD_A[] = 15;
WHEN 14 => HDD_A[] = 0;
WHEN 15 => HDD_A[] = 0;
END CASE;
-- === Memory Sinchronizer ======================================
% RF | MEM | RF
____ | | _______
/MR \__________/
| |
_____| | _______
MC_BEGIN \________/
| |__
MC_END ____________/ \_______
______ |__________
MC_TYPE \_____/
| |
RAS __ _ ___ __
\__/|\__/ | \__/
____ _ __
CAS \__/ | \__/|\__/
| |
%
-- MC_RQ = DFF(((/MR & DFF(/IO,CLK42,,)) or (/RD & /WR)),CLK42,,);
-- MC_RQ = DFF(((/MR & DFFE(GND,!CLK42,,!/IO,CT0)) or (/RD & /WR)),!CLK42,,);
-- MC_RQ = DFF((((/MR or !/RF) & DFF(/IO,CLK42,,/M1)) or (/RD & /WR)),CLK42,,);
-- MC_RQ = DFF((((/MR or !/RF) & IO_RW) or (/RD & /WR)),CLK42,,);
-- MC_RQ = DFF(((MEM_RW & IO_RW) or (/RD & /WR)),CLK42,,);
MC_RQ = DFF(((MEM_RW & DFF(DFF(IO_RW,CLK42,,!/IO),CLK42,,!/IO)) or (/RD & /WR)),!CLK42,,);
MC_BEGIN.clk= CLK42;
MC_BEGIN.ena= CT1 & CT2;
MC_BEGIN.d = MC_RQ;
MC_BEGIN.prn= !(/MR & /IO);
MC_END.clk = CLK42;
MC_END.d = VCC;
MC_END.ena = (CT0 & CT2) & !MC_BEGIN & CONTINUE & !BLK_C;
MC_END.clrn = !(/MR & /IO);
MC_TYPE.clk = CLK42;
MC_TYPE.ena = CT1 & CT2;
MC_TYPE.d = MC_RQ or MC_END;
MC_TYPE.prn = /RES;
MC_WRITE.clk= CLK42;
MC_WRITE.ena= CT1 & CT2;
MC_WRITE.d = MC_RQ or CS_RAM or /WR or MC_END;
MC_WRITE.prn= /RES;
RFT.clk = REFRESH;
RFT.d = GND;
RFT.prn = RFC;
-- RFT.prn = VCC;
RFC.clk = CLK42;
RFC.d = !MC_RQ or RFT;
-- RFC.d = !MC_RQ;
RFC.ena = CT1 & CT2;
RAS.ena = (!(CT1 or (CT0 xor MC_TYPE))) & (!MC_TYPE or !RFC);
CAS.ena = (!(CT1 or (CT0 xor !MC_TYPE))) & (!MC_TYPE or !RFC);
-- RAS.ena = (!(CT1 or (CT0 xor MC_TYPE)));
-- CAS.ena = (!(CT1 or (CT0 xor !MC_TYPE)));
RAS.clk = CLK42; CAS.clk = CLK42;
RAS.d = CT2; CAS.d = CT2 or BLK_C;
RAS.prn = /RES;
CAS.prn = /RES;
-- CAS.prn = !BLK_C;
-- /MR_WAIT = (MEM_RW or /CASH or DFF(MC_END,CLK42,!/MR,)) or (!TURBO & !ACC_ON);
-- /MR_WAIT = MC_END or LCELL(MEM_RW or /CASH or (!TURBO & !ACC_ON));
/MR_WAIT = LCELL(MC_END or MEM_RW or /CASH or (!TURBO & !ACC_ON));
-- MEM_RW = LCELL(/MR or !/RF);
-- anti gluk!
MEM_RW = DFF((!/RF or BLK_MEM),!/MR,,LCELL(MEM_RW or !/MR));
IO_RWM = DFF(!/M1,!/IO,,LCELL(IO_RW or !/IO));
IO_RW = DFF(/IO,CLK42,,/M1);
/IOMM.clk = CLK42;
-- /IOMM.ena = CT0 xor CT2;
/IOMM.ena = CLK21;
/IOMM.d = IO_RW or !MC_END or DFF((WT_CT[] == 0),CLK42,,);
/IOMM.prn = /RES;
/IOMX.clk = CLK42;
-- /IOMX.ena = CT0 xor CT2;
/IOMX.ena = CLK21;
/IOMX.d = /IOMM;
/IOMX.prn = /RES;
/IOMY.clk = CLK42;
-- /IOMY.ena = CT0 xor CT2;
/IOMY.ena = CLK21;
/IOMY.d = /IOMX or !MC_END or DFF((WT_CT[] == B"000X"),CLK42,,);
-- /IOMY.prn = /RES;
/IOMY.prn = PORTS_X;
PORTS_X = DFF(((DCPP[7..4] == B"0010") or (DCPP[7..4] == B"0001")),CLK42,,);
/IOMZ.clk = CLK42;
-- /IOMZ.ena = CT0 xor CT2;
/IOMZ.ena = CLK21;
/IOMZ.d = (A8 xor /RD) or /IOMX or !MC_END or DFF((WT_CT[] == B"000X"),CLK42,,);
/IOMZ.prn = PORTS_X;
HDD_DATA = DFF((HDD_ENA & DFF((MEM.q[11..8] == 0),CLK42,,) & PORTS_X),CLK42,,);
HDD_ENA = (MEM.q[7..5] == B"101");
HDD_FLIP.clk = /IOM;
HDD_FLIP.ena = HDD_ENA & DFF((DCPP[] == B"0010XXXX"),CLK42,,);
HDD_FLIP.d = !HDD_FLIP & (MEM.q[11..8] == 0);
HDD_FLIP.clrn = /RESET & DFF(GND,!DOUBLE_CAS,,HDD_FLIP);
/IOM.clk = CLK42;
-- /IOM.ena = CT0 xor CT2;
/IOM.ena = CLK21;
/IOM.d = (/IOMX & /IOM);
/IOM.prn = !/IO & /M1;
-- /IO_WAIT = LCELL(/IO or !/M1 or DFF(DFFE((WT_CT[] == 0),CLK42,,,CLK21),CLK42,,NO_IO_WAIT));
/IO_WAIT = LCELL(IO_RWM or DFF(DFFE((WT_CT[] == 0),CLK42,,,CLK21),CLK42,,NO_IO_WAIT));
NO_IO_WAIT = !DFF(((A[7..0] == B"111XX1XX") & !TURBO & DOS),CLK42,,);
-- NO_IO_WAIT = TURBO;
WT_CT[].clk = CLK42;
-- WT_CT[].ena = (CT2 xor CT0);
WT_CT[].ena = CLK21;
-- WT_CT[].ena = CT1;
WT_CT[].prn = MC_END;
CASE (/IOM,DFF((WT_CT[] == 0),CLK42,,)) IS
WHEN B"1X" => WT_CT[].d = W_TAB[];
WHEN B"00" => WT_CT[].d = WT_CT[]-1;
WHEN B"01" => WT_CT[].d = GND;
END CASE;
CASE (TURBO,MEM.q[14..12]) IS
WHEN 0 => W_TAB[] = 2; WHEN 8 => W_TAB[] = 2;
WHEN 1 => W_TAB[] = 2; WHEN 9 => W_TAB[] = 2;
WHEN 2 => W_TAB[] = 1; WHEN 10 => W_TAB[] = 4;
WHEN 3 => W_TAB[] = 1; WHEN 11 => W_TAB[] = 4;
WHEN 4 => W_TAB[] = 1; WHEN 12 => W_TAB[] = 7;
WHEN 5 => W_TAB[] = 2; WHEN 13 => W_TAB[] = 7;
-- WHEN 6 => W_TAB[] = 10; WHEN 14 => W_TAB[] = 10;
WHEN 6 => W_TAB[] = 7; WHEN 14 => W_TAB[] = 7;
-- WHEN 6 => W_TAB[] = 13; WHEN 14 => W_TAB[] = 13;
WHEN 7 => W_TAB[] = 10; WHEN 15 => W_TAB[] = 10;
END CASE;
CASE LCELL(MEM.q[11..8] == 0) IS
WHEN 0 => HDD_W[] = 10; -- registers wait
WHEN 1 => HDD_W[] = 4; -- datas wait
END CASE;
/WAIT = (/IO_WAIT & /MR_WAIT);
-- === Other Devicese CASHE, ISA, ROM... ===
V_RAM = PN2; -- for ORIGINAL Waits
IF UPDATE == 1 GENERATE
-- all ROM/RAM switches in main .tdf
BLK_R = SC4;
-- all cashes in main .tdf
/CASH = GND;
-- cashe dir in main .tdf
CASH_ON = GND;
ELSE GENERATE
-- for blk wait
/CASH = DFF((MEM.q[7..4] == 15),!CLK42,BLK_R,);
-- when BLK_R = 1 => Other Devices stay Active!
BLK_R = DFF( (LCELL((MEM.q7 & MEM.q6 & RAM) or
(MEM.q7 & LCELL(A14 & A15 & SC4))) &
!DFF(DFF(MC_RQ,CLK42,,!/MR),CLK42,,!/MR)),!CLK42,!/MR,);
CASH_ON = DFFE(A7,(/IO or /RD),/RESET,,DFF((DCPP[] == H"88"),CLK42,,));
END GENERATE;
RAM = !LCELL(A14 or A15 or (SC0 & SYS));
CS_ROM = LCELL(/MR or !RAM or !/RF);
CS_RAM = LCELL(/MR or RAM or !/RF);
-- ==============================================
-- graf screen enable for pages
GRAF_X = LCELL(MEM.q[7..4] == B"0101");
GRAF.clk = CLK42;
GRAF.ena = (CT0 & CT2);
GRAF.d = GRAF_X;
BLK_C = LCELL((GRAF_X xor GRAF) & !MC_TYPE);
-----------------------------------------
SCR128 = PN3;
D[] = DI[];
-- when not IO - reset DCPP!
DCP_RES = DFF((STARTING & !/IO & /M1),CLK42,,);
DCPP[].clk = CLK42;
DCPP[].ena = !DFF(MC_END,CLK42,,);
DCPP[].clrn = MC_END & DCP_RES; -- not in/out when START
DCPP[].d = MD[];
-- DD[].clk = !CLK42;
-- DD[].ena = !DFF(MC_END,!CLK42,,);
DD[].clk = CLK42;
DD[].ena = !DFF(MC_END,CLK42,,);
DD[].clrn = MC_END & DCP_RES;
CASE LCELL(MD[7..4] == 15) IS
WHEN 0 => DD[].d = MD[];
WHEN 1 => DD[].d = (VCC,VCC,PG3[]);
END CASE;
-- === Port Decoder =============================================
DCP_CX = (DCPP[] == B"1100XXXX");
SYS_ENA = DFF((DCP_CX & (DCPP[] == B"XXXXX110")),CLK42,,);
-- /IOWR = DFF((/WR or /IO),CLK42,,!/IO);
/IOWR = LCELL(/IO or /WR or !/M1);
CNF[].ena = SYS_ENA; CNF[].d = (DI[] & DI2) or (CNF[] & !DI2);
AROM16.ena = SYS_ENA; AROM16.d = (DI0 & !DI1) or (AROM16 & DI1);
TB_SW.ena = SYS_ENA; TB_SW.d = (DI0 & DI1) or (TB_SW & !DI1);
SYS.ena = SYS_ENA; SYS.d = !A6;
SC[].ena = DFF((DCP_CX & (DCPP[] == B"XXXXX000")),CLK42,,) ;SC[].d = DI[];
PN[].ena = DFF((DCP_CX & (DCPP[] == B"XXXXX001")),CLK42,,) ;PN[].d = DI[];
TB_SW.clk = /IOWR;
AROM16.clk = /IOWR;
PN[].clk = /IOWR;
SC[].clk = /IOWR;
SYS.clk = /IOWR;
CNF[].clk = /IOWR;
AROM16.clrn = /RESET;
TB_SW.prn = /RESET;
SYS.clrn = /RESET;
CNF[].clrn = /RESET;
SC[].clrn = /RESET & !CNF6; -- Scorpion-OFF
PN[5..0].clrn = /RESET & !CNF5; -- reset PN5
PN[7..6].clrn = /RESET & CNF7; -- set Pentagon-512
PN4Q = PN4;
-- ====================================
-- ********** Pages decoder ***********
-- ====================================
PG3[] = (!PN7,VCC,LCELL((SC4 & !CNF7) or (CNF7 & PN6)),PN[2..0]);
-- SC0,SC1,SYS,DOS,PN4,AROM16,CASH_ON,NMI_ENA
PG0[] = (VCC,GND,
LCELL(SC0 or !SYS or CASH_ON or !NMI_ENA),
LCELL(((AROM16 & !(SC0 & SYS)) or (CASH_ON & NMI_ENA))),
LCELL((SPR_1 & SC_LCELL) or !SYS or !NMI_ENA),
LCELL((SPR_0 & SC_LCELL) or !SYS or !NMI_ENA));
-- SC_LCELL = LCELL(!(SC0 & SYS) & !CASH_ON);
SC_LCELL = (!(SC0 & SYS) & !CASH_ON);
NMI_ENA = VCC;
SPR_[] = !SC1 & (DOS,(PN4 or !DOS)); -- expansion/dos/basic128/basic48
CASE (TEST_R,SYS) IS
WHEN B"X0" => RA[] = (!AROM16,B"000"); -- system 0/1
WHEN B"01" => RA[] = (!AROM16,GND,SPR_[]); -- expansion/dos/basic
WHEN B"11" => RA[] = (B"001",SPR_0); -- test
END CASE;
-- ====================================
CASE A[15..14] IS
WHEN 0 => MPGS[5..0] = PG0[];
WHEN 1 => MPGS[5..0] = B"101001"; %H"E9"%
WHEN 2 => MPGS[5..0] = B"101010"; %H"EA"%
WHEN 3 => MPGS[5..0] = PG3[];
END CASE;
MPGS[7..6] = VCC;
-- STARTING = DFF(GND,VCC,/RESET,(/IO or /RD));
STARTING = LCELL(/RESET & (STARTING or !(/IO or /RD)));
PGS[].clk = !CLK42;
CASE (LCELL(/IO & !(A14 & A15 & !STARTING)),MC_END) IS
WHEN B"1X" => PGS[] = (VCC,VCC,MPGS[5..0]);
WHEN B"01" => PGS[] = DD[];
WHEN B"00" => PGS[] = GND;
END CASE;
MEM_WR = DFFE((DCPP[7] & DCPP[6] & STARTING & DFF(DFF((MC_END & !/WR),CLK42,,),CLK42,,)),CLK42,!/IO,,CT1);
ADR8_MEM = GND;
CASE ADR8_MEM IS
WHEN 1 => MEM_D[] = (DI[],MEM.q[7..0]); DO[] = MEM.q[15..8];
WHEN 0 => MEM_D[] = (MEM.q[15..8],DI[]); DO[] = MEM.q[7..0];
END CASE;
MEM.wren = MEM_WR;
MEM.data[] = MEM_D[];
MEM.wraddress[] = PGS[];
MEM.wrclock = CLK42;
MEM.wrclken = VCC;
MEM.rden = VCC;
MEM.rdaddress[] = PGS[];
MEM.rdclock = CLK42;
MEM.rdclken = VCC;
-- = MEM.q[];
PAGE[] = MEM.q[11..0];
TYPE[] = MEM.q[15..12];
PORT = !(MEM.q[15..12] == 0) or /IO or (/RD & /WR);
END;

568
src/altera/acex/k30/KBD.ACF
View File

@ -1,568 +0,0 @@
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
CHIP kbd
BEGIN
DEVICE = EP1K30QC208-3;
END;
DEFAULT_DEVICES
BEGIN
AUTO_DEVICE = EP1K100FC484-1;
AUTO_DEVICE = EP1K100FC256-1;
AUTO_DEVICE = EP1K100QC208-1;
AUTO_DEVICE = EP1K50FC484-1;
AUTO_DEVICE = EP1K50FC256-1;
AUTO_DEVICE = EP1K50QC208-1;
AUTO_DEVICE = EP1K50TC144-1;
AUTO_DEVICE = EP1K30FC256-1;
AUTO_DEVICE = EP1K30QC208-1;
AUTO_DEVICE = EP1K30TC144-1;
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;
TIMING_POINT
BEGIN
DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3;
FREQUENCY = 100MHz;
MAINTAIN_STABLE_SYNTHESIS = OFF;
CUT_ALL_CLEAR_PRESET = ON;
CUT_ALL_BIDIR = ON;
END;
IGNORED_ASSIGNMENTS
BEGIN
FIT_IGNORE_TIMING = OFF;
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
IGNORE_DEVICE_ASSIGNMENTS = OFF;
IGNORE_LC_ASSIGNMENTS = OFF;
IGNORE_PIN_ASSIGNMENTS = OFF;
IGNORE_CHIP_ASSIGNMENTS = OFF;
IGNORE_TIMING_ASSIGNMENTS = OFF;
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
END;
GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
MAX7000B_ENABLE_VREFB = OFF;
MAX7000B_ENABLE_VREFA = OFF;
MAX7000B_VCCIO_IOBANK2 = 3.3V;
MAX7000B_VCCIO_IOBANK1 = 3.3V;
CONFIG_EPROM_PULLUP_RESISTOR = ON;
CONFIG_EPROM_USER_CODE = FFFFFFFF;
FLEX_CONFIGURATION_EPROM = AUTO;
MAX7000AE_ENABLE_JTAG = ON;
MAX7000AE_USER_CODE = FFFFFFFF;
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX6000_ENABLE_JTAG = OFF;
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
MULTIVOLT_IO = OFF;
MAX7000S_ENABLE_JTAG = ON;
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
MAX7000S_USER_CODE = FFFF;
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
FLEX10K_JTAG_USER_CODE = 7F;
ENABLE_INIT_DONE_OUTPUT = OFF;
ENABLE_CHIP_WIDE_OE = OFF;
ENABLE_CHIP_WIDE_RESET = OFF;
nCEO = UNRESERVED;
CLKUSR = UNRESERVED;
ADD17 = UNRESERVED;
ADD16 = UNRESERVED;
ADD15 = UNRESERVED;
ADD14 = UNRESERVED;
ADD13 = UNRESERVED;
ADD0_TO_ADD12 = UNRESERVED;
SDOUT = RESERVED_DRIVES_OUT;
RDCLK = UNRESERVED;
RDYnBUSY = UNRESERVED;
nWS_nRS_nCS_CS = UNRESERVED;
DATA1_TO_DATA7 = UNRESERVED;
DATA0 = RESERVED_TRI_STATED;
FLEX8000_ENABLE_JTAG = OFF;
CONFIG_SCHEME = ACTIVE_SERIAL;
DISABLE_TIME_OUT = OFF;
ENABLE_DCLK_OUTPUT = OFF;
RELEASE_CLEARS = OFF;
AUTO_RESTART = OFF;
USER_CLOCK = OFF;
SECURITY_BIT = OFF;
RESERVED_PINS_PERCENT = 0;
RESERVED_LCELLS_PERCENT = 0;
END;
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
STYLE = FAST;
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
AUTO_IMPLEMENT_IN_EAB = OFF;
AUTO_OPEN_DRAIN_PINS = ON;
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
AUTO_REGISTER_PACKING = OFF;
DEVICE_FAMILY = ACEX1K;
AUTO_FAST_IO = OFF;
AUTO_GLOBAL_OE = ON;
AUTO_GLOBAL_PRESET = ON;
AUTO_GLOBAL_CLEAR = ON;
AUTO_GLOBAL_CLOCK = ON;
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
OPTIMIZE_FOR_SPEED = 5;
END;
COMPILER_PROCESSING_CONFIGURATION
BEGIN
USE_QUARTUS_FITTER = ON;
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
FITTER_SETTINGS = NORMAL;
SMART_RECOMPILE = OFF;
GENERATE_AHDL_TDO_FILE = OFF;
RPT_FILE_USER_ASSIGNMENTS = ON;
RPT_FILE_LCELL_INTERCONNECT = ON;
RPT_FILE_HIERARCHY = ON;
RPT_FILE_EQUATIONS = ON;
LINKED_SNF_EXTRACTOR = OFF;
OPTIMIZE_TIMING_SNF = OFF;
TIMING_SNF_EXTRACTOR = ON;
FUNCTIONAL_SNF_EXTRACTOR = OFF;
DESIGN_DOCTOR_RULES = EPLD;
DESIGN_DOCTOR = OFF;
END;
COMPILER_INTERFACES_CONFIGURATION
BEGIN
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
EDIF_BUS_DELIMITERS = [];
EDIF_FLATTEN_BUS = OFF;
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
EDIF_OUTPUT_USE_EDC = OFF;
EDIF_INPUT_USE_LMF2 = OFF;
EDIF_INPUT_USE_LMF1 = OFF;
EDIF_OUTPUT_GND = GND;
EDIF_OUTPUT_VCC = VCC;
EDIF_INPUT_GND = GND;
EDIF_INPUT_VCC = VCC;
EDIF_OUTPUT_EDC_FILE = *.edc;
EDIF_INPUT_LMF2 = *.lmf;
EDIF_INPUT_LMF1 = *.lmf;
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
VHDL_FLATTEN_BUS = OFF;
VERILOG_FLATTEN_BUS = OFF;
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
VHDL_WRITER_VERSION = VHDL87;
VHDL_READER_VERSION = VHDL87;
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
SYNOPSYS_DESIGNWARE = OFF;
SYNOPSYS_COMPILER = DESIGN;
USE_SYNOPSYS_SYNTHESIS = OFF;
VHDL_NETLIST_WRITER = OFF;
VERILOG_NETLIST_WRITER = OFF;
XNF_GENERATE_AHDL_TDX_FILE = ON;
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
EDIF_OUTPUT_VERSION = 200;
EDIF_NETLIST_WRITER = OFF;
END;
CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
MASTER_RESET = OFF;
EXPANDER_NETWORKS = ON;
RACE_CONDITIONS = ON;
DELAY_CHAINS = ON;
ASYNCHRONOUS_INPUTS = ON;
PRESET_CLEAR_NETWORKS = ON;
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
MULTI_CLOCK_NETWORKS = ON;
MULTI_LEVEL_CLOCKS = ON;
GATED_CLOCKS = ON;
RIPPLE_CLOCKS = ON;
END;
SIMULATOR_CONFIGURATION
BEGIN
BIDIR_PIN = STRONG;
END_TIME = 0.0ns;
START_TIME = 0.0ns;
GLITCH_TIME = 0.0ns;
GLITCH = OFF;
OSCILLATION_TIME = 0.0ns;
OSCILLATION = OFF;
CHECK_OUTPUTS = OFF;
SETUP_HOLD = OFF;
USE_DEVICE = OFF;
END;
TIMING_ANALYZER_CONFIGURATION
BEGIN
ANALYSIS_MODE = REGISTERED_PERFORMANCE;
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
LIST_PATH_FREQUENCY = 10MHz;
LIST_PATH_COUNT = 10;
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
INCLUDE_PATHS_LESS_THAN = OFF;
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
INCLUDE_PATHS_GREATER_THAN = OFF;
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
CELL_WIDTH = 18;
LIST_ONLY_LONGEST_PATH = ON;
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
CUT_OFF_IO_PIN_FEEDBACK = ON;
AUTO_RECALCULATE = OFF;
END;
OTHER_CONFIGURATION
BEGIN
LAST_MAXPLUS2_VERSION = 10.0;
EXPLICIT_FAMILY = 1;
ROW_PINS_LCELL_INSERT = ON;
CARRY_OUT_PINS_LCELL_INSERT = OFF;
NORMAL_LCELL_INSERT = ON;
FLEX_10K_52_COLUMNS = 40;
DEFAULT_9K_EXP_PER_LCELL = 1/2;
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
LCELLS_PER_ROW_PERCENT = 100;
FAN_IN_PER_LCELL_PERCENT = 100;
EXP_PER_LCELL_PERCENT = 100;
ROW_PINS_PERCENT = 50;
ORIGINAL_MAXPLUS2_VERSION = 9.6;
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = ON;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = AUTO;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = AUTO;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = MANUAL;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = MANUAL;
END;

26
src/altera/acex/k30/KBD.INC
View File

@ -1,26 +0,0 @@
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- MAX+plus II Include File
-- Version 10.0 9/14/2000
-- Created: Thu May 03 21:43:31 2001
FUNCTION kbd (clk42, clk_k, kbd_cc, kbd_dd, /rf, /io, /iom, /m1, a[15..8], ena, int_ena)
RETURNS (kbo[7..0], kb_reset, kb_f12, kb_ctrl, kb_alt, kb_sh, int);

180
src/altera/acex/k30/KBD.TDF
View File

@ -1,180 +0,0 @@
TITLE "ZX-Keyboard";
INCLUDE "lpm_ram_dq";
SUBDESIGN kbd
(
CLK42 : INPUT; -- full sinc 42MHz
CLK_K : INPUT; -- sinc input 15KHz
KBD_CC : INPUT; -- sinc KBD
KBD_DD : INPUT; -- data KBD
/RF : INPUT; -- /rfsh
/IO : INPUT; -- /iorq
/IOM : INPUT;
/M1 : INPUT;
A[15..8] : INPUT;
KBO[7..0] : OUTPUT; -- output
KB_RESET : OUTPUT;
KB_F12 : OUTPUT;
KB_CTRL : OUTPUT;
KB_ALT : OUTPUT;
KB_SH : OUTPUT;
ENA : INPUT;
INT_ENA : INPUT;
INT : OUTPUT;
)
VARIABLE
KB_CT[2..0] : DFF;
KB_D[10..0] : DFF;
KB_OFF : DFFE;
KB_EXT : DFF;
KB_ALT : DFF;
KB_CTRL : DFF;
KB_SH : DFF;
KB_CTRL_X : NODE;
KB_ALT_X : NODE;
KB_SH_X : NODE;
KB_XXX : NODE;
KB_RESET : DFF;
RXA[1..0] : DFFE;
K_CLK : NODE;
KA[15..0] : NODE;
KB_MA[2..0] : DFF;
KB_MXA : NODE;
KDCA[2..0] : LCELL;
KDD[7..0] : DFF;
KBD[5..0] : DFF;
KD[7..0] : NODE;
KDX[5..0] : DFF;
KDXX[5..0] : DFF;
WR_KBD : NODE;
KB_OFL : NODE;
BEGIN
INT = DFF((KB_CT[] == 0),CLK42,,INT_ENA);
-- KB_CT[].clk = DFF(CLK_K,CLK42,,);
KB_CT[].clk = CLK_K;
KB_CT[].prn = DFF(KBD_CC,CLK42,,);
CASE KB_CT[] IS
WHEN 0 => KB_CT[].d = GND;
WHEN 1,2,3,4,5,6,7 => KB_CT[].d = KB_CT[] - 1;
END CASE;
KB_D[].clk = DFF(!KBD_CC,CLK42,,);
KB_D[].d = (KBD_DD,KB_D[10..1]);
KB_OFF.ena = !KB_EXT;
KB_OFF.clk = DFF((KB_CT[] == 0),CLK42,,);
KB_OFF.d = KB_D[] == B"XX11110000X";
KB_EXT.clk = DFF((KB_CT[] == 1),CLK42,,);
KB_EXT.d = KB_D[] == B"XX11100000X";
KB_CTRL.clk = !KB_CT2;
KB_ALT.clk = !KB_CT2;
KB_SH.clk = !KB_CT2;
KB_CTRL_X = LCELL(KB_D[] == B"XXXXX1X100X");
KB_ALT_X = LCELL(KB_D[] == B"XXXXX1X001X");
KB_SH_X = LCELL(KB_D[] == B"XX0X01X0XXX") &
CASCADE((KB_D[] == B"XXX1XX1X01X") or (KB_D[] == B"XXX0XX0X10X"));
KB_XXX = LCELL(KB_D[] == B"XX000X0XXXX");
CASE KB_OFF IS
WHEN 0 =>
KB_CTRL.d = (KB_CTRL_X & KB_XXX) or KB_CTRL;
KB_ALT.d = (KB_ALT_X & KB_XXX) or KB_ALT;
KB_SH.d = (KB_SH_X) or KB_SH;
WHEN 1 =>
KB_CTRL.d = !(KB_CTRL_X & KB_XXX) & KB_CTRL;
KB_ALT.d = !(KB_ALT_X & KB_XXX) & KB_ALT;
KB_SH.d = !(KB_SH_X) & KB_SH;
END CASE;
KB_F12 = DFF(!((KB_XXX & LCELL(KB_D[] == B"XXXXX0X111X")) & !KB_OFF),
!KB_CT2,,!(KB_CT[] == 1));
KB_RESET.clk = !KB_CT2;
KB_RESET.d = !(KB_ALT_X & (KB_D[] == B"XX011X0XXXX") & !KB_OFF & KB_CTRL & KB_ALT);
KB_RESET.prn = !DFF((KB_CT[] == 1),CLK42,,);
K_CLK = DFF(/RF,CLK42,,);
RXA[].ena = VCC;
RXA[].clk = K_CLK;
CASE DFF((!(KB_CT[] == B"01X") & (RXA[] == 0)),CLK42,,) IS
WHEN B"1" => RXA[] = GND;
WHEN B"0" => RXA[] = (RXA0,!RXA1);
END CASE;
CASE (DFF((/IO & (RXA[] == 0),CLK42,,)),LCELL(KDD7 & KDD6)) IS
WHEN B"0X" => KA[15..8] = (B"101",KDCA[],B"11");
WHEN B"10" => KA[15..8] = (B"110000",KDD7,KDD6);
WHEN B"11" => KA[15..8] = KB_D[8..1];
END CASE;
KB_MA[].clk = CLK42;
KB_MA[].d = KB_MA[] + 1;
KB_MA[].clrn = !DFF(/IO,CLK42,,);
KB_MXA = DFF(( (((KB_MA[] == 7) & A15) or ((KB_MA[] == 6) & A14))
or (((KB_MA[] == 5) & A13) or ((KB_MA[] == 4) & A12))
or (((KB_MA[] == 3) & A11) or ((KB_MA[] == 2) & A10))
or (((KB_MA[] == 1) & A9 ) or ((KB_MA[] == 0) & A8 ))),CLK42,,);
IF !DFF(/IO,CLK42,,) THEN
KDCA[] = KB_MA[];
ELSE
KDCA[] = KDD[5..3];
END IF;
KDD[].clk = RXA0;
KDD[].d = KD[];
KDD[7..6].prn = !KB_CT2;
KDXX[].clk = RXA0;
KDXX[].d = !((KD[2..0] == 5),(KD[2..0] == 4),
(KD[2..0] == 3),(KD[2..0] == 2),
(KD[2..0] == 1),(KD[2..0] == 0));
KDX[].clk = RXA1;
CASE KB_OFF IS
WHEN B"0" => KDX[].d = (KD[5..0] & KDXX[]);
WHEN B"1" => KDX[].d = (KD[5..0] or !KDXX[]);
END CASE;
-- ==============================
WR_KBD = K_CLK or !DFF((KB_CT[] == 2),CLK42,,) or !(RXA[] == 3);
KD[] = lpm_ram_dq((B"11",KDX[5..0]),KA[15..8],!WR_KBD,CLK42,)
WITH (lpm_width=8,lpm_widthad=8,lpm_file="KBD_INI2.MIF",
lpm_outdata="UNREGISTERED");
KBD[].clk = CLK42;
KBD[].prn = DFF(VCC,KB_MA2,(!/IO & ENA),);
-- KBD[].prn = DFF(!/IOM,CLK42,,);
KBD[].d = KBD[] & (KD[5..0] or KB_MXA);
KBO[] = (VCC,VCC,KBD[]);
END;

167
src/altera/acex/k30/KBD_INI2.MIF
View File

@ -1,167 +0,0 @@
DEPTH = 256; % Memory depth and width are required %
WIDTH = 8; % Enter a decimal number %
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
DATA_RADIX = BIN; % Enter BIN, DEC, HEX, or OCT; unless %
% otherwise specified, radixes = HEX %
-- Specify values for addresses, which can be single address or range
CONTENT
BEGIN
[0..FF] : 11111111;
0 :
11111111 % .. %
00100001 % F9 %
11111111 % .. %
00011100 % F5 %
00011010 % F3 %
00011000 % F1 %
00011001 % F2 %
11111111 % F12 %
11111111 % .. %
00100000 % F10 %
00100010 % F8 %
00100100 % F6 %
00011011 % F4 %
01011000 % Tab %
10001000 % ~` %
11111111 % .. %
11111111 % .. %
01111001 % Alt %
11000000 % Left Shift %
11111111 % .. %
11111001 % Ctrl %
11010000 % 'Q' %
11011000 % '1' %
11111111 % .. %
11111111 % .. %
11111111 % .. %
11000001 % 'Z' %
11001001 % 'S' %
11001000 % 'A' %
11010001 % 'W' %
11011001 % '2' %
01110000 % left WIN %
11111111 % .. %
11000011 % 'C' %
11000010 % 'X' %
11001010 % 'D' %
11010010 % 'E' %
11011011 % '4' %
11011010 % '3' %
10110000 % Right WIN %
11111111 % .. %
11111000 % ' ' %
11000100 % 'V' %
11001011 % 'F' %
11010100 % 'T' %
11010011 % 'R' %
11011100 % '5' %
10111000 % Right Mouse %
11111111 % .. %
11111011 % 'N' %
11111100 % 'B' %
11110100 % 'H' %
11001100 % 'G' %
11101100 % 'Y' %
11100100 % '6' %
11111111 % .. %
11111111 % .. %
11111111 % .. %
11111010 % 'M' %
11110011 % 'J' %
11101011 % 'U' %
11100011 % '7' %
11100010 % '8' %
11111111 % .. %
11111111 % .. %
10111011 % ',' %
11110010 % 'K' %
11101010 % 'I' %
11101001 % 'O' %
11100000 % '0' %
11100001 % '9' %
11111111 % .. %
11111111 % .. %
10111010 % '.' %
10000100 % '/' %
11110001 % 'L' %
10101001 % ';' %
11101000 % 'P' %
10110011 % '-' %
11111111 % .. %
11111111 % .. %
11111111 % .. %
10101000 % "'" %
11111111 % .. %
10101100 % '[' %
10110001 % '=' %
11111111 % .. %
11111111 % .. %
01011001 % Caps Lock %
11000000 % Right SHIFT %
11110000 % ENTER %
10101011 % ']' %
11111111 % .. %
10001010 % '\' %
11111111 % .. %
11111111 % .. %
11111111 % .. %
11111111 % .. %
11111111 % .. %
11111111 % .. %
11111111 % .. %
11111111 % .. %
01100000 % Back %
11111111 % .. %
11111111 % .. %
10010010 % End %
11111111 % .. %
01011100 % <- %
10010000 % Home %
11111111 % .. %
11111111 % .. %
11111111 % .. %
10010001 % ins %
01100001 % DEL %
01100100 % Dn %
10101010 % grey 5 ; ctrl + I %
01100010 % -> %
01100011 % Up %
01111000 % ESC %
00111111 % Num %
11111111 % F11 %
10110010 % G+ %
01011011 % PDn ; caps + 4 %
10110011 % G- %
10111100 % G* %
01011010 % PUp ; caps + 3 %
00000000 % Scrol Lock %
11111111 % .. %
11111111 % .. %
11111111 % .. %
11111111 % .. %
00100011 % F7 % ;
% !! DATA FOR CAPS !! %
C0 :
11111101 % Function shift %
11000000 % Left Shift %
11111001 % Ctrl %
11111111 ; % no shift %
END ;

Some files were not shown because too many files have changed in this diff Show More