mirror of
https://github.com/Tolik-Trek/Sprinter-BIOS.git
synced 2026-11-07 10:59:53 +03:00
170 lines
3.7 KiB
NASM
170 lines
3.7 KiB
NASM
;
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;**********************************;
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; ACEX Loading program ;
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;**********************************;
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MACRO Conf_loader altera_chip
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.START: DI
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LD BC,#FF*256 + Z84.SYS.Control
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XOR A ; Z84.REG.WaitState_Ctrl - register - waits
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OUT (C),A ; Z84.SYS.Control
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INC C ; LD BC,#FFEF
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LD A,4 ; Memory waits set to 1
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OUT (C),A ; Z84.SYS.Data
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DEC C ; Z84.SYS.Control
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DEC A ; LD A,3 - 3-nd register - boundaries
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OUT (C),A ; Z84.REG.Misc_Ctrl
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INC C ; cs0 enable, cs1 enable, 32-Bit CRC disable, reset output enable, Clock Divide-by-two
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OUT (C),A ; Z84.SYS.Data
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DEC C ; Z84.SYS.Control
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DEC A ; LD A,2 - Z84.REG..CS_Boundary 2-nd register - boundaries
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OUT (C),A ; Z84.SYS.Data
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INC C
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LD A,#FE ; boundaries FFFF..F000 - CS1
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OUT (C),A ; EFFF..0000 - CS0
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JR .LOOP_S1
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;**************************************
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BLOCK #38-$,#FF
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JP 0
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;**************************************
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.LOOP_S1:
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LD HL,#FEF0 ; !HARDCODE
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LD DE,.STRING
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.LOOP_S:
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LD A,(DE)
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CP (HL)
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JR NZ,.NO_CNF_RAM
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INC E
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INC L
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JR NZ,.LOOP_S ; !!!!! ¯à¨¢ï§ª ª ¤à¥áã ¢ HL
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; !TODO ã¡à âì ¢¥©âë ¤«ï ªíè ?
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LD BC,#FF*256 + Z84.SYS.Control
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LD A,Z84.REG.CS_Boundary
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OUT (C),A ; 0 register - waits
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INC C
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LD A,#F0
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OUT (C),A ; boundaries FFFF..1000 - CS1
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; ; 0FFF..0000 - CS0
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LD HL,#1000 ; !!!!! Load bitstream from Fast-RAM
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JR .NEW_SHM
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;**************************************
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BLOCK #66-$,#FF
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JP 0
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;**************************************
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.NO_CNF_RAM:
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LD HL,#0100 ; !!!!! Load bitstream from ROM
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.NEW_SHM:
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;--------------[conf check]-------------
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LD A,H ; á®åà 塞 áâ à訩 ¤à¥á ç « ª®äë,
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; ç «® ª®äë ¤®«¦® ¡ëâì á ¬« ¤è¨¬ ¤à¥á®¬ = 0
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EXX
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LD L,0
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LD H,A
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EX AF,AF'
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; ¢ HL ¤à¥á ¯¥à¢®£® ¡ ©â ª®äë
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LD DE,.Conf_header
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LD B,.Conf_header.length
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.conf_header_loop:
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LD A,(DE)
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CP (HL)
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JR NZ,.Conf_Packed
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INC DE
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INC L
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DJNZ .conf_header_loop
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;XOR A
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JR .exit_conf_check
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.Conf_Packed:
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SCF
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.exit_conf_check:
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EX AF,AF'
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EXX
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;---------------------------------------
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LD DE,#FE00 ;!HARDCODE ; !!!!! Check flag "don't erase fast-ram bitstream" - "IM"
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LD A,(#FEE0)
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CP "I"
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JR NZ,.ONES_CONFIG
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LD A,(#FEE1)
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CP "M"
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JR NZ,.ONES_CONFIG
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DEC D ; multiple config!
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.ONES_CONFIG:
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LD IY,SP2000_Loader_Flag
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;LD IX,#FFFD
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LD IX,ACEX.Config_ID.Sp2000
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.LOOP1:
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LD A,(HL)
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ex af,AF'
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ld b,1
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jr nc,.no_packed_loop
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ex af,AF'
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LD B,A ; save byte to B to check later if we worked with zero
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OR A
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JR NZ,.LOOP1A
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INC HL
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LD C,(HL) ; set counter
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jr .LOOP1A
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.no_packed_loop:
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ex af,AF'
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.LOOP1A:
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;---[Sending bits to Altera]---[v]
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DUP 7
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LD (DE),A
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RRCA
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EDUP
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LD (DE),A
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;------------------------------[^]
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INC E
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LD A,B ; was it zero?
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OR A
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JR NZ,.LOOP1E
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; it was zero so we need to decrement counter
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DEC C
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JR NZ,.LOOP1A
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; end of the counter reached
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.LOOP1E:
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INC HL
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JR .LOOP1
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.STRING: DB ACEX.RELOAD_STRING
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.Conf_header: include 'bios/Loader/bitstream_header.inc'
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.Conf_header.length EQU $-.Conf_header
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;----------------------;
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BLOCK #FE-$,#FF
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; �â®, ᪮॥ ¢á¥£®, à㤨¬¥â, â®â á ¬ë© ¡ ©â ®¯¨á â¥«ï ª®äë,
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; ª®â®àë© ¨é¥â § £àã§ç¨ª ¤«ï Sp97 ¯® áâ ஬㠤à¥áã #C090.
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; ‚®âªã« ¥£® ¢ ª®æ¥ § £àã§ç¨ª , ¬®¦¥â ¯®â®¬ ¯à¨£®¤¨âáï.
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.DEF_SYM: DW ACEX.Config_ID.Sp2000
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;------------------------------[Loader end]
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DEFINE Altera_Chip altera_chip
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LUA
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local file_path = '../Build/ACEX/'
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local file_ext = '.ACX'
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local altera_ver = sj.get_define("Altera_Chip")
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sj.insert_define("Altera_File", '"' .. file_path .. altera_ver .. file_ext .. '"')
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ENDLUA
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UNDEFINE Altera_Chip
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INCBIN Altera_File
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UNDEFINE Altera_File
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ENDM
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;
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