Analysis & Synthesis report for sp2_max
Sun Aug 28 03:30:39 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Registers Removed During Synthesis
  8. Source assignments for lpm_counter:CT_rtl_0
  9. Source assignments for lpm_counter:CTV_rtl_1
 10. Source assignments for lpm_counter:CTH_rtl_2
 11. Source assignments for lpm_add_sub:op_6|addcore:adder
 12. Source assignments for lpm_add_sub:op_6|addcore:adder|addcore:adder[0]
 13. Parameter Settings for User Entity Instance: Top-level Entity: |sp2_max
 14. Parameter Settings for Inferred Entity Instance: lpm_counter:CT_rtl_0
 15. Parameter Settings for Inferred Entity Instance: lpm_counter:CTV_rtl_1
 16. Parameter Settings for Inferred Entity Instance: lpm_counter:CTH_rtl_2
 17. Parameter Settings for Inferred Entity Instance: lpm_add_sub:op_6
 18. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                               ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Aug 28 03:30:39 2022        ;
; Quartus II Version          ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name               ; sp2_max                                      ;
; Top-level Entity Name       ; SP2_MAX                                      ;
; Family                      ; MAX7000S                                     ;
; Total macrocells            ; 74                                           ;
; Total pins                  ; 80                                           ;
+-----------------------------+----------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                   ;
+--------------------------------------------------------------+------------------+---------------+
; Option                                                       ; Setting          ; Default Value ;
+--------------------------------------------------------------+------------------+---------------+
; Device                                                       ; EPM7128STC100-10 ;               ;
; Top-level entity name                                        ; sp2_max          ; sp2_max       ;
; Family name                                                  ; MAX7000S         ; Stratix II    ;
; Use smart compilation                                        ; Off              ; Off           ;
; Create Debugging Nodes for IP Cores                          ; Off              ; Off           ;
; Preserve fewer node names                                    ; On               ; On            ;
; Disable OpenCore Plus hardware evaluation                    ; Off              ; Off           ;
; Verilog Version                                              ; Verilog_2001     ; Verilog_2001  ;
; VHDL Version                                                 ; VHDL93           ; VHDL93        ;
; State Machine Processing                                     ; Auto             ; Auto          ;
; Safe State Machine                                           ; Off              ; Off           ;
; Extract Verilog State Machines                               ; On               ; On            ;
; Extract VHDL State Machines                                  ; On               ; On            ;
; Ignore Verilog initial constructs                            ; Off              ; Off           ;
; Iteration limit for constant Verilog loops                   ; 5000             ; 5000          ;
; Iteration limit for non-constant Verilog loops               ; 250              ; 250           ;
; Add Pass-Through Logic to Inferred RAMs                      ; On               ; On            ;
; Parallel Synthesis                                           ; Off              ; Off           ;
; NOT Gate Push-Back                                           ; On               ; On            ;
; Power-Up Don't Care                                          ; On               ; On            ;
; Remove Duplicate Registers                                   ; On               ; On            ;
; Ignore CARRY Buffers                                         ; Off              ; Off           ;
; Ignore CASCADE Buffers                                       ; Off              ; Off           ;
; Ignore GLOBAL Buffers                                        ; Off              ; Off           ;
; Ignore ROW GLOBAL Buffers                                    ; Off              ; Off           ;
; Ignore LCELL Buffers                                         ; Auto             ; Auto          ;
; Ignore SOFT Buffers                                          ; Off              ; Off           ;
; Limit AHDL Integers to 32 Bits                               ; Off              ; Off           ;
; Optimization Technique                                       ; Speed            ; Speed         ;
; Allow XOR Gate Usage                                         ; On               ; On            ;
; Auto Logic Cell Insertion                                    ; On               ; On            ;
; Parallel Expander Chain Length                               ; 4                ; 4             ;
; Auto Parallel Expanders                                      ; On               ; On            ;
; Auto Open-Drain Pins                                         ; On               ; On            ;
; Auto Resource Sharing                                        ; Off              ; Off           ;
; Maximum Fan-in Per Macrocell                                 ; 100              ; 100           ;
; Use LogicLock Constraints during Resource Balancing          ; On               ; On            ;
; Ignore translate_off and synthesis_off directives            ; Off              ; Off           ;
; Show Parameter Settings Tables in Synthesis Report           ; On               ; On            ;
; HDL message level                                            ; Level2           ; Level2        ;
; Suppress Register Optimization Related Messages              ; Off              ; Off           ;
; Number of Removed Registers Reported in Synthesis Report     ; 100              ; 100           ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100              ; 100           ;
; Block Design Naming                                          ; Auto             ; Auto          ;
; Synthesis Effort                                             ; Auto             ; Auto          ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On               ; On            ;
; Analysis & Synthesis Message Level                           ; Medium           ; Medium        ;
+--------------------------------------------------------------+------------------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                               ;
+----------------------------------+-----------------+-----------------------+-------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type             ; File Name with Absolute Path                                            ;
+----------------------------------+-----------------+-----------------------+-------------------------------------------------------------------------+
; sp2_max.tdf                      ; yes             ; Auto-Found AHDL File  ; C:/Sprinter/src/altera/quartus/max/sp2_max.tdf                          ;
; lpm_counter.tdf                  ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal90.inc                    ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/aglobal90.inc           ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                      ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/addcore.inc             ;
; look_add.inc                     ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/look_add.inc            ;
; bypassff.inc                     ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                     ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/altshift.inc            ;
; alt_stratix_add_sub.inc          ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc          ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ;
; addcore.tdf                      ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/a_csnbuffer.tdf         ;
; altshift.tdf                     ; yes             ; Megafunction          ; c:/altera/90sp2/quartus/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+-----------------------+-------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 74                   ;
; Total registers      ; 57                   ;
; I/O pins             ; 80                   ;
; Shareable expanders  ; 9                    ;
; Parallel expanders   ; 3                    ;
; Maximum fan-out node ; HDD_C[2]             ;
; Maximum fan-out      ; 21                   ;
; Total fan-out        ; 434                  ;
; Average fan-out      ; 2.66                 ;
+----------------------+----------------------+


+------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                            ;
+----------------------------+------------+------+--------------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name            ; Library Name ;
+----------------------------+------------+------+--------------------------------+--------------+
; |SP2_MAX                   ; 74         ; 80   ; |SP2_MAX                       ; work         ;
;    |lpm_counter:CTH_rtl_2| ; 6          ; 0    ; |SP2_MAX|lpm_counter:CTH_rtl_2 ; work         ;
;    |lpm_counter:CTV_rtl_1| ; 9          ; 0    ; |SP2_MAX|lpm_counter:CTV_rtl_1 ; work         ;
;    |lpm_counter:CT_rtl_0|  ; 4          ; 0    ; |SP2_MAX|lpm_counter:CT_rtl_0  ; work         ;
+----------------------------+------------+------+--------------------------------+--------------+


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; CTV8M                                 ; Stuck at GND due to stuck port data_in ;
; XCT[2]                                ; Lost fanout                            ;
; Total Number of Removed Registers = 2 ;                                        ;
+---------------------------------------+----------------------------------------+


+-----------------------------------------------+
; Source assignments for lpm_counter:CT_rtl_0   ;
+---------------------------+-------+------+----+
; Assignment                ; Value ; From ; To ;
+---------------------------+-------+------+----+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -  ;
+---------------------------+-------+------+----+


+-----------------------------------------------+
; Source assignments for lpm_counter:CTV_rtl_1  ;
+---------------------------+-------+------+----+
; Assignment                ; Value ; From ; To ;
+---------------------------+-------+------+----+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -  ;
+---------------------------+-------+------+----+


+-----------------------------------------------+
; Source assignments for lpm_counter:CTH_rtl_2  ;
+---------------------------+-------+------+----+
; Assignment                ; Value ; From ; To ;
+---------------------------+-------+------+----+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -  ;
+---------------------------+-------+------+----+


+-------------------------------------------------------+
; Source assignments for lpm_add_sub:op_6|addcore:adder ;
+---------------------------+-------+------+------------+
; Assignment                ; Value ; From ; To         ;
+---------------------------+-------+------+------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -          ;
+---------------------------+-------+------+------------+


+------------------------------------------------------------------------+
; Source assignments for lpm_add_sub:op_6|addcore:adder|addcore:adder[0] ;
+---------------------------+-------+------+-----------------------------+
; Assignment                ; Value ; From ; To                          ;
+---------------------------+-------+------+-----------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103  ; -    ; -                           ;
+---------------------------+-------+------+-----------------------------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |sp2_max ;
+----------------+-----------+--------------------------------------------+
; Parameter Name ; Value     ; Type                                       ;
+----------------+-----------+--------------------------------------------+
; G_MODE         ; 1         ; Untyped                                    ;
; NUM            ; NO        ; Untyped                                    ;
; NUMBER1        ; 00100000X ; Unsigned Binary                            ;
; NUMBER2        ; 00110111X ; Unsigned Binary                            ;
; NUMBER3        ; 01001101X ; Unsigned Binary                            ;
; NUMBER4        ; 01010010X ; Unsigned Binary                            ;
; NUMBER5        ; 00100000X ; Unsigned Binary                            ;
; NUMBER6        ; 00100000X ; Unsigned Binary                            ;
; NUMBER7        ; 00100000X ; Unsigned Binary                            ;
+----------------+-----------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:CT_rtl_0 ;
+------------------------+-------------------+--------------------------+
; Parameter Name         ; Value             ; Type                     ;
+------------------------+-------------------+--------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY               ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY             ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE             ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE           ;
; LPM_WIDTH              ; 4                 ; Untyped                  ;
; LPM_DIRECTION          ; UP                ; Untyped                  ;
; LPM_MODULUS            ; 0                 ; Untyped                  ;
; LPM_AVALUE             ; UNUSED            ; Untyped                  ;
; LPM_SVALUE             ; UNUSED            ; Untyped                  ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                  ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                  ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                  ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH       ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK       ;
; CARRY_CNT_EN           ; SMART             ; Untyped                  ;
; LABWIDE_SCLR           ; ON                ; Untyped                  ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                  ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                  ;
+------------------------+-------------------+--------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:CTV_rtl_1 ;
+------------------------+-------------------+---------------------------+
; Parameter Name         ; Value             ; Type                      ;
+------------------------+-------------------+---------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE            ;
; LPM_WIDTH              ; 9                 ; Untyped                   ;
; LPM_DIRECTION          ; UP                ; Untyped                   ;
; LPM_MODULUS            ; 0                 ; Untyped                   ;
; LPM_AVALUE             ; UNUSED            ; Untyped                   ;
; LPM_SVALUE             ; UNUSED            ; Untyped                   ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                   ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                   ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                   ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH        ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK        ;
; CARRY_CNT_EN           ; SMART             ; Untyped                   ;
; LABWIDE_SCLR           ; ON                ; Untyped                   ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                   ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                   ;
+------------------------+-------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:CTH_rtl_2 ;
+------------------------+-------------------+---------------------------+
; Parameter Name         ; Value             ; Type                      ;
+------------------------+-------------------+---------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE            ;
; LPM_WIDTH              ; 6                 ; Untyped                   ;
; LPM_DIRECTION          ; UP                ; Untyped                   ;
; LPM_MODULUS            ; 0                 ; Untyped                   ;
; LPM_AVALUE             ; UNUSED            ; Untyped                   ;
; LPM_SVALUE             ; UNUSED            ; Untyped                   ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                   ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                   ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                   ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH        ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK        ;
; CARRY_CNT_EN           ; SMART             ; Untyped                   ;
; LABWIDE_SCLR           ; ON                ; Untyped                   ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                   ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                   ;
+------------------------+-------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:op_6 ;
+------------------------+-------------+----------------------------+
; Parameter Name         ; Value       ; Type                       ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH              ; 5           ; Untyped                    ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                    ;
; LPM_DIRECTION          ; ADD         ; Untyped                    ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                    ;
; LPM_PIPELINE           ; 0           ; Untyped                    ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                    ;
; REGISTERED_AT_END      ; 0           ; Untyped                    ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                    ;
; USE_CS_BUFFERS         ; 1           ; Untyped                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH         ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                    ;
; USE_WYS                ; OFF         ; Untyped                    ;
; STYLE                  ; FAST        ; Untyped                    ;
; CBXI_PARAMETER         ; add_sub_uch ; Untyped                    ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE             ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Sun Aug 28 03:30:38 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max
Warning: Using design file sp2_max.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SP2_MAX
Info: Elaborating entity "sp2_max" for the top level hierarchy
Warning: Variable or input pin "CTV8C" is defined but never used
Warning: Variable or input pin "XA" is defined but never used
Warning: Variable or input pin "VGA_IN" is defined but never used
Warning: Variable or input pin "SINC_IN" is defined but never used
Warning: Variable or input pin "XHR_RDY" is defined but never used
Warning: Variable or input pin "UNUSED65" is defined but never used
Warning: Variable or input pin "UNUSED33" is defined but never used
Warning: Variable or input pin "UNUSED1" is defined but never used
Warning: Variable or input pin "UNUSED2" is defined but never used
Warning: Variable or input pin "UNUSED5" is defined but never used
Warning: Variable or input pin "UNUSED7" is defined but never used
Warning: Variable or input pin "UNUSED22" is defined but never used
Warning: Variable or input pin "UNUSED24" is defined but never used
Warning: Variable or input pin "UNUSED27" is defined but never used
Warning: Variable or input pin "UNUSED28" is defined but never used
Warning: Variable or input pin "UNUSED49" is defined but never used
Warning: Variable or input pin "UNUSED50" is defined but never used
Warning: Variable or input pin "UNUSED53" is defined but never used
Warning: Variable or input pin "UNUSED55" is defined but never used
Warning: Variable or input pin "UNUSED63" is defined but never used
Warning: Variable or input pin "UNUSED70" is defined but never used
Warning: Variable or input pin "UNUSED72" is defined but never used
Warning: Variable or input pin "UNUSED77" is defined but never used
Warning: Variable or input pin "UNUSED78" is defined but never used
Info: Inferred 3 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "CT[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: "CTV[0]~9"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: "CTH[0]~7"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "op_6"
Info: Elaborated megafunction instantiation "lpm_counter:CT_rtl_0"
Info: Instantiated megafunction "lpm_counter:CT_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "lpm_counter:CTV_rtl_1"
Info: Instantiated megafunction "lpm_counter:CTV_rtl_1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "9"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "lpm_counter:CTH_rtl_2"
Info: Instantiated megafunction "lpm_counter:CTH_rtl_2" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "6"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "lpm_add_sub:op_6"
Info: Instantiated megafunction "lpm_add_sub:op_6" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:op_6"
Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:op_6"
Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:op_6"
Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|addcore:adder[0]", which is child of megafunction instantiation "lpm_add_sub:op_6"
Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|addcore:adder[0]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:op_6"
Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|addcore:adder[0]|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:op_6"
Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:op_6"
Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:op_6"
Info: Ignored 6 buffer(s)
    Info: Ignored 6 SOFT buffer(s)
Info: Registers with preset signals will power-up high
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "$00005"
    Warning: Node "$00006"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "BEEP" is stuck at GND
    Warning (13410): Pin "DENS_X" is stuck at VCC
    Warning (13410): Pin "HD_CS" is stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "TG42_IN" to global clock signal
    Info: Promoted clear signal driven by pin "EPM_RES" to global clear signal
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "XCT[2]" lost all its fanouts during netlist optimizations.
Warning: Design contains 25 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "XA[0]"
    Warning (15610): No output dependent on input pin "XA[1]"
    Warning (15610): No output dependent on input pin "XA[2]"
    Warning (15610): No output dependent on input pin "VGA_IN"
    Warning (15610): No output dependent on input pin "SINC_IN"
    Warning (15610): No output dependent on input pin "XHR_RDY"
    Warning (15610): No output dependent on input pin "UNUSED65"
    Warning (15610): No output dependent on input pin "UNUSED33"
    Warning (15610): No output dependent on input pin "UNUSED1"
    Warning (15610): No output dependent on input pin "UNUSED2"
    Warning (15610): No output dependent on input pin "UNUSED5"
    Warning (15610): No output dependent on input pin "UNUSED7"
    Warning (15610): No output dependent on input pin "UNUSED22"
    Warning (15610): No output dependent on input pin "UNUSED24"
    Warning (15610): No output dependent on input pin "UNUSED27"
    Warning (15610): No output dependent on input pin "UNUSED28"
    Warning (15610): No output dependent on input pin "UNUSED49"
    Warning (15610): No output dependent on input pin "UNUSED50"
    Warning (15610): No output dependent on input pin "UNUSED53"
    Warning (15610): No output dependent on input pin "UNUSED55"
    Warning (15610): No output dependent on input pin "UNUSED63"
    Warning (15610): No output dependent on input pin "UNUSED70"
    Warning (15610): No output dependent on input pin "UNUSED72"
    Warning (15610): No output dependent on input pin "UNUSED77"
    Warning (15610): No output dependent on input pin "UNUSED78"
Info: Implemented 163 device resources after synthesis - the final resource count might be different
    Info: Implemented 46 input pins
    Info: Implemented 30 output pins
    Info: Implemented 4 bidirectional pins
    Info: Implemented 74 macrocells
    Info: Implemented 9 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 58 warnings
    Info: Peak virtual memory: 229 megabytes
    Info: Processing ended: Sun Aug 28 03:30:39 2022
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


