{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:23:32 2022 " "Info: Processing started: Sun Aug 28 03:23:32 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0 -1}
{ "Warning" "WTAN_SCC_LOOP" "2 " "Warning: Found combinational loop of 2 nodes" { { "Warning" "WTAN_SCC_NODE" "RDAT_X~11 " "Warning: Node \"RDAT_X~11\"" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "RDAT_X~6 " "Warning: Node \"RDAT_X~6\"" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "TURBING~5 " "Warning: Node \"TURBING~5\"" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1}
{ "Warning" "WTAN_SCC_LOOP" "3 " "Warning: Found combinational loop of 3 nodes" { { "Warning" "WTAN_SCC_NODE" "THDD~2 " "Warning: Node \"THDD~2\"" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "NTHDD~13 " "Warning: Node \"NTHDD~13\"" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "NTHDD~11 " "Warning: Node \"NTHDD~11\"" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1}
{ "Warning" "WTAN_SCC_LOOP" "2 " "Warning: Found combinational loop of 2 nodes" { { "Warning" "WTAN_SCC_NODE" "NT320~12 " "Warning: Node \"NT320~12\"" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 426 2 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "NT320~2 " "Warning: Node \"NT320~2\"" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 426 2 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 426 2 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "TG42_IN " "Info: Assuming node \"TG42_IN\" is an undefined clock" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TG42_IN" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "STE " "Info: Assuming node \"STE\" is an undefined clock" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "STE" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "RSTB " "Info: Assuming node \"RSTB\" is an undefined clock" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "RSTB" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "WSTB " "Info: Assuming node \"WSTB\" is an undefined clock" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "WSTB" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "CT_WG1~8bal " "Info: Detected gated clock \"CT_WG1~8bal\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 304 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG1~8bal" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "STWG\[2\] " "Info: Detected ripple clock \"STWG\[2\]\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "STWG\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "STWG\[2\]~6bal " "Info: Detected gated clock \"STWG\[2\]~6bal\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "STWG\[2\]~6bal" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "CT_WG~6 " "Info: Detected gated clock \"CT_WG~6\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG~6" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "CT_WG~5 " "Info: Detected gated clock \"CT_WG~5\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG~5" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "CT_WG~4 " "Info: Detected gated clock \"CT_WG~4\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG~4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "CT_WG " "Info: Detected ripple clock \"CT_WG\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "TURBING~5 " "Info: Detected gated clock \"TURBING~5\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TURBING~5" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "FDD_1440 " "Info: Detected ripple clock \"FDD_1440\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FDD_1440" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "HDD_CLK " "Info: Detected ripple clock \"HDD_CLK\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:CT_rtl_0\|dffs\[3\] " "Info: Detected ripple clock \"lpm_counter:CT_rtl_0\|dffs\[3\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:CT_rtl_0\|dffs\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "SINC_HT " "Info: Detected ripple clock \"SINC_HT\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 123 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_HT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "SINC_VT " "Info: Detected ripple clock \"SINC_VT\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 124 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_VT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:CT_rtl_0\|dffs\[0\] " "Info: Detected ripple clock \"lpm_counter:CT_rtl_0\|dffs\[0\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:CT_rtl_0\|dffs\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~4 " "Info: Detected gated clock \"XCT\[2\]~4\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~3 " "Info: Detected gated clock \"XCT\[2\]~3\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~12 " "Info: Detected gated clock \"XCT\[2\]~12\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~12" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~11 " "Info: Detected gated clock \"XCT\[2\]~11\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~11" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "XCT\[0\] " "Info: Detected ripple clock \"XCT\[0\]\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "XCT\[1\] " "Info: Detected ripple clock \"XCT\[1\]\" as buffer" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_RESULT" "TG42_IN register /RESET register \$00051 -47.0 ns " "Info: Slack time is -47.0 ns for clock \"TG42_IN\" between source register \"/RESET\" and destination register \"\$00051\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "9.62 MHz 104.0 ns " "Info: Fmax is 9.62 MHz (period= 104.0 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-25.000 ns + Largest register register " "Info: + Largest register to register requirement is -25.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination TG42_IN 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"TG42_IN\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source TG42_IN 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"TG42_IN\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-26.000 ns + Largest " "Info: + Largest clock skew is -26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"TG42_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns \$00051 2 REG LC121 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC121; Fanout = 1; REG Node = '\$00051'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { TG42_IN $00051 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN source 27.500 ns - Longest register " "Info: - Longest clock path from clock \"TG42_IN\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 6.500 ns XCT\[2\]~4 2 COMB SEXP49 1 " "Info: 2: + IC(0.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP49; Fanout = 1; COMB Node = 'XCT\[2\]~4'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { TG42_IN XCT[2]~4 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 13.500 ns XCT\[1\] 3 REG LC56 18 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 13.500 ns; Loc. = LC56; Fanout = 18; REG Node = 'XCT\[1\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { XCT[2]~4 XCT[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 21.500 ns lpm_counter:CT_rtl_0\|dffs\[3\] 4 REG LC53 10 " "Info: 4: + IC(1.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC53; Fanout = 10; REG Node = 'lpm_counter:CT_rtl_0\|dffs\[3\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { XCT[1] lpm_counter:CT_rtl_0|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns /RESET 5 REG LC85 19 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC85; Fanout = 19; REG Node = '/RESET'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 173 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 173 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.000 ns - Longest register register " "Info: - Longest register to register delay is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns /RESET 1 REG LC85 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC85; Fanout = 19; REG Node = '/RESET'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { /RESET } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 173 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(16.000 ns) 16.000 ns THDD~2 2 COMB LOOP LC114 14 " "Info: 2: + IC(0.000 ns) + CELL(16.000 ns) = 16.000 ns; Loc. = LC114; Fanout = 14; COMB LOOP Node = 'THDD~2'" { { "Info" "ITDB_PART_OF_SCC" "NTHDD~11 LC119 " "Info: Loc. = LC119; Node \"NTHDD~11\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "THDD~2 LC114 " "Info: Loc. = LC114; Node \"THDD~2\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "NTHDD~13 LC118 " "Info: Loc. = LC118; Node \"NTHDD~13\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { /RESET THDD~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 22.000 ns \$00051 3 REG LC121 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 22.000 ns; Loc. = LC121; Fanout = 1; REG Node = '\$00051'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { THDD~2 $00051 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns ( 95.45 % ) " "Info: Total cell delay = 21.000 ns ( 95.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 4.55 % ) " "Info: Total interconnect delay = 1.000 ns ( 4.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { /RESET THDD~2 $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { /RESET {} THDD~2 {} $00051 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 16.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { /RESET THDD~2 $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { /RESET {} THDD~2 {} $00051 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 16.000ns 5.000ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'TG42_IN' 57 " "Warning: Can't achieve timing requirement Clock Setup: 'TG42_IN' along 57 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_RESULT" "STE register LR_T\[0\] register REG_P\[2\] -21.0 ns " "Info: Slack time is -21.0 ns for clock \"STE\" between source register \"LR_T\[0\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "19.23 MHz 52.0 ns " "Info: Fmax is 19.23 MHz (period= 52.0 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-15.000 ns + Largest register register " "Info: + Largest register to register requirement is -15.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination STE 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"STE\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source STE 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"STE\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-16.000 ns + Largest " "Info: + Largest clock skew is -16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE destination 27.500 ns + Shortest register " "Info: + Shortest clock path from clock \"STE\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE source 43.500 ns - Longest register " "Info: - Longest clock path from clock \"STE\" to source register is 43.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns STWG\[2\]~6bal 5 COMB LC16 3 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 37.500 ns STWG\[2\] 6 REG LC19 6 " "Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 43.500 ns LR_T\[0\] 7 REG LC10 4 " "Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.500 ns ( 90.80 % ) " "Info: Total cell delay = 39.500 ns ( 90.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 9.20 % ) " "Info: Total interconnect delay = 4.000 ns ( 9.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Longest register register " "Info: - Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LR_T\[0\] 1 REG LC10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'STE' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'STE' along 6 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_RESULT" "RSTB register LR_T\[0\] register REG_P\[2\] -21.0 ns " "Info: Slack time is -21.0 ns for clock \"RSTB\" between source register \"LR_T\[0\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "19.23 MHz 52.0 ns " "Info: Fmax is 19.23 MHz (period= 52.0 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-15.000 ns + Largest register register " "Info: + Largest register to register requirement is -15.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination RSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"RSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source RSTB 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"RSTB\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-16.000 ns + Largest " "Info: + Largest clock skew is -16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB destination 27.500 ns + Shortest register " "Info: + Shortest clock path from clock \"RSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB source 43.500 ns - Longest register " "Info: - Longest clock path from clock \"RSTB\" to source register is 43.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns STWG\[2\]~6bal 5 COMB LC16 3 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 37.500 ns STWG\[2\] 6 REG LC19 6 " "Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 43.500 ns LR_T\[0\] 7 REG LC10 4 " "Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.500 ns ( 90.80 % ) " "Info: Total cell delay = 39.500 ns ( 90.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 9.20 % ) " "Info: Total interconnect delay = 4.000 ns ( 9.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Longest register register " "Info: - Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LR_T\[0\] 1 REG LC10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'RSTB' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'RSTB' along 6 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_RESULT" "WSTB register LR_T\[0\] register REG_P\[2\] -21.0 ns " "Info: Slack time is -21.0 ns for clock \"WSTB\" between source register \"LR_T\[0\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "19.23 MHz 52.0 ns " "Info: Fmax is 19.23 MHz (period= 52.0 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-15.000 ns + Largest register register " "Info: + Largest register to register requirement is -15.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination WSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"WSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source WSTB 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"WSTB\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-16.000 ns + Largest " "Info: + Largest clock skew is -16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB destination 27.500 ns + Shortest register " "Info: + Shortest clock path from clock \"WSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB source 43.500 ns - Longest register " "Info: - Longest clock path from clock \"WSTB\" to source register is 43.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns STWG\[2\]~6bal 5 COMB LC16 3 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 37.500 ns STWG\[2\] 6 REG LC19 6 " "Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 43.500 ns LR_T\[0\] 7 REG LC10 4 " "Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.500 ns ( 90.80 % ) " "Info: Total cell delay = 39.500 ns ( 90.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 9.20 % ) " "Info: Total interconnect delay = 4.000 ns ( 9.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Longest register register " "Info: - Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LR_T\[0\] 1 REG LC10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'WSTB' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'WSTB' along 6 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "TG42_IN register FDD_1440 register \$00021 -12.2 ns " "Info: Minimum slack time is -12.2 ns for clock \"TG42_IN\" between source register \"FDD_1440\" and destination register \"\$00021\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.800 ns + Shortest register register " "Info: + Shortest register to register delay is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FDD_1440 1 REG LC91 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.800 ns) 8.800 ns RDAT_X~6 2 COMB LOOP LC21 6 " "Info: 2: + IC(0.000 ns) + CELL(8.800 ns) = 8.800 ns; Loc. = LC21; Fanout = 6; COMB LOOP Node = 'RDAT_X~6'" { { "Info" "ITDB_PART_OF_SCC" "RDAT_X~6 LC21 " "Info: Loc. = LC21; Node \"RDAT_X~6\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~6 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "RDAT_X~11 LC20 " "Info: Loc. = LC20; Node \"RDAT_X~11\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~11 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~11 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.800 ns" { FDD_1440 RDAT_X~6 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.800 ns \$00021 3 REG LC17 12 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.800 ns; Loc. = LC17; Fanout = 12; REG Node = '\$00021'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { RDAT_X~6 $00021 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 328 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.800 ns ( 93.24 % ) " "Info: Total cell delay = 13.800 ns ( 93.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 6.76 % ) " "Info: Total interconnect delay = 1.000 ns ( 6.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { FDD_1440 RDAT_X~6 $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { FDD_1440 {} RDAT_X~6 {} $00021 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 8.800ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "27.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 27.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination TG42_IN 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"TG42_IN\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source TG42_IN 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"TG42_IN\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "26.000 ns + Smallest " "Info: + Smallest clock skew is 26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 35.500 ns + Longest register " "Info: + Longest clock path from clock \"TG42_IN\" to destination register is 35.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 6.500 ns XCT\[2\]~4 2 COMB SEXP49 1 " "Info: 2: + IC(0.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP49; Fanout = 1; COMB Node = 'XCT\[2\]~4'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { TG42_IN XCT[2]~4 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 13.500 ns XCT\[1\] 3 REG LC56 18 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 13.500 ns; Loc. = LC56; Fanout = 18; REG Node = 'XCT\[1\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { XCT[2]~4 XCT[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 21.500 ns lpm_counter:CT_rtl_0\|dffs\[0\] 4 REG LC122 9 " "Info: 4: + IC(1.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC122; Fanout = 9; REG Node = 'lpm_counter:CT_rtl_0\|dffs\[0\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { XCT[1] lpm_counter:CT_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns CT_WG1~8bal 5 COMB LC28 7 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC28; Fanout = 7; COMB Node = 'CT_WG1~8bal'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 304 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 35.500 ns \$00021 6 REG LC17 12 " "Info: 6: + IC(1.000 ns) + CELL(5.000 ns) = 35.500 ns; Loc. = LC17; Fanout = 12; REG Node = '\$00021'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG1~8bal $00021 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 328 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "32.500 ns ( 91.55 % ) " "Info: Total cell delay = 32.500 ns ( 91.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 8.45 % ) " "Info: Total interconnect delay = 3.000 ns ( 8.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN source 9.500 ns - Shortest register " "Info: - Shortest clock path from clock \"TG42_IN\" to source register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns HDD_CLK 2 REG LC88 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TG42_IN HDD_CLK } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns FDD_1440 3 REG LC91 13 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { HDD_CLK FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 328 9 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { FDD_1440 RDAT_X~6 $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { FDD_1440 {} RDAT_X~6 {} $00021 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 8.800ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "TG42_IN 48 " "Warning: Can't achieve minimum setup and hold requirement TG42_IN along 48 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "STE register REG_P\[1\] register REG_P\[2\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"STE\" between source register \"REG_P\[1\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_P\[1\] 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination STE 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"STE\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source STE 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"STE\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE destination 27.500 ns + Longest register " "Info: + Longest clock path from clock \"STE\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE source 27.500 ns - Shortest register " "Info: - Shortest clock path from clock \"STE\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[1\] 5 REG LC2 3 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "RSTB register REG_P\[1\] register REG_P\[2\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"RSTB\" between source register \"REG_P\[1\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_P\[1\] 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination RSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"RSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source RSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"RSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB destination 27.500 ns + Longest register " "Info: + Longest clock path from clock \"RSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB source 27.500 ns - Shortest register " "Info: - Shortest clock path from clock \"RSTB\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[1\] 5 REG LC2 3 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "WSTB register REG_P\[1\] register REG_P\[2\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"WSTB\" between source register \"REG_P\[1\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_P\[1\] 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination WSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"WSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source WSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"WSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB destination 27.500 ns + Longest register " "Info: + Longest clock path from clock \"WSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB source 27.500 ns - Shortest register " "Info: - Shortest clock path from clock \"WSTB\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[1\] 5 REG LC2 3 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "\$00052 FDD_C\[2\] TG42_IN 23.800 ns register " "Info: tsu for register \"\$00052\" (data pin = \"FDD_C\[2\]\", clock pin = \"TG42_IN\") is 23.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.300 ns + Longest pin register " "Info: + Longest pin to register delay is 23.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns FDD_C\[2\] 1 PIN PIN_46 20 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_46; Fanout = 20; PIN Node = 'FDD_C\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FDD_C[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 59 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(16.800 ns) 17.300 ns NTHDD~11 2 COMB LOOP LC119 10 " "Info: 2: + IC(0.000 ns) + CELL(16.800 ns) = 17.300 ns; Loc. = LC119; Fanout = 10; COMB LOOP Node = 'NTHDD~11'" { { "Info" "ITDB_PART_OF_SCC" "NTHDD~11 LC119 " "Info: Loc. = LC119; Node \"NTHDD~11\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "THDD~2 LC114 " "Info: Loc. = LC114; Node \"THDD~2\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "NTHDD~13 LC118 " "Info: Loc. = LC118; Node \"NTHDD~13\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "16.800 ns" { FDD_C[2] NTHDD~11 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 23.300 ns \$00052 3 REG LC123 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 23.300 ns; Loc. = LC123; Fanout = 1; REG Node = '\$00052'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { NTHDD~11 $00052 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "22.300 ns ( 95.71 % ) " "Info: Total cell delay = 22.300 ns ( 95.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 4.29 % ) " "Info: Total interconnect delay = 1.000 ns ( 4.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "23.300 ns" { FDD_C[2] NTHDD~11 $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "23.300 ns" { FDD_C[2] {} FDD_C[2]~out {} NTHDD~11 {} $00052 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 16.800ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"TG42_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns \$00052 2 REG LC123 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC123; Fanout = 1; REG Node = '\$00052'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { TG42_IN $00052 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00052 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "23.300 ns" { FDD_C[2] NTHDD~11 $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "23.300 ns" { FDD_C[2] {} FDD_C[2]~out {} NTHDD~11 {} $00052 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 16.800ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00052 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "TG42_IN CLK_WG STWG\[2\] 50.000 ns register " "Info: tco from clock \"TG42_IN\" to destination pin \"CLK_WG\" through register \"STWG\[2\]\" is 50.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN source 46.500 ns + Longest register " "Info: + Longest clock path from clock \"TG42_IN\" to source register is 46.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns HDD_CLK 2 REG LC88 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TG42_IN HDD_CLK } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.500 ns FDD_1440 3 REG LC91 13 " "Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 11.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { HDD_CLK FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 19.500 ns TURBING~5 4 COMB LOOP LC32 3 " "Info: 4: + IC(0.000 ns) + CELL(8.000 ns) = 19.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { FDD_1440 TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 25.500 ns CT_WG~6 5 COMB SEXP17 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 25.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 32.500 ns CT_WG 6 REG LC26 8 " "Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 32.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 40.500 ns STWG\[2\]~6bal 7 COMB LC16 3 " "Info: 7: + IC(1.000 ns) + CELL(7.000 ns) = 40.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 46.500 ns STWG\[2\] 8 REG LC19 6 " "Info: 8: + IC(1.000 ns) + CELL(5.000 ns) = 46.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "42.500 ns ( 91.40 % ) " "Info: Total cell delay = 42.500 ns ( 91.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 8.60 % ) " "Info: Total interconnect delay = 4.000 ns ( 8.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "46.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "46.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STWG\[2\] 1 REG LC19 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_WG 2 PIN PIN_13 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'CLK_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { STWG[2] CLK_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 299 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { STWG[2] CLK_WG } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { STWG[2] {} CLK_WG {} } { 0.000ns 0.000ns } { 0.000ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "46.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "46.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { STWG[2] CLK_WG } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { STWG[2] {} CLK_WG {} } { 0.000ns 0.000ns } { 0.000ns 1.500ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "TG42_IN TG42_OUT 10.000 ns Longest " "Info: Longest tpd from source pin \"TG42_IN\" to destination pin \"TG42_OUT\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 8.500 ns \$00003~3 2 COMB LC128 1 " "Info: 2: + IC(0.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC128; Fanout = 1; COMB Node = '\$00003~3'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { TG42_IN $00003~3 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 183 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 10.000 ns TG42_OUT 3 PIN PIN_85 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 10.000 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'TG42_OUT'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { $00003~3 TG42_OUT } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 183 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 100.00 % ) " "Info: Total cell delay = 10.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { TG42_IN $00003~3 TG42_OUT } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { TG42_IN {} TG42_IN~out {} $00003~3 {} TG42_OUT {} } { 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 7.000ns 1.500ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "LR_T\[0\] SR TG42_IN 51.000 ns register " "Info: th for register \"LR_T\[0\]\" (data pin = \"SR\", clock pin = \"TG42_IN\") is 51.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 54.500 ns + Longest register " "Info: + Longest clock path from clock \"TG42_IN\" to destination register is 54.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns HDD_CLK 2 REG LC88 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TG42_IN HDD_CLK } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.500 ns FDD_1440 3 REG LC91 13 " "Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 11.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { HDD_CLK FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 19.500 ns TURBING~5 4 COMB LOOP LC32 3 " "Info: 4: + IC(0.000 ns) + CELL(8.000 ns) = 19.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { FDD_1440 TURBING~5 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 25.500 ns CT_WG~6 5 COMB SEXP17 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 25.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 32.500 ns CT_WG 6 REG LC26 8 " "Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 32.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 40.500 ns STWG\[2\]~6bal 7 COMB LC16 3 " "Info: 7: + IC(1.000 ns) + CELL(7.000 ns) = 40.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 48.500 ns STWG\[2\] 8 REG LC19 6 " "Info: 8: + IC(1.000 ns) + CELL(7.000 ns) = 48.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 54.500 ns LR_T\[0\] 9 REG LC10 4 " "Info: 9: + IC(1.000 ns) + CELL(5.000 ns) = 54.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "49.500 ns ( 90.83 % ) " "Info: Total cell delay = 49.500 ns ( 90.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns ( 9.17 % ) " "Info: Total interconnect delay = 5.000 ns ( 9.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "54.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "54.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SR 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'SR'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SR } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns LR_T\[0\] 2 REG LC10 4 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { SR LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { SR LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { SR {} SR~out {} LR_T[0] {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "54.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "54.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { SR LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { SR {} SR~out {} LR_T[0] {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Critical Warning" "WTAN_REQUIREMENTS_NOT_MET_SLOW" "" "Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details." {  } {  } 1 0 "Timing requirements for slow timing model timing analysis were not met. See Report window for details." 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 21 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:23:32 2022 " "Info: Processing ended: Sun Aug 28 03:23:32 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
