diff --git a/.gitmodules b/.gitmodules index 5c22af2..7355856 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,4 @@ [submodule "Shared_Includes"] + branch = main path = Shared_Includes url = https://github.com/Tolik-Trek/Shared_Includes.git diff --git a/Make_all.cmd b/Make_all.cmd deleted file mode 100644 index e7242d2..0000000 --- a/Make_all.cmd +++ /dev/null @@ -1,7 +0,0 @@ -@echo off - -cd src -call make_firmware.cmd -call build_firmware.cmd -cd .. - diff --git a/Shared_Includes b/Shared_Includes index 66d8b07..a0e68ce 160000 --- a/Shared_Includes +++ b/Shared_Includes @@ -1 +1 @@ -Subproject commit 66d8b070eafa4ef347e46889999d330eb9835b51 +Subproject commit a0e68ce3a19bd47537585e49bfbf5e45fab197a1 diff --git a/ZXMAK2.cmd b/ZXMAK2.cmd deleted file mode 100644 index 635c7ad..0000000 --- a/ZXMAK2.cmd +++ /dev/null @@ -1,20 +0,0 @@ -@rem COPY ROM TO EMULATOR -@rem -@echo -------------------------------------------------------[Copy to emul start] -@mkdir SPRINTER -@copy Build\_SPRIN.BIN SPRINTER\SP_304.BIN -@if errorlevel 1 goto error -@"C:\Program Files\7-Zip\7z.exe" a "Shared_Includes\Hide\Emulators\ZXMAK2\ROMS.PAK" SPRINTER\SP_304.BIN -@if errorlevel 1 goto error -@del SPRINTER\SP_304.BIN -@rmdir SPRINTER - -@goto quit - -:error -@echo ERROR during copying to emulator -@pause 0 -@exit 3 - -:quit -@echo -------------------------------------------------------[Copy to emul done] \ No newline at end of file diff --git a/__make_all_.cmd b/__make_all_.cmd deleted file mode 100644 index 5ce1d0d..0000000 --- a/__make_all_.cmd +++ /dev/null @@ -1,7 +0,0 @@ -@if [%1]==[] (set NO_STOP="3") else (set NO_STOP=%1) -@set error_level="0" -@cd src -@call make_firmware.cmd %NO_STOP% -@cd .. -@call build_firmware.cmd %NO_STOP% -@cd .. diff --git a/clean_all.cmd b/clean_all.cmd deleted file mode 100644 index 9083b37..0000000 --- a/clean_all.cmd +++ /dev/null @@ -1,13 +0,0 @@ -cd src\altera\acex -rem call clean.cmd -cd ..\..\ -cd bios\loader -call clean.cmd -cd ..\exp -call clean.cmd -cd ..\logo -call clean.cmd -cd ..\rom -call clean.cmd -pause 0 - diff --git a/copy_to_zxmak2.cmd b/copy_to_zxmak2.cmd deleted file mode 100644 index 635c7ad..0000000 --- a/copy_to_zxmak2.cmd +++ /dev/null @@ -1,20 +0,0 @@ -@rem COPY ROM TO EMULATOR -@rem -@echo -------------------------------------------------------[Copy to emul start] -@mkdir SPRINTER -@copy Build\_SPRIN.BIN SPRINTER\SP_304.BIN -@if errorlevel 1 goto error -@"C:\Program Files\7-Zip\7z.exe" a "Shared_Includes\Hide\Emulators\ZXMAK2\ROMS.PAK" SPRINTER\SP_304.BIN -@if errorlevel 1 goto error -@del SPRINTER\SP_304.BIN -@rmdir SPRINTER - -@goto quit - -:error -@echo ERROR during copying to emulator -@pause 0 -@exit 3 - -:quit -@echo -------------------------------------------------------[Copy to emul done] \ No newline at end of file diff --git a/make_and_start_emul_.cmd b/make_and_start_emul_.cmd deleted file mode 100644 index f9ec659..0000000 --- a/make_and_start_emul_.cmd +++ /dev/null @@ -1,4 +0,0 @@ -@echo off -call __make_all_vs.cmd -call copy_to_zxmak2.cmd -call start_emul.cmd diff --git a/src/ZX_ROMS/SP_128.BIN b/src/ZX_ROMS/new/SP_128.bin similarity index 98% rename from src/ZX_ROMS/SP_128.BIN rename to src/ZX_ROMS/new/SP_128.bin index df80f80..4aa5801 100644 Binary files a/src/ZX_ROMS/SP_128.BIN and b/src/ZX_ROMS/new/SP_128.bin differ diff --git a/src/ZX_ROMS/SP_TRD.BIN b/src/ZX_ROMS/new/SP_TRDOS.bin similarity index 65% rename from src/ZX_ROMS/SP_TRD.BIN rename to src/ZX_ROMS/new/SP_TRDOS.bin index 9ac3b0c..df91986 100644 Binary files a/src/ZX_ROMS/SP_TRD.BIN and b/src/ZX_ROMS/new/SP_TRDOS.bin differ diff --git a/src/ZX_ROMS/SP__48.BIN b/src/ZX_ROMS/new/SP__48.bin similarity index 99% rename from src/ZX_ROMS/SP__48.BIN rename to src/ZX_ROMS/new/SP__48.bin index 6a0b373..7ec5216 100644 Binary files a/src/ZX_ROMS/SP__48.BIN and b/src/ZX_ROMS/new/SP__48.bin differ diff --git a/src/ZX_ROMS/SP_EXP.BIN b/src/ZX_ROMS/new/ZX_EXP.bin similarity index 86% rename from src/ZX_ROMS/SP_EXP.BIN rename to src/ZX_ROMS/new/ZX_EXP.bin index 6b2a504..8116fb0 100644 Binary files a/src/ZX_ROMS/SP_EXP.BIN and b/src/ZX_ROMS/new/ZX_EXP.bin differ diff --git a/src/ZX_ROMS/SP_EXP2.BIN b/src/ZX_ROMS/new/ZX_EXP2.bin similarity index 99% rename from src/ZX_ROMS/SP_EXP2.BIN rename to src/ZX_ROMS/new/ZX_EXP2.bin index 877b42b..997d297 100644 Binary files a/src/ZX_ROMS/SP_EXP2.BIN and b/src/ZX_ROMS/new/ZX_EXP2.bin differ diff --git a/src/ZX_ROMS/sp_128.bin.hst b/src/ZX_ROMS/sp_128.bin.hst deleted file mode 100644 index e545dc5..0000000 Binary files a/src/ZX_ROMS/sp_128.bin.hst and /dev/null differ diff --git a/src/ZX_ROMS/sp__48.bin.hst b/src/ZX_ROMS/sp__48.bin.hst deleted file mode 100644 index 1e46c57..0000000 Binary files a/src/ZX_ROMS/sp__48.bin.hst and /dev/null differ diff --git a/src/ZX_ROMS/sp_exp.bin.hst b/src/ZX_ROMS/sp_exp.bin.hst deleted file mode 100644 index c707648..0000000 Binary files a/src/ZX_ROMS/sp_exp.bin.hst and /dev/null differ diff --git a/src/ZX_ROMS/sp_trd.bin.hst b/src/ZX_ROMS/sp_trd.bin.hst deleted file mode 100644 index 1606cdc..0000000 Binary files a/src/ZX_ROMS/sp_trd.bin.hst and /dev/null differ diff --git a/src/altera/acex/SP2_ACEX.sof b/src/altera/acex/SP2_ACEX.sof deleted file mode 100644 index 6cf281e..0000000 Binary files a/src/altera/acex/SP2_ACEX.sof and /dev/null differ diff --git a/src/altera/acex/SP2_ACEX.ttf b/src/altera/acex/SP2_ACEX.ttf deleted file mode 100644 index ad104a7..0000000 --- a/src/altera/acex/SP2_ACEX.ttf +++ /dev/null @@ -1,770 +0,0 @@ -255,255, 98,123, 57, 0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255, -224, 12,148,129, 50, 96, 6,202, 64, 25, 0,115, 96, 6, 76,128, 9, 50, 65, 6,200, 0, 25, 32, 3,108,128,109,144, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 32, 0, 0,132, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,152,253, - 2, 64, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0,128,128, 0, 0, 0, 0, 0, 16, 0, 0, 0, 32, 0, 4, 0, 0, 8, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,128, 48,252, - 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 8, 0, 8, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 16, 0, 73,251, - 32, 0, 0, 0, 0, 0, 0, 4, 32, 0, 0, 8, 0, 0, 0, 0, 64, 17, 0, 0, 0, 0, 1,128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 2, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0,208,255, - 10, 0, 0, 0, 0,132,128, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 32, 0, 4, 0, 0, 0, 0, 0, 0, 1, 2, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0,128, 0, 0, 0, 0, 0, 0,128, 10,251, - 8, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 64,128, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0,240,249, - 0, 0, 0,128, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 4, 8, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,248,251, - 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 64, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 1, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0,200,248, - 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 32, 0,162, 0, 0, 0, 0, 0, 2, 0, 2, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0,128, 0, 0,184,249, - 0, 0, 0, 0, 0, 0, 1, 16, 0, 0, 0, 32, 0, 4, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 32, 0, 0, 0, 64, 0, 0, 0, 40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 2, 0, 0, 16, 0, 0, 0,216,248, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 2, 2, 0, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,248,253, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 32, 0, 1, 0, 32, 1, 0, 0, 0,128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,128, 8,104,248, - 0, 64, 4, 0, 0, 0, 0, 64, 0, 8, 2, 65, 33, 0,104, 0, 8, 0, 4, 0, 0, 0, 0, 8, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,128, 4, 16,128, 16, 16, 0,200, 64, 0, 32, 1, 36,128, 4,132, 0, 16, 17, 2, 0, 0,128, 64, 0, 4, 0, 0,132, 0, 48,255, - 0, 1, 32, 0,129,192, 0, 18, 0, 2, 64, 1, 8, 0, 33, 32, 0, 0,192, 0, 24, 0,128, 64, 0, 8, 32, 1, 32, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 4, 0, 0, 20, 2, 2, 64, 0, 8, 0, 0, 32, 0, 4,128, 0, 16, 26, 2, 72, 8, 8, 0, 65, 0, 0, 96,249, - 0, 0, 0, 0, 0, 0, 0, 16, 0, 2,128, 0, 8, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 16, 2, 0, 64, 0, 8, 0, 0, 32, 0, 4,128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 48,255, - 0, 2, 0, 0, 0, 0, 1, 4,128, 0, 0, 0, 2, 0,130, 64, 0, 0, 0, 1, 32, 0, 0,128, 0, 16, 0, 2, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 1, 0, 0, 4,136, 0, 16, 0, 2, 0, 0, 8, 0, 1, 32, 0, 32, 1, 4,128, 0, 0, 0, 0, 8, 0, 32,251, - 0, 20,192, 2,120, 0, 10, 40, 1, 37, 0, 5,148, 0, 84,128, 2, 88, 0, 10, 64, 1, 44, 0, 5,160, 0, 20,128, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 22,128, 2, 74,128, 11, 40, 5, 36,160, 4,148, 0, 22, 80, 2, 74, 64, 9,192, 0, 40, 0, 7,176, 0, 22, 64, 2, 8,252, -160, 12,144, 1, 50, 97, 6,216, 0, 27, 48, 3,108,160,108,148, 1, 50, 80, 6,202, 0, 25, 40, 3,102,192, 12,152, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,192, 8,152, 1, 54, 64, 6,216, 70, 26, 96, 3,108,128, 12,176, 1, 54,192, 6,202,140, 25, 40, 19,100,128, 12,176, 1,168,253, -255,255 diff --git a/src/altera/acex/STREAM.303 b/src/altera/acex/STREAM.303 deleted file mode 100644 index 9d86203..0000000 Binary files a/src/altera/acex/STREAM.303 and /dev/null differ diff --git a/src/altera/acex/STREAM.304 b/src/altera/acex/STREAM.304 deleted file mode 100644 index a73a824..0000000 Binary files a/src/altera/acex/STREAM.304 and /dev/null differ diff --git a/src/altera/acex/STREAM.BIN b/src/altera/acex/STREAM.BIN deleted file mode 100644 index 0d2378b..0000000 Binary files a/src/altera/acex/STREAM.BIN and /dev/null differ diff --git a/src/altera/acex/STREAM.GS b/src/altera/acex/STREAM.GS deleted file mode 100644 index 456419d..0000000 Binary files a/src/altera/acex/STREAM.GS and /dev/null differ diff --git a/src/altera/acex/clean.cmd b/src/altera/acex/clean.cmd deleted file mode 100644 index 1d04c10..0000000 --- a/src/altera/acex/clean.cmd +++ /dev/null @@ -1,29 +0,0 @@ -@echo off - -del *.txt -del *.bak -del *.cnf -del *.db? - -del *.hif -del *.mmf -del *.mtf -del *.mtb -del *.hex -del *.ndb -del *.pin -del *.pof -del *.snf -del *.fit - -del *.SCF -del *.ACF -del *.TDF -del *.INC -del *.MIF - -del *.log -del *.rpt -del *.sof -del *.ttf -del *.bin diff --git a/src/altera/acex/clean_vs.cmd b/src/altera/acex/clean_vs.cmd deleted file mode 100644 index abd1354..0000000 --- a/src/altera/acex/clean_vs.cmd +++ /dev/null @@ -1,28 +0,0 @@ -@echo off - -del *.txt -del *.bak -del *.cnf -del *.db? - -del *.hif -del *.mmf -del *.mtf -del *.mtb -del *.hex -del *.ndb -del *.pin -del *.pof -del *.snf -del *.fit - -del *.SCF -del *.ACF -del *.TDF -del *.INC -del *.MIF - -del *.log -del *.rpt -del *.sof -del *.bin diff --git a/src/altera/acex/compile.log b/src/altera/acex/compile.log deleted file mode 100644 index dd7cb9a..0000000 --- a/src/altera/acex/compile.log +++ /dev/null @@ -1,4 +0,0 @@ -06.07.2022 05:20: [1/2] ALTERA ACEX-K30 STREAM -transform ttf-file to binary -Copyright (c) 2021 Sprinter Team -transform done. diff --git a/src/altera/acex/k30/ACCELER.SCF b/src/altera/acex/k30/ACCELER.SCF deleted file mode 100644 index 0cae83c..0000000 Binary files a/src/altera/acex/k30/ACCELER.SCF and /dev/null differ diff --git a/src/altera/acex/k30/DCP.MIF b/src/altera/acex/k30/DCP.MIF index d058208..aee8502 100644 --- a/src/altera/acex/k30/DCP.MIF +++ b/src/altera/acex/k30/DCP.MIF @@ -14,7 +14,7 @@ BEGIN 0 : 1040 % DCP PAGE %; % - MA[11..0] bit0 - WG_A5 + MA[11..0] bit0 - WG_A5 bit1 - WG_A6 bit2 - MUX_KP11, 0 - WG,CMOS 1 - KMPS,TM9 diff --git a/src/altera/acex/k30/DCP.SCF b/src/altera/acex/k30/DCP.SCF deleted file mode 100644 index 3012af0..0000000 Binary files a/src/altera/acex/k30/DCP.SCF and /dev/null differ diff --git a/src/altera/acex/k30/DCP.TDF b/src/altera/acex/k30/DCP.TDF index d73e33f..2a1f2cf 100644 --- a/src/altera/acex/k30/DCP.TDF +++ b/src/altera/acex/k30/DCP.TDF @@ -220,39 +220,39 @@ VARIABLE BEGIN % - DC.CLK42 = CLK42; - DC./RESET = /RESET; - - DC.A[15..0] = A[15..0]; - - DC./IO = /IO; - DC./WR = /WR; - DC./M1 = /M1; - --- DC./IOM; --- DC./IOMM; --- DC.DCP[7..0]; - - DC.DOS = DOS; - DC.CNF[1..0]= CNF[4..3]; - - DC.SYS = SYS; - --- DC.PORT_X; +-- DC.CLK42 = CLK42; +-- DC./RESET = /RESET; +-- +-- DC.A[15..0] = A[15..0]; +-- +-- DC./IO = /IO; +-- DC./WR = /WR; +-- DC./M1 = /M1; +-- +-- -- DC./IOM; +-- -- DC./IOMM; +-- -- DC.DCP[7..0]; +-- +-- DC.DOS = DOS; +-- DC.CNF[1..0]= CNF[4..3]; +-- +-- DC.SYS = SYS; +-- +-- -- DC.PORT_X; % -- ============================================================== % - CT[].clk = CLK42; - - IF CT1 THEN - CT[1..0] = GND; - CT2 = !CT2; - ELSE - CT[1..0] = CT[1..0]+1; - CT2 = CT2; - END IF; +-- CT[].clk = CLK42; +-- +-- IF CT1 THEN +-- CT[1..0] = GND; +-- CT2 = !CT2; +-- ELSE +-- CT[1..0] = CT[1..0]+1; +-- CT2 = CT2; +-- END IF; % /RES = DFFE(VCC,CLK42,,,CT0); @@ -319,18 +319,18 @@ BEGIN END IF; % - MA_[11..0] bit0 - WG_A5 - bit1 - WG_A6 - bit2 - MUX_KP11, 0 - WG,CMOS 1 - KMPS,TM9 - bit3 - RD/WR 0 - WRITE 1 - READ - bit4 - CS_WG93 or WR_TM9 - bit5 - HDD/CMOS strobe - bit7,6 - 00 - not - 01 - ???? - 10 - HDD1/2 - 11 - CMOS - bit8 - HDD CS1/CS3 or CMOS data/adr - bit9,10,11 - HDD_A[2..0] +-- MA_[11..0] bit0 - WG_A5 +-- bit1 - WG_A6 +-- bit2 - MUX_KP11, 0 - WG,CMOS 1 - KMPS,TM9 +-- bit3 - RD/WR 0 - WRITE 1 - READ +-- bit4 - CS_WG93 or WR_TM9 +-- bit5 - HDD/CMOS strobe +-- bit7,6 - 00 - not +-- 01 - ???? +-- 10 - HDD1/2 +-- 11 - CMOS +-- bit8 - HDD CS1/CS3 or CMOS data/adr +-- bit9,10,11 - HDD_A[2..0] % CASE A[15..14] IS WHEN 0 => SP_SCR = GND; SP_SA = GND; @@ -357,11 +357,11 @@ BEGIN WHEN 1 => X_MA_[] = (HDD_A[2..0],B"00000",/WR,VCC,A[6..5]); END CASE; % - CASE MA_CT1 IS --- WHEN 0 => MA_[] = X_ADR[]; - WHEN 0 => MA_[] = (GND,X_ADR[10..0]); - WHEN 1 => MA_[] = (HDD_A[2..0],X_MA_[8..4],/WR,X_MA_[3],A[6..5]); - END CASE; +-- CASE MA_CT1 IS +---- WHEN 0 => MA_[] = X_ADR[]; +-- WHEN 0 => MA_[] = (GND,X_ADR[10..0]); +-- WHEN 1 => MA_[] = (HDD_A[2..0],X_MA_[8..4],/WR,X_MA_[3],A[6..5]); +-- END CASE; % CASE (IO_RW,MA_CT1) IS @@ -667,7 +667,7 @@ END GENERATE; SC[].clrn = /RESET & !CNF6; -- Scorpion-OFF PN[5..0].clrn = /RESET & !CNF5; -- reset PN5 - PN[7..5].clrn = /RESET & CNF7; -- set Pentagon-512 + PN[7..6].clrn = /RESET & CNF7; -- set Pentagon-512 PN4Q = PN4; diff --git a/src/altera/acex/k30/MOUSE.SCF b/src/altera/acex/k30/MOUSE.SCF deleted file mode 100644 index f44bf36..0000000 Binary files a/src/altera/acex/k30/MOUSE.SCF and /dev/null differ diff --git a/src/altera/acex/k30/SP2_ACEX.SCF b/src/altera/acex/k30/SP2_ACEX.SCF deleted file mode 100644 index 8f39b4a..0000000 Binary files a/src/altera/acex/k30/SP2_ACEX.SCF and /dev/null differ diff --git a/src/altera/acex/k30/SP2_ACEX.TDF b/src/altera/acex/k30/SP2_ACEX.TDF index e46e041..dfa3d6e 100644 --- a/src/altera/acex/k30/SP2_ACEX.TDF +++ b/src/altera/acex/k30/SP2_ACEX.TDF @@ -320,7 +320,8 @@ BEGIN -- NEW 30.06.2022 -- KEYS.int_ena = ALL_MODE0; -- int in all keys -- KEYS.ena = !ALL_MODE0; -- ZX-Keyboard - KEYS.int_ena = LCELL(ALL_MODE0 & ALL_MODE3); -- new bit3 in ALL_MODE, disables keyboard interruptions w/o accellerator affected +-- new bit3 in ALL_MODE, disables keyboard interruptions w/o accellerator affected + KEYS.int_ena = LCELL(ALL_MODE0 & ALL_MODE3); KEYS.ena = VCC; -- ZX-Keyboard always enabled -- ======================================== @@ -1011,7 +1012,11 @@ END GENERATE; -- ZX_COLOR[3..0] SVIDEO.ZX_PORT[5..0] = (ACC.G_LINE[5..0]); - SVIDEO.ZX_PORT[7..6] = (DECODE.SP_SA,LCELL(DECODE.SP_SCR & !(A13 & !ACC.G_LINE7) & !ACC.G_LINE6)); +-- SVIDEO.ZX_PORT[7..6] = (DECODE.SP_SA,LCELL(DECODE.SP_SCR & !(A13 & !ACC.G_LINE7) & !ACC.G_LINE6)); + +-- NEW 25.08.2022 +-- disable zx adressing due accelerator is on + SVIDEO.ZX_PORT[7..6] = (DECODE.SP_SA,LCELL(DECODE.SP_SCR & !(A13 & !ACC.G_LINE7) & !ACC.G_LINE6 & !ALL_MODE0)); SVIDEO.DIR_PORT[0] = DECODE.SCR128; diff --git a/src/altera/acex/k30/VIDEO2.SCF b/src/altera/acex/k30/VIDEO2.SCF deleted file mode 100644 index 5f11143..0000000 Binary files a/src/altera/acex/k30/VIDEO2.SCF and /dev/null differ diff --git a/src/altera/acex/k30/VIDEO2.TDF b/src/altera/acex/k30/VIDEO2.TDF index d25114e..ea1e862 100644 --- a/src/altera/acex/k30/VIDEO2.TDF +++ b/src/altera/acex/k30/VIDEO2.TDF @@ -77,9 +77,9 @@ SUBDESIGN video2 ) VARIABLE - CLK84 : NODE; - CLK84_X : NODE; - CLK84_Y : NODE; +-- CLK84 : NODE; +-- CLK84_X : NODE; +-- CLK84_Y : NODE; ZX_COLOR[3..0] : NODE; @@ -120,11 +120,30 @@ VARIABLE V_WEM2 : NODE; V_WRM : NODE; V_WRM2 : NODE; - +% V_WEMM : NODE; V_WEMMM : NODE; V_WEMMN : NODE; V_WEMMO : NODE; +% + V_WEMM : NODE; + V_WEMMM : NODE; + V_WEMMN : NODE; + V_WEMMO : NODE; + V_WEMMP : NODE; + V_WEMMQ : NODE; + V_WEMMR : NODE; + V_WEMMS : NODE; + V_WEMMT : NODE; + V_WEMMU : NODE; + V_WEMMV : NODE; + V_WEMMW : NODE; + V_WEMMX : NODE; + V_WEMMY : NODE; + V_WEMMZ : NODE; + + + V_WET[3..0] : DFF; D_PIC0[7..0] : DFFE; @@ -143,6 +162,8 @@ VARIABLE WR_PIC : DFF; WR_COL : DFF; LD_PIC : NODE; +MXL: NODE; +MXR: NODE; RBRVA[10..8]: DFF; BRVA[7..0] : DFF; @@ -282,6 +303,7 @@ BEGIN CTV[8..0].clk = CLK42; CT[2..0].ena = VCC; + CASE CT[2..0] IS WHEN 0 => CT[2..0] = 1; WHEN 1 => CT[2..0] = 2; @@ -292,10 +314,11 @@ BEGIN WHEN 6 => CT[2..0] = 0; WHEN 7 => CT[2..0] = 0; END CASE; + -- for remove sinc jitter -- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,); CT[5..3].ena = DFF((CT0 & CT2),CLK42,,); - CT[5..3] = CT[5..3]+1; + CT[5..3] = CT[5..3]+1; % CASE CT[4..3] IS WHEN 0 => CT[5..3] = CT[5..3]+1; @@ -331,7 +354,7 @@ BEGIN SCR128 = DIR_PORT0; -- WR_PIX = LCELL(TSN_W3); - WR_PIX = (TSN_W3); + WR_PIX = TSN_W3; DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS; VXA[].clk = CLK42; VXA[].ena = !E_WR; @@ -397,12 +420,12 @@ IF MODE == "SPRINTER" GENERATE -- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]); CASE CT[2..0] IS - WHEN B"110" => VCM[2..0].d = 5; -- 101 - WHEN B"000" => VCM[2..0].d = 1; -- 001 - WHEN B"001" => VCM[2..0].d = 4; -- 100 - WHEN B"010" => VCM[2..0].d = 3; -- 011 - WHEN B"100" => VCM[2..0].d = 2; -- 010 - WHEN B"101" => VCM[2..0].d = 0; -- 000 + WHEN B"110" => VCM[2..0].d = 5; -- 110 -> 101 6 -> 5 + WHEN B"000" => VCM[2..0].d = 1; -- 000 -> 001 0 -> 1 + WHEN B"001" => VCM[2..0].d = 4; -- 001 -> 100 1 -> 4 + WHEN B"010" => VCM[2..0].d = 3; -- 010 -> 011 2 -> 3 + WHEN B"100" => VCM[2..0].d = 2; -- 100 -> 010 4 -> 2 + WHEN B"101" => VCM[2..0].d = 0; -- 101 -> 000 5 -> 0 END CASE; CASE VCM[1..0] IS @@ -411,6 +434,9 @@ IF MODE == "SPRINTER" GENERATE V_CST[].d = (VCC,GND); V_WE.d = VCC; V_WEX.d = VCC; + +TSN_W3.d = X_MODE_BOND; +% IF VCM2 THEN -- TSN_W3.d = X_MODE5; TSN_W3.d = X_MODE_BOND; @@ -419,6 +445,8 @@ IF MODE == "SPRINTER" GENERATE TSN_W3.d = X_MODE_BOND; -- V_CST[].d = (VCC,X_MODE_BOND); END IF; +% + WHEN 1 => WR_PIC.d = !VCM2; WR_COL.d = VCM2; @@ -433,7 +461,10 @@ IF MODE == "SPRINTER" GENERATE V_WEX.d = GND; V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); WHEN 3 => - WR_PIC.d = X_MODE5; +-- WR_PIC.d = X_MODE5; +-- NEW 26.08.2022, fix bug with first column +-- it was reproducing when changes mode 320 -> 640, like any 320px screen squares -> text mode squares + WR_PIC.d = MODE0[5]; VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND); WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]); V_CST[].d = (VCC,GND); @@ -500,6 +531,7 @@ IF MODE == "SPRINTER" GENERATE -- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + -- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS -- D_PIC0_[].clk = !CLK42; @@ -572,6 +604,9 @@ IF MODE == "SPRINTER" GENERATE D_PIC0[].ena = !LWR_PIC; D_PIC0[].clk = CLK42; + + + IF LD_PIC THEN -- D_PIC0[] = D_PIC0_[]; D_PIC0[] = D_PICX_[]; @@ -579,6 +614,7 @@ IF MODE == "SPRINTER" GENERATE D_PIC0[] = (D_PIC0[6..0],GND); END IF; + -- DCOL[].clk = (LWR_COL); DCOL[].ena = !LWR_COL; DCOL[].clk = CLK42; @@ -596,6 +632,9 @@ IF MODE == "SPRINTER" GENERATE BRVA[].clrn = !MS_POINT; BRVA[].prn = !MS_POINT2; +-- MODE0[4] - graph / text +-- MODE0[5] - 320 / 640 resolution + -- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS WHEN B"1X" => BRVA[7..0] = DCOL[]; @@ -635,6 +674,69 @@ IF MODE == "SPRINTER" GENERATE -- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX)); + + + V_WEMMM = LCELL(V_WE); +-- V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok +-- V_WEMMO = LCELL(V_WEMMN); -- green arts +-- V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts +-- V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??) +-- V_WEMMS = LCELL(V_WEMMR); +-- V_WEMMT = LCELL(V_WEMMS); +-- V_WEMMU = LCELL(V_WEMMT); +-- V_WEMMV = LCELL(V_WEMMU); +-- V_WEMMW = LCELL(V_WEMMV); +-- V_WEMMX = LCELL(V_WEMMW); +-- V_WEMMY = LCELL(V_WEMMX); +-- V_WEMMZ = LCELL(V_WEMMY); + + V_WRM = LCELL(V_WE or V_WEMMM); + + +-- V_WRM = LCELL(V_WEMMN or V_WEMMM); +-- V_WRM2 = LCELL(V_WEMMN or V_WEMMM); +-- V_WRM2 = LCELL(V_WEMMR); +-- V_WRM = LCELL(V_WEMMM or V_WEMMN); +-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN); + + V_WEM = (V_WE); + +-- V_WEM2 = LCELL(V_WE); +-- V_WEM = LCELL(V_WEMMM & V_WEMMN); +-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO); + +--- LWR_COL = DFF(WR_COL,CLK42,,); + F_WR = ((LCELL(LCELL(LCELL(DFF(VCC,V_WE,,)))))); +--- F_WR = DFF(V_WE,CLK42,,); +-- V_WEMMZ = LCELL(CLK42); + V_EN3 = (DFF(!(!VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,)); + V_EN2 = (DFF(!(!VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,)); + V_EN1 = (DFF(!(VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,)); + V_EN0 = (DFF(!(VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,)); + + +-- V_WR_3 = LCELL(V_WRM or V_EN3); +-- V_WR_2 = LCELL(V_WRM or V_EN2); +-- V_WR_1 = LCELL(V_WRM or V_EN1); +-- V_WR_0 = LCELL(V_WRM or V_EN0); + V_WR_3 = (LCELL(LCELL(LCELL(V_WRM or V_EN3)))); + V_WR_2 = (LCELL(LCELL(LCELL(V_WRM or V_EN2)))); + V_WR_1 = (LCELL(LCELL(LCELL(V_WRM or V_EN1)))); + V_WR_0 = (LCELL(LCELL(LCELL(V_WRM or V_EN0)))); + + V_WEY3 = LCELL(V_WE or V_EN3); + V_WEY2 = LCELL(V_WE or V_EN2); + V_WEY1 = LCELL(V_WE or V_EN1); + V_WEY0 = LCELL(V_WE or V_EN0); + + V_WR[] = V_WR_[]; -- V_WR0-3 + V_WEN[] = V_WEY[]; -- VD0-3 + + + + + +% V_WEMMM = LCELL(V_WE); V_WEMMN = LCELL(V_WEMMM); V_WEMMO = LCELL(V_WEMMN); @@ -665,10 +767,15 @@ IF MODE == "SPRINTER" GENERATE V_WR[] = V_WR_[]; V_WEN[] = V_WEY[]; +% - CLK84 = LCELL(CLK42 xor CLK84_X); - CLK84_X = DFF(!CLK84_X,CLK84,,); - CLK84_Y = CLK84; + + + + +-- CLK84 = LCELL(CLK42 xor CLK84_X); +-- CLK84_X = DFF(!CLK84_X,CLK84,,); +-- CLK84_Y = CLK84; END GENERATE; -- end "sprinter" mode diff --git a/src/altera/acex/k30/VIDEO2_T1.TDF b/src/altera/acex/k30/VIDEO2_T1.TDF new file mode 100644 index 0000000..8e3bb3e --- /dev/null +++ b/src/altera/acex/k30/VIDEO2_T1.TDF @@ -0,0 +1,708 @@ + + TITLE "Video-controller"; + +INCLUDE "lpm_ram_dp"; + +PARAMETERS + ( + MODE = "SPRINTER", + MOUSE = "NO", + HOR_PLACE = H"50", + VER_PLACE = H"91" -- 122h/2 + ); + +SUBDESIGN video2 + ( + CLK42 : INPUT; + + CT[5..0] : OUTPUT; + CTH[5..0] : OUTPUT; + CTV[8..0] : OUTPUT; + CTF[6..0] : OUTPUT; + + BLANK : OUTPUT; + + START_UP : INPUT; + COPY_SINC_H : INPUT; + COPY_SINC_V : INPUT; + + WR : INPUT; + + VAI[19..0] : INPUT; -- input screen adress + + VAO[15..0] : OUTPUT; + + D[7..0] : INPUT; + MDI[15..0] : INPUT; + + VDO0[7..0] : OUTPUT; + VDO1[7..0] : OUTPUT; + VDO2[7..0] : OUTPUT; + VDO3[7..0] : OUTPUT; + + VDM0[7..0] : INPUT; + VDM1[7..0] : INPUT; + VDM2[7..0] : INPUT; + VDM3[7..0] : INPUT; + + V_WR[3..0] : OUTPUT; + V_WEN[3..0] : OUTPUT; + + V_CS[1..0] : OUTPUT; + WR_PIX : OUTPUT; + +-- ZX_COLOR[3..0] : OUTPUT; + + ZX_PORT[7..0] : INPUT; + DIR_PORT[7..0] : INPUT; + +% + bit0 - Spectrum SCREEN Switch + bit1 - Spectrum Adress MODE + bit2 - Write to Spectrum Screen OFF + bit3 - MODE page 0/1 + bit4 - MODE on/off screen + + bit7..5 - Border +% + + INTT : OUTPUT; + + DOUBLE_CAS : INPUT; + + MOUSE_X[9..0] : INPUT; + MOUSE_Y[9..0] : INPUT; + + + ) +VARIABLE + + CLK84 : NODE; + CLK84_X : NODE; + CLK84_Y : NODE; + + ZX_COLOR[3..0] : NODE; + + CT[5..0] : DFFE; + CTH[5..0] : DFFE; + CTV[8..0] : DFFE; + CTF[6..0] : DFF; + + VXA[19..0] : DFFE; + + VXD0[7..0] : DFFE; + VXD1[7..0] : DFFE; + VXD2[7..0] : DFFE; + VXD3[7..0] : DFFE; + + E_WR : NODE; + E_WRD : NODE; + + BLANK : NODE; + BORD : NODE; +-- INTT_T : NODE; + INTTX : NODE; + + VLA[17..0] : DFF; +-- SVA[17..0] : NODE; + SVA[17..0] : DFF; +-- RSVA[8..0] : LCELL; + RSVA[8..0] : NODE; +-- RSVA[8..0] : DFF; + + V_CST[1..0] : DFF; + VCM[2..0] : DFF; + TSN_W3 : DFF; + V_WE : DFF; + V_WEX : DFF; + + V_WEM : NODE; + V_WEM1 : NODE; + V_WEM2 : NODE; + V_WEM3 : NODE; + V_WRM : NODE; + V_WRM1 : NODE; + V_WRM2 : NODE; + V_WRM3 : NODE; + + V_WEMM : NODE; + V_WEMMM : NODE; + V_WEMMN : NODE; + V_WEMMO : NODE; + V_WEMMP : NODE; + V_WEMMQ : NODE; + V_WEMMR : NODE; + V_WEMMS : NODE; + V_WEMMT : NODE; + V_WEMMU : NODE; + V_WEMMV : NODE; + V_WEMMW : NODE; + V_WEMMX : NODE; + V_WEMMY : NODE; + V_WEMMZ : NODE; + + V_WET[3..0] : DFF; + + D_PIC0[7..0] : DFFE; +-- D_PIC0_[7..0] : LCELL; + + D_PIC0_[7..0] : DFFE; + D_PIC1_[7..0] : DFFE; + D_PIC2_[7..0] : DFFE; + D_PIC3_[7..0] : DFFE; + + D_PICX_[7..0] : NODE; + + LWR_PIC : NODE; + LWR_COL : NODE; + + WR_PIC : DFF; + WR_COL : DFF; + LD_PIC : NODE; + + RBRVA[10..8]: DFF; + BRVA[7..0] : DFF; + DCOL[7..0] : DFFE; + + MXWE : NODE; +-- MXCE : NODE; + + AX128 : NODE; + + BRD[2..0] : NODE; + + ZX_COL[3..0] : LCELL; + + ZXA15 : NODE; + ZXS[5..0] : NODE; + ZX_SCREEN : NODE; + SCR128 : NODE; + + MODE0[7..0] : DFFE; + MODE1[7..0] : DFFE; + MODE2[7..0] : DFFE; +-- MODE3[7..0] : DFF; + + WR_MODE : DFF; + LWR_MODE : NODE; + X_MODE[7..4]: NODE; + X_MODE_BOND : NODE; + +-- M_CTV[2..0] : DFF; +-- M_CT[5..3] : DFF; + M_CTV[2..0] : LCELL; + M_CT[5..3] : LCELL; + + DOUBLE : DFFE; + + PIC_CLK : NODE; + + MS_X[9..0] : DFF; + MS_Y[9..0] : DFF; + + MS_POINT : NODE; + MS_POINT2 : NODE; + MS_PNT : NODE; + + MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF"); + + SCR_ENA : DFFE; + V_WR_[3..0] : LCELL; + V_WEY[3..0] : LCELL; + + V_WE_R : NODE; + + V_CSX[3..0] : NODE; + + V_EN[3..0] : NODE; + + F_WR : NODE; + +BEGIN + + DEFAULTS + WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC; + V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC; + V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC; + V_WET[].d = VCC; + END DEFAULTS; + + ZX_COLOR[] = ZX_COL[]; + +-- === MOUSE counters ======== + + MS_X[].clk = !CT1; + CASE LCELL(CTH[5..2] == 12) IS + WHEN 0 => MS_X[] = MS_X[] + 1; + WHEN 1 => MS_X[] = (!MOUSE_X[9..0]); + END CASE; + + MS_Y[].clk = !CTH5; + CASE LCELL(CTV8 & !CTV5 & CTV4) IS + WHEN 0 => MS_Y[] = MS_Y[] + 1; + WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]); + END CASE; + + MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,); + + MS_DAT.wren = GND; + MS_DAT.data[] = GND; + MS_DAT.wraddress[] = GND; + MS_DAT.wrclock = CLK42; + MS_DAT.wrclken = GND; + MS_DAT.rden = VCC; + MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]); + MS_DAT.rdclock = CLK42; + MS_DAT.rdclken = VCC; + + IF MOUSE == "NO" GENERATE + MS_POINT = GND; + MS_POINT2 = GND; + ELSE GENERATE + MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,); + MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,); + END GENERATE; + +-- === Sinc-counts GENERATOR ============================================ + +-- CT[].clrn = START_UP; + +-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE; +-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE; + +-- CTV[].clrn = !COPY_SINC_V or VER_PLACE; +-- CTV[].prn = !COPY_SINC_V or !VER_PLACE; + + CT[5].clrn = !COPY_SINC_H; + + -- set CTH to 50 (32h) + CTH[0].clrn = !COPY_SINC_H; + CTH[1].prn = !COPY_SINC_H; + CTH[2].clrn = !COPY_SINC_H; + CTH[3].clrn = !COPY_SINC_H; + CTH[4].prn = !COPY_SINC_H; + CTH[5].prn = !COPY_SINC_H; + + -- set CTV to 122h + CTV[0].clrn = !COPY_SINC_V; + CTV[1].prn = !COPY_SINC_V; + CTV[3..2].clrn = !COPY_SINC_V; + + CTV[4].clrn = !COPY_SINC_V; + CTV[5].prn = !COPY_SINC_V; + CTV[7..6].clrn = !COPY_SINC_V; + CTV[8].prn = !COPY_SINC_V; + + CT[5..0].clk = CLK42; + CTH[5..0].clk = CLK42; + CTV[8..0].clk = CLK42; + + CT[2..0].ena = VCC; + CASE CT[2..0] IS + WHEN 0 => CT[2..0] = 1; + WHEN 1 => CT[2..0] = 2; + WHEN 2 => CT[2..0] = 4; + WHEN 3 => CT[2..0] = 4; + WHEN 4 => CT[2..0] = 5; + WHEN 5 => CT[2..0] = 6; + WHEN 6 => CT[2..0] = 0; + WHEN 7 => CT[2..0] = 0; + END CASE; + -- for remove sinc jitter +-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,); + CT[5..3].ena = DFF((CT0 & CT2),CLK42,,); + CT[5..3] = CT[5..3]+1; +% + CASE CT[4..3] IS + WHEN 0 => CT[5..3] = CT[5..3]+1; + WHEN 1 => CT[5..3] = CT[5..3]+1; + WHEN 2 => CT[5..3] = CT[5..3]+1; + WHEN 3 => CT[5..3] = CT[5..3]+1; + END CASE; +% + CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,); + CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,); + + IF CTH[] == 55 THEN + CTH[] = GND; + ELSE + CTH[] = CTH[] + 1; + END IF; + + IF CTV[] == 319 THEN + CTV[] = GND; + ELSE + CTV[] = CTV[] + 1; + END IF; + + CTF[].clk = CTV8; + CTF[] = CTF[]+1; + +-- ==== Video ========================================================== + + ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens + ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write + ZXA15 = ZX_PORT7; -- ZX A15' line + + SCR128 = DIR_PORT0; + +-- WR_PIX = LCELL(TSN_W3); + WR_PIX = (TSN_W3); + + DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS; + VXA[].clk = CLK42; VXA[].ena = !E_WR; + + VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[]; + VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[]; + VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[]; + VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[]; + +-- VXD0[] = D[]; +-- VXD1[] = D[]; +-- VXD2[] = D[]; +-- VXD3[] = D[]; + + (VXD0[],VXD1[]) = MDI[]; + (VXD2[],VXD3[]) = MDI[]; + + BRD[] = DIR_PORT[7..5]; + + VCM[].clk = CLK42; + TSN_W3.clk = CLK42; + V_CST[].clk = CLK42; + V_WE.clk = CLK42; + V_WET[].clk = CLK42; + VLA[].clk = CLK42; + + SCR_ENA.clk = CLK42; + SCR_ENA.ena = !E_WR; + SCR_ENA.d = !(VAI19 or ZX_SCREEN); + + E_WRD = DFF(E_WR,CLK42,,); + E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,)); +-- E_WR = LCELL(WR or !DFF(WR,CLK42,,)); + +-- **************************************************** + +IF MODE == "SPRINTER" GENERATE + +-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode + +-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE); + MXWE = DFF(MXWE,CLK42,E_WR,V_WE); + + IF VAI[19] THEN + -- in graf mode all 256k(512k) range + VXA[] = VAI[]; + ELSE + -- in spectrum mode 8k/16k range pages + VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]); + END IF; + +-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,); +-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,); +-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,); + + BORD = DFF((MODE0[7..4] == 15),LWR_COL,,); + BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,); + INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,); + + INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,); + +-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,); +-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]); + + CASE CT[2..0] IS + WHEN B"110" => VCM[2..0].d = 5; -- 101 + WHEN B"000" => VCM[2..0].d = 1; -- 001 + WHEN B"001" => VCM[2..0].d = 4; -- 100 + WHEN B"010" => VCM[2..0].d = 3; -- 011 + WHEN B"100" => VCM[2..0].d = 2; -- 010 + WHEN B"101" => VCM[2..0].d = 0; -- 000 + END CASE; + + CASE VCM[1..0] IS + WHEN 0 => + VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + IF VCM2 THEN +-- TSN_W3.d = X_MODE5; + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE5); + ELSE + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE_BOND); + END IF; + WHEN 1 => + WR_PIC.d = !VCM2; + WR_COL.d = VCM2; + VLA[].d = SVA[]; + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + WHEN 2 => + VLA[].d = VXA[17..0]; + V_CST[].d = (!VXA18,VXA18) or MXWE; + V_WE.d = MXWE; + V_WEX.d = GND; + V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + WHEN 3 => + WR_PIC.d = X_MODE5; + VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND); + WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + END CASE; + +-- choose V-RAM komplect + + V_CST1.prn = GND; +-- V_CS0.clrn = GND; + V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0))); + V_CS1 = VCC; +-- V_CS0 = LCELL(V_CST0); + + V_CSX0 = LCELL(!CLK42); + V_CSX1 = LCELL(V_CSX0); + V_CSX2 = LCELL(V_CSX1 & V_CSX0); + V_CSX3 = LCELL(V_CSX2); + +-- V_CS0 = V_CSX3; + V_CS0 = GND; + +-- ===================== + + SVA[].clk = CLK42; + SVA[9..6] = MODE0[3..0]; +-- RSVA[].clk = CLK42; + (SVA[12..10],SVA[5..0]) = RSVA[]; + +-- M_CTV[2..0].clk = CLK42; +-- M_CT[5..3].clk = CLK42; + M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]); + M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]); + + CASE (!VCM2,MODE0[4]) IS +-- CASE (!VCM1,MODE0[4]) IS + WHEN B"X0" => + -- Graf adress -- + RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = CTV[2..0]; +-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]); + WHEN B"01" => + -- ZX-atr adress -- + RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]); + SVA[17..13] = MODE2[7..3]; + +-- SVA[12..10] = MODE2[2..0]; +-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]); + WHEN B"11" => + -- ZX-pic adress -- + RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = MODE1[2..0]; +-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + END CASE; + +-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC)); + X_MODE_BOND = GND; + +-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + +-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS + +-- D_PIC0_[].clk = !CLK42; +-- D_PIC1_[].clk = !CLK42; +-- D_PIC2_[].clk = !CLK42; +-- D_PIC3_[].clk = !CLK42; + +-- PIC_CLK = LCELL(LCELL(CLK42)); + PIC_CLK = !CLK42; + + D_PIC0_[].clk = PIC_CLK; + D_PIC1_[].clk = PIC_CLK; + D_PIC2_[].clk = PIC_CLK; + D_PIC3_[].clk = PIC_CLK; + + D_PIC0_[] = VDM0[]; + D_PIC1_[] = VDM1[]; + D_PIC2_[] = VDM2[]; + D_PIC3_[] = VDM3[]; + + CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS + WHEN 0 => D_PICX_[] = D_PIC0_[]; + WHEN 1 => D_PICX_[] = D_PIC1_[]; + WHEN 2 => D_PICX_[] = D_PIC2_[]; + WHEN 3 => D_PICX_[] = D_PIC3_[]; + END CASE; + + MODE0[].ena = VCC; + MODE1[].ena = VCC; + MODE2[].ena = VCC; + MODE0[].clk = LWR_MODE; + MODE1[].clk = LWR_MODE; + MODE2[].clk = LWR_MODE; + MODE0[].d = VDM3[]; + MODE1[].d = VDM2[]; + MODE2[].d = VDM1[]; + LWR_MODE = LCELL(LCELL(WR_MODE)); +% + MODE0[].ena = LWR_MODE; + MODE1[].ena = LWR_MODE; + MODE2[].ena = LWR_MODE; + MODE0[].clk = CLK42; + MODE1[].clk = CLK42; + MODE2[].clk = CLK42; + MODE0[].d = D_PIC3_[]; + MODE1[].d = D_PIC2_[]; + MODE2[].d = D_PIC1_[]; + LWR_MODE = DFF(!WR_MODE,CLK42,,); +% + X_MODE7 = DFF(MODE0[7],LWR_COL,,); + X_MODE6 = DFF(MODE0[6],LWR_COL,,); + X_MODE5 = DFF(MODE0[5],LWR_COL,,); + X_MODE4 = DFF(MODE0[4],LWR_COL,,); + + VAO[] = VLA[17..2]; + + WR_PIC.clk = CLK42; + WR_COL.clk = CLK42; + WR_MODE.clk = CLK42; + +-- LWR_PIC = LCELL(LCELL(WR_PIC)); +-- LWR_COL = LCELL(LCELL(WR_COL)); +-- LWR_PIC = LCELL(WR_PIC); +-- LWR_COL = LCELL(WR_COL); + LWR_PIC = DFF(WR_PIC,CLK42,,); + LWR_COL = DFF(WR_COL,CLK42,,); + +-- D_PIC0[].ena = VCC; +-- D_PIC0[].clk = (LWR_PIC); + D_PIC0[].ena = !LWR_PIC; + D_PIC0[].clk = CLK42; + + IF LD_PIC THEN +-- D_PIC0[] = D_PIC0_[]; + D_PIC0[] = D_PICX_[]; + ELSE + D_PIC0[] = (D_PIC0[6..0],GND); + END IF; + +-- DCOL[].clk = (LWR_COL); + DCOL[].ena = !LWR_COL; + DCOL[].clk = CLK42; + + IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN + DCOL[].d = (B"00",BRD[2..0],BRD[2..0]); + ELSE +-- DCOL[].d = D_PIC0_[]; + DCOL[].d = D_PICX_[]; + END IF; + + DCOL[].clrn = !BLANK; + + BRVA[].clk = CLK42; + BRVA[].clrn = !MS_POINT; + BRVA[].prn = !MS_POINT2; + +-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS + CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS + WHEN B"1X" => BRVA[7..0] = DCOL[]; + WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]); + WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]); + END CASE; + +-- BRVA[10..8] = (x_mode4,RBRVA[9..8]); + RBRVA[].clk = CLK42; + + CASE (BORD,X_MODE4) IS + WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]); + WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]); + END CASE; + + RBRVA[9..8].clrn = !BORD; + RBRVA[10].prn = !BORD; + + CASE (RBRVA[9..8],BRVA7) IS + WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]); + WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]); + END CASE; + +-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE)); +-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE)); + + V_WE_R = DFF(GND,!CLK42,,!V_WE); + V_WE.prn = V_WE_R; + V_WET[].prn = V_WE_R; + +-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + +-- V_WR[] = (V_WE) or !( + + V_WEX.clk = CLK42; +-- V_WEX.d = V_WE; +-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX)); + + +-- V_WE_R1 = LCELL(V_WE); +-- V_WEMMM = LCELL(V_WE_R1); + + V_WEMMM = LCELL(V_WE); + V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok + V_WEMMO = LCELL(V_WEMMN); -- green arts + V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts + V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??) + V_WEMMS = LCELL(V_WEMMR); +-- V_WEMMT = LCELL(V_WEMMS); +-- V_WEMMU = LCELL(V_WEMMT); +-- V_WEMMV = LCELL(V_WEMMU); +-- V_WEMMW = LCELL(V_WEMMV); +-- V_WEMMX = LCELL(V_WEMMW); +-- V_WEMMY = LCELL(V_WEMMX); +-- V_WEMMZ = LCELL(V_WEMMY); + + V_WRM = LCELL(V_WEMMN or V_WEMMM); +-- V_WRM2 = LCELL(V_WEMMR); +-- V_WRM = LCELL(V_WEMMM or V_WEMMN); +-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN); + + V_WEM = LCELL(V_WE); +-- V_WEM2 = LCELL(V_WE); +-- V_WEM = LCELL(V_WEMMM & V_WEMMN); +-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO); + + F_WR = DFF(VCC,V_WE,,); + V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,); + V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,); + V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,); + V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,); + + + V_WR_3 = (V_WRM or V_EN3); + V_WR_2 = (V_WRM or V_EN2); + V_WR_1 = (V_WRM or V_EN1); + V_WR_0 = (V_WRM or V_EN0); + + V_WEY3 = V_WEM or V_EN3; + V_WEY2 = V_WEM or V_EN2; + V_WEY1 = V_WEM or V_EN1; + V_WEY0 = V_WEM or V_EN0; + + V_WR[] = V_WR_[]; + V_WEN[] = V_WEY[]; + +-- CLK84 = LCELL(CLK42 xor CLK84_X); +-- CLK84_X = DFF(!CLK84_X,CLK84,,); +-- CLK84_Y = CLK84; + +END GENERATE; -- end "sprinter" mode + + +END; diff --git a/src/altera/acex/k30/VIDEO2_T2.TDF b/src/altera/acex/k30/VIDEO2_T2.TDF new file mode 100644 index 0000000..61f62e3 --- /dev/null +++ b/src/altera/acex/k30/VIDEO2_T2.TDF @@ -0,0 +1,773 @@ + + TITLE "Video-controller"; + +INCLUDE "lpm_ram_dp"; + +PARAMETERS + ( + MODE = "SPRINTER", + MOUSE = "NO", + HOR_PLACE = H"50", + VER_PLACE = H"91" -- 122h/2 + ); + +SUBDESIGN video2 + ( + CLK42 : INPUT; + + CT[5..0] : OUTPUT; + CTH[5..0] : OUTPUT; + CTV[8..0] : OUTPUT; + CTF[6..0] : OUTPUT; + + BLANK : OUTPUT; + + START_UP : INPUT; + COPY_SINC_H : INPUT; + COPY_SINC_V : INPUT; + + WR : INPUT; + + VAI[19..0] : INPUT; -- input screen adress + + VAO[15..0] : OUTPUT; + + D[7..0] : INPUT; + MDI[15..0] : INPUT; + + VDO0[7..0] : OUTPUT; + VDO1[7..0] : OUTPUT; + VDO2[7..0] : OUTPUT; + VDO3[7..0] : OUTPUT; + + VDM0[7..0] : INPUT; + VDM1[7..0] : INPUT; + VDM2[7..0] : INPUT; + VDM3[7..0] : INPUT; + + V_WR[3..0] : OUTPUT; + V_WEN[3..0] : OUTPUT; + + V_CS[1..0] : OUTPUT; + WR_PIX : OUTPUT; + +-- ZX_COLOR[3..0] : OUTPUT; + + ZX_PORT[7..0] : INPUT; + DIR_PORT[7..0] : INPUT; + +% + bit0 - Spectrum SCREEN Switch + bit1 - Spectrum Adress MODE + bit2 - Write to Spectrum Screen OFF + bit3 - MODE page 0/1 + bit4 - MODE on/off screen + + bit7..5 - Border +% + + INTT : OUTPUT; + + DOUBLE_CAS : INPUT; + + MOUSE_X[9..0] : INPUT; + MOUSE_Y[9..0] : INPUT; + + + ) +VARIABLE + +-- CLK84 : NODE; +-- CLK84_X : NODE; +-- CLK84_Y : NODE; + + ZX_COLOR[3..0] : NODE; + + CT[5..0] : DFFE; + CTH[5..0] : DFFE; + CTV[8..0] : DFFE; + CTF[6..0] : DFF; + + VXA[19..0] : DFFE; + + VXD0[7..0] : DFFE; + VXD1[7..0] : DFFE; + VXD2[7..0] : DFFE; + VXD3[7..0] : DFFE; + + E_WR : NODE; + E_WRD : NODE; + + BLANK : NODE; + BORD : NODE; +-- INTT_T : NODE; + INTTX : NODE; + + VLA[17..0] : DFF; +-- SVA[17..0] : NODE; + SVA[17..0] : DFF; +-- RSVA[8..0] : LCELL; + RSVA[8..0] : NODE; +-- RSVA[8..0] : DFF; + + V_CST[1..0] : DFF; + VCM[2..0] : DFF; + TSN_W3 : DFF; + V_WE : DFF; + V_WEX : DFF; + + V_WEM : NODE; + V_WEM2 : NODE; + V_WRM : NODE; + V_WRM2 : NODE; +% + V_WEMM : NODE; + V_WEMMM : NODE; + V_WEMMN : NODE; + V_WEMMO : NODE; +% + V_WEMM : NODE; + V_WEMMM : NODE; + V_WEMMN : NODE; + V_WEMMO : NODE; + V_WEMMP : NODE; + V_WEMMQ : NODE; + V_WEMMR : NODE; + V_WEMMS : NODE; + V_WEMMT : NODE; + V_WEMMU : NODE; + V_WEMMV : NODE; + V_WEMMW : NODE; + V_WEMMX : NODE; + V_WEMMY : NODE; + V_WEMMZ : NODE; + + + + V_WET[3..0] : DFF; + + D_PIC0[7..0] : DFFE; +-- D_PIC0_[7..0] : LCELL; + + D_PIC0_[7..0] : DFFE; + D_PIC1_[7..0] : DFFE; + D_PIC2_[7..0] : DFFE; + D_PIC3_[7..0] : DFFE; + + D_PICX_[7..0] : NODE; + + LWR_PIC : NODE; + LWR_COL : NODE; + + WR_PIC : DFF; + WR_COL : DFF; + LD_PIC : NODE; +MXL: NODE; +MXR: NODE; + + RBRVA[10..8]: DFF; + BRVA[7..0] : DFF; + DCOL[7..0] : DFFE; + + MXWE : NODE; +-- MXCE : NODE; + + AX128 : NODE; + + BRD[2..0] : NODE; + + ZX_COL[3..0] : LCELL; + + ZXA15 : NODE; + ZXS[5..0] : NODE; + ZX_SCREEN : NODE; + SCR128 : NODE; + + MODE0[7..0] : DFFE; + MODE1[7..0] : DFFE; + MODE2[7..0] : DFFE; +-- MODE3[7..0] : DFF; + + WR_MODE : DFF; + LWR_MODE : NODE; + X_MODE[7..4]: NODE; + X_MODE_BOND : NODE; + +-- M_CTV[2..0] : DFF; +-- M_CT[5..3] : DFF; + M_CTV[2..0] : LCELL; + M_CT[5..3] : LCELL; + + DOUBLE : DFFE; + + PIC_CLK : NODE; + + MS_X[9..0] : DFF; + MS_Y[9..0] : DFF; + + MS_POINT : NODE; + MS_POINT2 : NODE; + MS_PNT : NODE; + + MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF"); + + SCR_ENA : DFFE; + V_WR_[3..0] : LCELL; + V_WEY[3..0] : LCELL; + + V_WE_R : NODE; + + V_CSX[3..0] : NODE; + + V_EN[3..0] : NODE; + + F_WR : NODE; + +BEGIN + + DEFAULTS + WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC; + V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC; + V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC; + V_WET[].d = VCC; + END DEFAULTS; + + ZX_COLOR[] = ZX_COL[]; + +-- === MOUSE counters ======== + + MS_X[].clk = !CT1; + CASE LCELL(CTH[5..2] == 12) IS + WHEN 0 => MS_X[] = MS_X[] + 1; + WHEN 1 => MS_X[] = (!MOUSE_X[9..0]); + END CASE; + + MS_Y[].clk = !CTH5; + CASE LCELL(CTV8 & !CTV5 & CTV4) IS + WHEN 0 => MS_Y[] = MS_Y[] + 1; + WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]); + END CASE; + + MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,); + + MS_DAT.wren = GND; + MS_DAT.data[] = GND; + MS_DAT.wraddress[] = GND; + MS_DAT.wrclock = CLK42; + MS_DAT.wrclken = GND; + MS_DAT.rden = VCC; + MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]); + MS_DAT.rdclock = CLK42; + MS_DAT.rdclken = VCC; + + IF MOUSE == "NO" GENERATE + MS_POINT = GND; + MS_POINT2 = GND; + ELSE GENERATE + MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,); + MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,); + END GENERATE; + +-- === Sinc-counts GENERATOR ============================================ + +-- CT[].clrn = START_UP; + +-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE; +-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE; + +-- CTV[].clrn = !COPY_SINC_V or VER_PLACE; +-- CTV[].prn = !COPY_SINC_V or !VER_PLACE; + + CT[5].clrn = !COPY_SINC_H; + + -- set CTH to 50 (32h) + CTH[0].clrn = !COPY_SINC_H; + CTH[1].prn = !COPY_SINC_H; + CTH[2].clrn = !COPY_SINC_H; + CTH[3].clrn = !COPY_SINC_H; + CTH[4].prn = !COPY_SINC_H; + CTH[5].prn = !COPY_SINC_H; + + -- set CTV to 122h + CTV[0].clrn = !COPY_SINC_V; + CTV[1].prn = !COPY_SINC_V; + CTV[3..2].clrn = !COPY_SINC_V; + + CTV[4].clrn = !COPY_SINC_V; + CTV[5].prn = !COPY_SINC_V; + CTV[7..6].clrn = !COPY_SINC_V; + CTV[8].prn = !COPY_SINC_V; + + CT[5..0].clk = CLK42; + CTH[5..0].clk = CLK42; + CTV[8..0].clk = CLK42; + + CT[2..0].ena = VCC; + + CASE CT[2..0] IS + WHEN 0 => CT[2..0] = 1; + WHEN 1 => CT[2..0] = 2; + WHEN 2 => CT[2..0] = 4; + WHEN 3 => CT[2..0] = 4; + WHEN 4 => CT[2..0] = 5; + WHEN 5 => CT[2..0] = 6; + WHEN 6 => CT[2..0] = 0; + WHEN 7 => CT[2..0] = 0; + END CASE; + + -- for remove sinc jitter +-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,); + CT[5..3].ena = DFF((CT0 & CT2),CLK42,,); + CT[5..3] = CT[5..3]+1; +% + CASE CT[4..3] IS + WHEN 0 => CT[5..3] = CT[5..3]+1; + WHEN 1 => CT[5..3] = CT[5..3]+1; + WHEN 2 => CT[5..3] = CT[5..3]+1; + WHEN 3 => CT[5..3] = CT[5..3]+1; + END CASE; +% + CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,); + CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,); + + IF CTH[] == 55 THEN + CTH[] = GND; + ELSE + CTH[] = CTH[] + 1; + END IF; + + IF CTV[] == 319 THEN + CTV[] = GND; + ELSE + CTV[] = CTV[] + 1; + END IF; + + CTF[].clk = CTV8; + CTF[] = CTF[]+1; + +-- ==== Video ========================================================== + + ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens + ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write + ZXA15 = ZX_PORT7; -- ZX A15' line + + SCR128 = DIR_PORT0; + +-- WR_PIX = LCELL(TSN_W3); + WR_PIX = (TSN_W3); + + DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS; + VXA[].clk = CLK42; VXA[].ena = !E_WR; + + VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[]; + VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[]; + VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[]; + VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[]; + +-- VXD0[] = D[]; +-- VXD1[] = D[]; +-- VXD2[] = D[]; +-- VXD3[] = D[]; + + (VXD0[],VXD1[]) = MDI[]; + (VXD2[],VXD3[]) = MDI[]; + + BRD[] = DIR_PORT[7..5]; + + VCM[].clk = CLK42; + TSN_W3.clk = CLK42; + V_CST[].clk = CLK42; + V_WE.clk = CLK42; + V_WET[].clk = CLK42; + VLA[].clk = CLK42; + + SCR_ENA.clk = CLK42; + SCR_ENA.ena = !E_WR; + SCR_ENA.d = !(VAI19 or ZX_SCREEN); + + E_WRD = DFF(E_WR,CLK42,,); + E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,)); +-- E_WR = LCELL(WR or !DFF(WR,CLK42,,)); + +-- **************************************************** + +IF MODE == "SPRINTER" GENERATE + +-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode + +-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE); + MXWE = DFF(MXWE,CLK42,E_WR,V_WE); + + IF VAI[19] THEN + -- in graf mode all 256k(512k) range + VXA[] = VAI[]; + ELSE + -- in spectrum mode 8k/16k range pages + VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]); + END IF; + +-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,); +-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,); +-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,); + + BORD = DFF((MODE0[7..4] == 15),LWR_COL,,); + BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,); + INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,); + + INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,); + +-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,); +-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]); + + CASE CT[2..0] IS + WHEN B"110" => VCM[2..0].d = 5; -- 110 -> 101 6 -> 5 + WHEN B"000" => VCM[2..0].d = 1; -- 000 -> 001 0 -> 1 + WHEN B"001" => VCM[2..0].d = 4; -- 001 -> 100 1 -> 4 + WHEN B"010" => VCM[2..0].d = 3; -- 010 -> 011 2 -> 3 + WHEN B"100" => VCM[2..0].d = 2; -- 100 -> 010 4 -> 2 + WHEN B"101" => VCM[2..0].d = 0; -- 101 -> 000 5 -> 0 + END CASE; + + CASE VCM[1..0] IS + WHEN 0 => + VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + IF VCM2 THEN +-- TSN_W3.d = X_MODE5; + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE5); + ELSE + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE_BOND); + END IF; + WHEN 1 => + WR_PIC.d = !VCM2; + WR_COL.d = VCM2; + VLA[].d = SVA[]; + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + WHEN 2 => + VLA[].d = VXA[17..0]; + V_CST[].d = (!VXA18,VXA18) or MXWE; + V_WE.d = MXWE; + V_WEX.d = GND; + V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + WHEN 3 => +-- WR_PIC.d = X_MODE5; +-- NEW 26.08.2022, fix bug with first column +-- it was reproducing when changes mode 320 -> 640, like any 320px screen squares -> text mode squares + WR_PIC.d = MODE0[5]; + VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND); + WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + END CASE; + +-- choose V-RAM komplect + + V_CST1.prn = GND; +-- V_CS0.clrn = GND; + V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0))); + V_CS1 = VCC; +-- V_CS0 = LCELL(V_CST0); + + V_CSX0 = LCELL(!CLK42); + V_CSX1 = LCELL(V_CSX0); + V_CSX2 = LCELL(V_CSX1 & V_CSX0); + V_CSX3 = LCELL(V_CSX2); + +-- V_CS0 = V_CSX3; + V_CS0 = GND; + +-- ===================== + + SVA[].clk = CLK42; + SVA[9..6] = MODE0[3..0]; +-- RSVA[].clk = CLK42; + (SVA[12..10],SVA[5..0]) = RSVA[]; + +-- M_CTV[2..0].clk = CLK42; +-- M_CT[5..3].clk = CLK42; + M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]); + M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]); + + CASE (!VCM2,MODE0[4]) IS +-- CASE (!VCM1,MODE0[4]) IS + WHEN B"X0" => + -- Graf adress -- + RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = CTV[2..0]; +-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]); + WHEN B"01" => + -- ZX-atr adress -- + RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]); + SVA[17..13] = MODE2[7..3]; + +-- SVA[12..10] = MODE2[2..0]; +-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]); + WHEN B"11" => + -- ZX-pic adress -- + RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = MODE1[2..0]; +-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + END CASE; + +-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC)); + X_MODE_BOND = GND; + +-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); +-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + LD_PIC = LCELL((MODE0[5] & DFF((CT[5..2] == B"0000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + + +-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS + +-- D_PIC0_[].clk = !CLK42; +-- D_PIC1_[].clk = !CLK42; +-- D_PIC2_[].clk = !CLK42; +-- D_PIC3_[].clk = !CLK42; + +-- PIC_CLK = LCELL(LCELL(CLK42)); + PIC_CLK = !CLK42; + + D_PIC0_[].clk = PIC_CLK; + D_PIC1_[].clk = PIC_CLK; + D_PIC2_[].clk = PIC_CLK; + D_PIC3_[].clk = PIC_CLK; + + D_PIC0_[] = VDM0[]; + D_PIC1_[] = VDM1[]; + D_PIC2_[] = VDM2[]; + D_PIC3_[] = VDM3[]; + + CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS + WHEN 0 => D_PICX_[] = D_PIC0_[]; + WHEN 1 => D_PICX_[] = D_PIC1_[]; + WHEN 2 => D_PICX_[] = D_PIC2_[]; + WHEN 3 => D_PICX_[] = D_PIC3_[]; + END CASE; + + MODE0[].ena = VCC; + MODE1[].ena = VCC; + MODE2[].ena = VCC; + MODE0[].clk = LWR_MODE; + MODE1[].clk = LWR_MODE; + MODE2[].clk = LWR_MODE; + MODE0[].d = VDM3[]; + MODE1[].d = VDM2[]; + MODE2[].d = VDM1[]; + LWR_MODE = LCELL(LCELL(WR_MODE)); +% + MODE0[].ena = LWR_MODE; + MODE1[].ena = LWR_MODE; + MODE2[].ena = LWR_MODE; + MODE0[].clk = CLK42; + MODE1[].clk = CLK42; + MODE2[].clk = CLK42; + MODE0[].d = D_PIC3_[]; + MODE1[].d = D_PIC2_[]; + MODE2[].d = D_PIC1_[]; + LWR_MODE = DFF(!WR_MODE,CLK42,,); +% + X_MODE7 = DFF(MODE0[7],LWR_COL,,); + X_MODE6 = DFF(MODE0[6],LWR_COL,,); + X_MODE5 = DFF(MODE0[5],LWR_COL,,); + X_MODE4 = DFF(MODE0[4],LWR_COL,,); + + VAO[] = VLA[17..2]; + + WR_PIC.clk = CLK42; + WR_COL.clk = CLK42; + WR_MODE.clk = CLK42; + +-- LWR_PIC = LCELL(LCELL(WR_PIC)); +-- LWR_COL = LCELL(LCELL(WR_COL)); +-- LWR_PIC = LCELL(WR_PIC); +-- LWR_COL = LCELL(WR_COL); + LWR_PIC = DFF(WR_PIC,CLK42,,); + LWR_COL = DFF(WR_COL,CLK42,,); + +-- D_PIC0[].ena = VCC; +-- D_PIC0[].clk = (LWR_PIC); + D_PIC0[].ena = !LWR_PIC; + D_PIC0[].clk = CLK42; + + + + + IF LD_PIC THEN +-- D_PIC0[] = D_PIC0_[]; + D_PIC0[] = D_PICX_[]; + ELSE + D_PIC0[] = (D_PIC0[6..0],GND); + END IF; + + +-- DCOL[].clk = (LWR_COL); + DCOL[].ena = !LWR_COL; + DCOL[].clk = CLK42; + + IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN + DCOL[].d = (B"00",BRD[2..0],BRD[2..0]); + ELSE +-- DCOL[].d = D_PIC0_[]; + DCOL[].d = D_PICX_[]; + END IF; + + DCOL[].clrn = !BLANK; + + BRVA[].clk = CLK42; + BRVA[].clrn = !MS_POINT; + BRVA[].prn = !MS_POINT2; + +-- MODE0[4] - graph / text +-- MODE0[5] - 320 / 640 resolution + +-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS + CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS + WHEN B"1X" => BRVA[7..0] = DCOL[]; + WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]); + WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]); + END CASE; + +-- BRVA[10..8] = (x_mode4,RBRVA[9..8]); + RBRVA[].clk = CLK42; + + CASE (BORD,X_MODE4) IS + WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]); + WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]); + END CASE; + + RBRVA[9..8].clrn = !BORD; + RBRVA[10].prn = !BORD; + + CASE (RBRVA[9..8],BRVA7) IS + WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]); + WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]); + END CASE; + +-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE)); +-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE)); + + V_WE_R = DFF(GND,!CLK42,,!V_WE); + V_WE.prn = V_WE_R; + V_WET[].prn = V_WE_R; + +-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + +-- V_WR[] = (V_WE) or !( + + V_WEX.clk = CLK42; +-- V_WEX.d = V_WE; +-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX)); + + + + + V_WEMMM = LCELL(V_WE); + V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok + V_WEMMO = LCELL(V_WEMMN); -- green arts + V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts + V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??) + V_WEMMS = LCELL(V_WEMMR); +-- V_WEMMT = LCELL(V_WEMMS); +-- V_WEMMU = LCELL(V_WEMMT); +-- V_WEMMV = LCELL(V_WEMMU); +-- V_WEMMW = LCELL(V_WEMMV); +-- V_WEMMX = LCELL(V_WEMMW); +-- V_WEMMY = LCELL(V_WEMMX); +-- V_WEMMZ = LCELL(V_WEMMY); + + V_WRM = LCELL(V_WE or V_WEMMM); +-- V_WRM = LCELL(V_WEMMN or V_WEMMM); +-- V_WRM2 = LCELL(V_WEMMN or V_WEMMM); +-- V_WRM2 = LCELL(V_WEMMR); +-- V_WRM = LCELL(V_WEMMM or V_WEMMN); +-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN); + + V_WEM = (V_WE); +-- V_WEM2 = LCELL(V_WE); +-- V_WEM = LCELL(V_WEMMM & V_WEMMN); +-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO); + + F_WR = DFF(VCC,V_WE,,); + V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,); + V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,); + V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,); + V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,); + + +-- V_WR_3 = LCELL(V_WRM or V_EN3); +-- V_WR_2 = LCELL(V_WRM or V_EN2); +-- V_WR_1 = LCELL(V_WRM or V_EN1); +-- V_WR_0 = LCELL(V_WRM or V_EN0); + V_WR_3 = LCELL(LCELL(LCELL(V_WRM or V_EN3))); + V_WR_2 = LCELL(LCELL(LCELL(V_WRM or V_EN2))); + V_WR_1 = LCELL(LCELL(LCELL(V_WRM or V_EN1))); + V_WR_0 = LCELL(LCELL(LCELL(V_WRM or V_EN0))); + + V_WEY3 = LCELL(V_WEM or V_EN3); + V_WEY2 = LCELL(V_WEM or V_EN2); + V_WEY1 = LCELL(V_WEM or V_EN1); + V_WEY0 = LCELL(V_WEM or V_EN0); + + V_WR[] = V_WR_[]; -- V_WR0-3 + V_WEN[] = V_WEY[]; -- VD0-3 + + + + + +% + V_WEMMM = LCELL(V_WE); + V_WEMMN = LCELL(V_WEMMM); + V_WEMMO = LCELL(V_WEMMN); + V_WEMM = LCELL(V_WEMMO); + + V_WRM = LCELL(V_WEMMN & V_WEMMM); + V_WRM2 = LCELL(V_WEMMN & V_WEMMM); + + V_WEM = LCELL(V_WEMMM & V_WEMMO); + V_WEM2 = LCELL(V_WEMMM & V_WEMMO); + + V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)),CLK42,F_WR,); + V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,); + V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)) ,CLK42,F_WR,); + V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,); + + F_WR = DFF(VCC,V_WE,,); + + V_WR_3 = V_WRM or V_EN3; + V_WR_2 = V_WRM2 or V_EN2; + V_WR_1 = V_WRM or V_EN1; + V_WR_0 = V_WRM or V_EN0; + + V_WEY3 = V_WEM or V_EN3; + V_WEY2 = V_WEM2 or V_EN2; + V_WEY1 = V_WEM or V_EN1; + V_WEY0 = V_WEM or V_EN0; + + V_WR[] = V_WR_[]; + V_WEN[] = V_WEY[]; +% + + + + + +-- CLK84 = LCELL(CLK42 xor CLK84_X); +-- CLK84_X = DFF(!CLK84_X,CLK84,,); +-- CLK84_Y = CLK84; + +END GENERATE; -- end "sprinter" mode + + +END; diff --git a/src/altera/acex/k30/VIDEO2_T2_51mhz.TDF b/src/altera/acex/k30/VIDEO2_T2_51mhz.TDF new file mode 100644 index 0000000..baba4fa --- /dev/null +++ b/src/altera/acex/k30/VIDEO2_T2_51mhz.TDF @@ -0,0 +1,783 @@ + + TITLE "Video-controller"; + +INCLUDE "lpm_ram_dp"; + +PARAMETERS + ( + MODE = "SPRINTER", + MOUSE = "NO", + HOR_PLACE = H"50", + VER_PLACE = H"91" -- 122h/2 + ); + +SUBDESIGN video2 + ( + CLK42 : INPUT; + + CT[5..0] : OUTPUT; + CTH[5..0] : OUTPUT; + CTV[8..0] : OUTPUT; + CTF[6..0] : OUTPUT; + + BLANK : OUTPUT; + + START_UP : INPUT; + COPY_SINC_H : INPUT; + COPY_SINC_V : INPUT; + + WR : INPUT; + + VAI[19..0] : INPUT; -- input screen adress + + VAO[15..0] : OUTPUT; + + D[7..0] : INPUT; + MDI[15..0] : INPUT; + + VDO0[7..0] : OUTPUT; + VDO1[7..0] : OUTPUT; + VDO2[7..0] : OUTPUT; + VDO3[7..0] : OUTPUT; + + VDM0[7..0] : INPUT; + VDM1[7..0] : INPUT; + VDM2[7..0] : INPUT; + VDM3[7..0] : INPUT; + + V_WR[3..0] : OUTPUT; + V_WEN[3..0] : OUTPUT; + + V_CS[1..0] : OUTPUT; + WR_PIX : OUTPUT; + +-- ZX_COLOR[3..0] : OUTPUT; + + ZX_PORT[7..0] : INPUT; + DIR_PORT[7..0] : INPUT; + +% + bit0 - Spectrum SCREEN Switch + bit1 - Spectrum Adress MODE + bit2 - Write to Spectrum Screen OFF + bit3 - MODE page 0/1 + bit4 - MODE on/off screen + + bit7..5 - Border +% + + INTT : OUTPUT; + + DOUBLE_CAS : INPUT; + + MOUSE_X[9..0] : INPUT; + MOUSE_Y[9..0] : INPUT; + + + ) +VARIABLE + +-- CLK84 : NODE; +-- CLK84_X : NODE; +-- CLK84_Y : NODE; + + ZX_COLOR[3..0] : NODE; + + CT[5..0] : DFFE; + CTH[5..0] : DFFE; + CTV[8..0] : DFFE; + CTF[6..0] : DFF; + + VXA[19..0] : DFFE; + + VXD0[7..0] : DFFE; + VXD1[7..0] : DFFE; + VXD2[7..0] : DFFE; + VXD3[7..0] : DFFE; + + E_WR : NODE; + E_WRD : NODE; + + BLANK : NODE; + BORD : NODE; +-- INTT_T : NODE; + INTTX : NODE; + + VLA[17..0] : DFF; +-- SVA[17..0] : NODE; + SVA[17..0] : DFF; +-- RSVA[8..0] : LCELL; + RSVA[8..0] : NODE; +-- RSVA[8..0] : DFF; + + V_CST[1..0] : DFF; + VCM[2..0] : DFF; + TSN_W3 : DFF; + V_WE : DFF; + V_WEX : DFF; + + V_WEM : NODE; + V_WEM2 : NODE; + V_WRM : NODE; + V_WRM2 : NODE; +% + V_WEMM : NODE; + V_WEMMM : NODE; + V_WEMMN : NODE; + V_WEMMO : NODE; +% + V_WEMM : NODE; + V_WEMMM : NODE; + V_WEMMN : NODE; + V_WEMMO : NODE; + V_WEMMP : NODE; + V_WEMMQ : NODE; + V_WEMMR : NODE; + V_WEMMS : NODE; + V_WEMMT : NODE; + V_WEMMU : NODE; + V_WEMMV : NODE; + V_WEMMW : NODE; + V_WEMMX : NODE; + V_WEMMY : NODE; + V_WEMMZ : NODE; + + + + V_WET[3..0] : DFF; + + D_PIC0[7..0] : DFFE; +-- D_PIC0_[7..0] : LCELL; + + D_PIC0_[7..0] : DFFE; + D_PIC1_[7..0] : DFFE; + D_PIC2_[7..0] : DFFE; + D_PIC3_[7..0] : DFFE; + + D_PICX_[7..0] : NODE; + + LWR_PIC : NODE; + LWR_COL : NODE; + + WR_PIC : DFF; + WR_COL : DFF; + LD_PIC : NODE; +MXL: NODE; +MXR: NODE; + + RBRVA[10..8]: DFF; + BRVA[7..0] : DFF; + DCOL[7..0] : DFFE; + + MXWE : NODE; +-- MXCE : NODE; + + AX128 : NODE; + + BRD[2..0] : NODE; + + ZX_COL[3..0] : LCELL; + + ZXA15 : NODE; + ZXS[5..0] : NODE; + ZX_SCREEN : NODE; + SCR128 : NODE; + + MODE0[7..0] : DFFE; + MODE1[7..0] : DFFE; + MODE2[7..0] : DFFE; +-- MODE3[7..0] : DFF; + + WR_MODE : DFF; + LWR_MODE : NODE; + X_MODE[7..4]: NODE; + X_MODE_BOND : NODE; + +-- M_CTV[2..0] : DFF; +-- M_CT[5..3] : DFF; + M_CTV[2..0] : LCELL; + M_CT[5..3] : LCELL; + + DOUBLE : DFFE; + + PIC_CLK : NODE; + + MS_X[9..0] : DFF; + MS_Y[9..0] : DFF; + + MS_POINT : NODE; + MS_POINT2 : NODE; + MS_PNT : NODE; + + MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF"); + + SCR_ENA : DFFE; + V_WR_[3..0] : LCELL; + V_WEY[3..0] : LCELL; + + V_WE_R : NODE; + + V_CSX[3..0] : NODE; + + V_EN[3..0] : NODE; + + F_WR : NODE; + +BEGIN + + DEFAULTS + WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC; + V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC; + V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC; + V_WET[].d = VCC; + END DEFAULTS; + + ZX_COLOR[] = ZX_COL[]; + +-- === MOUSE counters ======== + + MS_X[].clk = !CT1; + CASE LCELL(CTH[5..2] == 12) IS + WHEN 0 => MS_X[] = MS_X[] + 1; + WHEN 1 => MS_X[] = (!MOUSE_X[9..0]); + END CASE; + + MS_Y[].clk = !CTH5; + CASE LCELL(CTV8 & !CTV5 & CTV4) IS + WHEN 0 => MS_Y[] = MS_Y[] + 1; + WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]); + END CASE; + + MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,); + + MS_DAT.wren = GND; + MS_DAT.data[] = GND; + MS_DAT.wraddress[] = GND; + MS_DAT.wrclock = CLK42; + MS_DAT.wrclken = GND; + MS_DAT.rden = VCC; + MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]); + MS_DAT.rdclock = CLK42; + MS_DAT.rdclken = VCC; + + IF MOUSE == "NO" GENERATE + MS_POINT = GND; + MS_POINT2 = GND; + ELSE GENERATE + MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,); + MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,); + END GENERATE; + +-- === Sinc-counts GENERATOR ============================================ + +-- CT[].clrn = START_UP; + +-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE; +-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE; + +-- CTV[].clrn = !COPY_SINC_V or VER_PLACE; +-- CTV[].prn = !COPY_SINC_V or !VER_PLACE; + + CT[5].clrn = !COPY_SINC_H; + + -- set CTH to 50 (32h) + CTH[0].clrn = !COPY_SINC_H; + CTH[1].prn = !COPY_SINC_H; + CTH[2].clrn = !COPY_SINC_H; + CTH[3].clrn = !COPY_SINC_H; + CTH[4].prn = !COPY_SINC_H; + CTH[5].prn = !COPY_SINC_H; + + -- set CTV to 122h + CTV[0].clrn = !COPY_SINC_V; + CTV[1].prn = !COPY_SINC_V; + CTV[3..2].clrn = !COPY_SINC_V; + + CTV[4].clrn = !COPY_SINC_V; + CTV[5].prn = !COPY_SINC_V; + CTV[7..6].clrn = !COPY_SINC_V; + CTV[8].prn = !COPY_SINC_V; + + CT[5..0].clk = CLK42; + CTH[5..0].clk = CLK42; + CTV[8..0].clk = CLK42; + + CT[2..0].ena = VCC; + + CASE CT[2..0] IS + WHEN 0 => CT[2..0] = 1; + WHEN 1 => CT[2..0] = 2; + WHEN 2 => CT[2..0] = 4; + WHEN 3 => CT[2..0] = 4; + WHEN 4 => CT[2..0] = 5; + WHEN 5 => CT[2..0] = 6; + WHEN 6 => CT[2..0] = 0; + WHEN 7 => CT[2..0] = 0; + END CASE; + + -- for remove sinc jitter +-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,); + CT[5..3].ena = DFF((CT0 & CT2),CLK42,,); + CT[5..3] = CT[5..3]+1; +% + CASE CT[4..3] IS + WHEN 0 => CT[5..3] = CT[5..3]+1; + WHEN 1 => CT[5..3] = CT[5..3]+1; + WHEN 2 => CT[5..3] = CT[5..3]+1; + WHEN 3 => CT[5..3] = CT[5..3]+1; + END CASE; +% + CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,); + CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,); + + IF CTH[] == 55 THEN + CTH[] = GND; + ELSE + CTH[] = CTH[] + 1; + END IF; + + IF CTV[] == 319 THEN + CTV[] = GND; + ELSE + CTV[] = CTV[] + 1; + END IF; + + CTF[].clk = CTV8; + CTF[] = CTF[]+1; + +-- ==== Video ========================================================== + + ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens + ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write + ZXA15 = ZX_PORT7; -- ZX A15' line + + SCR128 = DIR_PORT0; + +-- WR_PIX = LCELL(TSN_W3); + WR_PIX = TSN_W3; + + DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS; + VXA[].clk = CLK42; VXA[].ena = !E_WR; + + VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[]; + VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[]; + VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[]; + VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[]; + +-- VXD0[] = D[]; +-- VXD1[] = D[]; +-- VXD2[] = D[]; +-- VXD3[] = D[]; + + (VXD0[],VXD1[]) = MDI[]; + (VXD2[],VXD3[]) = MDI[]; + + BRD[] = DIR_PORT[7..5]; + + VCM[].clk = CLK42; + TSN_W3.clk = CLK42; + V_CST[].clk = CLK42; + V_WE.clk = CLK42; + V_WET[].clk = CLK42; + VLA[].clk = CLK42; + + SCR_ENA.clk = CLK42; + SCR_ENA.ena = !E_WR; + SCR_ENA.d = !(VAI19 or ZX_SCREEN); + + E_WRD = DFF(E_WR,CLK42,,); + E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,)); +-- E_WR = LCELL(WR or !DFF(WR,CLK42,,)); + +-- **************************************************** + +IF MODE == "SPRINTER" GENERATE + +-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode + +-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE); + MXWE = DFF(MXWE,CLK42,E_WR,V_WE); + + IF VAI[19] THEN + -- in graf mode all 256k(512k) range + VXA[] = VAI[]; + ELSE + -- in spectrum mode 8k/16k range pages + VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]); + END IF; + +-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,); +-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,); +-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,); + + BORD = DFF((MODE0[7..4] == 15),LWR_COL,,); + BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,); + INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,); + + INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,); + +-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,); +-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]); + + CASE CT[2..0] IS + WHEN B"110" => VCM[2..0].d = 5; -- 110 -> 101 6 -> 5 + WHEN B"000" => VCM[2..0].d = 1; -- 000 -> 001 0 -> 1 + WHEN B"001" => VCM[2..0].d = 4; -- 001 -> 100 1 -> 4 + WHEN B"010" => VCM[2..0].d = 3; -- 010 -> 011 2 -> 3 + WHEN B"100" => VCM[2..0].d = 2; -- 100 -> 010 4 -> 2 + WHEN B"101" => VCM[2..0].d = 0; -- 101 -> 000 5 -> 0 + END CASE; + + CASE VCM[1..0] IS + WHEN 0 => + VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + +TSN_W3.d = X_MODE_BOND; +% + IF VCM2 THEN +-- TSN_W3.d = X_MODE5; + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE5); + ELSE + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE_BOND); + END IF; +% + + WHEN 1 => + WR_PIC.d = !VCM2; + WR_COL.d = VCM2; + VLA[].d = SVA[]; + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + WHEN 2 => + VLA[].d = VXA[17..0]; + V_CST[].d = (!VXA18,VXA18) or MXWE; + V_WE.d = MXWE; + V_WEX.d = GND; + V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + WHEN 3 => +-- WR_PIC.d = X_MODE5; +-- NEW 26.08.2022, fix bug with first column +-- it was reproducing when changes mode 320 -> 640, like any 320px screen squares -> text mode squares + WR_PIC.d = MODE0[5]; + VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND); + WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + END CASE; + +-- choose V-RAM komplect + + V_CST1.prn = GND; +-- V_CS0.clrn = GND; + V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0))); + V_CS1 = VCC; +-- V_CS0 = LCELL(V_CST0); + + V_CSX0 = LCELL(!CLK42); + V_CSX1 = LCELL(V_CSX0); + V_CSX2 = LCELL(V_CSX1 & V_CSX0); + V_CSX3 = LCELL(V_CSX2); + +-- V_CS0 = V_CSX3; + V_CS0 = GND; + +-- ===================== + + SVA[].clk = CLK42; + SVA[9..6] = MODE0[3..0]; +-- RSVA[].clk = CLK42; + (SVA[12..10],SVA[5..0]) = RSVA[]; + +-- M_CTV[2..0].clk = CLK42; +-- M_CT[5..3].clk = CLK42; + M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]); + M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]); + + CASE (!VCM2,MODE0[4]) IS +-- CASE (!VCM1,MODE0[4]) IS + WHEN B"X0" => + -- Graf adress -- + RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = CTV[2..0]; +-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]); + WHEN B"01" => + -- ZX-atr adress -- + RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]); + SVA[17..13] = MODE2[7..3]; + +-- SVA[12..10] = MODE2[2..0]; +-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]); + WHEN B"11" => + -- ZX-pic adress -- + RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = MODE1[2..0]; +-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + END CASE; + +-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC)); + X_MODE_BOND = GND; + +-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + + +-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS + +-- D_PIC0_[].clk = !CLK42; +-- D_PIC1_[].clk = !CLK42; +-- D_PIC2_[].clk = !CLK42; +-- D_PIC3_[].clk = !CLK42; + +-- PIC_CLK = LCELL(LCELL(CLK42)); + PIC_CLK = !CLK42; + + D_PIC0_[].clk = PIC_CLK; + D_PIC1_[].clk = PIC_CLK; + D_PIC2_[].clk = PIC_CLK; + D_PIC3_[].clk = PIC_CLK; + + D_PIC0_[] = VDM0[]; + D_PIC1_[] = VDM1[]; + D_PIC2_[] = VDM2[]; + D_PIC3_[] = VDM3[]; + + CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS + WHEN 0 => D_PICX_[] = D_PIC0_[]; + WHEN 1 => D_PICX_[] = D_PIC1_[]; + WHEN 2 => D_PICX_[] = D_PIC2_[]; + WHEN 3 => D_PICX_[] = D_PIC3_[]; + END CASE; + + MODE0[].ena = VCC; + MODE1[].ena = VCC; + MODE2[].ena = VCC; + MODE0[].clk = LWR_MODE; + MODE1[].clk = LWR_MODE; + MODE2[].clk = LWR_MODE; + MODE0[].d = VDM3[]; + MODE1[].d = VDM2[]; + MODE2[].d = VDM1[]; + LWR_MODE = LCELL(LCELL(WR_MODE)); +% + MODE0[].ena = LWR_MODE; + MODE1[].ena = LWR_MODE; + MODE2[].ena = LWR_MODE; + MODE0[].clk = CLK42; + MODE1[].clk = CLK42; + MODE2[].clk = CLK42; + MODE0[].d = D_PIC3_[]; + MODE1[].d = D_PIC2_[]; + MODE2[].d = D_PIC1_[]; + LWR_MODE = DFF(!WR_MODE,CLK42,,); +% + X_MODE7 = DFF(MODE0[7],LWR_COL,,); + X_MODE6 = DFF(MODE0[6],LWR_COL,,); + X_MODE5 = DFF(MODE0[5],LWR_COL,,); + X_MODE4 = DFF(MODE0[4],LWR_COL,,); + + VAO[] = VLA[17..2]; + + WR_PIC.clk = CLK42; + WR_COL.clk = CLK42; + WR_MODE.clk = CLK42; + +-- LWR_PIC = LCELL(LCELL(WR_PIC)); +-- LWR_COL = LCELL(LCELL(WR_COL)); +-- LWR_PIC = LCELL(WR_PIC); +-- LWR_COL = LCELL(WR_COL); + LWR_PIC = DFF(WR_PIC,CLK42,,); + LWR_COL = DFF(WR_COL,CLK42,,); + +-- D_PIC0[].ena = VCC; +-- D_PIC0[].clk = (LWR_PIC); + D_PIC0[].ena = !LWR_PIC; + D_PIC0[].clk = CLK42; + + + + + IF LD_PIC THEN +-- D_PIC0[] = D_PIC0_[]; + D_PIC0[] = D_PICX_[]; + ELSE + D_PIC0[] = (D_PIC0[6..0],GND); + END IF; + + +-- DCOL[].clk = (LWR_COL); + DCOL[].ena = !LWR_COL; + DCOL[].clk = CLK42; + + IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN + DCOL[].d = (B"00",BRD[2..0],BRD[2..0]); + ELSE +-- DCOL[].d = D_PIC0_[]; + DCOL[].d = D_PICX_[]; + END IF; + + DCOL[].clrn = !BLANK; + + BRVA[].clk = CLK42; + BRVA[].clrn = !MS_POINT; + BRVA[].prn = !MS_POINT2; + +-- MODE0[4] - graph / text +-- MODE0[5] - 320 / 640 resolution + +-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS + CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS + WHEN B"1X" => BRVA[7..0] = DCOL[]; + WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]); + WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]); + END CASE; + +-- BRVA[10..8] = (x_mode4,RBRVA[9..8]); + RBRVA[].clk = CLK42; + + CASE (BORD,X_MODE4) IS + WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]); + WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]); + END CASE; + + RBRVA[9..8].clrn = !BORD; + RBRVA[10].prn = !BORD; + + CASE (RBRVA[9..8],BRVA7) IS + WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]); + WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]); + END CASE; + +-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE)); +-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE)); + + V_WE_R = DFF(GND,!CLK42,,!V_WE); + V_WE.prn = V_WE_R; + V_WET[].prn = V_WE_R; + +-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + +-- V_WR[] = (V_WE) or !( + + V_WEX.clk = CLK42; +-- V_WEX.d = V_WE; +-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX)); + + + + + V_WEMMM = LCELL(V_WE); +-- V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok +-- V_WEMMO = LCELL(V_WEMMN); -- green arts +-- V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts +-- V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??) +-- V_WEMMS = LCELL(V_WEMMR); +-- V_WEMMT = LCELL(V_WEMMS); +-- V_WEMMU = LCELL(V_WEMMT); +-- V_WEMMV = LCELL(V_WEMMU); +-- V_WEMMW = LCELL(V_WEMMV); +-- V_WEMMX = LCELL(V_WEMMW); +-- V_WEMMY = LCELL(V_WEMMX); +-- V_WEMMZ = LCELL(V_WEMMY); + + V_WRM = LCELL(V_WE or V_WEMMM); + + +-- V_WRM = LCELL(V_WEMMN or V_WEMMM); +-- V_WRM2 = LCELL(V_WEMMN or V_WEMMM); +-- V_WRM2 = LCELL(V_WEMMR); +-- V_WRM = LCELL(V_WEMMM or V_WEMMN); +-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN); + + V_WEM = (V_WE); + +-- V_WEM2 = LCELL(V_WE); +-- V_WEM = LCELL(V_WEMMM & V_WEMMN); +-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO); + +--- LWR_COL = DFF(WR_COL,CLK42,,); + F_WR = (LCELL(LCELL(LCELL(LCELL(DFF(VCC,V_WE,,)))))); +--- F_WR = DFF(V_WE,CLK42,,); + V_WEMMZ = LCELL(CLK42); + V_EN3 = (DFF(!(!VXA1 & LCELL(!VXA0 or DOUBLE)), V_WEMMZ, F_WR,)); + V_EN2 = (DFF(!(!VXA1 & LCELL(VXA0 or DOUBLE)), V_WEMMZ, F_WR,)); + V_EN1 = (DFF(!(VXA1 & LCELL(!VXA0 or DOUBLE)), V_WEMMZ, F_WR,)); + V_EN0 = (DFF(!(VXA1 & LCELL(VXA0 or DOUBLE)), V_WEMMZ, F_WR,)); + + +-- V_WR_3 = LCELL(V_WRM or V_EN3); +-- V_WR_2 = LCELL(V_WRM or V_EN2); +-- V_WR_1 = LCELL(V_WRM or V_EN1); +-- V_WR_0 = LCELL(V_WRM or V_EN0); + V_WR_3 = LCELL(LCELL(LCELL(LCELL(V_WE or V_EN3)))); + V_WR_2 = LCELL(LCELL(LCELL(LCELL(V_WE or V_EN2)))); + V_WR_1 = LCELL(LCELL(LCELL(LCELL(V_WE or V_EN1)))); + V_WR_0 = LCELL(LCELL(LCELL(LCELL(V_WE or V_EN0)))); + + V_WEY3 = LCELL(V_WE or V_EN3); + V_WEY2 = LCELL(V_WE or V_EN2); + V_WEY1 = LCELL(V_WE or V_EN1); + V_WEY0 = LCELL(V_WE or V_EN0); + + V_WR[] = V_WR_[]; -- V_WR0-3 + V_WEN[] = V_WEY[]; -- VD0-3 + + + + + +% + V_WEMMM = LCELL(V_WE); + V_WEMMN = LCELL(V_WEMMM); + V_WEMMO = LCELL(V_WEMMN); + V_WEMM = LCELL(V_WEMMO); + + V_WRM = LCELL(V_WEMMN & V_WEMMM); + V_WRM2 = LCELL(V_WEMMN & V_WEMMM); + + V_WEM = LCELL(V_WEMMM & V_WEMMO); + V_WEM2 = LCELL(V_WEMMM & V_WEMMO); + + V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)),CLK42,F_WR,); + V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,); + V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)) ,CLK42,F_WR,); + V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,); + + F_WR = DFF(VCC,V_WE,,); + + V_WR_3 = V_WRM or V_EN3; + V_WR_2 = V_WRM2 or V_EN2; + V_WR_1 = V_WRM or V_EN1; + V_WR_0 = V_WRM or V_EN0; + + V_WEY3 = V_WEM or V_EN3; + V_WEY2 = V_WEM2 or V_EN2; + V_WEY1 = V_WEM or V_EN1; + V_WEY0 = V_WEM or V_EN0; + + V_WR[] = V_WR_[]; + V_WEN[] = V_WEY[]; +% + + + + + +-- CLK84 = LCELL(CLK42 xor CLK84_X); +-- CLK84_X = DFF(!CLK84_X,CLK84,,); +-- CLK84_Y = CLK84; + +END GENERATE; -- end "sprinter" mode + + +END; diff --git a/src/altera/acex/k30/VIDEO2_T2_dip_stable.TDF b/src/altera/acex/k30/VIDEO2_T2_dip_stable.TDF new file mode 100644 index 0000000..ea1e862 --- /dev/null +++ b/src/altera/acex/k30/VIDEO2_T2_dip_stable.TDF @@ -0,0 +1,783 @@ + + TITLE "Video-controller"; + +INCLUDE "lpm_ram_dp"; + +PARAMETERS + ( + MODE = "SPRINTER", + MOUSE = "NO", + HOR_PLACE = H"50", + VER_PLACE = H"91" -- 122h/2 + ); + +SUBDESIGN video2 + ( + CLK42 : INPUT; + + CT[5..0] : OUTPUT; + CTH[5..0] : OUTPUT; + CTV[8..0] : OUTPUT; + CTF[6..0] : OUTPUT; + + BLANK : OUTPUT; + + START_UP : INPUT; + COPY_SINC_H : INPUT; + COPY_SINC_V : INPUT; + + WR : INPUT; + + VAI[19..0] : INPUT; -- input screen adress + + VAO[15..0] : OUTPUT; + + D[7..0] : INPUT; + MDI[15..0] : INPUT; + + VDO0[7..0] : OUTPUT; + VDO1[7..0] : OUTPUT; + VDO2[7..0] : OUTPUT; + VDO3[7..0] : OUTPUT; + + VDM0[7..0] : INPUT; + VDM1[7..0] : INPUT; + VDM2[7..0] : INPUT; + VDM3[7..0] : INPUT; + + V_WR[3..0] : OUTPUT; + V_WEN[3..0] : OUTPUT; + + V_CS[1..0] : OUTPUT; + WR_PIX : OUTPUT; + +-- ZX_COLOR[3..0] : OUTPUT; + + ZX_PORT[7..0] : INPUT; + DIR_PORT[7..0] : INPUT; + +% + bit0 - Spectrum SCREEN Switch + bit1 - Spectrum Adress MODE + bit2 - Write to Spectrum Screen OFF + bit3 - MODE page 0/1 + bit4 - MODE on/off screen + + bit7..5 - Border +% + + INTT : OUTPUT; + + DOUBLE_CAS : INPUT; + + MOUSE_X[9..0] : INPUT; + MOUSE_Y[9..0] : INPUT; + + + ) +VARIABLE + +-- CLK84 : NODE; +-- CLK84_X : NODE; +-- CLK84_Y : NODE; + + ZX_COLOR[3..0] : NODE; + + CT[5..0] : DFFE; + CTH[5..0] : DFFE; + CTV[8..0] : DFFE; + CTF[6..0] : DFF; + + VXA[19..0] : DFFE; + + VXD0[7..0] : DFFE; + VXD1[7..0] : DFFE; + VXD2[7..0] : DFFE; + VXD3[7..0] : DFFE; + + E_WR : NODE; + E_WRD : NODE; + + BLANK : NODE; + BORD : NODE; +-- INTT_T : NODE; + INTTX : NODE; + + VLA[17..0] : DFF; +-- SVA[17..0] : NODE; + SVA[17..0] : DFF; +-- RSVA[8..0] : LCELL; + RSVA[8..0] : NODE; +-- RSVA[8..0] : DFF; + + V_CST[1..0] : DFF; + VCM[2..0] : DFF; + TSN_W3 : DFF; + V_WE : DFF; + V_WEX : DFF; + + V_WEM : NODE; + V_WEM2 : NODE; + V_WRM : NODE; + V_WRM2 : NODE; +% + V_WEMM : NODE; + V_WEMMM : NODE; + V_WEMMN : NODE; + V_WEMMO : NODE; +% + V_WEMM : NODE; + V_WEMMM : NODE; + V_WEMMN : NODE; + V_WEMMO : NODE; + V_WEMMP : NODE; + V_WEMMQ : NODE; + V_WEMMR : NODE; + V_WEMMS : NODE; + V_WEMMT : NODE; + V_WEMMU : NODE; + V_WEMMV : NODE; + V_WEMMW : NODE; + V_WEMMX : NODE; + V_WEMMY : NODE; + V_WEMMZ : NODE; + + + + V_WET[3..0] : DFF; + + D_PIC0[7..0] : DFFE; +-- D_PIC0_[7..0] : LCELL; + + D_PIC0_[7..0] : DFFE; + D_PIC1_[7..0] : DFFE; + D_PIC2_[7..0] : DFFE; + D_PIC3_[7..0] : DFFE; + + D_PICX_[7..0] : NODE; + + LWR_PIC : NODE; + LWR_COL : NODE; + + WR_PIC : DFF; + WR_COL : DFF; + LD_PIC : NODE; +MXL: NODE; +MXR: NODE; + + RBRVA[10..8]: DFF; + BRVA[7..0] : DFF; + DCOL[7..0] : DFFE; + + MXWE : NODE; +-- MXCE : NODE; + + AX128 : NODE; + + BRD[2..0] : NODE; + + ZX_COL[3..0] : LCELL; + + ZXA15 : NODE; + ZXS[5..0] : NODE; + ZX_SCREEN : NODE; + SCR128 : NODE; + + MODE0[7..0] : DFFE; + MODE1[7..0] : DFFE; + MODE2[7..0] : DFFE; +-- MODE3[7..0] : DFF; + + WR_MODE : DFF; + LWR_MODE : NODE; + X_MODE[7..4]: NODE; + X_MODE_BOND : NODE; + +-- M_CTV[2..0] : DFF; +-- M_CT[5..3] : DFF; + M_CTV[2..0] : LCELL; + M_CT[5..3] : LCELL; + + DOUBLE : DFFE; + + PIC_CLK : NODE; + + MS_X[9..0] : DFF; + MS_Y[9..0] : DFF; + + MS_POINT : NODE; + MS_POINT2 : NODE; + MS_PNT : NODE; + + MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF"); + + SCR_ENA : DFFE; + V_WR_[3..0] : LCELL; + V_WEY[3..0] : LCELL; + + V_WE_R : NODE; + + V_CSX[3..0] : NODE; + + V_EN[3..0] : NODE; + + F_WR : NODE; + +BEGIN + + DEFAULTS + WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC; + V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC; + V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC; + V_WET[].d = VCC; + END DEFAULTS; + + ZX_COLOR[] = ZX_COL[]; + +-- === MOUSE counters ======== + + MS_X[].clk = !CT1; + CASE LCELL(CTH[5..2] == 12) IS + WHEN 0 => MS_X[] = MS_X[] + 1; + WHEN 1 => MS_X[] = (!MOUSE_X[9..0]); + END CASE; + + MS_Y[].clk = !CTH5; + CASE LCELL(CTV8 & !CTV5 & CTV4) IS + WHEN 0 => MS_Y[] = MS_Y[] + 1; + WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]); + END CASE; + + MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,); + + MS_DAT.wren = GND; + MS_DAT.data[] = GND; + MS_DAT.wraddress[] = GND; + MS_DAT.wrclock = CLK42; + MS_DAT.wrclken = GND; + MS_DAT.rden = VCC; + MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]); + MS_DAT.rdclock = CLK42; + MS_DAT.rdclken = VCC; + + IF MOUSE == "NO" GENERATE + MS_POINT = GND; + MS_POINT2 = GND; + ELSE GENERATE + MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,); + MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,); + END GENERATE; + +-- === Sinc-counts GENERATOR ============================================ + +-- CT[].clrn = START_UP; + +-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE; +-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE; + +-- CTV[].clrn = !COPY_SINC_V or VER_PLACE; +-- CTV[].prn = !COPY_SINC_V or !VER_PLACE; + + CT[5].clrn = !COPY_SINC_H; + + -- set CTH to 50 (32h) + CTH[0].clrn = !COPY_SINC_H; + CTH[1].prn = !COPY_SINC_H; + CTH[2].clrn = !COPY_SINC_H; + CTH[3].clrn = !COPY_SINC_H; + CTH[4].prn = !COPY_SINC_H; + CTH[5].prn = !COPY_SINC_H; + + -- set CTV to 122h + CTV[0].clrn = !COPY_SINC_V; + CTV[1].prn = !COPY_SINC_V; + CTV[3..2].clrn = !COPY_SINC_V; + + CTV[4].clrn = !COPY_SINC_V; + CTV[5].prn = !COPY_SINC_V; + CTV[7..6].clrn = !COPY_SINC_V; + CTV[8].prn = !COPY_SINC_V; + + CT[5..0].clk = CLK42; + CTH[5..0].clk = CLK42; + CTV[8..0].clk = CLK42; + + CT[2..0].ena = VCC; + + CASE CT[2..0] IS + WHEN 0 => CT[2..0] = 1; + WHEN 1 => CT[2..0] = 2; + WHEN 2 => CT[2..0] = 4; + WHEN 3 => CT[2..0] = 4; + WHEN 4 => CT[2..0] = 5; + WHEN 5 => CT[2..0] = 6; + WHEN 6 => CT[2..0] = 0; + WHEN 7 => CT[2..0] = 0; + END CASE; + + -- for remove sinc jitter +-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,); + CT[5..3].ena = DFF((CT0 & CT2),CLK42,,); + CT[5..3] = CT[5..3]+1; +% + CASE CT[4..3] IS + WHEN 0 => CT[5..3] = CT[5..3]+1; + WHEN 1 => CT[5..3] = CT[5..3]+1; + WHEN 2 => CT[5..3] = CT[5..3]+1; + WHEN 3 => CT[5..3] = CT[5..3]+1; + END CASE; +% + CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,); + CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,); + + IF CTH[] == 55 THEN + CTH[] = GND; + ELSE + CTH[] = CTH[] + 1; + END IF; + + IF CTV[] == 319 THEN + CTV[] = GND; + ELSE + CTV[] = CTV[] + 1; + END IF; + + CTF[].clk = CTV8; + CTF[] = CTF[]+1; + +-- ==== Video ========================================================== + + ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens + ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write + ZXA15 = ZX_PORT7; -- ZX A15' line + + SCR128 = DIR_PORT0; + +-- WR_PIX = LCELL(TSN_W3); + WR_PIX = TSN_W3; + + DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS; + VXA[].clk = CLK42; VXA[].ena = !E_WR; + + VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[]; + VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[]; + VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[]; + VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[]; + +-- VXD0[] = D[]; +-- VXD1[] = D[]; +-- VXD2[] = D[]; +-- VXD3[] = D[]; + + (VXD0[],VXD1[]) = MDI[]; + (VXD2[],VXD3[]) = MDI[]; + + BRD[] = DIR_PORT[7..5]; + + VCM[].clk = CLK42; + TSN_W3.clk = CLK42; + V_CST[].clk = CLK42; + V_WE.clk = CLK42; + V_WET[].clk = CLK42; + VLA[].clk = CLK42; + + SCR_ENA.clk = CLK42; + SCR_ENA.ena = !E_WR; + SCR_ENA.d = !(VAI19 or ZX_SCREEN); + + E_WRD = DFF(E_WR,CLK42,,); + E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,)); +-- E_WR = LCELL(WR or !DFF(WR,CLK42,,)); + +-- **************************************************** + +IF MODE == "SPRINTER" GENERATE + +-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode + +-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE); + MXWE = DFF(MXWE,CLK42,E_WR,V_WE); + + IF VAI[19] THEN + -- in graf mode all 256k(512k) range + VXA[] = VAI[]; + ELSE + -- in spectrum mode 8k/16k range pages + VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]); + END IF; + +-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,); +-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,); +-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,); + + BORD = DFF((MODE0[7..4] == 15),LWR_COL,,); + BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,); + INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,); + + INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,); + +-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,); +-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]); + + CASE CT[2..0] IS + WHEN B"110" => VCM[2..0].d = 5; -- 110 -> 101 6 -> 5 + WHEN B"000" => VCM[2..0].d = 1; -- 000 -> 001 0 -> 1 + WHEN B"001" => VCM[2..0].d = 4; -- 001 -> 100 1 -> 4 + WHEN B"010" => VCM[2..0].d = 3; -- 010 -> 011 2 -> 3 + WHEN B"100" => VCM[2..0].d = 2; -- 100 -> 010 4 -> 2 + WHEN B"101" => VCM[2..0].d = 0; -- 101 -> 000 5 -> 0 + END CASE; + + CASE VCM[1..0] IS + WHEN 0 => + VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + +TSN_W3.d = X_MODE_BOND; +% + IF VCM2 THEN +-- TSN_W3.d = X_MODE5; + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE5); + ELSE + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE_BOND); + END IF; +% + + WHEN 1 => + WR_PIC.d = !VCM2; + WR_COL.d = VCM2; + VLA[].d = SVA[]; + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + WHEN 2 => + VLA[].d = VXA[17..0]; + V_CST[].d = (!VXA18,VXA18) or MXWE; + V_WE.d = MXWE; + V_WEX.d = GND; + V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + WHEN 3 => +-- WR_PIC.d = X_MODE5; +-- NEW 26.08.2022, fix bug with first column +-- it was reproducing when changes mode 320 -> 640, like any 320px screen squares -> text mode squares + WR_PIC.d = MODE0[5]; + VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND); + WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + END CASE; + +-- choose V-RAM komplect + + V_CST1.prn = GND; +-- V_CS0.clrn = GND; + V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0))); + V_CS1 = VCC; +-- V_CS0 = LCELL(V_CST0); + + V_CSX0 = LCELL(!CLK42); + V_CSX1 = LCELL(V_CSX0); + V_CSX2 = LCELL(V_CSX1 & V_CSX0); + V_CSX3 = LCELL(V_CSX2); + +-- V_CS0 = V_CSX3; + V_CS0 = GND; + +-- ===================== + + SVA[].clk = CLK42; + SVA[9..6] = MODE0[3..0]; +-- RSVA[].clk = CLK42; + (SVA[12..10],SVA[5..0]) = RSVA[]; + +-- M_CTV[2..0].clk = CLK42; +-- M_CT[5..3].clk = CLK42; + M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]); + M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]); + + CASE (!VCM2,MODE0[4]) IS +-- CASE (!VCM1,MODE0[4]) IS + WHEN B"X0" => + -- Graf adress -- + RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = CTV[2..0]; +-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]); + WHEN B"01" => + -- ZX-atr adress -- + RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]); + SVA[17..13] = MODE2[7..3]; + +-- SVA[12..10] = MODE2[2..0]; +-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]); + WHEN B"11" => + -- ZX-pic adress -- + RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = MODE1[2..0]; +-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + END CASE; + +-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC)); + X_MODE_BOND = GND; + +-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + + +-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS + +-- D_PIC0_[].clk = !CLK42; +-- D_PIC1_[].clk = !CLK42; +-- D_PIC2_[].clk = !CLK42; +-- D_PIC3_[].clk = !CLK42; + +-- PIC_CLK = LCELL(LCELL(CLK42)); + PIC_CLK = !CLK42; + + D_PIC0_[].clk = PIC_CLK; + D_PIC1_[].clk = PIC_CLK; + D_PIC2_[].clk = PIC_CLK; + D_PIC3_[].clk = PIC_CLK; + + D_PIC0_[] = VDM0[]; + D_PIC1_[] = VDM1[]; + D_PIC2_[] = VDM2[]; + D_PIC3_[] = VDM3[]; + + CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS + WHEN 0 => D_PICX_[] = D_PIC0_[]; + WHEN 1 => D_PICX_[] = D_PIC1_[]; + WHEN 2 => D_PICX_[] = D_PIC2_[]; + WHEN 3 => D_PICX_[] = D_PIC3_[]; + END CASE; + + MODE0[].ena = VCC; + MODE1[].ena = VCC; + MODE2[].ena = VCC; + MODE0[].clk = LWR_MODE; + MODE1[].clk = LWR_MODE; + MODE2[].clk = LWR_MODE; + MODE0[].d = VDM3[]; + MODE1[].d = VDM2[]; + MODE2[].d = VDM1[]; + LWR_MODE = LCELL(LCELL(WR_MODE)); +% + MODE0[].ena = LWR_MODE; + MODE1[].ena = LWR_MODE; + MODE2[].ena = LWR_MODE; + MODE0[].clk = CLK42; + MODE1[].clk = CLK42; + MODE2[].clk = CLK42; + MODE0[].d = D_PIC3_[]; + MODE1[].d = D_PIC2_[]; + MODE2[].d = D_PIC1_[]; + LWR_MODE = DFF(!WR_MODE,CLK42,,); +% + X_MODE7 = DFF(MODE0[7],LWR_COL,,); + X_MODE6 = DFF(MODE0[6],LWR_COL,,); + X_MODE5 = DFF(MODE0[5],LWR_COL,,); + X_MODE4 = DFF(MODE0[4],LWR_COL,,); + + VAO[] = VLA[17..2]; + + WR_PIC.clk = CLK42; + WR_COL.clk = CLK42; + WR_MODE.clk = CLK42; + +-- LWR_PIC = LCELL(LCELL(WR_PIC)); +-- LWR_COL = LCELL(LCELL(WR_COL)); +-- LWR_PIC = LCELL(WR_PIC); +-- LWR_COL = LCELL(WR_COL); + LWR_PIC = DFF(WR_PIC,CLK42,,); + LWR_COL = DFF(WR_COL,CLK42,,); + +-- D_PIC0[].ena = VCC; +-- D_PIC0[].clk = (LWR_PIC); + D_PIC0[].ena = !LWR_PIC; + D_PIC0[].clk = CLK42; + + + + + IF LD_PIC THEN +-- D_PIC0[] = D_PIC0_[]; + D_PIC0[] = D_PICX_[]; + ELSE + D_PIC0[] = (D_PIC0[6..0],GND); + END IF; + + +-- DCOL[].clk = (LWR_COL); + DCOL[].ena = !LWR_COL; + DCOL[].clk = CLK42; + + IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN + DCOL[].d = (B"00",BRD[2..0],BRD[2..0]); + ELSE +-- DCOL[].d = D_PIC0_[]; + DCOL[].d = D_PICX_[]; + END IF; + + DCOL[].clrn = !BLANK; + + BRVA[].clk = CLK42; + BRVA[].clrn = !MS_POINT; + BRVA[].prn = !MS_POINT2; + +-- MODE0[4] - graph / text +-- MODE0[5] - 320 / 640 resolution + +-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS + CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS + WHEN B"1X" => BRVA[7..0] = DCOL[]; + WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]); + WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]); + END CASE; + +-- BRVA[10..8] = (x_mode4,RBRVA[9..8]); + RBRVA[].clk = CLK42; + + CASE (BORD,X_MODE4) IS + WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]); + WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]); + END CASE; + + RBRVA[9..8].clrn = !BORD; + RBRVA[10].prn = !BORD; + + CASE (RBRVA[9..8],BRVA7) IS + WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]); + WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]); + END CASE; + +-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE)); +-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE)); + + V_WE_R = DFF(GND,!CLK42,,!V_WE); + V_WE.prn = V_WE_R; + V_WET[].prn = V_WE_R; + +-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + +-- V_WR[] = (V_WE) or !( + + V_WEX.clk = CLK42; +-- V_WEX.d = V_WE; +-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX)); + + + + + V_WEMMM = LCELL(V_WE); +-- V_WEMMN = LCELL(V_WEMMM); -- bios ok, fn ok, fnf1 failed, zx almost ok +-- V_WEMMO = LCELL(V_WEMMN); -- green arts +-- V_WEMMP = LCELL(V_WEMMO); -- blue + pink arts +-- V_WEMMR = LCELL(V_WEMMP); -- no F1 issue, but red arts (fix by finger, not enough capacity??) +-- V_WEMMS = LCELL(V_WEMMR); +-- V_WEMMT = LCELL(V_WEMMS); +-- V_WEMMU = LCELL(V_WEMMT); +-- V_WEMMV = LCELL(V_WEMMU); +-- V_WEMMW = LCELL(V_WEMMV); +-- V_WEMMX = LCELL(V_WEMMW); +-- V_WEMMY = LCELL(V_WEMMX); +-- V_WEMMZ = LCELL(V_WEMMY); + + V_WRM = LCELL(V_WE or V_WEMMM); + + +-- V_WRM = LCELL(V_WEMMN or V_WEMMM); +-- V_WRM2 = LCELL(V_WEMMN or V_WEMMM); +-- V_WRM2 = LCELL(V_WEMMR); +-- V_WRM = LCELL(V_WEMMM or V_WEMMN); +-- V_WRM2 = LCELL(V_WEMMM or V_WEMMN); + + V_WEM = (V_WE); + +-- V_WEM2 = LCELL(V_WE); +-- V_WEM = LCELL(V_WEMMM & V_WEMMN); +-- V_WEM2 = LCELL(V_WEMMM & V_WEMMO); + +--- LWR_COL = DFF(WR_COL,CLK42,,); + F_WR = ((LCELL(LCELL(LCELL(DFF(VCC,V_WE,,)))))); +--- F_WR = DFF(V_WE,CLK42,,); +-- V_WEMMZ = LCELL(CLK42); + V_EN3 = (DFF(!(!VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,)); + V_EN2 = (DFF(!(!VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,)); + V_EN1 = (DFF(!(VXA1 & (!VXA0 or DOUBLE)), CLK42, F_WR,)); + V_EN0 = (DFF(!(VXA1 & (VXA0 or DOUBLE)), CLK42, F_WR,)); + + +-- V_WR_3 = LCELL(V_WRM or V_EN3); +-- V_WR_2 = LCELL(V_WRM or V_EN2); +-- V_WR_1 = LCELL(V_WRM or V_EN1); +-- V_WR_0 = LCELL(V_WRM or V_EN0); + V_WR_3 = (LCELL(LCELL(LCELL(V_WRM or V_EN3)))); + V_WR_2 = (LCELL(LCELL(LCELL(V_WRM or V_EN2)))); + V_WR_1 = (LCELL(LCELL(LCELL(V_WRM or V_EN1)))); + V_WR_0 = (LCELL(LCELL(LCELL(V_WRM or V_EN0)))); + + V_WEY3 = LCELL(V_WE or V_EN3); + V_WEY2 = LCELL(V_WE or V_EN2); + V_WEY1 = LCELL(V_WE or V_EN1); + V_WEY0 = LCELL(V_WE or V_EN0); + + V_WR[] = V_WR_[]; -- V_WR0-3 + V_WEN[] = V_WEY[]; -- VD0-3 + + + + + +% + V_WEMMM = LCELL(V_WE); + V_WEMMN = LCELL(V_WEMMM); + V_WEMMO = LCELL(V_WEMMN); + V_WEMM = LCELL(V_WEMMO); + + V_WRM = LCELL(V_WEMMN & V_WEMMM); + V_WRM2 = LCELL(V_WEMMN & V_WEMMM); + + V_WEM = LCELL(V_WEMMM & V_WEMMO); + V_WEM2 = LCELL(V_WEMMM & V_WEMMO); + + V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)),CLK42,F_WR,); + V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,); + V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)) ,CLK42,F_WR,); + V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,); + + F_WR = DFF(VCC,V_WE,,); + + V_WR_3 = V_WRM or V_EN3; + V_WR_2 = V_WRM2 or V_EN2; + V_WR_1 = V_WRM or V_EN1; + V_WR_0 = V_WRM or V_EN0; + + V_WEY3 = V_WEM or V_EN3; + V_WEY2 = V_WEM2 or V_EN2; + V_WEY1 = V_WEM or V_EN1; + V_WEY0 = V_WEM or V_EN0; + + V_WR[] = V_WR_[]; + V_WEN[] = V_WEY[]; +% + + + + + +-- CLK84 = LCELL(CLK42 xor CLK84_X); +-- CLK84_X = DFF(!CLK84_X,CLK84,,); +-- CLK84_Y = CLK84; + +END GENERATE; -- end "sprinter" mode + + +END; diff --git a/src/altera/acex/k30/scf/ACCELER.SCF b/src/altera/acex/k30/scf/ACCELER.SCF deleted file mode 100644 index 0cae83c..0000000 Binary files a/src/altera/acex/k30/scf/ACCELER.SCF and /dev/null differ diff --git a/src/altera/acex/k30/scf/DCP.SCF b/src/altera/acex/k30/scf/DCP.SCF deleted file mode 100644 index 3012af0..0000000 Binary files a/src/altera/acex/k30/scf/DCP.SCF and /dev/null differ diff --git a/src/altera/acex/k30/scf/MOUSE.SCF b/src/altera/acex/k30/scf/MOUSE.SCF deleted file mode 100644 index f44bf36..0000000 Binary files a/src/altera/acex/k30/scf/MOUSE.SCF and /dev/null differ diff --git a/src/altera/acex/k30/scf/SP2_ACEX.SCF b/src/altera/acex/k30/scf/SP2_ACEX.SCF deleted file mode 100644 index 8f39b4a..0000000 Binary files a/src/altera/acex/k30/scf/SP2_ACEX.SCF and /dev/null differ diff --git a/src/altera/acex/k30/scf/VIDEO2.SCF b/src/altera/acex/k30/scf/VIDEO2.SCF deleted file mode 100644 index 5f11143..0000000 Binary files a/src/altera/acex/k30/scf/VIDEO2.SCF and /dev/null differ diff --git a/src/altera/acex/k30_make.bat b/src/altera/acex/k30_make.bat new file mode 100644 index 0000000..cce458e --- /dev/null +++ b/src/altera/acex/k30_make.bat @@ -0,0 +1,5 @@ +C: +cd "C:\users\tolik\Documents\SP_Projects\ASM\GIT\SP_Core\Build\acex\tmp\" +"C:\Program Files (x86)\MAXPLUS2\MAXPLUS2.EXE" -compile SP2_ACEX >> compile.log +transttf.exe SP2_ACEX.ttf ..\STREAM.BIN +exit \ No newline at end of file diff --git a/src/altera/acex/make.cmd b/src/altera/acex/make.cmd deleted file mode 100644 index 42b31da..0000000 --- a/src/altera/acex/make.cmd +++ /dev/null @@ -1,49 +0,0 @@ -@set BIN=..\..\bin\ -@set CHIP=K30 - -@echo -------------------------------------------------------[Bitstream START] -@echo STEP 0, Task [1/2] ALTERA ACEX-%CHIP% STREAM - -@if exist SP2_ACEX.ttf goto trans - -@copy %CHIP%\*.* .\*.* - -@C:\MAXPLUS2\MAXPLUS2.EXE -compile SP2_ACEX - -@del *.txt -@del *.bak -@del *.cnf -@del *.db? - -@del *.hif -@del *.mmf -@del *.mtf -@del *.mtb -@del *.hex -@del *.ndb -@del *.pin -@del *.pof -@del *.snf -@del *.fit - -@del *.SCF -@del *.ACF -@del *.TDF -@del *.INC -@del *.MIF - -:trans -@%BIN%\transttf.exe SP2_ACEX.ttf STREAM.BIN -@if not exist STREAM.BIN goto error - -@goto quit - -:error -@color 04 -@echo ---------------------------------------------------------------------[Compiling bitstream %CHIP% ERROR!!!] -@pause 0 -@exit 3 - -:quit -@echo [OK ] -@echo. diff --git a/src/altera/acex/sp2_acex.rpt b/src/altera/acex/sp2_acex.rpt deleted file mode 100644 index 9e861cd..0000000 --- a/src/altera/acex/sp2_acex.rpt +++ /dev/null @@ -1,14807 +0,0 @@ -Project Information c:\sprinter\src\altera\acex\sp2_acex.rpt - -MAX+plus II Compiler Report File -Version 10.0 9/14/2000 -Compiled: 07/02/2022 02:04:56 - -Copyright (C) 1988-2000 Altera Corporation -Any megafunction design, and related net list (encrypted or decrypted), -support information, device programming or simulation file, and any other -associated documentation or information provided by Altera or a partner -under Altera's Megafunction Partnership Program may be used only to -program PLD devices (but not masked PLD devices) from Altera. Any other -use of such megafunction design, net list, support information, device -programming or simulation file, or any other related documentation or -information is prohibited for any other purpose, including, but not -limited to modification, reverse engineering, de-compiling, or use with -any other silicon devices, unless such use is explicitly licensed under -a separate agreement with Altera or a megafunction partner. Title to -the intellectual property, including patents, copyrights, trademarks, -trade secrets, or maskworks, embodied in any such megafunction design, -net list, support information, device programming or simulation file, or -any other related documentation or information provided by Altera or a -megafunction partner, remains with Altera, the megafunction partner, or -their respective licensors. No other licenses, including any licenses -needed under any third party's intellectual property, are provided herein. - - - -***** Project compilation was successful - - -Main - - -** DEVICE SUMMARY ** - -Chip/ Input Output Bidir Memory Memory LCs -POF Device Pins Pins Pins Bits % Utilized LCs % Utilized - -SP2_ACEX EP1K30QC208-3 24 61 62 14080 57 % 1568 90 % - -User Pins: 24 61 62 - - - -Project Information c:\sprinter\src\altera\acex\sp2_acex.rpt - -** PROJECT COMPILATION MESSAGES ** - -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD10" was declared but never used -Warning: Line 179, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RGMOD4" was declared but never used -Warning: Line 92, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "cth4" was declared but never used -Warning: Line 160, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RED1" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BLUE4" was declared but never used -Warning: Line 161, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "GREEN0" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD5" was declared but never used -Warning: Line 179, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RGMOD5" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctv0" was declared but never used -Warning: Line 160, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RED0" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BLUE5" was declared but never used -Warning: Line 161, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "GREEN3" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD2" was declared but never used -Warning: Line 179, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RGMOD6" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctv1" was declared but never used -Warning: Line 222, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ISA_CASH" was declared but never used -Warning: Line 160, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RED3" was declared but never used -Warning: Line 261, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "V_WRXX0" was declared but never used -Warning: Line 250, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ALL_MODE1" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BLUE2" was declared but never used -Warning: Line 161, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "GREEN2" was declared but never used -Warning: Line 214, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "SYS_ENA" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD3" was declared but never used -Warning: Line 147, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "T_SIGNAL" was declared but never used -Warning: Line 204, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "CBL_R0" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD15" was declared but never used -Warning: Line 179, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RGMOD7" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctv2" was declared but never used -Warning: Line 160, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RED2" was declared but never used -Warning: Line 261, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "V_WRXX1" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BLUE3" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD0" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD14" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctv3" was declared but never used -Warning: Line 170, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "MDR7" was declared but never used -Warning: Line 36, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "/HALT" was declared but never used -Warning: Line 261, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "V_WRXX2" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BLUE0" was declared but never used -Warning: Line 117, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "blank" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD1" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctv4" was declared but never used -Warning: Line 241, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ROM_WRITE_MODE" was declared but never used -Warning: Line 170, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "MDR6" was declared but never used -Warning: Line 261, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "V_WRXX3" was declared but never used -Warning: Line 250, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ALL_MODE4" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BLUE1" was declared but never used -Warning: Line 164, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BORDER7" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctv5" was declared but never used -Warning: Line 170, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "MDR5" was declared but never used -Warning: Line 250, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ALL_MODE5" was declared but never used -Warning: Line 240, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ROM_RG7" was declared but never used -Warning: Line 164, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BORDER6" was declared but never used -Warning: Line 135, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "FDD_CH" was declared but never used -Warning: Line 154, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "KEY_D0" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctv6" was declared but never used -Warning: Line 94, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctf2" was declared but never used -Warning: Line 240, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ROM_RG6" was declared but never used -Warning: Line 170, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "MDR4" was declared but never used -Warning: Line 250, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ALL_MODE6" was declared but never used -Warning: Line 92, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "cth3" was declared but never used -Warning: Line 164, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BORDER5" was declared but never used -Warning: Line 161, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "GREEN5" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD8" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctv7" was declared but never used -Warning: Line 94, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctf3" was declared but never used -Warning: Line 170, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "MDR3" was declared but never used -Warning: Line 250, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ALL_MODE7" was declared but never used -Warning: Line 240, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ROM_RG5" was declared but never used -Warning: Line 160, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RED5" was declared but never used -Warning: Line 161, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "GREEN4" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD9" was declared but never used -Warning: Line 94, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "ctf0" was declared but never used -Warning: Line 170, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "MDR2" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD13" was declared but never used -Warning: Line 179, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RGMOD1" was declared but never used -Warning: Line 160, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RED4" was declared but never used -Warning: Line 161, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "GREEN7" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD6" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD12" was declared but never used -Warning: Line 179, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RGMOD2" was declared but never used -Warning: Line 170, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "MDR1" was declared but never used -Warning: Line 136, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "FDD_W" was declared but never used -Warning: Line 160, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RED7" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BLUE6" was declared but never used -Warning: Line 161, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "GREEN6" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD7" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD11" was declared but never used -Warning: Line 170, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "MDR0" was declared but never used -Warning: Line 179, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RGMOD3" was declared but never used -Warning: Line 160, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "RED6" was declared but never used -Warning: Line 115, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "start_up" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "BLUE7" was declared but never used -Warning: Line 161, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "GREEN1" was declared but never used -Warning: Line 109, File c:\sprinter\src\altera\acex\sp2_acex.tdf: - Symbolic name "DMD4" was declared but never used -Warning: Line 57, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KDD1" was declared but never used -Warning: Line 57, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KDD0" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KA4" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KA5" was declared but never used -Warning: Line 57, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KDD2" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KA6" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KA7" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KA0" was declared but never used -Warning: Line 15, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "/IOM" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KA1" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KA2" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KA3" was declared but never used -Warning: Line 16, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "/M1" was declared but never used -Warning: Line 63, File c:\sprinter\src\altera\acex\kbd.tdf: - Symbolic name "KB_OFL" was declared but never used -Warning: Line 35, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "D6" was declared but never used -Warning: Line 57, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "DIR_PORT1" was declared but never used -Warning: Line 128, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "V_WET3" was declared but never used -Warning: Line 82, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "CLK84_Y" was declared but never used -Warning: Line 128, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "V_WET2" was declared but never used -Warning: Line 91, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "VXA19" was declared but never used -Warning: Line 128, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "V_WET1" was declared but never used -Warning: Line 128, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "V_WET0" was declared but never used -Warning: Line 113, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "V_CST1" was declared but never used -Warning: Line 35, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "D1" was declared but never used -Warning: Line 199, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "V_CSX3" was declared but never used -Warning: Line 189, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "MS_PNT" was declared but never used -Warning: Line 35, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "D0" was declared but never used -Warning: Line 117, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "V_WEX" was declared but never used -Warning: Line 124, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "V_WEMM" was declared but never used -Warning: Line 35, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "D3" was declared but never used -Warning: Line 35, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "D2" was declared but never used -Warning: Line 84, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "ZX_COLOR1" was declared but never used -Warning: Line 35, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "D5" was declared but never used -Warning: Line 74, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "MOUSE_Y9" was declared but never used -Warning: Line 57, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "DIR_PORT2" was declared but never used -Warning: Line 84, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "ZX_COLOR0" was declared but never used -Warning: Line 161, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "ZXS5" was declared but never used -Warning: Line 154, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "AX128" was declared but never used -Warning: Line 35, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "D4" was declared but never used -Warning: Line 193, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "SCR_ENA" was declared but never used -Warning: Line 84, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "ZX_COLOR3" was declared but never used -Warning: Line 191, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "MS_DAT" was declared but never used -Warning: Line 35, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "D7" was declared but never used -Warning: Line 84, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "ZX_COLOR2" was declared but never used -Warning: Line 25, File c:\sprinter\src\altera\acex\video2.tdf: - Symbolic name "START_UP" was declared but never used -Warning: Line 113, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "D6" was declared but never used -Warning: Line 72, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "G_LINE9" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_2" was declared but never used -Warning: Line 128, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "SC5" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_3" was declared but never used -Warning: Line 204, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "HDD_A3" was declared but never used -Warning: Line 123, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "MPGS7" was declared but never used -Warning: Line 128, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "SC6" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_11" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_0" was declared but never used -Warning: Line 123, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "MPGS6" was declared but never used -Warning: Line 128, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "SC7" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_10" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_1" was declared but never used -Warning: Line 113, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "D1" was declared but never used -Warning: Line 128, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "SC2" was declared but never used -Warning: Line 113, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "D0" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_8" was declared but never used -Warning: Line 128, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "SC3" was declared but never used -Warning: Line 113, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "D3" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_9" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "HDD_W3" was declared but never used -Warning: Line 113, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "D2" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_6" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "HDD_W2" was declared but never used -Warning: Line 113, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "D5" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_7" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "HDD_W1" was declared but never used -Warning: Line 113, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "D4" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_4" was declared but never used -Warning: Line 162, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "HDD_W0" was declared but never used -Warning: Line 113, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "D7" was declared but never used -Warning: Line 207, File c:\sprinter\src\altera\acex\dcp.tdf: - Symbolic name "X_MA_5" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "XMDH5" was declared but never used -Warning: Line 88, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "FN_ACC2" was declared but never used -Warning: Line 124, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "ACC_TIME" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "XMDH6" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "XMDH7" was declared but never used -Warning: Line 78, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "RETN" was declared but never used -Warning: Line 69, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "CB_CMD" was declared but never used -Warning: Line 70, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "ID_CMD" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "XMDH0" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "XMDH1" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "XMDH2" was declared but never used -Warning: Line 12, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "RAS" was declared but never used -Warning: Line 104, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "STATE_EI" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "XMDH3" was declared but never used -Warning: Line 21, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "MC_WRITE" was declared but never used -Warning: Line 93, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "XMDH4" was declared but never used -Warning: Line 19, File c:\sprinter\src\altera\acex\acceler.tdf: - Symbolic name "MC_BEGIN" was declared but never used -Warning: Line 294, File c:\sprinter\src\altera\acex\ay.tdf: - Group "AY_GF" is missing brackets [] -Warning: Line 98, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CH_DIR7" was declared but never used -Warning: Line 61, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_ADRX3" was declared but never used -Warning: Line 98, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CH_DIR6" was declared but never used -Warning: Line 61, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_ADRX2" was declared but never used -Warning: Line 61, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_ADRX5" was declared but never used -Warning: Line 61, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_ADRX4" was declared but never used -Warning: Line 61, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_ADRX7" was declared but never used -Warning: Line 61, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_ADRX6" was declared but never used -Warning: Line 98, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CH_DIR1" was declared but never used -Warning: Line 98, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CH_DIR0" was declared but never used -Warning: Line 51, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CLK1" was declared but never used -Warning: Line 98, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CH_DIR3" was declared but never used -Warning: Line 34, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AWR" was declared but never used -Warning: Line 43, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_AAX1" was declared but never used -Warning: Line 98, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CH_DIR2" was declared but never used -Warning: Line 98, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CH_DIR5" was declared but never used -Warning: Line 62, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CCC8" was declared but never used -Warning: Line 98, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_CH_DIR4" was declared but never used -Warning: Line 61, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_ADRX1" was declared but never used -Warning: Line 61, File c:\sprinter\src\altera\acex\ay.tdf: - Symbolic name "AY_ADRX0" was declared but never used -Warning: Flipflop 'AY_FULL0' stuck at GND -Warning: TRI or OPNDRN buffer ':1446' is permanently disabled -Warning: TRI or OPNDRN buffer ':1446' is permanently disabled -Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead. -Info: Reserved unused input pin '/HALT' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board -Warning: Ignored Increase Input Delay logic option on pin '/wr' -- pin is either a global pin or is assigned to a dedicated input pin -Warning: Ignored Increase Input Delay logic option on pin '/io' -- pin is either a global pin or is assigned to a dedicated input pin -Warning: Ignored Increase Input Delay logic option on pin '/rd' -- pin is either a global pin or is assigned to a dedicated input pin -Warning: Ignored Increase Input Delay logic option on pin '/mr' -- pin is either a global pin or is assigned to a dedicated input pin -Warning: Ignored Increase Input Delay logic option on pin '/HALT' -- pin is either a global pin or is assigned to a dedicated input pin -Warning: Node '|dcp:DECODE|:285' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem - - -** PROJECT TIMING MESSAGES ** - -Warning: Timing characteristics of device EP1K30QC208-3 are preliminary -Warning: Found ripple clock -- warning messages and Report File information on tco, tsu, and fmax may be inaccurate -Warning: Can't provide fmax of 100.00 MHz on Clock pin "TG42". Current fmax is 49.26 MHz. - - -Project Information c:\sprinter\src\altera\acex\sp2_acex.rpt - -** PIN/LOCATION/CHIP ASSIGNMENTS ** - - Actual - User Assignments -Assignments (if different) Node Name - -SP2_ACEX@EAB_D |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_0 -SP2_ACEX@EAB_D |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_1 -SP2_ACEX@EAB_D |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_2 -SP2_ACEX@EAB_D |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_3 -SP2_ACEX@EAB_D |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_4 -SP2_ACEX@EAB_D |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_5 -SP2_ACEX@EAB_D |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_6 -SP2_ACEX@EAB_D |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_7 -SP2_ACEX@EAB_E |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_0 -SP2_ACEX@EAB_E |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_1 -SP2_ACEX@EAB_E |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_2 -SP2_ACEX@EAB_E |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_3 -SP2_ACEX@EAB_E |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_4 -SP2_ACEX@EAB_E |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_5 -SP2_ACEX@EAB_E |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_6 -SP2_ACEX@EAB_E |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_7 -SP2_ACEX@26 a0 -SP2_ACEX@27 a1 -SP2_ACEX@28 a2 -SP2_ACEX@29 a3 -SP2_ACEX@30 a4 -SP2_ACEX@31 a5 -SP2_ACEX@36 A6 -SP2_ACEX@37 A7 -SP2_ACEX@38 A8 -SP2_ACEX@39 a9 -SP2_ACEX@40 A10 -SP2_ACEX@41 a11 -SP2_ACEX@44 A12 -SP2_ACEX@45 A13 -SP2_ACEX@46 A14 -SP2_ACEX@47 A15 -SP2_ACEX@LC7_B36 CASXE0 -SP2_ACEX@LC8_B36 CASXE1 -SP2_ACEX@LC1_B36 CASX_0 -SP2_ACEX@LC5_B36 CASX_1 -SP2_ACEX@LC2_B36 CASX_2 -SP2_ACEX@LC6_B36 CASX_3 -SP2_ACEX@12 CAS_0 -SP2_ACEX@14 CAS_1 -SP2_ACEX@13 CAS_2 -SP2_ACEX@15 CAS_3 -SP2_ACEX@62 CLKZ1 -SP2_ACEX@64 CS_CASH -SP2_ACEX@63 cs_rom -SP2_ACEX@160 DAC_BCK -SP2_ACEX@158 DAC_DATA -SP2_ACEX@159 DAC_WS -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_0 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_1 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_2 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_3 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_4 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_5 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_6 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_7 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_8 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_9 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_10 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_11 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_12 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_13 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_14 -SP2_ACEX@EAB_C |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_15 -SP2_ACEX@LC2_A15 |dcp:DECODE|WR_AWGX -SP2_ACEX@LC2_A32 --------- |dcp:DECODE|:285 -SP2_ACEX@53 D0 -SP2_ACEX@54 D1 -SP2_ACEX@55 d2 -SP2_ACEX@56 d3 -SP2_ACEX@57 d4 -SP2_ACEX@58 d5 -SP2_ACEX@60 d6 -SP2_ACEX@61 d7 -SP2_ACEX@182 /HALT -SP2_ACEX@78 /io -SP2_ACEX@EAB_B |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_0 -SP2_ACEX@EAB_B |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_1 -SP2_ACEX@EAB_B |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_2 -SP2_ACEX@EAB_B |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_3 -SP2_ACEX@EAB_B |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_4 -SP2_ACEX@EAB_B |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_5 -SP2_ACEX@EAB_B |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_6 -SP2_ACEX@EAB_B |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_7 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_5 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_6 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_7 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_8 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_9 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_10 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_11 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_12 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_13 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_14 -SP2_ACEX@EAB_A |lpm_ram_dp:CBL|altdpram:sram|segment0_15 -SP2_ACEX@166 ma0 -SP2_ACEX@167 ma1 -SP2_ACEX@168 ma2 -SP2_ACEX@170 ma3 -SP2_ACEX@172 ma4 -SP2_ACEX@174 ma5 -SP2_ACEX@175 ma6 -SP2_ACEX@197 ma7 -SP2_ACEX@202 ma8 -SP2_ACEX@203 ma9 -SP2_ACEX@177 ma10 -SP2_ACEX@199 ma11 -SP2_ACEX@206 ma12 -SP2_ACEX@195 ma13 -SP2_ACEX@191 ma14 -SP2_ACEX@196 md0 -SP2_ACEX@193 md1 -SP2_ACEX@190 md2 -SP2_ACEX@186 md3 -SP2_ACEX@164 md4 -SP2_ACEX@163 md5 -SP2_ACEX@162 md6 -SP2_ACEX@161 md7 -SP2_ACEX@8 md8 -SP2_ACEX@208 md9 -SP2_ACEX@204 md10 -SP2_ACEX@198 md11 -SP2_ACEX@192 md12 -SP2_ACEX@189 md13 -SP2_ACEX@187 md14 -SP2_ACEX@179 md15 -SP2_ACEX@184 /mr -SP2_ACEX@24 /m1 -SP2_ACEX@LC2_A35 RASX_0 -SP2_ACEX@LC2_A34 RASX_1 -SP2_ACEX@207 RAS_0 -SP2_ACEX@205 RAS_1 -SP2_ACEX@65 ra14 -SP2_ACEX@69 ra15 -SP2_ACEX@68 ra16 -SP2_ACEX@67 ra17 -SP2_ACEX@80 /rd -SP2_ACEX@10 RD_KMPS -SP2_ACEX@173 RDXA -SP2_ACEX@19 /reset -SP2_ACEX@25 /rf -SP2_ACEX@7 SXA -SP2_ACEX@183 TG42 -SP2_ACEX@102 VA0 -SP2_ACEX@100 VA1 -SP2_ACEX@97 VA2 -SP2_ACEX@96 VA3 -SP2_ACEX@94 VA4 -SP2_ACEX@92 VA5 -SP2_ACEX@89 VA6 -SP2_ACEX@86 VA7 -SP2_ACEX@90 VA8 -SP2_ACEX@93 VA9 -SP2_ACEX@99 VA10 -SP2_ACEX@95 VA11 -SP2_ACEX@74 VA12 -SP2_ACEX@87 VA13 -SP2_ACEX@73 VA14 -SP2_ACEX@71 VA15 -SP2_ACEX@101 v_cs0 -SP2_ACEX@70 v_cs1 -SP2_ACEX@103 VD00 -SP2_ACEX@113 VD01 -SP2_ACEX@116 VD02 -SP2_ACEX@121 VD03 -SP2_ACEX@126 VD04 -SP2_ACEX@125 VD05 -SP2_ACEX@119 VD06 -SP2_ACEX@112 VD07 -SP2_ACEX@104 VD10 -SP2_ACEX@111 VD11 -SP2_ACEX@120 VD12 -SP2_ACEX@127 VD13 -SP2_ACEX@132 VD14 -SP2_ACEX@134 VD15 -SP2_ACEX@133 VD16 -SP2_ACEX@122 VD17 -SP2_ACEX@150 VD20 -SP2_ACEX@115 VD21 -SP2_ACEX@135 VD22 -SP2_ACEX@140 VD23 -SP2_ACEX@141 VD24 -SP2_ACEX@147 VD25 -SP2_ACEX@142 VD26 -SP2_ACEX@131 VD27 -SP2_ACEX@114 VD30 -SP2_ACEX@136 VD31 -SP2_ACEX@144 VD32 -SP2_ACEX@148 VD33 -SP2_ACEX@149 VD34 -SP2_ACEX@143 VD35 -SP2_ACEX@139 VD36 -SP2_ACEX@128 VD37 -SP2_ACEX@LC6_F12 |video2:SVIDEO|V_WE -SP2_ACEX@LC2_F18 |video2:SVIDEO|V_WEM -SP2_ACEX@LC3_F12 |video2:SVIDEO|V_WEMMM -SP2_ACEX@LC2_F12 |video2:SVIDEO|V_WEMMN -SP2_ACEX@LC3_F15 |video2:SVIDEO|V_WEMMO -SP2_ACEX@LC2_F20 |video2:SVIDEO|V_WEM2 -SP2_ACEX@LC5_F11 |video2:SVIDEO|V_WE_R -SP2_ACEX@LC2_F17 |video2:SVIDEO|V_WEY0 -SP2_ACEX@LC2_F16 |video2:SVIDEO|V_WEY1 -SP2_ACEX@LC2_F19 |video2:SVIDEO|V_WEY2 -SP2_ACEX@LC2_F14 |video2:SVIDEO|V_WEY3 -SP2_ACEX@LC8_F18 |video2:SVIDEO|V_WRM -SP2_ACEX@LC8_F20 |video2:SVIDEO|V_WRM2 -SP2_ACEX@LC8_F17 |video2:SVIDEO|V_WR_0 -SP2_ACEX@LC8_F16 |video2:SVIDEO|V_WR_1 -SP2_ACEX@LC8_F19 |video2:SVIDEO|V_WR_2 -SP2_ACEX@LC8_F14 |video2:SVIDEO|V_WR_3 -SP2_ACEX@LC1_F17 V_WRX0 -SP2_ACEX@LC1_F16 V_WRX1 -SP2_ACEX@LC1_F19 V_WRX2 -SP2_ACEX@LC1_F14 V_WRX3 -SP2_ACEX@83 v_wr0 -SP2_ACEX@85 v_wr1 -SP2_ACEX@75 v_wr2 -SP2_ACEX@88 v_wr3 -SP2_ACEX@18 /wait -SP2_ACEX@16 /WE -SP2_ACEX@79 /wr -SP2_ACEX@176 wr_awg -SP2_ACEX@157 WR_COL -SP2_ACEX@11 wr_dwg -SP2_ACEX@169 XACS -SP2_ACEX@180 XA0 -SP2_ACEX@9 XA1 -SP2_ACEX@200 XA2 -SP2_ACEX@17 XA3 - - -Project Information c:\sprinter\src\altera\acex\sp2_acex.rpt - -** EMBEDDED ARRAYS ** - - -|kbd:KEYS|lpm_ram_dq:59|altram:sram|content: MEMORY ( - width = 8; - depth = 256; - segmentsize = 256; - mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; - file = "KBD_INI2.MIF"; - ) - OF SEGMENTS ( - |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_7, - |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_6, - |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_5, - |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_4, - |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_3, - |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_2, - |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_1, - |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_0 -); - - - -|video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|content: MEMORY ( - width = 16; - depth = 256; - segmentsize = 256; - mode = MEM_INITIALIZED#MEM_FIFO#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0#MEM_REG_DATAOUT_CLK1#MEM_REG_RADDR_CLK1#MEM_REG_RCTRL_CLK1; - file = "MOUSE.MIF"; - ) - OF SEGMENTS ( - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_15, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_14, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_13, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_12, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_11, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_10, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_9, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_8, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_7, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_6, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_5, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_4, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_3, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_2, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_1, /* This segment is removed by logic synthesis */ - |video2:SVIDEO|lpm_ram_dp:MS_DAT|altdpram:sram|segment0_0 /* This segment is removed by logic synthesis */ -); - - - -|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|content: MEMORY ( - width = 16; - depth = 256; - segmentsize = 256; - mode = MEM_INITIALIZED#MEM_FIFO#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0#MEM_REG_DATAOUT_CLK1#MEM_REG_RADDR_CLK1#MEM_REG_RCTRL_CLK1; - file = "DCP.MIF"; - ) - OF SEGMENTS ( - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_15, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_14, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_13, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_12, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_11, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_10, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_9, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_8, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_7, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_6, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_5, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_4, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_3, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_2, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_1, - |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_0 -); - - - -|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|content: MEMORY ( - width = 16; - depth = 256; - segmentsize = 256; - mode = MEM_FIFO#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0#MEM_REG_DATAOUT_CLK1#MEM_REG_RADDR_CLK1#MEM_REG_RCTRL_CLK1; - ) - OF SEGMENTS ( - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_15, /* This segment is removed by logic synthesis */ - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_14, /* This segment is removed by logic synthesis */ - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_13, /* This segment is removed by logic synthesis */ - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_12, /* This segment is removed by logic synthesis */ - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_11, /* This segment is removed by logic synthesis */ - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_10, /* This segment is removed by logic synthesis */ - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_9, /* This segment is removed by logic synthesis */ - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_8, /* This segment is removed by logic synthesis */ - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_7, - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_6, - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_5, - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_4, - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_3, - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_2, - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_1, - |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_0 -); - - - -|ay:AY3|lpm_ram_dq:90|altram:sram|content: MEMORY ( - width = 8; - depth = 256; - segmentsize = 256; - mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0#MEM_REG_DATAOUT_CLK1; - file = "AY.MIF"; - ) - OF SEGMENTS ( - |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_7, - |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_6, - |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_5, - |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_4, - |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_3, - |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_2, - |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_1, - |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_0 -); - - - -|lpm_ram_dp:CBL|altdpram:sram|content: MEMORY ( - width = 16; - depth = 256; - segmentsize = 256; - mode = MEM_FIFO#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0#MEM_REG_DATAOUT_CLK1#MEM_REG_RADDR_CLK1#MEM_REG_RCTRL_CLK1; - ) - OF SEGMENTS ( - |lpm_ram_dp:CBL|altdpram:sram|segment0_15, - |lpm_ram_dp:CBL|altdpram:sram|segment0_14, - |lpm_ram_dp:CBL|altdpram:sram|segment0_13, - |lpm_ram_dp:CBL|altdpram:sram|segment0_12, - |lpm_ram_dp:CBL|altdpram:sram|segment0_11, - |lpm_ram_dp:CBL|altdpram:sram|segment0_10, - |lpm_ram_dp:CBL|altdpram:sram|segment0_9, - |lpm_ram_dp:CBL|altdpram:sram|segment0_8, - |lpm_ram_dp:CBL|altdpram:sram|segment0_7, - |lpm_ram_dp:CBL|altdpram:sram|segment0_6, - |lpm_ram_dp:CBL|altdpram:sram|segment0_5, - |lpm_ram_dp:CBL|altdpram:sram|segment0_4, - |lpm_ram_dp:CBL|altdpram:sram|segment0_3, - |lpm_ram_dp:CBL|altdpram:sram|segment0_2, - |lpm_ram_dp:CBL|altdpram:sram|segment0_1, - |lpm_ram_dp:CBL|altdpram:sram|segment0_0 /* This segment is removed by logic synthesis */ -); - - - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -***** Logic for device 'SP2_ACEX' compiled without errors. - - - - -Device: EP1K30QC208-3 - -ACEX 1K Configuration Scheme: Passive Serial - -Device Options: - User-Supplied Start-Up Clock = OFF - Auto-Restart Configuration on Frame Error = ON - Release Clears Before Tri-States = ON - Enable Chip_Wide Reset = OFF - Enable Chip-Wide Output Enable = OFF - Enable INIT_DONE Output = OFF - JTAG User Code = 7f - MultiVolt I/O = ON - - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** ERROR SUMMARY ** - -Info: Chip 'SP2_ACEX' in device 'EP1K30QC208-3' has less than 20% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device -Info: Chip 'SP2_ACEX' in device 'EP1K30QC208-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device - - - D - D A - V V w A D C W - R R C V C / V r V C A _ R - A m A m C m m m C m m m m C T H m C m _ R X C _ C D _ - m S a S d m m I X a d m m a C m d a m d G d m I / G A G X d C a a m m D m G m A m m m C m m m m B _ A C - d _ 1 _ 1 a a N A 1 1 a d 1 I d 1 1 d 1 N 1 d N m 4 L N A 1 I 1 w a a X a N a C a a a I d d d d C W T O - 9 0 2 1 0 9 8 T 2 1 1 7 0 3 O 1 2 4 2 3 D 4 3 T r 2 T D 0 5 O 0 g 6 5 A 4 D 3 S 2 1 0 O 4 5 6 7 K S A L - ----------------------------------------------------------------------------------------------------------_ - / 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_ - / 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 | - #TCK | 1 156 | ^DATA0 -^CONF_DONE | 2 155 | ^DCLK - ^nCEO | 3 154 | ^nCE - #TDO | 4 153 | #TDI - VCCIO | 5 152 | VCCINT - GND | 6 151 | GND - SXA | 7 150 | VD20 - md8 | 8 149 | VD34 - XA1 | 9 148 | VD33 - RD_KMPS | 10 147 | VD25 - wr_dwg | 11 146 | VCCIO - CAS_0 | 12 145 | GND - CAS_2 | 13 144 | VD32 - CAS_1 | 14 143 | VD35 - CAS_3 | 15 142 | VD26 - /WE | 16 141 | VD24 - XA3 | 17 140 | VD23 - /wait | 18 139 | VD36 - /reset | 19 138 | VCCIO - GND | 20 137 | GND - VCCINT | 21 136 | VD31 - VCCIO | 22 135 | VD22 - GND | 23 134 | VD15 - /m1 | 24 133 | VD16 - /rf | 25 132 | VD14 - a0 | 26 131 | VD27 - a1 | 27 EP1K30QC208-3 130 | VCCINT - a2 | 28 129 | GND - a3 | 29 128 | VD37 - a4 | 30 127 | VD13 - a5 | 31 126 | VD04 - GND | 32 125 | VD05 - VCCINT | 33 124 | VCCINT - VCCIO | 34 123 | GND - GND | 35 122 | VD17 - A6 | 36 121 | VD03 - A7 | 37 120 | VD12 - A8 | 38 119 | VD06 - a9 | 39 118 | VCCIO - A10 | 40 117 | GND - a11 | 41 116 | VD02 - VCCIO | 42 115 | VD21 - GND | 43 114 | VD30 - A12 | 44 113 | VD01 - A13 | 45 112 | VD07 - A14 | 46 111 | VD11 - A15 | 47 110 | VCCIO - VCCINT | 48 109 | GND - GND | 49 108 | ^MSEL0 - #TMS | 50 107 | ^MSEL1 - #TRST | 51 106 | VCCINT - ^nSTATUS | 52 105 | ^nCONFIG - | 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _| - \ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 | - \----------------------------------------------------------------------------------------------------------- - D D d d d d G d d C c C r V r r r v V V V V v G V / / / G G v V v V V v V V V V V V V V V V V V v V V V - 0 1 2 3 4 5 N 6 7 L s S a C a a a _ A C A A _ N C i w r N N _ C _ A A _ A A C A A A A A A C A A _ A D D - D K _ _ 1 C 1 1 1 c 1 C 1 1 w D C o r d D D w C w 7 1 w 6 8 C 5 9 4 1 3 2 C 1 1 c 0 0 1 - Z r C 4 I 7 6 5 s 5 I 4 2 r I r I r 3 r I 1 I 0 s 0 0 - 1 o A O 1 N 2 N 0 O 1 3 N O 0 - m S T T T - H - - - - - -N.C. = No Connect. This pin has no internal connection to the device. -VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts). -VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts). -GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. -RESERVED = Unused I/O pin, which MUST be left unconnected. - -^ = Dedicated configuration pin. -+ = Reserved configuration pin, which is tri-stated during user mode. -* = Reserved configuration pin, which drives out in user mode. -PDn = Power Down pin. -@ = Special-purpose pin. -# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. -& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. -$ = Pin has PCI I/O option enabled. Pin is not '5.0 V'-tolerant. - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** RESOURCE USAGE ** - -Logic Column Row -Array Interconnect Interconnect Clears/ External -Block Logic Cells Driven Driven Clocks Presets Interconnect -A1 8/ 8(100%) 7/ 8( 87%) 4/ 8( 50%) 2/2 0/2 11/22( 50%) -A2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 12/22( 54%) -A3 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 9/22( 40%) -A4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%) -A5 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 10/22( 45%) -A6 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 12/22( 54%) -A7 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 2/22( 9%) -A8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%) -A9 7/ 8( 87%) 3/ 8( 37%) 5/ 8( 62%) 2/2 0/2 6/22( 27%) -A10 7/ 8( 87%) 7/ 8( 87%) 2/ 8( 25%) 1/2 0/2 13/22( 59%) -A11 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 2/2 1/2 14/22( 63%) -A12 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 1/2 11/22( 50%) -A13 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 12/22( 54%) -A14 7/ 8( 87%) 4/ 8( 50%) 4/ 8( 50%) 2/2 1/2 13/22( 59%) -A15 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 15/22( 68%) -A16 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 12/22( 54%) -A17 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 1/2 10/22( 45%) -A18 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 1/2 2/2 17/22( 77%) -A19 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%) -A20 7/ 8( 87%) 4/ 8( 50%) 3/ 8( 37%) 1/2 0/2 6/22( 27%) -A21 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 7/22( 31%) -A22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 11/22( 50%) -A23 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 9/22( 40%) -A24 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 12/22( 54%) -A25 8/ 8(100%) 2/ 8( 25%) 8/ 8(100%) 2/2 1/2 14/22( 63%) -A26 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 14/22( 63%) -A27 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 2/2 2/2 10/22( 45%) -A28 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 10/22( 45%) -A29 7/ 8( 87%) 5/ 8( 62%) 6/ 8( 75%) 1/2 1/2 6/22( 27%) -A30 8/ 8(100%) 6/ 8( 75%) 7/ 8( 87%) 1/2 1/2 6/22( 27%) -A31 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 17/22( 77%) -A32 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 2/2 12/22( 54%) -A33 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 1/2 13/22( 59%) -A34 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 2/2 1/2 20/22( 90%) -A35 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) -A36 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 11/22( 50%) -B1 4/ 8( 50%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 12/22( 54%) -B2 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 8/22( 36%) -B3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 9/22( 40%) -B4 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 7/22( 31%) -B5 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 8/22( 36%) -B6 5/ 8( 62%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 8/22( 36%) -B7 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 10/22( 45%) -B8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 9/22( 40%) -B9 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 15/22( 68%) -B10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 1/2 12/22( 54%) -B11 4/ 8( 50%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 12/22( 54%) -B12 7/ 8( 87%) 1/ 8( 12%) 6/ 8( 75%) 2/2 2/2 9/22( 40%) -B13 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 0/2 16/22( 72%) -B14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%) -B15 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 11/22( 50%) -B16 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 8/22( 36%) -B17 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 0/2 6/22( 27%) -B18 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 6/22( 27%) -B19 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 10/22( 45%) -B20 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 12/22( 54%) -B21 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 13/22( 59%) -B22 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 12/22( 54%) -B23 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 2/2 1/2 7/22( 31%) -B24 7/ 8( 87%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 12/22( 54%) -B25 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 12/22( 54%) -B26 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 2/2 0/2 14/22( 63%) -B27 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 12/22( 54%) -B28 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%) -B29 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 11/22( 50%) -B30 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 8/22( 36%) -B31 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 17/22( 77%) -B32 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 11/22( 50%) -B33 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 12/22( 54%) -B34 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 2/2 0/2 13/22( 59%) -B35 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 17/22( 77%) -B36 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 8/22( 36%) -C1 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 1/2 14/22( 63%) -C2 7/ 8( 87%) 7/ 8( 87%) 0/ 8( 0%) 2/2 0/2 19/22( 86%) -C3 7/ 8( 87%) 2/ 8( 25%) 4/ 8( 50%) 2/2 2/2 16/22( 72%) -C4 7/ 8( 87%) 5/ 8( 62%) 1/ 8( 12%) 2/2 1/2 12/22( 54%) -C5 5/ 8( 62%) 5/ 8( 62%) 4/ 8( 50%) 1/2 0/2 9/22( 40%) -C6 3/ 8( 37%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 7/22( 31%) -C7 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 12/22( 54%) -C8 8/ 8(100%) 5/ 8( 62%) 0/ 8( 0%) 2/2 2/2 17/22( 77%) -C9 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 9/22( 40%) -C10 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 1/2 22/22(100%) -C11 8/ 8(100%) 6/ 8( 75%) 2/ 8( 25%) 1/2 0/2 15/22( 68%) -C12 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 14/22( 63%) -C13 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 14/22( 63%) -C14 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 2/2 1/2 12/22( 54%) -C15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) -C16 7/ 8( 87%) 5/ 8( 62%) 1/ 8( 12%) 1/2 0/2 16/22( 72%) -C17 7/ 8( 87%) 7/ 8( 87%) 1/ 8( 12%) 1/2 0/2 11/22( 50%) -C18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 15/22( 68%) -C19 8/ 8(100%) 2/ 8( 25%) 7/ 8( 87%) 1/2 1/2 13/22( 59%) -C20 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 16/22( 72%) -C21 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 2/2 1/2 17/22( 77%) -C22 8/ 8(100%) 3/ 8( 37%) 8/ 8(100%) 1/2 0/2 11/22( 50%) -C23 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 1/2 11/22( 50%) -C24 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 10/22( 45%) -C25 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 2/2 15/22( 68%) -C26 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 14/22( 63%) -C27 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 2/2 2/2 19/22( 86%) -C28 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 2/2 1/2 13/22( 59%) -C29 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/22( 45%) -C30 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 10/22( 45%) -C31 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 20/22( 90%) -C32 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 16/22( 72%) -C33 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 2/2 11/22( 50%) -C34 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 2/2 15/22( 68%) -C35 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 11/22( 50%) -C36 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 13/22( 59%) -D1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 12/22( 54%) -D2 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 14/22( 63%) -D3 7/ 8( 87%) 4/ 8( 50%) 5/ 8( 62%) 1/2 1/2 12/22( 54%) -D4 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 14/22( 63%) -D5 7/ 8( 87%) 5/ 8( 62%) 2/ 8( 25%) 1/2 0/2 13/22( 59%) -D6 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 5/22( 22%) -D7 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 2/2 0/2 11/22( 50%) -D8 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 14/22( 63%) -D9 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 2/2 0/2 17/22( 77%) -D10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%) -D11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 13/22( 59%) -D12 8/ 8(100%) 6/ 8( 75%) 3/ 8( 37%) 2/2 2/2 12/22( 54%) -D13 7/ 8( 87%) 5/ 8( 62%) 3/ 8( 37%) 2/2 2/2 15/22( 68%) -D14 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 2/2 15/22( 68%) -D15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 12/22( 54%) -D16 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) -D17 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 2/2 1/2 15/22( 68%) -D18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 13/22( 59%) -D19 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 1/2 2/2 17/22( 77%) -D20 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 2/2 8/22( 36%) -D21 8/ 8(100%) 6/ 8( 75%) 4/ 8( 50%) 2/2 1/2 18/22( 81%) -D22 8/ 8(100%) 8/ 8(100%) 8/ 8(100%) 1/2 1/2 4/22( 18%) -D23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 12/22( 54%) -D24 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 11/22( 50%) -D25 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 7/22( 31%) -D26 8/ 8(100%) 6/ 8( 75%) 3/ 8( 37%) 1/2 1/2 15/22( 68%) -D27 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 2/2 2/2 12/22( 54%) -D28 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 2/2 0/2 12/22( 54%) -D29 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 12/22( 54%) -D30 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 12/22( 54%) -D31 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 1/2 2/2 18/22( 81%) -D32 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 13/22( 59%) -D33 8/ 8(100%) 7/ 8( 87%) 2/ 8( 25%) 1/2 1/2 14/22( 63%) -D34 8/ 8(100%) 5/ 8( 62%) 7/ 8( 87%) 2/2 1/2 8/22( 36%) -D35 6/ 8( 75%) 4/ 8( 50%) 3/ 8( 37%) 1/2 1/2 13/22( 59%) -D36 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 18/22( 81%) -E1 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 0/2 8/22( 36%) -E2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 11/22( 50%) -E3 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 10/22( 45%) -E4 7/ 8( 87%) 3/ 8( 37%) 4/ 8( 50%) 2/2 0/2 14/22( 63%) -E5 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/22( 40%) -E6 7/ 8( 87%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 15/22( 68%) -E7 8/ 8(100%) 8/ 8(100%) 1/ 8( 12%) 1/2 0/2 4/22( 18%) -E8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 14/22( 63%) -E9 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 12/22( 54%) -E10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 13/22( 59%) -E11 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 0/2 9/22( 40%) -E12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 2/2 12/22( 54%) -E13 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 10/22( 45%) -E14 7/ 8( 87%) 4/ 8( 50%) 5/ 8( 62%) 2/2 0/2 8/22( 36%) -E15 4/ 8( 50%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 10/22( 45%) -E16 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 9/22( 40%) -E17 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 0/2 11/22( 50%) -E18 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 1/2 11/22( 50%) -E19 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 1/2 0/2 10/22( 45%) -E20 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 9/22( 40%) -E21 3/ 8( 37%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 8/22( 36%) -E22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 16/22( 72%) -E23 6/ 8( 75%) 4/ 8( 50%) 3/ 8( 37%) 2/2 0/2 9/22( 40%) -E24 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 2/2 0/2 8/22( 36%) -E25 7/ 8( 87%) 5/ 8( 62%) 4/ 8( 50%) 2/2 0/2 5/22( 22%) -E26 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 10/22( 45%) -E27 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 11/22( 50%) -E28 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 8/22( 36%) -E29 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 14/22( 63%) -E30 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 6/22( 27%) -E31 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 1/2 0/2 7/22( 31%) -E32 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 3/22( 13%) -E33 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 4/22( 18%) -E34 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 14/22( 63%) -E35 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/22( 31%) -E36 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 2/2 0/2 8/22( 36%) -F1 8/ 8(100%) 5/ 8( 62%) 7/ 8( 87%) 1/2 2/2 10/22( 45%) -F2 6/ 8( 75%) 2/ 8( 25%) 6/ 8( 75%) 2/2 0/2 14/22( 63%) -F3 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 1/2 14/22( 63%) -F4 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 12/22( 54%) -F5 7/ 8( 87%) 2/ 8( 25%) 5/ 8( 62%) 2/2 1/2 10/22( 45%) -F6 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 10/22( 45%) -F7 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 1/2 10/22( 45%) -F8 8/ 8(100%) 8/ 8(100%) 0/ 8( 0%) 2/2 0/2 9/22( 40%) -F9 7/ 8( 87%) 4/ 8( 50%) 2/ 8( 25%) 2/2 2/2 12/22( 54%) -F10 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 2/2 2/2 9/22( 40%) -F11 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 2/2 1/2 9/22( 40%) -F12 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 12/22( 54%) -F13 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 12/22( 54%) -F14 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 13/22( 59%) -F15 7/ 8( 87%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 7/22( 31%) -F16 8/ 8(100%) 5/ 8( 62%) 1/ 8( 12%) 2/2 2/2 14/22( 63%) -F17 4/ 8( 50%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 5/22( 22%) -F18 6/ 8( 75%) 1/ 8( 12%) 6/ 8( 75%) 1/2 0/2 14/22( 63%) -F19 6/ 8( 75%) 4/ 8( 50%) 0/ 8( 0%) 2/2 0/2 9/22( 40%) -F20 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 14/22( 63%) -F21 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 15/22( 68%) -F22 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 7/22( 31%) -F23 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 9/22( 40%) -F24 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 10/22( 45%) -F25 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 9/22( 40%) -F26 7/ 8( 87%) 4/ 8( 50%) 5/ 8( 62%) 1/2 2/2 10/22( 45%) -F27 5/ 8( 62%) 1/ 8( 12%) 3/ 8( 37%) 2/2 2/2 8/22( 36%) -F28 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 11/22( 50%) -F29 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 4/22( 18%) -F30 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 18/22( 81%) -F31 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 9/22( 40%) -F32 8/ 8(100%) 7/ 8( 87%) 4/ 8( 50%) 2/2 2/2 7/22( 31%) -F33 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 9/22( 40%) -F34 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 11/22( 50%) -F35 7/ 8( 87%) 4/ 8( 50%) 3/ 8( 37%) 1/2 0/2 10/22( 45%) -F36 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 6/22( 27%) - - -Embedded Column Row -Array Embedded Interconnect Interconnect Read/ External -Block Cells Driven Driven Clocks Write Interconnect -A37 15/16( 93%) 0/16( 0%) 15/16( 93%) 1/2 2/6 32/88( 36%) -B37 8/16( 50%) 0/16( 0%) 8/16( 50%) 1/2 2/6 15/88( 17%) -C37 16/16(100%) 13/16( 81%) 16/16(100%) 1/2 2/6 17/88( 19%) -D37 8/16( 50%) 1/16( 6%) 8/16( 50%) 1/2 2/6 17/88( 19%) -E37 8/16( 50%) 0/16( 0%) 8/16( 50%) 1/2 2/6 17/88( 19%) - - -Total dedicated input pins used: 6/6 (100%) -Total I/O pins used: 141/141 (100%) -Total logic cells used: 1568/1728 ( 90%) -Total embedded cells used: 55/96 ( 57%) -Total EABs used: 5/6 ( 83%) -Average fan-in: 2.73/4 ( 68%) -Total fan-in: 4282/6912 ( 61%) - -Total input pins required: 24 -Total input I/O cell registers required: 0 -Total output pins required: 61 -Total output I/O cell registers required: 31 -Total buried I/O cell registers required: 0 -Total bidirectional pins required: 62 -Total reserved pins required 0 -Total logic cells required: 1568 -Total flipflops required: 931 -Total packed registers required: 0 -Total logic cells in carry chains: 166 -Total number of carry chains: 19 -Total number of carry chains of length 1-8 : 12 -Total number of carry chains of length 9-16: 6 -Total number of carry chains of length 17-24: 1 -Total logic cells in cascade chains: 59 -Total number of cascade chains: 29 -Total single-pin Clock Enables required: 0 -Total single-pin Output Enables required: 0 -Logic cells inserted for fitting: 11 - -Synthesized logic cells: 193/1728 ( 11%) - -Logic Cell and Embedded Cell Counts - -Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC) - A: 8 8 7 8 8 8 5 8 7 7 8 8 8 7 8 8 8 8 15 7 7 7 8 3 8 8 8 8 8 7 8 8 8 8 8 2 8 266/15 - B: 4 8 8 8 7 5 8 8 7 8 4 7 8 8 8 7 8 8 8 8 8 8 7 8 7 6 8 8 7 8 8 8 7 8 7 8 8 266/8 - C: 8 7 7 7 5 3 6 8 8 8 8 7 8 7 1 7 7 8 16 8 8 8 8 8 8 8 8 8 8 8 7 8 8 7 8 7 7 260/16 - D: 8 7 7 8 7 2 8 7 8 1 8 8 7 8 8 1 8 8 8 8 8 8 8 8 8 8 8 8 8 7 8 8 7 8 8 6 8 259/8 - E: 8 8 8 7 5 7 8 8 8 8 8 8 7 7 4 8 8 8 8 8 7 3 8 6 8 7 8 8 8 8 8 8 2 1 8 8 7 254/8 - F: 8 6 8 8 7 8 8 8 7 8 8 7 8 8 7 8 4 6 0 6 8 8 8 8 8 8 7 5 8 2 8 8 8 8 8 7 8 263/0 - -Total: 44 44 45 46 39 33 43 47 45 40 44 45 46 45 36 39 43 46 55 45 46 42 47 41 47 45 47 45 47 40 47 48 40 40 47 38 46 1568/55 - - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** INPUTS ** - - Fan-In Fan-Out - Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name - 26 - - D -- INPUT ^ 0 0 0 4 a0 - 27 - - D -- INPUT ^ 0 0 0 4 a1 - 28 - - D -- INPUT ^ 0 0 0 4 a2 - 29 - - D -- INPUT ^ 0 0 0 4 a3 - 30 - - D -- INPUT ^ 0 0 0 4 a4 - 31 - - D -- INPUT ^ 0 0 0 4 a5 - 36 - - E -- INPUT ^ 0 0 0 4 A6 - 37 - - E -- INPUT ^ 0 0 0 4 A7 - 38 - - E -- INPUT ^ 0 0 0 15 A8 - 39 - - E -- INPUT ^ 0 0 0 5 a9 - 40 - - E -- INPUT ^ 0 0 0 15 A10 - 41 - - E -- INPUT ^ 0 0 0 5 a11 - 44 - - F -- INPUT ^ 0 0 0 5 A12 - 45 - - F -- INPUT ^ 0 0 0 6 A13 - 46 - - F -- INPUT ^ 0 0 0 11 A14 - 47 - - F -- INPUT ^ 0 0 0 11 A15 - 53 - - - 36 BIDIR ^ 0 1 0 29 D0 - 54 - - - 35 BIDIR ^ 0 1 0 28 D1 - 55 - - - 34 BIDIR ^ 0 1 0 30 d2 - 56 - - - 33 BIDIR ^ 0 1 0 24 d3 - 57 - - - 32 BIDIR ^ 0 1 0 24 d4 - 58 - - - 31 BIDIR ^ 0 1 0 20 d5 - 60 - - - 30 BIDIR ^ 0 1 0 21 d6 - 61 - - - 29 BIDIR ^ 0 1 0 21 d7 - 182 - - - -- INPUT ^ 0 0 0 0 /HALT - 78 - - - -- INPUT G ^ 0 0 0 23 /io - 196 - - - 27 BIDIR ^ 0 1 0 2 md0 - 193 - - - 25 BIDIR ^ 0 1 0 2 md1 - 190 - - - 22 BIDIR ^ 0 1 0 2 md2 - 186 - - - 19 BIDIR ^ 0 1 0 2 md3 - 164 - - - 06 BIDIR ^ 0 1 0 2 md4 - 163 - - - 06 BIDIR ^ 0 1 0 2 md5 - 162 - - - 05 BIDIR ^ 0 1 0 2 md6 - 161 - - - 04 BIDIR ^ 0 1 0 2 md7 - 8 - - A -- BIDIR ^ 0 1 0 3 md8 - 208 - - - 36 BIDIR ^ 0 1 0 3 md9 - 204 - - - 33 BIDIR ^ 0 1 0 3 md10 - 198 - - - 28 BIDIR ^ 0 1 0 3 md11 - 192 - - - 24 BIDIR ^ 0 1 0 3 md12 - 189 - - - 21 BIDIR ^ 0 1 0 3 md13 - 187 - - - 20 BIDIR ^ 0 1 0 3 md14 - 179 - - - 17 BIDIR ^ 0 1 0 3 md15 - 184 - - - -- INPUT G ^ 0 0 0 14 /mr - 24 - - C -- INPUT ^ 0 0 0 16 /m1 - 80 - - - -- INPUT ^ 0 0 0 10 /rd - 19 - - C -- OPNDRN ^ 0 1 0 79 /reset - 25 - - D -- INPUT ^ 0 0 0 8 /rf - 183 - - - -- INPUT G ^ 0 0 0 0 TG42 - 103 - - - 02 BIDIR ^ 0 1 0 1 VD00 - 113 - - F -- BIDIR ^ 0 1 0 1 VD01 - 116 - - F -- BIDIR ^ 0 1 0 1 VD02 - 121 - - E -- BIDIR ^ 0 1 0 1 VD03 - 126 - - D -- BIDIR ^ 0 1 0 1 VD04 - 125 - - D -- BIDIR ^ 0 1 0 1 VD05 - 119 - - E -- BIDIR ^ 0 1 0 1 VD06 - 112 - - F -- BIDIR ^ 0 1 0 1 VD07 - 104 - - - 01 BIDIR ^ 0 1 0 2 VD10 - 111 - - F -- BIDIR ^ 0 1 0 2 VD11 - 120 - - E -- BIDIR ^ 0 1 0 2 VD12 - 127 - - D -- BIDIR ^ 0 1 0 2 VD13 - 132 - - C -- BIDIR ^ 0 1 0 2 VD14 - 134 - - C -- BIDIR ^ 0 1 0 2 VD15 - 133 - - C -- BIDIR ^ 0 1 0 2 VD16 - 122 - - E -- BIDIR ^ 0 1 0 2 VD17 - 150 - - A -- BIDIR ^ 0 1 0 2 VD20 - 115 - - F -- BIDIR ^ 0 1 0 2 VD21 - 135 - - C -- BIDIR ^ 0 1 0 2 VD22 - 140 - - B -- BIDIR ^ 0 1 0 2 VD23 - 141 - - B -- BIDIR ^ 0 1 0 2 VD24 - 147 - - A -- BIDIR ^ 0 1 0 2 VD25 - 142 - - B -- BIDIR ^ 0 1 0 2 VD26 - 131 - - C -- BIDIR ^ 0 1 0 2 VD27 - 114 - - F -- BIDIR ^ 0 1 0 2 VD30 - 136 - - C -- BIDIR ^ 0 1 0 2 VD31 - 144 - - B -- BIDIR ^ 0 1 0 2 VD32 - 148 - - A -- BIDIR ^ 0 1 0 2 VD33 - 149 - - A -- BIDIR ^ 0 1 0 2 VD34 - 143 - - B -- BIDIR ^ 0 1 0 2 VD35 - 139 - - B -- BIDIR ^ 0 1 0 2 VD36 - 128 - - D -- BIDIR ^ 0 1 0 2 VD37 - 18 - - C -- BIDIR ^ 0 1 0 0 /wait - 79 - - - -- INPUT ^ 0 0 0 16 /wr - 180 - - - 18 OPNDRN ^ 0 1 0 1 XA0 - 9 - - A -- OPNDRN ^ 0 1 0 1 XA1 - 200 - - - 30 BIDIR ^ 0 1 0 2 XA2 - 17 - - C -- BIDIR ^ 0 0 0 2 XA3 - - -Code: - -s = Synthesized pin or logic cell -+ = Synchronous flipflop -/ = Slow slew-rate output -! = NOT gate push-back -r = Fitter-inserted logic cell -^ = Increased input delay -* = PCI I/O is enabled -@ = Uses single-pin Clock Enable -& = Uses single-pin Output Enable -G = Global Source. Fan-out destinations counted here do not include destinations -that are driven using global routing resources. Refer to the Auto Global Signals, -Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals -Sections of this Report File for information on which signals' fan-outs are used as -Clock, Clear, Preset, Output Enable, and synchronous Load signals. - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** OUTPUTS ** - - Fed By Fed By Fan-In Fan-Out - Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name - 12 - - B -- OUTPUT / 0 1 0 0 CAS_0 - 14 - - B -- OUTPUT / 0 1 0 0 CAS_1 - 13 - - B -- OUTPUT / 0 1 0 0 CAS_2 - 15 - - B -- OUTPUT / 0 1 0 0 CAS_3 - 62 - - - 28 OUTPUT 0 1 0 0 CLKZ1 - 64 - - - 26 OUTPUT / 0 1 0 0 CS_CASH - 63 - - - 27 OUTPUT / 0 1 0 0 cs_rom - 160 - - - 04 OUTPUT / 0 1 0 0 DAC_BCK - 158 - - - 02 OUTPUT / 0 1 0 0 DAC_DATA - 159 - - - 03 OUTPUT / 0 1 0 0 DAC_WS - 53 - - - 36 TRI / 0 1 0 29 D0 - 54 - - - 35 TRI / 0 1 0 28 D1 - 55 - - - 34 TRI / 0 1 0 30 d2 - 56 - - - 33 TRI / 0 1 0 24 d3 - 57 - - - 32 TRI / 0 1 0 24 d4 - 58 - - - 31 TRI / 0 1 0 20 d5 - 60 - - - 30 TRI / 0 1 0 21 d6 - 61 - - - 29 TRI / 0 1 0 21 d7 - 166 - - - 07 FF + / 0 1 0 0 ma0 - 167 - - - 08 FF + / 0 1 0 0 ma1 - 168 - - - 09 FF + / 0 1 0 0 ma2 - 170 - - - 11 FF + / 0 1 0 0 ma3 - 172 - - - 12 FF + / 0 1 0 0 ma4 - 174 - - - 14 FF + / 0 1 0 0 ma5 - 175 - - - 14 FF + / 0 1 0 0 ma6 - 197 - - - 28 FF + / 0 1 0 0 ma7 - 202 - - - 31 FF + / 0 1 0 0 ma8 - 203 - - - 32 FF + / 0 1 0 0 ma9 - 177 - - - 16 FF + / 0 1 0 0 ma10 - 199 - - - 29 FF + / 0 1 0 0 ma11 - 206 - - - 34 OUTPUT / 0 0 0 0 ma12 - 195 - - - 26 OUTPUT / 0 1 0 0 ma13 - 191 - - - 23 OUTPUT / 0 1 0 0 ma14 - 196 - - - 27 TRI / 0 1 0 2 md0 - 193 - - - 25 TRI / 0 1 0 2 md1 - 190 - - - 22 TRI / 0 1 0 2 md2 - 186 - - - 19 TRI / 0 1 0 2 md3 - 164 - - - 06 TRI / 0 1 0 2 md4 - 163 - - - 06 TRI / 0 1 0 2 md5 - 162 - - - 05 TRI / 0 1 0 2 md6 - 161 - - - 04 TRI / 0 1 0 2 md7 - 8 - - A -- TRI / 0 1 0 3 md8 - 208 - - - 36 TRI / 0 1 0 3 md9 - 204 - - - 33 TRI / 0 1 0 3 md10 - 198 - - - 28 TRI / 0 1 0 3 md11 - 192 - - - 24 TRI / 0 1 0 3 md12 - 189 - - - 21 TRI / 0 1 0 3 md13 - 187 - - - 20 TRI / 0 1 0 3 md14 - 179 - - - 17 TRI / 0 1 0 3 md15 - 207 - - - 35 OUTPUT / 0 1 0 0 RAS_0 - 205 - - - 34 OUTPUT / 0 1 0 0 RAS_1 - 65 - - - 26 OUTPUT / 0 1 0 0 ra14 - 69 - - - 23 OUTPUT / 0 1 0 0 ra15 - 68 - - - 24 OUTPUT / 0 1 0 0 ra16 - 67 - - - 25 OUTPUT / 0 1 0 0 ra17 - 10 - - A -- OUTPUT / 0 1 0 0 RD_KMPS - 173 - - - 13 FF + / 0 1 0 1 RDXA - 19 - - C -- OPNDRN / 0 1 0 79 /reset - 7 - - A -- FF + / 0 1 0 3 SXA - 102 - - - 03 FF + / 0 1 0 0 VA0 - 100 - - - 05 FF + / 0 1 0 0 VA1 - 97 - - - 07 FF + / 0 1 0 0 VA2 - 96 - - - 08 FF + / 0 1 0 0 VA3 - 94 - - - 09 FF + / 0 1 0 0 VA4 - 92 - - - 11 FF + / 0 1 0 0 VA5 - 89 - - - 13 FF + / 0 1 0 0 VA6 - 86 - - - 15 FF + / 0 1 0 0 VA7 - 90 - - - 12 FF + / 0 1 0 0 VA8 - 93 - - - 10 FF + / 0 1 0 0 VA9 - 99 - - - 06 FF + / 0 1 0 0 VA10 - 95 - - - 09 FF + / 0 1 0 0 VA11 - 74 - - - 20 FF + / 0 1 0 0 VA12 - 87 - - - 14 FF + / 0 1 0 0 VA13 - 73 - - - 20 FF + / 0 1 0 0 VA14 - 71 - - - 21 FF + / 0 1 0 0 VA15 - 101 - - - 04 OUTPUT / 0 0 0 0 v_cs0 - 70 - - - 22 OUTPUT / 0 0 0 0 v_cs1 - 103 - - - 02 TRI 0 1 0 1 VD00 - 113 - - F -- TRI 0 1 0 1 VD01 - 116 - - F -- TRI 0 1 0 1 VD02 - 121 - - E -- TRI 0 1 0 1 VD03 - 126 - - D -- TRI 0 1 0 1 VD04 - 125 - - D -- TRI 0 1 0 1 VD05 - 119 - - E -- TRI 0 1 0 1 VD06 - 112 - - F -- TRI 0 1 0 1 VD07 - 104 - - - 01 TRI 0 1 0 2 VD10 - 111 - - F -- TRI 0 1 0 2 VD11 - 120 - - E -- TRI 0 1 0 2 VD12 - 127 - - D -- TRI 0 1 0 2 VD13 - 132 - - C -- TRI 0 1 0 2 VD14 - 134 - - C -- TRI 0 1 0 2 VD15 - 133 - - C -- TRI 0 1 0 2 VD16 - 122 - - E -- TRI 0 1 0 2 VD17 - 150 - - A -- TRI 0 1 0 2 VD20 - 115 - - F -- TRI 0 1 0 2 VD21 - 135 - - C -- TRI 0 1 0 2 VD22 - 140 - - B -- TRI 0 1 0 2 VD23 - 141 - - B -- TRI 0 1 0 2 VD24 - 147 - - A -- TRI 0 1 0 2 VD25 - 142 - - B -- TRI 0 1 0 2 VD26 - 131 - - C -- TRI 0 1 0 2 VD27 - 114 - - F -- TRI 0 1 0 2 VD30 - 136 - - C -- TRI 0 1 0 2 VD31 - 144 - - B -- TRI 0 1 0 2 VD32 - 148 - - A -- TRI 0 1 0 2 VD33 - 149 - - A -- TRI 0 1 0 2 VD34 - 143 - - B -- TRI 0 1 0 2 VD35 - 139 - - B -- TRI 0 1 0 2 VD36 - 128 - - D -- TRI 0 1 0 2 VD37 - 83 - - - 17 OUTPUT 0 1 0 0 v_wr0 - 85 - - - 16 OUTPUT 0 1 0 0 v_wr1 - 75 - - - 19 OUTPUT 0 1 0 0 v_wr2 - 88 - - - 14 OUTPUT 0 1 0 0 v_wr3 - 18 - - C -- TRI / 0 1 0 0 /wait - 16 - - C -- OUTPUT / 0 1 0 0 /WE - 176 - - - 15 OUTPUT 0 1 0 0 wr_awg - 157 - - - 01 FF + / 0 1 0 0 WR_COL - 11 - - A -- OUTPUT / 0 1 0 0 wr_dwg - 169 - - - 10 OUTPUT / 0 1 0 0 XACS - 180 - - - 18 OPNDRN / 0 1 0 1 XA0 - 9 - - A -- OPNDRN / 0 1 0 1 XA1 - 200 - - - 30 TRI / 0 1 0 2 XA2 - 17 - - C -- TRI / 0 0 0 2 XA3 - - -Code: - -s = Synthesized pin or logic cell -+ = Synchronous flipflop -/ = Slow slew-rate output -! = NOT gate push-back -r = Fitter-inserted logic cell -^ = Increased input delay -* = PCI I/O is enabled -@ = Uses single-pin Clock Enable -& = Uses single-pin Output Enable - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** BURIED LOGIC ** - - Fan-In Fan-Out - IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name - - 1 - F 04 DFFE + 0 4 0 1 |acceler:ACC|AAGR0 - - 7 - F 05 DFFE + 0 3 0 1 |acceler:ACC|AAGR1 - - 1 - F 13 DFFE + 0 3 0 1 |acceler:ACC|AAGR2 - - 6 - F 13 DFFE + 0 3 0 1 |acceler:ACC|AAGR3 - - 8 - F 13 DFFE + 0 3 0 1 |acceler:ACC|AAGR4 - - 4 - F 13 DFFE + 0 3 0 1 |acceler:ACC|AAGR5 - - 5 - F 13 DFFE + 0 3 0 1 |acceler:ACC|AAGR6 - - 7 - F 13 DFFE + 0 3 0 1 |acceler:ACC|AAGR7 - - 2 - F 05 DFFE + 1 2 0 1 |acceler:ACC|AAGR8 - - 3 - F 05 DFFE + 1 2 0 1 |acceler:ACC|AAGR9 - - 1 - C 22 DFFE + 1 3 0 5 |acceler:ACC|AA0 - - 2 - C 36 DFFE + 1 3 0 8 |acceler:ACC|AA1 - - 2 - C 22 DFFE + 1 2 0 7 |acceler:ACC|AA2 - - 3 - C 22 DFFE + 1 2 0 3 |acceler:ACC|AA3 - - 4 - C 22 DFFE + 1 2 0 3 |acceler:ACC|AA4 - - 5 - C 22 DFFE + 1 2 0 5 |acceler:ACC|AA5 - - 6 - C 22 DFFE + 1 2 0 6 |acceler:ACC|AA6 - - 7 - C 22 DFFE + 1 2 0 5 |acceler:ACC|AA7 - - 8 - C 22 DFFE + 1 2 0 4 |acceler:ACC|AA8 - - 1 - C 24 DFFE + 1 2 0 3 |acceler:ACC|AA9 - - 2 - C 24 DFFE + 1 2 0 1 |acceler:ACC|AA10 - - 3 - C 24 DFFE + 1 2 0 1 |acceler:ACC|AA11 - - 4 - C 24 DFFE + 1 2 0 1 |acceler:ACC|AA12 - - 5 - C 24 DFFE + 1 2 0 2 |acceler:ACC|AA13 - - 6 - C 24 DFFE + 1 2 0 13 |acceler:ACC|AA14 - - 8 - C 24 DFFE + 1 2 0 11 |acceler:ACC|AA15 - - 3 - F 09 DFFE ! 1 2 0 2 |acceler:ACC|ACC_BLK - - 1 - E 17 DFFE + 0 3 0 3 |acceler:ACC|ACC_CNT0 - - 2 - E 17 DFFE + 0 4 0 3 |acceler:ACC|ACC_CNT1 - - 5 - E 11 DFFE + 0 3 0 2 |acceler:ACC|ACC_CNT2 - - 6 - E 11 DFFE + 0 3 0 2 |acceler:ACC|ACC_CNT3 - - 7 - E 11 DFFE + 0 3 0 2 |acceler:ACC|ACC_CNT4 - - 8 - E 11 DFFE + 0 3 0 2 |acceler:ACC|ACC_CNT5 - - 1 - E 13 DFFE + 0 3 0 2 |acceler:ACC|ACC_CNT6 - - 4 - E 13 DFFE + 0 1 0 3 |acceler:ACC|ACC_CNT7 - - 3 - F 16 DFFE + ! 1 4 0 1 |acceler:ACC|ACC_END - - 4 - F 03 DFFE + ! 0 4 0 7 |acceler:ACC|ACC_GO - - 2 - F 11 DFFE + 0 1 0 3 |acceler:ACC|ACC_GO_1 - - 5 - F 10 DFFE + 0 3 0 7 |acceler:ACC|ACC_MODE0 - - 6 - F 05 DFFE + 0 3 0 5 |acceler:ACC|ACC_MODE1 - - 3 - F 10 DFFE + 0 3 0 4 |acceler:ACC|ACC_MODE2 - - 2 - F 10 DFFE + 0 2 0 2 |acceler:ACC|ACC_MODE3 - - 2 - C 19 DFFE + 0 5 0 3 |acceler:ACC|AGR0 - - 3 - C 36 DFFE + 0 5 0 4 |acceler:ACC|AGR1 - - 3 - C 19 DFFE + 0 4 0 2 |acceler:ACC|AGR2 - - 4 - C 19 DFFE + 0 4 0 2 |acceler:ACC|AGR3 - - 5 - C 19 DFFE + 0 4 0 2 |acceler:ACC|AGR4 - - 6 - C 19 DFFE + 0 4 0 1 |acceler:ACC|AGR5 - - 7 - C 19 DFFE + 0 4 0 2 |acceler:ACC|AGR6 - - 8 - C 19 DFFE + 0 4 0 2 |acceler:ACC|AGR7 - - 7 - F 16 DFFE 0 2 0 8 |acceler:ACC|ALT_ACC - - 2 - D 30 LCELL 2 3 0 2 |acceler:ACC|CORRECT_1F - - 6 - E 22 DFFE + 0 4 0 1 |acceler:ACC|ED_CMD - - 5 - D 18 DFFE + 0 3 0 8 |acceler:ACC|FN_ACC0 - - 4 - D 18 DFFE + 0 3 0 8 |acceler:ACC|FN_ACC1 - - 7 - D 18 DFFE + 0 4 0 2 |acceler:ACC|GLISS_R - - 5 - D 01 DFFE + 0 4 0 1 |acceler:ACC|IN_OUT_CMD - - - 1 D -- MEM_SGMT 0 10 0 4 |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_0 - - - 14 D -- MEM_SGMT 0 10 0 4 |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_1 - - - 2 D -- MEM_SGMT 0 10 0 4 |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_2 - - - 11 D -- MEM_SGMT 0 10 0 4 |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_3 - - - 4 D -- MEM_SGMT 0 10 0 4 |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_4 - - - 10 D -- MEM_SGMT 0 10 0 4 |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_5 - - - 3 D -- MEM_SGMT 0 10 0 4 |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_6 - - - 9 D -- MEM_SGMT 0 10 0 4 |acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_7 - - 6 - D 17 DFFE + 0 3 0 1 |acceler:ACC|MDOX0 - - 6 - D 07 DFFE + 0 3 0 1 |acceler:ACC|MDOX1 - - 7 - D 07 DFFE + 0 3 0 1 |acceler:ACC|MDOX2 - - 4 - D 17 DFFE + 0 3 0 1 |acceler:ACC|MDOX3 - - 5 - D 17 DFFE + 0 3 0 1 |acceler:ACC|MDOX4 - - 6 - D 05 DFFE + 0 3 0 1 |acceler:ACC|MDOX5 - - 2 - D 05 DFFE + 0 3 0 1 |acceler:ACC|MDOX6 - - 3 - D 07 DFFE + 0 3 0 1 |acceler:ACC|MDOX7 - - 3 - D 17 DFFE + 0 3 0 1 |acceler:ACC|MDOY0 - - 5 - D 07 DFFE + 0 3 0 1 |acceler:ACC|MDOY1 - - 4 - D 07 DFFE + 0 3 0 1 |acceler:ACC|MDOY2 - - 7 - D 17 DFFE + 0 3 0 1 |acceler:ACC|MDOY3 - - 8 - D 17 DFFE + 0 3 0 1 |acceler:ACC|MDOY4 - - 5 - D 06 DFFE + 0 3 0 1 |acceler:ACC|MDOY5 - - 1 - D 05 DFFE + 0 3 0 1 |acceler:ACC|MDOY6 - - 2 - D 07 DFFE + 0 3 0 1 |acceler:ACC|MDOY7 - - 2 - D 17 DFFE 1 2 0 6 |acceler:ACC|/M1M - - 7 - D 01 DFFE + 0 4 0 3 |acceler:ACC|PRF_CMD - - 7 - A 34 OR2 0 3 0 8 |acceler:ACC|RAM_ADR0 - - 5 - C 28 OR2 0 3 0 8 |acceler:ACC|RAM_ADR1 - - 6 - E 19 OR2 0 3 0 8 |acceler:ACC|RAM_ADR2 - - 5 - E 15 OR2 0 3 0 8 |acceler:ACC|RAM_ADR3 - - 3 - A 23 OR2 0 3 0 8 |acceler:ACC|RAM_ADR4 - - 4 - E 15 OR2 0 3 0 8 |acceler:ACC|RAM_ADR5 - - 6 - E 13 OR2 0 3 0 8 |acceler:ACC|RAM_ADR6 - - 3 - E 15 OR2 0 3 0 8 |acceler:ACC|RAM_ADR7 - - 3 - F 03 DFFE + 1 3 0 8 |acceler:ACC|RAM_WR - - 3 - E 04 DFFE + 0 4 0 1 |acceler:ACC|RETI - - 6 - E 17 DFFE + 0 2 0 1 |acceler:ACC|RGACC0 - - 5 - E 17 DFFE + 0 2 0 1 |acceler:ACC|RGACC1 - - 3 - E 11 DFFE + 0 2 0 1 |acceler:ACC|RGACC2 - - 2 - E 11 DFFE + 0 2 0 1 |acceler:ACC|RGACC3 - - 1 - E 11 DFFE + 0 2 0 1 |acceler:ACC|RGACC4 - - 1 - E 04 DFFE + 0 2 0 1 |acceler:ACC|RGACC5 - - 5 - E 13 DFFE + 0 2 0 1 |acceler:ACC|RGACC6 - - 4 - E 04 DFFE + 0 2 0 1 |acceler:ACC|RGACC7 - - 8 - F 09 LCELL 0 3 0 5 |acceler:ACC|START_ACC - - 7 - F 24 DFFE + 1 3 0 2 |acceler:ACC|WR_C7 - - 4 - F 05 DFFE + 0 3 0 1 |acceler:ACC|XAGR0 - - 5 - F 18 DFFE + 0 3 0 1 |acceler:ACC|XAGR1 - - 4 - F 02 DFFE + 0 4 0 1 |acceler:ACC|XAGR2 - - 3 - F 18 DFFE + 0 4 0 1 |acceler:ACC|XAGR3 - - 1 - F 02 DFFE + 0 4 0 1 |acceler:ACC|XAGR4 - - 1 - F 18 DFFE + 0 4 0 1 |acceler:ACC|XAGR5 - - 3 - F 13 DFFE + 0 4 0 1 |acceler:ACC|XAGR6 - - 2 - F 13 DFFE + 0 4 0 1 |acceler:ACC|XAGR7 - - 2 - F 02 DFFE + 1 3 0 2 |acceler:ACC|XCNT0 - - 8 - F 02 DFFE + 1 3 0 2 |acceler:ACC|XCNT1 - - 1 - F 08 DFFE + 1 2 0 1 |acceler:ACC|XCNT2 - - 2 - F 08 DFFE + 1 2 0 1 |acceler:ACC|XCNT3 - - 3 - F 08 DFFE + 1 2 0 1 |acceler:ACC|XCNT4 - - 4 - F 08 DFFE + 1 2 0 1 |acceler:ACC|XCNT5 - - 5 - F 08 DFFE + 0 2 0 1 |acceler:ACC|XCNT6 - - 6 - F 08 DFFE + 0 2 0 1 |acceler:ACC|XCNT7 - - 3 - D 08 DFFE + 0 4 0 1 |acceler:ACC|XMD0 - - 1 - D 08 DFFE + 0 4 0 1 |acceler:ACC|XMD1 - - 7 - D 08 DFFE + 0 4 0 1 |acceler:ACC|XMD2 - - 8 - D 08 DFFE + 0 4 0 1 |acceler:ACC|XMD3 - - 5 - D 04 DFFE + 0 4 0 1 |acceler:ACC|XMD4 - - 5 - D 02 DFFE + 0 4 0 1 |acceler:ACC|XMD5 - - 6 - D 02 DFFE + 0 4 0 1 |acceler:ACC|XMD6 - - 1 - D 02 DFFE + 0 4 0 1 |acceler:ACC|XMD7 - - 6 - D 34 DFFE 0 2 0 5 |acceler:ACC|:229 - - 7 - D 34 DFFE 0 2 0 5 |acceler:ACC|:230 - - 8 - D 34 DFFE 0 2 0 5 |acceler:ACC|:231 - - 6 - D 30 DFFE 0 3 0 5 |acceler:ACC|:232 - - 7 - D 30 DFFE 0 3 0 4 |acceler:ACC|:233 - - 3 - D 30 DFFE 0 2 0 4 |acceler:ACC|:234 - - 3 - D 36 DFFE 0 2 0 4 |acceler:ACC|:235 - - 4 - D 30 DFFE 0 2 0 4 |acceler:ACC|:236 - - 1 - D 17 DFFE + 0 4 1 3 |acceler:ACC|:237 - - 6 - D 19 DFFE + 0 4 1 3 |acceler:ACC|:238 - - 1 - D 21 DFFE + 0 4 1 3 |acceler:ACC|:239 - - 5 - D 24 DFFE + 0 4 1 3 |acceler:ACC|:240 - - 3 - D 28 DFFE + 0 4 1 3 |acceler:ACC|:241 - - 5 - D 33 DFFE + 0 4 1 3 |acceler:ACC|:242 - - 3 - D 35 DFFE + 0 4 1 3 |acceler:ACC|:243 - - 3 - A 01 DFFE + 0 4 1 3 |acceler:ACC|:244 - - 6 - D 03 DFFE + 0 4 1 3 |acceler:ACC|:245 - - 3 - D 05 DFFE + 0 4 1 3 |acceler:ACC|:246 - - 4 - D 05 DFFE + 0 4 1 3 |acceler:ACC|:247 - - 8 - D 05 DFFE + 0 4 1 3 |acceler:ACC|:248 - - 8 - D 19 DFFE + 0 4 1 3 |acceler:ACC|:249 - - 2 - D 21 DFFE + 0 4 1 3 |acceler:ACC|:250 - - 5 - D 25 DFFE + 0 4 1 3 |acceler:ACC|:251 - - 2 - D 28 DFFE + 0 4 1 2 |acceler:ACC|:252 - - 8 - D 02 LCELL 0 3 0 2 |acceler:ACC|:253 - - 3 - D 02 LCELL 0 3 0 2 |acceler:ACC|:254 - - 2 - D 02 LCELL 0 3 0 2 |acceler:ACC|:255 - - 4 - D 04 LCELL 0 3 0 2 |acceler:ACC|:256 - - 2 - D 08 LCELL 0 3 0 2 |acceler:ACC|:257 - - 4 - D 08 LCELL 0 3 0 2 |acceler:ACC|:258 - - 5 - D 08 LCELL 0 3 0 2 |acceler:ACC|:259 - - 4 - D 02 LCELL 0 3 0 2 |acceler:ACC|:260 - - 4 - F 15 LCELL 0 3 0 10 |acceler:ACC|:262 - - 7 - F 11 LCELL 0 2 0 1 |acceler:ACC|:263 - - 5 - F 15 LCELL 0 2 0 1 |acceler:ACC|:264 - - 1 - F 15 LCELL 0 3 0 1 |acceler:ACC|:265 - - 7 - F 15 LCELL 0 1 0 2 |acceler:ACC|:266 - - 6 - F 10 LCELL 0 2 0 5 |acceler:ACC|:267 - - 8 - F 15 LCELL 0 3 0 2 |acceler:ACC|:268 - - 1 - F 10 DFFE 1 3 0 1 |acceler:ACC|:420 - - 2 - F 15 DFFE 2 2 0 8 |acceler:ACC|:424 - - 3 - F 24 DFFE + 1 2 0 1 |acceler:ACC|:425 - - 1 - F 24 DFFE + 0 4 0 1 |acceler:ACC|:426 - - 4 - C 14 SOFT s ! 0 1 0 32 |acceler:ACC|~427~1 - - 3 - E 13 DFFE + 0 2 0 26 |acceler:ACC|:427 - - 2 - F 03 DFFE + 2 2 0 2 |acceler:ACC|:428 - - 7 - F 03 LCELL 0 4 0 8 |acceler:ACC|:429 - - 4 - F 24 DFFE + 0 1 0 1 |acceler:ACC|:432 - - 5 - F 24 DFFE + 0 4 0 1 |acceler:ACC|:433 - - 8 - F 03 LCELL 0 4 0 26 |acceler:ACC|:435 - - 6 - F 09 LCELL 3 1 0 1 |acceler:ACC|:438 - - 4 - F 11 LCELL 0 2 0 4 |acceler:ACC|:439 - - 5 - D 13 DFFE 1 4 0 4 |acceler:ACC|:440 - - 1 - D 13 LCELL 0 4 0 1 |acceler:ACC|:441 - - 6 - D 18 LCELL 0 4 0 1 |acceler:ACC|:442 - - 8 - F 10 DFFE 0 2 0 1 |acceler:ACC|:443 - - 6 - F 16 DFFE + 0 2 0 10 |acceler:ACC|:444 - - 3 - D 18 LCELL 0 3 0 1 |acceler:ACC|:445 - - 5 - D 05 LCELL 0 4 0 1 |acceler:ACC|:446 - - 3 - D 10 LCELL 0 4 0 1 |acceler:ACC|:447 - - 1 - D 15 LCELL 0 2 0 8 |acceler:ACC|:448 - - 4 - A 01 LCELL 1 1 0 16 |acceler:ACC|:449 - - 5 - D 30 DFFE + 0 1 0 8 |acceler:ACC|:450 - - 8 - D 18 LCELL 0 3 0 2 |acceler:ACC|:451 - - 1 - F 11 LCELL 0 4 0 16 |acceler:ACC|:455 - - 4 - D 01 OR2 0 4 0 1 |acceler:ACC|:490 - - 3 - D 01 AND2 s 0 3 0 1 |acceler:ACC|~492~1 - - 1 - E 22 AND2 s 0 3 0 1 |acceler:ACC|~521~1 - - 2 - E 22 AND2 s 0 4 0 1 |acceler:ACC|~521~2 - - 3 - E 22 AND2 s 0 3 0 1 |acceler:ACC|~535~1 - - 4 - E 22 AND2 s 0 5 0 1 |acceler:ACC|~535~2 - - 4 - F 10 AND2 0 2 0 1 |acceler:ACC|:548 - - 1 - D 01 AND2 s 0 3 0 1 |acceler:ACC|~588~1 - - 2 - D 01 AND2 s 0 4 0 1 |acceler:ACC|~588~2 - - 4 - F 18 OR2 0 4 0 8 |acceler:ACC|:597 - - 7 - C 36 OR2 0 2 0 1 |acceler:ACC|:602 - - 4 - E 11 OR2 0 2 0 1 |acceler:ACC|:676 - - 2 - F 04 OR2 0 2 0 1 |acceler:ACC|:748 - - 3 - F 04 AND2 s 0 0 0 1 |acceler:ACC|~751~1 - - 4 - F 04 OR2 s 0 2 0 1 |acceler:ACC|~758~1 - - 5 - F 04 AND2 s 0 0 0 1 |acceler:ACC|~761~1 - - 6 - F 04 OR2 s 0 2 0 1 |acceler:ACC|~768~1 - - 7 - F 04 AND2 s 0 0 0 1 |acceler:ACC|~771~1 - - 8 - F 04 OR2 s 0 2 0 1 |acceler:ACC|~779~1 - - 1 - F 06 AND2 s 0 0 0 1 |acceler:ACC|~782~1 - - 2 - F 06 OR2 s 0 2 0 1 |acceler:ACC|~789~1 - - 3 - F 06 AND2 s 0 0 0 1 |acceler:ACC|~792~1 - - 4 - F 06 OR2 s 0 2 0 1 |acceler:ACC|~799~1 - - 5 - F 06 AND2 s 0 0 0 1 |acceler:ACC|~802~1 - - 6 - F 06 OR2 s 0 2 0 1 |acceler:ACC|~810~1 - - 7 - F 06 OR2 0 2 0 1 |acceler:ACC|:820 - - 8 - F 06 OR2 0 2 0 1 |acceler:ACC|:830 - - 5 - F 16 AND2 0 2 0 1 |acceler:ACC|:943 - - 7 - E 13 OR2 s 0 4 0 1 |acceler:ACC|~951~1 - - 7 - E 15 OR2 s 0 4 0 1 |acceler:ACC|~951~2 - - 4 - F 16 AND2 0 2 0 3 |acceler:ACC|:1012 - - 7 - F 10 AND2 0 2 0 1 |acceler:ACC|:1014 - - 6 - C 36 OR2 0 2 0 1 |acceler:ACC|:1374 - - 8 - F 11 OR2 0 3 0 1 |acceler:ACC|:1485 - - 1 - D 18 AND2 s 0 3 0 1 |acceler:ACC|~1534~1 - - 2 - D 18 AND2 s 0 4 0 1 |acceler:ACC|~1534~2 - - 8 - F 24 OR2 s 0 4 0 1 |acceler:ACC|~1609~1 - - 6 - F 24 AND2 s 0 4 0 1 |acceler:ACC|~1629~1 - - 6 - F 03 AND2 2 0 0 1 |acceler:ACC|:1634 - - 8 - D 30 AND2 s 0 4 0 1 |acceler:ACC|~1653~1 - - 1 - D 30 AND2 s 0 4 0 1 |acceler:ACC|~1653~2 - - 1 - F 26 DFFE ! 0 4 0 2 ALL_MODE0 - - 7 - F 26 DFFE ! 0 4 0 1 ALL_MODE2 - - 8 - F 26 DFFE ! 0 4 0 1 ALL_MODE3 - - 2 - A 36 DFFE 0 5 0 17 AUDIO_CH - - 8 - A 16 DFFE + 0 3 0 1 AUDIO_R0 - - 1 - A 16 DFFE + 0 4 0 1 AUDIO_R1 - - 8 - A 17 DFFE + 0 4 0 1 AUDIO_R2 - - 7 - A 17 DFFE + 0 4 0 1 AUDIO_R3 - - 4 - A 17 DFFE + 0 4 0 1 AUDIO_R4 - - 2 - A 13 DFFE + 0 4 0 1 AUDIO_R5 - - 7 - A 13 DFFE + 0 4 0 1 AUDIO_R6 - - 5 - A 13 DFFE + 0 4 0 1 AUDIO_R7 - - 4 - A 13 DFFE + 0 4 0 1 AUDIO_R8 - - 3 - A 13 DFFE + 0 4 0 1 AUDIO_R9 - - 8 - A 13 DFFE + 0 4 0 1 AUDIO_R10 - - 6 - A 13 DFFE + 0 4 0 1 AUDIO_R11 - - 2 - A 03 DFFE + 0 4 0 1 AUDIO_R12 - - 3 - A 03 DFFE + 0 4 0 1 AUDIO_R13 - - 6 - A 03 DFFE + 0 4 0 1 AUDIO_R14 - - 4 - A 03 DFFE + 0 4 0 1 AUDIO_R15 - - 8 - E 10 DFFE 0 5 0 1 |ay:AY3|AY_AAX0 - - 5 - B 11 DFFE + 0 4 0 1 |ay:AY3|AY_AA0 - - 3 - B 06 DFFE + 0 4 0 1 |ay:AY3|AY_AA1 - - 6 - B 06 DFFE + 0 4 0 1 |ay:AY3|AY_AA2 - - 3 - B 01 DFFE + 0 4 0 1 |ay:AY3|AY_AA3 - - 2 - B 06 DFFE + 0 2 0 4 |ay:AY3|AY_ABLK - - 6 - E 10 DFFE 0 2 0 3 |ay:AY3|AY_ADR0 - - 6 - E 02 DFFE 0 2 0 3 |ay:AY3|AY_ADR1 - - 3 - E 10 DFFE 0 2 0 3 |ay:AY3|AY_ADR2 - - 4 - E 02 DFFE 0 2 0 3 |ay:AY3|AY_ADR3 - - 5 - E 12 DFFE + 0 3 0 1 |ay:AY3|AY_AMP0 - - 8 - E 04 DFFE + 0 3 0 1 |ay:AY3|AY_AMP1 - - 6 - E 12 DFFE + 0 3 0 1 |ay:AY3|AY_AMP2 - - 7 - E 12 DFFE + 0 3 0 1 |ay:AY3|AY_AMP3 - - 6 - E 09 OR2 s 0 4 0 1 |ay:AY3|AY_AX0~1 - - 3 - E 09 OR2 0 3 0 8 |ay:AY3|AY_AX0 - - 5 - E 02 OR2 s 0 4 0 1 |ay:AY3|AY_AX1~1 - - 1 - E 06 OR2 0 3 0 8 |ay:AY3|AY_AX1 - - 7 - E 09 OR2 s 0 4 0 1 |ay:AY3|AY_AX2~1 - - 2 - E 09 OR2 0 3 0 8 |ay:AY3|AY_AX2 - - 8 - E 02 OR2 s 0 4 0 1 |ay:AY3|AY_AX3~1 - - 1 - E 02 OR2 0 3 0 8 |ay:AY3|AY_AX3 - - 2 - E 03 OR2 0 4 0 8 |ay:AY3|AY_AX4 - - 3 - E 03 AND2 0 3 0 8 |ay:AY3|AY_AX5 - - 6 - B 02 DFFE + 0 3 0 1 |ay:AY3|AY_BBLK - - 1 - B 06 DFFE + 0 4 0 4 |ay:AY3|AY_BINV - - 6 - E 26 DFFE + 0 1 0 2 |ay:AY3|AY_C - - 4 - E 01 DFFE + 0 1 0 16 |ay:AY3|AY_CCC0 - - 7 - E 28 DFFE + 0 1 0 40 |ay:AY3|AY_CCC1 - - 2 - E 14 DFFE + 0 1 0 3 |ay:AY3|AY_CCC2 - - 5 - E 28 DFFE + 0 1 0 2 |ay:AY3|AY_CCC3 - - 5 - E 19 DFFE + 0 1 0 2 |ay:AY3|AY_CCC4 - - 2 - E 29 DFFE + 0 1 0 2 |ay:AY3|AY_CCC5 - - 1 - A 10 DFFE + 0 1 0 12 |ay:AY3|AY_CCC6 - - 8 - E 03 DFFE + 0 1 0 4 |ay:AY3|AY_CCC7 - - 1 - E 07 DFFE + 0 4 0 4 |ay:AY3|AY_CH_CS0 - - 2 - E 07 DFFE + 0 4 0 2 |ay:AY3|AY_CH_CS1 - - 4 - E 07 DFFE + 0 4 0 2 |ay:AY3|AY_CH_CS2 - - 7 - E 07 DFFE + 0 4 0 2 |ay:AY3|AY_CH_CS3 - - 8 - E 07 DFFE + 0 4 0 2 |ay:AY3|AY_CH_CS4 - - 3 - E 12 DFFE + 0 3 0 2 |ay:AY3|AY_CH_CS5 - - 3 - E 07 DFFE + 0 4 0 2 |ay:AY3|AY_CH_CS6 - - 5 - E 07 DFFE + 0 4 0 2 |ay:AY3|AY_CH_CS7 - - 6 - E 07 DFFE + 0 4 0 2 |ay:AY3|AY_CH_CS8 - - 8 - A 12 DFFE + 0 3 0 1 |ay:AY3|AY_CH_LX0 - - 6 - A 18 DFFE + 0 3 0 2 |ay:AY3|AY_CH_LX1 - - 5 - A 18 DFFE + 0 3 0 2 |ay:AY3|AY_CH_LX2 - - 7 - A 18 DFFE + 0 3 0 2 |ay:AY3|AY_CH_LX3 - - 1 - A 02 DFFE + 0 3 0 2 |ay:AY3|AY_CH_LX4 - - 2 - A 02 DFFE + 0 3 0 2 |ay:AY3|AY_CH_LX5 - - 7 - A 04 DFFE + 0 3 0 2 |ay:AY3|AY_CH_LX6 - - 8 - A 04 DFFE + 0 3 0 2 |ay:AY3|AY_CH_LX7 - - 6 - A 04 DFFE + 0 3 0 2 |ay:AY3|AY_CH_LX8 - - 4 - A 04 DFFE + 0 2 0 1 |ay:AY3|AY_CH_LX9 - - 5 - A 04 DFFE + 0 2 0 1 |ay:AY3|AY_CH_LX10 - - 6 - E 27 DFFE + 0 3 0 4 |ay:AY3|AY_CH_MIX - - 1 - A 12 DFFE + 0 3 0 1 |ay:AY3|AY_CH_RX0 - - 1 - A 06 DFFE + 0 3 0 2 |ay:AY3|AY_CH_RX1 - - 2 - A 06 DFFE + 0 3 0 2 |ay:AY3|AY_CH_RX2 - - 5 - A 12 DFFE + 0 3 0 2 |ay:AY3|AY_CH_RX3 - - 6 - A 12 DFFE + 0 3 0 2 |ay:AY3|AY_CH_RX4 - - 3 - A 12 DFFE + 0 3 0 2 |ay:AY3|AY_CH_RX5 - - 8 - A 08 DFFE + 0 3 0 2 |ay:AY3|AY_CH_RX6 - - 6 - A 08 DFFE + 0 3 0 2 |ay:AY3|AY_CH_RX7 - - 7 - A 08 DFFE + 0 3 0 2 |ay:AY3|AY_CH_RX8 - - 4 - A 08 DFFE + 0 2 0 1 |ay:AY3|AY_CH_RX9 - - 5 - A 08 DFFE + 0 2 0 1 |ay:AY3|AY_CH_RX10 - - 2 - E 16 DFFE + ! 0 5 0 5 |ay:AY3|AY_CX - - 4 - E 16 DFFE + ! 0 5 0 3 |ay:AY3|AY_CXX - - 8 - E 28 DFFE + 0 2 0 1 |ay:AY3|AY_DAT_WR - - 2 - E 19 DFFE + 0 3 0 5 |ay:AY3|AY_DAT0 - - 4 - E 19 DFFE + 0 4 0 5 |ay:AY3|AY_DAT1 - - 6 - E 21 DFFE + 0 4 0 5 |ay:AY3|AY_DAT2 - - 7 - E 26 DFFE + 0 3 0 5 |ay:AY3|AY_DAT3 - - 2 - E 26 DFFE + 0 2 0 7 |ay:AY3|AY_DAT4 - - 3 - E 26 DFFE + 0 2 0 3 |ay:AY3|AY_DAT5 - - 4 - E 26 DFFE + 0 2 0 2 |ay:AY3|AY_DAT6 - - 5 - E 26 DFFE + 0 2 0 2 |ay:AY3|AY_DAT7 - - 7 - E 19 DFFE + 0 2 0 1 |ay:AY3|AY_DD0 - - 3 - E 19 DFFE + 0 2 0 1 |ay:AY3|AY_DD1 - - 8 - E 19 DFFE + 0 2 0 1 |ay:AY3|AY_DD2 - - 3 - E 31 DFFE + 0 2 0 1 |ay:AY3|AY_DD3 - - 4 - E 31 DFFE + 0 2 0 1 |ay:AY3|AY_DD4 - - 2 - E 31 DFFE + 0 2 0 1 |ay:AY3|AY_DD5 - - 8 - E 31 DFFE + 0 2 0 1 |ay:AY3|AY_DD6 - - 7 - E 31 DFFE + 0 2 0 1 |ay:AY3|AY_DD7 - - 3 - E 17 OR2 0 4 0 1 |ay:AY3|AY_DI0 - - 4 - E 10 OR2 0 4 0 1 |ay:AY3|AY_DI1 - - 6 - E 01 OR2 0 4 0 1 |ay:AY3|AY_DI2 - - 4 - E 17 OR2 0 4 0 1 |ay:AY3|AY_DI3 - - 8 - E 01 OR2 0 4 0 1 |ay:AY3|AY_DI4 - - 6 - E 08 OR2 0 4 0 1 |ay:AY3|AY_DI5 - - 8 - E 08 OR2 0 4 0 1 |ay:AY3|AY_DI6 - - 4 - E 08 OR2 0 4 0 1 |ay:AY3|AY_DI7 - - 8 - E 12 DFFE + 0 5 0 8 |ay:AY3|AY_DQX0 - - 2 - E 06 DFFE + 0 4 0 9 |ay:AY3|AY_DQX1 - - 1 - E 12 DFFE + 0 5 0 9 |ay:AY3|AY_DQX2 - - 2 - E 12 DFFE + 0 5 0 9 |ay:AY3|AY_DQX3 - - 5 - E 03 DFFE 0 3 0 7 |ay:AY3|AY_F_RES - - 5 - E 10 DFFE + 0 2 0 2 |ay:AY3|AY_F_R1 - - 7 - E 06 DFFE + 0 2 0 2 |ay:AY3|AY_GF0 - - 7 - E 04 DFFE + 0 2 0 1 |ay:AY3|AY_GF1 - - 8 - E 06 DFFE + 0 2 0 4 |ay:AY3|AY_GF2 - - 2 - E 04 DFFE + 0 2 0 3 |ay:AY3|AY_GF3 - - 5 - E 04 DFFE + 0 4 0 4 |ay:AY3|AY_OUTSX - - 1 - E 35 DFFE + 0 4 0 4 |ay:AY3|AY_OUTS1 - - 6 - E 25 DFFE + 0 1 0 1 |ay:AY3|AY_OUTS1X - - 2 - E 21 DFFE + 0 2 0 1 |ay:AY3|AY_OUTS1Y - - 5 - E 35 DFFE + 0 4 0 4 |ay:AY3|AY_OUTS2 - - 6 - E 36 DFFE + 0 2 0 2 |ay:AY3|AY_OUTS2X - - 2 - E 35 DFFE + 0 4 0 4 |ay:AY3|AY_OUTS3 - - 5 - E 36 DFFE + 0 1 0 1 |ay:AY3|AY_OUTS3X - - 1 - E 36 DFFE + 0 2 0 1 |ay:AY3|AY_OUTS3Y - - 3 - E 29 DFFE + 0 2 0 1 |ay:AY3|AY_OUT1 - - 4 - E 36 DFFE + 0 2 0 1 |ay:AY3|AY_OUT2 - - 1 - E 29 DFFE + 0 2 0 1 |ay:AY3|AY_OUT3 - - 3 - E 05 DFFE + 0 4 0 7 |ay:AY3|AY_SH_Q - - 2 - D 20 DFFE + ! 0 3 0 4 |ay:AY3|AY_SH0 - - 7 - D 20 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH1 - - 6 - D 20 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH2 - - 4 - D 20 DFFE + ! 0 3 0 2 |ay:AY3|AY_SH3 - - 2 - D 25 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH4 - - 4 - D 25 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH5 - - 3 - D 25 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH6 - - 1 - D 25 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH7 - - 6 - D 25 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH8 - - 7 - D 25 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH9 - - 8 - D 25 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH10 - - 4 - D 24 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH11 - - 8 - D 24 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH12 - - 7 - D 24 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH13 - - 3 - D 24 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH14 - - 2 - D 24 DFFE + ! 0 3 0 1 |ay:AY3|AY_SH15 - - 8 - D 20 DFFE + ! 0 4 0 1 |ay:AY3|AY_SH16 - - 2 - B 02 DFFE + 0 3 0 1 |ay:AY3|AY_VAR - - 1 - B 02 DFFE + 0 3 0 2 |ay:AY3|AY_VA0 - - 3 - B 02 DFFE + 0 2 0 1 |ay:AY3|AY_VA1 - - 4 - B 02 DFFE + 0 2 0 1 |ay:AY3|AY_VA2 - - 5 - B 02 DFFE + 0 2 0 1 |ay:AY3|AY_VA3 - - 7 - B 02 DFFE + 0 2 0 3 |ay:AY3|AY_VX - - 1 - E 10 OR2 0 4 0 8 |ay:AY3|AY_WR - - 8 - E 27 DFFE + 0 2 0 1 |ay:AY3|AY_X_0 - - 7 - E 27 DFFE + 0 2 0 1 |ay:AY3|AY_X_1 - - 6 - E 29 DFFE + 0 2 0 1 |ay:AY3|AY_X_2 - - 5 - E 27 DFFE + 0 2 0 1 |ay:AY3|AY_X_3 - - 4 - E 27 DFFE + 0 2 0 1 |ay:AY3|AY_X_4 - - 5 - E 29 DFFE + 0 2 0 1 |ay:AY3|AY_X_5 - - 8 - E 17 DFFE + 0 2 0 1 |ay:AY3|BD0 - - 7 - E 10 DFFE + 0 2 0 1 |ay:AY3|BD1 - - 7 - E 01 DFFE + 0 2 0 1 |ay:AY3|BD2 - - 7 - E 17 DFFE + 0 2 0 1 |ay:AY3|BD3 - - 3 - E 02 DFFE + 0 3 0 1 |ay:AY3|BD4 - - 7 - E 08 DFFE + 0 3 0 1 |ay:AY3|BD5 - - 5 - E 08 DFFE + 0 3 0 1 |ay:AY3|BD6 - - 3 - E 08 DFFE + 0 3 0 1 |ay:AY3|BD7 - - 6 - E 28 DFFE + 0 2 0 2 |ay:AY3|BWR - - 4 - A 02 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node1 - - 5 - A 02 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node2 - - 6 - A 02 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node3 - - 7 - A 02 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node4 - - 8 - A 02 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node5 - - 1 - A 04 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node6 - - 2 - A 04 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node7 - - 3 - A 04 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node8 - - 4 - A 06 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node1 - - 5 - A 06 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node2 - - 6 - A 06 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node3 - - 7 - A 06 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node4 - - 8 - A 06 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node5 - - 1 - A 08 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node6 - - 2 - A 08 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node7 - - 3 - A 08 OR2 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node8 - - - 5 E -- MEM_SGMT 0 10 0 17 |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_0 - - - 11 E -- MEM_SGMT 0 10 0 14 |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_1 - - - 3 E -- MEM_SGMT 0 10 0 12 |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_2 - - - 12 E -- MEM_SGMT 0 10 0 4 |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_3 - - - 4 E -- MEM_SGMT 0 10 0 3 |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_4 - - - 13 E -- MEM_SGMT 0 10 0 15 |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_5 - - - 2 E -- MEM_SGMT 0 10 0 15 |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_6 - - - 9 E -- MEM_SGMT 0 10 0 15 |ay:AY3|lpm_ram_dq:90|altram:sram|segment0_7 - - 6 - E 03 DFFE 0 2 0 1 |ay:AY3|:420 - - 2 - E 10 LCELL 0 4 0 1 |ay:AY3|:421 - - 5 - E 16 DFFE + 0 4 0 2 |ay:AY3|:422 - - 3 - E 16 DFFE + 0 4 0 2 |ay:AY3|:424 - - 6 - E 16 DFFE + 0 3 0 2 |ay:AY3|:425 - - 8 - E 16 LCELL 0 1 0 1 |ay:AY3|:426 - - 4 - E 09 LCELL 0 1 0 1 |ay:AY3|:427 - - 1 - E 09 DFFE + 0 1 0 1 |ay:AY3|:428 - - 7 - E 16 DFFE + 0 3 0 2 |ay:AY3|:430 - - 1 - E 28 SOFT s ! 0 1 0 9 |ay:AY3|~431~1 - - 4 - E 28 DFFE + 0 1 0 1 |ay:AY3|:431 - - 1 - E 31 DFFE + 0 3 0 4 |ay:AY3|:432 - - 6 - E 31 DFFE + 0 1 0 1 |ay:AY3|:433 - - 5 - E 31 DFFE + 0 1 0 1 |ay:AY3|:434 - - 4 - E 12 DFFE + 0 2 0 3 |ay:AY3|:442 - - 3 - E 27 LCELL 0 4 0 1 |ay:AY3|:443 - - 2 - E 27 LCELL 0 4 0 1 |ay:AY3|:444 - - 7 - E 29 LCELL 0 4 0 1 |ay:AY3|:445 - - 2 - E 28 DFFE + 0 4 0 6 |ay:AY3|:447 - - 4 - E 35 DFFE + 0 4 0 6 |ay:AY3|:448 - - 4 - E 06 DFFE + 0 4 0 4 |ay:AY3|:449 - - 7 - E 03 DFFE + 0 4 0 22 |ay:AY3|:458 - - 2 - A 18 DFFE + 0 1 0 11 |ay:AY3|:459 - - 7 - E 33 DFFE + 0 4 0 1 |ay:AY3|:460 - - 5 - A 03 DFFE + 0 1 0 11 |ay:AY3|:461 - - 7 - E 36 DFFE + 0 4 0 1 |ay:AY3|:462 - - 7 - E 02 OR2 ! 0 4 0 3 |ay:AY3|:481 - - 2 - E 02 OR2 ! 0 4 0 1 |ay:AY3|:495 - - 3 - E 01 AND2 ! 0 2 0 16 |ay:AY3|:536 - - 1 - E 16 OR2 s 0 2 0 1 |ay:AY3|~647~1 - - 5 - E 09 OR2 ! 0 4 0 1 |ay:AY3|:650 - - 1 - E 19 OR2 0 2 0 1 |ay:AY3|:671 - - 8 - E 26 AND2 ! 0 4 0 2 |ay:AY3|:687 - - 1 - E 27 OR2 s 0 3 0 1 |ay:AY3|~778~1 - - 7 - E 25 AND2 0 2 0 17 |ay:AY3|:779 - - 4 - E 03 AND2 s 0 3 0 1 |ay:AY3|~1027~1 - - 3 - E 06 AND2 s 0 4 0 1 |ay:AY3|~1060~1 - - 3 - E 35 AND2 s 0 4 0 1 |ay:AY3|~1071~1 - - 5 - E 05 AND2 s 0 4 0 1 |ay:AY3|~1085~1 - - 2 - E 05 AND2 s 0 3 0 1 |ay:AY3|~1085~2 - - 4 - E 05 AND2 s 0 4 0 1 |ay:AY3|~1095~1 - - 1 - E 05 OR2 s 0 4 0 1 |ay:AY3|~1123~1 - - 8 - E 35 AND2 s 0 4 0 1 |ay:AY3|~1137~1 - - 7 - E 35 AND2 s 0 4 0 1 |ay:AY3|~1150~1 - - 6 - E 35 AND2 s 0 4 0 1 |ay:AY3|~1163~1 - - 1 - E 08 AND2 s 0 4 0 1 |ay:AY3|~1193~1 - - 2 - E 08 AND2 ! 0 5 0 2 |ay:AY3|:1193 - - 4 - A 16 DFFE 0 2 0 1 AY_CHS0 - - 3 - A 16 DFFE 0 2 0 1 AY_CHS1 - - 3 - A 17 DFFE 0 2 0 1 AY_CHS2 - - 2 - A 17 DFFE 0 2 0 1 AY_CHS3 - - 1 - A 17 DFFE 0 2 0 1 AY_CHS4 - - 1 - A 13 DFFE 0 3 0 1 AY_CHS5 - - 4 - C 02 DFFE 0 3 0 1 AY_CHS6 - - 5 - C 02 DFFE 0 3 0 1 AY_CHS7 - - 6 - C 02 DFFE 0 3 0 1 AY_CHS8 - - 7 - C 02 DFFE 0 3 0 1 AY_CHS9 - - 8 - C 02 DFFE 0 3 0 1 AY_CHS10 - - 1 - C 04 DFFE 0 3 0 1 AY_CHS11 - - 2 - C 04 DFFE 0 3 0 1 AY_CHS12 - - 3 - C 04 DFFE 0 3 0 1 AY_CHS13 - - 5 - C 04 DFFE 0 1 0 1 AY_CHS14 - - 4 - C 04 DFFE 0 3 0 1 AY_CHS15 - - 3 - C 02 DFFE + 0 4 0 1 AY_FULL1 - - 3 - A 10 DFFE + 0 3 0 1 AY_FULL2 - - 2 - A 12 DFFE + 0 3 0 1 AY_FULL3 - - 4 - A 12 DFFE + 0 3 0 1 AY_FULL4 - - 7 - A 12 DFFE + 0 3 0 1 AY_FULL5 - - 7 - A 10 DFFE + 0 3 0 1 AY_FULL6 - - 5 - A 10 DFFE + 0 3 0 1 AY_FULL7 - - 4 - A 10 DFFE + 0 3 0 1 AY_FULL8 - - 1 - A 18 DFFE + 0 3 0 1 AY_FULL9 - - 2 - A 10 DFFE + 0 3 0 1 AY_FULL10 - - 8 - D 26 LCELL 0 3 0 1 AY/PORTS0 - - 4 - D 36 LCELL 0 3 0 1 AY/PORTS1 - - 6 - D 23 LCELL 0 3 0 1 AY/PORTS2 - - 6 - D 32 LCELL 0 3 0 1 AY/PORTS3 - - 4 - D 32 LCELL 0 3 0 1 AY/PORTS4 - - 6 - A 26 LCELL 0 3 0 1 AY/PORTS5 - - 6 - D 29 LCELL 0 3 0 1 AY/PORTS6 - - 7 - A 31 LCELL 0 3 0 1 AY/PORTS7 - - 6 - C 18 LCELL 0 3 0 3 blk_mem - - 4 - C 18 LCELL 0 4 0 1 BLK_MR - - 5 - E 23 DFFE 0 3 0 2 BORDER0 - - 3 - E 23 DFFE 0 3 0 2 BORDER1 - - 2 - E 23 DFFE 0 3 0 2 BORDER2 - - 7 - E 23 DFFE 0 3 0 1 BORDER3 - - 1 - E 23 DFFE 0 3 0 1 BORDER4 - - 3 - B 36 LCELL 0 1 0 4 CAS_A - - 8 - C 25 DFFE 1 3 0 2 CASH_ON - - 7 - B 36 LCELL 0 2 0 2 CASXE0 - - 8 - B 36 LCELL 0 2 0 2 CASXE1 - - 1 - B 36 LCELL 0 4 1 0 CASX_0 - - 5 - B 36 LCELL 0 4 1 0 CASX_1 - - 2 - B 36 LCELL 0 4 1 0 CASX_2 - - 6 - B 36 LCELL 0 4 1 0 CASX_3 - - 4 - A 05 DFFE 0 4 0 1 CBD1 - - 5 - A 05 DFFE 0 4 0 1 CBD2 - - 8 - A 05 DFFE 0 4 0 1 CBD3 - - 7 - A 05 DFFE 0 4 0 1 CBD4 - - 3 - A 05 DFFE 0 4 0 1 CBD5 - - 2 - A 05 DFFE 0 4 0 1 CBD6 - - 1 - A 05 DFFE 0 4 0 1 CBD7 - - 4 - A 19 DFFE 0 5 0 2 CBL_CNT0 - - 8 - A 24 DFFE 0 5 0 18 CBL_CNT1 - - 1 - A 24 DFFE 0 5 0 18 CBL_CNT2 - - 7 - A 19 DFFE 0 4 0 18 CBL_CNT3 - - 3 - A 24 DFFE 0 4 0 17 CBL_CNT4 - - 4 - A 24 DFFE 0 4 0 17 CBL_CNT5 - - 3 - A 21 DFFE 0 4 0 19 CBL_CNT6 - - 8 - A 32 SOFT s ! 0 1 0 1 CBL_CNT7~1 - - 6 - A 24 DFFE 0 4 0 18 CBL_CNT7 - - 3 - E 36 DFFE 0 3 0 5 CBL_CTX0 - - 2 - E 36 DFFE 0 4 0 4 CBL_CTX1 - - 8 - E 30 DFFE 0 4 0 3 CBL_CTX2 - - 7 - E 30 DFFE 0 4 0 2 CBL_CTX3 - - 6 - E 30 DFFE 0 4 0 1 CBL_CTX4 - - 5 - A 25 DFFE ! 0 2 0 4 CBL_INT - - 6 - A 16 DFFE + 0 4 0 1 CBL_R1 - - 5 - A 16 DFFE + 0 4 0 1 CBL_R2 - - 6 - A 17 DFFE + 0 4 0 1 CBL_R3 - - 5 - A 17 DFFE + 0 4 0 1 CBL_R4 - - 4 - A 11 DFFE + 0 4 0 1 CBL_R5 - - 2 - A 11 DFFE + 0 4 0 2 CBL_R6 - - 6 - A 11 DFFE + 0 4 0 1 CBL_R7 - - 4 - A 18 DFFE + 0 5 0 1 CBL_R8 - - 2 - A 16 DFFE + 0 5 0 1 CBL_R9 - - 3 - A 18 DFFE + 0 5 0 1 CBL_R10 - - 8 - A 18 DFFE + 0 5 0 1 CBL_R11 - - 7 - A 16 DFFE + 0 5 0 1 CBL_R12 - - 4 - A 14 DFFE + 0 5 0 1 CBL_R13 - - 7 - A 11 DFFE + 0 5 0 1 CBL_R14 - - 5 - A 14 DFFE + ! 0 5 0 1 CBL_R15 - - 8 - A 20 LCELL 0 3 0 1 CBL_TAB0 - - 7 - A 20 LCELL 0 4 0 1 CBL_TAB1 - - 4 - A 20 LCELL 0 4 0 1 CBL_TAB2 - - 4 - A 23 LCELL 0 4 0 1 CBL_TAB3 - - 3 - A 20 LCELL 0 3 0 1 CBL_TAB4 - - 6 - C 08 OR2 ! 0 2 0 10 CBL_WAE - - 8 - A 33 DFFE 0 3 0 3 CBL_WA0 - - 1 - A 33 DFFE 0 4 0 2 CBL_WA1 - - 2 - A 33 DFFE 0 4 0 2 CBL_WA2 - - 3 - A 33 DFFE 0 4 0 2 CBL_WA3 - - 1 - A 34 DFFE 0 4 0 2 CBL_WA4 - - 7 - A 33 DFFE 0 4 0 2 CBL_WA5 - - 5 - A 33 DFFE 0 4 0 2 CBL_WA6 - - 7 - A 32 DFFE 0 5 0 2 CBL_WA7 - - 2 - C 08 OR2 ! 0 3 0 16 CBL_WR - - 1 - A 25 DFFE 0 3 0 3 CBL_XX0 - - 2 - A 20 DFFE 0 3 0 5 CBL_XX1 - - 1 - A 20 DFFE 0 3 0 5 CBL_XX2 - - 5 - A 20 DFFE 0 3 0 5 CBL_XX3 - - 2 - A 25 DFFE 0 3 0 12 CBL_XX4 - - 2 - A 14 DFFE 0 3 0 9 CBL_XX5 - - 3 - A 25 DFFE 0 3 0 12 CBL_XX6 - - 6 - A 25 DFFE 0 3 0 28 CBL_XX7 - - 2 - F 27 DFFE + 0 2 0 7 copy_sinc_h - - 6 - F 19 DFFE + 0 2 0 9 copy_sinc_v - - 8 - C 23 DFFE + ! 1 3 0 2 CS_CASHT - - 5 - C 33 DFFE + ! 1 2 0 3 CS_ISA - - 5 - C 27 DFFE + ! 1 3 1 2 CS_ROMT - - 1 - C 03 DFFE 0 5 0 1 |dcp:DECODE|AROM16 - - 2 - C 21 LCELL 0 3 0 2 |dcp:DECODE|BLK_C - - 1 - C 06 DFFE + 0 2 0 14 |dcp:DECODE|CLK21 - - 3 - C 31 DFFE 0 5 0 1 |dcp:DECODE|CNF3 - - 6 - C 27 DFFE 0 5 0 2 |dcp:DECODE|CNF4 - - 5 - D 14 DFFE 0 5 0 2 |dcp:DECODE|CNF5 - - 2 - D 12 DFFE 0 5 0 1 |dcp:DECODE|CNF6 - - 1 - D 12 DFFE 0 5 0 3 |dcp:DECODE|CNF7 - - 3 - D 19 DFFE + 2 1 0 1 |dcp:DECODE|DCP_RES - - 7 - D 26 DFFE + 0 5 0 1 |dcp:DECODE|DD0 - - 2 - D 26 DFFE + 0 5 0 1 |dcp:DECODE|DD1 - - 2 - D 33 DFFE + 0 5 0 1 |dcp:DECODE|DD2 - - 4 - D 33 DFFE + 0 5 0 1 |dcp:DECODE|DD3 - - 1 - D 20 DFFE + 0 4 0 1 |dcp:DECODE|DD4 - - 3 - D 34 DFFE + 0 5 0 1 |dcp:DECODE|DD5 - - 6 - D 26 DFFE + 0 4 0 1 |dcp:DECODE|DD6 - - 5 - D 20 DFFE + 0 4 0 1 |dcp:DECODE|DD7 - - 1 - C 16 LCELL 0 4 0 2 |dcp:DECODE|GRAF_X - - 4 - C 32 DFFE + 0 4 0 1 |dcp:DECODE|HDD_A0 - - 4 - C 16 DFFE + 0 3 0 1 |dcp:DECODE|HDD_A1 - - 4 - C 30 DFFE + 0 3 0 1 |dcp:DECODE|HDD_A2 - - 7 - D 03 DFFE + ! 0 3 0 3 |dcp:DECODE|/IOMX - - 8 - D 03 SOFT s ! 0 1 0 1 |dcp:DECODE|/IOMX~1 - - 3 - C 12 DFFE + ! 0 5 0 1 |dcp:DECODE|/IOMY - - 2 - C 06 DFFE + ! 0 5 0 1 |dcp:DECODE|/IOMZ - - 1 - E 21 DFFE + ! 2 0 0 27 |dcp:DECODE|IO_RW - - 6 - C 34 DFFE + ! 1 1 0 1 |dcp:DECODE|IO_RWM - - 5 - C 34 LCELL 0 2 0 1 |dcp:DECODE|/IO_WAIT - - 2 - D 13 LCELL 3 0 0 19 |dcp:DECODE|/IOWR - - - 2 C -- MEM_SGMT 0 10 0 3 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_0 - - - 16 C -- MEM_SGMT 0 10 0 3 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_1 - - - 5 C -- MEM_SGMT 0 10 0 5 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_2 - - - 14 C -- MEM_SGMT 0 10 0 5 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_3 - - - 7 C -- MEM_SGMT 0 10 0 7 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_4 - - - 12 C -- MEM_SGMT 0 10 0 9 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_5 - - - 1 C -- MEM_SGMT 0 10 0 9 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_6 - - - 10 C -- MEM_SGMT 0 10 0 9 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_7 - - - 8 C -- MEM_SGMT 0 10 0 4 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_8 - - - 13 C -- MEM_SGMT 0 10 0 3 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_9 - - - 4 C -- MEM_SGMT 0 10 0 3 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_10 - - - 15 C -- MEM_SGMT 0 10 0 3 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_11 - - - 6 C -- MEM_SGMT 0 10 0 46 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_12 - - - 9 C -- MEM_SGMT 0 10 0 22 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_13 - - - 3 C -- MEM_SGMT 0 10 0 22 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_14 - - - 11 C -- MEM_SGMT 0 10 0 2 |dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_15 - - 6 - C 23 DFFE + 0 2 0 19 |dcp:DECODE|MA_CT0 - - 3 - C 23 DFFE + 0 3 0 15 |dcp:DECODE|MA_CT1 - - 4 - C 35 DFFE + 2 2 0 4 |dcp:DECODE|MC_RQ - - 7 - C 33 DFFE + ! 1 2 0 3 |dcp:DECODE|MEM_RW - - 1 - C 32 DFFE + 0 4 0 16 |dcp:DECODE|MEM_WR - - 6 - C 21 LCELL 0 4 0 1 |dcp:DECODE|MPGS0 - - 5 - C 36 LCELL 0 4 0 1 |dcp:DECODE|MPGS1 - - 2 - C 20 LCELL 0 4 0 1 |dcp:DECODE|MPGS2 - - 5 - C 21 LCELL 0 4 0 1 |dcp:DECODE|MPGS3 - - 7 - C 24 LCELL 0 2 0 1 |dcp:DECODE|MPGS4 - - 4 - C 21 LCELL 0 3 0 1 |dcp:DECODE|MPGS5 - - 4 - C 34 LCELL 0 4 0 1 |dcp:DECODE|/MR_WAIT - - 3 - C 20 DFFE + 0 4 0 16 |dcp:DECODE|PGS0 - - 8 - C 20 DFFE + 0 4 0 16 |dcp:DECODE|PGS1 - - 5 - C 20 DFFE + 0 4 0 16 |dcp:DECODE|PGS2 - - 3 - C 21 DFFE + 0 4 0 16 |dcp:DECODE|PGS3 - - 6 - C 20 DFFE + 0 4 0 16 |dcp:DECODE|PGS4 - - 7 - C 21 DFFE + 0 4 0 16 |dcp:DECODE|PGS5 - - 7 - C 20 DFFE + 0 3 0 16 |dcp:DECODE|PGS6 - - 1 - C 20 DFFE + 0 3 0 16 |dcp:DECODE|PGS7 - - 3 - C 15 LCELL 0 3 0 1 |dcp:DECODE|PG00 - - 2 - C 03 LCELL 0 3 0 1 |dcp:DECODE|PG01 - - 6 - C 03 LCELL 0 3 0 1 |dcp:DECODE|PG02 - - 6 - F 17 LCELL 0 2 0 1 |dcp:DECODE|PG03 - - 4 - D 16 LCELL 0 3 0 3 |dcp:DECODE|PG33 - - 8 - D 31 DFFE 0 4 0 3 |dcp:DECODE|PN0 - - 2 - D 31 DFFE 0 4 0 3 |dcp:DECODE|PN1 - - 7 - D 31 DFFE 0 4 0 4 |dcp:DECODE|PN2 - - 8 - D 13 DFFE 0 4 0 1 |dcp:DECODE|PN3 - - 6 - D 13 DFFE 0 4 0 2 |dcp:DECODE|PN4 - - 3 - D 14 DFFE 0 4 0 1 |dcp:DECODE|PN5 - - 4 - D 13 DFFE 0 4 0 1 |dcp:DECODE|PN6 - - 6 - D 31 DFFE 0 4 0 3 |dcp:DECODE|PN7 - - 8 - C 30 DFFE + 0 4 0 4 |dcp:DECODE|PORTS_X - - 3 - F 32 DFFE + 0 3 0 3 |dcp:DECODE|RFC - - 1 - F 32 DFFE ! 0 2 0 1 |dcp:DECODE|RFT - - 4 - D 12 DFFE 0 4 0 5 |dcp:DECODE|SC0 - - 5 - D 12 DFFE 0 4 0 2 |dcp:DECODE|SC1 - - 3 - D 12 DFFE 0 4 0 4 |dcp:DECODE|SC4 - - 2 - C 10 LCELL 0 3 0 1 |dcp:DECODE|SPR_0 - - 3 - C 03 LCELL 0 2 0 1 |dcp:DECODE|SPR_1 - - 1 - D 36 LCELL 2 1 0 3 |dcp:DECODE|STARTING - - 5 - C 03 DFFE 0 4 0 5 |dcp:DECODE|SYS - - 7 - D 21 DFFE + 0 4 0 8 |dcp:DECODE|SYS_ENA - - 6 - D 36 DFFE ! 0 5 0 1 |dcp:DECODE|TB_SW - - 2 - A 15 DFFE ! 0 2 1 1 |dcp:DECODE|WR_AWGX - - 8 - D 23 LCELL 0 4 0 1 |dcp:DECODE|W_TAB0 - - 2 - D 23 LCELL 0 4 0 1 |dcp:DECODE|W_TAB1 - - 1 - D 23 LCELL 0 4 0 1 |dcp:DECODE|W_TAB2 - - 3 - D 29 LCELL 0 3 0 1 |dcp:DECODE|W_TAB3 - - 3 - D 23 DFFE + ! 0 4 0 4 |dcp:DECODE|WT_CT0 - - 1 - D 19 DFFE + ! 0 5 0 5 |dcp:DECODE|WT_CT1 - - 5 - D 27 DFFE + ! 0 4 0 3 |dcp:DECODE|WT_CT2 - - 8 - D 27 DFFE + ! 0 2 0 4 |dcp:DECODE|WT_CT3 - - 1 - C 07 LCELL 0 4 0 1 |dcp:DECODE|X_ADR0 - - 4 - C 07 LCELL 0 4 0 1 |dcp:DECODE|X_ADR1 - - 1 - C 35 LCELL 0 4 0 1 |dcp:DECODE|X_ADR2 - - 8 - C 11 LCELL 0 4 0 1 |dcp:DECODE|X_ADR3 - - 2 - C 12 LCELL 0 4 0 1 |dcp:DECODE|X_ADR4 - - 5 - C 13 LCELL 0 4 0 1 |dcp:DECODE|X_ADR5 - - 8 - C 12 LCELL 0 4 0 1 |dcp:DECODE|X_ADR6 - - 2 - C 28 LCELL 0 4 0 1 |dcp:DECODE|X_ADR7 - - 5 - C 31 LCELL ! 0 5 0 1 |dcp:DECODE|X_ADR8 - - 2 - C 27 LCELL ! 0 5 0 1 |dcp:DECODE|X_ADR9 - - 3 - C 27 LCELL 0 4 0 1 |dcp:DECODE|X_ADR10 - - 6 - F 32 DFFE + ! 0 3 0 4 |dcp:DECODE|:237 - - 7 - A 01 SOFT s ! 0 1 0 16 |dcp:DECODE|~238~1 - - 7 - F 32 DFFE + ! 0 4 0 6 |dcp:DECODE|:238 - - 4 - A 28 DFFE + 0 2 0 23 |dcp:DECODE|:239 - - 6 - A 28 DFFE + ! 0 3 1 1 |dcp:DECODE|:240 - - 8 - C 21 DFFE + ! 0 4 0 9 |dcp:DECODE|:241 - - 5 - C 01 DFFE + ! 0 5 0 3 |dcp:DECODE|:242 - - 8 - A 23 DFFE + 0 2 0 4 |dcp:DECODE|:243 - - 7 - D 27 DFFE + ! 0 4 0 13 |dcp:DECODE|:245 - - 4 - D 03 DFFE + ! 0 5 0 10 |dcp:DECODE|:246 - - 4 - C 03 DFFE + ! 1 4 0 1 |dcp:DECODE|:251 - - 6 - C 11 LCELL 0 1 0 19 |dcp:DECODE|:253 - - 3 - C 11 LCELL 0 3 0 2 |dcp:DECODE|:255 - - 8 - C 35 LCELL 0 3 0 2 |dcp:DECODE|:256 - - 1 - C 19 LCELL 0 3 0 2 |dcp:DECODE|:257 - - 8 - C 07 LCELL 0 3 0 2 |dcp:DECODE|:258 - - 8 - C 27 LCELL 0 3 0 4 |dcp:DECODE|:259 - - 2 - C 11 LCELL 0 3 0 3 |dcp:DECODE|:260 - - 7 - C 27 LCELL 0 3 0 3 |dcp:DECODE|:261 - - 6 - C 31 LCELL 0 3 0 3 |dcp:DECODE|:262 - - 2 - C 31 DFFE + 0 2 0 11 |dcp:DECODE|:263 - - 8 - C 31 LCELL 0 4 0 1 |dcp:DECODE|:264 - - 4 - C 36 LCELL 0 2 0 1 |dcp:DECODE|:265 - - 1 - C 14 DFFE 0 6 0 19 |dcp:DECODE|:267 - - 4 - D 34 DFFE + 0 3 0 18 |dcp:DECODE|:268 - - 1 - D 34 DFFE + 0 3 0 18 |dcp:DECODE|:269 - - 5 - D 34 DFFE + 0 3 0 17 |dcp:DECODE|:270 - - 3 - D 20 DFFE + 0 3 0 17 |dcp:DECODE|:271 - - 1 - D 33 DFFE + 0 3 0 8 |dcp:DECODE|:272 - - 7 - D 19 DFFE + 0 3 0 15 |dcp:DECODE|:273 - - 1 - D 26 DFFE + 0 3 0 15 |dcp:DECODE|:274 - - 4 - D 26 DFFE + 0 3 0 15 |dcp:DECODE|:275 - - 8 - F 32 DFFE + 0 1 0 17 |dcp:DECODE|:452 - - 6 - D 24 DFFE + 0 1 1 7 |dcp:DECODE|:453 - - 1 - D 24 DFFE ! 0 5 0 1 |dcp:DECODE|:454 - - 2 - D 27 DFFE + 0 3 1 6 |dcp:DECODE|:457 - - 1 - D 27 DFFE + 0 2 0 1 |dcp:DECODE|:458 - - 1 - A 15 DFFE + 0 1 0 1 |dcp:DECODE|:461 - - 5 - C 23 LCELL 0 2 0 2 |dcp:DECODE|:463 - - 1 - C 21 LCELL 0 4 0 1 |dcp:DECODE|:464 - - 2 - C 35 DFFE + ! 0 1 0 1 |dcp:DECODE|:466 - - 3 - C 35 DFFE + ! 0 1 0 1 |dcp:DECODE|:467 - - 4 - C 33 LCELL 1 1 0 1 |dcp:DECODE|:470 - - 5 - C 35 LCELL 1 1 0 1 |dcp:DECODE|:472 - - 1 - D 35 DFFE + 0 3 0 2 |dcp:DECODE|:477 - - 5 - C 14 DFFE + 0 3 0 17 |dcp:DECODE|:478 - - 2 - C 14 DFFE + 0 4 0 1 |dcp:DECODE|:479 - - 5 - C 30 DFFE + 0 4 0 1 |dcp:DECODE|:480 - - 6 - C 04 DFFE ! 0 2 0 1 |dcp:DECODE|:481 - - 2 - C 34 DFFE + ! 0 2 0 1 |dcp:DECODE|:483 - - 4 - D 35 DFFE + 0 2 0 1 |dcp:DECODE|:484 - - 7 - C 34 DFFE + 0 4 0 1 |dcp:DECODE|:485 - - 2 - D 35 DFFE + 0 4 0 3 |dcp:DECODE|:486 - - 8 - C 03 LCELL 0 4 0 2 |dcp:DECODE|:488 - - 6 - C 01 LCELL 2 1 0 1 |dcp:DECODE|:490 - - 8 - D 33 SOFT s ! 0 1 0 16 |dcp:DECODE|~494~1 - - 7 - D 33 DFFE + 0 1 0 1 |dcp:DECODE|:494 - - 2 - D 34 LCELL 0 4 0 8 |dcp:DECODE|:496 - - 6 - D 21 DFFE + 0 4 0 3 |dcp:DECODE|:499 - - 8 - D 21 DFFE + 0 4 0 8 |dcp:DECODE|:500 - - 4 - C 20 LCELL 1 3 0 8 |dcp:DECODE|:507 - - 7 - C 32 DFFE + 0 1 0 1 |dcp:DECODE|:509 - - 8 - C 32 DFFE + 1 1 0 1 |dcp:DECODE|:510 - - 5 - C 07 OR2 s 0 4 0 1 |dcp:DECODE|~669~1 - - 6 - C 35 OR2 s 0 4 0 1 |dcp:DECODE|~672~1 - - 7 - C 13 OR2 s 0 4 0 1 |dcp:DECODE|~681~1 - - 4 - C 12 OR2 s 0 4 0 1 |dcp:DECODE|~684~1 - - 6 - C 28 OR2 s 1 3 0 1 |dcp:DECODE|~687~1 - - 4 - C 31 OR2 s ! 0 4 0 1 |dcp:DECODE|~690~1 - - 1 - C 27 OR2 s ! 0 4 0 1 |dcp:DECODE|~693~1 - - 6 - C 12 AND2 0 4 0 1 |dcp:DECODE|:779 - - 8 - C 13 AND2 0 4 0 1 |dcp:DECODE|:782 - - 1 - C 12 OR2 0 3 1 0 |dcp:DECODE|:818 - - 2 - C 13 OR2 0 3 1 0 |dcp:DECODE|:821 - - 1 - C 13 OR2 0 4 1 0 |dcp:DECODE|:824 - - 3 - C 28 OR2 0 4 1 0 |dcp:DECODE|:827 - - 3 - C 32 OR2 0 4 1 0 |dcp:DECODE|:830 - - 2 - C 07 OR2 0 3 1 0 |dcp:DECODE|:845 - - 3 - C 07 OR2 0 3 1 0 |dcp:DECODE|:848 - - 1 - C 10 OR2 0 4 1 0 |dcp:DECODE|:850 - - 1 - C 11 OR2 1 2 1 0 |dcp:DECODE|:853 - - 6 - C 32 OR2 0 3 1 0 |dcp:DECODE|:856 - - 2 - C 16 OR2 0 3 1 0 |dcp:DECODE|:859 - - 1 - C 30 AND2 0 2 1 0 |dcp:DECODE|:862 - - 5 - A 34 AND2 s 0 3 0 1 |dcp:DECODE|~986~1 - - 5 - A 28 AND2 0 3 0 1 |dcp:DECODE|:986 - - 2 - A 28 OR2 ! 2 0 0 2 |dcp:DECODE|:987 - - 7 - C 01 AND2 s 1 1 0 1 |dcp:DECODE|~994~1 - - 4 - F 32 OR2 0 4 0 1 |dcp:DECODE|:1004 - - 5 - F 32 OR2 0 4 0 1 |dcp:DECODE|:1012 - - 5 - C 12 OR2 s 1 2 0 1 |dcp:DECODE|~1024~1 - - 3 - C 14 AND2 ! 0 3 0 1 |dcp:DECODE|:1028 - - 6 - C 14 AND2 0 4 0 1 |dcp:DECODE|:1030 - - 7 - C 14 AND2 s 0 3 0 1 |dcp:DECODE|~1036~1 - - 7 - C 04 AND2 0 2 0 1 |dcp:DECODE|:1037 - - 7 - D 23 OR2 ! 0 2 0 1 |dcp:DECODE|:1042 - - 3 - D 27 OR2 ! 0 2 0 1 |dcp:DECODE|:1044 - - 3 - D 06 AND2 ! 0 2 0 3 |dcp:DECODE|:1046 - - 4 - D 19 OR2 ! 0 4 0 1 |dcp:DECODE|:1069 - - 7 - C 23 AND2 0 2 0 1 |dcp:DECODE|:1211 - - 2 - D 19 AND2 0 2 0 16 |dcp:DECODE|:1220 - - 3 - D 21 AND2 ! 0 4 0 3 |dcp:DECODE|:1264 - - 7 - D 12 AND2 0 2 0 3 |dcp:DECODE|:1307 - - 6 - D 14 AND2 0 2 0 5 |dcp:DECODE|:1309 - - 7 - D 13 AND2 0 2 0 2 |dcp:DECODE|:1310 - - 7 - D 14 OR2 0 3 0 1 |dcp:DECODE|:1311 - - 5 - C 32 AND2 s 0 2 0 1 |dcp:DECODE|~1539~1 - - 5 - D 35 AND2 ! 0 4 0 1 |dcp:DECODE|:1630 - - 8 - C 34 AND2 s 0 3 0 1 |dcp:DECODE|~1642~1 - - 5 - D 36 OR2 1 2 1 0 DD0 - - 7 - D 36 OR2 1 2 1 0 DD1 - - 6 - D 33 OR2 1 2 1 0 DD2 - - 3 - D 33 OR2 1 2 1 0 DD3 - - 1 - D 32 OR2 1 2 1 0 DD4 - - 2 - A 31 OR2 1 2 1 0 DD5 - - 1 - D 29 OR2 1 2 1 0 DD6 - - 2 - D 29 OR2 1 2 1 0 DD7 - - 5 - C 10 DFFE ! 2 3 0 4 dos - - 1 - C 25 OR2 0 3 0 0 D_OUT - - 3 - C 18 LCELL 0 3 0 1 glisser - - 8 - E 14 GND s 0 0 0 8 ~GND~ - - 7 - D 09 DFFE 0 5 0 3 hddr0 - - 1 - D 07 DFFE 0 5 0 3 hddr1 - - 8 - D 07 DFFE 0 5 0 3 hddr2 - - 3 - D 09 DFFE 0 5 0 3 hddr3 - - 6 - D 09 DFFE 0 5 0 3 hddr4 - - 2 - D 09 DFFE 0 5 0 3 hddr5 - - 5 - D 09 DFFE 0 5 0 3 hddr6 - - 4 - D 09 DFFE 0 5 0 3 hddr7 - - 4 - F 26 DFFE ! 0 4 0 1 HOLD0 - - 5 - F 33 DFFE ! 0 4 0 1 HOLD1 - - 6 - F 26 DFFE ! 0 4 0 1 HOLD2 - - 3 - F 26 DFFE 0 4 0 1 HOLD3 - - 1 - F 33 DFFE ! 0 4 0 1 HOLD4 - - 2 - F 33 SOFT s ! 0 1 0 1 HOLD5~1 - - 6 - F 33 DFFE ! 0 4 0 1 HOLD5 - - 4 - F 33 SOFT s ! 0 1 0 1 HOLD6~1 - - 8 - F 33 DFFE ! 0 4 0 1 HOLD6 - - 3 - F 33 DFFE 0 4 0 1 HOLD7 - - 4 - A 25 AND2 ! 0 2 1 1 INT_X - - 7 - C 25 DFFE + ! 1 0 0 2 /IORD - - 5 - C 09 DFFE + ! 1 0 0 42 /IOWR - - 1 - C 26 OR2 0 4 1 0 ISA_A0 - - 1 - C 23 OR2 0 4 1 0 ISA_A1 - - 2 - C 23 OR2 0 3 1 0 ISA_A2 - - 2 - C 25 OR2 0 4 1 0 ISA_A3 - - 4 - C 26 DFFE 0 3 0 1 ISA_PORT1 - - 3 - C 26 DFFE 0 3 0 1 ISA_PORT2 - - 3 - C 09 DFFE 0 3 0 1 ISA_PORT4 - - 4 - C 09 DFFE 0 3 0 1 ISA_PORT5 - - 6 - C 09 DFFE 0 3 0 1 ISA_PORT6 - - 7 - C 09 DFFE 0 3 0 1 ISA_PORT7 - - 8 - D 28 DFFE 0 3 0 2 kbd_cc - - 5 - D 28 DFFE 0 3 0 1 kbd_dd - - 2 - B 10 OR2 0 4 0 8 |kbd:KEYS|KA8 - - 7 - B 10 OR2 0 4 0 8 |kbd:KEYS|KA9 - - 6 - B 10 OR2 0 4 0 8 |kbd:KEYS|KA10 - - 5 - B 10 OR2 0 4 0 8 |kbd:KEYS|KA11 - - 8 - B 02 OR2 0 4 0 8 |kbd:KEYS|KA12 - - 2 - B 14 OR2 0 3 0 8 |kbd:KEYS|KA13 - - 4 - B 14 OR2 0 3 0 8 |kbd:KEYS|KA14 - - 5 - B 14 OR2 0 3 0 8 |kbd:KEYS|KA15 - - 5 - E 34 LCELL 0 4 0 2 |kbd:KEYS|KB_ALT_X - - 2 - E 20 LCELL 0 4 0 1 |kbd:KEYS|KB_CTRL_X - - 7 - A 27 DFFE ! 0 4 0 7 |kbd:KEYS|KB_CT0 - - 6 - A 27 DFFE ! 0 4 0 8 |kbd:KEYS|KB_CT1 - - 1 - A 27 DFFE ! 0 4 0 15 |kbd:KEYS|KB_CT2 - - 3 - B 12 DFFE + ! 0 3 0 1 |kbd:KEYS|kbd0 - - 4 - E 23 DFFE 0 2 0 7 |kbd:KEYS|KB_D1 - - 1 - B 12 DFFE + ! 0 3 0 1 |kbd:KEYS|kbd1 - - 2 - E 32 DFFE 0 2 0 8 |kbd:KEYS|KB_D2 - - 8 - B 12 DFFE + ! 0 3 0 1 |kbd:KEYS|kbd2 - - 7 - E 24 DFFE 0 2 0 8 |kbd:KEYS|KB_D3 - - 4 - B 12 DFFE + ! 0 3 0 1 |kbd:KEYS|kbd3 - - 8 - E 24 DFFE 0 2 0 7 |kbd:KEYS|KB_D4 - - 2 - B 12 DFFE + ! 0 3 0 1 |kbd:KEYS|kbd4 - - 5 - E 24 DFFE 0 2 0 8 |kbd:KEYS|KB_D5 - - 7 - B 12 DFFE + ! 0 3 0 1 |kbd:KEYS|kbd5 - - 1 - F 29 DFFE 0 2 0 7 |kbd:KEYS|KB_D6 - - 2 - E 25 DFFE 0 2 0 7 |kbd:KEYS|KB_D7 - - 3 - E 25 DFFE 0 2 0 7 |kbd:KEYS|KB_D8 - - 4 - E 25 DFFE 0 2 0 1 |kbd:KEYS|KB_D9 - - 5 - E 25 DFFE 0 2 0 1 |kbd:KEYS|KB_D10 - - 7 - E 22 DFFE 0 5 0 1 |kbd:KEYS|KB_EXT - - 5 - E 22 SOFT s ! 0 1 0 1 |kbd:KEYS|KB_EXT~1 - - 8 - E 09 DFFE + 0 1 0 7 |kbd:KEYS|KB_MA0 - - 4 - E 18 DFFE + 0 2 0 3 |kbd:KEYS|KB_MA1 - - 5 - E 18 DFFE + 0 3 0 6 |kbd:KEYS|KB_MA2 - - 6 - E 18 DFFE + 0 4 0 6 |kbd:KEYS|KB_MXA - - 1 - E 34 DFFE 0 5 0 11 |kbd:KEYS|KB_OFF - - 2 - E 24 AND2 0 2 0 1 |kbd:KEYS|KB_SH_X - - 2 - E 34 LCELL 0 4 0 3 |kbd:KEYS|KB_XXX - - 8 - B 03 DFFE + 0 1 0 3 |kbd:KEYS|K_CLK - - 5 - B 05 LCELL 0 3 0 1 |kbd:KEYS|KDCA0 - - 1 - B 05 LCELL 0 3 0 1 |kbd:KEYS|KDCA1 - - 6 - B 05 LCELL 0 3 0 1 |kbd:KEYS|KDCA2 - - 2 - B 05 DFFE 0 2 0 1 |kbd:KEYS|KDD3 - - 4 - B 05 DFFE 0 2 0 1 |kbd:KEYS|KDD4 - - 7 - B 05 DFFE 0 2 0 1 |kbd:KEYS|KDD5 - - 3 - B 10 DFFE ! 0 3 0 2 |kbd:KEYS|KDD6 - - 8 - B 10 DFFE ! 0 3 0 2 |kbd:KEYS|KDD7 - - 1 - B 17 DFFE 0 4 0 1 |kbd:KEYS|KDXX0 - - 7 - B 17 DFFE 0 4 0 1 |kbd:KEYS|KDXX1 - - 8 - B 17 DFFE 0 4 0 1 |kbd:KEYS|KDXX2 - - 4 - B 17 DFFE 0 4 0 1 |kbd:KEYS|KDXX3 - - 2 - B 17 DFFE 0 4 0 1 |kbd:KEYS|KDXX4 - - 3 - B 17 DFFE 0 4 0 1 |kbd:KEYS|KDXX5 - - 3 - B 13 DFFE 0 4 0 1 |kbd:KEYS|KDX0 - - 5 - B 17 DFFE 0 4 0 1 |kbd:KEYS|KDX1 - - 6 - B 17 DFFE 0 4 0 1 |kbd:KEYS|KDX2 - - 4 - B 13 DFFE 0 4 0 1 |kbd:KEYS|KDX3 - - 6 - B 13 DFFE 0 4 0 1 |kbd:KEYS|KDX4 - - 7 - B 13 DFFE 0 4 0 1 |kbd:KEYS|KDX5 - - - 1 B -- MEM_SGMT 0 10 0 8 |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_0 - - - 14 B -- MEM_SGMT 0 10 0 8 |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_1 - - - 5 B -- MEM_SGMT 0 10 0 8 |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_2 - - - 13 B -- MEM_SGMT 0 10 0 3 |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_3 - - - 2 B -- MEM_SGMT 0 10 0 3 |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_4 - - - 10 B -- MEM_SGMT 0 10 0 3 |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_5 - - - 4 B -- MEM_SGMT 0 9 0 1 |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_6 - - - 12 B -- MEM_SGMT 0 9 0 1 |kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_7 - - 4 - B 03 DFFE 0 3 0 15 |kbd:KEYS|RXA0 - - 7 - B 03 DFFE 0 3 0 10 |kbd:KEYS|RXA1 - - 3 - B 03 AND2 ! 0 4 0 8 |kbd:KEYS|WR_KBD - - 4 - E 34 DFFE ! 0 6 0 1 |kbd:KEYS|:91 - - 1 - E 20 DFFE 0 4 0 2 |kbd:KEYS|:92 - - 3 - E 34 DFFE 0 4 0 2 |kbd:KEYS|:93 - - 3 - E 24 DFFE 0 3 0 1 |kbd:KEYS|:94 - - 4 - A 27 DFFE + ! 0 4 0 1 |kbd:KEYS|:177 - - 8 - A 27 DFFE + 0 1 0 3 |kbd:KEYS|:178 - - 1 - E 25 DFFE + 0 1 0 10 |kbd:KEYS|:179 - - 5 - E 20 DFFE + 0 3 0 1 |kbd:KEYS|:180 - - 4 - E 20 DFFE + 0 3 0 2 |kbd:KEYS|:181 - - 4 - E 24 LCELL 0 4 0 1 |kbd:KEYS|:184 - - 1 - E 24 CASCADE 0 4 0 1 |kbd:KEYS|:185 - - 6 - E 20 DFFE ! 0 5 0 1 |kbd:KEYS|:187 - - 7 - E 20 LCELL 0 4 0 1 |kbd:KEYS|:188 - - 5 - B 03 DFFE + 0 4 0 2 |kbd:KEYS|:191 - - 4 - B 10 LCELL 0 2 0 8 |kbd:KEYS|:192 - - 1 - B 10 DFFE + 0 3 0 8 |kbd:KEYS|:193 - - 3 - B 05 DFFE + 0 1 0 6 |kbd:KEYS|:196 - - 4 - B 01 DFFE + 0 3 0 1 |kbd:KEYS|:197 - - 5 - B 12 DFFE 0 2 0 6 |kbd:KEYS|:198 - - 6 - E 34 AND2 s 0 4 0 1 |kbd:KEYS|~267~1 - - 5 - E 32 AND2 s 0 3 0 1 |kbd:KEYS|~267~2 - - 6 - E 24 AND2 s 0 3 0 1 |kbd:KEYS|~278~1 - - 8 - E 22 AND2 s 0 3 0 1 |kbd:KEYS|~278~2 - - 7 - E 34 AND2 s 0 3 0 1 |kbd:KEYS|~320~1 - - 8 - E 34 AND2 s 0 3 0 1 |kbd:KEYS|~320~2 - - 7 - E 18 OR2 s 2 2 0 1 |kbd:KEYS|~540~1 - - 8 - E 18 OR2 s 2 2 0 1 |kbd:KEYS|~540~2 - - 2 - E 18 OR2 s ! 2 2 0 1 |kbd:KEYS|~540~3 - - 3 - E 18 OR2 s ! 2 3 0 1 |kbd:KEYS|~540~4 - - 3 - E 20 AND2 ! 0 3 0 1 |kbd:KEYS|:605 - - 4 - B 22 LCELL 2 2 0 1 KEMPS0 - - 2 - B 25 LCELL 2 2 0 1 KEMPS1 - - 2 - B 32 LCELL 2 2 0 1 KEMPS2 - - 4 - B 24 LCELL 2 2 0 1 KEMPS3 - - 1 - B 32 LCELL 2 2 0 1 KEMPS4 - - 7 - B 24 LCELL 2 2 0 1 KEMPS5 - - 3 - B 24 LCELL 2 2 0 1 KEMPS6 - - 8 - B 25 LCELL 2 2 0 1 KEMPS7 - - 2 - A 01 DFFE + 2 1 0 4 KEY_IO - - 5 - B 22 LCELL 0 3 0 1 KEY/KEMS0 - - 5 - B 25 LCELL 0 3 0 1 KEY/KEMS1 - - 4 - B 32 LCELL 0 3 0 1 KEY/KEMS2 - - 1 - B 24 LCELL 0 3 0 1 KEY/KEMS3 - - 4 - B 36 LCELL 0 3 0 1 KEY/KEMS4 - - 8 - A 26 LCELL 0 3 0 1 KEY/KEMS5 - - 5 - D 29 LCELL 0 3 0 1 KEY/KEMS6 - - 8 - A 31 LCELL 0 3 0 1 KEY/KEMS7 - - - 10 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_1 - - - 8 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_2 - - - 9 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_3 - - - 1 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_4 - - - 11 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_5 - - - 6 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_6 - - - 15 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_7 - - - 2 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_8 - - - 14 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_9 - - - 3 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_10 - - - 12 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_11 - - - 5 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_12 - - - 13 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_13 - - - 7 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_14 - - - 4 A -- MEM_SGMT 0 18 0 1 |lpm_ram_dp:CBL|altdpram:sram|segment0_15 - - 6 - D 11 DFFE 0 5 0 1 MDP0 - - 5 - D 11 DFFE 0 5 0 1 MDP1 - - 7 - D 15 DFFE 0 5 0 1 MDP2 - - 6 - D 15 DFFE 0 5 0 1 MDP3 - - 3 - D 04 DFFE 0 5 0 1 MDP4 - - 1 - D 11 DFFE 0 5 0 1 MDP5 - - 2 - D 14 DFFE 0 5 0 1 MDP6 - - 7 - D 04 DFFE 0 5 0 1 MDP7 - - 1 - D 28 DFFE 0 3 0 3 mouse_d - - 1 - A 07 DFFE 0 5 0 4 |MOUSE:MS|CT0 - - 2 - A 07 DFFE 0 3 0 4 |MOUSE:MS|CT1 - - 3 - A 07 DFFE 0 5 0 3 |MOUSE:MS|CT2 - - 4 - A 07 DFFE 0 5 0 3 |MOUSE:MS|CT3 - - 1 - A 28 OR2 0 2 0 4 |MOUSE:MS|MOUSE_IMP - - 3 - B 22 DFFE 0 3 0 1 |MOUSE:MS|RGK0 - - 4 - B 26 DFFE 0 3 0 1 |MOUSE:MS|RGK1 - - 8 - B 26 DFFE 0 3 0 1 |MOUSE:MS|RGK2 - - 3 - B 26 DFFE 0 3 0 1 |MOUSE:MS|RGK3 - - 3 - B 25 DFFE 0 3 0 1 |MOUSE:MS|RGK4 - - 6 - B 22 DFFE 0 3 0 1 |MOUSE:MS|RGK5 - - 1 - B 14 SOFT s ! 0 1 0 2 |MOUSE:MS|RG0~1 - - 2 - B 23 DFFE 0 3 0 14 |MOUSE:MS|RG0 - - 1 - B 23 DFFE 0 4 0 6 |MOUSE:MS|RG1 - - 6 - B 23 DFFE 0 4 0 4 |MOUSE:MS|RG2 - - 3 - B 23 DFFE 0 4 0 4 |MOUSE:MS|RG3 - - 4 - B 23 DFFE 0 4 0 4 |MOUSE:MS|RG4 - - 7 - B 23 DFFE 0 4 0 4 |MOUSE:MS|RG5 - - 5 - B 23 DFFE 0 4 0 4 |MOUSE:MS|RG6 - - 2 - B 28 DFFE 0 4 0 5 |MOUSE:MS|RG7 - - 4 - B 28 DFFE 0 4 0 1 |MOUSE:MS|RG8 - - 6 - B 28 DFFE 0 4 0 1 |MOUSE:MS|RG9 - - 3 - B 14 DFFE 0 3 0 3 |MOUSE:MS|STATE0 - - 6 - B 14 DFFE 0 3 0 2 |MOUSE:MS|STATE1 - - 8 - B 22 DFFE 0 3 0 2 |MOUSE:MS|SUM_X0 - - 4 - B 25 DFFE 0 3 0 2 |MOUSE:MS|SUM_X1 - - 7 - B 32 DFFE 0 3 0 2 |MOUSE:MS|SUM_X2 - - 6 - B 24 DFFE 0 3 0 2 |MOUSE:MS|SUM_X3 - - 6 - B 32 DFFE 0 3 0 2 |MOUSE:MS|SUM_X4 - - 5 - B 24 DFFE 0 3 0 2 |MOUSE:MS|SUM_X5 - - 2 - B 24 DFFE 0 3 0 2 |MOUSE:MS|SUM_X6 - - 8 - B 35 DFFE 0 3 0 1 |MOUSE:MS|SUM_X7 - - 1 - B 26 DFFE 0 3 0 2 |MOUSE:MS|SUM_Y0 - - 1 - B 28 DFFE 0 3 0 2 |MOUSE:MS|SUM_Y1 - - 3 - B 32 DFFE 0 3 0 2 |MOUSE:MS|SUM_Y2 - - 1 - B 22 DFFE 0 3 0 2 |MOUSE:MS|SUM_Y3 - - 8 - B 32 DFFE 0 3 0 2 |MOUSE:MS|SUM_Y4 - - 3 - B 28 DFFE 0 3 0 2 |MOUSE:MS|SUM_Y5 - - 5 - B 28 DFFE 0 3 0 2 |MOUSE:MS|SUM_Y6 - - 8 - B 31 DFFE 0 3 0 1 |MOUSE:MS|SUM_Y7 - - 7 - A 28 DFFE 0 2 0 1 |MOUSE:MS|:111 - - 8 - B 14 LCELL 0 4 0 8 |MOUSE:MS|:112 - - 7 - B 14 LCELL 0 4 0 8 |MOUSE:MS|:113 - - 5 - A 07 AND2 ! 0 4 0 1 |MOUSE:MS|:144 - - 8 - B 28 OR2 0 2 0 10 |MOUSE:MS|:147 - - 2 - B 11 AND2 0 2 0 6 |MOUSE:MS|:171 - - 2 - B 35 OR2 0 2 0 1 |MOUSE:MS|:185 - - 3 - B 35 OR2 0 2 0 1 |MOUSE:MS|:195 - - 4 - B 35 OR2 0 2 0 1 |MOUSE:MS|:205 - - 5 - B 35 OR2 0 2 0 1 |MOUSE:MS|:216 - - 6 - B 35 OR2 0 2 0 1 |MOUSE:MS|:226 - - 7 - B 35 OR2 0 2 0 1 |MOUSE:MS|:236 - - 2 - B 31 OR2 0 2 0 1 |MOUSE:MS|:282 - - 3 - B 31 OR2 0 2 0 1 |MOUSE:MS|:292 - - 4 - B 31 OR2 0 2 0 1 |MOUSE:MS|:302 - - 5 - B 31 OR2 0 2 0 1 |MOUSE:MS|:313 - - 6 - B 31 OR2 0 2 0 1 |MOUSE:MS|:323 - - 7 - B 31 OR2 0 2 0 1 |MOUSE:MS|:333 - - 3 - D 26 LCELL 0 4 0 1 PDD0 - - 8 - D 36 LCELL 0 4 0 1 PDD1 - - 5 - D 23 LCELL 0 4 0 1 PDD2 - - 5 - D 32 LCELL 0 4 0 1 PDD3 - - 7 - D 32 LCELL 0 4 0 1 PDD4 - - 1 - A 26 LCELL 0 4 0 1 PDD5 - - 7 - D 29 LCELL 0 4 0 1 PDD6 - - 1 - A 31 LCELL 0 4 0 1 PDD7 - - 3 - C 25 LCELL 2 1 0 7 PRE_CASH - - 8 - C 09 LCELL 2 2 0 3 PRE_ISA - - 4 - C 25 LCELL 2 2 0 7 PRE_ROM - - 2 - A 35 LCELL 0 1 1 0 RASX_0 - - 2 - A 34 LCELL 0 1 1 0 RASX_1 - - 5 - D 31 SOFT s ! 1 0 0 1 /rf~1 - - 7 - F 28 DFFE 0 4 0 1 RGMOD0 - - 8 - C 26 DFFE 0 4 0 1 ROM_RG0 - - 7 - C 26 DFFE 0 4 0 1 ROM_RG1 - - 5 - C 26 DFFE 0 4 0 1 ROM_RG2 - - 6 - F 27 DFFE 0 4 0 1 ROM_RG3 - - 5 - F 27 DFFE 0 4 0 3 ROM_RG4 - - 5 - F 36 DFFE 0 4 0 4 SINC_HOLD0 - - 6 - F 36 DFFE 0 5 0 4 SINC_HOLD1 - - 7 - F 36 DFFE 0 5 0 3 SINC_HOLD2 - - 8 - F 36 DFFE 0 5 0 2 SINC_HOLD3 - - 1 - F 22 DFFE 0 4 0 1 SINC_HOLD4 - - 8 - F 22 DFFE 0 5 0 3 SINC_HOLD5 - - 2 - F 22 DFFE 0 4 0 1 SINC_HOLD6 - - 3 - F 22 DFFE 0 4 0 1 SINC_HOLD7 - - 5 - F 22 DFFE 0 4 0 1 SINC_HOLD8 - - 5 - D 21 DFFE 0 4 0 4 SINC_1 - - 1 - F 36 DFFE + 0 4 0 6 SINC_1M - - 7 - F 33 SOFT s ! 0 1 0 4 SINC_2~1 - - 4 - D 21 DFFE 0 4 0 2 SINC_2 - - 4 - F 22 DFFE + 0 2 0 7 SINC_2M - - 7 - C 28 DFFE ! 0 3 0 2 SOFT_RES0 - - 8 - C 28 DFFE ! 0 3 0 2 SOFT_RES1 - - 6 - C 26 DFFE 1 3 0 2 /SYS - - 3 - C 29 DFFE + 3 1 0 2 SYS_ENA2 - - 1 - F 27 DFFE 0 5 0 1 SYS_PG - - 4 - D 28 DFFE 0 3 0 1 TAPE_IN - - 4 - E 29 LCELL 0 1 1 0 TAPE_OUT - - 8 - E 29 DFFE ! 0 5 0 1 TEST_SWITCH - - 7 - D 28 LCELL 0 1 0 6 T_RDXA - - 7 - C 18 LCELL 0 4 0 2 VIDEO_PG - - 3 - B 34 DFFE 0 5 0 5 |video2:SVIDEO|BORD - - 3 - B 29 DFFE + 0 4 0 1 |video2:SVIDEO|BRVA0 - - 5 - B 21 DFFE + 0 4 0 1 |video2:SVIDEO|BRVA1 - - 4 - B 33 DFFE + 0 4 0 1 |video2:SVIDEO|BRVA2 - - 6 - B 29 DFFE + 0 4 0 1 |video2:SVIDEO|BRVA3 - - 2 - B 29 DFFE + 0 2 0 1 |video2:SVIDEO|BRVA4 - - 8 - B 21 DFFE + 0 2 0 1 |video2:SVIDEO|BRVA5 - - 3 - B 33 DFFE + 0 2 0 1 |video2:SVIDEO|BRVA6 - - 1 - B 29 DFFE + 0 2 0 1 |video2:SVIDEO|BRVA7 - - 4 - B 29 DFFE + 0 5 0 1 |video2:SVIDEO|DCOL0 - - 6 - B 21 DFFE + 0 5 0 1 |video2:SVIDEO|DCOL1 - - 5 - B 33 DFFE + 0 5 0 1 |video2:SVIDEO|DCOL2 - - 5 - B 29 DFFE + 0 5 0 1 |video2:SVIDEO|DCOL3 - - 7 - B 29 DFFE + 0 5 0 2 |video2:SVIDEO|DCOL4 - - 7 - B 21 DFFE + 0 5 0 2 |video2:SVIDEO|DCOL5 - - 6 - B 33 DFFE + 0 4 0 2 |video2:SVIDEO|DCOL6 - - 8 - B 29 DFFE + 0 4 0 2 |video2:SVIDEO|DCOL7 - - 6 - F 07 DFFE + 0 2 0 4 |video2:SVIDEO|DOUBLE - - 3 - B 20 OR2 s ! 0 4 0 1 |video2:SVIDEO|D_PICX_0~1 - - 4 - B 20 OR2 ! 0 5 0 2 |video2:SVIDEO|D_PICX_0 - - 1 - F 34 OR2 s ! 0 4 0 1 |video2:SVIDEO|D_PICX_1~1 - - 2 - F 34 OR2 ! 0 5 0 2 |video2:SVIDEO|D_PICX_1 - - 7 - B 07 OR2 s ! 0 4 0 1 |video2:SVIDEO|D_PICX_2~1 - - 8 - B 07 OR2 ! 0 5 0 2 |video2:SVIDEO|D_PICX_2 - - 4 - B 08 OR2 s ! 0 4 0 1 |video2:SVIDEO|D_PICX_3~1 - - 5 - B 08 OR2 ! 0 5 0 2 |video2:SVIDEO|D_PICX_3 - - 4 - B 16 OR2 s ! 0 4 0 1 |video2:SVIDEO|D_PICX_4~1 - - 5 - B 16 OR2 ! 0 5 0 2 |video2:SVIDEO|D_PICX_4 - - 2 - B 07 OR2 s ! 0 4 0 1 |video2:SVIDEO|D_PICX_5~1 - - 3 - B 07 OR2 ! 0 5 0 2 |video2:SVIDEO|D_PICX_5 - - 4 - B 04 OR2 s ! 0 4 0 1 |video2:SVIDEO|D_PICX_6~1 - - 5 - B 04 OR2 ! 0 5 0 2 |video2:SVIDEO|D_PICX_6 - - 3 - B 15 OR2 s ! 0 4 0 1 |video2:SVIDEO|D_PICX_7~1 - - 4 - B 15 OR2 ! 0 5 0 2 |video2:SVIDEO|D_PICX_7 - - 1 - B 20 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC0_0 - - 3 - F 11 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC0_1 - - 8 - F 08 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC0_2 - - 6 - E 14 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC0_3 - - 6 - D 12 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC0_4 - - 8 - D 12 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC0_5 - - 6 - E 06 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC0_6 - - 7 - F 08 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC0_7 - - 5 - B 27 DFFE + 0 3 0 1 |video2:SVIDEO|D_PIC00 - - 7 - B 20 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC1_0 - - 7 - F 34 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC1_1 - - 5 - B 07 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC1_2 - - 7 - B 08 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC1_3 - - 7 - B 16 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC1_4 - - 6 - B 07 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC1_5 - - 8 - B 04 DFFE + 0 1 0 1 |video2:SVIDEO|D_PIC1_6 - - 6 - B 15 DFFE + 0 1 0 1 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:1336 - - 8 - D 09 LCELL 2 1 0 8 :1341 - - 1 - D 09 DFFE 1 1 0 8 :1342 - - 5 - A 26 LCELL 0 2 0 1 :1343 - - 3 - A 31 LCELL 0 4 0 1 :1344 - - 5 - C 25 LCELL 0 4 0 1 :1345 - - 2 - B 03 DFFE + 0 3 0 1 :1404 - - 3 - C 30 DFFE + 0 4 0 1 :1406 - - 3 - C 33 LCELL 2 2 0 1 :1408 - - 6 - C 13 DFFE 0 3 0 2 :1409 - - 3 - C 13 DFFE + 0 2 0 1 :1410 - - 1 - C 09 LCELL 2 1 0 1 :1411 - - 4 - C 13 LCELL 0 4 0 1 :1412 - - 3 - F 28 DFFE + 0 4 0 1 :1415 - - 1 - C 29 DFFE + 3 1 0 1 :1417 - - 2 - C 09 LCELL 0 4 0 1 :1419 - - 8 - B 18 DFFE + 0 4 0 1 :1423 - - 1 - C 33 LCELL 1 1 0 1 :1425 - - 2 - C 33 LCELL 1 1 0 1 :1427 - - 4 - C 23 LCELL 1 1 0 1 :1429 - - 5 - F 23 DFFE + 0 4 0 1 :1431 - - 5 - C 29 DFFE + 3 1 0 1 :1432 - - 2 - C 01 LCELL 0 1 0 1 :1433 - - 4 - C 01 DFFE + 0 1 0 1 :1434 - - 7 - A 22 DFFE ! 0 2 0 1 :1435 - - 6 - A 22 DFFE 0 2 0 1 :1436 - - 8 - A 22 DFFE 0 2 0 1 :1437 - - 6 - D 28 SOFT s ! 0 1 0 4 ~1442~1 - - 3 - F 27 DFFE + 0 1 0 1 :1458 - - 4 - F 19 DFFE + 0 1 0 1 :1460 - - 4 - F 31 DFFE + 0 4 0 8 :1464 - - 1 - C 18 DFFE + ! 0 3 1 0 :1475 - - 1 - C 28 LCELL 0 1 0 0 :1478 - - 6 - F 28 DFFE + 0 4 0 1 :1480 - - 2 - C 18 DFFE + ! 0 4 0 2 :1484 - - 7 - C 31 LCELL 1 3 0 1 :1485 - - 2 - F 31 DFFE + 0 4 0 3 :1486 - - 6 - A 01 DFFE 0 2 1 0 :1487 - - 8 - A 03 DFFE 0 2 0 1 :1488 - - 1 - E 03 DFFE + 0 1 1 0 :1489 - - 1 - A 03 DFFE + 0 1 1 0 :1490 - - 1 - F 23 DFFE + 0 4 0 8 :1494 - - 1 - C 31 LCELL 0 1 0 13 :1495 - - 4 - C 08 DFFE + 0 4 0 3 :1496 - - 3 - C 08 DFFE + 0 5 0 1 :1497 - - 5 - C 18 DFFE + ! 0 3 0 1 :1498 - - 6 - A 05 SOFT s ! 0 1 0 7 ~1499~1 - - 5 - C 08 DFFE ! 0 3 0 2 :1499 - - 8 - A 25 LCELL 0 3 0 15 :1500 - - 6 - A 14 DFFE + 0 4 0 15 :1501 - - 2 - F 24 DFFE + 1 2 0 1 :1502 - - 1 - F 31 DFFE + 0 4 0 1 :1503 - - 5 - F 03 DFFE + 1 2 0 5 :1504 - - 4 - F 23 DFFE + 0 4 0 1 :1505 - - 4 - A 36 DFFE + 0 3 0 16 :1506 - - 5 - A 30 DFFE + 0 2 0 42 :1508 - - 4 - D 11 OR2 0 4 0 1 :1561 - - 3 - D 11 OR2 0 4 0 1 :1563 - - 3 - D 15 OR2 0 4 0 1 :1565 - - 8 - D 15 OR2 0 4 0 1 :1567 - - 1 - D 04 OR2 0 4 0 1 :1569 - - 2 - D 15 OR2 0 4 0 1 :1571 - - 1 - D 14 OR2 0 4 0 1 :1573 - - 2 - D 04 OR2 0 4 0 1 :1575 - - 7 - D 11 AND2 0 4 0 1 :1579 - - 8 - D 11 AND2 0 4 0 1 :1582 - - 5 - D 15 AND2 0 4 0 1 :1585 - - 4 - D 15 AND2 0 4 0 1 :1588 - - 6 - D 04 AND2 0 4 0 1 :1591 - - 2 - D 11 AND2 0 4 0 1 :1594 - - 4 - D 14 AND2 0 4 0 1 :1597 - - 8 - D 04 AND2 0 4 0 1 :1600 - - 8 - D 14 AND2 0 2 0 8 :1619 - - 5 - D 26 OR2 s 0 4 0 1 ~1789~1 - - 2 - D 36 OR2 s 0 4 0 1 ~1791~1 - - 4 - D 23 OR2 s 0 4 0 1 ~1793~1 - - 2 - D 32 OR2 s 0 4 0 1 ~1795~1 - - 3 - D 32 OR2 s 0 4 0 1 ~1797~1 - - 4 - A 26 OR2 s 0 4 0 1 ~1799~1 - - 4 - D 29 OR2 s 0 4 0 1 ~1801~1 - - 6 - A 31 OR2 s 0 4 0 1 ~1803~1 - - 6 - C 30 AND2 0 2 0 6 :1884 - - 2 - C 26 OR2 0 4 1 0 :1967 - - 5 - F 26 OR2 0 2 0 1 :1973 - - 4 - F 09 OR2 1 2 0 1 :2013 - - 6 - C 25 AND2 ! 2 1 0 1 :2015 - - 8 - C 29 OR2 0 3 0 5 :2020 - - 4 - A 31 OR2 s 0 3 0 1 ~2028~1 - - 5 - A 31 OR2 1 3 1 0 :2028 - - 2 - F 36 OR2 0 2 0 1 :2043 - - 3 - F 36 OR2 0 3 0 1 :2047 - - 4 - F 36 OR2 0 4 0 1 :2051 - - 7 - F 22 OR2 0 2 0 1 :2082 - - 8 - C 10 AND2 s 4 0 0 1 ~2130~1 - - 7 - C 10 AND2 2 2 0 1 :2130 - - 1 - A 35 AND2 0 2 0 16 :2139 - - 3 - E 30 OR2 0 2 0 1 :2356 - - 4 - E 30 OR2 0 3 0 1 :2361 - - 5 - E 30 OR2 0 4 0 1 :2366 - - 6 - A 34 AND2 ! 0 2 0 1 :2398 - - 5 - A 19 AND2 s 0 1 0 1 ~2405~1 - - 6 - A 19 AND2 s 0 0 0 1 ~2409~2 - - 8 - A 19 AND2 s 0 1 0 1 ~2413~1 - - 1 - A 21 AND2 s 0 1 0 1 ~2417~1 - - 2 - A 21 AND2 s 0 0 0 1 ~2421~2 - - 1 - A 19 OR2 0 4 0 1 :2440 - - 7 - A 21 OR2 0 4 0 1 :2449 - - 8 - A 28 AND2 ! 0 2 0 5 :2456 - - 3 - A 28 OR2 s 0 2 0 1 ~2487~1 - - 7 - A 24 OR2 0 4 0 1 :2493 - - 7 - A 25 OR2 s ! 0 4 0 1 ~2494~1 - - 2 - A 24 OR2 0 2 0 1 :2496 - - 2 - A 19 OR2 s ! 0 3 0 1 ~2497~1 - - 4 - A 33 OR2 s ! 0 4 0 1 ~2500~1 - - 6 - A 21 OR2 s ! 0 4 0 1 ~2503~1 - - 5 - A 24 OR2 0 2 0 1 :2505 - - 5 - A 21 OR2 s ! 0 3 0 1 ~2506~1 - - 4 - A 21 OR2 s 0 3 0 1 ~2509~1 - - 1 - C 08 OR2 ! 0 2 0 3 :2514 - - 2 - A 26 AND2 s 0 2 0 1 ~2536~1 - - 6 - A 33 AND2 0 3 0 7 :2539 - - 2 - A 32 OR2 0 1 0 1 :2548 - - 3 - A 32 OR2 0 1 0 1 :2552 - - 4 - A 32 OR2 0 1 0 1 :2556 - - 5 - A 32 OR2 0 1 0 1 :2560 - - 6 - A 32 OR2 0 1 0 1 :2564 - - 3 - A 14 OR2 0 4 0 15 :2580 - - 1 - A 14 OR2 0 2 0 1 :2581 - - 3 - A 29 OR2 1 2 0 15 :2606 - - 3 - A 27 OR2 1 2 0 15 :2607 - - 3 - A 26 OR2 1 2 0 15 :2608 - - 2 - A 27 OR2 1 2 0 15 :2609 - - 5 - A 27 OR2 1 2 0 15 :2610 - - 3 - A 22 OR2 1 2 0 15 :2611 - - 7 - A 26 OR2 1 2 0 15 :2612 - - 1 - A 22 OR2 1 2 0 15 :2613 - - 2 - B 22 OR2 s 2 2 0 1 ~2864~1 - - 1 - B 25 OR2 s 2 2 0 1 ~2868~1 - - 5 - F 34 AND2 s 0 3 0 1 ~2907~1 - - 6 - F 23 AND2 s 0 3 0 1 ~2907~2 - - 6 - F 34 AND2 s 0 3 0 1 ~2921~1 - - 3 - F 31 AND2 s 0 3 0 1 ~2921~2 - - 6 - A 10 AND2 0 2 0 1 :2931 - - 7 - C 08 AND2 s 0 2 0 1 ~2945~1 - - 8 - C 08 AND2 s 0 4 0 1 ~2945~2 - - 2 - C 30 AND2 s 0 3 0 1 ~2955~1 - - 2 - C 32 AND2 s 0 3 0 1 ~2955~2 - - 1 - E 30 AND2 s 0 3 0 1 ~2960~1 - - 2 - E 30 AND2 ! 0 3 0 6 :2960 - - 2 - F 23 AND2 s 0 3 0 1 ~2971~1 - - 3 - F 23 AND2 s 0 3 0 1 ~2971~2 - - 5 - A 22 OR2 2 1 0 1 :2974 - - 7 - F 31 AND2 s 0 3 0 1 ~2995~1 - - 8 - F 31 AND2 s 0 3 0 1 ~2995~2 - - 1 - F 28 AND2 s 0 4 0 1 ~3026~1 - - 4 - C 10 AND2 ! 2 0 0 1 :3056 - - 6 - F 31 AND2 s 0 3 0 1 ~3069~1 - - 5 - F 31 AND2 s 0 3 0 1 ~3069~2 - - 6 - F 22 OR2 s 0 3 0 1 ~3081~1 - - 1 - A 29 OR2 0 2 1 0 :3093 - - 1 - E 14 OR2 ! 0 3 1 0 :3101 - - 4 - A 22 OR2 2 1 0 1 :3104 - - 2 - A 22 AND2 0 2 0 1 :3105 - - 4 - C 29 AND2 s 3 0 0 1 ~3117~1 - - 6 - C 29 AND2 s 2 1 0 1 ~3117~2 - - 8 - F 23 AND2 s 0 3 0 1 ~3130~1 - - 7 - F 23 AND2 s 0 3 0 1 ~3130~2 - - 7 - C 29 AND2 s 4 0 0 1 ~3192~1 - - 5 - F 28 AND2 s 0 3 0 1 ~3204~1 - - 4 - F 28 AND2 s 0 3 0 1 ~3204~2 - - 4 - C 27 AND2 0 2 0 1 :3207 - - 2 - F 09 OR2 2 0 0 2 :3210 - - 2 - C 29 AND2 s 4 0 0 1 ~3248~1 - - 2 - F 32 AND2 0 2 0 7 :3252 - - 5 - D 19 OR2 2 0 0 1 :3254 - - 1 - C 01 OR2 2 2 0 0 :3261 - - 8 - F 28 AND2 s 0 4 0 1 ~3321~1 - - 2 - C 19 AND2 0 4 0 1 |acceler:ACC|:604 - - 3 - C 19 AND2 0 4 0 1 |acceler:ACC|:608 - - 4 - C 19 AND2 0 4 0 1 |acceler:ACC|:612 - - 5 - C 19 AND2 0 4 0 1 |acceler:ACC|:616 - - 6 - C 19 AND2 0 4 0 1 |acceler:ACC|:620 - - 7 - C 19 AND2 0 4 0 1 |acceler:ACC|:624 - - 4 - E 11 OR2 0 2 0 1 |acceler:ACC|:678 - - 5 - E 11 OR2 0 4 0 1 |acceler:ACC|:683 - - 6 - E 11 OR2 0 4 0 1 |acceler:ACC|:688 - - 7 - E 11 OR2 0 4 0 1 |acceler:ACC|:694 - - 8 - E 11 OR2 0 4 0 1 |acceler:ACC|:699 - - 1 - E 13 OR2 0 4 0 1 |acceler:ACC|:704 - - 2 - E 13 OR2 0 2 0 1 |acceler:ACC|:708 - - 3 - E 13 OR2 0 3 0 1 |acceler:ACC|:734 - - 1 - F 04 OR2 ! 0 4 0 1 |acceler:ACC|:735 - - 3 - F 04 AND2 s 0 1 0 1 |acceler:ACC|~751~2 - - 2 - F 04 OR2 0 3 0 1 |acceler:ACC|:751 - - 5 - F 04 AND2 s 0 1 0 1 |acceler:ACC|~761~2 - - 4 - F 04 OR2 0 3 0 1 |acceler:ACC|:761 - - 7 - F 04 AND2 s 0 1 0 1 |acceler:ACC|~771~2 - - 6 - F 04 OR2 0 3 0 1 |acceler:ACC|:771 - - 1 - F 06 AND2 s 0 1 0 1 |acceler:ACC|~782~2 - - 8 - F 04 OR2 0 3 0 1 |acceler:ACC|:782 - - 3 - F 06 AND2 s 0 1 0 1 |acceler:ACC|~792~2 - - 2 - F 06 OR2 0 3 0 1 |acceler:ACC|:792 - - 5 - F 06 AND2 s 0 1 0 1 |acceler:ACC|~802~2 - - 4 - F 06 OR2 0 3 0 1 |acceler:ACC|:802 - - 6 - F 06 OR2 0 3 0 1 |acceler:ACC|:813 - - 7 - F 06 OR2 0 3 0 1 |acceler:ACC|:823 - - 8 - F 06 OR2 0 3 0 1 |acceler:ACC|:833 - - 1 - F 08 AND2 1 3 0 1 |acceler:ACC|:838 - - 2 - F 08 AND2 1 3 0 1 |acceler:ACC|:842 - - 3 - F 08 AND2 1 3 0 1 |acceler:ACC|:846 - - 4 - F 08 AND2 1 3 0 1 |acceler:ACC|:850 - - 5 - F 08 AND2 0 3 0 1 |acceler:ACC|:854 - - 1 - C 22 AND2 1 3 0 1 |acceler:ACC|:1376 - - 2 - C 22 AND2 1 3 0 1 |acceler:ACC|:1380 - - 3 - C 22 AND2 1 3 0 1 |acceler:ACC|:1384 - - 4 - C 22 AND2 1 3 0 1 |acceler:ACC|:1388 - - 5 - C 22 AND2 1 3 0 1 |acceler:ACC|:1392 - - 6 - C 22 AND2 1 3 0 1 |acceler:ACC|:1396 - - 7 - C 22 AND2 1 3 0 1 |acceler:ACC|:1400 - - 8 - C 22 AND2 1 3 0 1 |acceler:ACC|:1404 - - 1 - C 24 AND2 1 3 0 1 |acceler:ACC|:1408 - - 2 - C 24 AND2 1 3 0 1 |acceler:ACC|:1412 - - 3 - C 24 AND2 1 3 0 1 |acceler:ACC|:1416 - - 4 - C 24 AND2 1 3 0 1 |acceler:ACC|:1420 - - 5 - C 24 AND2 1 3 0 1 |acceler:ACC|:1424 - - 6 - C 24 AND2 1 3 0 1 |acceler:ACC|:1428 - - 7 - C 24 OR2 0 3 0 1 |acceler:ACC|:1430 - - 3 - A 02 CARRY 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_0 - - 4 - A 02 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_1 - - 5 - A 02 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_2 - - 6 - A 02 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_3 - - 7 - A 02 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_4 - - 8 - A 02 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_5 - - 1 - A 04 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_6 - - 2 - A 04 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_7 - - 3 - A 04 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_8 - - 4 - A 04 CARRY 0 2 0 1 |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_9 - - 3 - A 06 CARRY 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_0 - - 4 - A 06 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_1 - - 5 - A 06 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_2 - - 6 - A 06 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_3 - - 7 - A 06 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_4 - - 8 - A 06 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_5 - - 1 - A 08 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_6 - - 2 - A 08 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_7 - - 3 - A 08 CARRY 0 3 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_8 - - 4 - A 08 CARRY 0 2 0 1 |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_9 - - 1 - E 26 AND2 ! 0 2 0 1 |ay:AY3|:693 - - 2 - E 26 AND2 ! 0 3 0 1 |ay:AY3|:698 - - 3 - E 26 AND2 ! 0 3 0 1 |ay:AY3|:703 - - 4 - E 26 AND2 ! 0 3 0 1 |ay:AY3|:709 - - 5 - E 26 AND2 ! 0 3 0 1 |ay:AY3|:714 - - 2 - B 02 AND2 0 2 0 1 |ay:AY3|:787 - - 3 - B 02 AND2 0 2 0 1 |ay:AY3|:791 - - 4 - B 02 AND2 0 2 0 1 |ay:AY3|:795 - - 5 - B 02 AND2 0 2 0 1 |ay:AY3|:799 - - 6 - B 02 OR2 0 4 0 1 |ay:AY3|:801 - - 4 - D 27 OR2 0 2 0 1 |dcp:DECODE|:1054 - - 5 - D 27 OR2 0 4 0 1 |dcp:DECODE|:1059 - - 6 - D 27 OR2 ! 0 3 0 1 |dcp:DECODE|:1075 - - 7 - D 27 OR2 ! 0 4 0 1 |dcp:DECODE|:1076 - - 1 - B 35 AND2 0 2 0 1 |MOUSE:MS|:172 - - 2 - B 35 OR2 0 3 0 1 |MOUSE:MS|:188 - - 3 - B 35 OR2 0 3 0 1 |MOUSE:MS|:198 - - 4 - B 35 OR2 0 3 0 1 |MOUSE:MS|:208 - - 5 - B 35 OR2 0 3 0 1 |MOUSE:MS|:219 - - 6 - B 35 OR2 0 3 0 1 |MOUSE:MS|:229 - - 7 - B 35 OR2 0 3 0 1 |MOUSE:MS|:239 - - 1 - B 31 AND2 0 2 0 1 |MOUSE:MS|:269 - - 2 - B 31 OR2 0 3 0 1 |MOUSE:MS|:285 - - 3 - B 31 OR2 0 3 0 1 |MOUSE:MS|:295 - - 4 - B 31 OR2 0 3 0 1 |MOUSE:MS|:305 - - 5 - B 31 OR2 0 3 0 1 |MOUSE:MS|:316 - - 6 - B 31 OR2 0 3 0 1 |MOUSE:MS|:326 - - 7 - B 31 OR2 0 3 0 1 |MOUSE:MS|:336 - - 1 - A 30 AND2 0 2 0 1 |video2:SVIDEO|:951 - - 2 - A 30 AND2 0 3 0 1 |video2:SVIDEO|:955 - - 3 - A 30 AND2 0 3 0 1 |video2:SVIDEO|:959 - - 4 - A 30 AND2 0 3 0 1 |video2:SVIDEO|:963 - - 5 - A 30 OR2 ! 0 3 0 1 |video2:SVIDEO|:973 - - 1 - D 22 AND2 0 2 0 1 |video2:SVIDEO|:995 - - 2 - D 22 AND2 0 3 0 1 |video2:SVIDEO|:999 - - 3 - D 22 AND2 0 3 0 1 |video2:SVIDEO|:1003 - - 4 - D 22 AND2 0 3 0 1 |video2:SVIDEO|:1007 - - 5 - D 22 AND2 0 3 0 1 |video2:SVIDEO|:1011 - - 6 - D 22 AND2 0 3 0 1 |video2:SVIDEO|:1015 - - 7 - D 22 AND2 0 3 0 1 |video2:SVIDEO|:1019 - - 1 - B 30 AND2 0 1 0 1 |video2:SVIDEO|:1039 - - 2 - B 30 AND2 0 1 0 1 |video2:SVIDEO|:1043 - - 3 - B 30 AND2 0 1 0 1 |video2:SVIDEO|:1047 - - 4 - B 30 OR2 0 5 0 1 |video2:SVIDEO|:1049 - - 1 - F 22 AND2 0 3 0 1 :2084 - - 2 - F 22 AND2 0 4 0 1 :2088 - - 3 - F 22 AND2 0 4 0 1 :2092 - - 4 - F 22 OR2 0 3 0 1 :2094 - - 4 - A 19 AND2 0 4 0 1 :2405 - - 6 - A 19 AND2 s 0 1 0 1 ~2409~1 - - 5 - A 19 AND2 0 2 0 1 :2409 - - 7 - A 19 AND2 0 3 0 1 :2413 - - 8 - A 19 AND2 0 2 0 1 :2417 - - 2 - A 21 AND2 s 0 1 0 1 ~2421~1 - - 1 - A 21 AND2 0 2 0 1 :2421 - - 3 - A 21 AND2 0 3 0 1 :2425 - - 1 - A 24 AND2 0 3 0 1 :2465 - - 2 - A 24 AND2 0 3 0 1 :2469 - - 3 - A 24 AND2 0 3 0 1 :2473 - - 4 - A 24 AND2 0 3 0 1 :2477 - - 5 - A 24 AND2 0 3 0 1 :2481 - - 1 - A 32 AND2 0 2 0 1 :2546 - - 2 - A 32 AND2 0 2 0 1 :2550 - - 3 - A 32 AND2 0 2 0 1 :2554 - - 4 - A 32 AND2 0 2 0 1 :2558 - - 5 - A 32 AND2 0 2 0 1 :2562 - - 6 - A 32 AND2 0 2 0 1 :2566 - - 3 - C 02 AND2 0 4 0 1 :2717 - - 4 - C 02 OR2 0 3 0 1 :2736 - - 5 - C 02 OR2 0 3 0 1 :2746 - - 6 - C 02 OR2 0 3 0 1 :2757 - - 7 - C 02 OR2 0 3 0 1 :2767 - - 8 - C 02 OR2 0 3 0 1 :2777 - - 1 - C 04 OR2 0 3 0 1 :2788 - - 2 - C 04 OR2 0 3 0 1 :2798 - - 3 - C 04 OR2 0 3 0 1 :2808 - - 4 - C 04 OR2 0 3 0 1 :2816 - - -Code: - -s = Synthesized pin or logic cell -+ = Synchronous flipflop -/ = Slow slew-rate output -! = NOT gate push-back -r = Fitter-inserted logic cell -^ = Increased input delay -* = PCI I/O is enabled -p = Packed register - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** FASTTRACK INTERCONNECT UTILIZATION ** - -Row FastTrack Interconnect: - - Global Left Half- Right Half- - FastTrack FastTrack FastTrack -Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins -A: 142/144( 98%) 70/ 72( 97%) 71/ 72( 98%) 0/16( 0%) 3/16( 18%) 6/16( 37%) -B: 132/144( 91%) 63/ 72( 87%) 65/ 72( 90%) 0/16( 0%) 4/16( 25%) 6/16( 37%) -C: 142/144( 98%) 63/ 72( 87%) 66/ 72( 91%) 1/16( 6%) 1/16( 6%) 9/16( 56%) -D: 132/144( 91%) 45/ 72( 62%) 65/ 72( 90%) 7/16( 43%) 0/16( 0%) 4/16( 25%) -E: 98/144( 68%) 53/ 72( 73%) 47/ 72( 65%) 6/16( 37%) 0/16( 0%) 4/16( 25%) -F: 118/144( 81%) 62/ 72( 86%) 55/ 72( 76%) 4/16( 25%) 0/16( 0%) 6/16( 37%) - - -Column FastTrack Interconnect: - - FastTrack -Column Interconnect Input Pins Output Pins Bidir Pins -01: 11/24( 45%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -02: 16/24( 66%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -03: 15/24( 62%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -04: 12/24( 50%) 0/4( 0%) 2/4( 50%) 1/4( 25%) -05: 13/24( 54%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -06: 13/24( 54%) 0/4( 0%) 1/4( 25%) 2/4( 50%) -07: 14/24( 58%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -08: 16/24( 66%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -09: 13/24( 54%) 0/4( 0%) 3/4( 75%) 0/4( 0%) -10: 14/24( 58%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -11: 17/24( 70%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -12: 13/24( 54%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -13: 13/24( 54%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -14: 15/24( 62%) 0/4( 0%) 4/4(100%) 0/4( 0%) -15: 9/24( 37%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -16: 14/24( 58%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -17: 16/24( 66%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -18: 14/24( 58%) 0/4( 0%) 0/4( 0%) 1/4( 25%) -19: 13/24( 54%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -20: 15/24( 62%) 0/4( 0%) 2/4( 50%) 1/4( 25%) -21: 17/24( 70%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -22: 15/24( 62%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -23: 12/24( 50%) 0/4( 0%) 2/4( 50%) 0/4( 0%) -24: 15/24( 62%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -25: 14/24( 58%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -26: 15/24( 62%) 0/4( 0%) 3/4( 75%) 0/4( 0%) -27: 15/24( 62%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -28: 17/24( 70%) 0/4( 0%) 2/4( 50%) 1/4( 25%) -29: 15/24( 62%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -30: 14/24( 58%) 0/4( 0%) 0/4( 0%) 2/4( 50%) -31: 13/24( 54%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -32: 16/24( 66%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -33: 15/24( 62%) 0/4( 0%) 0/4( 0%) 2/4( 50%) -34: 14/24( 58%) 0/4( 0%) 2/4( 50%) 1/4( 25%) -35: 15/24( 62%) 0/4( 0%) 1/4( 25%) 1/4( 25%) -36: 13/24( 54%) 0/4( 0%) 0/4( 0%) 2/4( 50%) -EA: 7/24( 29%) 0/4( 0%) 0/4( 0%) 0/4( 0%) - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** CLOCK SIGNALS ** - -Type Fan-out Name -INPUT 700 TG42 -DFF 42 /IOWR -DFF 42 :1508 -INPUT 36 /mr -DFF 31 |video2:SVIDEO|:295 -INPUT 30 /io -LCELL 24 |video2:SVIDEO|LWR_MODE -DFF 21 |video2:SVIDEO|:302 -DFF 20 CBL_CNT6 -LCELL 19 |dcp:DECODE|/IOWR -DFF 18 |video2:SVIDEO|:293 -INPUT 16 /m1 -DFF 16 |kbd:KEYS|KB_CT2 -DFF 16 :1506 -LCELL 16 CBL_WR -DFF 15 |kbd:KEYS|RXA0 -DFF 14 |dcp:DECODE|:245 -DFF 13 |video2:SVIDEO|:292 -DFF 10 |kbd:KEYS|RXA1 -DFF 10 |kbd:KEYS|:179 -DFF 10 |dcp:DECODE|:246 -DFF 9 |video2:SVIDEO|LWR_COL -DFF 9 |video2:SVIDEO|:298 -DFF 9 |video2:SVIDEO|:304 -DFF 8 |acceler:ACC|:450 -LCELL 8 :1341 -DFF 7 |kbd:KEYS|KB_MA2 -DFF 7 |dcp:DECODE|:457 -DFF 6 |video2:SVIDEO|:301 -LCELL 6 T_RDXA -DFF 5 :1504 -DFF 4 |dcp:DECODE|:237 -DFF 4 |ay:AY3|AY_CCC7 -LCELL 4 |acceler:ACC|:439 -DFF 4 |video2:SVIDEO|V_WE -DFF 3 |kbd:KEYS|K_CLK -DFF 2 |acceler:ACC|WR_C7 -DFF 2 |video2:SVIDEO|WR_PIC -DFF 2 /IORD -DFF 2 |kbd:KEYS|:181 -LCELL 2 :3210 -DFF 1 |kbd:KEYS|:180 -DFF 1 |kbd:KEYS|:187 -DFF 1 |dcp:DECODE|:251 -LCELL 1 :3056 -LCELL 1 :3105 - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** CLEAR SIGNALS ** - -Type Fan-out Name -INPUT 79 /reset -INPUT 30 /io -DFF 28 CBL_XX7 -DFF 23 |dcp:DECODE|:239 -DFF 22 |ay:AY3|:458 -DFF 19 |dcp:DECODE|:267 -DFF 17 |dcp:DECODE|:452 -DFF 16 |kbd:KEYS|KB_CT2 -INPUT 16 /m1 -LCELL 16 |dcp:DECODE|:1220 -DFF 9 copy_sinc_v -DFF 9 CBL_XX5 -DFF 9 |video2:SVIDEO|:632 -LCELL 7 :2539 -DFF 7 |ay:AY3|AY_SH_Q -DFF 7 copy_sinc_h -DFF 7 |ay:AY3|AY_F_RES -DFF 6 |kbd:KEYS|:198 -DFF 6 |kbd:KEYS|:196 -LCELL 5 WAIT_ROMX -LCELL 5 |dcp:DECODE|:1309 -DFF 5 |video2:SVIDEO|BORD -LCELL 4 |MOUSE:MS|MOUSE_IMP -DFF 4 KEY_IO -DFF 4 |dcp:DECODE|PORTS_X -DFF 4 CBL_INT -DFF 4 |video2:SVIDEO|F_WR -DFF 4 |video2:SVIDEO|V_WE -LCELL 3 |video2:SVIDEO|E_WR -LCELL 3 |acceler:ACC|:1012 -LCELL 3 |ay:AY3|:481 -LCELL 3 |dcp:DECODE|:1307 -DFF 3 |dcp:DECODE|RFC -DFF 3 |kbd:KEYS|:178 -DFF 2 :1409 -LCELL 2 |acceler:ACC|CORRECT_1F -DFF 2 |kbd:KEYS|:181 -DFF 2 |ay:AY3|AY_F_R1 -LCELL 2 |dcp:DECODE|:1310 -DFF 2 |ay:AY3|:422 -LCELL 2 |dcp:DECODE|:987 -LCELL 1 :1425 -LCELL 1 :1427 -LCELL 1 :1429 -LCELL 1 :2013 -LCELL 1 ~2536~1 -LCELL 1 |acceler:ACC|:548 -LCELL 1 :2931 -LCELL 1 :2974 -LCELL 1 :3104 -LCELL 1 |acceler:ACC|:1014 -LCELL 1 :1336 -LCELL 1 |acceler:ACC|:1634 -LCELL 1 |dcp:DECODE|:1311 -LCELL 1 |kbd:KEYS|:605 -LCELL 1 |dcp:DECODE|:1037 -DFF 1 |dcp:DECODE|:485 -LCELL 1 |dcp:DECODE|:472 -LCELL 1 |dcp:DECODE|:470 -DFF 1 |dcp:DECODE|:461 -LCELL 1 |ay:AY3|:495 -DFF 1 |video2:SVIDEO|V_WE_R -LCELL 1 :3254 - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** CARRY CHAINS ** - -Type Member Length Member Name: SUM, (CARRY) -UP/DOWN COUNTER 1 |acceler:ACC|AAGR0, (|acceler:ACC|:735) -ARITHMETIC 2 |acceler:ACC|:748, (|acceler:ACC|:751) -ARITHMETIC 3 |acceler:ACC|~751~1, (|acceler:ACC|~751~2) -ARITHMETIC 4 |acceler:ACC|~758~1, (|acceler:ACC|:761) -ARITHMETIC 5 |acceler:ACC|~761~1, (|acceler:ACC|~761~2) -ARITHMETIC 6 |acceler:ACC|~768~1, (|acceler:ACC|:771) -ARITHMETIC 7 |acceler:ACC|~771~1, (|acceler:ACC|~771~2) -ARITHMETIC 8 |acceler:ACC|~779~1, (|acceler:ACC|:782) -ARITHMETIC 9 |acceler:ACC|~782~1, (|acceler:ACC|~782~2) -ARITHMETIC 10 |acceler:ACC|~789~1, (|acceler:ACC|:792) -ARITHMETIC 11 |acceler:ACC|~792~1, (|acceler:ACC|~792~2) -ARITHMETIC 12 |acceler:ACC|~799~1, (|acceler:ACC|:802) -ARITHMETIC 13 |acceler:ACC|~802~1, (|acceler:ACC|~802~2) -ARITHMETIC 14 |acceler:ACC|~810~1, (|acceler:ACC|:813) -ARITHMETIC 15 |acceler:ACC|:820, (|acceler:ACC|:823) -ARITHMETIC 16 |acceler:ACC|:830, (|acceler:ACC|:833) -UP/DOWN COUNTER 17 |acceler:ACC|XCNT2, (|acceler:ACC|:838) -UP/DOWN COUNTER 18 |acceler:ACC|XCNT3, (|acceler:ACC|:842) -UP/DOWN COUNTER 19 |acceler:ACC|XCNT4, (|acceler:ACC|:846) -UP/DOWN COUNTER 20 |acceler:ACC|XCNT5, (|acceler:ACC|:850) -CLEARABLE COUNTER 21 |acceler:ACC|XCNT6, (|acceler:ACC|:854) -NORMAL 22 |acceler:ACC|XCNT7 - -UP/DOWN COUNTER 1 |acceler:ACC|AA0, (|acceler:ACC|:1376) -UP/DOWN COUNTER 2 |acceler:ACC|AA2, (|acceler:ACC|:1380) -UP/DOWN COUNTER 3 |acceler:ACC|AA3, (|acceler:ACC|:1384) -UP/DOWN COUNTER 4 |acceler:ACC|AA4, (|acceler:ACC|:1388) -UP/DOWN COUNTER 5 |acceler:ACC|AA5, (|acceler:ACC|:1392) -UP/DOWN COUNTER 6 |acceler:ACC|AA6, (|acceler:ACC|:1396) -UP/DOWN COUNTER 7 |acceler:ACC|AA7, (|acceler:ACC|:1400) -UP/DOWN COUNTER 8 |acceler:ACC|AA8, (|acceler:ACC|:1404) -UP/DOWN COUNTER 9 |acceler:ACC|AA9, (|acceler:ACC|:1408) -UP/DOWN COUNTER 10 |acceler:ACC|AA10, (|acceler:ACC|:1412) -UP/DOWN COUNTER 11 |acceler:ACC|AA11, (|acceler:ACC|:1416) -UP/DOWN COUNTER 12 |acceler:ACC|AA12, (|acceler:ACC|:1420) -UP/DOWN COUNTER 13 |acceler:ACC|AA13, (|acceler:ACC|:1424) -UP/DOWN COUNTER 14 |acceler:ACC|AA14, (|acceler:ACC|:1428) -ARITHMETIC 15 |dcp:DECODE|MPGS4, (|acceler:ACC|:1430) -NORMAL 16 |acceler:ACC|AA15 - -UP/DOWN COUNTER 1 AY_FULL1, (:2717) -ARITHMETIC 2 AY_CHS6, (:2736) -ARITHMETIC 3 AY_CHS7, (:2746) -ARITHMETIC 4 AY_CHS8, (:2757) -ARITHMETIC 5 AY_CHS9, (:2767) -ARITHMETIC 6 AY_CHS10, (:2777) -ARITHMETIC 7 AY_CHS11, (:2788) -ARITHMETIC 8 AY_CHS12, (:2798) -ARITHMETIC 9 AY_CHS13, (:2808) -ARITHMETIC 10 AY_CHS15, (:2816) -NORMAL 11 AY_CHS14 - -ARITHMETIC 1 (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_0) -ARITHMETIC 2 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node1, (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_1) -ARITHMETIC 3 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node2, (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_2) -ARITHMETIC 4 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node3, (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_3) -ARITHMETIC 5 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node4, (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_4) -ARITHMETIC 6 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node5, (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_5) -ARITHMETIC 7 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node6, (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_6) -ARITHMETIC 8 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node7, (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_7) -ARITHMETIC 9 |ay:AY3|lpm_add_sub:121|addcore:adder|result_node8, (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_8) -UP/DOWN COUNTER 10 |ay:AY3|AY_CH_LX9, (|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_9) -NORMAL 11 |ay:AY3|AY_CH_LX10 - -ARITHMETIC 1 (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_0) -ARITHMETIC 2 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node1, (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_1) -ARITHMETIC 3 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node2, (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_2) -ARITHMETIC 4 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node3, (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_3) -ARITHMETIC 5 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node4, (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_4) -ARITHMETIC 6 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node5, (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_5) -ARITHMETIC 7 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node6, (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_6) -ARITHMETIC 8 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node7, (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_7) -ARITHMETIC 9 |ay:AY3|lpm_add_sub:164|addcore:adder|result_node8, (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_8) -UP/DOWN COUNTER 10 |ay:AY3|AY_CH_RX9, (|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_9) -NORMAL 11 |ay:AY3|AY_CH_RX10 - -ARITHMETIC 1 |acceler:ACC|:676, (|acceler:ACC|:678) -UP/DOWN COUNTER 2 |acceler:ACC|ACC_CNT2, (|acceler:ACC|:683) -UP/DOWN COUNTER 3 |acceler:ACC|ACC_CNT3, (|acceler:ACC|:688) -UP/DOWN COUNTER 4 |acceler:ACC|ACC_CNT4, (|acceler:ACC|:694) -UP/DOWN COUNTER 5 |acceler:ACC|ACC_CNT5, (|acceler:ACC|:699) -UP/DOWN COUNTER 6 |acceler:ACC|ACC_CNT6, (|acceler:ACC|:704) -ARITHMETIC 7 (|acceler:ACC|:708) -UP/DOWN COUNTER 8 |acceler:ACC|:427, (|acceler:ACC|:734) -NORMAL 9 |acceler:ACC|ACC_CNT7 - -UP/DOWN COUNTER 1 CBL_CNT0, (:2405) -ARITHMETIC 2 ~2405~1, (:2409) -ARITHMETIC 3 ~2409~2, (~2409~1) -UP/DOWN COUNTER 4 CBL_CNT3, (:2413) -ARITHMETIC 5 ~2413~1, (:2417) -ARITHMETIC 6 ~2417~1, (:2421) -ARITHMETIC 7 ~2421~2, (~2421~1) -UP/DOWN COUNTER 8 CBL_CNT6, (:2425) -NORMAL 9 ~2509~1 - -UP/DOWN COUNTER 1 |video2:SVIDEO|:312, (|video2:SVIDEO|:995) -CLEARABLE COUNTER 2 |video2:SVIDEO|:310, (|video2:SVIDEO|:999) -CLEARABLE COUNTER 3 |video2:SVIDEO|:309, (|video2:SVIDEO|:1003) -CLEARABLE COUNTER 4 |video2:SVIDEO|:308, (|video2:SVIDEO|:1007) -UP/DOWN COUNTER 5 |video2:SVIDEO|:307, (|video2:SVIDEO|:1011) -CLEARABLE COUNTER 6 |video2:SVIDEO|:306, (|video2:SVIDEO|:1015) -CLEARABLE COUNTER 7 |video2:SVIDEO|:305, (|video2:SVIDEO|:1019) -NORMAL 8 |video2:SVIDEO|:304 - -ARITHMETIC 1 (|MOUSE:MS|:269) -ARITHMETIC 2 |MOUSE:MS|:282, (|MOUSE:MS|:285) -ARITHMETIC 3 |MOUSE:MS|:292, (|MOUSE:MS|:295) -ARITHMETIC 4 |MOUSE:MS|:302, (|MOUSE:MS|:305) -ARITHMETIC 5 |MOUSE:MS|:313, (|MOUSE:MS|:316) -ARITHMETIC 6 |MOUSE:MS|:323, (|MOUSE:MS|:326) -ARITHMETIC 7 |MOUSE:MS|:333, (|MOUSE:MS|:336) -NORMAL 8 |MOUSE:MS|SUM_Y7 - -ARITHMETIC 1 (|MOUSE:MS|:172) -ARITHMETIC 2 |MOUSE:MS|:185, (|MOUSE:MS|:188) -ARITHMETIC 3 |MOUSE:MS|:195, (|MOUSE:MS|:198) -ARITHMETIC 4 |MOUSE:MS|:205, (|MOUSE:MS|:208) -ARITHMETIC 5 |MOUSE:MS|:216, (|MOUSE:MS|:219) -ARITHMETIC 6 |MOUSE:MS|:226, (|MOUSE:MS|:229) -ARITHMETIC 7 |MOUSE:MS|:236, (|MOUSE:MS|:239) -NORMAL 8 |MOUSE:MS|SUM_X7 - -ARITHMETIC 1 (:2546) -ARITHMETIC 2 :2548, (:2550) -ARITHMETIC 3 :2552, (:2554) -ARITHMETIC 4 :2556, (:2558) -ARITHMETIC 5 :2560, (:2562) -ARITHMETIC 6 :2564, (:2566) -NORMAL 7 CBL_WA7 - -UP/DOWN COUNTER 1 |acceler:ACC|AGR0, (|acceler:ACC|:604) -UP/DOWN COUNTER 2 |acceler:ACC|AGR2, (|acceler:ACC|:608) -UP/DOWN COUNTER 3 |acceler:ACC|AGR3, (|acceler:ACC|:612) -UP/DOWN COUNTER 4 |acceler:ACC|AGR4, (|acceler:ACC|:616) -UP/DOWN COUNTER 5 |acceler:ACC|AGR5, (|acceler:ACC|:620) -UP/DOWN COUNTER 6 |acceler:ACC|AGR6, (|acceler:ACC|:624) -NORMAL 7 |acceler:ACC|AGR7 - -UP/DOWN COUNTER 1 |video2:SVIDEO|:303, (|video2:SVIDEO|:951) -CLEARABLE COUNTER 2 |video2:SVIDEO|:301, (|video2:SVIDEO|:955) -CLEARABLE COUNTER 3 |video2:SVIDEO|:300, (|video2:SVIDEO|:959) -UP/DOWN COUNTER 4 |video2:SVIDEO|:299, (|video2:SVIDEO|:963) -ARITHMETIC 5 :1508, (|video2:SVIDEO|:973) -NORMAL 6 |video2:SVIDEO|:298 - -UP/DOWN COUNTER 1 |ay:AY3|AY_VAR, (|ay:AY3|:787) -UP/DOWN COUNTER 2 |ay:AY3|AY_VA1, (|ay:AY3|:791) -UP/DOWN COUNTER 3 |ay:AY3|AY_VA2, (|ay:AY3|:795) -UP/DOWN COUNTER 4 |ay:AY3|AY_VA3, (|ay:AY3|:799) -CLEARABLE COUNTER 5 |ay:AY3|AY_BBLK, (|ay:AY3|:801) -NORMAL 6 |ay:AY3|AY_VX - -ARITHMETIC 1 (|ay:AY3|:693) -ARITHMETIC 2 |ay:AY3|AY_DAT4, (|ay:AY3|:698) -ARITHMETIC 3 |ay:AY3|AY_DAT5, (|ay:AY3|:703) -ARITHMETIC 4 |ay:AY3|AY_DAT6, (|ay:AY3|:709) -ARITHMETIC 5 |ay:AY3|AY_DAT7, (|ay:AY3|:714) -NORMAL 6 |ay:AY3|AY_C - -UP/DOWN COUNTER 1 CBL_CNT2, (:2465) -ARITHMETIC 2 :2496, (:2469) -UP/DOWN COUNTER 3 CBL_CNT4, (:2473) -UP/DOWN COUNTER 4 CBL_CNT5, (:2477) -ARITHMETIC 5 :2505, (:2481) -NORMAL 6 CBL_CNT7 - -ARITHMETIC 1 (|dcp:DECODE|:1054) -CLEARABLE COUNTER 2 |dcp:DECODE|WT_CT2, (|dcp:DECODE|:1059) -ARITHMETIC 3 (|dcp:DECODE|:1075) -UP/DOWN COUNTER 4 |dcp:DECODE|:245, (|dcp:DECODE|:1076) -NORMAL 5 |dcp:DECODE|WT_CT3 - -UP/DOWN COUNTER 1 |video2:SVIDEO|:319, (|video2:SVIDEO|:1039) -UP/DOWN COUNTER 2 |video2:SVIDEO|:317, (|video2:SVIDEO|:1043) -UP/DOWN COUNTER 3 |video2:SVIDEO|:316, (|video2:SVIDEO|:1047) -UP/DOWN COUNTER 4 |video2:SVIDEO|RBRVA9, (|video2:SVIDEO|:1049) -NORMAL 5 |video2:SVIDEO|:315 - -UP/DOWN COUNTER 1 SINC_HOLD4, (:2084) -UP/DOWN COUNTER 2 SINC_HOLD6, (:2088) -UP/DOWN COUNTER 3 SINC_HOLD7, (:2092) -ARITHMETIC 4 SINC_2M, (:2094) -NORMAL 5 SINC_HOLD8 - - - -Device-Specific Information: c:\sprinter\src\altera\acex\sp2_acex.rpt -SP2_ACEX - -** EQUATIONS ** - -a0 : INPUT; -a1 : INPUT; -a2 : INPUT; -a3 : INPUT; -a4 : INPUT; -a5 : INPUT; -A6 : INPUT; -A7 : INPUT; -A8 : INPUT; -a9 : INPUT; -A10 : INPUT; -a11 : INPUT; -A12 : INPUT; -A13 : INPUT; -A14 : INPUT; -A15 : INPUT; -TG42 : INPUT; -/HALT : INPUT; -/io : INPUT; -/mr : INPUT; -/m1 : INPUT; -/rd : INPUT; -/rf : INPUT; -/wr : INPUT; - --- Node name is 'ALL_MODE0' from file "sp2_acex.tdf" line 250, column 10 --- Equation name is 'ALL_MODE0', location is LC1_F26, type is buried. -!ALL_MODE0 = ALL_MODE0~NOT; -ALL_MODE0~NOT = DFFE(!D0, /IOWR, /reset, VCC, _LC2_F31); - --- Node name is 'ALL_MODE2' from file "sp2_acex.tdf" line 250, column 10 --- Equation name is 'ALL_MODE2', location is LC7_F26, type is buried. -!ALL_MODE2 = ALL_MODE2~NOT; -ALL_MODE2~NOT = DFFE(!d2, /IOWR, /reset, VCC, _LC2_F31); - --- Node name is 'ALL_MODE3' from file "sp2_acex.tdf" line 250, column 10 --- Equation name is 'ALL_MODE3', location is LC8_F26, type is buried. -!ALL_MODE3 = ALL_MODE3~NOT; -ALL_MODE3~NOT = DFFE(!d3, /IOWR, /reset, VCC, _LC2_F31); - --- Node name is 'AUDIO_CH' from file "sp2_acex.tdf" line 1063, column 13 --- Equation name is 'AUDIO_CH', location is LC2_A36, type is buried. -AUDIO_CH = DFFE( _EQ001, _LC3_E28, VCC, VCC, VCC); - _EQ001 = _LC1_A30 & _LC5_A29 & _LC6_A29 & _LC7_A29; - --- Node name is 'AUDIO_R0' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R0', location is LC8_A16, type is buried. -AUDIO_R0 = DFFE( _EQ002, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ002 = AUDIO_CH & AY_CHS0; - --- Node name is 'AUDIO_R1' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R1', location is LC1_A16, type is buried. -AUDIO_R1 = DFFE( _EQ003, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ003 = !AUDIO_CH & AUDIO_R0 - # AUDIO_CH & AY_CHS1; - --- Node name is 'AUDIO_R2' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R2', location is LC8_A17, type is buried. -AUDIO_R2 = DFFE( _EQ004, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ004 = !AUDIO_CH & AUDIO_R1 - # AUDIO_CH & AY_CHS2; - --- Node name is 'AUDIO_R3' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R3', location is LC7_A17, type is buried. -AUDIO_R3 = DFFE( _EQ005, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ005 = !AUDIO_CH & AUDIO_R2 - # AUDIO_CH & AY_CHS3; - --- Node name is 'AUDIO_R4' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R4', location is LC4_A17, type is buried. -AUDIO_R4 = DFFE( _EQ006, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ006 = !AUDIO_CH & AUDIO_R3 - # AUDIO_CH & AY_CHS4; - --- Node name is 'AUDIO_R5' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R5', location is LC2_A13, type is buried. -AUDIO_R5 = DFFE( _EQ007, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ007 = !AUDIO_CH & AUDIO_R4 - # AUDIO_CH & AY_CHS5; - --- Node name is 'AUDIO_R6' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R6', location is LC7_A13, type is buried. -AUDIO_R6 = DFFE( _EQ008, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ008 = !AUDIO_CH & AUDIO_R5 - # AUDIO_CH & AY_CHS6; - --- Node name is 'AUDIO_R7' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R7', location is LC5_A13, type is buried. -AUDIO_R7 = DFFE( _EQ009, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ009 = !AUDIO_CH & AUDIO_R6 - # AUDIO_CH & AY_CHS7; - --- Node name is 'AUDIO_R8' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R8', location is LC4_A13, type is buried. -AUDIO_R8 = DFFE( _EQ010, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ010 = !AUDIO_CH & AUDIO_R7 - # AUDIO_CH & AY_CHS8; - --- Node name is 'AUDIO_R9' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R9', location is LC3_A13, type is buried. -AUDIO_R9 = DFFE( _EQ011, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ011 = !AUDIO_CH & AUDIO_R8 - # AUDIO_CH & AY_CHS9; - --- Node name is 'AUDIO_R10' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R10', location is LC8_A13, type is buried. -AUDIO_R10 = DFFE( _EQ012, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ012 = !AUDIO_CH & AUDIO_R9 - # AUDIO_CH & AY_CHS10; - --- Node name is 'AUDIO_R11' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R11', location is LC6_A13, type is buried. -AUDIO_R11 = DFFE( _EQ013, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ013 = !AUDIO_CH & AUDIO_R10 - # AUDIO_CH & AY_CHS11; - --- Node name is 'AUDIO_R12' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R12', location is LC2_A3, type is buried. -AUDIO_R12 = DFFE( _EQ014, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ014 = !AUDIO_CH & AUDIO_R11 - # AUDIO_CH & AY_CHS12; - --- Node name is 'AUDIO_R13' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R13', location is LC3_A3, type is buried. -AUDIO_R13 = DFFE( _EQ015, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ015 = !AUDIO_CH & AUDIO_R12 - # AUDIO_CH & AY_CHS13; - --- Node name is 'AUDIO_R14' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R14', location is LC6_A3, type is buried. -AUDIO_R14 = DFFE( _EQ016, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ016 = !AUDIO_CH & AUDIO_R13 - # AUDIO_CH & AY_CHS14; - --- Node name is 'AUDIO_R15' from file "sp2_acex.tdf" line 207, column 9 --- Equation name is 'AUDIO_R15', location is LC4_A3, type is buried. -AUDIO_R15 = DFFE( _EQ017, GLOBAL( TG42), VCC, VCC, _LC1_A35); - _EQ017 = !AUDIO_CH & AUDIO_R14 - # AUDIO_CH & AY_CHS15; - --- Node name is 'AY_CHS0' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS0', location is LC4_A16, type is buried. -AY_CHS0 = DFFE( CBL_R1, !_LC4_A36, VCC, VCC, VCC); - --- Node name is 'AY_CHS1' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS1', location is LC3_A16, type is buried. -AY_CHS1 = DFFE( CBL_R2, !_LC4_A36, VCC, VCC, VCC); - --- Node name is 'AY_CHS2' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS2', location is LC3_A17, type is buried. -AY_CHS2 = DFFE( CBL_R3, !_LC4_A36, VCC, VCC, VCC); - --- Node name is 'AY_CHS3' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS3', location is LC2_A17, type is buried. -AY_CHS3 = DFFE( CBL_R4, !_LC4_A36, VCC, VCC, VCC); - --- Node name is 'AY_CHS4' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS4', location is LC1_A17, type is buried. -AY_CHS4 = DFFE( CBL_R5, !_LC4_A36, VCC, VCC, VCC); - --- Node name is 'AY_CHS5' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS5', location is LC1_A13, type is buried. -AY_CHS5 = DFFE( _EQ018, !_LC4_A36, VCC, VCC, VCC); - _EQ018 = AY_FULL1 & !CBL_R6 - # !AY_FULL1 & CBL_R6; - --- Node name is 'AY_CHS6' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS6', location is LC4_C2, type is buried. -AY_CHS6 = DFFE( _EQ019, !_LC4_A36, VCC, VCC, VCC); - _EQ019 = !AY_FULL2 & CBL_R7 & !_LC3_C2_CARRY - # AY_FULL2 & !CBL_R7 & !_LC3_C2_CARRY - # !AY_FULL2 & !CBL_R7 & _LC3_C2_CARRY - # AY_FULL2 & CBL_R7 & _LC3_C2_CARRY; - --- Node name is 'AY_CHS7' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS7', location is LC5_C2, type is buried. -AY_CHS7 = DFFE( _EQ020, !_LC4_A36, VCC, VCC, VCC); - _EQ020 = !AY_FULL3 & CBL_R8 & !_LC4_C2_CARRY - # AY_FULL3 & !CBL_R8 & !_LC4_C2_CARRY - # !AY_FULL3 & !CBL_R8 & _LC4_C2_CARRY - # AY_FULL3 & CBL_R8 & _LC4_C2_CARRY; - --- Node name is 'AY_CHS8' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS8', location is LC6_C2, type is buried. -AY_CHS8 = DFFE( _EQ021, !_LC4_A36, VCC, VCC, VCC); - _EQ021 = !AY_FULL4 & CBL_R9 & !_LC5_C2_CARRY - # AY_FULL4 & !CBL_R9 & !_LC5_C2_CARRY - # !AY_FULL4 & !CBL_R9 & _LC5_C2_CARRY - # AY_FULL4 & CBL_R9 & _LC5_C2_CARRY; - --- Node name is 'AY_CHS9' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS9', location is LC7_C2, type is buried. -AY_CHS9 = DFFE( _EQ022, !_LC4_A36, VCC, VCC, VCC); - _EQ022 = !AY_FULL5 & CBL_R10 & !_LC6_C2_CARRY - # AY_FULL5 & !CBL_R10 & !_LC6_C2_CARRY - # !AY_FULL5 & !CBL_R10 & _LC6_C2_CARRY - # AY_FULL5 & CBL_R10 & _LC6_C2_CARRY; - --- Node name is 'AY_CHS10' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS10', location is LC8_C2, type is buried. -AY_CHS10 = DFFE( _EQ023, !_LC4_A36, VCC, VCC, VCC); - _EQ023 = !AY_FULL6 & CBL_R11 & !_LC7_C2_CARRY - # AY_FULL6 & !CBL_R11 & !_LC7_C2_CARRY - # !AY_FULL6 & !CBL_R11 & _LC7_C2_CARRY - # AY_FULL6 & CBL_R11 & _LC7_C2_CARRY; - --- Node name is 'AY_CHS11' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS11', location is LC1_C4, type is buried. -AY_CHS11 = DFFE( _EQ024, !_LC4_A36, VCC, VCC, VCC); - _EQ024 = !AY_FULL7 & CBL_R12 & !_LC8_C2_CARRY - # AY_FULL7 & !CBL_R12 & !_LC8_C2_CARRY - # !AY_FULL7 & !CBL_R12 & _LC8_C2_CARRY - # AY_FULL7 & CBL_R12 & _LC8_C2_CARRY; - --- Node name is 'AY_CHS12' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS12', location is LC2_C4, type is buried. -AY_CHS12 = DFFE( _EQ025, !_LC4_A36, VCC, VCC, VCC); - _EQ025 = !AY_FULL8 & CBL_R13 & !_LC1_C4_CARRY - # AY_FULL8 & !CBL_R13 & !_LC1_C4_CARRY - # !AY_FULL8 & !CBL_R13 & _LC1_C4_CARRY - # AY_FULL8 & CBL_R13 & _LC1_C4_CARRY; - --- Node name is 'AY_CHS13' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS13', location is LC3_C4, type is buried. -AY_CHS13 = DFFE( _EQ026, !_LC4_A36, VCC, VCC, VCC); - _EQ026 = !AY_FULL9 & CBL_R14 & !_LC2_C4_CARRY - # AY_FULL9 & !CBL_R14 & !_LC2_C4_CARRY - # !AY_FULL9 & !CBL_R14 & _LC2_C4_CARRY - # AY_FULL9 & CBL_R14 & _LC2_C4_CARRY; - --- Node name is 'AY_CHS14' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS14', location is LC5_C4, type is buried. -AY_CHS14 = DFFE( _LC4_C4_CARRY, !_LC4_A36, VCC, VCC, VCC); - --- Node name is 'AY_CHS15' from file "sp2_acex.tdf" line 243, column 8 --- Equation name is 'AY_CHS15', location is LC4_C4, type is buried. -AY_CHS15 = DFFE( _EQ027, !_LC4_A36, VCC, VCC, VCC); - _EQ027 = !AY_FULL10 & !CBL_R15 - # !AY_FULL10 & !_LC3_C4_CARRY - # !CBL_R15 & !_LC3_C4_CARRY; - --- Node name is 'AY_FULL1' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL1', location is LC3_C2, type is buried. --- AY_FULL1 is in Up/Down Counter Mode --- synchronous load = _LC1_A10 --- synchronous data = _LC6_A18 -AY_FULL1 = DFFE(( _LC1_A6 & _LC1_A10 # _LC6_A18 & !_LC1_A10), GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'AY_FULL2' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL2', location is LC3_A10, type is buried. -AY_FULL2 = DFFE( _EQ028, GLOBAL( TG42), VCC, VCC, VCC); - _EQ028 = _LC1_A10 & _LC2_A6 - # !_LC1_A10 & _LC5_A18; - --- Node name is 'AY_FULL3' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL3', location is LC2_A12, type is buried. -AY_FULL3 = DFFE( _EQ029, GLOBAL( TG42), VCC, VCC, VCC); - _EQ029 = _LC1_A10 & _LC5_A12 - # !_LC1_A10 & _LC7_A18; - --- Node name is 'AY_FULL4' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL4', location is LC4_A12, type is buried. -AY_FULL4 = DFFE( _EQ030, GLOBAL( TG42), VCC, VCC, VCC); - _EQ030 = _LC1_A10 & _LC6_A12 - # _LC1_A2 & !_LC1_A10; - --- Node name is 'AY_FULL5' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL5', location is LC7_A12, type is buried. -AY_FULL5 = DFFE( _EQ031, GLOBAL( TG42), VCC, VCC, VCC); - _EQ031 = _LC1_A10 & _LC3_A12 - # !_LC1_A10 & _LC2_A2; - --- Node name is 'AY_FULL6' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL6', location is LC7_A10, type is buried. -AY_FULL6 = DFFE( _EQ032, GLOBAL( TG42), VCC, VCC, VCC); - _EQ032 = _LC1_A10 & _LC8_A8 - # !_LC1_A10 & _LC7_A4; - --- Node name is 'AY_FULL7' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL7', location is LC5_A10, type is buried. -AY_FULL7 = DFFE( _EQ033, GLOBAL( TG42), VCC, VCC, VCC); - _EQ033 = _LC1_A10 & _LC6_A8 - # !_LC1_A10 & _LC8_A4; - --- Node name is 'AY_FULL8' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL8', location is LC4_A10, type is buried. -AY_FULL8 = DFFE( _EQ034, GLOBAL( TG42), VCC, VCC, VCC); - _EQ034 = _LC1_A10 & _LC7_A8 - # !_LC1_A10 & _LC6_A4; - --- Node name is 'AY_FULL9' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL9', location is LC1_A18, type is buried. -AY_FULL9 = DFFE( _EQ035, GLOBAL( TG42), VCC, VCC, VCC); - _EQ035 = _LC1_A10 & _LC4_A8 - # !_LC1_A10 & _LC4_A4; - --- Node name is 'AY_FULL10' from file "sp2_acex.tdf" line 248, column 9 --- Equation name is 'AY_FULL10', location is LC2_A10, type is buried. -AY_FULL10 = DFFE( _EQ036, GLOBAL( TG42), VCC, VCC, VCC); - _EQ036 = _LC1_A10 & _LC5_A8 - # !_LC1_A10 & _LC5_A4; - --- Node name is 'AY/PORTS0' from file "sp2_acex.tdf" line 259, column 10 --- Equation name is 'AY/PORTS0', location is LC8_D26, type is buried. -AY/PORTS0 = LCELL( _EQ037); - _EQ037 = _EC2_C & !_EC6_C - # _EC6_C & _LC7_E19; - --- Node name is 'AY/PORTS1' from file "sp2_acex.tdf" line 259, column 10 --- Equation name is 'AY/PORTS1', location is LC4_D36, type is buried. -AY/PORTS1 = LCELL( _EQ038); - _EQ038 = !_EC6_C & _EC16_C - # _EC6_C & _LC3_E19; - --- Node name is 'AY/PORTS2' from file "sp2_acex.tdf" line 259, column 10 --- Equation name is 'AY/PORTS2', location is LC6_D23, type is buried. -AY/PORTS2 = LCELL( _EQ039); - _EQ039 = _EC5_C & !_EC6_C - # _EC6_C & _LC8_E19; - --- Node name is 'AY/PORTS3' from file "sp2_acex.tdf" line 259, column 10 --- Equation name is 'AY/PORTS3', location is LC6_D32, type is buried. -AY/PORTS3 = LCELL( _EQ040); - _EQ040 = !_EC6_C & _EC14_C - # _EC6_C & _LC3_E31; - --- Node name is 'AY/PORTS4' from file "sp2_acex.tdf" line 259, column 10 --- Equation name is 'AY/PORTS4', location is LC4_D32, type is buried. -AY/PORTS4 = LCELL( _EQ041); - _EQ041 = !_EC6_C & _EC7_C - # _EC6_C & _LC4_E31; - --- Node name is 'AY/PORTS5' from file "sp2_acex.tdf" line 259, column 10 --- Equation name is 'AY/PORTS5', location is LC6_A26, type is buried. -AY/PORTS5 = LCELL( _EQ042); - _EQ042 = !_EC6_C & _EC12_C - # _EC6_C & _LC2_E31; - --- Node name is 'AY/PORTS6' from file "sp2_acex.tdf" line 259, column 10 --- Equation name is 'AY/PORTS6', location is LC6_D29, type is buried. -AY/PORTS6 = LCELL( _EQ043); - _EQ043 = _EC1_C & !_EC6_C - # _EC6_C & _LC8_E31; - --- Node name is 'AY/PORTS7' from file "sp2_acex.tdf" line 259, column 10 --- Equation name is 'AY/PORTS7', location is LC7_A31, type is buried. -AY/PORTS7 = LCELL( _EQ044); - _EQ044 = !_EC6_C & _EC10_C - # _EC6_C & _LC7_E31; - --- Node name is 'blk_mem' from file "sp2_acex.tdf" line 632, column 13 --- Equation name is 'blk_mem', location is LC6_C18, type is buried. -blk_mem = LCELL( _EQ045); - _EQ045 = !PRE_ISA - # !PRE_ROM - # !PRE_CASH; - --- Node name is 'BLK_MR' from file "sp2_acex.tdf" line 972, column 12 --- Equation name is 'BLK_MR', location is LC4_C18, type is buried. -BLK_MR = LCELL( _EQ046); - _EQ046 = _EC5_C & VIDEO_PG - # _EC14_C & _LC7_D18 & VIDEO_PG; - --- Node name is 'BORDER0' from file "sp2_acex.tdf" line 164, column 8 --- Equation name is 'BORDER0', location is LC5_E23, type is buried. -BORDER0 = DFFE( D0, /IOWR, VCC, VCC, _LC2_F28); - --- Node name is 'BORDER1' from file "sp2_acex.tdf" line 164, column 8 --- Equation name is 'BORDER1', location is LC3_E23, type is buried. -BORDER1 = DFFE( D1, /IOWR, VCC, VCC, _LC2_F28); - --- Node name is 'BORDER2' from file "sp2_acex.tdf" line 164, column 8 --- Equation name is 'BORDER2', location is LC2_E23, type is buried. -BORDER2 = DFFE( d2, /IOWR, VCC, VCC, _LC2_F28); - --- Node name is 'BORDER3' from file "sp2_acex.tdf" line 164, column 8 --- Equation name is 'BORDER3', location is LC7_E23, type is buried. -BORDER3 = DFFE( d3, /IOWR, VCC, VCC, _LC2_F28); - --- Node name is 'BORDER4' from file "sp2_acex.tdf" line 164, column 8 --- Equation name is 'BORDER4', location is LC1_E23, type is buried. -BORDER4 = DFFE( d4, /IOWR, VCC, VCC, _LC2_F28); - --- Node name is 'CAS_A' from file "sp2_acex.tdf" line 864, column 10 --- Equation name is 'CAS_A', location is LC3_B36, type is buried. -CAS_A = LCELL( _LC7_F32); - --- Node name is 'CASH_ON' from file "sp2_acex.tdf" line 582, column 12 --- Equation name is 'CASH_ON', location is LC8_C25, type is buried. -CASH_ON = DFFE( A7, /IORD, /reset, VCC, _LC1_C29); - --- Node name is 'CASXE0' from file "sp2_acex.tdf" line 867, column 11 --- Equation name is 'CASXE0', location is LC7_B36, type is buried. -CASXE0 = LCELL( _EQ047); - _EQ047 = !_LC6_F16 - # _LC4_F11; - --- Node name is 'CASXE1' from file "sp2_acex.tdf" line 868, column 11 --- Equation name is 'CASXE1', location is LC8_B36, type is buried. -CASXE1 = LCELL( _EQ048); - _EQ048 = _LC6_F16 - # _LC4_F11; - --- Node name is 'CASX_0' from file "sp2_acex.tdf" line 870, column 11 --- Equation name is 'CASX_0', location is LC1_B36, type is buried. -CASX_0 = LCELL( _EQ049); - _EQ049 = CAS_A - # _LC8_A23 & !_LC8_C21 - # !CASXE0 & !_LC8_C21; - --- Node name is 'CASX_1' from file "sp2_acex.tdf" line 871, column 11 --- Equation name is 'CASX_1', location is LC5_B36, type is buried. -CASX_1 = LCELL( _EQ050); - _EQ050 = !CASXE1 & !_LC8_C21 - # _LC8_A23 & !_LC8_C21 - # CAS_A; - --- Node name is 'CASX_2' from file "sp2_acex.tdf" line 872, column 11 --- Equation name is 'CASX_2', location is LC2_B36, type is buried. -CASX_2 = LCELL( _EQ051); - _EQ051 = !_LC8_A23 & !_LC8_C21 - # !CASXE0 & !_LC8_C21 - # CAS_A; - --- Node name is 'CASX_3' from file "sp2_acex.tdf" line 873, column 11 --- Equation name is 'CASX_3', location is LC6_B36, type is buried. -CASX_3 = LCELL( _EQ052); - _EQ052 = !CASXE1 & !_LC8_C21 - # !_LC8_A23 & !_LC8_C21 - # CAS_A; - --- Node name is 'CAS_0' from file "sp2_acex.tdf" line 875, column 6 --- Equation name is 'CAS_0', type is output -CAS_0 = CASX_0; - --- Node name is 'CAS_1' from file "sp2_acex.tdf" line 875, column 6 --- Equation name is 'CAS_1', type is output -CAS_1 = CASX_1; - --- Node name is 'CAS_2' from file "sp2_acex.tdf" line 875, column 6 --- Equation name is 'CAS_2', type is output -CAS_2 = CASX_2; - --- Node name is 'CAS_3' from file "sp2_acex.tdf" line 875, column 6 --- Equation name is 'CAS_3', type is output -CAS_3 = CASX_3; - --- Node name is 'CBD1' from file "sp2_acex.tdf" line 205, column 5 --- Equation name is 'CBD1', location is LC4_A5, type is buried. -CBD1 = DFFE( _LC5_D25, !CBL_WR, CBL_XX5, VCC, !_LC6_A5); - --- Node name is 'CBD2' from file "sp2_acex.tdf" line 205, column 5 --- Equation name is 'CBD2', location is LC5_A5, type is buried. -CBD2 = DFFE( _LC2_D21, !CBL_WR, CBL_XX5, VCC, !_LC6_A5); - --- Node name is 'CBD3' from file "sp2_acex.tdf" line 205, column 5 --- Equation name is 'CBD3', location is LC8_A5, type is buried. -CBD3 = DFFE( _LC8_D19, !CBL_WR, CBL_XX5, VCC, !_LC6_A5); - --- Node name is 'CBD4' from file "sp2_acex.tdf" line 205, column 5 --- Equation name is 'CBD4', location is LC7_A5, type is buried. -CBD4 = DFFE( _LC8_D5, !CBL_WR, CBL_XX5, VCC, !_LC6_A5); - --- Node name is 'CBD5' from file "sp2_acex.tdf" line 205, column 5 --- Equation name is 'CBD5', location is LC3_A5, type is buried. -CBD5 = DFFE( _LC4_D5, !CBL_WR, CBL_XX5, VCC, !_LC6_A5); - --- Node name is 'CBD6' from file "sp2_acex.tdf" line 205, column 5 --- Equation name is 'CBD6', location is LC2_A5, type is buried. -CBD6 = DFFE( _LC3_D5, !CBL_WR, CBL_XX5, VCC, !_LC6_A5); - --- Node name is 'CBD7' from file "sp2_acex.tdf" line 205, column 5 --- Equation name is 'CBD7', location is LC1_A5, type is buried. -CBD7 = DFFE( _LC6_D3, !CBL_WR, CBL_XX5, VCC, !_LC6_A5); - --- Node name is 'CBL_CNT0' from file "sp2_acex.tdf" line 196, column 9 --- Equation name is 'CBL_CNT0', location is LC4_A19, type is buried. --- CBL_CNT0 is in Up/Down Counter Mode --- synchronous load = CBL_CNT0 --- synchronous data = !_LC6_A34 -CBL_CNT0 = DFFE(( _LC3_A28 & CBL_CNT0 # !_LC6_A34 & !CBL_CNT0), !_LC8_A30, CBL_XX7, VCC, VCC); - --- Node name is 'CBL_CNT1' from file "sp2_acex.tdf" line 196, column 9 --- Equation name is 'CBL_CNT1', location is LC8_A24, type is buried. -CBL_CNT1 = DFFE( _EQ053, !_LC8_A30, CBL_XX7, VCC, VCC); - _EQ053 = !CBL_CNT0 & CBL_CNT1 & !CBL_XX6 - # CBL_CNT0 & !CBL_CNT1 & _LC1_C31 - # !CBL_CNT1 & CBL_XX6 & _LC1_C31 - # CBL_CNT1 & !_LC1_C31; - --- Node name is 'CBL_CNT2' from file "sp2_acex.tdf" line 196, column 9 --- Equation name is 'CBL_CNT2', location is LC1_A24, type is buried. --- CBL_CNT2 is in Up/Down Counter Mode --- synchronous load = !_LC7_A25 -CBL_CNT2 = DFFE(( _LC7_A24 & !_LC7_A25 # _LC7_A25), !_LC8_A30, CBL_XX7, VCC, VCC); - --- Node name is 'CBL_CNT3' from file "sp2_acex.tdf" line 196, column 9 --- Equation name is 'CBL_CNT3', location is LC7_A19, type is buried. --- CBL_CNT3 is in Up/Down Counter Mode --- synchronous load = !_LC2_A19 -CBL_CNT3 = DFFE(( _LC1_A19 & !_LC2_A19 # _LC2_A19), !_LC8_A30, CBL_XX7, VCC, VCC); - --- Node name is 'CBL_CNT4' from file "sp2_acex.tdf" line 196, column 9 --- Equation name is 'CBL_CNT4', location is LC3_A24, type is buried. --- CBL_CNT4 is in Up/Down Counter Mode --- synchronous load = !_LC4_A33 -CBL_CNT4 = DFFE(( _EQ054 & !_LC4_A33 # _LC4_A33), !_LC8_A30, CBL_XX7, VCC, VCC); - _EQ054 = CBL_CNT4 & !_LC2_A24_CARRY & !_LC8_A28 - # !CBL_CNT4 & _LC2_A24_CARRY & !_LC8_A28; - --- Node name is 'CBL_CNT5' from file "sp2_acex.tdf" line 196, column 9 --- Equation name is 'CBL_CNT5', location is LC4_A24, type is buried. --- CBL_CNT5 is in Up/Down Counter Mode --- synchronous load = !_LC6_A21 -CBL_CNT5 = DFFE(( _EQ055 & !_LC6_A21 # _LC6_A21), !_LC8_A30, CBL_XX7, VCC, VCC); - _EQ055 = CBL_CNT5 & !_LC3_A24_CARRY & !_LC8_A28 - # !CBL_CNT5 & _LC3_A24_CARRY & !_LC8_A28; - --- Node name is 'CBL_CNT6' from file "sp2_acex.tdf" line 196, column 9 --- Equation name is 'CBL_CNT6', location is LC3_A21, type is buried. --- CBL_CNT6 is in Up/Down Counter Mode --- synchronous load = !_LC5_A21 -CBL_CNT6 = DFFE(( _LC7_A21 & !_LC5_A21 # _LC5_A21), !_LC8_A30, CBL_XX7, VCC, VCC); - --- Node name is 'CBL_CNT7~1' from file "sp2_acex.tdf" line 196, column 9 --- Equation name is 'CBL_CNT7~1', location is LC8_A32, type is buried. --- synthesized logic cell -!_LC8_A32 = _LC8_A32~NOT; -_LC8_A32~NOT = LCELL(!CBL_CNT7); - --- Node name is 'CBL_CNT7' from file "sp2_acex.tdf" line 196, column 9 --- Equation name is 'CBL_CNT7', location is LC6_A24, type is buried. -CBL_CNT7 = DFFE( _EQ056, !_LC8_A30, CBL_XX7, VCC, VCC); - _EQ056 = _LC4_A21 - # CBL_CNT7 & !_LC5_A24_CARRY & !_LC8_A28 - # !CBL_CNT7 & _LC5_A24_CARRY & !_LC8_A28; - --- Node name is 'CBL_CTX0' from file "sp2_acex.tdf" line 197, column 9 --- Equation name is 'CBL_CTX0', location is LC3_E36, type is buried. -CBL_CTX0 = DFFE( _EQ057, !_LC8_A30, VCC, VCC, VCC); - _EQ057 = !CBL_CTX0 & _LC2_E30 - # CBL_TAB0 & !_LC2_E30; - --- Node name is 'CBL_CTX1' from file "sp2_acex.tdf" line 197, column 9 --- Equation name is 'CBL_CTX1', location is LC2_E36, type is buried. -CBL_CTX1 = DFFE( _EQ058, !_LC8_A30, VCC, VCC, VCC); - _EQ058 = CBL_CTX0 & CBL_CTX1 & _LC2_E30 - # !CBL_CTX0 & !CBL_CTX1 & _LC2_E30 - # CBL_TAB1 & !_LC2_E30; - --- Node name is 'CBL_CTX2' from file "sp2_acex.tdf" line 197, column 9 --- Equation name is 'CBL_CTX2', location is LC8_E30, type is buried. -CBL_CTX2 = DFFE( _EQ059, !_LC8_A30, VCC, VCC, VCC); - _EQ059 = !CBL_CTX2 & _LC2_E30 & !_LC3_E30 - # CBL_CTX2 & _LC2_E30 & _LC3_E30 - # CBL_TAB2 & !_LC2_E30; - --- Node name is 'CBL_CTX3' from file "sp2_acex.tdf" line 197, column 9 --- Equation name is 'CBL_CTX3', location is LC7_E30, type is buried. -CBL_CTX3 = DFFE( _EQ060, !_LC8_A30, VCC, VCC, VCC); - _EQ060 = !CBL_CTX3 & _LC2_E30 & !_LC4_E30 - # CBL_CTX3 & _LC2_E30 & _LC4_E30 - # CBL_TAB3 & !_LC2_E30; - --- Node name is 'CBL_CTX4' from file "sp2_acex.tdf" line 197, column 9 --- Equation name is 'CBL_CTX4', location is LC6_E30, type is buried. -CBL_CTX4 = DFFE( _EQ061, !_LC8_A30, VCC, VCC, VCC); - _EQ061 = !CBL_CTX4 & _LC2_E30 & !_LC5_E30 - # CBL_CTX4 & _LC2_E30 & _LC5_E30 - # CBL_TAB4 & !_LC2_E30; - --- Node name is 'CBL_INT' from file "sp2_acex.tdf" line 1078, column 14 --- Equation name is 'CBL_INT', location is LC5_A25, type is buried. -!CBL_INT = CBL_INT~NOT; -CBL_INT~NOT = DFFE( VCC, !CBL_CNT6, _LC5_A22, VCC, VCC); - --- Node name is 'CBL_R1' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R1', location is LC6_A16, type is buried. -CBL_R1 = DFFE( _EQ062, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ062 = CBL_XX7 & _EC10_A; - --- Node name is 'CBL_R2' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R2', location is LC5_A16, type is buried. -CBL_R2 = DFFE( _EQ063, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ063 = CBL_XX7 & _EC8_A; - --- Node name is 'CBL_R3' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R3', location is LC6_A17, type is buried. -CBL_R3 = DFFE( _EQ064, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ064 = CBL_XX7 & _EC9_A; - --- Node name is 'CBL_R4' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R4', location is LC5_A17, type is buried. -CBL_R4 = DFFE( _EQ065, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ065 = CBL_XX7 & _EC1_A; - --- Node name is 'CBL_R5' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R5', location is LC4_A11, type is buried. -CBL_R5 = DFFE( _EQ066, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ066 = CBL_XX7 & _EC11_A; - --- Node name is 'CBL_R6' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R6', location is LC2_A11, type is buried. -CBL_R6 = DFFE( _EQ067, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ067 = CBL_XX7 & _EC6_A; - --- Node name is 'CBL_R7' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R7', location is LC6_A11, type is buried. -CBL_R7 = DFFE( _EQ068, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ068 = CBL_XX7 & _EC15_A; - --- Node name is 'CBL_R8' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R8', location is LC4_A18, type is buried. -CBL_R8 = DFFE( _EQ069, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ069 = !CBL_XX7 & D0 - # CBL_XX7 & _EC2_A; - --- Node name is 'CBL_R9' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R9', location is LC2_A16, type is buried. -CBL_R9 = DFFE( _EQ070, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ070 = !CBL_XX7 & D1 - # CBL_XX7 & _EC14_A; - --- Node name is 'CBL_R10' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R10', location is LC3_A18, type is buried. -CBL_R10 = DFFE( _EQ071, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ071 = !CBL_XX7 & d2 - # CBL_XX7 & _EC3_A; - --- Node name is 'CBL_R11' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R11', location is LC8_A18, type is buried. -CBL_R11 = DFFE( _EQ072, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ072 = !CBL_XX7 & d3 - # CBL_XX7 & _EC12_A; - --- Node name is 'CBL_R12' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R12', location is LC7_A16, type is buried. -CBL_R12 = DFFE( _EQ073, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ073 = !CBL_XX7 & d4 - # CBL_XX7 & _EC5_A; - --- Node name is 'CBL_R13' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R13', location is LC4_A14, type is buried. -CBL_R13 = DFFE( _EQ074, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ074 = !CBL_XX7 & d5 - # CBL_XX7 & _EC13_A; - --- Node name is 'CBL_R14' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R14', location is LC7_A11, type is buried. -CBL_R14 = DFFE( _EQ075, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ075 = !CBL_XX7 & d6 - # CBL_XX7 & _EC7_A; - --- Node name is 'CBL_R15' from file "sp2_acex.tdf" line 204, column 7 --- Equation name is 'CBL_R15', location is LC5_A14, type is buried. -!CBL_R15 = CBL_R15~NOT; -CBL_R15~NOT = DFFE( _EQ076, GLOBAL( TG42), /reset, VCC, _LC6_A14); - _EQ076 = CBL_XX7 & !_EC4_A - # !d7 & !_EC4_A - # !CBL_XX7 & !d7; - --- Node name is 'CBL_TAB0' from file "sp2_acex.tdf" line 202, column 9 --- Equation name is 'CBL_TAB0', location is LC8_A20, type is buried. -CBL_TAB0 = LCELL( _EQ077); - _EQ077 = CBL_XX1 & CBL_XX3 - # !CBL_XX1 & !CBL_XX2; - --- Node name is 'CBL_TAB1' from file "sp2_acex.tdf" line 202, column 9 --- Equation name is 'CBL_TAB1', location is LC7_A20, type is buried. -CBL_TAB1 = LCELL( _EQ078); - _EQ078 = !CBL_XX1 & !CBL_XX2 & CBL_XX3 - # !CBL_XX0 & CBL_XX2 & CBL_XX3 - # !CBL_XX0 & !CBL_XX1 & CBL_XX3; - --- Node name is 'CBL_TAB2' from file "sp2_acex.tdf" line 202, column 9 --- Equation name is 'CBL_TAB2', location is LC4_A20, type is buried. -CBL_TAB2 = LCELL( _EQ079); - _EQ079 = !CBL_XX0 & !CBL_XX1 & !CBL_XX2 & !CBL_XX3 - # !CBL_XX0 & CBL_XX1 & !CBL_XX2 & CBL_XX3 - # !CBL_XX1 & CBL_XX2 & CBL_XX3; - --- Node name is 'CBL_TAB3' from file "sp2_acex.tdf" line 202, column 9 --- Equation name is 'CBL_TAB3', location is LC4_A23, type is buried. -CBL_TAB3 = LCELL( _EQ080); - _EQ080 = !CBL_XX0 & !CBL_XX1 & !CBL_XX2 - # !CBL_XX1 & !CBL_XX2 & !CBL_XX3 - # !CBL_XX0 & !CBL_XX2 & CBL_XX3 - # CBL_XX1 & !CBL_XX2 & CBL_XX3; - --- Node name is 'CBL_TAB4' from file "sp2_acex.tdf" line 202, column 9 --- Equation name is 'CBL_TAB4', location is LC3_A20, type is buried. -CBL_TAB4 = LCELL( _EQ081); - _EQ081 = !CBL_XX1 & !CBL_XX2 & CBL_XX3; - --- Node name is 'CBL_WAE' from file "sp2_acex.tdf" line 1131, column 25 --- Equation name is 'CBL_WAE', location is LC6_C8, type is buried. -!CBL_WAE = CBL_WAE~NOT; -CBL_WAE~NOT = LCELL( _EQ082); - _EQ082 = !CBL_XX5 - # !_LC5_C8; - --- Node name is 'CBL_WA0' from file "sp2_acex.tdf" line 198, column 8 --- Equation name is 'CBL_WA0', location is LC8_A33, type is buried. -CBL_WA0 = DFFE(!CBL_WA0, !CBL_WR, _LC6_A33, VCC, !CBL_WAE); - --- Node name is 'CBL_WA1' from file "sp2_acex.tdf" line 198, column 8 --- Equation name is 'CBL_WA1', location is LC1_A33, type is buried. -CBL_WA1 = DFFE( _EQ083, !CBL_WR, _LC6_A33, VCC, !CBL_WAE); - _EQ083 = CBL_WA0 & !CBL_WA1 - # !CBL_WA0 & CBL_WA1; - --- Node name is 'CBL_WA2' from file "sp2_acex.tdf" line 198, column 8 --- Equation name is 'CBL_WA2', location is LC2_A33, type is buried. -CBL_WA2 = DFFE( _LC2_A32, !CBL_WR, _LC6_A33, VCC, !CBL_WAE); - --- Node name is 'CBL_WA3' from file "sp2_acex.tdf" line 198, column 8 --- Equation name is 'CBL_WA3', location is LC3_A33, type is buried. -CBL_WA3 = DFFE( _LC3_A32, !CBL_WR, _LC6_A33, VCC, !CBL_WAE); - --- Node name is 'CBL_WA4' from file "sp2_acex.tdf" line 198, column 8 --- Equation name is 'CBL_WA4', location is LC1_A34, type is buried. -CBL_WA4 = DFFE( _LC4_A32, !CBL_WR, _LC6_A33, VCC, !CBL_WAE); - --- Node name is 'CBL_WA5' from file "sp2_acex.tdf" line 198, column 8 --- Equation name is 'CBL_WA5', location is LC7_A33, type is buried. -CBL_WA5 = DFFE( _LC5_A32, !CBL_WR, _LC6_A33, VCC, !CBL_WAE); - --- Node name is 'CBL_WA6' from file "sp2_acex.tdf" line 198, column 8 --- Equation name is 'CBL_WA6', location is LC5_A33, type is buried. -CBL_WA6 = DFFE( _LC6_A32, !CBL_WR, _LC6_A33, VCC, !CBL_WAE); - --- Node name is 'CBL_WA7' from file "sp2_acex.tdf" line 198, column 8 --- Equation name is 'CBL_WA7', location is LC7_A32, type is buried. -CBL_WA7 = DFFE( _EQ084, !CBL_WR, _LC2_A26 & !(!CBL_INT & _LC8_A32), !(!CBL_INT & !_LC8_A32), !CBL_WAE); - _EQ084 = CBL_WA7 & !_LC6_A32_CARRY - # !CBL_WA7 & _LC6_A32_CARRY; - --- Node name is 'CBL_WR' from file "sp2_acex.tdf" line 1126, column 59 --- Equation name is 'CBL_WR', location is LC2_C8, type is buried. -!CBL_WR = CBL_WR~NOT; -CBL_WR~NOT = LCELL( _EQ085); - _EQ085 = /IOWR & !_LC1_C8 - # !_LC1_C8 & !_LC4_C8; - --- Node name is 'CBL_XX0' from file "sp2_acex.tdf" line 195, column 8 --- Equation name is 'CBL_XX0', location is LC1_A25, type is buried. -CBL_XX0 = DFFE( D0, /IOWR, VCC, VCC, _LC1_F23); - --- Node name is 'CBL_XX1' from file "sp2_acex.tdf" line 195, column 8 --- Equation name is 'CBL_XX1', location is LC2_A20, type is buried. -CBL_XX1 = DFFE( D1, /IOWR, VCC, VCC, _LC1_F23); - --- Node name is 'CBL_XX2' from file "sp2_acex.tdf" line 195, column 8 --- Equation name is 'CBL_XX2', location is LC1_A20, type is buried. -CBL_XX2 = DFFE( d2, /IOWR, VCC, VCC, _LC1_F23); - --- Node name is 'CBL_XX3' from file "sp2_acex.tdf" line 195, column 8 --- Equation name is 'CBL_XX3', location is LC5_A20, type is buried. -CBL_XX3 = DFFE( d3, /IOWR, VCC, VCC, _LC1_F23); - --- Node name is 'CBL_XX4' from file "sp2_acex.tdf" line 195, column 8 --- Equation name is 'CBL_XX4', location is LC2_A25, type is buried. -CBL_XX4 = DFFE( d4, /IOWR, VCC, VCC, _LC1_F23); - --- Node name is 'CBL_XX5' from file "sp2_acex.tdf" line 195, column 8 --- Equation name is 'CBL_XX5', location is LC2_A14, type is buried. -CBL_XX5 = DFFE( d5, /IOWR, VCC, VCC, _LC1_F23); - --- Node name is 'CBL_XX6' from file "sp2_acex.tdf" line 195, column 8 --- Equation name is 'CBL_XX6', location is LC3_A25, type is buried. -CBL_XX6 = DFFE( d6, /IOWR, VCC, VCC, _LC1_F23); - --- Node name is 'CBL_XX7' from file "sp2_acex.tdf" line 195, column 8 --- Equation name is 'CBL_XX7', location is LC6_A25, type is buried. -CBL_XX7 = DFFE( d7, /IOWR, VCC, VCC, _LC1_F23); - --- Node name is 'CLKZ1' from file "sp2_acex.tdf" line 893, column 2 --- Equation name is 'CLKZ1', type is output -CLKZ1 = _LC2_D27; - --- Node name is 'copy_sinc_h' from file "sp2_acex.tdf" line 819, column 16 --- Equation name is 'copy_sinc_h', location is LC2_F27, type is buried. -copy_sinc_h = DFFE( _EQ086, GLOBAL( TG42), VCC, VCC, VCC); - _EQ086 = _LC3_F27 & !SINC_1M; - --- Node name is 'copy_sinc_v' from file "sp2_acex.tdf" line 820, column 16 --- Equation name is 'copy_sinc_v', location is LC6_F19, type is buried. -copy_sinc_v = DFFE( _EQ087, GLOBAL( TG42), VCC, VCC, VCC); - _EQ087 = _LC4_F19 & !SINC_2M; - --- Node name is 'CS_CASH' from file "sp2_acex.tdf" line 609, column 2 --- Equation name is 'CS_CASH', type is output -CS_CASH = _LC2_C26; - --- Node name is 'CS_CASHT' from file "sp2_acex.tdf" line 605, column 13 --- Equation name is 'CS_CASHT', location is LC8_C23, type is buried. -!CS_CASHT = CS_CASHT~NOT; -CS_CASHT~NOT = DFFE( _EQ088, GLOBAL(!/mr), _LC4_C23, VCC, VCC); - _EQ088 = !PRE_CASH & PRE_ROM & /rf; - --- Node name is 'CS_ISA' from file "sp2_acex.tdf" line 603, column 12 --- Equation name is 'CS_ISA', location is LC5_C33, type is buried. -!CS_ISA = CS_ISA~NOT; -CS_ISA~NOT = DFFE( _EQ089, GLOBAL(!/mr), _LC1_C33, VCC, VCC); - _EQ089 = !PRE_ISA & /rf; - --- Node name is 'cs_rom' from file "sp2_acex.tdf" line 607, column 2 --- Equation name is 'cs_rom', type is output -cs_rom = CS_ROMT; - --- Node name is 'CS_ROMT' from file "sp2_acex.tdf" line 604, column 13 --- Equation name is 'CS_ROMT', location is LC5_C27, type is buried. -!CS_ROMT = CS_ROMT~NOT; -CS_ROMT~NOT = DFFE( _EQ090, GLOBAL(!/mr), _LC2_C33, VCC, VCC); - _EQ090 = PRE_CASH & !PRE_ROM & /rf; - --- Node name is 'DAC_BCK' from file "sp2_acex.tdf" line 1058, column 2 --- Equation name is 'DAC_BCK', type is output -DAC_BCK = _LC1_A3; - --- Node name is 'DAC_DATA' from file "sp2_acex.tdf" line 1052, column 2 --- Equation name is 'DAC_DATA', type is output -DAC_DATA = _LC6_A1; - --- Node name is 'DAC_WS' from file "sp2_acex.tdf" line 1057, column 2 --- Equation name is 'DAC_WS', type is output -DAC_WS = _LC1_E3; - --- Node name is 'DD0' from file "sp2_acex.tdf" line 409, column 18 --- Equation name is 'DD0', location is LC5_D36, type is buried. -DD0 = LCELL( _EQ091); - _EQ091 = !/io & PDD0 - # /io & _LC4_D30; - --- Node name is 'DD1' from file "sp2_acex.tdf" line 409, column 18 --- Equation name is 'DD1', location is LC7_D36, type is buried. -DD1 = LCELL( _EQ092); - _EQ092 = !/io & PDD1 - # /io & _LC3_D36; - --- Node name is 'DD2' from file "sp2_acex.tdf" line 409, column 18 --- Equation name is 'DD2', location is LC6_D33, type is buried. -DD2 = LCELL( _EQ093); - _EQ093 = !/io & PDD2 - # /io & _LC3_D30; - --- Node name is 'DD3' from file "sp2_acex.tdf" line 409, column 18 --- Equation name is 'DD3', location is LC3_D33, type is buried. -DD3 = LCELL( _EQ094); - _EQ094 = !/io & PDD3 - # /io & _LC7_D30; - --- Node name is 'DD4' from file "sp2_acex.tdf" line 409, column 18 --- Equation name is 'DD4', location is LC1_D32, type is buried. -DD4 = LCELL( _EQ095); - _EQ095 = !/io & PDD4 - # /io & _LC6_D30; - --- Node name is 'DD5' from file "sp2_acex.tdf" line 409, column 18 --- Equation name is 'DD5', location is LC2_A31, type is buried. -DD5 = LCELL( _EQ096); - _EQ096 = !/io & PDD5 - # /io & _LC8_D34; - --- Node name is 'DD6' from file "sp2_acex.tdf" line 409, column 18 --- Equation name is 'DD6', location is LC1_D29, type is buried. -DD6 = LCELL( _EQ097); - _EQ097 = !/io & PDD6 - # /io & _LC7_D34; - --- Node name is 'DD7' from file "sp2_acex.tdf" line 409, column 18 --- Equation name is 'DD7', location is LC2_D29, type is buried. -DD7 = LCELL( _EQ098); - _EQ098 = !/io & PDD7 - # /io & _LC6_D34; - --- Node name is 'dos' from file "sp2_acex.tdf" line 842, column 9 --- Equation name is 'dos', location is LC5_C10, type is buried. -!dos = dos~NOT; -dos~NOT = DFFE( _EQ099, !_LC4_C10, /reset, VCC, VCC); - _EQ099 = !A14 & !A15 & !dos - # !A14 & !A15 & _LC7_C10; - --- Node name is 'D_OUT' from file "sp2_acex.tdf" line 413, column 68 --- Equation name is 'D_OUT', location is LC1_C25, type is buried. -D_OUT = LCELL( _EQ100); - _EQ100 = !_LC6_C25 - # !/IORD & !_LC5_C25; - --- Node name is 'D0' from file "sp2_acex.tdf" line 423, column 4 --- Equation name is 'D0', type is bidir -D0 = TRI(DD0, D_OUT); - --- Node name is 'D1' from file "sp2_acex.tdf" line 423, column 4 --- Equation name is 'D1', type is bidir -D1 = TRI(DD1, D_OUT); - --- Node name is 'd2' from file "sp2_acex.tdf" line 423, column 4 --- Equation name is 'd2', type is bidir -d2 = TRI(DD2, D_OUT); - --- Node name is 'd3' from file "sp2_acex.tdf" line 423, column 4 --- Equation name is 'd3', type is bidir -d3 = TRI(DD3, D_OUT); - --- Node name is 'd4' from file "sp2_acex.tdf" line 423, column 4 --- Equation name is 'd4', type is bidir -d4 = TRI(DD4, D_OUT); - --- Node name is 'd5' from file "sp2_acex.tdf" line 423, column 4 --- Equation name is 'd5', type is bidir -d5 = TRI(DD5, D_OUT); - --- Node name is 'd6' from file "sp2_acex.tdf" line 423, column 4 --- Equation name is 'd6', type is bidir -d6 = TRI(DD6, D_OUT); - --- Node name is 'd7' from file "sp2_acex.tdf" line 423, column 4 --- Equation name is 'd7', type is bidir -d7 = TRI(DD7, D_OUT); - --- Node name is 'glisser' from file "sp2_acex.tdf" line 975, column 13 --- Equation name is 'glisser', location is LC3_C18, type is buried. -glisser = LCELL( _EQ101); - _EQ101 = _EC14_C & _LC7_D18 & VIDEO_PG; - --- Node name is 'hddr0' from file "sp2_acex.tdf" line 181, column 6 --- Equation name is 'hddr0', location is LC7_D9, type is buried. -hddr0 = DFFE( _EQ102, _LC8_D9, VCC, VCC, _LC8_D14); - _EQ102 = _LC1_D9 & md8 - # D0 & !_LC1_D9; - --- Node name is 'hddr1' from file "sp2_acex.tdf" line 181, column 6 --- Equation name is 'hddr1', location is LC1_D7, type is buried. -hddr1 = DFFE( _EQ103, _LC8_D9, VCC, VCC, _LC8_D14); - _EQ103 = _LC1_D9 & md9 - # D1 & !_LC1_D9; - --- Node name is 'hddr2' from file "sp2_acex.tdf" line 181, column 6 --- Equation name is 'hddr2', location is LC8_D7, type is buried. -hddr2 = DFFE( _EQ104, _LC8_D9, VCC, VCC, _LC8_D14); - _EQ104 = _LC1_D9 & md10 - # d2 & !_LC1_D9; - --- Node name is 'hddr3' from file "sp2_acex.tdf" line 181, column 6 --- Equation name is 'hddr3', location is LC3_D9, type is buried. -hddr3 = DFFE( _EQ105, _LC8_D9, VCC, VCC, _LC8_D14); - _EQ105 = _LC1_D9 & md11 - # d3 & !_LC1_D9; - --- Node name is 'hddr4' from file "sp2_acex.tdf" line 181, column 6 --- Equation name is 'hddr4', location is LC6_D9, type is buried. -hddr4 = DFFE( _EQ106, _LC8_D9, VCC, VCC, _LC8_D14); - _EQ106 = _LC1_D9 & md12 - # d4 & !_LC1_D9; - --- Node name is 'hddr5' from file "sp2_acex.tdf" line 181, column 6 --- Equation name is 'hddr5', location is LC2_D9, type is buried. -hddr5 = DFFE( _EQ107, _LC8_D9, VCC, VCC, _LC8_D14); - _EQ107 = _LC1_D9 & md13 - # d5 & !_LC1_D9; - --- Node name is 'hddr6' from file "sp2_acex.tdf" line 181, column 6 --- Equation name is 'hddr6', location is LC5_D9, type is buried. -hddr6 = DFFE( _EQ108, _LC8_D9, VCC, VCC, _LC8_D14); - _EQ108 = _LC1_D9 & md14 - # d6 & !_LC1_D9; - --- Node name is 'hddr7' from file "sp2_acex.tdf" line 181, column 6 --- Equation name is 'hddr7', location is LC4_D9, type is buried. -hddr7 = DFFE( _EQ109, _LC8_D9, VCC, VCC, _LC8_D14); - _EQ109 = _LC1_D9 & md15 - # d7 & !_LC1_D9; - --- Node name is 'HOLD0' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD0', location is LC4_F26, type is buried. -!HOLD0 = HOLD0~NOT; -HOLD0~NOT = DFFE(!D0, /IOWR, _LC8_F32, VCC, _LC4_F31); - --- Node name is 'HOLD1' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD1', location is LC5_F33, type is buried. -!HOLD1 = HOLD1~NOT; -HOLD1~NOT = DFFE(!D1, /IOWR, _LC8_F32, VCC, _LC4_F31); - --- Node name is 'HOLD2' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD2', location is LC6_F26, type is buried. -!HOLD2 = HOLD2~NOT; -HOLD2~NOT = DFFE(!d2, /IOWR, _LC8_F32, VCC, _LC4_F31); - --- Node name is 'HOLD3' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD3', location is LC3_F26, type is buried. -HOLD3 = DFFE( d3, /IOWR, _LC8_F32, VCC, _LC4_F31); - --- Node name is 'HOLD4' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD4', location is LC1_F33, type is buried. -!HOLD4 = HOLD4~NOT; -HOLD4~NOT = DFFE(!d4, /IOWR, _LC8_F32, VCC, _LC4_F31); - --- Node name is 'HOLD5~1' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD5~1', location is LC2_F33, type is buried. --- synthesized logic cell -!_LC2_F33 = _LC2_F33~NOT; -_LC2_F33~NOT = LCELL( HOLD5); - --- Node name is 'HOLD5' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD5', location is LC6_F33, type is buried. -!HOLD5 = HOLD5~NOT; -HOLD5~NOT = DFFE(!d5, /IOWR, _LC8_F32, VCC, _LC4_F31); - --- Node name is 'HOLD6~1' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD6~1', location is LC4_F33, type is buried. --- synthesized logic cell -!_LC4_F33 = _LC4_F33~NOT; -_LC4_F33~NOT = LCELL( HOLD6); - --- Node name is 'HOLD6' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD6', location is LC8_F33, type is buried. -!HOLD6 = HOLD6~NOT; -HOLD6~NOT = DFFE(!d6, /IOWR, _LC8_F32, VCC, _LC4_F31); - --- Node name is 'HOLD7' from file "sp2_acex.tdf" line 283, column 6 --- Equation name is 'HOLD7', location is LC3_F33, type is buried. -HOLD7 = DFFE( d7, /IOWR, _LC8_F32, VCC, _LC4_F31); - --- Node name is 'INT_X' from file "sp2_acex.tdf" line 750, column 6 --- Equation name is 'INT_X', location is LC4_A25, type is buried. -!INT_X = INT_X~NOT; -INT_X~NOT = LCELL( _EQ110); - _EQ110 = CBL_INT & _LC7_A22; - --- Node name is 'ISA_A0' from file "sp2_acex.tdf" line 620, column 25 --- Equation name is 'ISA_A0', location is LC1_C26, type is buried. -ISA_A0 = LCELL( _EQ111); - _EQ111 = ISA_PORT1 & PRE_CASH & PRE_ROM - # PRE_CASH & !PRE_ROM & ROM_RG0 - # !PRE_CASH & PRE_ROM & ROM_RG0; - --- Node name is 'ISA_A1' from file "sp2_acex.tdf" line 620, column 25 --- Equation name is 'ISA_A1', location is LC1_C23, type is buried. -ISA_A1 = LCELL( _EQ112); - _EQ112 = ISA_PORT2 & PRE_CASH & PRE_ROM - # PRE_CASH & !PRE_ROM & ROM_RG1 - # !PRE_CASH & PRE_ROM & ROM_RG1; - --- Node name is 'ISA_A2' from file "sp2_acex.tdf" line 619, column 25 --- Equation name is 'ISA_A2', location is LC2_C23, type is buried. -ISA_A2 = LCELL( _EQ113); - _EQ113 = PRE_CASH & !PRE_ROM & ROM_RG2 - # !PRE_CASH & PRE_ROM; - --- Node name is 'ISA_A3' from file "sp2_acex.tdf" line 620, column 25 --- Equation name is 'ISA_A3', location is LC2_C25, type is buried. -ISA_A3 = LCELL( _EQ114); - _EQ114 = !PRE_CASH & !PRE_ROM - # _LC5_F26 & !PRE_ROM - # PRE_CASH & !PRE_ISA & PRE_ROM; - --- Node name is 'ISA_PORT1' from file "sp2_acex.tdf" line 288, column 10 --- Equation name is 'ISA_PORT1', location is LC4_C26, type is buried. -ISA_PORT1 = DFFE( D1, /IOWR, VCC, VCC, _LC6_C30); - --- Node name is 'ISA_PORT2' from file "sp2_acex.tdf" line 288, column 10 --- Equation name is 'ISA_PORT2', location is LC3_C26, type is buried. -ISA_PORT2 = DFFE( d2, /IOWR, VCC, VCC, _LC6_C30); - --- Node name is 'ISA_PORT4' from file "sp2_acex.tdf" line 288, column 10 --- Equation name is 'ISA_PORT4', location is LC3_C9, type is buried. -ISA_PORT4 = DFFE( d4, /IOWR, VCC, VCC, _LC6_C30); - --- Node name is 'ISA_PORT5' from file "sp2_acex.tdf" line 288, column 10 --- Equation name is 'ISA_PORT5', location is LC4_C9, type is buried. -ISA_PORT5 = DFFE( d5, /IOWR, VCC, VCC, _LC6_C30); - --- Node name is 'ISA_PORT6' from file "sp2_acex.tdf" line 288, column 10 --- Equation name is 'ISA_PORT6', location is LC6_C9, type is buried. -ISA_PORT6 = DFFE( d6, /IOWR, VCC, VCC, _LC6_C30); - --- Node name is 'ISA_PORT7' from file "sp2_acex.tdf" line 288, column 10 --- Equation name is 'ISA_PORT7', location is LC7_C9, type is buried. -ISA_PORT7 = DFFE( d7, /IOWR, VCC, VCC, _LC6_C30); - --- Node name is 'kbd_cc' from file "sp2_acex.tdf" line 791, column 12 --- Equation name is 'kbd_cc', location is LC8_D28, type is buried. -kbd_cc = DFFE( XA0, T_RDXA, VCC, VCC, !_LC6_D28); - --- Node name is 'kbd_dd' from file "sp2_acex.tdf" line 790, column 12 --- Equation name is 'kbd_dd', location is LC5_D28, type is buried. -kbd_dd = DFFE( XA1, T_RDXA, VCC, VCC, !_LC6_D28); - --- Node name is 'KEMPS0' from file "sp2_acex.tdf" line 256, column 7 --- Equation name is 'KEMPS0', location is LC4_B22, type is buried. -KEMPS0 = LCELL( _EQ115); - _EQ115 = _LC2_B22 - # A8 & !A10 & _LC8_B22; - --- Node name is 'KEMPS1' from file "sp2_acex.tdf" line 256, column 7 --- Equation name is 'KEMPS1', location is LC2_B25, type is buried. -KEMPS1 = LCELL( _EQ116); - _EQ116 = _LC1_B25 - # A8 & !A10 & _LC4_B25; - --- Node name is 'KEMPS2' from file "sp2_acex.tdf" line 256, column 7 --- Equation name is 'KEMPS2', location is LC2_B32, type is buried. -KEMPS2 = LCELL( _EQ117); - _EQ117 = !A8 - # A10 & !_LC3_B32 - # !A10 & _LC7_B32; - --- Node name is 'KEMPS3' from file "sp2_acex.tdf" line 256, column 7 --- Equation name is 'KEMPS3', location is LC4_B24, type is buried. -KEMPS3 = LCELL( _EQ118); - _EQ118 = !A8 - # A10 & !_LC1_B22 - # !A10 & _LC6_B24; - --- Node name is 'KEMPS4' from file "sp2_acex.tdf" line 256, column 7 --- Equation name is 'KEMPS4', location is LC1_B32, type is buried. -KEMPS4 = LCELL( _EQ119); - _EQ119 = !A8 - # A10 & !_LC8_B32 - # !A10 & _LC6_B32; - --- Node name is 'KEMPS5' from file "sp2_acex.tdf" line 256, column 7 --- Equation name is 'KEMPS5', location is LC7_B24, type is buried. -KEMPS5 = LCELL( _EQ120); - _EQ120 = !A8 - # A10 & !_LC3_B28 - # !A10 & _LC5_B24; - --- Node name is 'KEMPS6' from file "sp2_acex.tdf" line 256, column 7 --- Equation name is 'KEMPS6', location is LC3_B24, type is buried. -KEMPS6 = LCELL( _EQ121); - _EQ121 = !A8 - # A10 & !_LC5_B28 - # !A10 & _LC2_B24; - --- Node name is 'KEMPS7' from file "sp2_acex.tdf" line 256, column 7 --- Equation name is 'KEMPS7', location is LC8_B25, type is buried. -KEMPS7 = LCELL( _EQ122); - _EQ122 = !A8 - # A10 & !_LC8_B31 - # !A10 & _LC8_B35; - --- Node name is 'KEY_IO' from file "sp2_acex.tdf" line 530, column 12 --- Equation name is 'KEY_IO', location is LC2_A1, type is buried. -KEY_IO = DFFE( _EQ123, GLOBAL( TG42), VCC, VCC, _LC2_F32); - _EQ123 = /io - # !/m1; - --- Node name is 'KEY/KEMS0' from file "sp2_acex.tdf" line 258, column 10 --- Equation name is 'KEY/KEMS0', location is LC5_B22, type is buried. -KEY/KEMS0 = LCELL( _EQ124); - _EQ124 = _EC6_C & KEMPS0 - # !_EC6_C & _LC3_B12; - --- Node name is 'KEY/KEMS1' from file "sp2_acex.tdf" line 258, column 10 --- Equation name is 'KEY/KEMS1', location is LC5_B25, type is buried. -KEY/KEMS1 = LCELL( _EQ125); - _EQ125 = _EC6_C & KEMPS1 - # !_EC6_C & _LC1_B12; - --- Node name is 'KEY/KEMS2' from file "sp2_acex.tdf" line 258, column 10 --- Equation name is 'KEY/KEMS2', location is LC4_B32, type is buried. -KEY/KEMS2 = LCELL( _EQ126); - _EQ126 = _EC6_C & KEMPS2 - # !_EC6_C & _LC8_B12; - --- Node name is 'KEY/KEMS3' from file "sp2_acex.tdf" line 258, column 10 --- Equation name is 'KEY/KEMS3', location is LC1_B24, type is buried. -KEY/KEMS3 = LCELL( _EQ127); - _EQ127 = _EC6_C & KEMPS3 - # !_EC6_C & _LC4_B12; - --- Node name is 'KEY/KEMS4' from file "sp2_acex.tdf" line 258, column 10 --- Equation name is 'KEY/KEMS4', location is LC4_B36, type is buried. -KEY/KEMS4 = LCELL( _EQ128); - _EQ128 = _EC6_C & KEMPS4 - # !_EC6_C & _LC2_B12; - --- Node name is 'KEY/KEMS5' from file "sp2_acex.tdf" line 258, column 10 --- Equation name is 'KEY/KEMS5', location is LC8_A26, type is buried. -KEY/KEMS5 = LCELL( _EQ129); - _EQ129 = _EC6_C & KEMPS5 - # !_EC6_C & _LC5_A26; - --- Node name is 'KEY/KEMS6' from file "sp2_acex.tdf" line 258, column 10 --- Equation name is 'KEY/KEMS6', location is LC5_D29, type is buried. -KEY/KEMS6 = LCELL( _EQ130); - _EQ130 = _EC6_C & KEMPS6 - # !_EC6_C & TAPE_IN; - --- Node name is 'KEY/KEMS7' from file "sp2_acex.tdf" line 258, column 10 --- Equation name is 'KEY/KEMS7', location is LC8_A31, type is buried. -KEY/KEMS7 = LCELL( _EQ131); - _EQ131 = _EC6_C & KEMPS7 - # !_EC6_C & _LC3_A31; - --- Node name is 'ma0' = '|dcp:DECODE|MA_0' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma0', type is output -ma0 = _IOC_166; - --- Node name is '|dcp:DECODE|MA_0' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_166', type is buried -_IOC_166 = DFFE( _LC2_C7, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma1' = '|dcp:DECODE|MA_1' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma1', type is output -ma1 = _IOC_167; - --- Node name is '|dcp:DECODE|MA_1' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_167', type is buried -_IOC_167 = DFFE( _LC3_C7, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma2' = '|dcp:DECODE|MA_2' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma2', type is output -ma2 = _IOC_168; - --- Node name is '|dcp:DECODE|MA_2' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_168', type is buried -_IOC_168 = DFFE( _LC1_C10, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma3' = '|dcp:DECODE|MA_3' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma3', type is output -ma3 = _IOC_170; - --- Node name is '|dcp:DECODE|MA_3' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_170', type is buried -_IOC_170 = DFFE( _LC1_C11, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma4' = '|dcp:DECODE|MA_4' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma4', type is output -ma4 = _IOC_172; - --- Node name is '|dcp:DECODE|MA_4' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_172', type is buried -_IOC_172 = DFFE( _LC1_C12, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma5' = '|dcp:DECODE|MA_5' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma5', type is output -ma5 = _IOC_174; - --- Node name is '|dcp:DECODE|MA_5' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_174', type is buried -_IOC_174 = DFFE( _LC2_C13, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma6' = '|dcp:DECODE|MA_6' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma6', type is output -ma6 = _IOC_175; - --- Node name is '|dcp:DECODE|MA_6' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_175', type is buried -_IOC_175 = DFFE( _LC1_C13, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma7' = '|dcp:DECODE|MA_7' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma7', type is output -ma7 = _IOC_197; - --- Node name is '|dcp:DECODE|MA_7' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_197', type is buried -_IOC_197 = DFFE( _LC3_C28, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma8' = '|dcp:DECODE|MA_8' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma8', type is output -ma8 = _IOC_202; - --- Node name is '|dcp:DECODE|MA_8' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_202', type is buried -_IOC_202 = DFFE( _LC3_C32, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma9' = '|dcp:DECODE|MA_9' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma9', type is output -ma9 = _IOC_203; - --- Node name is '|dcp:DECODE|MA_9' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_203', type is buried -_IOC_203 = DFFE( _LC6_C32, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma10' = '|dcp:DECODE|MA_10' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma10', type is output -ma10 = _IOC_177; - --- Node name is '|dcp:DECODE|MA_10' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_177', type is buried -_IOC_177 = DFFE( _LC2_C16, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma11' = '|dcp:DECODE|MA_11' from file "dcp.tdf" line 152, column 5 --- Equation name is 'ma11', type is output -ma11 = _IOC_199; - --- Node name is '|dcp:DECODE|MA_11' from file "dcp.tdf" line 152, column 5 --- Equation name is '_IOC_199', type is buried -_IOC_199 = DFFE( _LC1_C30, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is 'ma12' from file "sp2_acex.tdf" line 891, column 4 --- Equation name is 'ma12', type is output -ma12 = GND; - --- Node name is 'ma13' from file "sp2_acex.tdf" line 891, column 4 --- Equation name is 'ma13', type is output -ma13 = INT_X; - --- Node name is 'ma14' from file "sp2_acex.tdf" line 891, column 4 --- Equation name is 'ma14', type is output -ma14 = !_LC6_D24; - --- Node name is 'MDP0' from file "sp2_acex.tdf" line 173, column 5 --- Equation name is 'MDP0', location is LC6_D11, type is buried. -MDP0 = DFFE( _EQ132, _LC4_D3, VCC, VCC, VCC); - _EQ132 = _LC4_D11 - # _EC6_C & md8 - # _LC7_D11; - --- Node name is 'MDP1' from file "sp2_acex.tdf" line 173, column 5 --- Equation name is 'MDP1', location is LC5_D11, type is buried. -MDP1 = DFFE( _EQ133, _LC4_D3, VCC, VCC, VCC); - _EQ133 = _LC3_D11 - # _EC6_C & md9 - # _LC8_D11; - --- Node name is 'MDP2' from file "sp2_acex.tdf" line 173, column 5 --- Equation name is 'MDP2', location is LC7_D15, type is buried. -MDP2 = DFFE( _EQ134, _LC4_D3, VCC, VCC, VCC); - _EQ134 = _LC3_D15 - # _EC6_C & md10 - # _LC5_D15; - --- Node name is 'MDP3' from file "sp2_acex.tdf" line 173, column 5 --- Equation name is 'MDP3', location is LC6_D15, type is buried. -MDP3 = DFFE( _EQ135, _LC4_D3, VCC, VCC, VCC); - _EQ135 = _LC8_D15 - # _EC6_C & md11 - # _LC4_D15; - --- Node name is 'MDP4' from file "sp2_acex.tdf" line 173, column 5 --- Equation name is 'MDP4', location is LC3_D4, type is buried. -MDP4 = DFFE( _EQ136, _LC4_D3, VCC, VCC, VCC); - _EQ136 = _LC1_D4 - # _EC6_C & md12 - # _LC6_D4; - --- Node name is 'MDP5' from file "sp2_acex.tdf" line 173, column 5 --- Equation name is 'MDP5', location is LC1_D11, type is buried. -MDP5 = DFFE( _EQ137, _LC4_D3, VCC, VCC, VCC); - _EQ137 = _LC2_D15 - # _EC6_C & md13 - # _LC2_D11; - --- Node name is 'MDP6' from file "sp2_acex.tdf" line 173, column 5 --- Equation name is 'MDP6', location is LC2_D14, type is buried. -MDP6 = DFFE( _EQ138, _LC4_D3, VCC, VCC, VCC); - _EQ138 = _LC1_D14 - # _EC6_C & md14 - # _LC4_D14; - --- Node name is 'MDP7' from file "sp2_acex.tdf" line 173, column 5 --- Equation name is 'MDP7', location is LC7_D4, type is buried. -MDP7 = DFFE( _EQ139, _LC4_D3, VCC, VCC, VCC); - _EQ139 = _LC2_D4 - # _EC6_C & md15 - # _LC8_D4; - --- Node name is 'md0' from file "sp2_acex.tdf" line 428, column 5 --- Equation name is 'md0', type is bidir -md0 = TRI(_LC2_D28, _LC1_C1); - --- Node name is 'md1' from file "sp2_acex.tdf" line 428, column 5 --- Equation name is 'md1', type is bidir -md1 = TRI(_LC5_D25, _LC1_C1); - --- Node name is 'md2' from file "sp2_acex.tdf" line 428, column 5 --- Equation name is 'md2', type is bidir -md2 = TRI(_LC2_D21, _LC1_C1); - --- Node name is 'md3' from file "sp2_acex.tdf" line 428, column 5 --- Equation name is 'md3', type is bidir -md3 = TRI(_LC8_D19, _LC1_C1); - --- Node name is 'md4' from file "sp2_acex.tdf" line 428, column 5 --- Equation name is 'md4', type is bidir -md4 = TRI(_LC8_D5, _LC1_C1); - --- Node name is 'md5' from file "sp2_acex.tdf" line 428, column 5 --- Equation name is 'md5', type is bidir -md5 = TRI(_LC4_D5, _LC1_C1); - --- Node name is 'md6' from file "sp2_acex.tdf" line 428, column 5 --- Equation name is 'md6', type is bidir -md6 = TRI(_LC3_D5, _LC1_C1); - --- Node name is 'md7' from file "sp2_acex.tdf" line 428, column 5 --- Equation name is 'md7', type is bidir -md7 = TRI(_LC6_D3, _LC1_C1); - --- Node name is 'md8' from file "sp2_acex.tdf" line 429, column 5 --- Equation name is 'md8', type is bidir -md8 = TRI(_LC3_A1, _LC1_C1); - --- Node name is 'md9' from file "sp2_acex.tdf" line 429, column 5 --- Equation name is 'md9', type is bidir -md9 = TRI(_LC3_D35, _LC1_C1); - --- Node name is 'md10' from file "sp2_acex.tdf" line 429, column 5 --- Equation name is 'md10', type is bidir -md10 = TRI(_LC5_D33, _LC1_C1); - --- Node name is 'md11' from file "sp2_acex.tdf" line 429, column 5 --- Equation name is 'md11', type is bidir -md11 = TRI(_LC3_D28, _LC1_C1); - --- Node name is 'md12' from file "sp2_acex.tdf" line 429, column 5 --- Equation name is 'md12', type is bidir -md12 = TRI(_LC5_D24, _LC1_C1); - --- Node name is 'md13' from file "sp2_acex.tdf" line 429, column 5 --- Equation name is 'md13', type is bidir -md13 = TRI(_LC1_D21, _LC1_C1); - --- Node name is 'md14' from file "sp2_acex.tdf" line 429, column 5 --- Equation name is 'md14', type is bidir -md14 = TRI(_LC6_D19, _LC1_C1); - --- Node name is 'md15' from file "sp2_acex.tdf" line 429, column 5 --- Equation name is 'md15', type is bidir -md15 = TRI(_LC1_D17, _LC1_C1); - --- Node name is 'mouse_d' from file "sp2_acex.tdf" line 793, column 16 --- Equation name is 'mouse_d', location is LC1_D28, type is buried. -mouse_d = DFFE( XA3, T_RDXA, VCC, VCC, !_LC6_D28); - --- Node name is 'PDD0' from file "sp2_acex.tdf" line 176, column 5 --- Equation name is 'PDD0', location is LC3_D26, type is buried. -PDD0 = LCELL( _EQ140); - _EQ140 = AY/PORTS0 & !_EC3_C & _EC9_C - # _LC5_D26; - --- Node name is 'PDD1' from file "sp2_acex.tdf" line 176, column 5 --- Equation name is 'PDD1', location is LC8_D36, type is buried. -PDD1 = LCELL( _EQ141); - _EQ141 = AY/PORTS1 & !_EC3_C & _EC9_C - # _LC2_D36; - --- Node name is 'PDD2' from file "sp2_acex.tdf" line 176, column 5 --- Equation name is 'PDD2', location is LC5_D23, type is buried. -PDD2 = LCELL( _EQ142); - _EQ142 = AY/PORTS2 & !_EC3_C & _EC9_C - # _LC4_D23; - --- Node name is 'PDD3' from file "sp2_acex.tdf" line 176, column 5 --- Equation name is 'PDD3', location is LC5_D32, type is buried. -PDD3 = LCELL( _EQ143); - _EQ143 = AY/PORTS3 & !_EC3_C & _EC9_C - # _LC2_D32; - --- Node name is 'PDD4' from file "sp2_acex.tdf" line 176, column 5 --- Equation name is 'PDD4', location is LC7_D32, type is buried. -PDD4 = LCELL( _EQ144); - _EQ144 = AY/PORTS4 & !_EC3_C & _EC9_C - # _LC3_D32; - --- Node name is 'PDD5' from file "sp2_acex.tdf" line 176, column 5 --- Equation name is 'PDD5', location is LC1_A26, type is buried. -PDD5 = LCELL( _EQ145); - _EQ145 = AY/PORTS5 & !_EC3_C & _EC9_C - # _LC4_A26; - --- Node name is 'PDD6' from file "sp2_acex.tdf" line 176, column 5 --- Equation name is 'PDD6', location is LC7_D29, type is buried. -PDD6 = LCELL( _EQ146); - _EQ146 = AY/PORTS6 & !_EC3_C & _EC9_C - # _LC4_D29; - --- Node name is 'PDD7' from file "sp2_acex.tdf" line 176, column 5 --- Equation name is 'PDD7', location is LC1_A31, type is buried. -PDD7 = LCELL( _EQ147); - _EQ147 = AY/PORTS7 & !_EC3_C & _EC9_C - # _LC6_A31; - --- Node name is 'PRE_CASH' from file "sp2_acex.tdf" line 588, column 13 --- Equation name is 'PRE_CASH', location is LC3_C25, type is buried. -PRE_CASH = LCELL( _EQ148); - _EQ148 = !CASH_ON - # A15 - # A14; - --- Node name is 'PRE_ISA' from file "sp2_acex.tdf" line 586, column 13 --- Equation name is 'PRE_ISA', location is LC8_C9, type is buried. -PRE_ISA = LCELL( _EQ149); - _EQ149 = !_LC3_D12 - # !_LC2_C9 - # !A15 - # !A14; - --- Node name is 'PRE_ROM' from file "sp2_acex.tdf" line 587, column 13 --- Equation name is 'PRE_ROM', location is LC4_C25, type is buried. -PRE_ROM = LCELL( _EQ150); - _EQ150 = /SYS - # CASH_ON - # A15 - # A14; - --- Node name is 'RASX_0' from file "sp2_acex.tdf" line 856, column 35 --- Equation name is 'RASX_0', location is LC2_A35, type is buried. -RASX_0 = LCELL( _LC6_F32); - --- Node name is 'RASX_1' from file "sp2_acex.tdf" line 856, column 17 --- Equation name is 'RASX_1', location is LC2_A34, type is buried. -RASX_1 = LCELL( _LC6_F32); - --- Node name is 'RAS_0' from file "sp2_acex.tdf" line 858, column 6 --- Equation name is 'RAS_0', type is output -RAS_0 = RASX_0; - --- Node name is 'RAS_1' from file "sp2_acex.tdf" line 858, column 6 --- Equation name is 'RAS_1', type is output -RAS_1 = RASX_1; - --- Node name is 'ra14' from file "sp2_acex.tdf" line 622, column 4 --- Equation name is 'ra14', type is output -ra14 = ISA_A0; - --- Node name is 'ra15' from file "sp2_acex.tdf" line 622, column 4 --- Equation name is 'ra15', type is output -ra15 = ISA_A1; - --- Node name is 'ra16' from file "sp2_acex.tdf" line 622, column 4 --- Equation name is 'ra16', type is output -ra16 = ISA_A2; - --- Node name is 'ra17' from file "sp2_acex.tdf" line 622, column 4 --- Equation name is 'ra17', type is output -ra17 = ISA_A3; - --- Node name is 'RD_KMPS' from file "sp2_acex.tdf" line 723, column 2 --- Equation name is 'RD_KMPS', type is output -RD_KMPS = _LC5_A31; - --- Node name is 'RDXA' = ':1439' from file "sp2_acex.tdf" line 764, column 10 --- Equation name is 'RDXA', type is output -RDXA = _IOC_173; - --- Node name is ':1439' from file "sp2_acex.tdf" line 764, column 10 --- Equation name is '_IOC_173', type is buried -_IOC_173 = DFFE(!_LC1_E14, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'RGMOD0' from file "sp2_acex.tdf" line 179, column 7 --- Equation name is 'RGMOD0', location is LC7_F28, type is buried. -RGMOD0 = DFFE( D0, /IOWR, /reset, VCC, _LC6_F28); - --- Node name is 'ROM_RG0' from file "sp2_acex.tdf" line 240, column 8 --- Equation name is 'ROM_RG0', location is LC8_C26, type is buried. -ROM_RG0 = DFFE( D0, /IOWR, /reset, VCC, _LC8_C29); - --- Node name is 'ROM_RG1' from file "sp2_acex.tdf" line 240, column 8 --- Equation name is 'ROM_RG1', location is LC7_C26, type is buried. -ROM_RG1 = DFFE( D1, /IOWR, /reset, VCC, _LC8_C29); - --- Node name is 'ROM_RG2' from file "sp2_acex.tdf" line 240, column 8 --- Equation name is 'ROM_RG2', location is LC5_C26, type is buried. -ROM_RG2 = DFFE( d2, /IOWR, /reset, VCC, _LC8_C29); - --- Node name is 'ROM_RG3' from file "sp2_acex.tdf" line 240, column 8 --- Equation name is 'ROM_RG3', location is LC6_F27, type is buried. -ROM_RG3 = DFFE( d3, /IOWR, /reset, VCC, _LC8_C29); - --- Node name is 'ROM_RG4' from file "sp2_acex.tdf" line 240, column 8 --- Equation name is 'ROM_RG4', location is LC5_F27, type is buried. -ROM_RG4 = DFFE( d4, /IOWR, /reset, VCC, _LC8_C29); - --- Node name is 'SINC_HOLD0' from file "sp2_acex.tdf" line 281, column 11 --- Equation name is 'SINC_HOLD0', location is LC5_F36, type is buried. -SINC_HOLD0 = DFFE( _EQ151, _LC7_A29, VCC, VCC, VCC); - _EQ151 = !SINC_1 & !SINC_1M - # !SINC_HOLD0 & !SINC_1 - # HOLD0 & SINC_1; - --- Node name is 'SINC_HOLD1' from file "sp2_acex.tdf" line 281, column 11 --- Equation name is 'SINC_HOLD1', location is LC6_F36, type is buried. -SINC_HOLD1 = DFFE( _EQ152, _LC7_A29, VCC, VCC, VCC); - _EQ152 = !SINC_1 & !SINC_1M - # _LC2_F36 & !SINC_1 - # HOLD1 & SINC_1; - --- Node name is 'SINC_HOLD2' from file "sp2_acex.tdf" line 281, column 11 --- Equation name is 'SINC_HOLD2', location is LC7_F36, type is buried. -SINC_HOLD2 = DFFE( _EQ153, _LC7_A29, VCC, VCC, VCC); - _EQ153 = !SINC_1 & !SINC_1M - # _LC3_F36 & !SINC_1 - # HOLD2 & SINC_1; - --- Node name is 'SINC_HOLD3' from file "sp2_acex.tdf" line 281, column 11 --- Equation name is 'SINC_HOLD3', location is LC8_F36, type is buried. -SINC_HOLD3 = DFFE( _EQ154, _LC7_A29, VCC, VCC, VCC); - _EQ154 = !SINC_1 & !SINC_1M - # _LC4_F36 & !SINC_1 - # HOLD3 & SINC_1; - --- Node name is 'SINC_HOLD4' from file "sp2_acex.tdf" line 281, column 11 --- Equation name is 'SINC_HOLD4', location is LC1_F22, type is buried. --- SINC_HOLD4 is in Up/Down Counter Mode --- synchronous load = !_LC7_F33 --- synchronous data = !_LC7_F33 -SINC_HOLD4 = DFFE(( _EQ155 & !_LC7_F33 # !_LC7_F33 & _LC7_F33), _LC6_A30, VCC, VCC, VCC); - _EQ155 = !SINC_2M - # !SINC_HOLD4; - --- Node name is 'SINC_HOLD5' from file "sp2_acex.tdf" line 281, column 11 --- Equation name is 'SINC_HOLD5', location is LC8_F22, type is buried. -SINC_HOLD5 = DFFE( _EQ156, _LC6_A30, VCC, VCC, VCC); - _EQ156 = !SINC_2 & !SINC_2M - # _LC7_F22 & !SINC_2 - # HOLD4 & SINC_2; - --- Node name is 'SINC_HOLD6' from file "sp2_acex.tdf" line 281, column 11 --- Equation name is 'SINC_HOLD6', location is LC2_F22, type is buried. --- SINC_HOLD6 is in Up/Down Counter Mode --- synchronous load = !_LC7_F33 --- synchronous data = !_LC2_F33 -SINC_HOLD6 = DFFE(( _EQ157 & !_LC7_F33 # !_LC2_F33 & _LC7_F33), _LC6_A30, VCC, VCC, VCC); - _EQ157 = !SINC_2M - # !_LC1_F22_CARRY & SINC_HOLD6 - # _LC1_F22_CARRY & !SINC_HOLD6; - --- Node name is 'SINC_HOLD7' from file "sp2_acex.tdf" line 281, column 11 --- Equation name is 'SINC_HOLD7', location is LC3_F22, type is buried. --- SINC_HOLD7 is in Up/Down Counter Mode --- synchronous load = !_LC7_F33 --- synchronous data = !_LC4_F33 -SINC_HOLD7 = DFFE(( _EQ158 & !_LC7_F33 # !_LC4_F33 & _LC7_F33), _LC6_A30, VCC, VCC, VCC); - _EQ158 = !SINC_2M - # !_LC2_F22_CARRY & SINC_HOLD7 - # _LC2_F22_CARRY & !SINC_HOLD7; - --- Node name is 'SINC_HOLD8' from file "sp2_acex.tdf" line 281, column 11 --- Equation name is 'SINC_HOLD8', location is LC5_F22, type is buried. --- SINC_HOLD8 is in Up/Down Counter Mode --- synchronous load = !_LC7_F33 --- synchronous data = HOLD7 -SINC_HOLD8 = DFFE(( _EQ159 & !_LC7_F33 # HOLD7 & _LC7_F33), _LC6_A30, VCC, VCC, VCC); - _EQ159 = !SINC_2M - # _LC4_F22_CARRY; - --- Node name is 'SINC_1' from file "sp2_acex.tdf" line 797, column 16 --- Equation name is 'SINC_1', location is LC5_D21, type is buried. -SINC_1 = DFFE( XA2, T_RDXA, _LC8_F32, VCC, _IOC_7); - --- Node name is 'SINC_1M' from file "sp2_acex.tdf" line 803, column 12 --- Equation name is 'SINC_1M', location is LC1_F36, type is buried. -SINC_1M = DFFE( _EQ160, GLOBAL( TG42), VCC, VCC, VCC); - _EQ160 = !SINC_HOLD0 - # !SINC_HOLD1 - # !SINC_HOLD2 - # !SINC_HOLD3; - --- Node name is 'SINC_2~1' from file "sp2_acex.tdf" line 798, column 16 --- Equation name is 'SINC_2~1', location is LC7_F33, type is buried. --- synthesized logic cell -!_LC7_F33 = _LC7_F33~NOT; -_LC7_F33~NOT = LCELL(!SINC_2); - --- Node name is 'SINC_2' from file "sp2_acex.tdf" line 798, column 16 --- Equation name is 'SINC_2', location is LC4_D21, type is buried. -SINC_2 = DFFE( XA3, T_RDXA, _LC8_F32, VCC, _IOC_7); - --- Node name is 'SINC_2M' from file "sp2_acex.tdf" line 810, column 12 --- Equation name is 'SINC_2M', location is LC4_F22, type is buried. -SINC_2M = DFFE( _EQ161, GLOBAL( TG42), VCC, VCC, VCC); - _EQ161 = _LC6_F22 - # !SINC_HOLD8; - --- Node name is 'SOFT_RES0' from file "sp2_acex.tdf" line 246, column 10 --- Equation name is 'SOFT_RES0', location is LC7_C28, type is buried. -!SOFT_RES0 = SOFT_RES0~NOT; -SOFT_RES0~NOT = DFFE( _EQ162, !_LC7_A29, !_LC6_C13, VCC, VCC); - _EQ162 = SOFT_RES0 - # !SOFT_RES1; - --- Node name is 'SOFT_RES1' from file "sp2_acex.tdf" line 246, column 10 --- Equation name is 'SOFT_RES1', location is LC8_C28, type is buried. -!SOFT_RES1 = SOFT_RES1~NOT; -SOFT_RES1~NOT = DFFE( _EQ163, !_LC7_A29, !_LC6_C13, VCC, VCC); - _EQ163 = !SOFT_RES0 - # !SOFT_RES1; - --- Node name is 'SXA' = ':1442' from file "sp2_acex.tdf" line 775, column 10 --- Equation name is 'SXA', type is output -SXA = _IOC_7; - --- Node name is ':1442' from file "sp2_acex.tdf" line 775, column 10 --- Equation name is '_IOC_7', type is buried -_IOC_7 = DFFE( _LC1_A29, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'SYS_ENA2' from file "sp2_acex.tdf" line 555, column 13 --- Equation name is 'SYS_ENA2', location is LC3_C29, type is buried. -SYS_ENA2 = DFFE( _EQ164, GLOBAL( TG42), VCC, VCC, VCC); - _EQ164 = !a1 & a5 & !A7 & _LC2_C29; - --- Node name is 'SYS_PG' from file "sp2_acex.tdf" line 574, column 11 --- Equation name is 'SYS_PG', location is LC1_F27, type is buried. -SYS_PG = DFFE( D0, /IOWR, /reset, !ROM_RG4, _LC4_C27); - --- Node name is 'TAPE_IN' from file "sp2_acex.tdf" line 792, column 13 --- Equation name is 'TAPE_IN', location is LC4_D28, type is buried. -TAPE_IN = DFFE( XA2, T_RDXA, VCC, VCC, !_LC6_D28); - --- Node name is 'TAPE_OUT' from file "sp2_acex.tdf" line 752, column 13 --- Equation name is 'TAPE_OUT', location is LC4_E29, type is buried. -TAPE_OUT = LCELL( BORDER3); - --- Node name is 'TEST_SWITCH' from file "sp2_acex.tdf" line 526, column 17 --- Equation name is 'TEST_SWITCH', location is LC8_E29, type is buried. -!TEST_SWITCH = TEST_SWITCH~NOT; -TEST_SWITCH~NOT = DFFE( _EQ165, _LC6_E20, /reset, VCC, VCC); - _EQ165 = !_LC1_E20 & !_LC3_E24 & !_LC3_E34 & TEST_SWITCH - # _LC1_E20 & !TEST_SWITCH - # _LC3_E24 & !TEST_SWITCH - # _LC3_E34 & !TEST_SWITCH; - --- Node name is 'T_RDXA' from file "sp2_acex.tdf" line 767, column 12 --- Equation name is 'T_RDXA', location is LC7_D28, type is buried. -T_RDXA = LCELL( _IOC_173); - --- Node name is 'VA0' = '|video2:SVIDEO|VLA2' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA0', type is output -VA0 = _IOC_102; - --- Node name is '|video2:SVIDEO|VLA2' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_102', type is buried -_IOC_102 = DFFE(!_LC1_F3, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA1' = '|video2:SVIDEO|VLA3' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA1', type is output -VA1 = _IOC_100; - --- Node name is '|video2:SVIDEO|VLA3' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_100', type is buried -_IOC_100 = DFFE(!_LC1_F5, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA2' = '|video2:SVIDEO|VLA4' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA2', type is output -VA2 = _IOC_97; - --- Node name is '|video2:SVIDEO|VLA4' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_97', type is buried -_IOC_97 = DFFE(!_LC2_F7, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA3' = '|video2:SVIDEO|VLA5' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA3', type is output -VA3 = _IOC_96; - --- Node name is '|video2:SVIDEO|VLA5' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_96', type is buried -_IOC_96 = DFFE( _LC4_F7, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA4' = '|video2:SVIDEO|VLA6' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA4', type is output -VA4 = _IOC_94; - --- Node name is '|video2:SVIDEO|VLA6' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_94', type is buried -_IOC_94 = DFFE( _LC2_B9, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA5' = '|video2:SVIDEO|VLA7' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA5', type is output -VA5 = _IOC_92; - --- Node name is '|video2:SVIDEO|VLA7' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_92', type is buried -_IOC_92 = DFFE( _LC1_A11, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA6' = '|video2:SVIDEO|VLA8' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA6', type is output -VA6 = _IOC_89; - --- Node name is '|video2:SVIDEO|VLA8' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_89', type is buried -_IOC_89 = DFFE( _LC1_B13, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA7' = '|video2:SVIDEO|VLA9' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA7', type is output -VA7 = _IOC_86; - --- Node name is '|video2:SVIDEO|VLA9' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_86', type is buried -_IOC_86 = DFFE( _LC1_B15, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA8' = '|video2:SVIDEO|VLA10' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA8', type is output -VA8 = _IOC_90; - --- Node name is '|video2:SVIDEO|VLA10' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_90', type is buried -_IOC_90 = DFFE(!_LC6_F11, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA9' = '|video2:SVIDEO|VLA11' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA9', type is output -VA9 = _IOC_93; - --- Node name is '|video2:SVIDEO|VLA11' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_93', type is buried -_IOC_93 = DFFE(!_LC5_F9, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA10' = '|video2:SVIDEO|VLA12' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA10', type is output -VA10 = _IOC_99; - --- Node name is '|video2:SVIDEO|VLA12' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_99', type is buried -_IOC_99 = DFFE(!_LC8_F5, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA11' = '|video2:SVIDEO|VLA13' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA11', type is output -VA11 = _IOC_95; - --- Node name is '|video2:SVIDEO|VLA13' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_95', type is buried -_IOC_95 = DFFE(!_LC1_B9, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA12' = '|video2:SVIDEO|VLA14' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA12', type is output -VA12 = _IOC_74; - --- Node name is '|video2:SVIDEO|VLA14' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_74', type is buried -_IOC_74 = DFFE(!_LC1_B19, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA13' = '|video2:SVIDEO|VLA15' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA13', type is output -VA13 = _IOC_87; - --- Node name is '|video2:SVIDEO|VLA15' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_87', type is buried -_IOC_87 = DFFE(!_LC7_A14, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA14' = '|video2:SVIDEO|VLA16' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA14', type is output -VA14 = _IOC_73; - --- Node name is '|video2:SVIDEO|VLA16' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_73', type is buried -_IOC_73 = DFFE(!_LC2_B20, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'VA15' = '|video2:SVIDEO|VLA17' from file "video2.tdf" line 106, column 5 --- Equation name is 'VA15', type is output -VA15 = _IOC_71; - --- Node name is '|video2:SVIDEO|VLA17' from file "video2.tdf" line 106, column 5 --- Equation name is '_IOC_71', type is buried -_IOC_71 = DFFE(!_LC1_F21, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'v_cs0' from file "sp2_acex.tdf" line 1008, column 6 --- Equation name is 'v_cs0', type is output -v_cs0 = GND; - --- Node name is 'v_cs1' from file "sp2_acex.tdf" line 1008, column 6 --- Equation name is 'v_cs1', type is output -v_cs1 = VCC; - --- Node name is 'VD00' from file "sp2_acex.tdf" line 427, column 6 --- Equation name is 'VD00', type is bidir -VD00 = TRI(_LC5_A1, V_WRX0); - --- Node name is 'VD01' from file "sp2_acex.tdf" line 427, column 6 --- Equation name is 'VD01', type is bidir -VD01 = TRI(_LC5_F29, V_WRX0); - --- Node name is 'VD02' from file "sp2_acex.tdf" line 427, column 6 --- Equation name is 'VD02', type is bidir -VD02 = TRI(_LC1_F1, V_WRX0); - --- Node name is 'VD03' from file "sp2_acex.tdf" line 427, column 6 --- Equation name is 'VD03', type is bidir -VD03 = TRI(_LC3_E14, V_WRX0); - --- Node name is 'VD04' from file "sp2_acex.tdf" line 427, column 6 --- Equation name is 'VD04', type is bidir -VD04 = TRI(_LC5_D3, V_WRX0); - --- Node name is 'VD05' from file "sp2_acex.tdf" line 427, column 6 --- Equation name is 'VD05', type is bidir -VD05 = TRI(_LC8_D1, V_WRX0); - --- Node name is 'VD06' from file "sp2_acex.tdf" line 427, column 6 --- Equation name is 'VD06', type is bidir -VD06 = TRI(_LC7_E14, V_WRX0); - --- Node name is 'VD07' from file "sp2_acex.tdf" line 427, column 6 --- Equation name is 'VD07', type is bidir -VD07 = TRI(_LC6_F1, V_WRX0); - --- Node name is 'VD10' from file "sp2_acex.tdf" line 426, column 6 --- Equation name is 'VD10', type is bidir -VD10 = TRI(_LC6_D1, V_WRX1); - --- Node name is 'VD11' from file "sp2_acex.tdf" line 426, column 6 --- Equation name is 'VD11', type is bidir -VD11 = TRI(_LC8_F1, V_WRX1); - --- Node name is 'VD12' from file "sp2_acex.tdf" line 426, column 6 --- Equation name is 'VD12', type is bidir -VD12 = TRI(_LC5_E14, V_WRX1); - --- Node name is 'VD13' from file "sp2_acex.tdf" line 426, column 6 --- Equation name is 'VD13', type is bidir -VD13 = TRI(_LC3_D3, V_WRX1); - --- Node name is 'VD14' from file "sp2_acex.tdf" line 426, column 6 --- Equation name is 'VD14', type is bidir -VD14 = TRI(_LC6_C5, V_WRX1); - --- Node name is 'VD15' from file "sp2_acex.tdf" line 426, column 6 --- Equation name is 'VD15', type is bidir -VD15 = TRI(_LC4_C5, V_WRX1); - --- Node name is 'VD16' from file "sp2_acex.tdf" line 426, column 6 --- Equation name is 'VD16', type is bidir -VD16 = TRI(_LC5_C5, V_WRX1); - --- Node name is 'VD17' from file "sp2_acex.tdf" line 426, column 6 --- Equation name is 'VD17', type is bidir -VD17 = TRI(_LC1_E1, V_WRX1); - --- Node name is 'VD20' from file "sp2_acex.tdf" line 425, column 6 --- Equation name is 'VD20', type is bidir -VD20 = TRI(_LC1_A1, V_WRX2); - --- Node name is 'VD21' from file "sp2_acex.tdf" line 425, column 6 --- Equation name is 'VD21', type is bidir -VD21 = TRI(_LC3_F2, V_WRX2); - --- Node name is 'VD22' from file "sp2_acex.tdf" line 425, column 6 --- Equation name is 'VD22', type is bidir -VD22 = TRI(_LC3_C1, V_WRX2); - --- Node name is 'VD23' from file "sp2_acex.tdf" line 425, column 6 --- Equation name is 'VD23', type is bidir -VD23 = TRI(_LC6_B3, V_WRX2); - --- Node name is 'VD24' from file "sp2_acex.tdf" line 425, column 6 --- Equation name is 'VD24', type is bidir -VD24 = TRI(_LC5_B18, V_WRX2); - --- Node name is 'VD25' from file "sp2_acex.tdf" line 425, column 6 --- Equation name is 'VD25', type is bidir -VD25 = TRI(_LC8_A1, V_WRX2); - --- Node name is 'VD26' from file "sp2_acex.tdf" line 425, column 6 --- Equation name is 'VD26', type is bidir -VD26 = TRI(_LC3_B18, V_WRX2); - --- Node name is 'VD27' from file "sp2_acex.tdf" line 425, column 6 --- Equation name is 'VD27', type is bidir -VD27 = TRI(_LC8_C1, V_WRX2); - --- Node name is 'VD30' from file "sp2_acex.tdf" line 424, column 6 --- Equation name is 'VD30', type is bidir -VD30 = TRI(_LC4_F1, V_WRX3); - --- Node name is 'VD31' from file "sp2_acex.tdf" line 424, column 6 --- Equation name is 'VD31', type is bidir -VD31 = TRI(_LC1_C5, V_WRX3); - --- Node name is 'VD32' from file "sp2_acex.tdf" line 424, column 6 --- Equation name is 'VD32', type is bidir -VD32 = TRI(_LC1_B3, V_WRX3); - --- Node name is 'VD33' from file "sp2_acex.tdf" line 424, column 6 --- Equation name is 'VD33', type is bidir -VD33 = TRI(_LC6_A15, V_WRX3); - --- Node name is 'VD34' from file "sp2_acex.tdf" line 424, column 6 --- Equation name is 'VD34', type is bidir -VD34 = TRI(_LC3_A15, V_WRX3); - --- Node name is 'VD35' from file "sp2_acex.tdf" line 424, column 6 --- Equation name is 'VD35', type is bidir -VD35 = TRI(_LC2_B18, V_WRX3); - --- Node name is 'VD36' from file "sp2_acex.tdf" line 424, column 6 --- Equation name is 'VD36', type is bidir -VD36 = TRI(_LC7_B18, V_WRX3); - --- Node name is 'VD37' from file "sp2_acex.tdf" line 424, column 6 --- Equation name is 'VD37', type is bidir -VD37 = TRI(_LC1_D3, V_WRX3); - --- Node name is 'VIDEO_PG' from file "sp2_acex.tdf" line 971, column 13 --- Equation name is 'VIDEO_PG', location is LC7_C18, type is buried. -VIDEO_PG = LCELL( _EQ166); - _EQ166 = _EC1_C & _EC7_C & !_EC10_C & !_EC12_C; - --- Node name is 'V_WRX0' from file "sp2_acex.tdf" line 262, column 7 --- Equation name is 'V_WRX0', location is LC1_F17, type is buried. -V_WRX0 = LCELL(!_LC2_F17); - --- Node name is 'V_WRX1' from file "sp2_acex.tdf" line 262, column 7 --- Equation name is 'V_WRX1', location is LC1_F16, type is buried. -V_WRX1 = LCELL(!_LC2_F16); - --- Node name is 'V_WRX2' from file "sp2_acex.tdf" line 262, column 7 --- Equation name is 'V_WRX2', location is LC1_F19, type is buried. -V_WRX2 = LCELL(!_LC2_F19); - --- Node name is 'V_WRX3' from file "sp2_acex.tdf" line 262, column 7 --- Equation name is 'V_WRX3', location is LC1_F14, type is buried. -V_WRX3 = LCELL(!_LC2_F14); - --- Node name is 'v_wr0' from file "sp2_acex.tdf" line 543, column 6 --- Equation name is 'v_wr0', type is output -v_wr0 = _LC8_F17; - --- Node name is 'v_wr1' from file "sp2_acex.tdf" line 543, column 6 --- Equation name is 'v_wr1', type is output -v_wr1 = _LC8_F16; - --- Node name is 'v_wr2' from file "sp2_acex.tdf" line 543, column 6 --- Equation name is 'v_wr2', type is output -v_wr2 = _LC8_F19; - --- Node name is 'v_wr3' from file "sp2_acex.tdf" line 543, column 6 --- Equation name is 'v_wr3', type is output -v_wr3 = _LC8_F14; - --- Node name is 'WAIT_ORIG' from file "sp2_acex.tdf" line 563, column 15 --- Equation name is 'WAIT_ORIG', location is LC6_C33, type is buried. -WAIT_ORIG = LCELL( _EQ167); - _EQ167 = _LC3_C33 - # ALL_MODE2 - # _LC6_A29 - # /mr; - --- Node name is 'WAIT_ROMX' from file "sp2_acex.tdf" line 592, column 14 --- Equation name is 'WAIT_ROMX', location is LC1_B11, type is buried. -WAIT_ROMX = LCELL( _EQ168); - _EQ168 = CS_ISA & CS_ROMT; - --- Node name is 'wr_awg' from file "sp2_acex.tdf" line 779, column 2 --- Equation name is 'wr_awg', type is output -wr_awg = _LC2_A15; - --- Node name is 'WR_COL' = '|video2:SVIDEO|TSN_W3' from file "video2.tdf" line 115, column 2 --- Equation name is 'WR_COL', type is output -WR_COL = _IOC_157; - --- Node name is '|video2:SVIDEO|TSN_W3' from file "video2.tdf" line 115, column 2 --- Equation name is '_IOC_157', type is buried -_IOC_157 = DFFE( _LC2_F1, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is 'wr_dwg' from file "sp2_acex.tdf" line 731, column 2 --- Equation name is 'wr_dwg', type is output -wr_dwg = !_LC6_A28; - --- Node name is 'wr_tm9~1' from file "sp2_acex.tdf" line 770, column 12 --- Equation name is 'wr_tm9~1', location is LC4_A29, type is buried. -_LC4_A29 = LCELL( _LC3_E28); - --- Node name is 'wr_tm9' from file "sp2_acex.tdf" line 770, column 12 --- Equation name is 'wr_tm9', location is LC1_E18, type is buried. -_LC1_E18 = LCELL( _LC3_E28); - --- Node name is 'WT_R0' from file "sp2_acex.tdf" line 232, column 6 --- Equation name is 'WT_R0', location is LC1_B18, type is buried. -WT_R0 = DFFE( _EQ169, GLOBAL( TG42), VCC, VCC, VCC); - _EQ169 = !WAIT_ROMX & !WT_R0 & WT_R2 - # !WAIT_ROMX & !WT_R0 & WT_R1; - --- Node name is 'WT_R1' from file "sp2_acex.tdf" line 232, column 6 --- Equation name is 'WT_R1', location is LC4_B18, type is buried. -WT_R1 = DFFE( _EQ170, GLOBAL( TG42), VCC, VCC, VCC); - _EQ170 = !WAIT_ROMX & !WT_R0 & !WT_R1 & WT_R2 - # !WAIT_ROMX & WT_R0 & WT_R1; - --- Node name is 'WT_R2' from file "sp2_acex.tdf" line 232, column 6 --- Equation name is 'WT_R2', location is LC6_B18, type is buried. -WT_R2 = DFFE( _EQ171, GLOBAL( TG42), VCC, VCC, VCC); - _EQ171 = WT_R0 & WT_R2 - # WT_R1 & WT_R2 - # WAIT_ROMX; - --- Node name is 'XACS' from file "sp2_acex.tdf" line 254, column 2 --- Equation name is 'XACS', type is output -XACS = _LC1_F9; - --- Node name is 'XA0' from file "sp2_acex.tdf" line 785, column 2 --- Equation name is 'XA0', type is bidir -XA0 = OPNDRN(!_LC1_E18); - --- Node name is 'XA1' from file "sp2_acex.tdf" line 786, column 2 --- Equation name is 'XA1', type is bidir -XA1 = OPNDRN(!_LC4_A29); - --- Node name is 'XA2' from file "sp2_acex.tdf" line 787, column 2 --- Equation name is 'XA2', type is bidir -XA2 = TRI(TAPE_OUT, _LC1_E18); - --- Node name is 'XA3' from file "sp2_acex.tdf" line 788, column 2 --- Equation name is 'XA3', type is bidir -XA3 = TRI(GND, GND); - --- Node name is '|acceler:ACC|AAGR0' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC1_F4', type is buried --- |acceler:ACC|AAGR0 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = D0 -_LC1_F4 = DFFE(( _LC1_F4 & !_LC4_C14 # D0 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC8_F3); - --- Node name is '|acceler:ACC|AAGR1' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC7_F5', type is buried -_LC7_F5 = DFFE( _EQ172, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ172 = D1 & _LC3_E13 - # !_LC3_E13 & _LC7_F5; - --- Node name is '|acceler:ACC|AAGR2' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC1_F13', type is buried -_LC1_F13 = DFFE( _EQ173, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ173 = d2 & _LC3_E13 - # _LC1_F13 & !_LC3_E13; - --- Node name is '|acceler:ACC|AAGR3' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC6_F13', type is buried -_LC6_F13 = DFFE( _EQ174, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ174 = d3 & _LC3_E13 - # !_LC3_E13 & _LC6_F13; - --- Node name is '|acceler:ACC|AAGR4' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC8_F13', type is buried -_LC8_F13 = DFFE( _EQ175, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ175 = d4 & _LC3_E13 - # !_LC3_E13 & _LC8_F13; - --- Node name is '|acceler:ACC|AAGR5' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC4_F13', type is buried -_LC4_F13 = DFFE( _EQ176, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ176 = d5 & _LC3_E13 - # !_LC3_E13 & _LC4_F13; - --- Node name is '|acceler:ACC|AAGR6' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC5_F13', type is buried -_LC5_F13 = DFFE( _EQ177, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ177 = d6 & _LC3_E13 - # !_LC3_E13 & _LC5_F13; - --- Node name is '|acceler:ACC|AAGR7' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC7_F13', type is buried -_LC7_F13 = DFFE( _EQ178, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ178 = d7 & _LC3_E13 - # !_LC3_E13 & _LC7_F13; - --- Node name is '|acceler:ACC|AAGR8' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC2_F5', type is buried -_LC2_F5 = DFFE( _EQ179, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ179 = A8 & _LC3_E13 - # _LC2_F5 & !_LC3_E13; - --- Node name is '|acceler:ACC|AAGR9' from file "acceler.tdf" line 109, column 6 --- Equation name is '_LC3_F5', type is buried -_LC3_F5 = DFFE( _EQ180, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ180 = a9 & _LC3_E13 - # !_LC3_E13 & _LC3_F5; - --- Node name is '|acceler:ACC|AA0' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC1_C22', type is buried --- |acceler:ACC|AA0 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = a0 -_LC1_C22 = DFFE((!_LC1_C22 & !_LC4_C14 # a0 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - --- Node name is '|acceler:ACC|AA1' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC2_C36', type is buried -_LC2_C36 = DFFE( _EQ181, GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ181 = !_LC3_E13 & _LC6_C36 - # a1 & _LC3_E13; - --- Node name is '|acceler:ACC|AA2' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC2_C22', type is buried --- |acceler:ACC|AA2 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = a2 -_LC2_C22 = DFFE(( _EQ182 & !_LC4_C14 # a2 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ182 = !_LC1_C22_CARRY & _LC2_C22 - # _LC1_C22_CARRY & !_LC2_C22; - --- Node name is '|acceler:ACC|AA3' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC3_C22', type is buried --- |acceler:ACC|AA3 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = a3 -_LC3_C22 = DFFE(( _EQ183 & !_LC4_C14 # a3 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ183 = !_LC2_C22_CARRY & _LC3_C22 - # _LC2_C22_CARRY & !_LC3_C22; - --- Node name is '|acceler:ACC|AA4' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC4_C22', type is buried --- |acceler:ACC|AA4 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = a4 -_LC4_C22 = DFFE(( _EQ184 & !_LC4_C14 # a4 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ184 = !_LC3_C22_CARRY & _LC4_C22 - # _LC3_C22_CARRY & !_LC4_C22; - --- Node name is '|acceler:ACC|AA5' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC5_C22', type is buried --- |acceler:ACC|AA5 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = a5 -_LC5_C22 = DFFE(( _EQ185 & !_LC4_C14 # a5 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ185 = !_LC4_C22_CARRY & _LC5_C22 - # _LC4_C22_CARRY & !_LC5_C22; - --- Node name is '|acceler:ACC|AA6' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC6_C22', type is buried --- |acceler:ACC|AA6 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A6 -_LC6_C22 = DFFE(( _EQ186 & !_LC4_C14 # A6 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ186 = !_LC5_C22_CARRY & _LC6_C22 - # _LC5_C22_CARRY & !_LC6_C22; - --- Node name is '|acceler:ACC|AA7' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC7_C22', type is buried --- |acceler:ACC|AA7 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A7 -_LC7_C22 = DFFE(( _EQ187 & !_LC4_C14 # A7 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ187 = !_LC6_C22_CARRY & _LC7_C22 - # _LC6_C22_CARRY & !_LC7_C22; - --- Node name is '|acceler:ACC|AA8' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC8_C22', type is buried --- |acceler:ACC|AA8 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A8 -_LC8_C22 = DFFE(( _EQ188 & !_LC4_C14 # A8 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ188 = !_LC7_C22_CARRY & _LC8_C22 - # _LC7_C22_CARRY & !_LC8_C22; - --- Node name is '|acceler:ACC|AA9' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC1_C24', type is buried --- |acceler:ACC|AA9 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = a9 -_LC1_C24 = DFFE(( _EQ189 & !_LC4_C14 # a9 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ189 = _LC1_C24 & !_LC8_C22_CARRY - # !_LC1_C24 & _LC8_C22_CARRY; - --- Node name is '|acceler:ACC|AA10' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC2_C24', type is buried --- |acceler:ACC|AA10 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A10 -_LC2_C24 = DFFE(( _EQ190 & !_LC4_C14 # A10 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ190 = !_LC1_C24_CARRY & _LC2_C24 - # _LC1_C24_CARRY & !_LC2_C24; - --- Node name is '|acceler:ACC|AA11' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC3_C24', type is buried --- |acceler:ACC|AA11 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = a11 -_LC3_C24 = DFFE(( _EQ191 & !_LC4_C14 # a11 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ191 = !_LC2_C24_CARRY & _LC3_C24 - # _LC2_C24_CARRY & !_LC3_C24; - --- Node name is '|acceler:ACC|AA12' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC4_C24', type is buried --- |acceler:ACC|AA12 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A12 -_LC4_C24 = DFFE(( _EQ192 & !_LC4_C14 # A12 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ192 = !_LC3_C24_CARRY & _LC4_C24 - # _LC3_C24_CARRY & !_LC4_C24; - --- Node name is '|acceler:ACC|AA13' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC5_C24', type is buried --- |acceler:ACC|AA13 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A13 -_LC5_C24 = DFFE(( _EQ193 & !_LC4_C14 # A13 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ193 = !_LC4_C24_CARRY & _LC5_C24 - # _LC4_C24_CARRY & !_LC5_C24; - --- Node name is '|acceler:ACC|AA14' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC6_C24', type is buried --- |acceler:ACC|AA14 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A14 -_LC6_C24 = DFFE(( _EQ194 & !_LC4_C14 # A14 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ194 = !_LC5_C24_CARRY & _LC6_C24 - # _LC5_C24_CARRY & !_LC6_C24; - --- Node name is '|acceler:ACC|AA15' from file "acceler.tdf" line 80, column 4 --- Equation name is '_LC8_C24', type is buried -_LC8_C24 = DFFE( _EQ195, GLOBAL( TG42), VCC, VCC, _LC1_F11); - _EQ195 = !_LC3_E13 & _LC7_C24_CARRY - # A15 & _LC3_E13; - --- Node name is '|acceler:ACC|ACC_BLK' from file "acceler.tdf" line 75, column 2 --- Equation name is '_LC3_F9', type is buried -!_LC3_F9 = _LC3_F9~NOT; -_LC3_F9~NOT = DFFE(!_LC1_F10, /m1, _LC4_F10, VCC, VCC); - --- Node name is '|acceler:ACC|ACC_CNT0' from file "acceler.tdf" line 84, column 9 --- Equation name is '_LC1_E17', type is buried -_LC1_E17 = DFFE( _EQ196, GLOBAL( TG42), VCC, VCC, _LC7_F3); - _EQ196 = !_LC1_E17 & !_LC3_E13 - # _LC3_E13 & _LC6_E17; - --- Node name is '|acceler:ACC|ACC_CNT1' from file "acceler.tdf" line 84, column 9 --- Equation name is '_LC2_E17', type is buried -_LC2_E17 = DFFE( _EQ197, GLOBAL( TG42), VCC, VCC, _LC7_F3); - _EQ197 = !_LC3_E13 & _LC4_E11 - # _LC3_E13 & _LC5_E17; - --- Node name is '|acceler:ACC|ACC_CNT2' from file "acceler.tdf" line 84, column 9 --- Equation name is '_LC5_E11', type is buried --- |acceler:ACC|ACC_CNT2 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = _LC3_E11 -_LC5_E11 = DFFE(( _EQ198 & !_LC4_C14 # _LC3_E11 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC7_F3); - _EQ198 = !_LC4_E11_CARRY & !_LC5_E11 - # _LC4_E11_CARRY & _LC5_E11; - --- Node name is '|acceler:ACC|ACC_CNT3' from file "acceler.tdf" line 84, column 9 --- Equation name is '_LC6_E11', type is buried --- |acceler:ACC|ACC_CNT3 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = _LC2_E11 -_LC6_E11 = DFFE(( _EQ199 & !_LC4_C14 # _LC2_E11 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC7_F3); - _EQ199 = !_LC5_E11_CARRY & !_LC6_E11 - # _LC5_E11_CARRY & _LC6_E11; - --- Node name is '|acceler:ACC|ACC_CNT4' from file "acceler.tdf" line 84, column 9 --- Equation name is '_LC7_E11', type is buried --- |acceler:ACC|ACC_CNT4 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = _LC1_E11 -_LC7_E11 = DFFE(( _EQ200 & !_LC4_C14 # _LC1_E11 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC7_F3); - _EQ200 = !_LC6_E11_CARRY & !_LC7_E11 - # _LC6_E11_CARRY & _LC7_E11; - --- Node name is '|acceler:ACC|ACC_CNT5' from file "acceler.tdf" line 84, column 9 --- Equation name is '_LC8_E11', type is buried --- |acceler:ACC|ACC_CNT5 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = _LC1_E4 -_LC8_E11 = DFFE(( _EQ201 & !_LC4_C14 # _LC1_E4 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC7_F3); - _EQ201 = !_LC7_E11_CARRY & !_LC8_E11 - # _LC7_E11_CARRY & _LC8_E11; - --- Node name is '|acceler:ACC|ACC_CNT6' from file "acceler.tdf" line 84, column 9 --- Equation name is '_LC1_E13', type is buried --- |acceler:ACC|ACC_CNT6 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = _LC5_E13 -_LC1_E13 = DFFE(( _EQ202 & !_LC4_C14 # _LC5_E13 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC7_F3); - _EQ202 = !_LC1_E13 & !_LC8_E11_CARRY - # _LC1_E13 & _LC8_E11_CARRY; - --- Node name is '|acceler:ACC|ACC_CNT7' from file "acceler.tdf" line 84, column 9 --- Equation name is '_LC4_E13', type is buried -_LC4_E13 = DFFE( _LC3_E13_CARRY, GLOBAL( TG42), VCC, VCC, _LC7_F3); - --- Node name is '|acceler:ACC|ACC_END' from file "acceler.tdf" line 87, column 2 --- Equation name is '_LC3_F16', type is buried -!_LC3_F16 = _LC3_F16~NOT; -_LC3_F16~NOT = DFFE( _EQ203, GLOBAL( TG42), /m1, VCC, _LC5_F16); - _EQ203 = _LC7_E13 & _LC7_F15 - # _LC7_E15 & _LC7_F15; - --- Node name is '|acceler:ACC|ACC_GO' from file "acceler.tdf" line 184, column 13 --- Equation name is '_LC4_F3', type is buried -!_LC4_F3 = _LC4_F3~NOT; -_LC4_F3~NOT = DFFE( _EQ204, GLOBAL( TG42), _LC6_F3, VCC, _LC3_F35); - _EQ204 = !_LC7_F32 & !_LC8_F9; - --- Node name is '|acceler:ACC|ACC_GO_1' from file "acceler.tdf" line 185, column 14 --- Equation name is '_LC2_F11', type is buried -_LC2_F11 = DFFE( _LC4_F3, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|acceler:ACC|ACC_MODE0' from file "acceler.tdf" line 89, column 10 --- Equation name is '_LC5_F10', type is buried -_LC5_F10 = DFFE( D0, GLOBAL( /mr), _LC4_F16, VCC, _LC5_D13); - --- Node name is '|acceler:ACC|ACC_MODE1' from file "acceler.tdf" line 89, column 10 --- Equation name is '_LC6_F5', type is buried -_LC6_F5 = DFFE( D1, GLOBAL( /mr), _LC4_F16, VCC, _LC5_D13); - --- Node name is '|acceler:ACC|ACC_MODE2' from file "acceler.tdf" line 89, column 10 --- Equation name is '_LC3_F10', type is buried -_LC3_F10 = DFFE( d2, GLOBAL( /mr), _LC4_F16, VCC, _LC5_D13); - --- Node name is '|acceler:ACC|ACC_MODE3' from file "acceler.tdf" line 89, column 10 --- Equation name is '_LC2_F10', type is buried -_LC2_F10 = DFFE( VCC, GLOBAL( /mr), _LC7_F10, VCC, _LC5_D13); - --- Node name is '|acceler:ACC|AGR0' from file "acceler.tdf" line 83, column 5 --- Equation name is '_LC2_C19', type is buried --- |acceler:ACC|AGR0 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = D0 -_LC2_C19 = DFFE((!_LC2_C19 & !_LC4_C14 # D0 & _LC4_C14), GLOBAL( TG42), /reset, VCC, _LC4_F18); - --- Node name is '|acceler:ACC|AGR1' from file "acceler.tdf" line 83, column 5 --- Equation name is '_LC3_C36', type is buried -_LC3_C36 = DFFE( _EQ205, GLOBAL( TG42), /reset, VCC, _LC4_F18); - _EQ205 = D1 & _LC3_E13 - # !_LC3_E13 & _LC7_C36; - --- Node name is '|acceler:ACC|AGR2' from file "acceler.tdf" line 83, column 5 --- Equation name is '_LC3_C19', type is buried --- |acceler:ACC|AGR2 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = d2 -_LC3_C19 = DFFE(( _EQ206 & !_LC4_C14 # d2 & _LC4_C14), GLOBAL( TG42), /reset, VCC, _LC4_F18); - _EQ206 = !_LC2_C19_CARRY & _LC3_C19 - # _LC2_C19_CARRY & !_LC3_C19; - --- Node name is '|acceler:ACC|AGR3' from file "acceler.tdf" line 83, column 5 --- Equation name is '_LC4_C19', type is buried --- |acceler:ACC|AGR3 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = d3 -_LC4_C19 = DFFE(( _EQ207 & !_LC4_C14 # d3 & _LC4_C14), GLOBAL( TG42), /reset, VCC, _LC4_F18); - _EQ207 = !_LC3_C19_CARRY & _LC4_C19 - # _LC3_C19_CARRY & !_LC4_C19; - --- Node name is '|acceler:ACC|AGR4' from file "acceler.tdf" line 83, column 5 --- Equation name is '_LC5_C19', type is buried --- |acceler:ACC|AGR4 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = d4 -_LC5_C19 = DFFE(( _EQ208 & !_LC4_C14 # d4 & _LC4_C14), GLOBAL( TG42), /reset, VCC, _LC4_F18); - _EQ208 = !_LC4_C19_CARRY & _LC5_C19 - # _LC4_C19_CARRY & !_LC5_C19; - --- Node name is '|acceler:ACC|AGR5' from file "acceler.tdf" line 83, column 5 --- Equation name is '_LC6_C19', type is buried --- |acceler:ACC|AGR5 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = d5 -_LC6_C19 = DFFE(( _EQ209 & !_LC4_C14 # d5 & _LC4_C14), GLOBAL( TG42), /reset, VCC, _LC4_F18); - _EQ209 = !_LC5_C19_CARRY & _LC6_C19 - # _LC5_C19_CARRY & !_LC6_C19; - --- Node name is '|acceler:ACC|AGR6' from file "acceler.tdf" line 83, column 5 --- Equation name is '_LC7_C19', type is buried --- |acceler:ACC|AGR6 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = d6 -_LC7_C19 = DFFE(( _EQ210 & !_LC4_C14 # d6 & _LC4_C14), GLOBAL( TG42), /reset, VCC, _LC4_F18); - _EQ210 = !_LC6_C19_CARRY & _LC7_C19 - # _LC6_C19_CARRY & !_LC7_C19; - --- Node name is '|acceler:ACC|AGR7' from file "acceler.tdf" line 83, column 5 --- Equation name is '_LC8_C19', type is buried --- |acceler:ACC|AGR7 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = d7 -_LC8_C19 = DFFE(( _EQ211 & !_LC4_C14 # d7 & _LC4_C14), GLOBAL( TG42), /reset, VCC, _LC4_F18); - _EQ211 = !_LC7_C19_CARRY & _LC8_C19 - # _LC7_C19_CARRY & !_LC8_C19; - --- Node name is '|acceler:ACC|ALT_ACC' from file "acceler.tdf" line 221, column 12 --- Equation name is '_LC7_F16', type is buried -_LC7_F16 = DFFE( VCC, _LC7_F24, /reset, VCC, VCC); - --- Node name is '|acceler:ACC|CORRECT_1F' from file "acceler.tdf" line 181, column 16 --- Equation name is '_LC2_D30', type is buried -_LC2_D30 = LCELL( _EQ212C); - _EQ212C = _EQ212 & CASCADE( _EQ213C); - _EQ212 = !_LC6_D34 & _LC8_D30 & !/mr & !/rd; - --- Node name is '|acceler:ACC|ED_CMD' from file "acceler.tdf" line 68, column 2 --- Equation name is '_LC6_E22', type is buried -_LC6_E22 = DFFE( _EQ214, GLOBAL( /mr), VCC, VCC, _LC2_D17); - _EQ214 = d5 & d7 & _LC2_E22; - --- Node name is '|acceler:ACC|FN_ACC0' from file "acceler.tdf" line 88, column 8 --- Equation name is '_LC5_D18', type is buried -_LC5_D18 = DFFE( _EQ215, GLOBAL( /mr), VCC, VCC, _LC2_D17); - _EQ215 = !d3 & _LC8_D18; - --- Node name is '|acceler:ACC|FN_ACC1' from file "acceler.tdf" line 88, column 8 --- Equation name is '_LC4_D18', type is buried -_LC4_D18 = DFFE( _EQ216, GLOBAL( /mr), VCC, VCC, _LC2_D17); - _EQ216 = !d4 & _LC8_D18; - --- Node name is '|acceler:ACC|GLISS_R' from file "acceler.tdf" line 122, column 2 --- Equation name is '_LC7_D18', type is buried -_LC7_D18 = DFFE( _EQ217, GLOBAL( TG42), VCC, VCC, VCC); - _EQ217 = _LC3_D18 & !_LC6_F10 - # _LC3_D10 & _LC5_D5 & _LC6_F10; - --- Node name is '|acceler:ACC|IN_OUT_CMD' from file "acceler.tdf" line 71, column 2 --- Equation name is '_LC5_D1', type is buried -_LC5_D1 = DFFE( _EQ218, GLOBAL( /mr), GLOBAL( /io), VCC, _LC2_D17); - _EQ218 = !d5 & d7 & _LC2_D1; - --- Node name is '|acceler:ACC|MDOX0' from file "acceler.tdf" line 119, column 6 --- Equation name is '_LC6_D17', type is buried -_LC6_D17 = DFFE( _EQ219, GLOBAL( TG42), VCC, VCC, VCC); - _EQ219 = D0 & !_LC1_D15 - # hddr0 & _LC1_D15; - --- Node name is '|acceler:ACC|MDOX1' from file "acceler.tdf" line 119, column 6 --- Equation name is '_LC6_D7', type is buried -_LC6_D7 = DFFE( _EQ220, GLOBAL( TG42), VCC, VCC, VCC); - _EQ220 = D1 & !_LC1_D15 - # hddr1 & _LC1_D15; - --- Node name is '|acceler:ACC|MDOX2' from file "acceler.tdf" line 119, column 6 --- Equation name is '_LC7_D7', type is buried -_LC7_D7 = DFFE( _EQ221, GLOBAL( TG42), VCC, VCC, VCC); - _EQ221 = d2 & !_LC1_D15 - # hddr2 & _LC1_D15; - --- Node name is '|acceler:ACC|MDOX3' from file "acceler.tdf" line 119, column 6 --- Equation name is '_LC4_D17', type is buried -_LC4_D17 = DFFE( _EQ222, GLOBAL( TG42), VCC, VCC, VCC); - _EQ222 = d3 & !_LC1_D15 - # hddr3 & _LC1_D15; - --- Node name is '|acceler:ACC|MDOX4' from file "acceler.tdf" line 119, column 6 --- Equation name is '_LC5_D17', type is buried -_LC5_D17 = DFFE( _EQ223, GLOBAL( TG42), VCC, VCC, VCC); - _EQ223 = d4 & !_LC1_D15 - # hddr4 & _LC1_D15; - --- Node name is '|acceler:ACC|MDOX5' from file "acceler.tdf" line 119, column 6 --- Equation name is '_LC6_D5', type is buried -_LC6_D5 = DFFE( _EQ224, GLOBAL( TG42), VCC, VCC, VCC); - _EQ224 = d5 & !_LC1_D15 - # hddr5 & _LC1_D15; - --- Node name is '|acceler:ACC|MDOX6' from file "acceler.tdf" line 119, column 6 --- Equation name is '_LC2_D5', type is buried -_LC2_D5 = DFFE( _EQ225, GLOBAL( TG42), VCC, VCC, VCC); - _EQ225 = d6 & !_LC1_D15 - # hddr6 & _LC1_D15; - --- Node name is '|acceler:ACC|MDOX7' from file "acceler.tdf" line 119, column 6 --- Equation name is '_LC3_D7', type is buried -_LC3_D7 = DFFE( _EQ226, GLOBAL( TG42), VCC, VCC, VCC); - _EQ226 = d7 & !_LC1_D15 - # hddr7 & _LC1_D15; - --- Node name is '|acceler:ACC|MDOY0' from file "acceler.tdf" line 120, column 6 --- Equation name is '_LC3_D17', type is buried -_LC3_D17 = DFFE( _EQ227, GLOBAL( TG42), VCC, VCC, VCC); - _EQ227 = D0 & !_LC4_F15 - # hddr0 & _LC4_F15; - --- Node name is '|acceler:ACC|MDOY1' from file "acceler.tdf" line 120, column 6 --- Equation name is '_LC5_D7', type is buried -_LC5_D7 = DFFE( _EQ228, GLOBAL( TG42), VCC, VCC, VCC); - _EQ228 = D1 & !_LC4_F15 - # hddr1 & _LC4_F15; - --- Node name is '|acceler:ACC|MDOY2' from file "acceler.tdf" line 120, column 6 --- Equation name is '_LC4_D7', type is buried -_LC4_D7 = DFFE( _EQ229, GLOBAL( TG42), VCC, VCC, VCC); - _EQ229 = d2 & !_LC4_F15 - # hddr2 & _LC4_F15; - --- Node name is '|acceler:ACC|MDOY3' from file "acceler.tdf" line 120, column 6 --- Equation name is '_LC7_D17', type is buried -_LC7_D17 = DFFE( _EQ230, GLOBAL( TG42), VCC, VCC, VCC); - _EQ230 = d3 & !_LC4_F15 - # hddr3 & _LC4_F15; - --- Node name is '|acceler:ACC|MDOY4' from file "acceler.tdf" line 120, column 6 --- Equation name is '_LC8_D17', type is buried -_LC8_D17 = DFFE( _EQ231, GLOBAL( TG42), VCC, VCC, VCC); - _EQ231 = d4 & !_LC4_F15 - # hddr4 & _LC4_F15; - --- Node name is '|acceler:ACC|MDOY5' from file "acceler.tdf" line 120, column 6 --- Equation name is '_LC5_D6', type is buried -_LC5_D6 = DFFE( _EQ232, GLOBAL( TG42), VCC, VCC, VCC); - _EQ232 = d5 & !_LC4_F15 - # hddr5 & _LC4_F15; - --- Node name is '|acceler:ACC|MDOY6' from file "acceler.tdf" line 120, column 6 --- Equation name is '_LC1_D5', type is buried -_LC1_D5 = DFFE( _EQ233, GLOBAL( TG42), VCC, VCC, VCC); - _EQ233 = d6 & !_LC4_F15 - # hddr6 & _LC4_F15; - --- Node name is '|acceler:ACC|MDOY7' from file "acceler.tdf" line 120, column 6 --- Equation name is '_LC2_D7', type is buried -_LC2_D7 = DFFE( _EQ234, GLOBAL( TG42), VCC, VCC, VCC); - _EQ234 = d7 & !_LC4_F15 - # hddr7 & _LC4_F15; - --- Node name is '|acceler:ACC|/M1M' from file "acceler.tdf" line 130, column 10 --- Equation name is '_LC2_D17', type is buried -_LC2_D17 = DFFE(!/m1, _LC2_D27, /reset, VCC, VCC); - --- Node name is '|acceler:ACC|PRF_CMD' from file "acceler.tdf" line 67, column 2 --- Equation name is '_LC7_D1', type is buried -_LC7_D1 = DFFE( _EQ235, GLOBAL( /mr), VCC, VCC, _LC2_D17); - _EQ235 = d7 & _LC3_D1 & _LC4_D1; - --- Node name is '|acceler:ACC|RAM_ADR0' from file "acceler.tdf" line 341, column 23 --- Equation name is '_LC7_A34', type is buried -_LC7_A34 = LCELL( _EQ236); - _EQ236 = _LC2_F2 & _LC7_F16 - # _LC1_E17 & !_LC7_F16; - --- Node name is '|acceler:ACC|RAM_ADR1' from file "acceler.tdf" line 341, column 23 --- Equation name is '_LC5_C28', type is buried -_LC5_C28 = LCELL( _EQ237); - _EQ237 = _LC7_F16 & _LC8_F2 - # _LC2_E17 & !_LC7_F16; - --- Node name is '|acceler:ACC|RAM_ADR2' from file "acceler.tdf" line 341, column 23 --- Equation name is '_LC6_E19', type is buried -_LC6_E19 = LCELL( _EQ238); - _EQ238 = _LC1_F8 & _LC7_F16 - # _LC5_E11 & !_LC7_F16; - --- Node name is '|acceler:ACC|RAM_ADR3' from file "acceler.tdf" line 341, column 23 --- Equation name is '_LC5_E15', type is buried -_LC5_E15 = LCELL( _EQ239); - _EQ239 = _LC2_F8 & _LC7_F16 - # _LC6_E11 & !_LC7_F16; - --- Node name is '|acceler:ACC|RAM_ADR4' from file "acceler.tdf" line 341, column 23 --- Equation name is '_LC3_A23', type is buried -_LC3_A23 = LCELL( _EQ240); - _EQ240 = _LC3_F8 & _LC7_F16 - # _LC7_E11 & !_LC7_F16; - --- Node name is '|acceler:ACC|RAM_ADR5' from file "acceler.tdf" line 341, column 23 --- Equation name is '_LC4_E15', type is buried -_LC4_E15 = LCELL( _EQ241); - _EQ241 = _LC4_F8 & _LC7_F16 - # !_LC7_F16 & _LC8_E11; - --- Node name is '|acceler:ACC|RAM_ADR6' from file "acceler.tdf" line 341, column 23 --- Equation name is '_LC6_E13', type is buried -_LC6_E13 = LCELL( _EQ242); - _EQ242 = _LC5_F8 & _LC7_F16 - # _LC1_E13 & !_LC7_F16; - --- Node name is '|acceler:ACC|RAM_ADR7' from file "acceler.tdf" line 341, column 23 --- Equation name is '_LC3_E15', type is buried -_LC3_E15 = LCELL( _EQ243); - _EQ243 = _LC6_F8 & _LC7_F16 - # _LC4_E13 & !_LC7_F16; - --- Node name is '|acceler:ACC|RAM_WR' from file "acceler.tdf" line 347, column 13 --- Equation name is '_LC3_F3', type is buried -_LC3_F3 = DFFE( _EQ244, GLOBAL( TG42), VCC, VCC, VCC); - _EQ244 = !_LC4_F3 & _LC6_F10 & _LC7_F1 & !/rd; - --- Node name is '|acceler:ACC|RETI' from file "acceler.tdf" line 77, column 2 --- Equation name is '_LC3_E4', type is buried -_LC3_E4 = DFFE( _EQ245, GLOBAL( /mr), VCC, VCC, _LC2_D17); - _EQ245 = !d5 & !d7 & _LC4_E22; - --- Node name is '|acceler:ACC|RGACC0' from file "acceler.tdf" line 82, column 7 --- Equation name is '_LC6_E17', type is buried -_LC6_E17 = DFFE( D0, GLOBAL( /mr), VCC, VCC, _LC2_F15); - --- Node name is '|acceler:ACC|RGACC1' from file "acceler.tdf" line 82, column 7 --- Equation name is '_LC5_E17', type is buried -_LC5_E17 = DFFE( D1, GLOBAL( /mr), VCC, VCC, _LC2_F15); - --- Node name is '|acceler:ACC|RGACC2' from file "acceler.tdf" line 82, column 7 --- Equation name is '_LC3_E11', type is buried -_LC3_E11 = DFFE( d2, GLOBAL( /mr), VCC, VCC, _LC2_F15); - --- Node name is '|acceler:ACC|RGACC3' from file "acceler.tdf" line 82, column 7 --- Equation name is '_LC2_E11', type is buried -_LC2_E11 = DFFE( d3, GLOBAL( /mr), VCC, VCC, _LC2_F15); - --- Node name is '|acceler:ACC|RGACC4' from file "acceler.tdf" line 82, column 7 --- Equation name is '_LC1_E11', type is buried -_LC1_E11 = DFFE( d4, GLOBAL( /mr), VCC, VCC, _LC2_F15); - --- Node name is '|acceler:ACC|RGACC5' from file "acceler.tdf" line 82, column 7 --- Equation name is '_LC1_E4', type is buried -_LC1_E4 = DFFE( d5, GLOBAL( /mr), VCC, VCC, _LC2_F15); - --- Node name is '|acceler:ACC|RGACC6' from file "acceler.tdf" line 82, column 7 --- Equation name is '_LC5_E13', type is buried -_LC5_E13 = DFFE( d6, GLOBAL( /mr), VCC, VCC, _LC2_F15); - --- Node name is '|acceler:ACC|RGACC7' from file "acceler.tdf" line 82, column 7 --- Equation name is '_LC4_E4', type is buried -_LC4_E4 = DFFE( d7, GLOBAL( /mr), VCC, VCC, _LC2_F15); - --- Node name is '|acceler:ACC|START_ACC' from file "acceler.tdf" line 237, column 14 --- Equation name is '_LC8_F9', type is buried -_LC8_F9 = LCELL( _EQ246); - _EQ246 = _LC6_F9 - # _LC8_C21 - # !_LC8_F15; - --- Node name is '|acceler:ACC|WR_C7' from file "acceler.tdf" line 220, column 10 --- Equation name is '_LC7_F24', type is buried -_LC7_F24 = DFFE( _EQ247, GLOBAL( TG42), VCC, VCC, VCC); - _EQ247 = _LC7_D27 - # _LC4_F24 - # /wr - # _LC5_F24; - --- Node name is '|acceler:ACC|XAGR0' from file "acceler.tdf" line 108, column 6 --- Equation name is '_LC4_F5', type is buried -_LC4_F5 = DFFE( _EQ248, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ248 = !_LC1_F4 & !_LC3_E13 & _LC4_F5 - # _LC1_F4 & !_LC3_E13 & !_LC4_F5; - --- Node name is '|acceler:ACC|XAGR1' from file "acceler.tdf" line 108, column 6 --- Equation name is '_LC5_F18', type is buried -_LC5_F18 = DFFE( _EQ249, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ249 = _LC2_F4 & !_LC3_E13; - --- Node name is '|acceler:ACC|XAGR2' from file "acceler.tdf" line 108, column 6 --- Equation name is '_LC4_F2', type is buried -_LC4_F2 = DFFE( _EQ250, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ250 = !_LC3_E13 & _LC3_F4 & !_LC4_F4 - # !_LC3_E13 & !_LC3_F4 & _LC4_F4; - --- Node name is '|acceler:ACC|XAGR3' from file "acceler.tdf" line 108, column 6 --- Equation name is '_LC3_F18', type is buried -_LC3_F18 = DFFE( _EQ251, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ251 = !_LC3_E13 & _LC5_F4 & !_LC6_F4 - # !_LC3_E13 & !_LC5_F4 & _LC6_F4; - --- Node name is '|acceler:ACC|XAGR4' from file "acceler.tdf" line 108, column 6 --- Equation name is '_LC1_F2', type is buried -_LC1_F2 = DFFE( _EQ252, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ252 = !_LC3_E13 & _LC7_F4 & !_LC8_F4 - # !_LC3_E13 & !_LC7_F4 & _LC8_F4; - --- Node name is '|acceler:ACC|XAGR5' from file "acceler.tdf" line 108, column 6 --- Equation name is '_LC1_F18', type is buried -_LC1_F18 = DFFE( _EQ253, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ253 = _LC1_F6 & !_LC2_F6 & !_LC3_E13 - # !_LC1_F6 & _LC2_F6 & !_LC3_E13; - --- Node name is '|acceler:ACC|XAGR6' from file "acceler.tdf" line 108, column 6 --- Equation name is '_LC3_F13', type is buried -_LC3_F13 = DFFE( _EQ254, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ254 = !_LC3_E13 & _LC3_F6 & !_LC4_F6 - # !_LC3_E13 & !_LC3_F6 & _LC4_F6; - --- Node name is '|acceler:ACC|XAGR7' from file "acceler.tdf" line 108, column 6 --- Equation name is '_LC2_F13', type is buried -_LC2_F13 = DFFE( _EQ255, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ255 = !_LC3_E13 & _LC5_F6 & !_LC6_F6 - # !_LC3_E13 & !_LC5_F6 & _LC6_F6; - --- Node name is '|acceler:ACC|XCNT0' from file "acceler.tdf" line 110, column 6 --- Equation name is '_LC2_F2', type is buried -_LC2_F2 = DFFE( _EQ256, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ256 = A10 & _LC3_E13 - # !_LC3_E13 & _LC7_F6; - --- Node name is '|acceler:ACC|XCNT1' from file "acceler.tdf" line 110, column 6 --- Equation name is '_LC8_F2', type is buried -_LC8_F2 = DFFE( _EQ257, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ257 = a11 & _LC3_E13 - # !_LC3_E13 & _LC8_F6; - --- Node name is '|acceler:ACC|XCNT2' from file "acceler.tdf" line 110, column 6 --- Equation name is '_LC1_F8', type is buried --- |acceler:ACC|XCNT2 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A12 -_LC1_F8 = DFFE(( _EQ258 & !_LC4_C14 # A12 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ258 = _LC1_F8 & !_LC8_F6_CARRY - # !_LC1_F8 & _LC8_F6_CARRY; - --- Node name is '|acceler:ACC|XCNT3' from file "acceler.tdf" line 110, column 6 --- Equation name is '_LC2_F8', type is buried --- |acceler:ACC|XCNT3 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A13 -_LC2_F8 = DFFE(( _EQ259 & !_LC4_C14 # A13 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ259 = !_LC1_F8_CARRY & _LC2_F8 - # _LC1_F8_CARRY & !_LC2_F8; - --- Node name is '|acceler:ACC|XCNT4' from file "acceler.tdf" line 110, column 6 --- Equation name is '_LC3_F8', type is buried --- |acceler:ACC|XCNT4 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A14 -_LC3_F8 = DFFE(( _EQ260 & !_LC4_C14 # A14 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ260 = !_LC2_F8_CARRY & _LC3_F8 - # _LC2_F8_CARRY & !_LC3_F8; - --- Node name is '|acceler:ACC|XCNT5' from file "acceler.tdf" line 110, column 6 --- Equation name is '_LC4_F8', type is buried --- |acceler:ACC|XCNT5 is in Up/Down Counter Mode --- synchronous load = !_LC4_C14 --- synchronous data = A15 -_LC4_F8 = DFFE(( _EQ261 & !_LC4_C14 # A15 & _LC4_C14), GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ261 = !_LC3_F8_CARRY & _LC4_F8 - # _LC3_F8_CARRY & !_LC4_F8; - --- Node name is '|acceler:ACC|XCNT6' from file "acceler.tdf" line 110, column 6 --- Equation name is '_LC5_F8', type is buried --- |acceler:ACC|XCNT6 is in Clearable Counter Mode --- synchronous clear = !_LC4_C14 -_LC5_F8 = DFFE( _EQ262 & !_LC4_C14, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ262 = !_LC4_F8_CARRY & _LC5_F8 - # _LC4_F8_CARRY & !_LC5_F8; - --- Node name is '|acceler:ACC|XCNT7' from file "acceler.tdf" line 110, column 6 --- Equation name is '_LC6_F8', type is buried -_LC6_F8 = DFFE( _EQ263, GLOBAL( TG42), VCC, VCC, _LC8_F3); - _EQ263 = !_LC3_E13 & !_LC5_F8_CARRY & _LC6_F8 - # !_LC3_E13 & _LC5_F8_CARRY & !_LC6_F8; - --- Node name is '|acceler:ACC|XMD0' from file "acceler.tdf" line 92, column 5 --- Equation name is '_LC3_D8', type is buried -_LC3_D8 = DFFE( _EQ264, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ264 = _EC1_D & !_LC4_D2 & _LC4_D18 & !_LC5_D18 - # !_EC1_D & _LC4_D2 & !_LC5_D18 - # _EC1_D & !_LC4_D18 & _LC5_D18 - # _LC4_D2 & !_LC4_D18 - # _EC1_D & _LC4_D2 & _LC5_D18; - --- Node name is '|acceler:ACC|XMD1' from file "acceler.tdf" line 92, column 5 --- Equation name is '_LC1_D8', type is buried -_LC1_D8 = DFFE( _EQ265, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ265 = _EC14_D & _LC4_D18 & !_LC5_D8 & !_LC5_D18 - # !_EC14_D & _LC5_D8 & !_LC5_D18 - # _EC14_D & !_LC4_D18 & _LC5_D18 - # !_LC4_D18 & _LC5_D8 - # _EC14_D & _LC5_D8 & _LC5_D18; - --- Node name is '|acceler:ACC|XMD2' from file "acceler.tdf" line 92, column 5 --- Equation name is '_LC7_D8', type is buried -_LC7_D8 = DFFE( _EQ266, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ266 = _EC2_D & !_LC4_D8 & _LC4_D18 & !_LC5_D18 - # !_EC2_D & _LC4_D8 & !_LC5_D18 - # _EC2_D & !_LC4_D18 & _LC5_D18 - # _LC4_D8 & !_LC4_D18 - # _EC2_D & _LC4_D8 & _LC5_D18; - --- Node name is '|acceler:ACC|XMD3' from file "acceler.tdf" line 92, column 5 --- Equation name is '_LC8_D8', type is buried -_LC8_D8 = DFFE( _EQ267, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ267 = _EC11_D & !_LC2_D8 & _LC4_D18 & !_LC5_D18 - # !_EC11_D & _LC2_D8 & !_LC5_D18 - # _EC11_D & !_LC4_D18 & _LC5_D18 - # _LC2_D8 & !_LC4_D18 - # _EC11_D & _LC2_D8 & _LC5_D18; - --- Node name is '|acceler:ACC|XMD4' from file "acceler.tdf" line 92, column 5 --- Equation name is '_LC5_D4', type is buried -_LC5_D4 = DFFE( _EQ268, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ268 = _EC4_D & !_LC4_D4 & _LC4_D18 & !_LC5_D18 - # !_EC4_D & _LC4_D4 & !_LC5_D18 - # _EC4_D & !_LC4_D18 & _LC5_D18 - # _LC4_D4 & !_LC4_D18 - # _EC4_D & _LC4_D4 & _LC5_D18; - --- Node name is '|acceler:ACC|XMD5' from file "acceler.tdf" line 92, column 5 --- Equation name is '_LC5_D2', type is buried -_LC5_D2 = DFFE( _EQ269, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ269 = _EC10_D & !_LC2_D2 & _LC4_D18 & !_LC5_D18 - # !_EC10_D & _LC2_D2 & !_LC5_D18 - # _EC10_D & !_LC4_D18 & _LC5_D18 - # _LC2_D2 & !_LC4_D18 - # _EC10_D & _LC2_D2 & _LC5_D18; - --- Node name is '|acceler:ACC|XMD6' from file "acceler.tdf" line 92, column 5 --- Equation name is '_LC6_D2', type is buried -_LC6_D2 = DFFE( _EQ270, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ270 = _EC3_D & !_LC3_D2 & _LC4_D18 & !_LC5_D18 - # !_EC3_D & _LC3_D2 & !_LC5_D18 - # _EC3_D & !_LC4_D18 & _LC5_D18 - # _LC3_D2 & !_LC4_D18 - # _EC3_D & _LC3_D2 & _LC5_D18; - --- Node name is '|acceler:ACC|XMD7' from file "acceler.tdf" line 92, column 5 --- Equation name is '_LC1_D2', type is buried -_LC1_D2 = DFFE( _EQ271, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ271 = _EC9_D & _LC4_D18 & !_LC5_D18 & !_LC8_D2 - # !_EC9_D & !_LC5_D18 & _LC8_D2 - # _EC9_D & !_LC4_D18 & _LC5_D18 - # _EC9_D & _LC5_D18 & _LC8_D2 - # !_LC4_D18 & _LC8_D2; - --- Node name is '|acceler:ACC|:229' from file "acceler.tdf" line 64, column 4 --- Equation name is '_LC6_D34', type is buried -_LC6_D34 = DFFE( _LC8_D2, _LC5_D30, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:230' from file "acceler.tdf" line 64, column 4 --- Equation name is '_LC7_D34', type is buried -_LC7_D34 = DFFE( _LC3_D2, _LC5_D30, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:231' from file "acceler.tdf" line 64, column 4 --- Equation name is '_LC8_D34', type is buried -_LC8_D34 = DFFE( _LC2_D2, _LC5_D30, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:232' from file "acceler.tdf" line 64, column 4 --- Equation name is '_LC6_D30', type is buried -_LC6_D30 = DFFE( _LC4_D4, _LC5_D30, !_LC2_D30, VCC, VCC); - --- Node name is '|acceler:ACC|:233' from file "acceler.tdf" line 64, column 4 --- Equation name is '_LC7_D30', type is buried -_LC7_D30 = DFFE( _LC2_D8, _LC5_D30, !_LC2_D30, VCC, VCC); - --- Node name is '|acceler:ACC|:234' from file "acceler.tdf" line 64, column 4 --- Equation name is '_LC3_D30', type is buried -_LC3_D30 = DFFE( _LC4_D8, _LC5_D30, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:235' from file "acceler.tdf" line 64, column 4 --- Equation name is '_LC3_D36', type is buried -_LC3_D36 = DFFE( _LC5_D8, _LC5_D30, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:236' from file "acceler.tdf" line 64, column 4 --- Equation name is '_LC4_D30', type is buried -_LC4_D30 = DFFE( _LC4_D2, _LC5_D30, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:237' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC1_D17', type is buried -_LC1_D17 = DFFE( _EQ272, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ272 = _LC2_D7 & !_LC4_A1 - # _EC9_D & _LC4_A1; - --- Node name is '|acceler:ACC|:238' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC6_D19', type is buried -_LC6_D19 = DFFE( _EQ273, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ273 = _LC1_D5 & !_LC4_A1 - # _EC3_D & _LC4_A1; - --- Node name is '|acceler:ACC|:239' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC1_D21', type is buried -_LC1_D21 = DFFE( _EQ274, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ274 = !_LC4_A1 & _LC5_D6 - # _EC10_D & _LC4_A1; - --- Node name is '|acceler:ACC|:240' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC5_D24', type is buried -_LC5_D24 = DFFE( _EQ275, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ275 = !_LC4_A1 & _LC8_D17 - # _EC4_D & _LC4_A1; - --- Node name is '|acceler:ACC|:241' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC3_D28', type is buried -_LC3_D28 = DFFE( _EQ276, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ276 = !_LC4_A1 & _LC7_D17 - # _EC11_D & _LC4_A1; - --- Node name is '|acceler:ACC|:242' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC5_D33', type is buried -_LC5_D33 = DFFE( _EQ277, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ277 = !_LC4_A1 & _LC4_D7 - # _EC2_D & _LC4_A1; - --- Node name is '|acceler:ACC|:243' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC3_D35', type is buried -_LC3_D35 = DFFE( _EQ278, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ278 = !_LC4_A1 & _LC5_D7 - # _EC14_D & _LC4_A1; - --- Node name is '|acceler:ACC|:244' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC3_A1', type is buried -_LC3_A1 = DFFE( _EQ279, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ279 = _LC3_D17 & !_LC4_A1 - # _EC1_D & _LC4_A1; - --- Node name is '|acceler:ACC|:245' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC6_D3', type is buried -_LC6_D3 = DFFE( _EQ280, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ280 = _EC9_D & _LC4_A1 - # _LC3_D7 & !_LC4_A1; - --- Node name is '|acceler:ACC|:246' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC3_D5', type is buried -_LC3_D5 = DFFE( _EQ281, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ281 = _EC3_D & _LC4_A1 - # _LC2_D5 & !_LC4_A1; - --- Node name is '|acceler:ACC|:247' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC4_D5', type is buried -_LC4_D5 = DFFE( _EQ282, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ282 = _EC10_D & _LC4_A1 - # !_LC4_A1 & _LC6_D5; - --- Node name is '|acceler:ACC|:248' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC8_D5', type is buried -_LC8_D5 = DFFE( _EQ283, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ283 = _EC4_D & _LC4_A1 - # !_LC4_A1 & _LC5_D17; - --- Node name is '|acceler:ACC|:249' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC8_D19', type is buried -_LC8_D19 = DFFE( _EQ284, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ284 = _EC11_D & _LC4_A1 - # !_LC4_A1 & _LC4_D17; - --- Node name is '|acceler:ACC|:250' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC2_D21', type is buried -_LC2_D21 = DFFE( _EQ285, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ285 = _EC2_D & _LC4_A1 - # !_LC4_A1 & _LC7_D7; - --- Node name is '|acceler:ACC|:251' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC5_D25', type is buried -_LC5_D25 = DFFE( _EQ286, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ286 = _EC14_D & _LC4_A1 - # !_LC4_A1 & _LC6_D7; - --- Node name is '|acceler:ACC|:252' from file "acceler.tdf" line 65, column 5 --- Equation name is '_LC2_D28', type is buried -_LC2_D28 = DFFE( _EQ287, GLOBAL( TG42), VCC, VCC, !_LC7_A1); - _EQ287 = _EC1_D & _LC4_A1 - # !_LC4_A1 & _LC6_D17; - --- Node name is '|acceler:ACC|:253' from file "acceler.tdf" line 91, column 4 --- Equation name is '_LC8_D2', type is buried -_LC8_D2 = LCELL( _EQ288); - _EQ288 = _LC6_F16 & md15 - # !_LC6_F16 & md7; - --- Node name is '|acceler:ACC|:254' from file "acceler.tdf" line 91, column 4 --- Equation name is '_LC3_D2', type is buried -_LC3_D2 = LCELL( _EQ289); - _EQ289 = _LC6_F16 & md14 - # !_LC6_F16 & md6; - --- Node name is '|acceler:ACC|:255' from file "acceler.tdf" line 91, column 4 --- Equation name is '_LC2_D2', type is buried -_LC2_D2 = LCELL( _EQ290); - _EQ290 = _LC6_F16 & md13 - # !_LC6_F16 & md5; - --- Node name is '|acceler:ACC|:256' from file "acceler.tdf" line 91, column 4 --- Equation name is '_LC4_D4', type is buried -_LC4_D4 = LCELL( _EQ291); - _EQ291 = _LC6_F16 & md12 - # !_LC6_F16 & md4; - --- Node name is '|acceler:ACC|:257' from file "acceler.tdf" line 91, column 4 --- Equation name is '_LC2_D8', type is buried -_LC2_D8 = LCELL( _EQ292); - _EQ292 = _LC6_F16 & md11 - # !_LC6_F16 & md3; - --- Node name is '|acceler:ACC|:258' from file "acceler.tdf" line 91, column 4 --- Equation name is '_LC4_D8', type is buried -_LC4_D8 = LCELL( _EQ293); - _EQ293 = _LC6_F16 & md10 - # !_LC6_F16 & md2; - --- Node name is '|acceler:ACC|:259' from file "acceler.tdf" line 91, column 4 --- Equation name is '_LC5_D8', type is buried -_LC5_D8 = LCELL( _EQ294); - _EQ294 = _LC6_F16 & md9 - # !_LC6_F16 & md1; - --- Node name is '|acceler:ACC|:260' from file "acceler.tdf" line 91, column 4 --- Equation name is '_LC4_D2', type is buried -_LC4_D2 = LCELL( _EQ295); - _EQ295 = _LC6_F16 & md8 - # !_LC6_F16 & md0; - --- Node name is '|acceler:ACC|:262' from file "acceler.tdf" line 95, column 9 --- Equation name is '_LC4_F15', type is buried -_LC4_F15 = LCELL( _EQ296); - _EQ296 = _LC3_F10 & !_LC5_F10 & !_LC6_F5; - --- Node name is '|acceler:ACC|:263' from file "acceler.tdf" line 95, column 9 --- Equation name is '_LC7_F11', type is buried -_LC7_F11 = LCELL( _EQ297); - _EQ297 = _LC5_F10 & !_LC6_F5; - --- Node name is '|acceler:ACC|:264' from file "acceler.tdf" line 95, column 9 --- Equation name is '_LC5_F15', type is buried -_LC5_F15 = LCELL( _EQ298); - _EQ298 = _LC5_F10 & _LC6_F5; - --- Node name is '|acceler:ACC|:265' from file "acceler.tdf" line 95, column 9 --- Equation name is '_LC1_F15', type is buried -_LC1_F15 = LCELL( _EQ299); - _EQ299 = !_LC3_F10 & !_LC5_F10 & _LC6_F5; - --- Node name is '|acceler:ACC|:266' from file "acceler.tdf" line 95, column 9 --- Equation name is '_LC7_F15', type is buried -_LC7_F15 = LCELL( _LC5_F10); - --- Node name is '|acceler:ACC|:267' from file "acceler.tdf" line 95, column 9 --- Equation name is '_LC6_F10', type is buried -_LC6_F10 = LCELL( _EQ300); - _EQ300 = _LC3_F10 & _LC5_F10; - --- Node name is '|acceler:ACC|:268' from file "acceler.tdf" line 95, column 9 --- Equation name is '_LC8_F15', type is buried -_LC8_F15 = LCELL( _EQ301); - _EQ301 = !_LC3_F10 & _LC6_F5 - # !_LC3_F10 & _LC5_F10 - # _LC5_F10 & _LC6_F5 - # _LC3_F10 & !_LC6_F5; - --- Node name is '|acceler:ACC|:420' from file "acceler.tdf" line 165, column 15 --- Equation name is '_LC1_F10', type is buried -_LC1_F10 = DFFE( _EQ302, _LC2_D27, VCC, VCC, VCC); - _EQ302 = /io & _LC3_F9 - # _LC3_E4 & !_LC3_F9; - --- Node name is '|acceler:ACC|:424' from file "acceler.tdf" line 190, column 17 --- Equation name is '_LC2_F15', type is buried -_LC2_F15 = DFFE( _EQ303, _LC2_D27, VCC, VCC, VCC); - _EQ303 = _LC1_F15 & /m1 & /rf; - --- Node name is '|acceler:ACC|:425' from file "acceler.tdf" line 196, column 15 --- Equation name is '_LC3_F24', type is buried -_LC3_F24 = DFFE( _EQ304, GLOBAL( TG42), VCC, VCC, VCC); - _EQ304 = _LC7_D27 - # /wr - # !_LC1_F24; - --- Node name is '|acceler:ACC|:426' from file "acceler.tdf" line 196, column 36 --- Equation name is '_LC1_F24', type is buried -_LC1_F24 = DFFE( _EQ305, GLOBAL( TG42), VCC, VCC, VCC); - _EQ305 = !_LC4_D26 & !_LC5_D34 & _LC6_F24 & _LC7_D19; - --- Node name is '|acceler:ACC|~427~1' from file "acceler.tdf" line 199, column 7 --- Equation name is '_LC4_C14', type is buried --- synthesized logic cell -!_LC4_C14 = _LC4_C14~NOT; -_LC4_C14~NOT = LCELL(!_LC3_E13); - --- Node name is '|acceler:ACC|:427' from file "acceler.tdf" line 199, column 7 --- Equation name is '_LC3_E13', type is buried --- |acceler:ACC|:427 is in Up/Down Counter Mode -_LC3_E13 = DFFE( _LC8_F9, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:428' from file "acceler.tdf" line 210, column 23 --- Equation name is '_LC2_F3', type is buried -_LC2_F3 = DFFE( _EQ306, GLOBAL( TG42), VCC, VCC, VCC); - _EQ306 = _LC7_F1 & !/rd - # _LC3_F35 & !/wr; - --- Node name is '|acceler:ACC|:429' from file "acceler.tdf" line 213, column 18 --- Equation name is '_LC7_F3', type is buried -_LC7_F3 = LCELL( _EQ307); - _EQ307 = _LC2_F3 & !_LC4_F3 & _LC7_F15 - # _LC8_F9; - --- Node name is '|acceler:ACC|:432' from file "acceler.tdf" line 220, column 23 --- Equation name is '_LC4_F24', type is buried -_LC4_F24 = DFFE(!_LC7_D27, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:433' from file "acceler.tdf" line 220, column 52 --- Equation name is '_LC5_F24', type is buried -_LC5_F24 = DFFE( _EQ308, GLOBAL( TG42), VCC, VCC, VCC); - _EQ308 = _LC8_F24 - # !_LC7_D19 - # _LC5_D34 - # !_LC4_D26; - --- Node name is '|acceler:ACC|:435' from file "acceler.tdf" line 223, column 39 --- Equation name is '_LC8_F3', type is buried -_LC8_F3 = LCELL( _EQ309); - _EQ309 = !_LC7_F24 - # _LC2_F3 & !_LC4_F3 & _LC6_F10; - --- Node name is '|acceler:ACC|:438' from file "acceler.tdf" line 237, column 20 --- Equation name is '_LC6_F9', type is buried -_LC6_F9 = LCELL( _EQ310); - _EQ310 = /mr - # !/rf - # !/m1 - # !_LC3_F9; - --- Node name is '|acceler:ACC|:439' from file "acceler.tdf" line 239, column 14 --- Equation name is '_LC4_F11', type is buried -_LC4_F11 = LCELL( _EQ311); - _EQ311 = _LC4_F15 & !_LC8_F9; - --- Node name is '|acceler:ACC|:440' from file "acceler.tdf" line 262, column 19 --- Equation name is '_LC5_D13', type is buried -_LC5_D13 = DFFE( _EQ312, _LC2_D27, VCC, VCC, VCC); - _EQ312 = _LC1_D13 & _LC6_D18 & !_LC7_D1 & !/m1; - --- Node name is '|acceler:ACC|:441' from file "acceler.tdf" line 263, column 11 --- Equation name is '_LC1_D13', type is buried -_LC1_D13 = LCELL( _EQ313); - _EQ313 = !D0 & !D1 & !d3 & !d4 - # !D0 & D1 & !d3 & d4 - # D0 & !D1 & d3 & !d4 - # D0 & D1 & d3 & d4; - --- Node name is '|acceler:ACC|:442' from file "acceler.tdf" line 267, column 11 --- Equation name is '_LC6_D18', type is buried -_LC6_D18 = LCELL( _EQ314); - _EQ314 = !d2 & !d5 & d6 & !d7 - # d2 & d5 & d6 & !d7; - --- Node name is '|acceler:ACC|:443' from file "acceler.tdf" line 271, column 31 --- Equation name is '_LC8_F10', type is buried -_LC8_F10 = DFFE( _LC2_F10, _LC2_D27, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:444' from file "acceler.tdf" line 275, column 7 --- Equation name is '_LC6_F16', type is buried -_LC6_F16 = DFFE( _LC1_C22, GLOBAL( TG42), VCC, VCC, _LC2_F32); - --- Node name is '|acceler:ACC|:445' from file "acceler.tdf" line 284, column 23 --- Equation name is '_LC3_D18', type is buried -_LC3_D18 = LCELL( _EQ315C); - _EQ315C = _EQ315 & CASCADE( _EQ316C); - _EQ315 = d5 & d7; - --- Node name is '|acceler:ACC|:446' from file "acceler.tdf" line 285, column 23 --- Equation name is '_LC5_D5', type is buried -_LC5_D5 = LCELL( _EQ317); - _EQ317 = _EC3_D & _EC4_D & _EC9_D & _EC10_D; - --- Node name is '|acceler:ACC|:447' from file "acceler.tdf" line 285, column 52 --- Equation name is '_LC3_D10', type is buried -_LC3_D10 = LCELL( _EQ318); - _EQ318 = _EC1_D & _EC2_D & _EC11_D & _EC14_D; - --- Node name is '|acceler:ACC|:448' from file "acceler.tdf" line 297, column 7 --- Equation name is '_LC1_D15', type is buried -_LC1_D15 = LCELL( _EQ319); - _EQ319 = _LC1_C14 & _LC4_A28; - --- Node name is '|acceler:ACC|:449' from file "acceler.tdf" line 307, column 7 --- Equation name is '_LC4_A1', type is buried -_LC4_A1 = LCELL( _EQ320); - _EQ320 = /io & _LC6_F10; - --- Node name is '|acceler:ACC|:450' from file "acceler.tdf" line 312, column 14 --- Equation name is '_LC5_D30', type is buried -_LC5_D30 = DFFE( _LC4_A28, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|acceler:ACC|:451' from file "acceler.tdf" line 322, column 16 --- Equation name is '_LC8_D18', type is buried -_LC8_D18 = LCELL( _EQ321); - _EQ321 = !d6 & d7 & !_LC7_D1; - --- Node name is '|acceler:ACC|:455' from file "acceler.tdf" line 363, column 13 --- Equation name is '_LC1_F11', type is buried -_LC1_F11 = LCELL( _EQ322); - _EQ322 = _LC7_F11 & !_LC7_F32 & _LC8_F11 - # _LC8_F9; - --- Node name is '|acceler:ACC|:490' from file "acceler.tdf" line 137, column 33 --- Equation name is '_LC4_D1', type is buried -_LC4_D1 = LCELL( _EQ323); - _EQ323 = D1 & !d2 & !d4 & !d5 - # !D1 & d2 & d5 - # !D1 & d2 & d4; - --- Node name is '|acceler:ACC|~492~1' from file "acceler.tdf" line 134, column 37 --- Equation name is '_LC3_D1', type is buried --- synthesized logic cell -_LC3_D1 = LCELL( _EQ324); - _EQ324 = D0 & d3 & d6; - --- Node name is '|acceler:ACC|~521~1' from file "acceler.tdf" line 150, column 20 --- Equation name is '_LC1_E22', type is buried --- synthesized logic cell -_LC1_E22 = LCELL( _EQ325C); - _EQ325C = _EQ325; - _EQ325 = D0 & !D1 & d2; - --- Node name is '|acceler:ACC|~521~2' from file "acceler.tdf" line 150, column 20 --- Equation name is '_LC2_E22', type is buried --- synthesized logic cell -_LC2_E22 = LCELL( _EQ326C); - _EQ326C = _EQ326 & CASCADE( _EQ325C); - _EQ326 = d3 & !d4 & d6; - --- Node name is '|acceler:ACC|~535~1' from file "acceler.tdf" line 154, column 20 --- Equation name is '_LC3_E22', type is buried --- synthesized logic cell -_LC3_E22 = LCELL( _EQ327C); - _EQ327C = _EQ327; - _EQ327 = d3 & !d4 & d6; - --- Node name is '|acceler:ACC|~535~2' from file "acceler.tdf" line 154, column 20 --- Equation name is '_LC4_E22', type is buried --- synthesized logic cell -_LC4_E22 = LCELL( _EQ328C); - _EQ328C = _EQ328 & CASCADE( _EQ327C); - _EQ328 = D0 & !D1 & d2 & _LC6_E22; - --- Node name is '|acceler:ACC|:548' from file "acceler.tdf" line 166, column 24 --- Equation name is '_LC4_F10', type is buried -_LC4_F10 = LCELL( _EQ329); - _EQ329 = _LC2_F10 & /reset; - --- Node name is '|acceler:ACC|~588~1' from file "acceler.tdf" line 178, column 39 --- Equation name is '_LC1_D1', type is buried --- synthesized logic cell -_LC1_D1 = LCELL( _EQ330C); - _EQ330C = _EQ330; - _EQ330 = D0 & D1 & !_LC7_D1; - --- Node name is '|acceler:ACC|~588~2' from file "acceler.tdf" line 178, column 39 --- Equation name is '_LC2_D1', type is buried --- synthesized logic cell -_LC2_D1 = LCELL( _EQ331C); - _EQ331C = _EQ331 & CASCADE( _EQ330C); - _EQ331 = !d2 & d4 & d6; - --- Node name is '|acceler:ACC|:597' from file "acceler.tdf" line 196, column 82 --- Equation name is '_LC4_F18', type is buried -_LC4_F18 = LCELL( _EQ332); - _EQ332 = !_LC3_F24 - # _LC2_F11 & !_LC4_F3 & _LC5_F15; - --- Node name is '|acceler:ACC|:602' from file "acceler.tdf" line 200, column 29 --- Equation name is '_LC7_C36', type is buried -_LC7_C36 = LCELL( _EQ333); - _EQ333 = !_LC2_C19 & _LC3_C36 - # _LC2_C19 & !_LC3_C36; - --- Node name is '|acceler:ACC|:604' from file "acceler.tdf" line 200, column 29 --- Equation name is '_LC2_C19_CARRY', type is buried --- |acceler:ACC|:604 is in Up/Down Counter Mode -_LC2_C19_CARRY = CARRY( _EQ334); - _EQ334 = _LC2_C19 & _LC3_C36; - --- Node name is '|acceler:ACC|:608' from file "acceler.tdf" line 200, column 29 --- Equation name is '_LC3_C19_CARRY', type is buried --- |acceler:ACC|:608 is in Up/Down Counter Mode -_LC3_C19_CARRY = CARRY( _EQ335); - _EQ335 = _LC2_C19_CARRY & _LC3_C19; - --- Node name is '|acceler:ACC|:612' from file "acceler.tdf" line 200, column 29 --- Equation name is '_LC4_C19_CARRY', type is buried --- |acceler:ACC|:612 is in Up/Down Counter Mode -_LC4_C19_CARRY = CARRY( _EQ336); - _EQ336 = _LC3_C19_CARRY & _LC4_C19; - --- Node name is '|acceler:ACC|:616' from file "acceler.tdf" line 200, column 29 --- Equation name is '_LC5_C19_CARRY', type is buried --- |acceler:ACC|:616 is in Up/Down Counter Mode -_LC5_C19_CARRY = CARRY( _EQ337); - _EQ337 = _LC4_C19_CARRY & _LC5_C19; - --- Node name is '|acceler:ACC|:620' from file "acceler.tdf" line 200, column 29 --- Equation name is '_LC6_C19_CARRY', type is buried --- |acceler:ACC|:620 is in Up/Down Counter Mode -_LC6_C19_CARRY = CARRY( _EQ338); - _EQ338 = _LC5_C19_CARRY & _LC6_C19; - --- Node name is '|acceler:ACC|:624' from file "acceler.tdf" line 200, column 29 --- Equation name is '_LC7_C19_CARRY', type is buried --- |acceler:ACC|:624 is in Up/Down Counter Mode -_LC7_C19_CARRY = CARRY( _EQ339); - _EQ339 = _LC6_C19_CARRY & _LC7_C19; - --- Node name is '|acceler:ACC|:676' from file "acceler.tdf" line 217, column 37 --- Equation name is '_LC4_E11', type is buried -_LC4_E11 = LCELL( _EQ340); - _EQ340 = _LC1_E17 & _LC2_E17 - # !_LC1_E17 & !_LC2_E17; - --- Node name is '|acceler:ACC|:678' from file "acceler.tdf" line 217, column 37 --- Equation name is '_LC4_E11_CARRY', type is buried -_LC4_E11_CARRY = CARRY( _EQ341); - _EQ341 = _LC1_E17 - # _LC2_E17; - --- Node name is '|acceler:ACC|:683' from file "acceler.tdf" line 217, column 37 --- Equation name is '_LC5_E11_CARRY', type is buried --- |acceler:ACC|:683 is in Up/Down Counter Mode -_LC5_E11_CARRY = CARRY( _EQ342); - _EQ342 = _LC5_E11 - # _LC4_E11_CARRY; - --- Node name is '|acceler:ACC|:688' from file "acceler.tdf" line 217, column 37 --- Equation name is '_LC6_E11_CARRY', type is buried --- |acceler:ACC|:688 is in Up/Down Counter Mode -_LC6_E11_CARRY = CARRY( _EQ343); - _EQ343 = _LC6_E11 - # _LC5_E11_CARRY; - --- Node name is '|acceler:ACC|:694' from file "acceler.tdf" line 217, column 37 --- Equation name is '_LC7_E11_CARRY', type is buried --- |acceler:ACC|:694 is in Up/Down Counter Mode -_LC7_E11_CARRY = CARRY( _EQ344); - _EQ344 = _LC7_E11 - # _LC6_E11_CARRY; - --- Node name is '|acceler:ACC|:699' from file "acceler.tdf" line 217, column 37 --- Equation name is '_LC8_E11_CARRY', type is buried --- |acceler:ACC|:699 is in Up/Down Counter Mode -_LC8_E11_CARRY = CARRY( _EQ345); - _EQ345 = _LC8_E11 - # _LC7_E11_CARRY; - --- Node name is '|acceler:ACC|:704' from file "acceler.tdf" line 217, column 37 --- Equation name is '_LC1_E13_CARRY', type is buried --- |acceler:ACC|:704 is in Up/Down Counter Mode -_LC1_E13_CARRY = CARRY( _EQ346); - _EQ346 = _LC1_E13 - # _LC8_E11_CARRY; - --- Node name is '|acceler:ACC|:708' from file "acceler.tdf" line 217, column 37 --- Equation name is '_LC2_E13_CARRY', type is buried -_LC2_E13_CARRY = CARRY( _EQ347); - _EQ347 = !_LC1_E13_CARRY & !_LC4_E13 - # _LC1_E13_CARRY & _LC4_E13; - --- Node name is '|acceler:ACC|:734' from file "acceler.tdf" line 217, column 25 --- Equation name is '_LC3_E13_CARRY', type is buried --- |acceler:ACC|:734 is in Up/Down Counter Mode -_LC3_E13_CARRY = CARRY( _EQ348); - _EQ348 = _LC2_E13_CARRY & !_LC3_E13 - # _LC3_E13 & _LC4_E4; - --- Node name is '|acceler:ACC|:735' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC1_F4_CARRY', type is buried --- |acceler:ACC|:735 is in Up/Down Counter Mode -!_LC1_F4_CARRY = _LC1_F4_CARRY~NOT; -_LC1_F4_CARRY~NOT = CARRY( _EQ349); - _EQ349 = !_LC4_F5 - # !_LC1_F4; - --- Node name is '|acceler:ACC|:748' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC2_F4', type is buried -_LC2_F4 = LCELL( _EQ350); - _EQ350 = _LC1_F4_CARRY & !_LC5_F18 & !_LC7_F5 - # _LC1_F4_CARRY & _LC5_F18 & _LC7_F5 - # !_LC1_F4_CARRY & !_LC5_F18 & _LC7_F5 - # !_LC1_F4_CARRY & _LC5_F18 & !_LC7_F5; - --- Node name is '|acceler:ACC|~751~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC3_F4', type is buried --- synthesized logic cell -_LC3_F4 = LCELL( _LC2_F4_CARRY); - --- Node name is '|acceler:ACC|~751~2' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC3_F4_CARRY', type is buried --- synthesized logic cell -_LC3_F4_CARRY = CARRY( _LC2_F4_CARRY); - --- Node name is '|acceler:ACC|:751' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC2_F4_CARRY', type is buried -_LC2_F4_CARRY = CARRY( _EQ351); - _EQ351 = _LC5_F18 & _LC7_F5 - # _LC1_F4_CARRY & _LC5_F18 - # _LC1_F4_CARRY & _LC7_F5; - --- Node name is '|acceler:ACC|~758~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC4_F4', type is buried --- synthesized logic cell -_LC4_F4 = LCELL( _EQ352); - _EQ352 = _LC1_F13 & !_LC4_F2 - # !_LC1_F13 & _LC4_F2; - --- Node name is '|acceler:ACC|~761~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC5_F4', type is buried --- synthesized logic cell -_LC5_F4 = LCELL( _LC4_F4_CARRY); - --- Node name is '|acceler:ACC|~761~2' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC5_F4_CARRY', type is buried --- synthesized logic cell -_LC5_F4_CARRY = CARRY( _LC4_F4_CARRY); - --- Node name is '|acceler:ACC|:761' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC4_F4_CARRY', type is buried -_LC4_F4_CARRY = CARRY( _EQ353); - _EQ353 = _LC3_F4_CARRY & _LC4_F2 - # _LC1_F13 & _LC3_F4_CARRY - # _LC1_F13 & _LC4_F2; - --- Node name is '|acceler:ACC|~768~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC6_F4', type is buried --- synthesized logic cell -_LC6_F4 = LCELL( _EQ354); - _EQ354 = !_LC3_F18 & _LC6_F13 - # _LC3_F18 & !_LC6_F13; - --- Node name is '|acceler:ACC|~771~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC7_F4', type is buried --- synthesized logic cell -_LC7_F4 = LCELL( _LC6_F4_CARRY); - --- Node name is '|acceler:ACC|~771~2' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC7_F4_CARRY', type is buried --- synthesized logic cell -_LC7_F4_CARRY = CARRY( _LC6_F4_CARRY); - --- Node name is '|acceler:ACC|:771' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC6_F4_CARRY', type is buried -_LC6_F4_CARRY = CARRY( _EQ355); - _EQ355 = _LC3_F18 & _LC5_F4_CARRY - # _LC5_F4_CARRY & _LC6_F13 - # _LC3_F18 & _LC6_F13; - --- Node name is '|acceler:ACC|~779~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC8_F4', type is buried --- synthesized logic cell -_LC8_F4 = LCELL( _EQ356); - _EQ356 = !_LC1_F2 & _LC8_F13 - # _LC1_F2 & !_LC8_F13; - --- Node name is '|acceler:ACC|~782~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC1_F6', type is buried --- synthesized logic cell -_LC1_F6 = LCELL( _LC8_F4_CARRY); - --- Node name is '|acceler:ACC|~782~2' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC1_F6_CARRY', type is buried --- synthesized logic cell -_LC1_F6_CARRY = CARRY( _LC8_F4_CARRY); - --- Node name is '|acceler:ACC|:782' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC8_F4_CARRY', type is buried -_LC8_F4_CARRY = CARRY( _EQ357); - _EQ357 = _LC1_F2 & _LC7_F4_CARRY - # _LC7_F4_CARRY & _LC8_F13 - # _LC1_F2 & _LC8_F13; - --- Node name is '|acceler:ACC|~789~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC2_F6', type is buried --- synthesized logic cell -_LC2_F6 = LCELL( _EQ358); - _EQ358 = !_LC1_F18 & _LC4_F13 - # _LC1_F18 & !_LC4_F13; - --- Node name is '|acceler:ACC|~792~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC3_F6', type is buried --- synthesized logic cell -_LC3_F6 = LCELL( _LC2_F6_CARRY); - --- Node name is '|acceler:ACC|~792~2' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC3_F6_CARRY', type is buried --- synthesized logic cell -_LC3_F6_CARRY = CARRY( _LC2_F6_CARRY); - --- Node name is '|acceler:ACC|:792' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC2_F6_CARRY', type is buried -_LC2_F6_CARRY = CARRY( _EQ359); - _EQ359 = _LC1_F6_CARRY & _LC1_F18 - # _LC1_F6_CARRY & _LC4_F13 - # _LC1_F18 & _LC4_F13; - --- Node name is '|acceler:ACC|~799~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC4_F6', type is buried --- synthesized logic cell -_LC4_F6 = LCELL( _EQ360); - _EQ360 = !_LC3_F13 & _LC5_F13 - # _LC3_F13 & !_LC5_F13; - --- Node name is '|acceler:ACC|~802~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC5_F6', type is buried --- synthesized logic cell -_LC5_F6 = LCELL( _LC4_F6_CARRY); - --- Node name is '|acceler:ACC|~802~2' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC5_F6_CARRY', type is buried --- synthesized logic cell -_LC5_F6_CARRY = CARRY( _LC4_F6_CARRY); - --- Node name is '|acceler:ACC|:802' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC4_F6_CARRY', type is buried -_LC4_F6_CARRY = CARRY( _EQ361); - _EQ361 = _LC3_F6_CARRY & _LC3_F13 - # _LC3_F6_CARRY & _LC5_F13 - # _LC3_F13 & _LC5_F13; - --- Node name is '|acceler:ACC|~810~1' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC6_F6', type is buried --- synthesized logic cell -_LC6_F6 = LCELL( _EQ362); - _EQ362 = !_LC2_F13 & _LC7_F13 - # _LC2_F13 & !_LC7_F13; - --- Node name is '|acceler:ACC|:813' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC6_F6_CARRY', type is buried -_LC6_F6_CARRY = CARRY( _EQ363); - _EQ363 = _LC2_F13 & _LC5_F6_CARRY - # _LC5_F6_CARRY & _LC7_F13 - # _LC2_F13 & _LC7_F13; - --- Node name is '|acceler:ACC|:820' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC7_F6', type is buried -_LC7_F6 = LCELL( _EQ364); - _EQ364 = _LC2_F2 & !_LC2_F5 & !_LC6_F6_CARRY - # !_LC2_F2 & _LC2_F5 & !_LC6_F6_CARRY - # _LC2_F2 & _LC2_F5 & _LC6_F6_CARRY - # !_LC2_F2 & !_LC2_F5 & _LC6_F6_CARRY; - --- Node name is '|acceler:ACC|:823' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC7_F6_CARRY', type is buried -_LC7_F6_CARRY = CARRY( _EQ365); - _EQ365 = _LC2_F2 & _LC6_F6_CARRY - # _LC2_F5 & _LC6_F6_CARRY - # _LC2_F2 & _LC2_F5; - --- Node name is '|acceler:ACC|:830' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC8_F6', type is buried -_LC8_F6 = LCELL( _EQ366); - _EQ366 = !_LC3_F5 & !_LC7_F6_CARRY & _LC8_F2 - # _LC3_F5 & !_LC7_F6_CARRY & !_LC8_F2 - # _LC3_F5 & _LC7_F6_CARRY & _LC8_F2 - # !_LC3_F5 & _LC7_F6_CARRY & !_LC8_F2; - --- Node name is '|acceler:ACC|:833' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC8_F6_CARRY', type is buried -_LC8_F6_CARRY = CARRY( _EQ367); - _EQ367 = _LC7_F6_CARRY & _LC8_F2 - # _LC3_F5 & _LC7_F6_CARRY - # _LC3_F5 & _LC8_F2; - --- Node name is '|acceler:ACC|:838' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC1_F8_CARRY', type is buried --- |acceler:ACC|:838 is in Up/Down Counter Mode -_LC1_F8_CARRY = CARRY( _EQ368); - _EQ368 = _LC1_F8 & _LC8_F6_CARRY; - --- Node name is '|acceler:ACC|:842' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC2_F8_CARRY', type is buried --- |acceler:ACC|:842 is in Up/Down Counter Mode -_LC2_F8_CARRY = CARRY( _EQ369); - _EQ369 = _LC1_F8_CARRY & _LC2_F8; - --- Node name is '|acceler:ACC|:846' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC3_F8_CARRY', type is buried --- |acceler:ACC|:846 is in Up/Down Counter Mode -_LC3_F8_CARRY = CARRY( _EQ370); - _EQ370 = _LC2_F8_CARRY & _LC3_F8; - --- Node name is '|acceler:ACC|:850' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC4_F8_CARRY', type is buried --- |acceler:ACC|:850 is in Up/Down Counter Mode -_LC4_F8_CARRY = CARRY( _EQ371); - _EQ371 = _LC3_F8_CARRY & _LC4_F8; - --- Node name is '|acceler:ACC|:854' from file "acceler.tdf" line 226, column 36 --- Equation name is '_LC5_F8_CARRY', type is buried --- |acceler:ACC|:854 is in Clearable Counter Mode -_LC5_F8_CARRY = CARRY( _EQ372); - _EQ372 = _LC4_F8_CARRY & _LC5_F8; - --- Node name is '|acceler:ACC|:943' from file "acceler.tdf" line 242, column 24 --- Equation name is '_LC5_F16', type is buried -_LC5_F16 = LCELL( _EQ373); - _EQ373 = _LC2_F11 & !_LC4_F3; - --- Node name is '|acceler:ACC|~951~1' from file "acceler.tdf" line 244, column 25 --- Equation name is '_LC7_E13', type is buried --- synthesized logic cell -_LC7_E13 = LCELL( _EQ374); - _EQ374 = _LC1_E13 - # _LC4_E13 - # _LC8_E11 - # _LC7_E11; - --- Node name is '|acceler:ACC|~951~2' from file "acceler.tdf" line 244, column 25 --- Equation name is '_LC7_E15', type is buried --- synthesized logic cell -_LC7_E15 = LCELL( _EQ375); - _EQ375 = _LC5_E11 - # _LC6_E11 - # _LC2_E17 - # !_LC1_E17; - --- Node name is '|acceler:ACC|:1012' from file "acceler.tdf" line 270, column 31 --- Equation name is '_LC4_F16', type is buried -_LC4_F16 = LCELL( _EQ376); - _EQ376 = ALL_MODE0 & /reset; - --- Node name is '|acceler:ACC|:1014' from file "acceler.tdf" line 271, column 28 --- Equation name is '_LC7_F10', type is buried -_LC7_F10 = LCELL( _EQ377); - _EQ377 = !_LC8_F10 & /reset; - --- Node name is '|acceler:ACC|:1374' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC6_C36', type is buried -_LC6_C36 = LCELL( _EQ378); - _EQ378 = !_LC1_C22 & _LC2_C36 - # _LC1_C22 & !_LC2_C36; - --- Node name is '|acceler:ACC|:1376' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC1_C22_CARRY', type is buried --- |acceler:ACC|:1376 is in Up/Down Counter Mode -_LC1_C22_CARRY = CARRY( _EQ379); - _EQ379 = _LC1_C22 & _LC2_C36; - --- Node name is '|acceler:ACC|:1380' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC2_C22_CARRY', type is buried --- |acceler:ACC|:1380 is in Up/Down Counter Mode -_LC2_C22_CARRY = CARRY( _EQ380); - _EQ380 = _LC1_C22_CARRY & _LC2_C22; - --- Node name is '|acceler:ACC|:1384' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC3_C22_CARRY', type is buried --- |acceler:ACC|:1384 is in Up/Down Counter Mode -_LC3_C22_CARRY = CARRY( _EQ381); - _EQ381 = _LC2_C22_CARRY & _LC3_C22; - --- Node name is '|acceler:ACC|:1388' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC4_C22_CARRY', type is buried --- |acceler:ACC|:1388 is in Up/Down Counter Mode -_LC4_C22_CARRY = CARRY( _EQ382); - _EQ382 = _LC3_C22_CARRY & _LC4_C22; - --- Node name is '|acceler:ACC|:1392' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC5_C22_CARRY', type is buried --- |acceler:ACC|:1392 is in Up/Down Counter Mode -_LC5_C22_CARRY = CARRY( _EQ383); - _EQ383 = _LC4_C22_CARRY & _LC5_C22; - --- Node name is '|acceler:ACC|:1396' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC6_C22_CARRY', type is buried --- |acceler:ACC|:1396 is in Up/Down Counter Mode -_LC6_C22_CARRY = CARRY( _EQ384); - _EQ384 = _LC5_C22_CARRY & _LC6_C22; - --- Node name is '|acceler:ACC|:1400' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC7_C22_CARRY', type is buried --- |acceler:ACC|:1400 is in Up/Down Counter Mode -_LC7_C22_CARRY = CARRY( _EQ385); - _EQ385 = _LC6_C22_CARRY & _LC7_C22; - --- Node name is '|acceler:ACC|:1404' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC8_C22_CARRY', type is buried --- |acceler:ACC|:1404 is in Up/Down Counter Mode -_LC8_C22_CARRY = CARRY( _EQ386); - _EQ386 = _LC7_C22_CARRY & _LC8_C22; - --- Node name is '|acceler:ACC|:1408' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC1_C24_CARRY', type is buried --- |acceler:ACC|:1408 is in Up/Down Counter Mode -_LC1_C24_CARRY = CARRY( _EQ387); - _EQ387 = _LC1_C24 & _LC8_C22_CARRY; - --- Node name is '|acceler:ACC|:1412' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC2_C24_CARRY', type is buried --- |acceler:ACC|:1412 is in Up/Down Counter Mode -_LC2_C24_CARRY = CARRY( _EQ388); - _EQ388 = _LC1_C24_CARRY & _LC2_C24; - --- Node name is '|acceler:ACC|:1416' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC3_C24_CARRY', type is buried --- |acceler:ACC|:1416 is in Up/Down Counter Mode -_LC3_C24_CARRY = CARRY( _EQ389); - _EQ389 = _LC2_C24_CARRY & _LC3_C24; - --- Node name is '|acceler:ACC|:1420' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC4_C24_CARRY', type is buried --- |acceler:ACC|:1420 is in Up/Down Counter Mode -_LC4_C24_CARRY = CARRY( _EQ390); - _EQ390 = _LC3_C24_CARRY & _LC4_C24; - --- Node name is '|acceler:ACC|:1424' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC5_C24_CARRY', type is buried --- |acceler:ACC|:1424 is in Up/Down Counter Mode -_LC5_C24_CARRY = CARRY( _EQ391); - _EQ391 = _LC4_C24_CARRY & _LC5_C24; - --- Node name is '|acceler:ACC|:1428' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC6_C24_CARRY', type is buried --- |acceler:ACC|:1428 is in Up/Down Counter Mode -_LC6_C24_CARRY = CARRY( _EQ392); - _EQ392 = _LC5_C24_CARRY & _LC6_C24; - --- Node name is '|acceler:ACC|:1430' from file "acceler.tdf" line 368, column 27 --- Equation name is '_LC7_C24_CARRY', type is buried -_LC7_C24_CARRY = CARRY( _EQ393); - _EQ393 = !_LC6_C24_CARRY & _LC8_C24 - # _LC6_C24_CARRY & !_LC8_C24; - --- Node name is '|acceler:ACC|:1485' from file "acceler.tdf" line 363, column 74 --- Equation name is '_LC8_F11', type is buried -_LC8_F11 = LCELL( _EQ394); - _EQ394 = _LC4_F3 - # _LC2_F11 & _LC4_F15; - --- Node name is '|acceler:ACC|~1534~1' from file "acceler.tdf" line 284, column 34 --- Equation name is '_LC1_D18', type is buried --- synthesized logic cell -_LC1_D18 = LCELL( _EQ395C); - _EQ395C = _EQ395; - _EQ395 = D0 & D1 & d2; - --- Node name is '|acceler:ACC|~1534~2' from file "acceler.tdf" line 284, column 34 --- Equation name is '_LC2_D18', type is buried --- synthesized logic cell -_LC2_D18 = LCELL( _EQ316C); - _EQ316C = _EQ316 & CASCADE( _EQ395C); - _EQ316 = d3 & d4 & d6; - --- Node name is '|acceler:ACC|~1609~1' from file "acceler.tdf" line 220, column 64 --- Equation name is '_LC8_F24', type is buried --- synthesized logic cell -_LC8_F24 = LCELL( _EQ396); - _EQ396 = _LC3_D20 - # !_LC1_D26 - # !_LC4_D34 - # !_LC1_D34; - --- Node name is '|acceler:ACC|~1629~1' from file "acceler.tdf" line 196, column 47 --- Equation name is '_LC6_F24', type is buried --- synthesized logic cell -_LC6_F24 = LCELL( _EQ397); - _EQ397 = !_LC1_D26 & _LC1_D34 & !_LC3_D20 & _LC4_D34; - --- Node name is '|acceler:ACC|:1634' from file "acceler.tdf" line 184, column 50 --- Equation name is '_LC6_F3', type is buried -_LC6_F3 = LCELL( _EQ398); - _EQ398 = !/mr & /m1; - --- Node name is '|acceler:ACC|~1653~1' from file "acceler.tdf" line 181, column 58 --- Equation name is '_LC8_D30', type is buried --- synthesized logic cell -_LC8_D30 = LCELL( _EQ399); - _EQ399 = _LC3_D30 & _LC3_D36 & _LC4_D30 & _LC5_D1; - --- Node name is '|acceler:ACC|~1653~2' from file "acceler.tdf" line 181, column 58 --- Equation name is '_LC1_D30', type is buried --- synthesized logic cell -_LC1_D30 = LCELL( _EQ213C); - _EQ213C = _EQ213; - _EQ213 = _LC6_D30 & _LC7_D30 & !_LC7_D34 & !_LC8_D34; - --- Node name is '|ay:AY3|AY_AAX0' from file "ay.tdf" line 43, column 8 --- Equation name is '_LC8_E10', type is buried -_LC8_E10 = DFFE( _EQ400, _LC5_F3, VCC, VCC, VCC); - _EQ400 = D0 & !D1 & d2 & d3; - --- Node name is '|ay:AY3|AY_AA0' from file "ay.tdf" line 53, column 7 --- Equation name is '_LC5_B11', type is buried -_LC5_B11 = DFFE( _EQ401, GLOBAL( TG42), VCC, VCC, VCC); - _EQ401 = !_LC1_B2 & _LC1_B6 & !_LC2_B6 & _LC8_E6 - # _LC1_B2 & !_LC1_B6 & !_LC2_B6 & _LC8_E6 - # _LC1_B2 & _LC1_B6 & !_LC2_B6 & !_LC8_E6 - # !_LC1_B2 & !_LC1_B6 & !_LC2_B6 & !_LC8_E6; - --- Node name is '|ay:AY3|AY_AA1' from file "ay.tdf" line 53, column 7 --- Equation name is '_LC3_B6', type is buried -_LC3_B6 = DFFE( _EQ402, GLOBAL( TG42), VCC, VCC, VCC); - _EQ402 = _LC1_B6 & !_LC2_B6 & _LC3_B2 & !_LC8_E6 - # !_LC1_B6 & !_LC2_B6 & !_LC3_B2 & !_LC8_E6 - # _LC1_B6 & !_LC2_B6 & !_LC3_B2 & _LC8_E6 - # !_LC1_B6 & !_LC2_B6 & _LC3_B2 & _LC8_E6; - --- Node name is '|ay:AY3|AY_AA2' from file "ay.tdf" line 53, column 7 --- Equation name is '_LC6_B6', type is buried -_LC6_B6 = DFFE( _EQ403, GLOBAL( TG42), VCC, VCC, VCC); - _EQ403 = _LC1_B6 & !_LC2_B6 & !_LC4_B2 & _LC8_E6 - # !_LC1_B6 & !_LC2_B6 & _LC4_B2 & _LC8_E6 - # _LC1_B6 & !_LC2_B6 & _LC4_B2 & !_LC8_E6 - # !_LC1_B6 & !_LC2_B6 & !_LC4_B2 & !_LC8_E6; - --- Node name is '|ay:AY3|AY_AA3' from file "ay.tdf" line 53, column 7 --- Equation name is '_LC3_B1', type is buried -_LC3_B1 = DFFE( _EQ404, GLOBAL( TG42), VCC, VCC, VCC); - _EQ404 = _LC1_B6 & !_LC2_B6 & !_LC5_B2 & _LC8_E6 - # !_LC1_B6 & !_LC2_B6 & _LC5_B2 & _LC8_E6 - # _LC1_B6 & !_LC2_B6 & _LC5_B2 & !_LC8_E6 - # !_LC1_B6 & !_LC2_B6 & !_LC5_B2 & !_LC8_E6; - --- Node name is '|ay:AY3|AY_ABLK' from file "ay.tdf" line 291, column 13 --- Equation name is '_LC2_B6', type is buried -_LC2_B6 = DFFE( _EQ405, GLOBAL( TG42), VCC, VCC, VCC); - _EQ405 = !_LC2_E4 & _LC7_B2; - --- Node name is '|ay:AY3|AY_ADR0' from file "ay.tdf" line 42, column 8 --- Equation name is '_LC6_E10', type is buried -_LC6_E10 = DFFE( D0, _LC5_F3, VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_ADR1' from file "ay.tdf" line 42, column 8 --- Equation name is '_LC6_E2', type is buried -_LC6_E2 = DFFE( D1, _LC5_F3, VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_ADR2' from file "ay.tdf" line 42, column 8 --- Equation name is '_LC3_E10', type is buried -_LC3_E10 = DFFE( d2, _LC5_F3, VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_ADR3' from file "ay.tdf" line 42, column 8 --- Equation name is '_LC4_E2', type is buried -_LC4_E2 = DFFE( d3, _LC5_F3, VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_AMP0' from file "ay.tdf" line 83, column 8 --- Equation name is '_LC5_E12', type is buried -_LC5_E12 = DFFE( _EQ406, GLOBAL( TG42), VCC, VCC, VCC); - _EQ406 = _LC2_E19 & !_LC2_E26 - # _LC2_E26 & _LC5_B11 - # _LC2_E19 & _LC5_B11; - --- Node name is '|ay:AY3|AY_AMP1' from file "ay.tdf" line 83, column 8 --- Equation name is '_LC8_E4', type is buried -_LC8_E4 = DFFE( _EQ407, GLOBAL( TG42), VCC, VCC, VCC); - _EQ407 = !_LC2_E26 & _LC4_E19 - # _LC2_E26 & _LC3_B6 - # _LC3_B6 & _LC4_E19; - --- Node name is '|ay:AY3|AY_AMP2' from file "ay.tdf" line 83, column 8 --- Equation name is '_LC6_E12', type is buried -_LC6_E12 = DFFE( _EQ408, GLOBAL( TG42), VCC, VCC, VCC); - _EQ408 = !_LC2_E26 & _LC6_E21 - # _LC2_E26 & _LC6_B6 - # _LC6_B6 & _LC6_E21; - --- Node name is '|ay:AY3|AY_AMP3' from file "ay.tdf" line 83, column 8 --- Equation name is '_LC7_E12', type is buried -_LC7_E12 = DFFE( _EQ409, GLOBAL( TG42), VCC, VCC, VCC); - _EQ409 = !_LC2_E26 & _LC7_E26 - # _LC2_E26 & _LC3_B1 - # _LC3_B1 & _LC7_E26; - --- Node name is '|ay:AY3|AY_AX0~1' from file "ay.tdf" line 182, column 13 --- Equation name is '_LC6_E9', type is buried --- synthesized logic cell -_LC6_E9 = LCELL( _EQ410); - _EQ410 = _LC2_E14 & !_LC4_E1 & !_LC7_E28 - # _LC4_E1 & _LC6_E10 & !_LC7_E28; - --- Node name is '|ay:AY3|AY_AX0' from file "ay.tdf" line 182, column 13 --- Equation name is '_LC3_E9', type is buried -_LC3_E9 = LCELL( _EQ411); - _EQ411 = _EC5_E & _LC7_E28 - # _LC6_E9; - --- Node name is '|ay:AY3|AY_AX1~1' from file "ay.tdf" line 182, column 13 --- Equation name is '_LC5_E2', type is buried --- synthesized logic cell -_LC5_E2 = LCELL( _EQ412); - _EQ412 = !_LC4_E1 & _LC5_E28 & !_LC7_E28 - # _LC4_E1 & _LC6_E2 & !_LC7_E28; - --- Node name is '|ay:AY3|AY_AX1' from file "ay.tdf" line 182, column 13 --- Equation name is '_LC1_E6', type is buried -_LC1_E6 = LCELL( _EQ413); - _EQ413 = _EC11_E & _LC7_E28 - # _LC5_E2; - --- Node name is '|ay:AY3|AY_AX2~1' from file "ay.tdf" line 182, column 13 --- Equation name is '_LC7_E9', type is buried --- synthesized logic cell -_LC7_E9 = LCELL( _EQ414); - _EQ414 = !_LC4_E1 & _LC5_E19 & !_LC7_E28 - # _LC3_E10 & _LC4_E1 & !_LC7_E28; - --- Node name is '|ay:AY3|AY_AX2' from file "ay.tdf" line 182, column 13 --- Equation name is '_LC2_E9', type is buried -_LC2_E9 = LCELL( _EQ415); - _EQ415 = _EC3_E & _LC7_E28 - # _LC7_E9; - --- Node name is '|ay:AY3|AY_AX3~1' from file "ay.tdf" line 182, column 13 --- Equation name is '_LC8_E2', type is buried --- synthesized logic cell -_LC8_E2 = LCELL( _EQ416); - _EQ416 = _LC2_E29 & !_LC4_E1 & !_LC7_E28 - # _LC4_E1 & _LC4_E2 & !_LC7_E28; - --- Node name is '|ay:AY3|AY_AX3' from file "ay.tdf" line 182, column 13 --- Equation name is '_LC1_E2', type is buried -_LC1_E2 = LCELL( _EQ417); - _EQ417 = _EC12_E & _LC7_E28 - # _LC8_E2; - --- Node name is '|ay:AY3|AY_AX4' from file "ay.tdf" line 182, column 13 --- Equation name is '_LC2_E3', type is buried -_LC2_E3 = LCELL( _EQ418); - _EQ418 = _EC4_E & _LC7_E28 - # _LC1_A10 & !_LC4_E1 & !_LC7_E28; - --- Node name is '|ay:AY3|AY_AX5' from file "ay.tdf" line 168, column 13 --- Equation name is '_LC3_E3', type is buried -_LC3_E3 = LCELL( _EQ419); - _EQ419 = !_LC4_E1 & !_LC7_E28 & _LC8_E3; - --- Node name is '|ay:AY3|AY_BBLK' from file "ay.tdf" line 288, column 13 --- Equation name is '_LC6_B2', type is buried --- |ay:AY3|AY_BBLK is in Clearable Counter Mode --- synchronous load = _LC2_E4 --- synchronous clear = _LC7_B2 -_LC6_B2 = DFFE(( _LC7_E6 & _LC2_E4 # !_LC2_E4) & _LC7_B2, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_BINV' from file "ay.tdf" line 294, column 13 --- Equation name is '_LC1_B6', type is buried -_LC1_B6 = DFFE( _EQ420, GLOBAL( TG42), VCC, VCC, VCC); - _EQ420 = _LC2_E4 & _LC7_B2 & _LC7_E4 & !_LC7_E6 - # _LC2_E4 & _LC7_B2 & !_LC7_E4 & _LC7_E6; - --- Node name is '|ay:AY3|AY_C' from file "ay.tdf" line 64, column 2 --- Equation name is '_LC6_E26', type is buried -_LC6_E26 = DFFE(!_LC5_E26_CARRY, GLOBAL( TG42), VCC, VCC, !_LC1_E28); - --- Node name is '|ay:AY3|AY_CCC0' from file "ay.tdf" line 62, column 8 --- Equation name is '_LC4_E1', type is buried -_LC4_E1 = DFFE( _LC7_F1, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_CCC1' from file "ay.tdf" line 62, column 8 --- Equation name is '_LC7_E28', type is buried -_LC7_E28 = DFFE( _LC3_F35, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_CCC2' from file "ay.tdf" line 62, column 8 --- Equation name is '_LC2_E14', type is buried -_LC2_E14 = DFFE( _LC3_E28, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_CCC3' from file "ay.tdf" line 62, column 8 --- Equation name is '_LC5_E28', type is buried -_LC5_E28 = DFFE( _LC5_A29, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_CCC4' from file "ay.tdf" line 62, column 8 --- Equation name is '_LC5_E19', type is buried -_LC5_E19 = DFFE( _LC7_A29, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_CCC5' from file "ay.tdf" line 62, column 8 --- Equation name is '_LC2_E29', type is buried -_LC2_E29 = DFFE( _LC6_A29, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_CCC6' from file "ay.tdf" line 62, column 8 --- Equation name is '_LC1_A10', type is buried -_LC1_A10 = DFFE( _LC1_A30, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_CCC7' from file "ay.tdf" line 62, column 8 --- Equation name is '_LC8_E3', type is buried -_LC8_E3 = DFFE( _LC8_A30, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_CH_CS0' from file "ay.tdf" line 91, column 10 --- Equation name is '_LC1_E7', type is buried -_LC1_E7 = DFFE( _EQ421, GLOBAL( TG42), VCC, VCC, VCC); - _EQ421 = _LC1_E12 & _LC2_E12 & !_LC8_E12 - # _LC1_E12 & !_LC2_E6 & !_LC2_E12 & _LC8_E12 - # !_LC1_E12 & !_LC2_E6 & _LC2_E12 & _LC8_E12; - --- Node name is '|ay:AY3|AY_CH_CS1' from file "ay.tdf" line 91, column 10 --- Equation name is '_LC2_E7', type is buried -_LC2_E7 = DFFE( _EQ422, GLOBAL( TG42), VCC, VCC, VCC); - _EQ422 = !_LC1_E12 & _LC2_E6 & _LC8_E12 - # _LC1_E12 & _LC2_E12 & !_LC8_E12 - # !_LC2_E12 & _LC8_E12; - --- Node name is '|ay:AY3|AY_CH_CS2' from file "ay.tdf" line 91, column 10 --- Equation name is '_LC4_E7', type is buried -_LC4_E7 = DFFE( _EQ423, GLOBAL( TG42), VCC, VCC, VCC); - _EQ423 = _LC2_E6 & !_LC2_E12 & _LC8_E12 - # _LC1_E12 & _LC2_E12 & !_LC8_E12 - # _LC1_E12 & !_LC2_E6 & _LC2_E12 - # !_LC2_E6 & _LC2_E12 & _LC8_E12 - # !_LC1_E12 & _LC2_E6 & !_LC2_E12; - --- Node name is '|ay:AY3|AY_CH_CS3' from file "ay.tdf" line 91, column 10 --- Equation name is '_LC7_E7', type is buried -_LC7_E7 = DFFE( _EQ424, GLOBAL( TG42), VCC, VCC, VCC); - _EQ424 = _LC2_E6 & _LC2_E12 & _LC8_E12 - # _LC1_E12 & _LC2_E6 & _LC2_E12 - # _LC1_E12 & _LC2_E12 & !_LC8_E12 - # !_LC1_E12 & _LC2_E12 & _LC8_E12 - # _LC1_E12 & !_LC2_E6 & !_LC2_E12 - # _LC1_E12 & !_LC2_E6 & !_LC8_E12; - --- Node name is '|ay:AY3|AY_CH_CS4' from file "ay.tdf" line 91, column 10 --- Equation name is '_LC8_E7', type is buried -_LC8_E7 = DFFE( _EQ425, GLOBAL( TG42), VCC, VCC, VCC); - _EQ425 = !_LC1_E12 & _LC2_E6 & _LC2_E12 & _LC8_E12 - # _LC1_E12 & _LC2_E12 & !_LC8_E12 - # _LC1_E12 & !_LC2_E6 & _LC2_E12 - # _LC1_E12 & _LC2_E6 & !_LC2_E12; - --- Node name is '|ay:AY3|AY_CH_CS5' from file "ay.tdf" line 91, column 10 --- Equation name is '_LC3_E12', type is buried -_LC3_E12 = DFFE( _EQ426, GLOBAL( TG42), VCC, VCC, VCC); - _EQ426 = _LC1_E12 & _LC2_E12 - # !_LC2_E6 & _LC2_E12; - --- Node name is '|ay:AY3|AY_CH_CS6' from file "ay.tdf" line 91, column 10 --- Equation name is '_LC3_E7', type is buried -_LC3_E7 = DFFE( _EQ427, GLOBAL( TG42), VCC, VCC, VCC); - _EQ427 = _LC1_E12 & _LC2_E12 & !_LC8_E12 - # _LC2_E6 & _LC2_E12; - --- Node name is '|ay:AY3|AY_CH_CS7' from file "ay.tdf" line 91, column 10 --- Equation name is '_LC5_E7', type is buried -_LC5_E7 = DFFE( _EQ428, GLOBAL( TG42), VCC, VCC, VCC); - _EQ428 = _LC1_E12 & _LC2_E6 & _LC2_E12 & !_LC8_E12 - # _LC1_E12 & !_LC2_E6 & _LC2_E12 & _LC8_E12; - --- Node name is '|ay:AY3|AY_CH_CS8' from file "ay.tdf" line 91, column 10 --- Equation name is '_LC6_E7', type is buried -_LC6_E7 = DFFE( _EQ429, GLOBAL( TG42), VCC, VCC, VCC); - _EQ429 = _LC1_E12 & _LC2_E6 & _LC2_E12 & _LC8_E12; - --- Node name is '|ay:AY3|AY_CH_LX0' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC8_A12', type is buried -_LC8_A12 = DFFE( _EQ430, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - _EQ430 = _LC1_E7 & !_LC8_A12 - # !_LC1_E7 & _LC8_A12; - --- Node name is '|ay:AY3|AY_CH_LX1' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC6_A18', type is buried -_LC6_A18 = DFFE( _LC4_A2, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - --- Node name is '|ay:AY3|AY_CH_LX2' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC5_A18', type is buried -_LC5_A18 = DFFE( _LC5_A2, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - --- Node name is '|ay:AY3|AY_CH_LX3' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC7_A18', type is buried -_LC7_A18 = DFFE( _LC6_A2, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - --- Node name is '|ay:AY3|AY_CH_LX4' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC1_A2', type is buried -_LC1_A2 = DFFE( _LC7_A2, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - --- Node name is '|ay:AY3|AY_CH_LX5' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC2_A2', type is buried -_LC2_A2 = DFFE( _LC8_A2, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - --- Node name is '|ay:AY3|AY_CH_LX6' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC7_A4', type is buried -_LC7_A4 = DFFE( _LC1_A4, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - --- Node name is '|ay:AY3|AY_CH_LX7' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC8_A4', type is buried -_LC8_A4 = DFFE( _LC2_A4, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - --- Node name is '|ay:AY3|AY_CH_LX8' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC6_A4', type is buried -_LC6_A4 = DFFE( _LC3_A4, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - --- Node name is '|ay:AY3|AY_CH_LX9' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC4_A4', type is buried --- |ay:AY3|AY_CH_LX9 is in Up/Down Counter Mode -_LC4_A4 = DFFE( _EQ431, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - _EQ431 = !_LC3_A4_CARRY & _LC4_A4 - # _LC3_A4_CARRY & !_LC4_A4; - --- Node name is '|ay:AY3|AY_CH_LX10' from file "ay.tdf" line 92, column 10 --- Equation name is '_LC5_A4', type is buried -_LC5_A4 = DFFE( _EQ432, GLOBAL( TG42), !_LC7_E3, VCC, _LC2_A18); - _EQ432 = !_LC4_A4_CARRY & _LC5_A4 - # _LC4_A4_CARRY & !_LC5_A4; - --- Node name is '|ay:AY3|AY_CH_MIX' from file "ay.tdf" line 81, column 2 --- Equation name is '_LC6_E27', type is buried -_LC6_E27 = DFFE( _EQ433, GLOBAL( TG42), VCC, VCC, VCC); - _EQ433 = _EC11_E & _LC1_E27 - # !_EC11_E & _LC3_E27; - --- Node name is '|ay:AY3|AY_CH_RX0' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC1_A12', type is buried -_LC1_A12 = DFFE( _EQ434, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - _EQ434 = !_LC1_A12 & _LC1_E7 - # _LC1_A12 & !_LC1_E7; - --- Node name is '|ay:AY3|AY_CH_RX1' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC1_A6', type is buried -_LC1_A6 = DFFE( _LC4_A6, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - --- Node name is '|ay:AY3|AY_CH_RX2' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC2_A6', type is buried -_LC2_A6 = DFFE( _LC5_A6, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - --- Node name is '|ay:AY3|AY_CH_RX3' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC5_A12', type is buried -_LC5_A12 = DFFE( _LC6_A6, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - --- Node name is '|ay:AY3|AY_CH_RX4' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC6_A12', type is buried -_LC6_A12 = DFFE( _LC7_A6, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - --- Node name is '|ay:AY3|AY_CH_RX5' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC3_A12', type is buried -_LC3_A12 = DFFE( _LC8_A6, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - --- Node name is '|ay:AY3|AY_CH_RX6' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC8_A8', type is buried -_LC8_A8 = DFFE( _LC1_A8, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - --- Node name is '|ay:AY3|AY_CH_RX7' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC6_A8', type is buried -_LC6_A8 = DFFE( _LC2_A8, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - --- Node name is '|ay:AY3|AY_CH_RX8' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC7_A8', type is buried -_LC7_A8 = DFFE( _LC3_A8, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - --- Node name is '|ay:AY3|AY_CH_RX9' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC4_A8', type is buried --- |ay:AY3|AY_CH_RX9 is in Up/Down Counter Mode -_LC4_A8 = DFFE( _EQ435, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - _EQ435 = !_LC3_A8_CARRY & _LC4_A8 - # _LC3_A8_CARRY & !_LC4_A8; - --- Node name is '|ay:AY3|AY_CH_RX10' from file "ay.tdf" line 93, column 10 --- Equation name is '_LC5_A8', type is buried -_LC5_A8 = DFFE( _EQ436, GLOBAL( TG42), !_LC7_E3, VCC, _LC5_A3); - _EQ436 = !_LC4_A8_CARRY & _LC5_A8 - # _LC4_A8_CARRY & !_LC5_A8; - --- Node name is '|ay:AY3|AY_CX' from file "ay.tdf" line 65, column 2 --- Equation name is '_LC2_E16', type is buried -!_LC2_E16 = _LC2_E16~NOT; -_LC2_E16~NOT = DFFE( _EQ437, GLOBAL( TG42), !_LC5_E16, VCC, _LC3_E16); - _EQ437 = !_LC6_E16 & !_LC7_E16 - # _LC1_E16 & !_LC7_E16 - # _LC1_E16 & _LC6_E16; - --- Node name is '|ay:AY3|AY_CXX' from file "ay.tdf" line 66, column 2 --- Equation name is '_LC4_E16', type is buried -!_LC4_E16 = _LC4_E16~NOT; -_LC4_E16~NOT = DFFE( _EQ438, GLOBAL( TG42), !_LC5_E16, VCC, _LC3_E16); - _EQ438 = !_LC5_E9 & !_LC7_E16 - # !_LC5_E9 & _LC6_E16 - # !_LC6_E16 & !_LC7_E16; - --- Node name is '|ay:AY3|AY_DAT_WR' from file "ay.tdf" line 72, column 2 --- Equation name is '_LC8_E28', type is buried -_LC8_E28 = DFFE( _EQ439, GLOBAL( TG42), VCC, VCC, VCC); - _EQ439 = _EC2_E - # !_LC7_E28; - --- Node name is '|ay:AY3|AY_DAT0' from file "ay.tdf" line 73, column 8 --- Equation name is '_LC2_E19', type is buried -_LC2_E19 = DFFE( _EQ440, GLOBAL( TG42), VCC, VCC, !_LC1_E28); - _EQ440 = _EC5_E & !_LC1_E31 - # !_EC5_E & _LC1_E31; - --- Node name is '|ay:AY3|AY_DAT1' from file "ay.tdf" line 73, column 8 --- Equation name is '_LC4_E19', type is buried -_LC4_E19 = DFFE( _EQ441, GLOBAL( TG42), VCC, VCC, !_LC1_E28); - _EQ441 = !_EC5_E & !_EC11_E & _LC1_E31 - # _EC5_E & _EC11_E - # _EC11_E & !_LC1_E31; - --- Node name is '|ay:AY3|AY_DAT2' from file "ay.tdf" line 73, column 8 --- Equation name is '_LC6_E21', type is buried -_LC6_E21 = DFFE( _EQ442, GLOBAL( TG42), VCC, VCC, !_LC1_E28); - _EQ442 = !_EC3_E & !_EC11_E & !_LC1_E19 - # _EC3_E & _EC11_E - # _EC3_E & _LC1_E19; - --- Node name is '|ay:AY3|AY_DAT3' from file "ay.tdf" line 73, column 8 --- Equation name is '_LC7_E26', type is buried -_LC7_E26 = DFFE( _EQ443, GLOBAL( TG42), VCC, VCC, !_LC1_E28); - _EQ443 = !_EC12_E & !_LC8_E26 - # _EC12_E & _LC8_E26; - --- Node name is '|ay:AY3|AY_DAT4' from file "ay.tdf" line 73, column 8 --- Equation name is '_LC2_E26', type is buried -_LC2_E26 = DFFE( _EQ444, GLOBAL( TG42), VCC, VCC, !_LC1_E28); - _EQ444 = !_EC4_E & !_LC1_E26_CARRY - # _EC4_E & _LC1_E26_CARRY; - --- Node name is '|ay:AY3|AY_DAT5' from file "ay.tdf" line 73, column 8 --- Equation name is '_LC3_E26', type is buried -_LC3_E26 = DFFE( _EQ445, GLOBAL( TG42), VCC, VCC, !_LC1_E28); - _EQ445 = !_EC13_E & !_LC2_E26_CARRY - # _EC13_E & _LC2_E26_CARRY; - --- Node name is '|ay:AY3|AY_DAT6' from file "ay.tdf" line 73, column 8 --- Equation name is '_LC4_E26', type is buried -_LC4_E26 = DFFE( _EQ446, GLOBAL( TG42), VCC, VCC, !_LC1_E28); - _EQ446 = !_EC2_E & !_LC3_E26_CARRY - # _EC2_E & _LC3_E26_CARRY; - --- Node name is '|ay:AY3|AY_DAT7' from file "ay.tdf" line 73, column 8 --- Equation name is '_LC5_E26', type is buried -_LC5_E26 = DFFE( _EQ447, GLOBAL( TG42), VCC, VCC, !_LC1_E28); - _EQ447 = !_EC9_E & !_LC4_E26_CARRY - # _EC9_E & _LC4_E26_CARRY; - --- Node name is '|ay:AY3|AY_DD0' from file "ay.tdf" line 85, column 7 --- Equation name is '_LC7_E19', type is buried -_LC7_E19 = DFFE( _EC5_E, GLOBAL( TG42), VCC, VCC, !_LC3_E1); - --- Node name is '|ay:AY3|AY_DD1' from file "ay.tdf" line 85, column 7 --- Equation name is '_LC3_E19', type is buried -_LC3_E19 = DFFE( _EC11_E, GLOBAL( TG42), VCC, VCC, !_LC3_E1); - --- Node name is '|ay:AY3|AY_DD2' from file "ay.tdf" line 85, column 7 --- Equation name is '_LC8_E19', type is buried -_LC8_E19 = DFFE( _EC3_E, GLOBAL( TG42), VCC, VCC, !_LC3_E1); - --- Node name is '|ay:AY3|AY_DD3' from file "ay.tdf" line 85, column 7 --- Equation name is '_LC3_E31', type is buried -_LC3_E31 = DFFE( _EC12_E, GLOBAL( TG42), VCC, VCC, !_LC3_E1); - --- Node name is '|ay:AY3|AY_DD4' from file "ay.tdf" line 85, column 7 --- Equation name is '_LC4_E31', type is buried -_LC4_E31 = DFFE( _EC4_E, GLOBAL( TG42), VCC, VCC, !_LC3_E1); - --- Node name is '|ay:AY3|AY_DD5' from file "ay.tdf" line 85, column 7 --- Equation name is '_LC2_E31', type is buried -_LC2_E31 = DFFE( _EC13_E, GLOBAL( TG42), VCC, VCC, !_LC3_E1); - --- Node name is '|ay:AY3|AY_DD6' from file "ay.tdf" line 85, column 7 --- Equation name is '_LC8_E31', type is buried -_LC8_E31 = DFFE( _EC2_E, GLOBAL( TG42), VCC, VCC, !_LC3_E1); - --- Node name is '|ay:AY3|AY_DD7' from file "ay.tdf" line 85, column 7 --- Equation name is '_LC7_E31', type is buried -_LC7_E31 = DFFE( _EC9_E, GLOBAL( TG42), VCC, VCC, !_LC3_E1); - --- Node name is '|ay:AY3|AY_DI0' from file "ay.tdf" line 187, column 13 --- Equation name is '_LC3_E17', type is buried -_LC3_E17 = LCELL( _EQ448); - _EQ448 = _LC4_E1 & !_LC7_E28 & _LC8_E17 - # _LC2_E19 & !_LC4_E1 - # _LC2_E19 & _LC7_E28; - --- Node name is '|ay:AY3|AY_DI1' from file "ay.tdf" line 187, column 13 --- Equation name is '_LC4_E10', type is buried -_LC4_E10 = LCELL( _EQ449); - _EQ449 = _LC4_E1 & _LC7_E10 & !_LC7_E28 - # !_LC4_E1 & _LC4_E19 - # _LC4_E19 & _LC7_E28; - --- Node name is '|ay:AY3|AY_DI2' from file "ay.tdf" line 187, column 13 --- Equation name is '_LC6_E1', type is buried -_LC6_E1 = LCELL( _EQ450); - _EQ450 = _LC4_E1 & _LC7_E1 & !_LC7_E28 - # !_LC4_E1 & _LC6_E21 - # _LC6_E21 & _LC7_E28; - --- Node name is '|ay:AY3|AY_DI3' from file "ay.tdf" line 187, column 13 --- Equation name is '_LC4_E17', type is buried -_LC4_E17 = LCELL( _EQ451); - _EQ451 = _LC4_E1 & _LC7_E17 & !_LC7_E28 - # !_LC4_E1 & _LC7_E26 - # _LC7_E26 & _LC7_E28; - --- Node name is '|ay:AY3|AY_DI4' from file "ay.tdf" line 187, column 13 --- Equation name is '_LC8_E1', type is buried -_LC8_E1 = LCELL( _EQ452); - _EQ452 = _LC3_E2 & _LC4_E1 & !_LC7_E28 - # _LC2_E26 & !_LC4_E1 - # _LC2_E26 & _LC7_E28; - --- Node name is '|ay:AY3|AY_DI5' from file "ay.tdf" line 187, column 13 --- Equation name is '_LC6_E8', type is buried -_LC6_E8 = LCELL( _EQ453); - _EQ453 = _LC4_E1 & _LC7_E8 & !_LC7_E28 - # _LC3_E26 & !_LC4_E1 - # _LC3_E26 & _LC7_E28; - --- Node name is '|ay:AY3|AY_DI6' from file "ay.tdf" line 187, column 13 --- Equation name is '_LC8_E8', type is buried -_LC8_E8 = LCELL( _EQ454); - _EQ454 = _LC4_E1 & _LC5_E8 & !_LC7_E28 - # !_LC4_E1 & _LC4_E26 - # _LC4_E26 & _LC7_E28; - --- Node name is '|ay:AY3|AY_DI7' from file "ay.tdf" line 187, column 13 --- Equation name is '_LC4_E8', type is buried -_LC4_E8 = LCELL( _EQ455); - _EQ455 = _LC3_E8 & _LC4_E1 & !_LC7_E28 - # !_LC4_E1 & _LC5_E26 - # _LC5_E26 & _LC7_E28; - --- Node name is '|ay:AY3|AY_DQX0' from file "ay.tdf" line 79, column 8 --- Equation name is '_LC8_E12', type is buried -_LC8_E12 = DFFE( _EQ456, GLOBAL( TG42), !_LC3_E5, !_LC4_E12, _LC5_E4); - _EQ456 = _LC5_E12 & _LC6_E27; - --- Node name is '|ay:AY3|AY_DQX1' from file "ay.tdf" line 79, column 8 --- Equation name is '_LC2_E6', type is buried -_LC2_E6 = DFFE( _EQ457, GLOBAL( TG42), !_LC3_E5, VCC, _LC5_E4); - _EQ457 = _LC6_E27 & _LC8_E4; - --- Node name is '|ay:AY3|AY_DQX2' from file "ay.tdf" line 79, column 8 --- Equation name is '_LC1_E12', type is buried -_LC1_E12 = DFFE( _EQ458, GLOBAL( TG42), !_LC3_E5, !_LC4_E12, _LC5_E4); - _EQ458 = _LC6_E12 & _LC6_E27; - --- Node name is '|ay:AY3|AY_DQX3' from file "ay.tdf" line 79, column 8 --- Equation name is '_LC2_E12', type is buried -_LC2_E12 = DFFE( _EQ459, GLOBAL( TG42), !_LC3_E5, !_LC4_E12, _LC5_E4); - _EQ459 = _LC6_E27 & _LC7_E12; - --- Node name is '|ay:AY3|AY_F_RES' from file "ay.tdf" line 155, column 13 --- Equation name is '_LC5_E3', type is buried -_LC5_E3 = DFFE( _LC6_E3, _LC8_E3, _LC5_E10, VCC, VCC); - --- Node name is '|ay:AY3|AY_F_R1' from file "ay.tdf" line 154, column 13 --- Equation name is '_LC5_E10', type is buried -_LC5_E10 = DFFE( _EQ460, GLOBAL( TG42), VCC, VCC, VCC); - _EQ460 = _LC6_E28 - # !_LC8_E10; - --- Node name is '|ay:AY3|AY_GF0' from file "ay.tdf" line 46, column 7 --- Equation name is '_LC7_E6', type is buried -_LC7_E6 = DFFE( _LC2_E19, GLOBAL( TG42), VCC, VCC, _LC4_E6); - --- Node name is '|ay:AY3|AY_GF1' from file "ay.tdf" line 46, column 7 --- Equation name is '_LC7_E4', type is buried -_LC7_E4 = DFFE( _LC4_E19, GLOBAL( TG42), VCC, VCC, _LC4_E6); - --- Node name is '|ay:AY3|AY_GF2' from file "ay.tdf" line 46, column 7 --- Equation name is '_LC8_E6', type is buried -_LC8_E6 = DFFE( _LC6_E21, GLOBAL( TG42), VCC, VCC, _LC4_E6); - --- Node name is '|ay:AY3|AY_GF3' from file "ay.tdf" line 46, column 7 --- Equation name is '_LC2_E4', type is buried -_LC2_E4 = DFFE( _LC7_E26, GLOBAL( TG42), VCC, VCC, _LC4_E6); - --- Node name is '|ay:AY3|AY_OUTSX' from file "ay.tdf" line 246, column 14 --- Equation name is '_LC5_E4', type is buried -_LC5_E4 = DFFE( _EQ461, GLOBAL( TG42), VCC, VCC, VCC); - _EQ461 = _EC2_E & !_EC9_E & _EC13_E & _LC1_E5; - --- Node name is '|ay:AY3|AY_OUTS1' from file "ay.tdf" line 226, column 15 --- Equation name is '_LC1_E35', type is buried -_LC1_E35 = DFFE( _EQ462, GLOBAL( TG42), VCC, VCC, VCC); - _EQ462 = _EC2_E & !_EC9_E & _EC13_E & _LC6_E35; - --- Node name is '|ay:AY3|AY_OUTS1X' from file "ay.tdf" line 340, column 14 --- Equation name is '_LC6_E25', type is buried -_LC6_E25 = DFFE( _LC1_E35, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_OUTS1Y' from file "ay.tdf" line 344, column 14 --- Equation name is '_LC2_E21', type is buried -_LC2_E21 = DFFE( _EQ463, GLOBAL( TG42), VCC, VCC, VCC); - _EQ463 = _LC6_E25 - # _LC1_E35; - --- Node name is '|ay:AY3|AY_OUTS2' from file "ay.tdf" line 233, column 15 --- Equation name is '_LC5_E35', type is buried -_LC5_E35 = DFFE( _EQ464, GLOBAL( TG42), VCC, VCC, VCC); - _EQ464 = _EC2_E & !_EC9_E & _EC13_E & _LC7_E35; - --- Node name is '|ay:AY3|AY_OUTS2X' from file "ay.tdf" line 341, column 14 --- Equation name is '_LC6_E36', type is buried -_LC6_E36 = DFFE( _EQ465, GLOBAL( TG42), VCC, VCC, VCC); - _EQ465 = _LC5_E35 - # _LC3_E5; - --- Node name is '|ay:AY3|AY_OUTS3' from file "ay.tdf" line 240, column 15 --- Equation name is '_LC2_E35', type is buried -_LC2_E35 = DFFE( _EQ466, GLOBAL( TG42), VCC, VCC, VCC); - _EQ466 = _EC2_E & !_EC9_E & _EC13_E & _LC8_E35; - --- Node name is '|ay:AY3|AY_OUTS3X' from file "ay.tdf" line 342, column 14 --- Equation name is '_LC5_E36', type is buried -_LC5_E36 = DFFE( _LC2_E35, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|AY_OUTS3Y' from file "ay.tdf" line 346, column 14 --- Equation name is '_LC1_E36', type is buried -_LC1_E36 = DFFE( _EQ467, GLOBAL( TG42), VCC, VCC, VCC); - _EQ467 = _LC5_E36 - # _LC2_E35; - --- Node name is '|ay:AY3|AY_OUT1' from file "ay.tdf" line 48, column 8 --- Equation name is '_LC3_E29', type is buried -_LC3_E29 = DFFE( _EQ468, GLOBAL( TG42), VCC, VCC, _LC1_E35); - _EQ468 = !_LC2_E16 & _LC3_E29 - # _LC2_E16 & !_LC3_E29; - --- Node name is '|ay:AY3|AY_OUT2' from file "ay.tdf" line 48, column 8 --- Equation name is '_LC4_E36', type is buried -_LC4_E36 = DFFE( _EQ469, GLOBAL( TG42), VCC, VCC, _LC5_E35); - _EQ469 = !_LC2_E16 & _LC4_E36 - # _LC2_E16 & !_LC4_E36; - --- Node name is '|ay:AY3|AY_OUT3' from file "ay.tdf" line 48, column 8 --- Equation name is '_LC1_E29', type is buried -_LC1_E29 = DFFE( _EQ470, GLOBAL( TG42), VCC, VCC, _LC2_E35); - _EQ470 = _LC1_E29 & !_LC2_E16 - # !_LC1_E29 & _LC2_E16; - --- Node name is '|ay:AY3|AY_SH_Q' from file "ay.tdf" line 262, column 13 --- Equation name is '_LC3_E5', type is buried -_LC3_E5 = DFFE( _EQ471, GLOBAL( TG42), VCC, VCC, VCC); - _EQ471 = _EC2_E & !_EC9_E & _EC13_E & _LC4_E5; - --- Node name is '|ay:AY3|AY_SH0' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC2_D20', type is buried -!_LC2_D20 = _LC2_D20~NOT; -_LC2_D20~NOT = DFFE(!_LC7_D20, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH1' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC7_D20', type is buried -!_LC7_D20 = _LC7_D20~NOT; -_LC7_D20~NOT = DFFE(!_LC6_D20, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH2' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC6_D20', type is buried -!_LC6_D20 = _LC6_D20~NOT; -_LC6_D20~NOT = DFFE(!_LC4_D20, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH3' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC4_D20', type is buried -!_LC4_D20 = _LC4_D20~NOT; -_LC4_D20~NOT = DFFE(!_LC2_D25, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH4' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC2_D25', type is buried -!_LC2_D25 = _LC2_D25~NOT; -_LC2_D25~NOT = DFFE(!_LC4_D25, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH5' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC4_D25', type is buried -!_LC4_D25 = _LC4_D25~NOT; -_LC4_D25~NOT = DFFE(!_LC3_D25, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH6' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC3_D25', type is buried -!_LC3_D25 = _LC3_D25~NOT; -_LC3_D25~NOT = DFFE(!_LC1_D25, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH7' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC1_D25', type is buried -!_LC1_D25 = _LC1_D25~NOT; -_LC1_D25~NOT = DFFE(!_LC6_D25, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH8' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC6_D25', type is buried -!_LC6_D25 = _LC6_D25~NOT; -_LC6_D25~NOT = DFFE(!_LC7_D25, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH9' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC7_D25', type is buried -!_LC7_D25 = _LC7_D25~NOT; -_LC7_D25~NOT = DFFE(!_LC8_D25, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH10' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC8_D25', type is buried -!_LC8_D25 = _LC8_D25~NOT; -_LC8_D25~NOT = DFFE(!_LC4_D24, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH11' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC4_D24', type is buried -!_LC4_D24 = _LC4_D24~NOT; -_LC4_D24~NOT = DFFE(!_LC8_D24, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH12' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC8_D24', type is buried -!_LC8_D24 = _LC8_D24~NOT; -_LC8_D24~NOT = DFFE(!_LC7_D24, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH13' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC7_D24', type is buried -!_LC7_D24 = _LC7_D24~NOT; -_LC7_D24~NOT = DFFE(!_LC3_D24, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH14' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC3_D24', type is buried -!_LC3_D24 = _LC3_D24~NOT; -_LC3_D24~NOT = DFFE(!_LC2_D24, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH15' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC2_D24', type is buried -!_LC2_D24 = _LC2_D24~NOT; -_LC2_D24~NOT = DFFE(!_LC8_D20, GLOBAL( TG42), /reset, VCC, _LC7_E25); - --- Node name is '|ay:AY3|AY_SH16' from file "ay.tdf" line 52, column 7 --- Equation name is '_LC8_D20', type is buried -!_LC8_D20 = _LC8_D20~NOT; -_LC8_D20~NOT = DFFE( _EQ472, GLOBAL( TG42), /reset, VCC, _LC7_E25); - _EQ472 = _LC2_D20 & _LC4_D20 - # !_LC2_D20 & !_LC4_D20; - --- Node name is '|ay:AY3|AY_VAR' from file "ay.tdf" line 69, column 2 --- Equation name is '_LC2_B2', type is buried --- |ay:AY3|AY_VAR is in Up/Down Counter Mode -_LC2_B2 = DFFE(!_LC2_B2, GLOBAL( TG42), _LC5_E3, VCC, _LC2_E28); - --- Node name is '|ay:AY3|AY_VA0' from file "ay.tdf" line 68, column 7 --- Equation name is '_LC1_B2', type is buried -_LC1_B2 = DFFE( _EQ473, GLOBAL( TG42), _LC5_E3, VCC, _LC2_E28); - _EQ473 = _LC1_B2 & !_LC2_B2 - # !_LC1_B2 & _LC2_B2; - --- Node name is '|ay:AY3|AY_VA1' from file "ay.tdf" line 68, column 7 --- Equation name is '_LC3_B2', type is buried --- |ay:AY3|AY_VA1 is in Up/Down Counter Mode -_LC3_B2 = DFFE( _EQ474, GLOBAL( TG42), _LC5_E3, VCC, _LC2_E28); - _EQ474 = !_LC2_B2_CARRY & _LC3_B2 - # _LC2_B2_CARRY & !_LC3_B2; - --- Node name is '|ay:AY3|AY_VA2' from file "ay.tdf" line 68, column 7 --- Equation name is '_LC4_B2', type is buried --- |ay:AY3|AY_VA2 is in Up/Down Counter Mode -_LC4_B2 = DFFE( _EQ475, GLOBAL( TG42), _LC5_E3, VCC, _LC2_E28); - _EQ475 = !_LC3_B2_CARRY & _LC4_B2 - # _LC3_B2_CARRY & !_LC4_B2; - --- Node name is '|ay:AY3|AY_VA3' from file "ay.tdf" line 68, column 7 --- Equation name is '_LC5_B2', type is buried --- |ay:AY3|AY_VA3 is in Up/Down Counter Mode -_LC5_B2 = DFFE( _EQ476, GLOBAL( TG42), _LC5_E3, VCC, _LC2_E28); - _EQ476 = !_LC4_B2_CARRY & _LC5_B2 - # _LC4_B2_CARRY & !_LC5_B2; - --- Node name is '|ay:AY3|AY_VX' from file "ay.tdf" line 70, column 2 --- Equation name is '_LC7_B2', type is buried -_LC7_B2 = DFFE( _LC6_B2_CARRY, GLOBAL( TG42), _LC5_E3, VCC, _LC2_E28); - --- Node name is '|ay:AY3|AY_WR' from file "ay.tdf" line 184, column 11 --- Equation name is '_LC1_E10', type is buried -_LC1_E10 = LCELL( _EQ477); - _EQ477 = !_LC2_E10 & _LC7_E28 - # _LC4_E1 & !_LC6_E28 & !_LC7_E28; - --- Node name is '|ay:AY3|AY_X_0' from file "ay.tdf" line 45, column 7 --- Equation name is '_LC8_E27', type is buried -_LC8_E27 = DFFE( _LC2_E19, GLOBAL( TG42), VCC, VCC, _LC4_E35); - --- Node name is '|ay:AY3|AY_X_1' from file "ay.tdf" line 45, column 7 --- Equation name is '_LC7_E27', type is buried -_LC7_E27 = DFFE( _LC4_E19, GLOBAL( TG42), VCC, VCC, _LC4_E35); - --- Node name is '|ay:AY3|AY_X_2' from file "ay.tdf" line 45, column 7 --- Equation name is '_LC6_E29', type is buried -_LC6_E29 = DFFE( _LC6_E21, GLOBAL( TG42), VCC, VCC, _LC4_E35); - --- Node name is '|ay:AY3|AY_X_3' from file "ay.tdf" line 45, column 7 --- Equation name is '_LC5_E27', type is buried -_LC5_E27 = DFFE( _LC7_E26, GLOBAL( TG42), VCC, VCC, _LC4_E35); - --- Node name is '|ay:AY3|AY_X_4' from file "ay.tdf" line 45, column 7 --- Equation name is '_LC4_E27', type is buried -_LC4_E27 = DFFE( _LC2_E26, GLOBAL( TG42), VCC, VCC, _LC4_E35); - --- Node name is '|ay:AY3|AY_X_5' from file "ay.tdf" line 45, column 7 --- Equation name is '_LC5_E29', type is buried -_LC5_E29 = DFFE( _LC3_E26, GLOBAL( TG42), VCC, VCC, _LC4_E35); - --- Node name is '|ay:AY3|BD0' from file "ay.tdf" line 32, column 4 --- Equation name is '_LC8_E17', type is buried -_LC8_E17 = DFFE( D0, GLOBAL( TG42), VCC, VCC, _LC7_E28); - --- Node name is '|ay:AY3|BD1' from file "ay.tdf" line 32, column 4 --- Equation name is '_LC7_E10', type is buried -_LC7_E10 = DFFE( D1, GLOBAL( TG42), VCC, VCC, _LC7_E28); - --- Node name is '|ay:AY3|BD2' from file "ay.tdf" line 32, column 4 --- Equation name is '_LC7_E1', type is buried -_LC7_E1 = DFFE( d2, GLOBAL( TG42), VCC, VCC, _LC7_E28); - --- Node name is '|ay:AY3|BD3' from file "ay.tdf" line 32, column 4 --- Equation name is '_LC7_E17', type is buried -_LC7_E17 = DFFE( d3, GLOBAL( TG42), VCC, VCC, _LC7_E28); - --- Node name is '|ay:AY3|BD4' from file "ay.tdf" line 32, column 4 --- Equation name is '_LC3_E2', type is buried -_LC3_E2 = DFFE( d4, GLOBAL( TG42), !_LC2_E2, VCC, _LC7_E28); - --- Node name is '|ay:AY3|BD5' from file "ay.tdf" line 32, column 4 --- Equation name is '_LC7_E8', type is buried -_LC7_E8 = DFFE( d5, GLOBAL( TG42), !_LC7_E2, VCC, _LC7_E28); - --- Node name is '|ay:AY3|BD6' from file "ay.tdf" line 32, column 4 --- Equation name is '_LC5_E8', type is buried -_LC5_E8 = DFFE( d6, GLOBAL( TG42), !_LC7_E2, VCC, _LC7_E28); - --- Node name is '|ay:AY3|BD7' from file "ay.tdf" line 32, column 4 --- Equation name is '_LC3_E8', type is buried -_LC3_E8 = DFFE( d7, GLOBAL( TG42), !_LC7_E2, VCC, _LC7_E28); - --- Node name is '|ay:AY3|BWR' from file "ay.tdf" line 33, column 2 --- Equation name is '_LC6_E28', type is buried -_LC6_E28 = DFFE( _LC2_F24, GLOBAL( TG42), VCC, VCC, _LC7_E28); - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_0' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC3_A2_CARRY', type is buried -_LC3_A2_CARRY = CARRY( _EQ478); - _EQ478 = _LC1_E7 & _LC8_A12; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_1' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC4_A2_CARRY', type is buried -_LC4_A2_CARRY = CARRY( _EQ479); - _EQ479 = _LC3_A2_CARRY & _LC6_A18 - # _LC2_E7 & _LC3_A2_CARRY - # _LC2_E7 & _LC6_A18; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_2' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC5_A2_CARRY', type is buried -_LC5_A2_CARRY = CARRY( _EQ480); - _EQ480 = _LC4_A2_CARRY & _LC5_A18 - # _LC4_A2_CARRY & _LC4_E7 - # _LC4_E7 & _LC5_A18; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_3' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC6_A2_CARRY', type is buried -_LC6_A2_CARRY = CARRY( _EQ481); - _EQ481 = _LC5_A2_CARRY & _LC7_A18 - # _LC5_A2_CARRY & _LC7_E7 - # _LC7_A18 & _LC7_E7; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_4' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC7_A2_CARRY', type is buried -_LC7_A2_CARRY = CARRY( _EQ482); - _EQ482 = _LC1_A2 & _LC6_A2_CARRY - # _LC6_A2_CARRY & _LC8_E7 - # _LC1_A2 & _LC8_E7; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_5' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC8_A2_CARRY', type is buried -_LC8_A2_CARRY = CARRY( _EQ483); - _EQ483 = _LC2_A2 & _LC7_A2_CARRY - # _LC3_E12 & _LC7_A2_CARRY - # _LC2_A2 & _LC3_E12; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_6' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC1_A4_CARRY', type is buried -_LC1_A4_CARRY = CARRY( _EQ484); - _EQ484 = _LC7_A4 & _LC8_A2_CARRY - # _LC3_E7 & _LC8_A2_CARRY - # _LC3_E7 & _LC7_A4; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_7' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC2_A4_CARRY', type is buried -_LC2_A4_CARRY = CARRY( _EQ485); - _EQ485 = _LC1_A4_CARRY & _LC8_A4 - # _LC1_A4_CARRY & _LC5_E7 - # _LC5_E7 & _LC8_A4; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_8' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC3_A4_CARRY', type is buried -_LC3_A4_CARRY = CARRY( _EQ486); - _EQ486 = _LC2_A4_CARRY & _LC6_A4 - # _LC2_A4_CARRY & _LC6_E7 - # _LC6_A4 & _LC6_E7; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_9' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC4_A4_CARRY', type is buried --- |ay:AY3|lpm_add_sub:121|addcore:adder|pcarry0_9 is in Up/Down Counter Mode -_LC4_A4_CARRY = CARRY( _EQ487); - _EQ487 = _LC3_A4_CARRY & _LC4_A4; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|result_node1' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC4_A2', type is buried -_LC4_A2 = LCELL( _EQ488); - _EQ488 = !_LC2_E7 & !_LC3_A2_CARRY & _LC6_A18 - # !_LC2_E7 & _LC3_A2_CARRY & !_LC6_A18 - # _LC2_E7 & _LC3_A2_CARRY & _LC6_A18 - # _LC2_E7 & !_LC3_A2_CARRY & !_LC6_A18; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|result_node2' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC5_A2', type is buried -_LC5_A2 = LCELL( _EQ489); - _EQ489 = _LC4_A2_CARRY & _LC4_E7 & _LC5_A18 - # !_LC4_A2_CARRY & _LC4_E7 & !_LC5_A18 - # !_LC4_A2_CARRY & !_LC4_E7 & _LC5_A18 - # _LC4_A2_CARRY & !_LC4_E7 & !_LC5_A18; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|result_node3' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC6_A2', type is buried -_LC6_A2 = LCELL( _EQ490); - _EQ490 = _LC5_A2_CARRY & _LC7_A18 & _LC7_E7 - # !_LC5_A2_CARRY & !_LC7_A18 & _LC7_E7 - # !_LC5_A2_CARRY & _LC7_A18 & !_LC7_E7 - # _LC5_A2_CARRY & !_LC7_A18 & !_LC7_E7; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|result_node4' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC7_A2', type is buried -_LC7_A2 = LCELL( _EQ491); - _EQ491 = _LC1_A2 & _LC6_A2_CARRY & _LC8_E7 - # !_LC1_A2 & !_LC6_A2_CARRY & _LC8_E7 - # _LC1_A2 & !_LC6_A2_CARRY & !_LC8_E7 - # !_LC1_A2 & _LC6_A2_CARRY & !_LC8_E7; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|result_node5' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC8_A2', type is buried -_LC8_A2 = LCELL( _EQ492); - _EQ492 = _LC2_A2 & _LC3_E12 & _LC7_A2_CARRY - # !_LC2_A2 & _LC3_E12 & !_LC7_A2_CARRY - # _LC2_A2 & !_LC3_E12 & !_LC7_A2_CARRY - # !_LC2_A2 & !_LC3_E12 & _LC7_A2_CARRY; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|result_node6' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC1_A4', type is buried -_LC1_A4 = LCELL( _EQ493); - _EQ493 = _LC3_E7 & _LC7_A4 & _LC8_A2_CARRY - # _LC3_E7 & !_LC7_A4 & !_LC8_A2_CARRY - # !_LC3_E7 & _LC7_A4 & !_LC8_A2_CARRY - # !_LC3_E7 & !_LC7_A4 & _LC8_A2_CARRY; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|result_node7' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC2_A4', type is buried -_LC2_A4 = LCELL( _EQ494); - _EQ494 = _LC1_A4_CARRY & _LC5_E7 & _LC8_A4 - # !_LC1_A4_CARRY & _LC5_E7 & !_LC8_A4 - # !_LC1_A4_CARRY & !_LC5_E7 & _LC8_A4 - # _LC1_A4_CARRY & !_LC5_E7 & !_LC8_A4; - --- Node name is '|ay:AY3|lpm_add_sub:121|addcore:adder|result_node8' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC3_A4', type is buried -_LC3_A4 = LCELL( _EQ495); - _EQ495 = _LC2_A4_CARRY & _LC6_A4 & _LC6_E7 - # !_LC2_A4_CARRY & !_LC6_A4 & _LC6_E7 - # !_LC2_A4_CARRY & _LC6_A4 & !_LC6_E7 - # _LC2_A4_CARRY & !_LC6_A4 & !_LC6_E7; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_0' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC3_A6_CARRY', type is buried -_LC3_A6_CARRY = CARRY( _EQ496); - _EQ496 = _LC1_A12 & _LC1_E7; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_1' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC4_A6_CARRY', type is buried -_LC4_A6_CARRY = CARRY( _EQ497); - _EQ497 = _LC1_A6 & _LC3_A6_CARRY - # _LC2_E7 & _LC3_A6_CARRY - # _LC1_A6 & _LC2_E7; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_2' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC5_A6_CARRY', type is buried -_LC5_A6_CARRY = CARRY( _EQ498); - _EQ498 = _LC2_A6 & _LC4_A6_CARRY - # _LC4_A6_CARRY & _LC4_E7 - # _LC2_A6 & _LC4_E7; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_3' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC6_A6_CARRY', type is buried -_LC6_A6_CARRY = CARRY( _EQ499); - _EQ499 = _LC5_A6_CARRY & _LC5_A12 - # _LC5_A6_CARRY & _LC7_E7 - # _LC5_A12 & _LC7_E7; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_4' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC7_A6_CARRY', type is buried -_LC7_A6_CARRY = CARRY( _EQ500); - _EQ500 = _LC6_A6_CARRY & _LC6_A12 - # _LC6_A6_CARRY & _LC8_E7 - # _LC6_A12 & _LC8_E7; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_5' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC8_A6_CARRY', type is buried -_LC8_A6_CARRY = CARRY( _EQ501); - _EQ501 = _LC3_A12 & _LC7_A6_CARRY - # _LC3_E12 & _LC7_A6_CARRY - # _LC3_A12 & _LC3_E12; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_6' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC1_A8_CARRY', type is buried -_LC1_A8_CARRY = CARRY( _EQ502); - _EQ502 = _LC8_A6_CARRY & _LC8_A8 - # _LC3_E7 & _LC8_A6_CARRY - # _LC3_E7 & _LC8_A8; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_7' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC2_A8_CARRY', type is buried -_LC2_A8_CARRY = CARRY( _EQ503); - _EQ503 = _LC1_A8_CARRY & _LC6_A8 - # _LC1_A8_CARRY & _LC5_E7 - # _LC5_E7 & _LC6_A8; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_8' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC3_A8_CARRY', type is buried -_LC3_A8_CARRY = CARRY( _EQ504); - _EQ504 = _LC2_A8_CARRY & _LC7_A8 - # _LC2_A8_CARRY & _LC6_E7 - # _LC6_E7 & _LC7_A8; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_9' from file "addcore.tdf" line 100, column 13 --- Equation name is '_LC4_A8_CARRY', type is buried --- |ay:AY3|lpm_add_sub:164|addcore:adder|pcarry0_9 is in Up/Down Counter Mode -_LC4_A8_CARRY = CARRY( _EQ505); - _EQ505 = _LC3_A8_CARRY & _LC4_A8; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|result_node1' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC4_A6', type is buried -_LC4_A6 = LCELL( _EQ506); - _EQ506 = _LC1_A6 & !_LC2_E7 & !_LC3_A6_CARRY - # !_LC1_A6 & !_LC2_E7 & _LC3_A6_CARRY - # _LC1_A6 & _LC2_E7 & _LC3_A6_CARRY - # !_LC1_A6 & _LC2_E7 & !_LC3_A6_CARRY; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|result_node2' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC5_A6', type is buried -_LC5_A6 = LCELL( _EQ507); - _EQ507 = _LC2_A6 & !_LC4_A6_CARRY & !_LC4_E7 - # !_LC2_A6 & _LC4_A6_CARRY & !_LC4_E7 - # _LC2_A6 & _LC4_A6_CARRY & _LC4_E7 - # !_LC2_A6 & !_LC4_A6_CARRY & _LC4_E7; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|result_node3' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC6_A6', type is buried -_LC6_A6 = LCELL( _EQ508); - _EQ508 = !_LC5_A6_CARRY & _LC5_A12 & !_LC7_E7 - # _LC5_A6_CARRY & !_LC5_A12 & !_LC7_E7 - # _LC5_A6_CARRY & _LC5_A12 & _LC7_E7 - # !_LC5_A6_CARRY & !_LC5_A12 & _LC7_E7; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|result_node4' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC7_A6', type is buried -_LC7_A6 = LCELL( _EQ509); - _EQ509 = !_LC6_A6_CARRY & _LC6_A12 & !_LC8_E7 - # _LC6_A6_CARRY & !_LC6_A12 & !_LC8_E7 - # _LC6_A6_CARRY & _LC6_A12 & _LC8_E7 - # !_LC6_A6_CARRY & !_LC6_A12 & _LC8_E7; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|result_node5' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC8_A6', type is buried -_LC8_A6 = LCELL( _EQ510); - _EQ510 = _LC3_A12 & !_LC3_E12 & !_LC7_A6_CARRY - # !_LC3_A12 & !_LC3_E12 & _LC7_A6_CARRY - # _LC3_A12 & _LC3_E12 & _LC7_A6_CARRY - # !_LC3_A12 & _LC3_E12 & !_LC7_A6_CARRY; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|result_node6' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC1_A8', type is buried -_LC1_A8 = LCELL( _EQ511); - _EQ511 = !_LC3_E7 & !_LC8_A6_CARRY & _LC8_A8 - # !_LC3_E7 & _LC8_A6_CARRY & !_LC8_A8 - # _LC3_E7 & _LC8_A6_CARRY & _LC8_A8 - # _LC3_E7 & !_LC8_A6_CARRY & !_LC8_A8; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|result_node7' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC2_A8', type is buried -_LC2_A8 = LCELL( _EQ512); - _EQ512 = !_LC1_A8_CARRY & !_LC5_E7 & _LC6_A8 - # _LC1_A8_CARRY & !_LC5_E7 & !_LC6_A8 - # _LC1_A8_CARRY & _LC5_E7 & _LC6_A8 - # !_LC1_A8_CARRY & _LC5_E7 & !_LC6_A8; - --- Node name is '|ay:AY3|lpm_add_sub:164|addcore:adder|result_node8' from file "addcore.tdf" line 231, column 46 --- Equation name is '_LC3_A8', type is buried -_LC3_A8 = LCELL( _EQ513); - _EQ513 = !_LC2_A8_CARRY & !_LC6_E7 & _LC7_A8 - # _LC2_A8_CARRY & !_LC6_E7 & !_LC7_A8 - # _LC2_A8_CARRY & _LC6_E7 & _LC7_A8 - # !_LC2_A8_CARRY & _LC6_E7 & !_LC7_A8; - --- Node name is '|ay:AY3|:420' from file "ay.tdf" line 155, column 17 --- Equation name is '_LC6_E3', type is buried -_LC6_E3 = DFFE( VCC, _LC8_E3, _LC5_E10, VCC, VCC); - --- Node name is '|ay:AY3|:421' from file "ay.tdf" line 184, column 14 --- Equation name is '_LC2_E10', type is buried -_LC2_E10 = LCELL( _EQ514); - _EQ514 = !_EC2_E - # _EC13_E - # _EC9_E & !_LC4_E16; - --- Node name is '|ay:AY3|:422' from file "ay.tdf" line 198, column 15 --- Equation name is '_LC5_E16', type is buried -_LC5_E16 = DFFE( _EQ515, GLOBAL( TG42), VCC, VCC, VCC); - _EQ515 = !_EC2_E & !_EC9_E & !_EC13_E & _LC7_E28; - --- Node name is '|ay:AY3|:424' from file "ay.tdf" line 204, column 27 --- Equation name is '_LC3_E16', type is buried -_LC3_E16 = DFFE( _EQ516, GLOBAL( TG42), VCC, VCC, VCC); - _EQ516 = _EC2_E & _EC9_E & _EC13_E & _LC7_E28 - # _EC2_E & !_EC9_E & !_EC13_E & _LC7_E28; - --- Node name is '|ay:AY3|:425' from file "ay.tdf" line 206, column 5 --- Equation name is '_LC6_E16', type is buried -_LC6_E16 = DFFE( _EQ517, GLOBAL( TG42), VCC, VCC, VCC); - _EQ517 = _EC2_E & !_EC9_E & !_EC13_E; - --- Node name is '|ay:AY3|:426' from file "ay.tdf" line 207, column 12 --- Equation name is '_LC8_E16', type is buried -_LC8_E16 = LCELL(!_LC2_E8); - --- Node name is '|ay:AY3|:427' from file "ay.tdf" line 210, column 13 --- Equation name is '_LC4_E9', type is buried -_LC4_E9 = LCELL(!_LC2_E8); - --- Node name is '|ay:AY3|:428' from file "ay.tdf" line 210, column 55 --- Equation name is '_LC1_E9', type is buried -_LC1_E9 = DFFE( _EC5_E, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|:430' from file "ay.tdf" line 213, column 12 --- Equation name is '_LC7_E16', type is buried -_LC7_E16 = DFFE( _EQ518, GLOBAL( TG42), VCC, VCC, VCC); - _EQ518 = _EC5_E & !/reset - # !_EC5_E & !_LC5_E3; - --- Node name is '|ay:AY3|~431~1' from file "ay.tdf" line 217, column 29 --- Equation name is '_LC1_E28', type is buried --- synthesized logic cell -!_LC1_E28 = _LC1_E28~NOT; -_LC1_E28~NOT = LCELL(!_LC4_E28); - --- Node name is '|ay:AY3|:431' from file "ay.tdf" line 217, column 29 --- Equation name is '_LC4_E28', type is buried -_LC4_E28 = DFFE( _LC8_E28, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|:432' from file "ay.tdf" line 218, column 49 --- Equation name is '_LC1_E31', type is buried -_LC1_E31 = DFFE( _EQ519, GLOBAL( TG42), VCC, VCC, VCC); - _EQ519 = _LC6_E31 - # _LC5_E31 & _LC6_E26; - --- Node name is '|ay:AY3|:433' from file "ay.tdf" line 218, column 54 --- Equation name is '_LC6_E31', type is buried -_LC6_E31 = DFFE(!_EC13_E, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|:434' from file "ay.tdf" line 218, column 86 --- Equation name is '_LC5_E31', type is buried -_LC5_E31 = DFFE( _EC9_E, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|:442' from file "ay.tdf" line 253, column 31 --- Equation name is '_LC4_E12', type is buried -_LC4_E12 = DFFE( _EQ520, GLOBAL( TG42), VCC, VCC, VCC); - _EQ520 = BORDER4 & _LC3_E5; - --- Node name is '|ay:AY3|:443' from file "ay.tdf" line 257, column 27 --- Equation name is '_LC3_E27', type is buried -_LC3_E27 = LCELL( _EQ521); - _EQ521 = _LC5_E27 & _LC8_E27 - # _LC3_E29 & _LC5_E27 - # _LC2_D20 & _LC8_E27 - # _LC2_D20 & _LC3_E29; - --- Node name is '|ay:AY3|:444' from file "ay.tdf" line 258, column 25 --- Equation name is '_LC2_E27', type is buried -_LC2_E27 = LCELL( _EQ522); - _EQ522 = _LC4_E27 & _LC7_E27 - # _LC4_E27 & _LC4_E36 - # _LC2_D20 & _LC7_E27 - # _LC2_D20 & _LC4_E36; - --- Node name is '|ay:AY3|:445' from file "ay.tdf" line 259, column 25 --- Equation name is '_LC7_E29', type is buried -_LC7_E29 = LCELL( _EQ523); - _EQ523 = _LC5_E29 & _LC6_E29 - # _LC1_E29 & _LC5_E29 - # _LC2_D20 & _LC6_E29 - # _LC1_E29 & _LC2_D20; - --- Node name is '|ay:AY3|:447' from file "ay.tdf" line 276, column 39 --- Equation name is '_LC2_E28', type is buried -_LC2_E28 = DFFE( _EQ524, GLOBAL( TG42), VCC, VCC, VCC); - _EQ524 = _EC5_E & !_EC9_E & _LC2_E5 & _LC5_E5; - --- Node name is '|ay:AY3|:448' from file "ay.tdf" line 280, column 16 --- Equation name is '_LC4_E35', type is buried -_LC4_E35 = DFFE( _EQ525, GLOBAL( TG42), VCC, VCC, VCC); - _EQ525 = _EC2_E & !_EC9_E & _EC13_E & _LC3_E35; - --- Node name is '|ay:AY3|:449' from file "ay.tdf" line 284, column 16 --- Equation name is '_LC4_E6', type is buried -_LC4_E6 = DFFE( _EQ526, GLOBAL( TG42), VCC, VCC, VCC); - _EQ526 = _EC2_E & !_EC9_E & _EC13_E & _LC3_E6; - --- Node name is '|ay:AY3|:458' from file "ay.tdf" line 348, column 39 --- Equation name is '_LC7_E3', type is buried -_LC7_E3 = DFFE( _EQ527, GLOBAL( TG42), VCC, VCC, VCC); - _EQ527 = !_LC1_A10 & !_LC2_E14 & _LC4_E3 & !_LC5_E28; - --- Node name is '|ay:AY3|:459' from file "ay.tdf" line 357, column 19 --- Equation name is '_LC2_A18', type is buried -_LC2_A18 = DFFE( _LC7_E33, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|:460' from file "ay.tdf" line 357, column 23 --- Equation name is '_LC7_E33', type is buried -_LC7_E33 = DFFE( _EQ528, GLOBAL( TG42), VCC, VCC, VCC); - _EQ528 = _LC6_E36 - # _LC2_E21 - # _LC5_E35 - # _LC1_E35; - --- Node name is '|ay:AY3|:461' from file "ay.tdf" line 358, column 19 --- Equation name is '_LC5_A3', type is buried -_LC5_A3 = DFFE( _LC7_E36, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|ay:AY3|:462' from file "ay.tdf" line 358, column 23 --- Equation name is '_LC7_E36', type is buried -_LC7_E36 = DFFE( _EQ529, GLOBAL( TG42), VCC, VCC, VCC); - _EQ529 = _LC1_E36 - # _LC2_E35 - # _LC5_E35 - # _LC6_E36; - --- Node name is '|ay:AY3|:481' from file "ay.tdf" line 121, column 34 --- Equation name is '_LC7_E2', type is buried -!_LC7_E2 = _LC7_E2~NOT; -_LC7_E2~NOT = LCELL( _EQ530); - _EQ530 = _LC3_E10 & _LC6_E2 & _LC6_E10 - # !_LC6_E2 & !_LC6_E10 - # !_LC3_E10 & !_LC6_E10 - # _LC4_E2; - --- Node name is '|ay:AY3|:495' from file "ay.tdf" line 124, column 43 --- Equation name is '_LC2_E2', type is buried -!_LC2_E2 = _LC2_E2~NOT; -_LC2_E2~NOT = LCELL( _EQ531); - _EQ531 = _LC3_E10 & _LC6_E2 - # _LC4_E2 - # !_LC6_E10; - --- Node name is '|ay:AY3|:536' from file "ay.tdf" line 167, column 3 --- Equation name is '_LC3_E1', type is buried -!_LC3_E1 = _LC3_E1~NOT; -_LC3_E1~NOT = LCELL( _EQ532); - _EQ532 = !_LC4_E1 & !_LC7_E28; - --- Node name is '|ay:AY3|~647~1' from file "ay.tdf" line 207, column 9 --- Equation name is '_LC1_E16', type is buried --- synthesized logic cell -_LC1_E16 = LCELL( _EQ533); - _EQ533 = !_LC2_E16 - # !_LC8_E16; - --- Node name is '|ay:AY3|:650' from file "ay.tdf" line 210, column 44 --- Equation name is '_LC5_E9', type is buried -!_LC5_E9 = _LC5_E9~NOT; -_LC5_E9~NOT = LCELL( _EQ534); - _EQ534 = !_LC1_E9 & !_LC4_E16 - # !_LC1_E9 & !_LC4_E9 - # !_LC4_E16 & !_LC6_E26 - # !_LC4_E9 & !_LC6_E26; - --- Node name is '|ay:AY3|:671' from file "ay.tdf" line 218, column 34 --- Equation name is '_LC1_E19', type is buried -_LC1_E19 = LCELL( _EQ535); - _EQ535 = _EC5_E - # !_LC1_E31; - --- Node name is '|ay:AY3|:687' from file "ay.tdf" line 218, column 34 --- Equation name is '_LC8_E26', type is buried -!_LC8_E26 = _LC8_E26~NOT; -_LC8_E26~NOT = LCELL( _EQ536); - _EQ536 = !_EC3_E & !_EC5_E & !_EC11_E & _LC1_E31; - --- Node name is '|ay:AY3|:693' from file "ay.tdf" line 218, column 34 --- Equation name is '_LC1_E26_CARRY', type is buried -!_LC1_E26_CARRY = _LC1_E26_CARRY~NOT; -_LC1_E26_CARRY~NOT = CARRY( _EQ537); - _EQ537 = !_EC12_E & !_LC8_E26; - --- Node name is '|ay:AY3|:698' from file "ay.tdf" line 218, column 34 --- Equation name is '_LC2_E26_CARRY', type is buried -!_LC2_E26_CARRY = _LC2_E26_CARRY~NOT; -_LC2_E26_CARRY~NOT = CARRY( _EQ538); - _EQ538 = !_EC4_E & !_LC1_E26_CARRY; - --- Node name is '|ay:AY3|:703' from file "ay.tdf" line 218, column 34 --- Equation name is '_LC3_E26_CARRY', type is buried -!_LC3_E26_CARRY = _LC3_E26_CARRY~NOT; -_LC3_E26_CARRY~NOT = CARRY( _EQ539); - _EQ539 = !_EC13_E & !_LC2_E26_CARRY; - --- Node name is '|ay:AY3|:709' from file "ay.tdf" line 218, column 34 --- Equation name is '_LC4_E26_CARRY', type is buried -!_LC4_E26_CARRY = _LC4_E26_CARRY~NOT; -_LC4_E26_CARRY~NOT = CARRY( _EQ540); - _EQ540 = !_EC2_E & !_LC3_E26_CARRY; - --- Node name is '|ay:AY3|:714' from file "ay.tdf" line 218, column 34 --- Equation name is '_LC5_E26_CARRY', type is buried -!_LC5_E26_CARRY = _LC5_E26_CARRY~NOT; -_LC5_E26_CARRY~NOT = CARRY( _EQ541); - _EQ541 = !_EC9_E & !_LC4_E26_CARRY; - --- Node name is '|ay:AY3|~778~1' from file "ay.tdf" line 259, column 23 --- Equation name is '_LC1_E27', type is buried --- synthesized logic cell -_LC1_E27 = LCELL( _EQ542); - _EQ542 = !_EC5_E & _LC2_E27 - # _EC5_E & _LC7_E29; - --- Node name is '|ay:AY3|:779' from file "ay.tdf" line 266, column 25 --- Equation name is '_LC7_E25', type is buried -_LC7_E25 = LCELL( _EQ543); - _EQ543 = _LC3_E5 & _LC4_E16; - --- Node name is '|ay:AY3|:787' from file "ay.tdf" line 277, column 50 --- Equation name is '_LC2_B2_CARRY', type is buried --- |ay:AY3|:787 is in Up/Down Counter Mode -_LC2_B2_CARRY = CARRY( _EQ544); - _EQ544 = _LC1_B2 & _LC2_B2; - --- Node name is '|ay:AY3|:791' from file "ay.tdf" line 277, column 50 --- Equation name is '_LC3_B2_CARRY', type is buried --- |ay:AY3|:791 is in Up/Down Counter Mode -_LC3_B2_CARRY = CARRY( _EQ545); - _EQ545 = _LC2_B2_CARRY & _LC3_B2; - --- Node name is '|ay:AY3|:795' from file "ay.tdf" line 277, column 50 --- Equation name is '_LC4_B2_CARRY', type is buried --- |ay:AY3|:795 is in Up/Down Counter Mode -_LC4_B2_CARRY = CARRY( _EQ546); - _EQ546 = _LC3_B2_CARRY & _LC4_B2; - --- Node name is '|ay:AY3|:799' from file "ay.tdf" line 277, column 50 --- Equation name is '_LC5_B2_CARRY', type is buried --- |ay:AY3|:799 is in Up/Down Counter Mode -_LC5_B2_CARRY = CARRY( _EQ547); - _EQ547 = _LC4_B2_CARRY & _LC5_B2; - --- Node name is '|ay:AY3|:801' from file "ay.tdf" line 277, column 50 --- Equation name is '_LC6_B2_CARRY', type is buried --- |ay:AY3|:801 is in Clearable Counter Mode -_LC6_B2_CARRY = CARRY( _EQ548); - _EQ548 = !_LC5_B2_CARRY & _LC7_B2 - # _LC5_B2_CARRY & !_LC7_B2; - --- Node name is '|ay:AY3|~1027~1' from file "ay.tdf" line 348, column 57 --- Equation name is '_LC4_E3', type is buried --- synthesized logic cell -_LC4_E3 = LCELL( _EQ549); - _EQ549 = !_LC2_E29 & !_LC5_E19 & !_LC8_E3; - --- Node name is '|ay:AY3|~1060~1' from file "ay.tdf" line 284, column 50 --- Equation name is '_LC3_E6', type is buried --- synthesized logic cell -_LC3_E6 = LCELL( _EQ550); - _EQ550 = _EC3_E & _EC5_E & _EC11_E & _LC7_E28; - --- Node name is '|ay:AY3|~1071~1' from file "ay.tdf" line 280, column 50 --- Equation name is '_LC3_E35', type is buried --- synthesized logic cell -_LC3_E35 = LCELL( _EQ551); - _EQ551 = _EC3_E & !_EC5_E & _EC11_E & _LC7_E28; - --- Node name is '|ay:AY3|~1085~1' from file "ay.tdf" line 276, column 94 --- Equation name is '_LC5_E5', type is buried --- synthesized logic cell -_LC5_E5 = LCELL( _EQ552); - _EQ552 = _EC2_E & _EC3_E & !_EC11_E & _EC13_E; - --- Node name is '|ay:AY3|~1085~2' from file "ay.tdf" line 276, column 94 --- Equation name is '_LC2_E5', type is buried --- synthesized logic cell -_LC2_E5 = LCELL( _EQ553); - _EQ553 = _LC2_E16 & !_LC6_B2 & _LC7_E28; - --- Node name is '|ay:AY3|~1095~1' from file "ay.tdf" line 262, column 47 --- Equation name is '_LC4_E5', type is buried --- synthesized logic cell -_LC4_E5 = LCELL( _EQ554); - _EQ554 = _EC3_E & !_EC5_E & !_EC11_E & _LC7_E28; - --- Node name is '|ay:AY3|~1123~1' from file "ay.tdf" line 247, column 40 --- Equation name is '_LC1_E5', type is buried --- synthesized logic cell -_LC1_E5 = LCELL( _EQ555); - _EQ555 = !_EC3_E & _EC11_E & _LC7_E28 - # !_EC3_E & _EC5_E & _LC7_E28; - --- Node name is '|ay:AY3|~1137~1' from file "ay.tdf" line 240, column 49 --- Equation name is '_LC8_E35', type is buried --- synthesized logic cell -_LC8_E35 = LCELL( _EQ556); - _EQ556 = !_EC3_E & _EC5_E & _EC11_E & _LC7_E28; - --- Node name is '|ay:AY3|~1150~1' from file "ay.tdf" line 233, column 49 --- Equation name is '_LC7_E35', type is buried --- synthesized logic cell -_LC7_E35 = LCELL( _EQ557); - _EQ557 = !_EC3_E & !_EC5_E & _EC11_E & _LC7_E28; - --- Node name is '|ay:AY3|~1163~1' from file "ay.tdf" line 226, column 49 --- Equation name is '_LC6_E35', type is buried --- synthesized logic cell -_LC6_E35 = LCELL( _EQ558); - _EQ558 = !_EC3_E & _EC5_E & !_EC11_E & _LC7_E28; - --- Node name is '|ay:AY3|~1193~1' from file "ay.tdf" line 207, column 27 --- Equation name is '_LC1_E8', type is buried --- synthesized logic cell -_LC1_E8 = LCELL( _EQ559C); - _EQ559C = _EQ559; - _EQ559 = !_LC2_E26 & !_LC3_E26 & !_LC4_E26 & !_LC5_E26; - --- Node name is '|ay:AY3|:1193' from file "ay.tdf" line 207, column 27 --- Equation name is '_LC2_E8', type is buried -!_LC2_E8 = _LC2_E8~NOT; -_LC2_E8~NOT = LCELL( _EQ560C); - _EQ560C = _EQ560 & CASCADE( _EQ559C); - _EQ560 = !_LC2_E19 & !_LC4_E19 & !_LC6_E21 & !_LC7_E26; - --- Node name is '|dcp:DECODE|AROM16' from file "dcp.tdf" line 131, column 2 --- Equation name is '_LC1_C3', type is buried -_LC1_C3 = DFFE( _EQ561, _LC2_D13, /reset, VCC, _LC7_D21); - _EQ561 = D0 & !D1 - # D1 & _LC1_C3; - --- Node name is '|dcp:DECODE|BLK_C' from file "dcp.tdf" line 611, column 12 --- Equation name is '_LC2_C21', type is buried -_LC2_C21 = LCELL( _EQ562); - _EQ562 = !_LC1_C16 & _LC2_C31 & !_LC8_C21 - # _LC1_C16 & !_LC2_C31 & !_LC8_C21; - --- Node name is '|dcp:DECODE|CLK21' from file "dcp.tdf" line 279, column 10 --- Equation name is '_LC1_C6', type is buried -_LC1_C6 = DFFE( _EQ563, GLOBAL( TG42), VCC, VCC, VCC); - _EQ563 = _LC3_E28 & _LC7_F1 - # !_LC3_E28 & !_LC7_F1; - --- Node name is '|dcp:DECODE|CNF3' from file "dcp.tdf" line 130, column 5 --- Equation name is '_LC3_C31', type is buried -_LC3_C31 = DFFE( _EQ564, _LC2_D13, /reset, VCC, _LC7_D21); - _EQ564 = d2 & d3 - # !d2 & _LC3_C31; - --- Node name is '|dcp:DECODE|CNF4' from file "dcp.tdf" line 130, column 5 --- Equation name is '_LC6_C27', type is buried -_LC6_C27 = DFFE( _EQ565, _LC2_D13, /reset, VCC, _LC7_D21); - _EQ565 = d2 & d4 - # !d2 & _LC6_C27; - --- Node name is '|dcp:DECODE|CNF5' from file "dcp.tdf" line 130, column 5 --- Equation name is '_LC5_D14', type is buried -_LC5_D14 = DFFE( _EQ566, _LC2_D13, /reset, VCC, _LC7_D21); - _EQ566 = d2 & d5 - # !d2 & _LC5_D14; - --- Node name is '|dcp:DECODE|CNF6' from file "dcp.tdf" line 130, column 5 --- Equation name is '_LC2_D12', type is buried -_LC2_D12 = DFFE( _EQ567, _LC2_D13, /reset, VCC, _LC7_D21); - _EQ567 = d2 & d6 - # !d2 & _LC2_D12; - --- Node name is '|dcp:DECODE|CNF7' from file "dcp.tdf" line 130, column 5 --- Equation name is '_LC1_D12', type is buried -_LC1_D12 = DFFE( _EQ568, _LC2_D13, /reset, VCC, _LC7_D21); - _EQ568 = d2 & d7 - # !d2 & _LC1_D12; - --- Node name is '|dcp:DECODE|DCP_RES' from file "dcp.tdf" line 620, column 13 --- Equation name is '_LC3_D19', type is buried -_LC3_D19 = DFFE( _EQ569, GLOBAL( TG42), VCC, VCC, VCC); - _EQ569 = !/io & _LC1_D36 & /m1; - --- Node name is '|dcp:DECODE|DD0' from file "dcp.tdf" line 137, column 4 --- Equation name is '_LC7_D26', type is buried -_LC7_D26 = DFFE( _EQ570, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - _EQ570 = _LC2_D34 & _LC8_D31 - # !_LC2_D34 & _LC4_D30; - --- Node name is '|dcp:DECODE|DD1' from file "dcp.tdf" line 137, column 4 --- Equation name is '_LC2_D26', type is buried -_LC2_D26 = DFFE( _EQ571, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - _EQ571 = _LC2_D31 & _LC2_D34 - # !_LC2_D34 & _LC3_D36; - --- Node name is '|dcp:DECODE|DD2' from file "dcp.tdf" line 137, column 4 --- Equation name is '_LC2_D33', type is buried -_LC2_D33 = DFFE( _EQ572, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - _EQ572 = _LC2_D34 & _LC7_D31 - # !_LC2_D34 & _LC3_D30; - --- Node name is '|dcp:DECODE|DD3' from file "dcp.tdf" line 137, column 4 --- Equation name is '_LC4_D33', type is buried -_LC4_D33 = DFFE( _EQ573, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - _EQ573 = _LC2_D34 & _LC4_D16 - # !_LC2_D34 & _LC7_D30; - --- Node name is '|dcp:DECODE|DD4' from file "dcp.tdf" line 137, column 4 --- Equation name is '_LC1_D20', type is buried -_LC1_D20 = DFFE( _EQ574, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - _EQ574 = _LC2_D34 - # _LC6_D30; - --- Node name is '|dcp:DECODE|DD5' from file "dcp.tdf" line 137, column 4 --- Equation name is '_LC3_D34', type is buried -_LC3_D34 = DFFE( _EQ575, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - _EQ575 = _LC2_D34 & !_LC6_D31 - # !_LC2_D34 & _LC8_D34; - --- Node name is '|dcp:DECODE|DD6' from file "dcp.tdf" line 137, column 4 --- Equation name is '_LC6_D26', type is buried -_LC6_D26 = DFFE( _EQ576, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - _EQ576 = _LC2_D34 - # _LC7_D34; - --- Node name is '|dcp:DECODE|DD7' from file "dcp.tdf" line 137, column 4 --- Equation name is '_LC5_D20', type is buried -_LC5_D20 = DFFE( _EQ577, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - _EQ577 = _LC2_D34 - # _LC6_D34; - --- Node name is '|dcp:DECODE|GRAF_X' from file "dcp.tdf" line 605, column 12 --- Equation name is '_LC1_C16', type is buried -_LC1_C16 = LCELL( _EQ578); - _EQ578 = _EC1_C & _EC7_C & !_EC10_C & !_EC12_C; - --- Node name is '|dcp:DECODE|HDD_A0' from file "dcp.tdf" line 204, column 7 --- Equation name is '_LC4_C32', type is buried -_LC4_C32 = DFFE( _EQ579, GLOBAL( TG42), VCC, VCC, VCC); - _EQ579 = _LC1_C22 & !_LC2_C22 & _LC2_C36 - # _LC1_C22 & _LC2_C22 & !_LC2_C36 - # _LC1_C22 & !_LC2_C22 & !_LC6_C24; - --- Node name is '|dcp:DECODE|HDD_A1' from file "dcp.tdf" line 204, column 7 --- Equation name is '_LC4_C16', type is buried -_LC4_C16 = DFFE( _EQ580, GLOBAL( TG42), VCC, VCC, VCC); - _EQ580 = _LC2_C22 & !_LC2_C36 & _LC6_C24 - # !_LC2_C22 & _LC2_C36; - --- Node name is '|dcp:DECODE|HDD_A2' from file "dcp.tdf" line 204, column 7 --- Equation name is '_LC4_C30', type is buried -_LC4_C30 = DFFE( _EQ581, GLOBAL( TG42), VCC, VCC, VCC); - _EQ581 = !_LC2_C22 & _LC2_C36 & _LC6_C24 - # _LC2_C22 & !_LC2_C36; - --- Node name is '|dcp:DECODE|/IOMX' from file "dcp.tdf" line 157, column 2 --- Equation name is '_LC7_D3', type is buried -!_LC7_D3 = _LC7_D3~NOT; -_LC7_D3~NOT = DFFE(!_LC4_D3, GLOBAL( TG42), _LC8_F32, VCC, _LC1_C6); - --- Node name is '|dcp:DECODE|/IOMX~1' from file "dcp.tdf" line 157, column 2 --- Equation name is '_LC8_D3', type is buried --- synthesized logic cell -!_LC8_D3 = _LC8_D3~NOT; -_LC8_D3~NOT = LCELL( _LC7_D3); - --- Node name is '|dcp:DECODE|/IOMY' from file "dcp.tdf" line 158, column 2 --- Equation name is '_LC3_C12', type is buried -!_LC3_C12 = _LC3_C12~NOT; -_LC3_C12~NOT = DFFE( _EQ582, GLOBAL( TG42), _LC8_C30, VCC, _LC1_C6); - _EQ582 = !_LC1_D35 & _LC4_A28 & !_LC7_D3; - --- Node name is '|dcp:DECODE|/IOMZ' from file "dcp.tdf" line 188, column 2 --- Equation name is '_LC2_C6', type is buried -!_LC2_C6 = _LC2_C6~NOT; -_LC2_C6~NOT = DFFE( _EQ583, GLOBAL( TG42), _LC8_C30, VCC, _LC1_C6); - _EQ583 = !_LC1_D35 & _LC5_C12 & !_LC7_D3; - --- Node name is '|dcp:DECODE|IO_RW' from file "dcp.tdf" line 492, column 11 --- Equation name is '_LC1_E21', type is buried -!_LC1_E21 = _LC1_E21~NOT; -_LC1_E21~NOT = DFFE(!/io, GLOBAL( TG42), /m1, VCC, VCC); - --- Node name is '|dcp:DECODE|IO_RWM' from file "dcp.tdf" line 490, column 12 --- Equation name is '_LC6_C34', type is buried -!_LC6_C34 = _LC6_C34~NOT; -_LC6_C34~NOT = DFFE( /m1, GLOBAL(!/io), _LC5_C35, VCC, VCC); - --- Node name is '|dcp:DECODE|/IO_WAIT' from file "dcp.tdf" line 537, column 13 --- Equation name is '_LC5_C34', type is buried -_LC5_C34 = LCELL( _EQ584); - _EQ584 = _LC6_C34 - # _LC2_C34; - --- Node name is '|dcp:DECODE|/IOWR' from file "dcp.tdf" line 645, column 11 --- Equation name is '_LC2_D13', type is buried -_LC2_D13 = LCELL( _EQ585); - _EQ585 = /wr - # /io - # !/m1; - --- Node name is '|dcp:DECODE|MA_CT0' from file "dcp.tdf" line 170, column 7 --- Equation name is '_LC6_C23', type is buried -_LC6_C23 = DFFE( _EQ586, GLOBAL( TG42), VCC, VCC, _LC1_C6); - _EQ586 = !_LC5_C23 & !_LC6_C23; - --- Node name is '|dcp:DECODE|MA_CT1' from file "dcp.tdf" line 170, column 7 --- Equation name is '_LC3_C23', type is buried -_LC3_C23 = DFFE( _EQ587, GLOBAL( TG42), VCC, VCC, _LC1_C6); - _EQ587 = _LC3_C23 & !_LC5_C23 & !_LC6_C23 - # !_LC3_C23 & !_LC5_C23 & _LC6_C23; - --- Node name is '|dcp:DECODE|MC_RQ' from file "dcp.tdf" line 437, column 11 --- Equation name is '_LC4_C35', type is buried -_LC4_C35 = DFFE( _EQ588, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ588 = _LC2_C35 & _LC7_C33 - # /rd & /wr; - --- Node name is '|dcp:DECODE|MEM_RW' from file "dcp.tdf" line 489, column 12 --- Equation name is '_LC7_C33', type is buried -!_LC7_C33 = _LC7_C33~NOT; -_LC7_C33~NOT = DFFE( _EQ589, GLOBAL(!/mr), _LC4_C33, VCC, VCC); - _EQ589 = !blk_mem & /rf; - --- Node name is '|dcp:DECODE|MEM_WR' from file "dcp.tdf" line 722, column 11 --- Equation name is '_LC1_C32', type is buried -_LC1_C32 = DFFE( _EQ590, GLOBAL( TG42), GLOBAL(!/io), VCC, _LC3_F35); - _EQ590 = _LC1_D36 & _LC5_C32 & _LC7_C32; - --- Node name is '|dcp:DECODE|MPGS0' from file "dcp.tdf" line 123, column 6 --- Equation name is '_LC6_C21', type is buried -_LC6_C21 = LCELL( _EQ591); - _EQ591 = _LC3_C15 & !_LC8_C24 - # _LC6_C24 & !_LC8_C24 - # _LC6_C24 & _LC8_D31; - --- Node name is '|dcp:DECODE|MPGS1' from file "dcp.tdf" line 123, column 6 --- Equation name is '_LC5_C36', type is buried -_LC5_C36 = LCELL( _EQ592); - _EQ592 = _LC2_C3 & !_LC6_C24 - # !_LC6_C24 & _LC8_C24 - # _LC2_D31 & _LC8_C24; - --- Node name is '|dcp:DECODE|MPGS2' from file "dcp.tdf" line 123, column 6 --- Equation name is '_LC2_C20', type is buried -_LC2_C20 = LCELL( _EQ593); - _EQ593 = _LC6_C3 & !_LC6_C24 & !_LC8_C24 - # _LC6_C24 & _LC7_D31 & _LC8_C24; - --- Node name is '|dcp:DECODE|MPGS3' from file "dcp.tdf" line 123, column 6 --- Equation name is '_LC5_C21', type is buried -_LC5_C21 = LCELL( _EQ594); - _EQ594 = !_LC6_C24 & _LC8_C24 - # !_LC6_C24 & _LC6_F17 - # _LC6_C24 & !_LC8_C24 - # _LC4_D16 & _LC8_C24; - --- Node name is '|dcp:DECODE|MPGS4' from file "dcp.tdf" line 123, column 6 --- Equation name is '_LC7_C24', type is buried -_LC7_C24 = LCELL( _EQ595); - _EQ595 = _LC6_C24 & _LC8_C24; - --- Node name is '|dcp:DECODE|MPGS5' from file "dcp.tdf" line 123, column 6 --- Equation name is '_LC4_C21', type is buried -_LC4_C21 = LCELL( _EQ596); - _EQ596 = !_LC6_C24 - # !_LC8_C24 - # !_LC6_D31; - --- Node name is '|dcp:DECODE|/MR_WAIT' from file "dcp.tdf" line 484, column 13 --- Equation name is '_LC4_C34', type is buried -_LC4_C34 = LCELL( _EQ597); - _EQ597 = !_LC6_D24 & !_LC8_F15 - # _LC4_A28 - # _LC7_C33; - --- Node name is '|dcp:DECODE|PGS0' from file "dcp.tdf" line 124, column 5 --- Equation name is '_LC3_C20', type is buried -_LC3_C20 = DFFE( _EQ598, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ598 = _LC4_A28 & !_LC4_C20 & _LC7_D26 - # _LC4_C20 & _LC6_C21; - --- Node name is '|dcp:DECODE|PGS1' from file "dcp.tdf" line 124, column 5 --- Equation name is '_LC8_C20', type is buried -_LC8_C20 = DFFE( _EQ599, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ599 = _LC2_D26 & _LC4_A28 & !_LC4_C20 - # _LC4_C20 & _LC5_C36; - --- Node name is '|dcp:DECODE|PGS2' from file "dcp.tdf" line 124, column 5 --- Equation name is '_LC5_C20', type is buried -_LC5_C20 = DFFE( _EQ600, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ600 = _LC2_D33 & _LC4_A28 & !_LC4_C20 - # _LC2_C20 & _LC4_C20; - --- Node name is '|dcp:DECODE|PGS3' from file "dcp.tdf" line 124, column 5 --- Equation name is '_LC3_C21', type is buried -_LC3_C21 = DFFE( _EQ601, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ601 = _LC4_A28 & !_LC4_C20 & _LC4_D33 - # _LC4_C20 & _LC5_C21; - --- Node name is '|dcp:DECODE|PGS4' from file "dcp.tdf" line 124, column 5 --- Equation name is '_LC6_C20', type is buried -_LC6_C20 = DFFE( _EQ602, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ602 = _LC1_D20 & _LC4_A28 & !_LC4_C20 - # _LC4_C20 & _LC7_C24; - --- Node name is '|dcp:DECODE|PGS5' from file "dcp.tdf" line 124, column 5 --- Equation name is '_LC7_C21', type is buried -_LC7_C21 = DFFE( _EQ603, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ603 = _LC3_D34 & _LC4_A28 & !_LC4_C20 - # _LC4_C20 & _LC4_C21; - --- Node name is '|dcp:DECODE|PGS6' from file "dcp.tdf" line 124, column 5 --- Equation name is '_LC7_C20', type is buried -_LC7_C20 = DFFE( _EQ604, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ604 = _LC4_A28 & _LC6_D26 - # _LC4_C20; - --- Node name is '|dcp:DECODE|PGS7' from file "dcp.tdf" line 124, column 5 --- Equation name is '_LC1_C20', type is buried -_LC1_C20 = DFFE( _EQ605, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ605 = _LC4_C20 - # _LC4_A28 & _LC5_D20; - --- Node name is '|dcp:DECODE|PG00' from file "dcp.tdf" line 687, column 7 --- Equation name is '_LC3_C15', type is buried -_LC3_C15 = LCELL( _EQ606); - _EQ606 = _LC2_C10 & !_LC4_D12 - # !_LC5_C3; - --- Node name is '|dcp:DECODE|PG01' from file "dcp.tdf" line 686, column 7 --- Equation name is '_LC2_C3', type is buried -_LC2_C3 = LCELL( _EQ607); - _EQ607 = _LC3_C3 & !_LC4_D12 - # !_LC5_C3; - --- Node name is '|dcp:DECODE|PG02' from file "dcp.tdf" line 685, column 7 --- Equation name is '_LC6_C3', type is buried -_LC6_C3 = LCELL( _EQ608); - _EQ608 = _LC1_C3 & !_LC4_D12 - # _LC1_C3 & !_LC5_C3; - --- Node name is '|dcp:DECODE|PG03' from file "dcp.tdf" line 684, column 7 --- Equation name is '_LC6_F17', type is buried -_LC6_F17 = LCELL( _EQ609); - _EQ609 = _LC4_D12 - # !_LC5_C3; - --- Node name is '|dcp:DECODE|PG33' from file "dcp.tdf" line 680, column 21 --- Equation name is '_LC4_D16', type is buried -_LC4_D16 = LCELL( _EQ610); - _EQ610 = !_LC1_D12 & _LC3_D12 - # _LC1_D12 & _LC4_D13; - --- Node name is '|dcp:DECODE|PN0' from file "dcp.tdf" line 127, column 4 --- Equation name is '_LC8_D31', type is buried -_LC8_D31 = DFFE( D0, _LC2_D13, _LC6_D14, VCC, _LC8_D21); - --- Node name is '|dcp:DECODE|PN1' from file "dcp.tdf" line 127, column 4 --- Equation name is '_LC2_D31', type is buried -_LC2_D31 = DFFE( D1, _LC2_D13, _LC6_D14, VCC, _LC8_D21); - --- Node name is '|dcp:DECODE|PN2' from file "dcp.tdf" line 127, column 4 --- Equation name is '_LC7_D31', type is buried -_LC7_D31 = DFFE( d2, _LC2_D13, _LC6_D14, VCC, _LC8_D21); - --- Node name is '|dcp:DECODE|PN3' from file "dcp.tdf" line 127, column 4 --- Equation name is '_LC8_D13', type is buried -_LC8_D13 = DFFE( d3, _LC2_D13, _LC6_D14, VCC, _LC8_D21); - --- Node name is '|dcp:DECODE|PN4' from file "dcp.tdf" line 127, column 4 --- Equation name is '_LC6_D13', type is buried -_LC6_D13 = DFFE( d4, _LC2_D13, _LC6_D14, VCC, _LC8_D21); - --- Node name is '|dcp:DECODE|PN5' from file "dcp.tdf" line 127, column 4 --- Equation name is '_LC3_D14', type is buried -_LC3_D14 = DFFE( d5, _LC2_D13, _LC7_D14, VCC, _LC8_D21); - --- Node name is '|dcp:DECODE|PN6' from file "dcp.tdf" line 127, column 4 --- Equation name is '_LC4_D13', type is buried -_LC4_D13 = DFFE( d6, _LC2_D13, _LC7_D13, VCC, _LC8_D21); - --- Node name is '|dcp:DECODE|PN7' from file "dcp.tdf" line 127, column 4 --- Equation name is '_LC6_D31', type is buried -_LC6_D31 = DFFE( d7, _LC2_D13, _LC7_D13, VCC, _LC8_D21); - --- Node name is '|dcp:DECODE|PORTS_X' from file "dcp.tdf" line 513, column 13 --- Equation name is '_LC8_C30', type is buried -_LC8_C30 = DFFE( _EQ611, GLOBAL( TG42), VCC, VCC, VCC); - _EQ611 = !_LC1_D34 & _LC3_D20 & !_LC4_D34 & !_LC5_D34 - # !_LC1_D34 & !_LC3_D20 & !_LC4_D34 & _LC5_D34; - --- Node name is '|dcp:DECODE|RFC' from file "dcp.tdf" line 178, column 2 --- Equation name is '_LC3_F32', type is buried -_LC3_F32 = DFFE( _EQ612, GLOBAL( TG42), VCC, VCC, _LC2_F32); - _EQ612 = !_LC4_C35 - # _LC1_F32; - --- Node name is '|dcp:DECODE|RFT' from file "dcp.tdf" line 177, column 2 --- Equation name is '_LC1_F32', type is buried -!_LC1_F32 = _LC1_F32~NOT; -_LC1_F32~NOT = DFFE( VCC, _LC7_A29, _LC3_F32, VCC, VCC); - --- Node name is '|dcp:DECODE|SC0' from file "dcp.tdf" line 128, column 4 --- Equation name is '_LC4_D12', type is buried -_LC4_D12 = DFFE( D0, _LC2_D13, _LC7_D12, VCC, _LC6_D21); - --- Node name is '|dcp:DECODE|SC1' from file "dcp.tdf" line 128, column 4 --- Equation name is '_LC5_D12', type is buried -_LC5_D12 = DFFE( D1, _LC2_D13, _LC7_D12, VCC, _LC6_D21); - --- Node name is '|dcp:DECODE|SC4' from file "dcp.tdf" line 128, column 4 --- Equation name is '_LC3_D12', type is buried -_LC3_D12 = DFFE( d4, _LC2_D13, _LC7_D12, VCC, _LC6_D21); - --- Node name is '|dcp:DECODE|SPR_0' from file "dcp.tdf" line 216, column 6 --- Equation name is '_LC2_C10', type is buried -_LC2_C10 = LCELL( _EQ613); - _EQ613 = !dos & !_LC5_D12 - # !_LC5_D12 & _LC6_D13; - --- Node name is '|dcp:DECODE|SPR_1' from file "dcp.tdf" line 216, column 6 --- Equation name is '_LC3_C3', type is buried -_LC3_C3 = LCELL( _EQ614); - _EQ614 = dos & !_LC5_D12; - --- Node name is '|dcp:DECODE|STARTING' from file "dcp.tdf" line 713, column 13 --- Equation name is '_LC1_D36', type is buried -_LC1_D36 = LCELL( _EQ615); - _EQ615 = _LC1_D36 & /reset - # !/io & !/rd & /reset; - --- Node name is '|dcp:DECODE|SYS' from file "dcp.tdf" line 129, column 2 --- Equation name is '_LC5_C3', type is buried -_LC5_C3 = DFFE(!_LC6_C22, _LC2_D13, /reset, VCC, _LC7_D21); - --- Node name is '|dcp:DECODE|SYS_ENA' from file "dcp.tdf" line 642, column 13 --- Equation name is '_LC7_D21', type is buried -_LC7_D21 = DFFE( _EQ616, GLOBAL( TG42), VCC, VCC, VCC); - _EQ616 = _LC1_D26 & !_LC3_D21 & !_LC4_D26 & _LC7_D19; - --- Node name is '|dcp:DECODE|TB_SW' from file "dcp.tdf" line 132, column 2 --- Equation name is '_LC6_D36', type is buried -!_LC6_D36 = _LC6_D36~NOT; -_LC6_D36~NOT = DFFE( _EQ617, _LC2_D13, /reset, VCC, _LC7_D21); - _EQ617 = !D1 & !_LC6_D36 - # !D0 & !_LC6_D36 - # !D0 & D1; - --- Node name is '|dcp:DECODE|WR_AWGX' from file "dcp.tdf" line 298, column 13 --- Equation name is '_LC2_A15', type is buried -!_LC2_A15 = _LC2_A15~NOT; -_LC2_A15~NOT = DFFE( VCC, !_LC4_C3, _LC1_A15, VCC, VCC); - --- Node name is '|dcp:DECODE|W_TAB0' from file "dcp.tdf" line 161, column 7 --- Equation name is '_LC8_D23', type is buried -_LC8_D23 = LCELL( _EQ618); - _EQ618 = _EC3_C & !_EC9_C & _LC6_D24 - # !_EC3_C & _EC9_C & !_LC6_D24 - # _EC3_C & !_EC6_C; - --- Node name is '|dcp:DECODE|W_TAB1' from file "dcp.tdf" line 161, column 7 --- Equation name is '_LC2_D23', type is buried -_LC2_D23 = LCELL( _EQ619); - _EQ619 = !_EC9_C & _LC6_D24 - # _EC3_C & _EC9_C - # _EC3_C & _LC6_D24 - # !_EC3_C & !_EC9_C - # _EC6_C & !_EC9_C; - --- Node name is '|dcp:DECODE|W_TAB2' from file "dcp.tdf" line 161, column 7 --- Equation name is '_LC1_D23', type is buried -_LC1_D23 = LCELL( _EQ620); - _EQ620 = _EC3_C & !_EC9_C & _LC6_D24 - # _EC3_C & !_EC6_C & _LC6_D24 - # _EC3_C & !_EC6_C & _EC9_C - # !_EC3_C & _EC9_C & _LC6_D24; - --- Node name is '|dcp:DECODE|W_TAB3' from file "dcp.tdf" line 161, column 7 --- Equation name is '_LC3_D29', type is buried -_LC3_D29 = LCELL( _EQ621); - _EQ621 = _EC3_C & _EC6_C & _EC9_C; - --- Node name is '|dcp:DECODE|WT_CT0' from file "dcp.tdf" line 160, column 7 --- Equation name is '_LC3_D23', type is buried -!_LC3_D23 = _LC3_D23~NOT; -_LC3_D23~NOT = DFFE( _EQ622, GLOBAL( TG42), _LC4_A28, VCC, _LC1_C6); - _EQ622 = _LC3_D23 & !_LC7_D23 - # _LC3_D6 & !_LC7_D23; - --- Node name is '|dcp:DECODE|WT_CT1' from file "dcp.tdf" line 160, column 7 --- Equation name is '_LC1_D19', type is buried -!_LC1_D19 = _LC1_D19~NOT; -_LC1_D19~NOT = DFFE( _EQ623, GLOBAL( TG42), _LC4_A28, VCC, _LC1_C6); - _EQ623 = !_LC4_D19 & !_LC7_D27 - # !_LC2_D23 & !_LC4_D19; - --- Node name is '|dcp:DECODE|WT_CT2' from file "dcp.tdf" line 160, column 7 --- Equation name is '_LC5_D27', type is buried --- |dcp:DECODE|WT_CT2 is in Clearable Counter Mode --- synchronous load = !_LC3_D6 --- synchronous clear = !_LC3_D27 -!_LC5_D27 = _LC5_D27~NOT; -_LC5_D27~NOT = DFFE(( _EQ624 & !_LC3_D6 # _LC3_D6) & !_LC3_D27, GLOBAL( TG42), _LC4_A28, VCC, _LC1_C6); - _EQ624 = _LC4_D27_CARRY & !_LC5_D27 - # !_LC4_D27_CARRY & _LC5_D27; - --- Node name is '|dcp:DECODE|WT_CT3' from file "dcp.tdf" line 160, column 7 --- Equation name is '_LC8_D27', type is buried -!_LC8_D27 = _LC8_D27~NOT; -_LC8_D27~NOT = DFFE(!_LC7_D27_CARRY, GLOBAL( TG42), _LC4_A28, VCC, _LC1_C6); - --- Node name is '|dcp:DECODE|X_ADR0' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC1_C7', type is buried -_LC1_C7 = LCELL( _EQ625); - _EQ625 = _LC1_E21 & _LC6_C23 & _LC8_C7 - # _LC2_C22 & !_LC6_C23; - --- Node name is '|dcp:DECODE|X_ADR1' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC4_C7', type is buried -_LC4_C7 = LCELL( _EQ626); - _EQ626 = _LC1_C19 & _LC1_E21 & _LC6_C23 - # _LC5_C7; - --- Node name is '|dcp:DECODE|X_ADR2' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC1_C35', type is buried -_LC1_C35 = LCELL( _EQ627); - _EQ627 = _LC1_E21 & _LC6_C23 & _LC8_C35 - # _LC6_C35; - --- Node name is '|dcp:DECODE|X_ADR3' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC8_C11', type is buried -_LC8_C11 = LCELL( _EQ628); - _EQ628 = _LC1_E21 & _LC3_C11 & _LC6_C23 - # _LC5_C22 & !_LC6_C23; - --- Node name is '|dcp:DECODE|X_ADR4' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC2_C12', type is buried -_LC2_C12 = LCELL( _EQ629); - _EQ629 = _EC7_C & _LC1_E21 & _LC6_C23 - # _LC6_C22 & !_LC6_C23; - --- Node name is '|dcp:DECODE|X_ADR5' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC5_C13', type is buried -_LC5_C13 = LCELL( _EQ630); - _EQ630 = _EC12_C & _LC1_E21 & _LC6_C23 - # _LC7_C13; - --- Node name is '|dcp:DECODE|X_ADR6' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC8_C12', type is buried -_LC8_C12 = LCELL( _EQ631); - _EQ631 = _EC1_C & _LC1_E21 & _LC6_C23 - # _LC4_C12; - --- Node name is '|dcp:DECODE|X_ADR7' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC2_C28', type is buried -_LC2_C28 = LCELL( _EQ632); - _EQ632 = _EC10_C & _LC1_E21 & _LC6_C23 - # _LC6_C28; - --- Node name is '|dcp:DECODE|X_ADR8' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC5_C31', type is buried -!_LC5_C31 = _LC5_C31~NOT; -_LC5_C31~NOT = LCELL( _EQ633C); - _EQ633C = _EQ633 & CASCADE( _EQ634C); - _EQ633 = _LC1_E21 - # !_LC3_C31 & _LC6_C23 - # !dos & !_LC6_C23 - # !dos & !_LC3_C31; - --- Node name is '|dcp:DECODE|X_ADR9' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC2_C27', type is buried -!_LC2_C27 = _LC2_C27~NOT; -_LC2_C27~NOT = LCELL( _EQ635C); - _EQ635C = _EQ635 & CASCADE( _EQ636C); - _EQ635 = _LC1_E21 - # _LC6_C23 & !_LC6_C27 - # !_LC3_D14 & !_LC6_C23 - # !_LC3_D14 & !_LC6_C27; - --- Node name is '|dcp:DECODE|X_ADR10' from file "dcp.tdf" line 206, column 7 --- Equation name is '_LC3_C27', type is buried -_LC3_C27 = LCELL( _EQ637); - _EQ637 = _LC1_E21 & !_LC6_C23 & _LC8_C27 - # !_LC1_E21 & !_LC6_C23 & _LC6_C27; - --- Node name is '|dcp:DECODE|:237' from file "dcp.tdf" line 149, column 2 --- Equation name is '_LC6_F32', type is buried -!_LC6_F32 = _LC6_F32~NOT; -_LC6_F32~NOT = DFFE(!_LC3_E28, GLOBAL( TG42), _LC8_F32, VCC, _LC4_F32); - --- Node name is '|dcp:DECODE|~238~1' from file "dcp.tdf" line 150, column 2 --- Equation name is '_LC7_A1', type is buried --- synthesized logic cell -!_LC7_A1 = _LC7_A1~NOT; -_LC7_A1~NOT = LCELL( _LC7_F32); - --- Node name is '|dcp:DECODE|:238' from file "dcp.tdf" line 150, column 2 --- Equation name is '_LC7_F32', type is buried -!_LC7_F32 = _LC7_F32~NOT; -_LC7_F32~NOT = DFFE( _EQ638, GLOBAL( TG42), _LC8_F32, VCC, _LC5_F32); - _EQ638 = !_LC2_C21 & !_LC3_E28; - --- Node name is '|dcp:DECODE|:239' from file "dcp.tdf" line 145, column 2 --- Equation name is '_LC4_A28', type is buried -_LC4_A28 = DFFE( VCC, GLOBAL( TG42), !_LC2_A28, VCC, _LC5_A28); - --- Node name is '|dcp:DECODE|:240' from file "dcp.tdf" line 146, column 2 --- Equation name is '_LC6_A28', type is buried -!_LC6_A28 = _LC6_A28~NOT; -_LC6_A28~NOT = DFFE(!_LC4_C35, GLOBAL( TG42), !_LC2_A28, VCC, _LC2_F32); - --- Node name is '|dcp:DECODE|:241' from file "dcp.tdf" line 147, column 2 --- Equation name is '_LC8_C21', type is buried -!_LC8_C21 = _LC8_C21~NOT; -_LC8_C21~NOT = DFFE( _EQ639, GLOBAL( TG42), _LC8_F32, VCC, _LC2_F32); - _EQ639 = !_LC4_A28 & !_LC4_C35; - --- Node name is '|dcp:DECODE|:242' from file "dcp.tdf" line 148, column 2 --- Equation name is '_LC5_C1', type is buried -!_LC5_C1 = _LC5_C1~NOT; -_LC5_C1~NOT = DFFE( _EQ640, GLOBAL( TG42), _LC8_F32, VCC, _LC2_F32); - _EQ640 = !_LC4_C35 & !_LC6_C1 & _LC7_C1; - --- Node name is '|dcp:DECODE|:243' from file "dcp.tdf" line 153, column 5 --- Equation name is '_LC8_A23', type is buried -_LC8_A23 = DFFE( _LC2_C36, GLOBAL( TG42), VCC, VCC, _LC2_F32); - --- Node name is '|dcp:DECODE|:245' from file "dcp.tdf" line 155, column 2 --- Equation name is '_LC7_D27', type is buried --- |dcp:DECODE|:245 is in Up/Down Counter Mode --- synchronous load = !_LC8_D3 -!_LC7_D27 = _LC7_D27~NOT; -_LC7_D27~NOT = DFFE((!_LC7_D27 & !_LC8_D3 # _LC8_D3), GLOBAL( TG42), !_LC5_D19, VCC, _LC1_C6); - --- Node name is '|dcp:DECODE|:246' from file "dcp.tdf" line 156, column 2 --- Equation name is '_LC4_D3', type is buried -!_LC4_D3 = _LC4_D3~NOT; -_LC4_D3~NOT = DFFE( _EQ641, GLOBAL( TG42), _LC8_F32, VCC, _LC1_C6); - _EQ641 = !_LC1_E21 & !_LC2_D35 & _LC4_A28; - --- Node name is '|dcp:DECODE|:251' from file "dcp.tdf" line 172, column 2 --- Equation name is '_LC4_C3', type is buried -!_LC4_C3 = _LC4_C3~NOT; -_LC4_C3~NOT = DFFE( _EQ642, GLOBAL( TG42), _LC8_F32, VCC, _LC1_C6); - _EQ642 = /io & _LC3_C23 - # _LC3_C23 & _LC8_C30; - --- Node name is '|dcp:DECODE|:253' from file "dcp.tdf" line 182, column 4 --- Equation name is '_LC6_C11', type is buried -_LC6_C11 = LCELL( _LC2_C31); - --- Node name is '|dcp:DECODE|:255' from file "dcp.tdf" line 182, column 4 --- Equation name is '_LC3_C11', type is buried -_LC3_C11 = LCELL( _EQ643); - _EQ643 = _EC14_C & !_LC2_C31 - # _LC2_C31 & _LC8_C19; - --- Node name is '|dcp:DECODE|:256' from file "dcp.tdf" line 182, column 4 --- Equation name is '_LC8_C35', type is buried -_LC8_C35 = LCELL( _EQ644); - _EQ644 = _EC5_C & !_LC2_C31 - # _LC2_C31 & _LC7_C19; - --- Node name is '|dcp:DECODE|:257' from file "dcp.tdf" line 182, column 4 --- Equation name is '_LC1_C19', type is buried -_LC1_C19 = LCELL( _EQ645); - _EQ645 = _EC16_C & !_LC2_C31 - # _LC2_C31 & _LC6_C19; - --- Node name is '|dcp:DECODE|:258' from file "dcp.tdf" line 182, column 4 --- Equation name is '_LC8_C7', type is buried -_LC8_C7 = LCELL( _EQ646); - _EQ646 = _EC2_C & !_LC2_C31 - # _LC2_C31 & _LC5_C19; - --- Node name is '|dcp:DECODE|:259' from file "dcp.tdf" line 182, column 4 --- Equation name is '_LC8_C27', type is buried -_LC8_C27 = LCELL( _EQ647); - _EQ647 = _LC2_C31 & _LC4_C19 - # !_LC2_C31 & _LC5_C24; - --- Node name is '|dcp:DECODE|:260' from file "dcp.tdf" line 182, column 4 --- Equation name is '_LC2_C11', type is buried -_LC2_C11 = LCELL( _EQ648); - _EQ648 = _LC2_C31 & _LC3_C19 - # !_LC2_C31 & _LC4_C24; - --- Node name is '|dcp:DECODE|:261' from file "dcp.tdf" line 182, column 4 --- Equation name is '_LC7_C27', type is buried -_LC7_C27 = LCELL( _EQ649); - _EQ649 = _LC2_C31 & _LC3_C36 - # !_LC2_C31 & _LC3_C24; - --- Node name is '|dcp:DECODE|:262' from file "dcp.tdf" line 182, column 4 --- Equation name is '_LC6_C31', type is buried -_LC6_C31 = LCELL( _EQ650); - _EQ650 = _LC2_C19 & _LC2_C31 - # _LC2_C24 & !_LC2_C31; - --- Node name is '|dcp:DECODE|:263' from file "dcp.tdf" line 180, column 2 --- Equation name is '_LC2_C31', type is buried -_LC2_C31 = DFFE( _LC1_C16, GLOBAL( TG42), VCC, VCC, _LC7_C23); - --- Node name is '|dcp:DECODE|:264' from file "dcp.tdf" line 184, column 2 --- Equation name is '_LC8_C31', type is buried -_LC8_C31 = LCELL( _EQ651); - _EQ651 = _LC1_C21 & !_LC2_C31 & _LC6_C24 - # !_LC2_C31 & _LC6_C24 & !_LC8_C24; - --- Node name is '|dcp:DECODE|:265' from file "dcp.tdf" line 185, column 2 --- Equation name is '_LC4_C36', type is buried -_LC4_C36 = LCELL( _EQ652); - _EQ652 = _LC2_D31 & _LC8_C24; - --- Node name is '|dcp:DECODE|:267' from file "dcp.tdf" line 187, column 2 --- Equation name is '_LC1_C14', type is buried -_LC1_C14 = DFFE( _EQ653, _LC7_D27, _LC7_C4, VCC, _LC6_C14); - _EQ653 = !_EC8_C & !_EC15_C & _LC7_C14; - --- Node name is '|dcp:DECODE|:268' from file "dcp.tdf" line 196, column 6 --- Equation name is '_LC4_D34', type is buried -_LC4_D34 = DFFE( _LC6_D34, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - --- Node name is '|dcp:DECODE|:269' from file "dcp.tdf" line 196, column 6 --- Equation name is '_LC1_D34', type is buried -_LC1_D34 = DFFE( _LC7_D34, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - --- Node name is '|dcp:DECODE|:270' from file "dcp.tdf" line 196, column 6 --- Equation name is '_LC5_D34', type is buried -_LC5_D34 = DFFE( _LC8_D34, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - --- Node name is '|dcp:DECODE|:271' from file "dcp.tdf" line 196, column 6 --- Equation name is '_LC3_D20', type is buried -_LC3_D20 = DFFE( _LC6_D30, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - --- Node name is '|dcp:DECODE|:272' from file "dcp.tdf" line 196, column 6 --- Equation name is '_LC1_D33', type is buried -_LC1_D33 = DFFE( _LC7_D30, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - --- Node name is '|dcp:DECODE|:273' from file "dcp.tdf" line 196, column 6 --- Equation name is '_LC7_D19', type is buried -_LC7_D19 = DFFE( _LC3_D30, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - --- Node name is '|dcp:DECODE|:274' from file "dcp.tdf" line 196, column 6 --- Equation name is '_LC1_D26', type is buried -_LC1_D26 = DFFE( _LC3_D36, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - --- Node name is '|dcp:DECODE|:275' from file "dcp.tdf" line 196, column 6 --- Equation name is '_LC4_D26', type is buried -_LC4_D26 = DFFE( _LC4_D30, GLOBAL( TG42), _LC2_D19, VCC, !_LC8_D33); - --- Node name is '|dcp:DECODE|:452' from file "dcp.tdf" line 258, column 9 --- Equation name is '_LC8_F32', type is buried -_LC8_F32 = DFFE( VCC, GLOBAL( TG42), VCC, VCC, _LC7_F1); - --- Node name is '|dcp:DECODE|:453' from file "dcp.tdf" line 262, column 10 --- Equation name is '_LC6_D24', type is buried -_LC6_D24 = DFFE( _LC1_D24, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|:454' from file "dcp.tdf" line 262, column 14 --- Equation name is '_LC1_D24', type is buried -!_LC1_D24 = _LC1_D24~NOT; -_LC1_D24~NOT = DFFE( _EQ654, _LC2_D27, /reset, VCC, !_LC5_D31); - _EQ654 = !_LC6_D36 - # !TEST_SWITCH; - --- Node name is '|dcp:DECODE|:457' from file "dcp.tdf" line 275, column 12 --- Equation name is '_LC2_D27', type is buried -_LC2_D27 = DFFE( _EQ655, GLOBAL(!TG42), VCC, VCC, VCC); - _EQ655 = _LC1_C6 & _LC6_D24 - # _LC1_D27 & !_LC6_D24; - --- Node name is '|dcp:DECODE|:458' from file "dcp.tdf" line 275, column 36 --- Equation name is '_LC1_D27', type is buried -_LC1_D27 = DFFE( _EQ656, GLOBAL( TG42), VCC, VCC, VCC); - _EQ656 = _LC1_D27 & _LC3_E28 - # _LC1_D27 & !_LC3_F35 - # !_LC1_D27 & !_LC3_E28 & _LC3_F35; - --- Node name is '|dcp:DECODE|:461' from file "dcp.tdf" line 298, column 30 --- Equation name is '_LC1_A15', type is buried -_LC1_A15 = DFFE( _LC2_A15, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|:463' from file "dcp.tdf" line 315, column 6 --- Equation name is '_LC5_C23', type is buried -_LC5_C23 = LCELL( _EQ657); - _EQ657 = _LC3_E28 & !_LC3_F35; - --- Node name is '|dcp:DECODE|:464' from file "dcp.tdf" line 339, column 30 --- Equation name is '_LC1_C21', type is buried -_LC1_C21 = LCELL( _EQ658); - _EQ658 = !_LC4_D16 & !_LC6_D31 & _LC7_D31 & _LC8_D31; - --- Node name is '|dcp:DECODE|:466' from file "dcp.tdf" line 437, column 26 --- Equation name is '_LC2_C35', type is buried -!_LC2_C35 = _LC2_C35~NOT; -_LC2_C35~NOT = DFFE(!_LC3_C35, GLOBAL( TG42), GLOBAL(!/io), VCC, VCC); - --- Node name is '|dcp:DECODE|:467' from file "dcp.tdf" line 437, column 30 --- Equation name is '_LC3_C35', type is buried -!_LC3_C35 = _LC3_C35~NOT; -_LC3_C35~NOT = DFFE(!_LC1_E21, GLOBAL( TG42), GLOBAL(!/io), VCC, VCC); - --- Node name is '|dcp:DECODE|:470' from file "dcp.tdf" line 489, column 40 --- Equation name is '_LC4_C33', type is buried -_LC4_C33 = LCELL( _EQ659); - _EQ659 = !/mr - # _LC7_C33; - --- Node name is '|dcp:DECODE|:472' from file "dcp.tdf" line 490, column 27 --- Equation name is '_LC5_C35', type is buried -_LC5_C35 = LCELL( _EQ660); - _EQ660 = !/io - # _LC1_E21; - --- Node name is '|dcp:DECODE|:477' from file "dcp.tdf" line 518, column 49 --- Equation name is '_LC1_D35', type is buried -_LC1_D35 = DFFE( _EQ661, GLOBAL( TG42), VCC, VCC, VCC); - _EQ661 = !_LC1_D19 & !_LC5_D27 & !_LC8_D27; - --- Node name is '|dcp:DECODE|:478' from file "dcp.tdf" line 521, column 13 --- Equation name is '_LC5_C14', type is buried -_LC5_C14 = DFFE( _EQ662, GLOBAL( TG42), VCC, VCC, VCC); - _EQ662 = _LC2_C14 & !_LC3_C14 & _LC8_C30; - --- Node name is '|dcp:DECODE|:479' from file "dcp.tdf" line 521, column 28 --- Equation name is '_LC2_C14', type is buried -_LC2_C14 = DFFE( _EQ663, GLOBAL( TG42), VCC, VCC, VCC); - _EQ663 = !_EC4_C & !_EC8_C & !_EC13_C & !_EC15_C; - --- Node name is '|dcp:DECODE|:480' from file "dcp.tdf" line 525, column 27 --- Equation name is '_LC5_C30', type is buried -_LC5_C30 = DFFE( _EQ664, GLOBAL( TG42), VCC, VCC, VCC); - _EQ664 = !_LC1_D34 & !_LC3_D20 & !_LC4_D34 & _LC5_D34; - --- Node name is '|dcp:DECODE|:481' from file "dcp.tdf" line 527, column 27 --- Equation name is '_LC6_C4', type is buried -!_LC6_C4 = _LC6_C4~NOT; -_LC6_C4~NOT = DFFE( VCC, !_LC4_F11, _LC1_C14, VCC, VCC); - --- Node name is '|dcp:DECODE|:483' from file "dcp.tdf" line 537, column 29 --- Equation name is '_LC2_C34', type is buried -!_LC2_C34 = _LC2_C34~NOT; -_LC2_C34~NOT = DFFE(!_LC4_D35, GLOBAL( TG42), !_LC7_C34, VCC, VCC); - --- Node name is '|dcp:DECODE|:484' from file "dcp.tdf" line 537, column 33 --- Equation name is '_LC4_D35', type is buried -_LC4_D35 = DFFE(!_LC5_D35, GLOBAL( TG42), VCC, VCC, _LC1_C6); - --- Node name is '|dcp:DECODE|:485' from file "dcp.tdf" line 539, column 16 --- Equation name is '_LC7_C34', type is buried -_LC7_C34 = DFFE( _EQ665, GLOBAL( TG42), VCC, VCC, VCC); - _EQ665 = _LC5_C22 & _LC6_C22 & !_LC6_D24 & _LC8_C34; - --- Node name is '|dcp:DECODE|:486' from file "dcp.tdf" line 548, column 13 --- Equation name is '_LC2_D35', type is buried -_LC2_D35 = DFFE( _EQ666, GLOBAL( TG42), VCC, VCC, VCC); - _EQ666 = !_LC1_D19 & !_LC3_D23 & !_LC5_D27 & !_LC8_D27; - --- Node name is '|dcp:DECODE|:488' from file "dcp.tdf" line 596, column 9 --- Equation name is '_LC8_C3', type is buried -_LC8_C3 = LCELL( _EQ667); - _EQ667 = _LC6_C24 - # _LC8_C24 - # _LC4_D12 & _LC5_C3; - --- Node name is '|dcp:DECODE|:490' from file "dcp.tdf" line 599, column 11 --- Equation name is '_LC6_C1', type is buried -_LC6_C1 = LCELL( _EQ668); - _EQ668 = /mr - # !/rf - # !_LC8_C3; - --- Node name is '|dcp:DECODE|~494~1' from file "dcp.tdf" line 623, column 16 --- Equation name is '_LC8_D33', type is buried --- synthesized logic cell -!_LC8_D33 = _LC8_D33~NOT; -_LC8_D33~NOT = LCELL(!_LC7_D33); - --- Node name is '|dcp:DECODE|:494' from file "dcp.tdf" line 623, column 16 --- Equation name is '_LC7_D33', type is buried -_LC7_D33 = DFFE( _LC4_A28, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|:496' from file "dcp.tdf" line 634, column 7 --- Equation name is '_LC2_D34', type is buried -_LC2_D34 = LCELL( _EQ669); - _EQ669 = _LC6_D30 & _LC6_D34 & _LC7_D34 & _LC8_D34; - --- Node name is '|dcp:DECODE|:499' from file "dcp.tdf" line 652, column 14 --- Equation name is '_LC6_D21', type is buried -_LC6_D21 = DFFE( _EQ670, GLOBAL( TG42), VCC, VCC, VCC); - _EQ670 = !_LC1_D26 & !_LC3_D21 & !_LC4_D26 & !_LC7_D19; - --- Node name is '|dcp:DECODE|:500' from file "dcp.tdf" line 653, column 14 --- Equation name is '_LC8_D21', type is buried -_LC8_D21 = DFFE( _EQ671, GLOBAL( TG42), VCC, VCC, VCC); - _EQ671 = !_LC1_D26 & !_LC3_D21 & _LC4_D26 & !_LC7_D19; - --- Node name is '|dcp:DECODE|:507' from file "dcp.tdf" line 716, column 8 --- Equation name is '_LC4_C20', type is buried -_LC4_C20 = LCELL( _EQ672); - _EQ672 = /io & !_LC6_C24 - # /io & !_LC8_C24 - # /io & _LC1_D36; - --- Node name is '|dcp:DECODE|:509' from file "dcp.tdf" line 722, column 48 --- Equation name is '_LC7_C32', type is buried -_LC7_C32 = DFFE( _LC8_C32, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|:510' from file "dcp.tdf" line 722, column 52 --- Equation name is '_LC8_C32', type is buried -_LC8_C32 = DFFE( _EQ673, GLOBAL( TG42), VCC, VCC, VCC); - _EQ673 = _LC4_A28 & !/wr; - --- Node name is '|dcp:DECODE|~669~1' from file "dcp.tdf" line 352, column 21 --- Equation name is '_LC5_C7', type is buried --- synthesized logic cell -_LC5_C7 = LCELL( _EQ674); - _EQ674 = _LC1_E21 & _LC3_C22 & !_LC6_C23 - # !_LC1_E21 & !_LC6_C23 & _LC7_C22; - --- Node name is '|dcp:DECODE|~672~1' from file "dcp.tdf" line 352, column 21 --- Equation name is '_LC6_C35', type is buried --- synthesized logic cell -_LC6_C35 = LCELL( _EQ675); - _EQ675 = _LC1_E21 & _LC4_C22 & !_LC6_C23 - # !_LC1_E21 & _LC5_C24 & !_LC6_C23; - --- Node name is '|dcp:DECODE|~681~1' from file "dcp.tdf" line 352, column 21 --- Equation name is '_LC7_C13', type is buried --- synthesized logic cell -_LC7_C13 = LCELL( _EQ676); - _EQ676 = _LC1_E21 & !_LC6_C23 & _LC7_C22 - # !_LC1_E21 & !_LC6_C23 & _LC6_C24; - --- Node name is '|dcp:DECODE|~684~1' from file "dcp.tdf" line 352, column 21 --- Equation name is '_LC4_C12', type is buried --- synthesized logic cell -_LC4_C12 = LCELL( _EQ677); - _EQ677 = !_LC1_E21 & _LC6_C23 - # !_LC1_E21 & _LC8_C24 - # _LC1_E21 & !_LC6_C23 & _LC8_C22; - --- Node name is '|dcp:DECODE|~687~1' from file "dcp.tdf" line 352, column 21 --- Equation name is '_LC6_C28', type is buried --- synthesized logic cell -_LC6_C28 = LCELL( _EQ678); - _EQ678 = _LC1_C24 & _LC1_E21 & !_LC6_C23 - # !_LC1_E21 & !_LC6_C23 & /wr; - --- Node name is '|dcp:DECODE|~690~1' from file "dcp.tdf" line 352, column 21 --- Equation name is '_LC4_C31', type is buried --- synthesized logic cell -!_LC4_C31 = _LC4_C31~NOT; -_LC4_C31~NOT = LCELL( _EQ634C); - _EQ634C = _EQ634; - _EQ634 = !_LC1_E21 - # !_LC2_C11 & !_LC6_C31 - # !_LC6_C23 & !_LC6_C31 - # !_LC2_C11 & _LC6_C23; - --- Node name is '|dcp:DECODE|~693~1' from file "dcp.tdf" line 352, column 21 --- Equation name is '_LC1_C27', type is buried --- synthesized logic cell -!_LC1_C27 = _LC1_C27~NOT; -_LC1_C27~NOT = LCELL( _EQ636C); - _EQ636C = _EQ636; - _EQ636 = !_LC1_E21 - # !_LC7_C27 & !_LC8_C27 - # !_LC6_C23 & !_LC7_C27 - # _LC6_C23 & !_LC8_C27; - --- Node name is '|dcp:DECODE|:779' from file "dcp.tdf" line 371, column 11 --- Equation name is '_LC6_C12', type is buried -_LC6_C12 = LCELL( _EQ679); - _EQ679 = _EC7_C & !_LC1_E21 & !_LC3_C12 & _LC3_C23; - --- Node name is '|dcp:DECODE|:782' from file "dcp.tdf" line 371, column 11 --- Equation name is '_LC8_C13', type is buried -_LC8_C13 = LCELL( _EQ680); - _EQ680 = _EC12_C & !_LC1_E21 & !_LC2_C6 & _LC3_C23; - --- Node name is '|dcp:DECODE|:818' from file "dcp.tdf" line 373, column 11 --- Equation name is '_LC1_C12', type is buried -_LC1_C12 = LCELL( _EQ681); - _EQ681 = _LC6_C12 - # _LC2_C12 & !_LC3_C23; - --- Node name is '|dcp:DECODE|:821' from file "dcp.tdf" line 373, column 11 --- Equation name is '_LC2_C13', type is buried -_LC2_C13 = LCELL( _EQ682); - _EQ682 = _LC8_C13 - # !_LC3_C23 & _LC5_C13; - --- Node name is '|dcp:DECODE|:824' from file "dcp.tdf" line 373, column 11 --- Equation name is '_LC1_C13', type is buried -_LC1_C13 = LCELL( _EQ683); - _EQ683 = !_LC3_C23 & _LC8_C12 - # _EC1_C & !_LC1_E21 & _LC3_C23; - --- Node name is '|dcp:DECODE|:827' from file "dcp.tdf" line 373, column 11 --- Equation name is '_LC3_C28', type is buried -_LC3_C28 = LCELL( _EQ684); - _EQ684 = _LC2_C28 & !_LC3_C23 - # _EC10_C & !_LC1_E21 & _LC3_C23; - --- Node name is '|dcp:DECODE|:830' from file "dcp.tdf" line 373, column 11 --- Equation name is '_LC3_C32', type is buried -_LC3_C32 = LCELL( _EQ685); - _EQ685 = !_LC3_C23 & _LC5_C31 - # _EC8_C & !_LC1_E21 & _LC3_C23; - --- Node name is '|dcp:DECODE|:845' from file "dcp.tdf" line 375, column 11 --- Equation name is '_LC2_C7', type is buried -_LC2_C7 = LCELL( _EQ686); - _EQ686 = _LC1_C7 & !_LC3_C23 - # _LC3_C23 & _LC5_C22; - --- Node name is '|dcp:DECODE|:848' from file "dcp.tdf" line 375, column 11 --- Equation name is '_LC3_C7', type is buried -_LC3_C7 = LCELL( _EQ687); - _EQ687 = !_LC3_C23 & _LC4_C7 - # _LC3_C23 & _LC6_C22; - --- Node name is '|dcp:DECODE|:850' from file "dcp.tdf" line 375, column 11 --- Equation name is '_LC1_C10', type is buried -_LC1_C10 = LCELL( _EQ688); - _EQ688 = _LC1_C35 & !_LC3_C23 - # _LC1_E21 & _LC3_C23 - # _EC5_C & _LC3_C23; - --- Node name is '|dcp:DECODE|:853' from file "dcp.tdf" line 375, column 11 --- Equation name is '_LC1_C11', type is buried -_LC1_C11 = LCELL( _EQ689); - _EQ689 = !_LC3_C23 & _LC8_C11 - # _LC3_C23 & /wr; - --- Node name is '|dcp:DECODE|:856' from file "dcp.tdf" line 375, column 11 --- Equation name is '_LC6_C32', type is buried -_LC6_C32 = LCELL( _EQ690); - _EQ690 = _LC2_C27 & !_LC3_C23 - # _LC3_C23 & _LC4_C32; - --- Node name is '|dcp:DECODE|:859' from file "dcp.tdf" line 375, column 11 --- Equation name is '_LC2_C16', type is buried -_LC2_C16 = LCELL( _EQ691); - _EQ691 = !_LC3_C23 & _LC3_C27 - # _LC3_C23 & _LC4_C16; - --- Node name is '|dcp:DECODE|:862' from file "dcp.tdf" line 375, column 11 --- Equation name is '_LC1_C30', type is buried -_LC1_C30 = LCELL( _EQ692); - _EQ692 = _LC3_C23 & _LC4_C30; - --- Node name is '|dcp:DECODE|~986~1' from file "dcp.tdf" line 446, column 50 --- Equation name is '_LC5_A34', type is buried --- synthesized logic cell -_LC5_A34 = LCELL( _EQ693); - _EQ693 = _LC3_E28 & _LC3_F16 & _LC7_F1; - --- Node name is '|dcp:DECODE|:986' from file "dcp.tdf" line 446, column 50 --- Equation name is '_LC5_A28', type is buried -_LC5_A28 = LCELL( _EQ694); - _EQ694 = !_LC2_C21 & _LC5_A34 & !_LC6_A28; - --- Node name is '|dcp:DECODE|:987' from file "dcp.tdf" line 447, column 22 --- Equation name is '_LC2_A28', type is buried -!_LC2_A28 = _LC2_A28~NOT; -_LC2_A28~NOT = LCELL( _EQ695); - _EQ695 = !/mr - # !/io; - --- Node name is '|dcp:DECODE|~994~1' from file "dcp.tdf" line 456, column 38 --- Equation name is '_LC7_C1', type is buried --- synthesized logic cell -_LC7_C1 = LCELL( _EQ696); - _EQ696 = !_LC4_A28 & !/wr; - --- Node name is '|dcp:DECODE|:1004' from file "dcp.tdf" line 469, column 43 --- Equation name is '_LC4_F32', type is buried -_LC4_F32 = LCELL( _EQ697); - _EQ697 = !_LC3_F35 & !_LC7_F1 & !_LC8_C21 - # !_LC3_F32 & !_LC3_F35 & _LC7_F1 & _LC8_C21; - --- Node name is '|dcp:DECODE|:1012' from file "dcp.tdf" line 470, column 44 --- Equation name is '_LC5_F32', type is buried -_LC5_F32 = LCELL( _EQ698); - _EQ698 = !_LC3_F35 & _LC7_F1 & !_LC8_C21 - # !_LC3_F32 & !_LC3_F35 & !_LC7_F1 & _LC8_C21; - --- Node name is '|dcp:DECODE|~1024~1' from file "dcp.tdf" line 518, column 46 --- Equation name is '_LC5_C12', type is buried --- synthesized logic cell -_LC5_C12 = LCELL( _EQ699); - _EQ699 = _LC4_A28 & _LC8_C22 & /rd - # _LC4_A28 & !_LC8_C22 & !/rd; - --- Node name is '|dcp:DECODE|:1028' from file "dcp.tdf" line 522, column 26 --- Equation name is '_LC3_C14', type is buried -!_LC3_C14 = _LC3_C14~NOT; -_LC3_C14~NOT = LCELL( _EQ700); - _EQ700 = !_EC1_C & _EC10_C & _EC12_C; - --- Node name is '|dcp:DECODE|:1030' from file "dcp.tdf" line 525, column 25 --- Equation name is '_LC6_C14', type is buried -_LC6_C14 = LCELL( _EQ701); - _EQ701 = !_EC1_C & _EC10_C & _EC12_C & _LC5_C30; - --- Node name is '|dcp:DECODE|~1036~1' from file "dcp.tdf" line 526, column 26 --- Equation name is '_LC7_C14', type is buried --- synthesized logic cell -_LC7_C14 = LCELL( _EQ702); - _EQ702 = !_EC4_C & !_EC13_C & !_LC1_C14; - --- Node name is '|dcp:DECODE|:1037' from file "dcp.tdf" line 527, column 25 --- Equation name is '_LC7_C4', type is buried -_LC7_C4 = LCELL( _EQ703); - _EQ703 = _LC6_C4 & /reset; - --- Node name is '|dcp:DECODE|:1042' from file "dcp.tdf" line 549, column 27 --- Equation name is '_LC7_D23', type is buried -!_LC7_D23 = _LC7_D23~NOT; -_LC7_D23~NOT = LCELL( _EQ704); - _EQ704 = !_LC7_D27 - # !_LC8_D23; - --- Node name is '|dcp:DECODE|:1044' from file "dcp.tdf" line 549, column 27 --- Equation name is '_LC3_D27', type is buried -!_LC3_D27 = _LC3_D27~NOT; -_LC3_D27~NOT = LCELL( _EQ705); - _EQ705 = !_LC7_D27 - # !_LC1_D23; - --- Node name is '|dcp:DECODE|:1046' from file "dcp.tdf" line 550, column 3 --- Equation name is '_LC3_D6', type is buried -!_LC3_D6 = _LC3_D6~NOT; -_LC3_D6~NOT = LCELL( _EQ706); - _EQ706 = !_LC2_D35 & !_LC7_D27; - --- Node name is '|dcp:DECODE|:1054' from file "dcp.tdf" line 550, column 36 --- Equation name is '_LC4_D27_CARRY', type is buried -_LC4_D27_CARRY = CARRY( _EQ707); - _EQ707 = _LC1_D19 - # _LC3_D23; - --- Node name is '|dcp:DECODE|:1059' from file "dcp.tdf" line 550, column 36 --- Equation name is '_LC5_D27_CARRY', type is buried --- |dcp:DECODE|:1059 is in Clearable Counter Mode -_LC5_D27_CARRY = CARRY( _EQ708); - _EQ708 = _LC5_D27 - # _LC4_D27_CARRY; - --- Node name is '|dcp:DECODE|:1069' from file "dcp.tdf" line 550, column 27 --- Equation name is '_LC4_D19', type is buried -!_LC4_D19 = _LC4_D19~NOT; -_LC4_D19~NOT = LCELL( _EQ709); - _EQ709 = _LC7_D27 - # _LC2_D35 - # !_LC1_D19 & _LC3_D23 - # _LC1_D19 & !_LC3_D23; - --- Node name is '|dcp:DECODE|:1075' from file "dcp.tdf" line 550, column 27 --- Equation name is '_LC6_D27_CARRY', type is buried -!_LC6_D27_CARRY = _LC6_D27_CARRY~NOT; -_LC6_D27_CARRY~NOT = CARRY( _EQ710); - _EQ710 = _LC5_D27_CARRY & !_LC8_D27 - # !_LC5_D27_CARRY & _LC8_D27 - # _LC3_D6; - --- Node name is '|dcp:DECODE|:1076' from file "dcp.tdf" line 550, column 27 --- Equation name is '_LC7_D27_CARRY', type is buried --- |dcp:DECODE|:1076 is in Up/Down Counter Mode -!_LC7_D27_CARRY = _LC7_D27_CARRY~NOT; -_LC7_D27_CARRY~NOT = CARRY( _EQ711); - _EQ711 = !_LC6_D27_CARRY & !_LC7_D27 - # !_LC3_D29 & !_LC6_D27_CARRY; - --- Node name is '|dcp:DECODE|:1211' from file "dcp.tdf" line 608, column 18 --- Equation name is '_LC7_C23', type is buried -_LC7_C23 = LCELL( _EQ712); - _EQ712 = _LC3_E28 & _LC7_F1; - --- Node name is '|dcp:DECODE|:1220' from file "dcp.tdf" line 624, column 23 --- Equation name is '_LC2_D19', type is buried -_LC2_D19 = LCELL( _EQ713); - _EQ713 = _LC3_D19 & _LC4_A28; - --- Node name is '|dcp:DECODE|:1264' from file "dcp.tdf" line 641, column 20 --- Equation name is '_LC3_D21', type is buried -!_LC3_D21 = _LC3_D21~NOT; -_LC3_D21~NOT = LCELL( _EQ714); - _EQ714 = _LC1_D34 & !_LC3_D20 & _LC4_D34 & !_LC5_D34; - --- Node name is '|dcp:DECODE|:1307' from file "dcp.tdf" line 667, column 22 --- Equation name is '_LC7_D12', type is buried -_LC7_D12 = LCELL( _EQ715); - _EQ715 = !_LC2_D12 & /reset; - --- Node name is '|dcp:DECODE|:1309' from file "dcp.tdf" line 669, column 25 --- Equation name is '_LC6_D14', type is buried -_LC6_D14 = LCELL( _EQ716); - _EQ716 = !_LC5_D14 & /reset; - --- Node name is '|dcp:DECODE|:1310' from file "dcp.tdf" line 670, column 25 --- Equation name is '_LC7_D13', type is buried -_LC7_D13 = LCELL( _EQ717); - _EQ717 = _LC1_D12 & /reset; - --- Node name is '|dcp:DECODE|:1311' from file "dcp.tdf" line 670, column 16 --- Equation name is '_LC7_D14', type is buried -_LC7_D14 = LCELL( _EQ718); - _EQ718 = !_LC5_D14 & /reset - # _LC1_D12 & /reset; - --- Node name is '|dcp:DECODE|~1539~1' from file "dcp.tdf" line 722, column 46 --- Equation name is '_LC5_C32', type is buried --- synthesized logic cell -_LC5_C32 = LCELL( _EQ719); - _EQ719 = _LC1_D34 & _LC4_D34; - --- Node name is '|dcp:DECODE|:1630' from file "dcp.tdf" line 548, column 26 --- Equation name is '_LC5_D35', type is buried -!_LC5_D35 = _LC5_D35~NOT; -_LC5_D35~NOT = LCELL( _EQ720); - _EQ720 = !_LC1_D19 & !_LC3_D23 & !_LC5_D27 & !_LC8_D27; - --- Node name is '|dcp:DECODE|~1642~1' from file "dcp.tdf" line 539, column 55 --- Equation name is '_LC8_C34', type is buried --- synthesized logic cell -_LC8_C34 = LCELL( _EQ721); - _EQ721 = dos & _LC2_C22 & _LC7_C22; - --- Node name is '|kbd:KEYS|KA8' from file "kbd.tdf" line 129, column 27 --- Equation name is '_LC2_B10', type is buried -_LC2_B10 = LCELL( _EQ722); - _EQ722 = !_LC1_B10 - # _LC4_B10 & _LC4_E23 - # _LC3_B10 & !_LC4_B10; - --- Node name is '|kbd:KEYS|KA9' from file "kbd.tdf" line 129, column 27 --- Equation name is '_LC7_B10', type is buried -_LC7_B10 = LCELL( _EQ723); - _EQ723 = !_LC1_B10 - # _LC2_E32 & _LC4_B10 - # !_LC4_B10 & _LC8_B10; - --- Node name is '|kbd:KEYS|KA10' from file "kbd.tdf" line 129, column 27 --- Equation name is '_LC6_B10', type is buried -_LC6_B10 = LCELL( _EQ724); - _EQ724 = !_LC1_B10 & _LC5_B5 - # _LC1_B10 & _LC4_B10 & _LC7_E24; - --- Node name is '|kbd:KEYS|KA11' from file "kbd.tdf" line 129, column 27 --- Equation name is '_LC5_B10', type is buried -_LC5_B10 = LCELL( _EQ725); - _EQ725 = _LC1_B5 & !_LC1_B10 - # _LC1_B10 & _LC4_B10 & _LC8_E24; - --- Node name is '|kbd:KEYS|KA12' from file "kbd.tdf" line 129, column 27 --- Equation name is '_LC8_B2', type is buried -_LC8_B2 = LCELL( _EQ726); - _EQ726 = !_LC1_B10 & _LC6_B5 - # _LC1_B10 & _LC4_B10 & _LC5_E24; - --- Node name is '|kbd:KEYS|KA13' from file "kbd.tdf" line 129, column 27 --- Equation name is '_LC2_B14', type is buried -_LC2_B14 = LCELL( _EQ727); - _EQ727 = !_LC1_B10 - # _LC1_F29 & _LC4_B10; - --- Node name is '|kbd:KEYS|KA14' from file "kbd.tdf" line 129, column 27 --- Equation name is '_LC4_B14', type is buried -_LC4_B14 = LCELL( _EQ728); - _EQ728 = _LC1_B10 & !_LC4_B10 - # _LC1_B10 & _LC2_E25; - --- Node name is '|kbd:KEYS|KA15' from file "kbd.tdf" line 129, column 27 --- Equation name is '_LC5_B14', type is buried -_LC5_B14 = LCELL( _EQ729); - _EQ729 = !_LC1_B10 - # _LC3_E25 - # !_LC4_B10; - --- Node name is '|kbd:KEYS|KB_ALT_X' from file "kbd.tdf" line 93, column 13 --- Equation name is '_LC5_E34', type is buried -_LC5_E34 = LCELL( _EQ730); - _EQ730 = !_LC2_E32 & _LC4_E23 & _LC5_E24 & !_LC7_E24; - --- Node name is '|kbd:KEYS|KB_CTRL_X' from file "kbd.tdf" line 92, column 14 --- Equation name is '_LC2_E20', type is buried -_LC2_E20 = LCELL( _EQ731); - _EQ731 = !_LC2_E32 & !_LC4_E23 & _LC5_E24 & _LC7_E24; - --- Node name is '|kbd:KEYS|KB_CT0' from file "kbd.tdf" line 35, column 7 --- Equation name is '_LC7_A27', type is buried -!_LC7_A27 = _LC7_A27~NOT; -_LC7_A27~NOT = DFFE( _EQ732, _LC5_A30, _LC8_A27, VCC, VCC); - _EQ732 = _LC7_A27 - # !_LC1_A27 & !_LC6_A27; - --- Node name is '|kbd:KEYS|KB_CT1' from file "kbd.tdf" line 35, column 7 --- Equation name is '_LC6_A27', type is buried -!_LC6_A27 = _LC6_A27~NOT; -_LC6_A27~NOT = DFFE( _EQ733, _LC5_A30, _LC8_A27, VCC, VCC); - _EQ733 = !_LC1_A27 & !_LC6_A27 - # !_LC6_A27 & _LC7_A27 - # _LC6_A27 & !_LC7_A27; - --- Node name is '|kbd:KEYS|KB_CT2' from file "kbd.tdf" line 35, column 7 --- Equation name is '_LC1_A27', type is buried -!_LC1_A27 = _LC1_A27~NOT; -_LC1_A27~NOT = DFFE( _EQ734, _LC5_A30, _LC8_A27, VCC, VCC); - _EQ734 = !_LC1_A27 - # !_LC6_A27 & !_LC7_A27; - --- Node name is '|kbd:KEYS|kbd0' from file "kbd.tdf" line 58, column 5 --- Equation name is '_LC3_B12', type is buried -!_LC3_B12 = _LC3_B12~NOT; -_LC3_B12~NOT = DFFE( _EQ735, GLOBAL( TG42), _LC5_B12, VCC, VCC); - _EQ735 = !_LC3_B12 - # !_EC1_B & !_LC6_E18; - --- Node name is '|kbd:KEYS|KB_D1' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC4_E23', type is buried -_LC4_E23 = DFFE( _LC2_E32, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|kbd1' from file "kbd.tdf" line 58, column 5 --- Equation name is '_LC1_B12', type is buried -!_LC1_B12 = _LC1_B12~NOT; -_LC1_B12~NOT = DFFE( _EQ736, GLOBAL( TG42), _LC5_B12, VCC, VCC); - _EQ736 = !_LC1_B12 - # !_EC14_B & !_LC6_E18; - --- Node name is '|kbd:KEYS|KB_D2' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC2_E32', type is buried -_LC2_E32 = DFFE( _LC7_E24, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|kbd2' from file "kbd.tdf" line 58, column 5 --- Equation name is '_LC8_B12', type is buried -!_LC8_B12 = _LC8_B12~NOT; -_LC8_B12~NOT = DFFE( _EQ737, GLOBAL( TG42), _LC5_B12, VCC, VCC); - _EQ737 = !_LC8_B12 - # !_EC5_B & !_LC6_E18; - --- Node name is '|kbd:KEYS|KB_D3' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC7_E24', type is buried -_LC7_E24 = DFFE( _LC8_E24, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|kbd3' from file "kbd.tdf" line 58, column 5 --- Equation name is '_LC4_B12', type is buried -!_LC4_B12 = _LC4_B12~NOT; -_LC4_B12~NOT = DFFE( _EQ738, GLOBAL( TG42), _LC5_B12, VCC, VCC); - _EQ738 = !_LC4_B12 - # !_EC13_B & !_LC6_E18; - --- Node name is '|kbd:KEYS|KB_D4' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC8_E24', type is buried -_LC8_E24 = DFFE( _LC5_E24, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|kbd4' from file "kbd.tdf" line 58, column 5 --- Equation name is '_LC2_B12', type is buried -!_LC2_B12 = _LC2_B12~NOT; -_LC2_B12~NOT = DFFE( _EQ739, GLOBAL( TG42), _LC5_B12, VCC, VCC); - _EQ739 = !_LC2_B12 - # !_EC2_B & !_LC6_E18; - --- Node name is '|kbd:KEYS|KB_D5' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC5_E24', type is buried -_LC5_E24 = DFFE( _LC1_F29, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|kbd5' from file "kbd.tdf" line 58, column 5 --- Equation name is '_LC7_B12', type is buried -!_LC7_B12 = _LC7_B12~NOT; -_LC7_B12~NOT = DFFE( _EQ740, GLOBAL( TG42), _LC5_B12, VCC, VCC); - _EQ740 = !_LC7_B12 - # !_EC10_B & !_LC6_E18; - --- Node name is '|kbd:KEYS|KB_D6' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC1_F29', type is buried -_LC1_F29 = DFFE( _LC2_E25, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|KB_D7' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC2_E25', type is buried -_LC2_E25 = DFFE( _LC3_E25, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|KB_D8' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC3_E25', type is buried -_LC3_E25 = DFFE( _LC4_E25, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|KB_D9' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC4_E25', type is buried -_LC4_E25 = DFFE( _LC5_E25, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|KB_D10' from file "kbd.tdf" line 36, column 6 --- Equation name is '_LC5_E25', type is buried -_LC5_E25 = DFFE( kbd_dd, _LC1_E25, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|KB_EXT' from file "kbd.tdf" line 39, column 2 --- Equation name is '_LC7_E22', type is buried -_LC7_E22 = DFFE( _EQ741, _LC4_E20, VCC, VCC, VCC); - _EQ741 = _LC3_E25 & !_LC5_E24 & _LC6_E24 & _LC8_E22; - --- Node name is '|kbd:KEYS|KB_EXT~1' from file "kbd.tdf" line 39, column 2 --- Equation name is '_LC5_E22', type is buried --- synthesized logic cell -!_LC5_E22 = _LC5_E22~NOT; -_LC5_E22~NOT = LCELL(!_LC7_E22); - --- Node name is '|kbd:KEYS|KB_MA0' from file "kbd.tdf" line 53, column 7 --- Equation name is '_LC8_E9', type is buried -_LC8_E9 = DFFE(!_LC8_E9, GLOBAL( TG42), !_LC3_B5, VCC, VCC); - --- Node name is '|kbd:KEYS|KB_MA1' from file "kbd.tdf" line 53, column 7 --- Equation name is '_LC4_E18', type is buried -_LC4_E18 = DFFE( _EQ742, GLOBAL( TG42), !_LC3_B5, VCC, VCC); - _EQ742 = !_LC4_E18 & _LC8_E9 - # _LC4_E18 & !_LC8_E9; - --- Node name is '|kbd:KEYS|KB_MA2' from file "kbd.tdf" line 53, column 7 --- Equation name is '_LC5_E18', type is buried -_LC5_E18 = DFFE( _EQ743, GLOBAL( TG42), !_LC3_B5, VCC, VCC); - _EQ743 = _LC5_E18 & !_LC8_E9 - # !_LC4_E18 & _LC5_E18 - # _LC4_E18 & !_LC5_E18 & _LC8_E9; - --- Node name is '|kbd:KEYS|KB_MXA' from file "kbd.tdf" line 136, column 11 --- Equation name is '_LC6_E18', type is buried -_LC6_E18 = DFFE( _EQ744, GLOBAL( TG42), VCC, VCC, VCC); - _EQ744 = _LC4_E18 & _LC7_E18 - # _LC4_E18 & _LC8_E18 - # _LC3_E18 & !_LC4_E18; - --- Node name is '|kbd:KEYS|KB_OFF' from file "kbd.tdf" line 37, column 2 --- Equation name is '_LC1_E34', type is buried -_LC1_E34 = DFFE( _EQ745, _LC5_E20, VCC, VCC, !_LC5_E22); - _EQ745 = _LC5_E24 & _LC5_E32 & _LC6_E34; - --- Node name is '|kbd:KEYS|KB_SH_X' from file "kbd.tdf" line 94, column 45 --- Equation name is '_LC2_E24', type is buried -_LC2_E24 = LCELL( _EQ746C); - _EQ746C = _EQ746 & CASCADE( _EQ747C); - _EQ746 = _LC4_E24; - --- Node name is '|kbd:KEYS|KB_XXX' from file "kbd.tdf" line 96, column 12 --- Equation name is '_LC2_E34', type is buried -_LC2_E34 = LCELL( _EQ748); - _EQ748 = !_LC1_F29 & !_LC2_E25 & !_LC3_E25 & !_LC8_E24; - --- Node name is '|kbd:KEYS|K_CLK' from file "kbd.tdf" line 116, column 10 --- Equation name is '_LC8_B3', type is buried -_LC8_B3 = DFFE( _LC2_B3, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|KDCA0' from file "kbd.tdf" line 55, column 6 --- Equation name is '_LC5_B5', type is buried -_LC5_B5 = LCELL( _EQ749); - _EQ749 = _LC2_B5 & _LC3_B5 - # !_LC3_B5 & _LC8_E9; - --- Node name is '|kbd:KEYS|KDCA1' from file "kbd.tdf" line 55, column 6 --- Equation name is '_LC1_B5', type is buried -_LC1_B5 = LCELL( _EQ750); - _EQ750 = _LC3_B5 & _LC4_B5 - # !_LC3_B5 & _LC4_E18; - --- Node name is '|kbd:KEYS|KDCA2' from file "kbd.tdf" line 55, column 6 --- Equation name is '_LC6_B5', type is buried -_LC6_B5 = LCELL( _EQ751); - _EQ751 = _LC3_B5 & _LC7_B5 - # !_LC3_B5 & _LC5_E18; - --- Node name is '|kbd:KEYS|KDD3' from file "kbd.tdf" line 57, column 5 --- Equation name is '_LC2_B5', type is buried -_LC2_B5 = DFFE( _EC13_B, _LC4_B3, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|KDD4' from file "kbd.tdf" line 57, column 5 --- Equation name is '_LC4_B5', type is buried -_LC4_B5 = DFFE( _EC2_B, _LC4_B3, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|KDD5' from file "kbd.tdf" line 57, column 5 --- Equation name is '_LC7_B5', type is buried -_LC7_B5 = DFFE( _EC10_B, _LC4_B3, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|KDD6' from file "kbd.tdf" line 57, column 5 --- Equation name is '_LC3_B10', type is buried -!_LC3_B10 = _LC3_B10~NOT; -_LC3_B10~NOT = DFFE(!_EC4_B, _LC4_B3, !_LC1_A27, VCC, VCC); - --- Node name is '|kbd:KEYS|KDD7' from file "kbd.tdf" line 57, column 5 --- Equation name is '_LC8_B10', type is buried -!_LC8_B10 = _LC8_B10~NOT; -_LC8_B10~NOT = DFFE(!_EC12_B, _LC4_B3, !_LC1_A27, VCC, VCC); - --- Node name is '|kbd:KEYS|KDXX0' from file "kbd.tdf" line 61, column 6 --- Equation name is '_LC1_B17', type is buried -_LC1_B17 = DFFE( _EQ752, _LC4_B3, VCC, VCC, VCC); - _EQ752 = _EC5_B - # _EC14_B - # _EC1_B; - --- Node name is '|kbd:KEYS|KDXX1' from file "kbd.tdf" line 61, column 6 --- Equation name is '_LC7_B17', type is buried -_LC7_B17 = DFFE( _EQ753, _LC4_B3, VCC, VCC, VCC); - _EQ753 = _EC5_B - # _EC14_B - # !_EC1_B; - --- Node name is '|kbd:KEYS|KDXX2' from file "kbd.tdf" line 61, column 6 --- Equation name is '_LC8_B17', type is buried -_LC8_B17 = DFFE( _EQ754, _LC4_B3, VCC, VCC, VCC); - _EQ754 = _EC5_B - # !_EC14_B - # _EC1_B; - --- Node name is '|kbd:KEYS|KDXX3' from file "kbd.tdf" line 61, column 6 --- Equation name is '_LC4_B17', type is buried -_LC4_B17 = DFFE( _EQ755, _LC4_B3, VCC, VCC, VCC); - _EQ755 = !_EC14_B - # !_EC1_B - # _EC5_B; - --- Node name is '|kbd:KEYS|KDXX4' from file "kbd.tdf" line 61, column 6 --- Equation name is '_LC2_B17', type is buried -_LC2_B17 = DFFE( _EQ756, _LC4_B3, VCC, VCC, VCC); - _EQ756 = _EC14_B - # _EC1_B - # !_EC5_B; - --- Node name is '|kbd:KEYS|KDXX5' from file "kbd.tdf" line 61, column 6 --- Equation name is '_LC3_B17', type is buried -_LC3_B17 = DFFE( _EQ757, _LC4_B3, VCC, VCC, VCC); - _EQ757 = !_EC5_B - # _EC14_B - # !_EC1_B; - --- Node name is '|kbd:KEYS|KDX0' from file "kbd.tdf" line 60, column 5 --- Equation name is '_LC3_B13', type is buried -_LC3_B13 = DFFE( _EQ758, _LC7_B3, VCC, VCC, VCC); - _EQ758 = _EC1_B & _LC1_B17 - # !_LC1_B17 & _LC1_E34; - --- Node name is '|kbd:KEYS|KDX1' from file "kbd.tdf" line 60, column 5 --- Equation name is '_LC5_B17', type is buried -_LC5_B17 = DFFE( _EQ759, _LC7_B3, VCC, VCC, VCC); - _EQ759 = _EC14_B & _LC7_B17 - # _LC1_E34 & !_LC7_B17; - --- Node name is '|kbd:KEYS|KDX2' from file "kbd.tdf" line 60, column 5 --- Equation name is '_LC6_B17', type is buried -_LC6_B17 = DFFE( _EQ760, _LC7_B3, VCC, VCC, VCC); - _EQ760 = _EC5_B & _LC8_B17 - # _LC1_E34 & !_LC8_B17; - --- Node name is '|kbd:KEYS|KDX3' from file "kbd.tdf" line 60, column 5 --- Equation name is '_LC4_B13', type is buried -_LC4_B13 = DFFE( _EQ761, _LC7_B3, VCC, VCC, VCC); - _EQ761 = _EC13_B & _LC4_B17 - # _LC1_E34 & !_LC4_B17; - --- Node name is '|kbd:KEYS|KDX4' from file "kbd.tdf" line 60, column 5 --- Equation name is '_LC6_B13', type is buried -_LC6_B13 = DFFE( _EQ762, _LC7_B3, VCC, VCC, VCC); - _EQ762 = _EC2_B & _LC2_B17 - # _LC1_E34 & !_LC2_B17; - --- Node name is '|kbd:KEYS|KDX5' from file "kbd.tdf" line 60, column 5 --- Equation name is '_LC7_B13', type is buried -_LC7_B13 = DFFE( _EQ763, _LC7_B3, VCC, VCC, VCC); - _EQ763 = _EC10_B & _LC3_B17 - # _LC1_E34 & !_LC3_B17; - --- Node name is '|kbd:KEYS|RXA0' from file "kbd.tdf" line 49, column 5 --- Equation name is '_LC4_B3', type is buried -_LC4_B3 = DFFE( _EQ764, _LC8_B3, VCC, VCC, VCC); - _EQ764 = !_LC5_B3 & !_LC7_B3; - --- Node name is '|kbd:KEYS|RXA1' from file "kbd.tdf" line 49, column 5 --- Equation name is '_LC7_B3', type is buried -_LC7_B3 = DFFE( _EQ765, _LC8_B3, VCC, VCC, VCC); - _EQ765 = _LC4_B3 & !_LC5_B3; - --- Node name is '|kbd:KEYS|WR_KBD' from file "kbd.tdf" line 165, column 49 --- Equation name is '_LC3_B3', type is buried -!_LC3_B3 = _LC3_B3~NOT; -_LC3_B3~NOT = LCELL( _EQ766); - _EQ766 = _LC4_B1 & _LC4_B3 & _LC7_B3 & !_LC8_B3; - --- Node name is '|kbd:KEYS|:91' from file "kbd.tdf" line 48, column 2 --- Equation name is '_LC4_E34', type is buried -!_LC4_E34 = _LC4_E34~NOT; -_LC4_E34~NOT = DFFE( _EQ767, !_LC1_A27, !_LC4_E20, VCC, VCC); - _EQ767 = _LC1_F29 & _LC5_E34 & _LC7_E34 & _LC8_E34; - --- Node name is '|kbd:KEYS|:92' from file "kbd.tdf" line 41, column 2 --- Equation name is '_LC1_E20', type is buried -_LC1_E20 = DFFE( _EQ768, !_LC1_A27, VCC, VCC, VCC); - _EQ768 = _LC1_E20 & !_LC2_E34 - # _LC1_E20 & !_LC2_E20 - # !_LC1_E34 & _LC2_E20 & _LC2_E34; - --- Node name is '|kbd:KEYS|:93' from file "kbd.tdf" line 40, column 2 --- Equation name is '_LC3_E34', type is buried -_LC3_E34 = DFFE( _EQ769, !_LC1_A27, VCC, VCC, VCC); - _EQ769 = _LC3_E34 & !_LC5_E34 - # !_LC2_E34 & _LC3_E34 - # !_LC1_E34 & _LC2_E34 & _LC5_E34; - --- Node name is '|kbd:KEYS|:94' from file "kbd.tdf" line 42, column 2 --- Equation name is '_LC3_E24', type is buried -_LC3_E24 = DFFE( _EQ770, !_LC1_A27, VCC, VCC, VCC); - _EQ770 = !_LC2_E24 & _LC3_E24 - # !_LC1_E34 & _LC2_E24; - --- Node name is '|kbd:KEYS|:177' from file "kbd.tdf" line 67, column 9 --- Equation name is '_LC4_A27', type is buried -!_LC4_A27 = _LC4_A27~NOT; -_LC4_A27~NOT = DFFE( _EQ771, GLOBAL( TG42), _LC4_A34, VCC, VCC); - _EQ771 = _LC6_A27 - # _LC7_A27 - # _LC1_A27; - --- Node name is '|kbd:KEYS|:178' from file "kbd.tdf" line 71, column 16 --- Equation name is '_LC8_A27', type is buried -_LC8_A27 = DFFE( kbd_cc, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|:179' from file "kbd.tdf" line 78, column 15 --- Equation name is '_LC1_E25', type is buried -_LC1_E25 = DFFE(!kbd_cc, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|:180' from file "kbd.tdf" line 82, column 15 --- Equation name is '_LC5_E20', type is buried -_LC5_E20 = DFFE( _EQ772, GLOBAL( TG42), VCC, VCC, VCC); - _EQ772 = !_LC1_A27 & !_LC6_A27 & !_LC7_A27; - --- Node name is '|kbd:KEYS|:181' from file "kbd.tdf" line 85, column 15 --- Equation name is '_LC4_E20', type is buried -_LC4_E20 = DFFE( _EQ773, GLOBAL( TG42), VCC, VCC, VCC); - _EQ773 = !_LC1_A27 & !_LC6_A27 & _LC7_A27; - --- Node name is '|kbd:KEYS|:184' from file "kbd.tdf" line 94, column 13 --- Equation name is '_LC4_E24', type is buried -_LC4_E24 = LCELL( _EQ774); - _EQ774 = !_LC1_F29 & !_LC3_E25 & _LC5_E24 & !_LC7_E24; - --- Node name is '|kbd:KEYS|:185' from file "kbd.tdf" line 95, column 7 --- Equation name is '_LC1_E24', type is buried -_LC1_E24 = LCELL( _EQ747C); - _EQ747C = _EQ747; - _EQ747 = _LC2_E25 & !_LC2_E32 & _LC4_E23 & _LC8_E24 - # !_LC2_E25 & _LC2_E32 & !_LC4_E23 & !_LC8_E24; - --- Node name is '|kbd:KEYS|:187' from file "kbd.tdf" line 109, column 11 --- Equation name is '_LC6_E20', type is buried -!_LC6_E20 = _LC6_E20~NOT; -_LC6_E20~NOT = DFFE( _EQ775, !_LC1_A27, _LC3_E20, VCC, VCC); - _EQ775 = !_LC1_E34 & _LC2_E34 & _LC7_E20; - --- Node name is '|kbd:KEYS|:188' from file "kbd.tdf" line 109, column 27 --- Equation name is '_LC7_E20', type is buried -_LC7_E20 = LCELL( _EQ776); - _EQ776 = _LC2_E32 & _LC4_E23 & !_LC5_E24 & _LC7_E24; - --- Node name is '|kbd:KEYS|:191' from file "kbd.tdf" line 121, column 7 --- Equation name is '_LC5_B3', type is buried -_LC5_B3 = DFFE( _EQ777, GLOBAL( TG42), VCC, VCC, VCC); - _EQ777 = _LC1_A27 & !_LC4_B3 & !_LC7_B3 - # !_LC4_B3 & !_LC6_A27 & !_LC7_B3; - --- Node name is '|kbd:KEYS|:192' from file "kbd.tdf" line 126, column 42 --- Equation name is '_LC4_B10', type is buried -_LC4_B10 = LCELL( _EQ778); - _EQ778 = _LC3_B10 & _LC8_B10; - --- Node name is '|kbd:KEYS|:193' from file "kbd.tdf" line 126, column 8 --- Equation name is '_LC1_B10', type is buried -_LC1_B10 = DFFE( _EQ779, GLOBAL( TG42), VCC, VCC, VCC); - _EQ779 = KEY_IO & !_LC4_B3 & !_LC7_B3; - --- Node name is '|kbd:KEYS|:196' from file "kbd.tdf" line 141, column 6 --- Equation name is '_LC3_B5', type is buried -_LC3_B5 = DFFE( KEY_IO, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|:197' from file "kbd.tdf" line 165, column 21 --- Equation name is '_LC4_B1', type is buried -_LC4_B1 = DFFE( _EQ780, GLOBAL( TG42), VCC, VCC, VCC); - _EQ780 = !_LC1_A27 & _LC6_A27 & !_LC7_A27; - --- Node name is '|kbd:KEYS|:198' from file "kbd.tdf" line 172, column 14 --- Equation name is '_LC5_B12', type is buried -_LC5_B12 = DFFE( VCC, _LC5_E18, !KEY_IO, VCC, VCC); - --- Node name is '|kbd:KEYS|~267~1' from file "kbd.tdf" line 83, column 20 --- Equation name is '_LC6_E34', type is buried --- synthesized logic cell -_LC6_E34 = LCELL( _EQ781); - _EQ781 = _LC1_F29 & _LC2_E25 & _LC3_E25 & !_LC8_E24; - --- Node name is '|kbd:KEYS|~267~2' from file "kbd.tdf" line 83, column 20 --- Equation name is '_LC5_E32', type is buried --- synthesized logic cell -_LC5_E32 = LCELL( _EQ782); - _EQ782 = !_LC2_E32 & !_LC4_E23 & !_LC7_E24; - --- Node name is '|kbd:KEYS|~278~1' from file "kbd.tdf" line 86, column 20 --- Equation name is '_LC6_E24', type is buried --- synthesized logic cell -_LC6_E24 = LCELL( _EQ783); - _EQ783 = _LC1_F29 & _LC2_E25 & !_LC8_E24; - --- Node name is '|kbd:KEYS|~278~2' from file "kbd.tdf" line 86, column 20 --- Equation name is '_LC8_E22', type is buried --- synthesized logic cell -_LC8_E22 = LCELL( _EQ784); - _EQ784 = !_LC2_E32 & !_LC4_E23 & !_LC7_E24; - --- Node name is '|kbd:KEYS|~320~1' from file "kbd.tdf" line 113, column 76 --- Equation name is '_LC7_E34', type is buried --- synthesized logic cell -_LC7_E34 = LCELL( _EQ785); - _EQ785 = !_LC1_E34 & _LC2_E25 & !_LC3_E25; - --- Node name is '|kbd:KEYS|~320~2' from file "kbd.tdf" line 113, column 76 --- Equation name is '_LC8_E34', type is buried --- synthesized logic cell -_LC8_E34 = LCELL( _EQ786); - _EQ786 = _LC1_E20 & _LC3_E34 & !_LC8_E24; - --- Node name is '|kbd:KEYS|~540~1' from file "kbd.tdf" line 139, column 6 --- Equation name is '_LC7_E18', type is buried --- synthesized logic cell -_LC7_E18 = LCELL( _EQ787); - _EQ787 = A10 & !_LC5_E18 & !_LC8_E9 - # A14 & _LC5_E18 & !_LC8_E9; - --- Node name is '|kbd:KEYS|~540~2' from file "kbd.tdf" line 139, column 6 --- Equation name is '_LC8_E18', type is buried --- synthesized logic cell -_LC8_E18 = LCELL( _EQ788); - _EQ788 = a11 & !_LC5_E18 & _LC8_E9 - # A15 & _LC5_E18 & _LC8_E9; - --- Node name is '|kbd:KEYS|~540~3' from file "kbd.tdf" line 139, column 6 --- Equation name is '_LC2_E18', type is buried --- synthesized logic cell -!_LC2_E18 = _LC2_E18~NOT; -_LC2_E18~NOT = LCELL( _EQ789C); - _EQ789C = _EQ789; - _EQ789 = !a9 & !A13 - # !A13 & _LC5_E18 - # !a9 & !_LC5_E18 - # !_LC8_E9; - --- Node name is '|kbd:KEYS|~540~4' from file "kbd.tdf" line 139, column 6 --- Equation name is '_LC3_E18', type is buried --- synthesized logic cell -!_LC3_E18 = _LC3_E18~NOT; -_LC3_E18~NOT = LCELL( _EQ790C); - _EQ790C = _EQ790 & CASCADE( _EQ789C); - _EQ790 = !A8 & !A12 - # !A12 & _LC5_E18 - # !A8 & !_LC5_E18 - # _LC8_E9; - --- Node name is '|kbd:KEYS|:605' from file "kbd.tdf" line 85, column 28 --- Equation name is '_LC3_E20', type is buried -!_LC3_E20 = _LC3_E20~NOT; -_LC3_E20~NOT = LCELL( _EQ791); - _EQ791 = !_LC1_A27 & !_LC6_A27 & _LC7_A27; - --- Node name is '|MOUSE:MS|CT0' from file "mouse.tdf" line 20, column 4 --- Equation name is '_LC1_A7', type is buried -_LC1_A7 = DFFE( _EQ792, _LC5_A30, _LC1_A28, VCC, VCC); - _EQ792 = !_LC1_A7 & !_LC4_A7 - # !_LC1_A7 & !_LC3_A7 - # !_LC1_A7 & _LC2_A7; - --- Node name is '|MOUSE:MS|CT1' from file "mouse.tdf" line 20, column 4 --- Equation name is '_LC2_A7', type is buried -_LC2_A7 = DFFE( _EQ793, _LC5_A30, _LC1_A28, VCC, VCC); - _EQ793 = _LC1_A7 & !_LC2_A7 - # !_LC1_A7 & _LC2_A7; - --- Node name is '|MOUSE:MS|CT2' from file "mouse.tdf" line 20, column 4 --- Equation name is '_LC3_A7', type is buried -_LC3_A7 = DFFE( _EQ794, _LC5_A30, _LC1_A28, VCC, VCC); - _EQ794 = _LC1_A7 & _LC2_A7 & !_LC3_A7 - # !_LC1_A7 & _LC3_A7 & !_LC4_A7 - # !_LC1_A7 & _LC2_A7 & _LC3_A7 - # !_LC2_A7 & _LC3_A7 & !_LC4_A7 - # _LC1_A7 & !_LC2_A7 & _LC3_A7; - --- Node name is '|MOUSE:MS|CT3' from file "mouse.tdf" line 20, column 4 --- Equation name is '_LC4_A7', type is buried -_LC4_A7 = DFFE( _EQ795, _LC5_A30, _LC1_A28, VCC, VCC); - _EQ795 = !_LC3_A7 & _LC4_A7 - # _LC1_A7 & _LC2_A7 & _LC3_A7 & !_LC4_A7 - # !_LC1_A7 & _LC2_A7 & _LC4_A7 - # _LC1_A7 & !_LC2_A7 & _LC4_A7; - --- Node name is '|MOUSE:MS|MOUSE_IMP' from file "mouse.tdf" line 34, column 22 --- Equation name is '_LC1_A28', type is buried -_LC1_A28 = LCELL( _EQ796); - _EQ796 = _LC7_A28 & mouse_d - # !_LC7_A28 & !mouse_d; - --- Node name is '|MOUSE:MS|RGK0' from file "mouse.tdf" line 23, column 5 --- Equation name is '_LC3_B22', type is buried -_LC3_B22 = DFFE( _LC1_B23, _LC5_A30, VCC, VCC, _LC2_B11); - --- Node name is '|MOUSE:MS|RGK1' from file "mouse.tdf" line 23, column 5 --- Equation name is '_LC4_B26', type is buried -_LC4_B26 = DFFE( _LC6_B23, _LC5_A30, VCC, VCC, _LC2_B11); - --- Node name is '|MOUSE:MS|RGK2' from file "mouse.tdf" line 23, column 5 --- Equation name is '_LC8_B26', type is buried -_LC8_B26 = DFFE( _LC3_B23, _LC5_A30, VCC, VCC, _LC2_B11); - --- Node name is '|MOUSE:MS|RGK3' from file "mouse.tdf" line 23, column 5 --- Equation name is '_LC3_B26', type is buried -_LC3_B26 = DFFE( _LC4_B23, _LC5_A30, VCC, VCC, _LC2_B11); - --- Node name is '|MOUSE:MS|RGK4' from file "mouse.tdf" line 23, column 5 --- Equation name is '_LC3_B25', type is buried -_LC3_B25 = DFFE( _LC7_B23, _LC5_A30, VCC, VCC, _LC2_B11); - --- Node name is '|MOUSE:MS|RGK5' from file "mouse.tdf" line 23, column 5 --- Equation name is '_LC6_B22', type is buried -_LC6_B22 = DFFE( _LC5_B23, _LC5_A30, VCC, VCC, _LC2_B11); - --- Node name is '|MOUSE:MS|RG0~1' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC1_B14', type is buried --- synthesized logic cell -!_LC1_B14 = _LC1_B14~NOT; -_LC1_B14~NOT = LCELL(!_LC2_B23); - --- Node name is '|MOUSE:MS|RG0' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC2_B23', type is buried -_LC2_B23 = DFFE( _EQ797, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ797 = _LC1_B23 - # !_LC2_B23; - --- Node name is '|MOUSE:MS|RG1' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC1_B23', type is buried -_LC1_B23 = DFFE( _EQ798, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ798 = _LC6_B23 - # !_LC2_B23; - --- Node name is '|MOUSE:MS|RG2' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC6_B23', type is buried -_LC6_B23 = DFFE( _EQ799, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ799 = _LC3_B23 - # !_LC2_B23; - --- Node name is '|MOUSE:MS|RG3' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC3_B23', type is buried -_LC3_B23 = DFFE( _EQ800, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ800 = _LC4_B23 - # !_LC2_B23; - --- Node name is '|MOUSE:MS|RG4' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC4_B23', type is buried -_LC4_B23 = DFFE( _EQ801, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ801 = _LC7_B23 - # !_LC2_B23; - --- Node name is '|MOUSE:MS|RG5' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC7_B23', type is buried -_LC7_B23 = DFFE( _EQ802, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ802 = _LC5_B23 - # !_LC2_B23; - --- Node name is '|MOUSE:MS|RG6' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC5_B23', type is buried -_LC5_B23 = DFFE( _EQ803, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ803 = _LC2_B28 - # !_LC2_B23; - --- Node name is '|MOUSE:MS|RG7' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC2_B28', type is buried -_LC2_B28 = DFFE( _EQ804, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ804 = _LC4_B28 - # !_LC2_B23; - --- Node name is '|MOUSE:MS|RG8' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC4_B28', type is buried -_LC4_B28 = DFFE( _EQ805, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ805 = _LC6_B28 - # !_LC2_B23; - --- Node name is '|MOUSE:MS|RG9' from file "mouse.tdf" line 21, column 4 --- Equation name is '_LC6_B28', type is buried -_LC6_B28 = DFFE( _EQ806, _LC5_A30, VCC, VCC, _LC8_B28); - _EQ806 = !_LC2_B23 - # mouse_d; - --- Node name is '|MOUSE:MS|STATE0' from file "mouse.tdf" line 22, column 7 --- Equation name is '_LC3_B14', type is buried -_LC3_B14 = DFFE( _LC2_B28, _LC5_A30, VCC, VCC, !_LC1_B14); - --- Node name is '|MOUSE:MS|STATE1' from file "mouse.tdf" line 22, column 7 --- Equation name is '_LC6_B14', type is buried -_LC6_B14 = DFFE( _LC3_B14, _LC5_A30, VCC, VCC, !_LC1_B14); - --- Node name is '|MOUSE:MS|SUM_X0' from file "mouse.tdf" line 17, column 7 --- Equation name is '_LC8_B22', type is buried -_LC8_B22 = DFFE( _EQ807, _LC5_A30, VCC, VCC, _LC8_B14); - _EQ807 = _LC1_B23 & !_LC8_B22 - # !_LC1_B23 & _LC8_B22; - --- Node name is '|MOUSE:MS|SUM_X1' from file "mouse.tdf" line 17, column 7 --- Equation name is '_LC4_B25', type is buried -_LC4_B25 = DFFE( _LC2_B35, _LC5_A30, VCC, VCC, _LC8_B14); - --- Node name is '|MOUSE:MS|SUM_X2' from file "mouse.tdf" line 17, column 7 --- Equation name is '_LC7_B32', type is buried -_LC7_B32 = DFFE( _LC3_B35, _LC5_A30, VCC, VCC, _LC8_B14); - --- Node name is '|MOUSE:MS|SUM_X3' from file "mouse.tdf" line 17, column 7 --- Equation name is '_LC6_B24', type is buried -_LC6_B24 = DFFE( _LC4_B35, _LC5_A30, VCC, VCC, _LC8_B14); - --- Node name is '|MOUSE:MS|SUM_X4' from file "mouse.tdf" line 17, column 7 --- Equation name is '_LC6_B32', type is buried -_LC6_B32 = DFFE( _LC5_B35, _LC5_A30, VCC, VCC, _LC8_B14); - --- Node name is '|MOUSE:MS|SUM_X5' from file "mouse.tdf" line 17, column 7 --- Equation name is '_LC5_B24', type is buried -_LC5_B24 = DFFE( _LC6_B35, _LC5_A30, VCC, VCC, _LC8_B14); - --- Node name is '|MOUSE:MS|SUM_X6' from file "mouse.tdf" line 17, column 7 --- Equation name is '_LC2_B24', type is buried -_LC2_B24 = DFFE( _LC7_B35, _LC5_A30, VCC, VCC, _LC8_B14); - --- Node name is '|MOUSE:MS|SUM_X7' from file "mouse.tdf" line 17, column 7 --- Equation name is '_LC8_B35', type is buried -_LC8_B35 = DFFE( _EQ808, _LC5_A30, VCC, VCC, _LC8_B14); - _EQ808 = !_LC4_B26 & _LC7_B35_CARRY & !_LC8_B35 - # _LC4_B26 & _LC7_B35_CARRY & _LC8_B35 - # _LC4_B26 & !_LC7_B35_CARRY & !_LC8_B35 - # !_LC4_B26 & !_LC7_B35_CARRY & _LC8_B35; - --- Node name is '|MOUSE:MS|SUM_Y0' from file "mouse.tdf" line 18, column 7 --- Equation name is '_LC1_B26', type is buried -_LC1_B26 = DFFE( _EQ809, _LC5_A30, VCC, VCC, _LC7_B14); - _EQ809 = _LC1_B23 & !_LC1_B26 - # !_LC1_B23 & _LC1_B26; - --- Node name is '|MOUSE:MS|SUM_Y1' from file "mouse.tdf" line 18, column 7 --- Equation name is '_LC1_B28', type is buried -_LC1_B28 = DFFE( _LC2_B31, _LC5_A30, VCC, VCC, _LC7_B14); - --- Node name is '|MOUSE:MS|SUM_Y2' from file "mouse.tdf" line 18, column 7 --- Equation name is '_LC3_B32', type is buried -_LC3_B32 = DFFE( _LC3_B31, _LC5_A30, VCC, VCC, _LC7_B14); - --- Node name is '|MOUSE:MS|SUM_Y3' from file "mouse.tdf" line 18, column 7 --- Equation name is '_LC1_B22', type is buried -_LC1_B22 = DFFE( _LC4_B31, _LC5_A30, VCC, VCC, _LC7_B14); - --- Node name is '|MOUSE:MS|SUM_Y4' from file "mouse.tdf" line 18, column 7 --- Equation name is '_LC8_B32', type is buried -_LC8_B32 = DFFE( _LC5_B31, _LC5_A30, VCC, VCC, _LC7_B14); - --- Node name is '|MOUSE:MS|SUM_Y5' from file "mouse.tdf" line 18, column 7 --- Equation name is '_LC3_B28', type is buried -_LC3_B28 = DFFE( _LC6_B31, _LC5_A30, VCC, VCC, _LC7_B14); - --- Node name is '|MOUSE:MS|SUM_Y6' from file "mouse.tdf" line 18, column 7 --- Equation name is '_LC5_B28', type is buried -_LC5_B28 = DFFE( _LC7_B31, _LC5_A30, VCC, VCC, _LC7_B14); - --- Node name is '|MOUSE:MS|SUM_Y7' from file "mouse.tdf" line 18, column 7 --- Equation name is '_LC8_B31', type is buried -_LC8_B31 = DFFE( _EQ810, _LC5_A30, VCC, VCC, _LC7_B14); - _EQ810 = !_LC3_B26 & _LC7_B31_CARRY & !_LC8_B31 - # _LC3_B26 & _LC7_B31_CARRY & _LC8_B31 - # _LC3_B26 & !_LC7_B31_CARRY & !_LC8_B31 - # !_LC3_B26 & !_LC7_B31_CARRY & _LC8_B31; - --- Node name is '|MOUSE:MS|:111' from file "mouse.tdf" line 34, column 27 --- Equation name is '_LC7_A28', type is buried -_LC7_A28 = DFFE( mouse_d, _LC5_A30, VCC, VCC, VCC); - --- Node name is '|MOUSE:MS|:112' from file "mouse.tdf" line 61, column 16 --- Equation name is '_LC8_B14', type is buried -_LC8_B14 = LCELL( _EQ811); - _EQ811 = !_LC2_B23 & !_LC2_B28 & _LC3_B14 & !_LC6_B14; - --- Node name is '|MOUSE:MS|:113' from file "mouse.tdf" line 62, column 16 --- Equation name is '_LC7_B14', type is buried -_LC7_B14 = LCELL( _EQ812); - _EQ812 = !_LC2_B23 & !_LC2_B28 & !_LC3_B14 & _LC6_B14; - --- Node name is '|MOUSE:MS|:144' from file "mouse.tdf" line 45, column 19 --- Equation name is '_LC5_A7', type is buried -!_LC5_A7 = _LC5_A7~NOT; -_LC5_A7~NOT = LCELL( _EQ813); - _EQ813 = !_LC1_A7 & !_LC2_A7 & _LC3_A7 & !_LC4_A7; - --- Node name is '|MOUSE:MS|:147' from file "mouse.tdf" line 45, column 25 --- Equation name is '_LC8_B28', type is buried -_LC8_B28 = LCELL( _EQ814); - _EQ814 = !_LC2_B23 - # !_LC5_A7; - --- Node name is '|MOUSE:MS|:171' from file "mouse.tdf" line 55, column 19 --- Equation name is '_LC2_B11', type is buried -_LC2_B11 = LCELL( _EQ815); - _EQ815 = !_LC2_B23 & _LC2_B28; - --- Node name is '|MOUSE:MS|:172' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC1_B35_CARRY', type is buried -_LC1_B35_CARRY = CARRY( _EQ816); - _EQ816 = _LC1_B23 & _LC8_B22; - --- Node name is '|MOUSE:MS|:185' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC2_B35', type is buried -_LC2_B35 = LCELL( _EQ817); - _EQ817 = !_LC1_B35_CARRY & _LC4_B25 & !_LC6_B23 - # !_LC1_B35_CARRY & !_LC4_B25 & _LC6_B23 - # _LC1_B35_CARRY & _LC4_B25 & _LC6_B23 - # _LC1_B35_CARRY & !_LC4_B25 & !_LC6_B23; - --- Node name is '|MOUSE:MS|:188' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC2_B35_CARRY', type is buried -_LC2_B35_CARRY = CARRY( _EQ818); - _EQ818 = _LC1_B35_CARRY & _LC4_B25 - # _LC1_B35_CARRY & _LC6_B23 - # _LC4_B25 & _LC6_B23; - --- Node name is '|MOUSE:MS|:195' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC3_B35', type is buried -_LC3_B35 = LCELL( _EQ819); - _EQ819 = _LC2_B35_CARRY & _LC3_B23 & _LC7_B32 - # _LC2_B35_CARRY & !_LC3_B23 & !_LC7_B32 - # !_LC2_B35_CARRY & !_LC3_B23 & _LC7_B32 - # !_LC2_B35_CARRY & _LC3_B23 & !_LC7_B32; - --- Node name is '|MOUSE:MS|:198' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC3_B35_CARRY', type is buried -_LC3_B35_CARRY = CARRY( _EQ820); - _EQ820 = _LC2_B35_CARRY & _LC7_B32 - # _LC2_B35_CARRY & _LC3_B23 - # _LC3_B23 & _LC7_B32; - --- Node name is '|MOUSE:MS|:205' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC4_B35', type is buried -_LC4_B35 = LCELL( _EQ821); - _EQ821 = _LC3_B35_CARRY & _LC4_B23 & _LC6_B24 - # _LC3_B35_CARRY & !_LC4_B23 & !_LC6_B24 - # !_LC3_B35_CARRY & !_LC4_B23 & _LC6_B24 - # !_LC3_B35_CARRY & _LC4_B23 & !_LC6_B24; - --- Node name is '|MOUSE:MS|:208' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC4_B35_CARRY', type is buried -_LC4_B35_CARRY = CARRY( _EQ822); - _EQ822 = _LC3_B35_CARRY & _LC6_B24 - # _LC3_B35_CARRY & _LC4_B23 - # _LC4_B23 & _LC6_B24; - --- Node name is '|MOUSE:MS|:216' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC5_B35', type is buried -_LC5_B35 = LCELL( _EQ823); - _EQ823 = _LC4_B35_CARRY & _LC6_B32 & _LC7_B23 - # _LC4_B35_CARRY & !_LC6_B32 & !_LC7_B23 - # !_LC4_B35_CARRY & _LC6_B32 & !_LC7_B23 - # !_LC4_B35_CARRY & !_LC6_B32 & _LC7_B23; - --- Node name is '|MOUSE:MS|:219' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC5_B35_CARRY', type is buried -_LC5_B35_CARRY = CARRY( _EQ824); - _EQ824 = _LC4_B35_CARRY & _LC6_B32 - # _LC4_B35_CARRY & _LC7_B23 - # _LC6_B32 & _LC7_B23; - --- Node name is '|MOUSE:MS|:226' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC6_B35', type is buried -_LC6_B35 = LCELL( _EQ825); - _EQ825 = _LC5_B23 & _LC5_B24 & _LC5_B35_CARRY - # !_LC5_B23 & !_LC5_B24 & _LC5_B35_CARRY - # !_LC5_B23 & _LC5_B24 & !_LC5_B35_CARRY - # _LC5_B23 & !_LC5_B24 & !_LC5_B35_CARRY; - --- Node name is '|MOUSE:MS|:229' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC6_B35_CARRY', type is buried -_LC6_B35_CARRY = CARRY( _EQ826); - _EQ826 = _LC5_B24 & _LC5_B35_CARRY - # _LC5_B23 & _LC5_B35_CARRY - # _LC5_B23 & _LC5_B24; - --- Node name is '|MOUSE:MS|:236' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC7_B35', type is buried -_LC7_B35 = LCELL( _EQ827); - _EQ827 = _LC2_B24 & _LC3_B22 & _LC6_B35_CARRY - # !_LC2_B24 & !_LC3_B22 & _LC6_B35_CARRY - # _LC2_B24 & !_LC3_B22 & !_LC6_B35_CARRY - # !_LC2_B24 & _LC3_B22 & !_LC6_B35_CARRY; - --- Node name is '|MOUSE:MS|:239' from file "mouse.tdf" line 67, column 21 --- Equation name is '_LC7_B35_CARRY', type is buried -_LC7_B35_CARRY = CARRY( _EQ828); - _EQ828 = _LC2_B24 & _LC6_B35_CARRY - # _LC3_B22 & _LC6_B35_CARRY - # _LC2_B24 & _LC3_B22; - --- Node name is '|MOUSE:MS|:269' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC1_B31_CARRY', type is buried -_LC1_B31_CARRY = CARRY( _EQ829); - _EQ829 = _LC1_B23 & _LC1_B26; - --- Node name is '|MOUSE:MS|:282' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC2_B31', type is buried -_LC2_B31 = LCELL( _EQ830); - _EQ830 = _LC1_B28 & _LC1_B31_CARRY & _LC6_B23 - # !_LC1_B28 & _LC1_B31_CARRY & !_LC6_B23 - # _LC1_B28 & !_LC1_B31_CARRY & !_LC6_B23 - # !_LC1_B28 & !_LC1_B31_CARRY & _LC6_B23; - --- Node name is '|MOUSE:MS|:285' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC2_B31_CARRY', type is buried -_LC2_B31_CARRY = CARRY( _EQ831); - _EQ831 = _LC1_B28 & _LC1_B31_CARRY - # _LC1_B31_CARRY & _LC6_B23 - # _LC1_B28 & _LC6_B23; - --- Node name is '|MOUSE:MS|:292' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC3_B31', type is buried -_LC3_B31 = LCELL( _EQ832); - _EQ832 = _LC2_B31_CARRY & _LC3_B23 & _LC3_B32 - # _LC2_B31_CARRY & !_LC3_B23 & !_LC3_B32 - # !_LC2_B31_CARRY & !_LC3_B23 & _LC3_B32 - # !_LC2_B31_CARRY & _LC3_B23 & !_LC3_B32; - --- Node name is '|MOUSE:MS|:295' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC3_B31_CARRY', type is buried -_LC3_B31_CARRY = CARRY( _EQ833); - _EQ833 = _LC2_B31_CARRY & _LC3_B32 - # _LC2_B31_CARRY & _LC3_B23 - # _LC3_B23 & _LC3_B32; - --- Node name is '|MOUSE:MS|:302' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC4_B31', type is buried -_LC4_B31 = LCELL( _EQ834); - _EQ834 = _LC1_B22 & _LC3_B31_CARRY & _LC4_B23 - # !_LC1_B22 & _LC3_B31_CARRY & !_LC4_B23 - # _LC1_B22 & !_LC3_B31_CARRY & !_LC4_B23 - # !_LC1_B22 & !_LC3_B31_CARRY & _LC4_B23; - --- Node name is '|MOUSE:MS|:305' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC4_B31_CARRY', type is buried -_LC4_B31_CARRY = CARRY( _EQ835); - _EQ835 = _LC1_B22 & _LC3_B31_CARRY - # _LC3_B31_CARRY & _LC4_B23 - # _LC1_B22 & _LC4_B23; - --- Node name is '|MOUSE:MS|:313' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC5_B31', type is buried -_LC5_B31 = LCELL( _EQ836); - _EQ836 = _LC4_B31_CARRY & _LC7_B23 & _LC8_B32 - # _LC4_B31_CARRY & !_LC7_B23 & !_LC8_B32 - # !_LC4_B31_CARRY & !_LC7_B23 & _LC8_B32 - # !_LC4_B31_CARRY & _LC7_B23 & !_LC8_B32; - --- Node name is '|MOUSE:MS|:316' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC5_B31_CARRY', type is buried -_LC5_B31_CARRY = CARRY( _EQ837); - _EQ837 = _LC4_B31_CARRY & _LC8_B32 - # _LC4_B31_CARRY & _LC7_B23 - # _LC7_B23 & _LC8_B32; - --- Node name is '|MOUSE:MS|:323' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC6_B31', type is buried -_LC6_B31 = LCELL( _EQ838); - _EQ838 = _LC3_B28 & _LC5_B23 & _LC5_B31_CARRY - # !_LC3_B28 & !_LC5_B23 & _LC5_B31_CARRY - # _LC3_B28 & !_LC5_B23 & !_LC5_B31_CARRY - # !_LC3_B28 & _LC5_B23 & !_LC5_B31_CARRY; - --- Node name is '|MOUSE:MS|:326' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC6_B31_CARRY', type is buried -_LC6_B31_CARRY = CARRY( _EQ839); - _EQ839 = _LC3_B28 & _LC5_B31_CARRY - # _LC5_B23 & _LC5_B31_CARRY - # _LC3_B28 & _LC5_B23; - --- Node name is '|MOUSE:MS|:333' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC7_B31', type is buried -_LC7_B31 = LCELL( _EQ840); - _EQ840 = _LC5_B28 & _LC6_B31_CARRY & _LC8_B26 - # !_LC5_B28 & _LC6_B31_CARRY & !_LC8_B26 - # _LC5_B28 & !_LC6_B31_CARRY & !_LC8_B26 - # !_LC5_B28 & !_LC6_B31_CARRY & _LC8_B26; - --- Node name is '|MOUSE:MS|:336' from file "mouse.tdf" line 68, column 21 --- Equation name is '_LC7_B31_CARRY', type is buried -_LC7_B31_CARRY = CARRY( _EQ841); - _EQ841 = _LC5_B28 & _LC6_B31_CARRY - # _LC6_B31_CARRY & _LC8_B26 - # _LC5_B28 & _LC8_B26; - --- Node name is '|video2:SVIDEO|BORD' from file "video2.tdf" line 390, column 9 --- Equation name is '_LC3_B34', type is buried -_LC3_B34 = DFFE( _EQ842, _LC1_B21, VCC, VCC, VCC); - _EQ842 = _LC2_B4 & _LC4_A9 & _LC5_B19 & _LC7_B27; - --- Node name is '|video2:SVIDEO|BRVA0' from file "video2.tdf" line 148, column 6 --- Equation name is '_LC3_B29', type is buried -_LC3_B29 = DFFE( _EQ843, GLOBAL( TG42), VCC, VCC, VCC); - _EQ843 = !_LC1_B34 & _LC3_E28 & _LC7_B29 - # _LC1_B34 & _LC4_B29 - # !_LC3_E28 & _LC4_B29; - --- Node name is '|video2:SVIDEO|BRVA1' from file "video2.tdf" line 148, column 6 --- Equation name is '_LC5_B21', type is buried -_LC5_B21 = DFFE( _EQ844, GLOBAL( TG42), VCC, VCC, VCC); - _EQ844 = !_LC1_B34 & _LC3_E28 & _LC7_B21 - # _LC1_B34 & _LC6_B21 - # !_LC3_E28 & _LC6_B21; - --- Node name is '|video2:SVIDEO|BRVA2' from file "video2.tdf" line 148, column 6 --- Equation name is '_LC4_B33', type is buried -_LC4_B33 = DFFE( _EQ845, GLOBAL( TG42), VCC, VCC, VCC); - _EQ845 = !_LC1_B34 & _LC3_E28 & _LC6_B33 - # _LC1_B34 & _LC5_B33 - # !_LC3_E28 & _LC5_B33; - --- Node name is '|video2:SVIDEO|BRVA3' from file "video2.tdf" line 148, column 6 --- Equation name is '_LC6_B29', type is buried -_LC6_B29 = DFFE( _EQ846, GLOBAL( TG42), VCC, VCC, VCC); - _EQ846 = !_LC1_B34 & _LC3_E28 & _LC8_B29 - # _LC1_B34 & _LC5_B29 - # !_LC3_E28 & _LC5_B29; - --- Node name is '|video2:SVIDEO|BRVA4' from file "video2.tdf" line 148, column 6 --- Equation name is '_LC2_B29', type is buried -_LC2_B29 = DFFE( _EQ847, GLOBAL( TG42), VCC, VCC, VCC); - _EQ847 = _LC1_B34 & _LC7_B29; - --- Node name is '|video2:SVIDEO|BRVA5' from file "video2.tdf" line 148, column 6 --- Equation name is '_LC8_B21', type is buried -_LC8_B21 = DFFE( _EQ848, GLOBAL( TG42), VCC, VCC, VCC); - _EQ848 = _LC1_B34 & _LC7_B21; - --- Node name is '|video2:SVIDEO|BRVA6' from file "video2.tdf" line 148, column 6 --- Equation name is '_LC3_B33', type is buried -_LC3_B33 = DFFE( _EQ849, GLOBAL( TG42), VCC, VCC, VCC); - _EQ849 = _LC1_B34 & _LC6_B33; - --- Node name is '|video2:SVIDEO|BRVA7' from file "video2.tdf" line 148, column 6 --- Equation name is '_LC1_B29', type is buried -_LC1_B29 = DFFE( _EQ850, GLOBAL( TG42), VCC, VCC, VCC); - _EQ850 = _LC1_B34 & _LC8_B29; - --- Node name is '|video2:SVIDEO|DCOL0' from file "video2.tdf" line 149, column 6 --- Equation name is '_LC4_B29', type is buried -_LC4_B29 = DFFE( _EQ851, GLOBAL( TG42), !_LC6_B26, VCC, !_LC8_B33); - _EQ851 = BORDER0 & _LC7_B33 - # _LC4_B20 & !_LC7_B33; - --- Node name is '|video2:SVIDEO|DCOL1' from file "video2.tdf" line 149, column 6 --- Equation name is '_LC6_B21', type is buried -_LC6_B21 = DFFE( _EQ852, GLOBAL( TG42), !_LC6_B26, VCC, !_LC8_B33); - _EQ852 = BORDER1 & _LC7_B33 - # _LC2_F34 & !_LC7_B33; - --- Node name is '|video2:SVIDEO|DCOL2' from file "video2.tdf" line 149, column 6 --- Equation name is '_LC5_B33', type is buried -_LC5_B33 = DFFE( _EQ853, GLOBAL( TG42), !_LC6_B26, VCC, !_LC8_B33); - _EQ853 = BORDER2 & _LC7_B33 - # !_LC7_B33 & _LC8_B7; - --- Node name is '|video2:SVIDEO|DCOL3' from file "video2.tdf" line 149, column 6 --- Equation name is '_LC5_B29', type is buried -_LC5_B29 = DFFE( _EQ854, GLOBAL( TG42), !_LC6_B26, VCC, !_LC8_B33); - _EQ854 = _LC5_B8 & !_LC7_B33 - # BORDER0 & _LC7_B33; - --- Node name is '|video2:SVIDEO|DCOL4' from file "video2.tdf" line 149, column 6 --- Equation name is '_LC7_B29', type is buried -_LC7_B29 = DFFE( _EQ855, GLOBAL( TG42), !_LC6_B26, VCC, !_LC8_B33); - _EQ855 = _LC5_B16 & !_LC7_B33 - # BORDER1 & _LC7_B33; - --- Node name is '|video2:SVIDEO|DCOL5' from file "video2.tdf" line 149, column 6 --- Equation name is '_LC7_B21', type is buried -_LC7_B21 = DFFE( _EQ856, GLOBAL( TG42), !_LC6_B26, VCC, !_LC8_B33); - _EQ856 = _LC3_B7 & !_LC7_B33 - # BORDER2 & _LC7_B33; - --- Node name is '|video2:SVIDEO|DCOL6' from file "video2.tdf" line 149, column 6 --- Equation name is '_LC6_B33', type is buried -_LC6_B33 = DFFE( _EQ857, GLOBAL( TG42), !_LC6_B26, VCC, !_LC8_B33); - _EQ857 = _LC5_B4 & !_LC7_B33; - --- Node name is '|video2:SVIDEO|DCOL7' from file "video2.tdf" line 149, column 6 --- Equation name is '_LC8_B29', type is buried -_LC8_B29 = DFFE( _EQ858, GLOBAL( TG42), !_LC6_B26, VCC, !_LC8_B33); - _EQ858 = _LC4_B15 & !_LC7_B33; - --- Node name is '|video2:SVIDEO|DOUBLE' from file "video2.tdf" line 180, column 2 --- Equation name is '_LC6_F7', type is buried -_LC6_F7 = DFFE( _LC4_F11, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - --- Node name is '|video2:SVIDEO|D_PICX_0~1' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC3_B20', type is buried --- synthesized logic cell -!_LC3_B20 = _LC3_B20~NOT; -_LC3_B20~NOT = LCELL( _EQ859C); - _EQ859C = _EQ859; - _EQ859 = _LC3_F20 - # _LC1_B1 & !_LC7_B20 - # !_LC1_B1 & !_LC1_B20 - # !_LC1_B20 & !_LC7_B20; - --- Node name is '|video2:SVIDEO|D_PICX_0' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC4_B20', type is buried -!_LC4_B20 = _LC4_B20~NOT; -_LC4_B20~NOT = LCELL( _EQ860C); - _EQ860C = _EQ860 & CASCADE( _EQ859C); - _EQ860 = !_LC3_F20 - # _LC1_B1 & !_LC7_B15 - # !_LC1_B1 & !_LC8_B20 - # !_LC7_B15 & !_LC8_B20; - --- Node name is '|video2:SVIDEO|D_PICX_1~1' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC1_F34', type is buried --- synthesized logic cell -!_LC1_F34 = _LC1_F34~NOT; -_LC1_F34~NOT = LCELL( _EQ861C); - _EQ861C = _EQ861; - _EQ861 = _LC3_F20 - # _LC1_B1 & !_LC7_F34 - # !_LC1_B1 & !_LC3_F11 - # !_LC3_F11 & !_LC7_F34; - --- Node name is '|video2:SVIDEO|D_PICX_1' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC2_F34', type is buried -!_LC2_F34 = _LC2_F34~NOT; -_LC2_F34~NOT = LCELL( _EQ862C); - _EQ862C = _EQ862 & CASCADE( _EQ861C); - _EQ862 = !_LC3_F20 - # _LC1_B1 & !_LC4_F34 - # !_LC1_B1 & !_LC8_F34 - # !_LC4_F34 & !_LC8_F34; - --- Node name is '|video2:SVIDEO|D_PICX_2~1' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC7_B7', type is buried --- synthesized logic cell -!_LC7_B7 = _LC7_B7~NOT; -_LC7_B7~NOT = LCELL( _EQ863C); - _EQ863C = _EQ863; - _EQ863 = _LC3_F20 - # _LC1_B1 & !_LC5_B7 - # !_LC1_B1 & !_LC8_F8 - # !_LC5_B7 & !_LC8_F8; - --- Node name is '|video2:SVIDEO|D_PICX_2' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC8_B7', type is buried -!_LC8_B7 = _LC8_B7~NOT; -_LC8_B7~NOT = LCELL( _EQ864C); - _EQ864C = _EQ864 & CASCADE( _EQ863C); - _EQ864 = !_LC3_F20 - # _LC1_B1 & !_LC3_B16 - # !_LC1_B1 & !_LC4_B7 - # !_LC3_B16 & !_LC4_B7; - --- Node name is '|video2:SVIDEO|D_PICX_3~1' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC4_B8', type is buried --- synthesized logic cell -!_LC4_B8 = _LC4_B8~NOT; -_LC4_B8~NOT = LCELL( _EQ865C); - _EQ865C = _EQ865; - _EQ865 = _LC3_F20 - # _LC1_B1 & !_LC7_B8 - # !_LC1_B1 & !_LC6_E14 - # !_LC6_E14 & !_LC7_B8; - --- Node name is '|video2:SVIDEO|D_PICX_3' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC5_B8', type is buried -!_LC5_B8 = _LC5_B8~NOT; -_LC5_B8~NOT = LCELL( _EQ866C); - _EQ866C = _EQ866 & CASCADE( _EQ865C); - _EQ866 = !_LC3_F20 - # _LC1_B1 & !_LC3_B8 - # !_LC1_B1 & !_LC7_B6 - # !_LC3_B8 & !_LC7_B6; - --- Node name is '|video2:SVIDEO|D_PICX_4~1' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC4_B16', type is buried --- synthesized logic cell -!_LC4_B16 = _LC4_B16~NOT; -_LC4_B16~NOT = LCELL( _EQ867C); - _EQ867C = _EQ867; - _EQ867 = _LC3_F20 - # _LC1_B1 & !_LC7_B16 - # !_LC1_B1 & !_LC6_D12 - # !_LC6_D12 & !_LC7_B16; - --- Node name is '|video2:SVIDEO|D_PICX_4' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC5_B16', type is buried -!_LC5_B16 = _LC5_B16~NOT; -_LC5_B16~NOT = LCELL( _EQ868C); - _EQ868C = _EQ868 & CASCADE( _EQ867C); - _EQ868 = !_LC3_F20 - # _LC1_B1 & !_LC3_A9 - # !_LC1_B1 & !_LC6_B16 - # !_LC3_A9 & !_LC6_B16; - --- Node name is '|video2:SVIDEO|D_PICX_5~1' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC2_B7', type is buried --- synthesized logic cell -!_LC2_B7 = _LC2_B7~NOT; -_LC2_B7~NOT = LCELL( _EQ869C); - _EQ869C = _EQ869; - _EQ869 = _LC3_F20 - # _LC1_B1 & !_LC6_B7 - # !_LC1_B1 & !_LC8_D12 - # !_LC6_B7 & !_LC8_D12; - --- Node name is '|video2:SVIDEO|D_PICX_5' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC3_B7', type is buried -!_LC3_B7 = _LC3_B7~NOT; -_LC3_B7~NOT = LCELL( _EQ870C); - _EQ870C = _EQ870 & CASCADE( _EQ869C); - _EQ870 = !_LC3_F20 - # _LC1_B1 & !_LC1_B7 - # !_LC1_B1 & !_LC5_A9 - # !_LC1_B7 & !_LC5_A9; - --- Node name is '|video2:SVIDEO|D_PICX_6~1' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC4_B4', type is buried --- synthesized logic cell -!_LC4_B4 = _LC4_B4~NOT; -_LC4_B4~NOT = LCELL( _EQ871C); - _EQ871C = _EQ871; - _EQ871 = _LC3_F20 - # _LC1_B1 & !_LC8_B4 - # !_LC1_B1 & !_LC6_E6 - # !_LC6_E6 & !_LC8_B4; - --- Node name is '|video2:SVIDEO|D_PICX_6' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC5_B4', type is buried -!_LC5_B4 = _LC5_B4~NOT; -_LC5_B4~NOT = LCELL( _EQ872C); - _EQ872C = _EQ872 & CASCADE( _EQ871C); - _EQ872 = !_LC3_F20 - # _LC1_B1 & !_LC6_B4 - # !_LC1_B1 & !_LC7_B4 - # !_LC6_B4 & !_LC7_B4; - --- Node name is '|video2:SVIDEO|D_PICX_7~1' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC3_B15', type is buried --- synthesized logic cell -!_LC3_B15 = _LC3_B15~NOT; -_LC3_B15~NOT = LCELL( _EQ873C); - _EQ873C = _EQ873; - _EQ873 = _LC3_F20 - # !_LC6_B15 & !_LC7_F8 - # !_LC1_B1 & !_LC7_F8 - # _LC1_B1 & !_LC6_B15; - --- Node name is '|video2:SVIDEO|D_PICX_7' from file "video2.tdf" line 527, column 23 --- Equation name is '_LC4_B15', type is buried -!_LC4_B15 = _LC4_B15~NOT; -_LC4_B15~NOT = LCELL( _EQ874C); - _EQ874C = _EQ874 & CASCADE( _EQ873C); - _EQ874 = !_LC3_F20 - # !_LC2_B15 & !_LC5_B15 - # !_LC1_B1 & !_LC2_B15 - # _LC1_B1 & !_LC5_B15; - --- Node name is '|video2:SVIDEO|D_PIC0_0' from file "video2.tdf" line 133, column 9 --- Equation name is '_LC1_B20', type is buried -_LC1_B20 = DFFE( VD00, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC0_1' from file "video2.tdf" line 133, column 9 --- Equation name is '_LC3_F11', type is buried -_LC3_F11 = DFFE( VD01, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC0_2' from file "video2.tdf" line 133, column 9 --- Equation name is '_LC8_F8', type is buried -_LC8_F8 = DFFE( VD02, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC0_3' from file "video2.tdf" line 133, column 9 --- Equation name is '_LC6_E14', type is buried -_LC6_E14 = DFFE( VD03, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC0_4' from file "video2.tdf" line 133, column 9 --- Equation name is '_LC6_D12', type is buried -_LC6_D12 = DFFE( VD04, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC0_5' from file "video2.tdf" line 133, column 9 --- Equation name is '_LC8_D12', type is buried -_LC8_D12 = DFFE( VD05, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC0_6' from file "video2.tdf" line 133, column 9 --- Equation name is '_LC6_E6', type is buried -_LC6_E6 = DFFE( VD06, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC0_7' from file "video2.tdf" line 133, column 9 --- Equation name is '_LC7_F8', type is buried -_LC7_F8 = DFFE( VD07, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC00' from file "video2.tdf" line 130, column 8 --- Equation name is '_LC5_B27', type is buried -_LC5_B27 = DFFE( _EQ875, GLOBAL( TG42), VCC, VCC, !_LC1_B33); - _EQ875 = _LC4_B20 & _LC8_B27; - --- Node name is '|video2:SVIDEO|D_PIC1_0' from file "video2.tdf" line 134, column 9 --- Equation name is '_LC7_B20', type is buried -_LC7_B20 = DFFE( VD10, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC1_1' from file "video2.tdf" line 134, column 9 --- Equation name is '_LC7_F34', type is buried -_LC7_F34 = DFFE( VD11, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC1_2' from file "video2.tdf" line 134, column 9 --- Equation name is '_LC5_B7', type is buried -_LC5_B7 = DFFE( VD12, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC1_3' from file "video2.tdf" line 134, column 9 --- Equation name is '_LC7_B8', type is buried -_LC7_B8 = DFFE( VD13, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC1_4' from file "video2.tdf" line 134, column 9 --- Equation name is '_LC7_B16', type is buried -_LC7_B16 = DFFE( VD14, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC1_5' from file "video2.tdf" line 134, column 9 --- Equation name is '_LC6_B7', type is buried -_LC6_B7 = DFFE( VD15, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC1_6' from file "video2.tdf" line 134, column 9 --- Equation name is '_LC8_B4', type is buried -_LC8_B4 = DFFE( VD16, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC1_7' from file "video2.tdf" line 134, column 9 --- Equation name is '_LC6_B15', type is buried -_LC6_B15 = DFFE( VD17, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC01' from file "video2.tdf" line 130, column 8 --- Equation name is '_LC6_B27', type is buried -_LC6_B27 = DFFE( _EQ876, GLOBAL( TG42), VCC, VCC, !_LC1_B33); - _EQ876 = _LC5_B27 & !_LC8_B27 - # _LC2_F34 & _LC8_B27; - --- Node name is '|video2:SVIDEO|D_PIC2_0' from file "video2.tdf" line 135, column 9 --- Equation name is '_LC8_B20', type is buried -_LC8_B20 = DFFE( VD20, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC2_1' from file "video2.tdf" line 135, column 9 --- Equation name is '_LC8_F34', type is buried -_LC8_F34 = DFFE( VD21, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC2_2' from file "video2.tdf" line 135, column 9 --- Equation name is '_LC4_B7', type is buried -_LC4_B7 = DFFE( VD22, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC2_3' from file "video2.tdf" line 135, column 9 --- Equation name is '_LC7_B6', type is buried -_LC7_B6 = DFFE( VD23, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC2_4' from file "video2.tdf" line 135, column 9 --- Equation name is '_LC6_B16', type is buried -_LC6_B16 = DFFE( VD24, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC2_5' from file "video2.tdf" line 135, column 9 --- Equation name is '_LC5_A9', type is buried -_LC5_A9 = DFFE( VD25, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC2_6' from file "video2.tdf" line 135, column 9 --- Equation name is '_LC7_B4', type is buried -_LC7_B4 = DFFE( VD26, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC2_7' from file "video2.tdf" line 135, column 9 --- Equation name is '_LC2_B15', type is buried -_LC2_B15 = DFFE( VD27, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC02' from file "video2.tdf" line 130, column 8 --- Equation name is '_LC1_B27', type is buried -_LC1_B27 = DFFE( _EQ877, GLOBAL( TG42), VCC, VCC, !_LC1_B33); - _EQ877 = _LC6_B27 & !_LC8_B27 - # _LC8_B7 & _LC8_B27; - --- Node name is '|video2:SVIDEO|D_PIC3_0' from file "video2.tdf" line 136, column 9 --- Equation name is '_LC7_B15', type is buried -_LC7_B15 = DFFE( VD30, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC3_1' from file "video2.tdf" line 136, column 9 --- Equation name is '_LC4_F34', type is buried -_LC4_F34 = DFFE( VD31, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC3_2' from file "video2.tdf" line 136, column 9 --- Equation name is '_LC3_B16', type is buried -_LC3_B16 = DFFE( VD32, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC3_3' from file "video2.tdf" line 136, column 9 --- Equation name is '_LC3_B8', type is buried -_LC3_B8 = DFFE( VD33, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC3_4' from file "video2.tdf" line 136, column 9 --- Equation name is '_LC3_A9', type is buried -_LC3_A9 = DFFE( VD34, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC3_5' from file "video2.tdf" line 136, column 9 --- Equation name is '_LC1_B7', type is buried -_LC1_B7 = DFFE( VD35, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC3_6' from file "video2.tdf" line 136, column 9 --- Equation name is '_LC6_B4', type is buried -_LC6_B4 = DFFE( VD36, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC3_7' from file "video2.tdf" line 136, column 9 --- Equation name is '_LC5_B15', type is buried -_LC5_B15 = DFFE( VD37, GLOBAL(!TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|D_PIC03' from file "video2.tdf" line 130, column 8 --- Equation name is '_LC2_B27', type is buried -_LC2_B27 = DFFE( _EQ878, GLOBAL( TG42), VCC, VCC, !_LC1_B33); - _EQ878 = _LC1_B27 & !_LC8_B27 - # _LC5_B8 & _LC8_B27; - --- Node name is '|video2:SVIDEO|D_PIC04' from file "video2.tdf" line 130, column 8 --- Equation name is '_LC3_B27', type is buried -_LC3_B27 = DFFE( _EQ879, GLOBAL( TG42), VCC, VCC, !_LC1_B33); - _EQ879 = _LC2_B27 & !_LC8_B27 - # _LC5_B16 & _LC8_B27; - --- Node name is '|video2:SVIDEO|D_PIC05' from file "video2.tdf" line 130, column 8 --- Equation name is '_LC4_B27', type is buried -_LC4_B27 = DFFE( _EQ880, GLOBAL( TG42), VCC, VCC, !_LC1_B33); - _EQ880 = _LC3_B27 & !_LC8_B27 - # _LC3_B7 & _LC8_B27; - --- Node name is '|video2:SVIDEO|D_PIC06' from file "video2.tdf" line 130, column 8 --- Equation name is '_LC4_B34', type is buried -_LC4_B34 = DFFE( _EQ881, GLOBAL( TG42), VCC, VCC, !_LC1_B33); - _EQ881 = _LC4_B27 & !_LC8_B27 - # _LC5_B4 & _LC8_B27; - --- Node name is '|video2:SVIDEO|D_PIC07' from file "video2.tdf" line 130, column 8 --- Equation name is '_LC8_B34', type is buried -_LC8_B34 = DFFE( _EQ882, GLOBAL( TG42), VCC, VCC, !_LC1_B33); - _EQ882 = _LC4_B34 & !_LC8_B27 - # _LC4_B15 & _LC8_B27; - --- Node name is '|video2:SVIDEO|E_WR' from file "video2.tdf" line 366, column 9 --- Equation name is '_LC6_C17', type is buried -_LC6_C17 = LCELL( _EQ883); - _EQ883 = !_LC6_C11 & !_LC7_C31 - # !_LC5_C6 - # _LC2_C18; - --- Node name is '|video2:SVIDEO|E_WRD' from file "video2.tdf" line 365, column 10 --- Equation name is '_LC5_E1', type is buried -_LC5_E1 = DFFE( _LC6_C17, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|E_WRD~1' from file "video2.tdf" line 365, column 10 --- Equation name is '_LC2_E1', type is buried --- synthesized logic cell -!_LC2_E1 = _LC2_E1~NOT; -_LC2_E1~NOT = LCELL(!_LC5_E1); - --- Node name is '|video2:SVIDEO|E_WR~1' from file "video2.tdf" line 366, column 9 --- Equation name is '_LC2_C17', type is buried --- synthesized logic cell -!_LC2_C17 = _LC2_C17~NOT; -_LC2_C17~NOT = LCELL(!_LC6_C17); - --- Node name is '|video2:SVIDEO|F_WR' from file "video2.tdf" line 654, column 9 --- Equation name is '_LC1_F7', type is buried -_LC1_F7 = DFFE( VCC, _LC6_F12, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|INTTX' from file "video2.tdf" line 392, column 11 --- Equation name is '_LC2_B26', type is buried -_LC2_B26 = DFFE( _EQ884, _LC1_B21, VCC, VCC, VCC); - _EQ884 = _LC1_B8 & _LC1_B16 & _LC2_B8 & _LC3_B34; - --- Node name is '|video2:SVIDEO|LD_PIC' from file "video2.tdf" line 501, column 11 --- Equation name is '_LC8_B27', type is buried -_LC8_B27 = LCELL( _EQ885); - _EQ885 = _LC5_B19 & _LC5_B34 - # !_LC5_B19 & _LC6_B30; - --- Node name is '|video2:SVIDEO|LWR_COL' from file "video2.tdf" line 568, column 13 --- Equation name is '_LC1_B21', type is buried -_LC1_B21 = DFFE( _LC3_B21, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|LWR_COL~1' from file "video2.tdf" line 568, column 13 --- Equation name is '_LC8_B33', type is buried --- synthesized logic cell -!_LC8_B33 = _LC8_B33~NOT; -_LC8_B33~NOT = LCELL(!_LC1_B21); - --- Node name is '|video2:SVIDEO|LWR_MODE' from file "video2.tdf" line 539, column 14 --- Equation name is '_LC7_B19', type is buried -_LC7_B19 = LCELL( _LC4_B19); - --- Node name is '|video2:SVIDEO|LWR_PIC' from file "video2.tdf" line 567, column 13 --- Equation name is '_LC2_B33', type is buried -_LC2_B33 = DFFE( _LC4_B21, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|LWR_PIC~1' from file "video2.tdf" line 567, column 13 --- Equation name is '_LC1_B33', type is buried --- synthesized logic cell -!_LC1_B33 = _LC1_B33~NOT; -_LC1_B33~NOT = LCELL(!_LC2_B33); - --- Node name is '|video2:SVIDEO|M_CTV0' from file "video2.tdf" line 177, column 7 --- Equation name is '_LC4_F21', type is buried -_LC4_F21 = LCELL( _EQ886); - _EQ886 = _LC1_D22 & !_LC5_F2 - # _LC5_F2 & _LC7_D35; - --- Node name is '|video2:SVIDEO|M_CTV1' from file "video2.tdf" line 177, column 7 --- Equation name is '_LC1_F25', type is buried -_LC1_F25 = LCELL( _EQ887); - _EQ887 = !_LC5_F2 & _LC7_D35 - # _LC2_D22 & _LC5_F2; - --- Node name is '|video2:SVIDEO|M_CTV2' from file "video2.tdf" line 177, column 7 --- Equation name is '_LC5_F25', type is buried -_LC5_F25 = LCELL( _EQ888); - _EQ888 = _LC2_D22 & !_LC5_F2 - # _LC5_F2 & _LC6_F25; - --- Node name is '|video2:SVIDEO|M_CT3' from file "video2.tdf" line 178, column 6 --- Equation name is '_LC2_F35', type is buried -_LC2_F35 = LCELL( _EQ889); - _EQ889 = !_LC5_A29 & !_LC5_F2 - # _LC5_F2 & !_LC7_A29; - --- Node name is '|video2:SVIDEO|M_CT4' from file "video2.tdf" line 178, column 6 --- Equation name is '_LC4_F20', type is buried -_LC4_F20 = LCELL( _EQ890); - _EQ890 = !_LC5_F2 & !_LC7_A29 - # _LC5_F2 & !_LC6_A29; - --- Node name is '|video2:SVIDEO|M_CT5' from file "video2.tdf" line 178, column 6 --- Equation name is '_LC7_F21', type is buried -_LC7_F21 = LCELL( _EQ891); - _EQ891 = !_LC5_F2 & _LC6_A29 - # _LC5_F2 & _LC5_F21; - --- Node name is '|video2:SVIDEO|MODE00' from file "video2.tdf" line 165, column 7 --- Equation name is '_LC1_B8', type is buried -_LC1_B8 = DFFE( VD30, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE01' from file "video2.tdf" line 165, column 7 --- Equation name is '_LC8_A11', type is buried -_LC8_A11 = DFFE( VD31, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE02' from file "video2.tdf" line 165, column 7 --- Equation name is '_LC1_B16', type is buried -_LC1_B16 = DFFE( VD32, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE03' from file "video2.tdf" line 165, column 7 --- Equation name is '_LC2_B8', type is buried -_LC2_B8 = DFFE( VD33, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE04' from file "video2.tdf" line 165, column 7 --- Equation name is '_LC4_A9', type is buried -_LC4_A9 = DFFE( VD34, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE05' from file "video2.tdf" line 165, column 7 --- Equation name is '_LC5_B19', type is buried -_LC5_B19 = DFFE( VD35, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE06' from file "video2.tdf" line 165, column 7 --- Equation name is '_LC2_B4', type is buried -_LC2_B4 = DFFE( VD36, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE07' from file "video2.tdf" line 165, column 7 --- Equation name is '_LC7_B27', type is buried -_LC7_B27 = DFFE( VD37, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE10' from file "video2.tdf" line 166, column 7 --- Equation name is '_LC3_F34', type is buried -_LC3_F34 = DFFE( VD20, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE11' from file "video2.tdf" line 166, column 7 --- Equation name is '_LC3_F25', type is buried -_LC3_F25 = DFFE( VD21, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE12' from file "video2.tdf" line 166, column 7 --- Equation name is '_LC4_F14', type is buried -_LC4_F14 = DFFE( VD22, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE13' from file "video2.tdf" line 166, column 7 --- Equation name is '_LC6_B8', type is buried -_LC6_B8 = DFFE( VD23, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE14' from file "video2.tdf" line 166, column 7 --- Equation name is '_LC8_B9', type is buried -_LC8_B9 = DFFE( VD24, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE15' from file "video2.tdf" line 166, column 7 --- Equation name is '_LC6_A9', type is buried -_LC6_A9 = DFFE( VD25, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE16' from file "video2.tdf" line 166, column 7 --- Equation name is '_LC1_B4', type is buried -_LC1_B4 = DFFE( VD26, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE17' from file "video2.tdf" line 166, column 7 --- Equation name is '_LC8_A9', type is buried -_LC8_A9 = DFFE( VD27, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE20' from file "video2.tdf" line 167, column 7 --- Equation name is '_LC5_F21', type is buried -_LC5_F21 = DFFE( VD10, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE21' from file "video2.tdf" line 167, column 7 --- Equation name is '_LC6_F25', type is buried -_LC6_F25 = DFFE( VD11, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE22' from file "video2.tdf" line 167, column 7 --- Equation name is '_LC5_F2', type is buried -_LC5_F2 = DFFE( VD12, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE23' from file "video2.tdf" line 167, column 7 --- Equation name is '_LC8_B8', type is buried -_LC8_B8 = DFFE( VD13, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE24' from file "video2.tdf" line 167, column 7 --- Equation name is '_LC2_B16', type is buried -_LC2_B16 = DFFE( VD14, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE25' from file "video2.tdf" line 167, column 7 --- Equation name is '_LC7_A9', type is buried -_LC7_A9 = DFFE( VD15, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE26' from file "video2.tdf" line 167, column 7 --- Equation name is '_LC3_B4', type is buried -_LC3_B4 = DFFE( VD16, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MODE27' from file "video2.tdf" line 167, column 7 --- Equation name is '_LC2_A9', type is buried -_LC2_A9 = DFFE( VD17, _LC7_B19, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|MXWE' from file "video2.tdf" line 376, column 9 --- Equation name is '_LC5_F1', type is buried -_LC5_F1 = DFFE( _LC5_F1, GLOBAL( TG42), _LC6_C17, _LC6_F12, VCC); - --- Node name is '|video2:SVIDEO|RBRVA8' from file "video2.tdf" line 147, column 7 --- Equation name is '_LC8_B23', type is buried -_LC8_B23 = DFFE( _EQ892, GLOBAL( TG42), !_LC3_B34, VCC, VCC); - _EQ892 = _LC6_B34 & _LC8_B34 - # _LC2_B34 & !_LC6_B34; - --- Node name is '|video2:SVIDEO|RBRVA9' from file "video2.tdf" line 147, column 7 --- Equation name is '_LC4_B30', type is buried --- |video2:SVIDEO|RBRVA9 is in Up/Down Counter Mode --- synchronous load = _LC6_B34 --- synchronous data = _LC5_B26 -_LC4_B30 = DFFE(( _LC7_B26 & _LC6_B34 # _LC5_B26 & !_LC6_B34), GLOBAL( TG42), !_LC3_B34, VCC, VCC); - --- Node name is '|video2:SVIDEO|RBRVA10' from file "video2.tdf" line 147, column 7 --- Equation name is '_LC7_B30', type is buried -!_LC7_B30 = _LC7_B30~NOT; -_LC7_B30~NOT = DFFE(!_LC6_B34, GLOBAL( TG42), !_LC3_B34, VCC, VCC); - --- Node name is '|video2:SVIDEO|RSVA0~1' from file "video2.tdf" line 490, column 11 --- Equation name is '_LC4_F35', type is buried --- synthesized logic cell -_LC4_F35 = LCELL( _EQ893); - _EQ893 = !_LC1_D22 & _LC4_A9 & !_LC7_F35 - # !_LC2_B4 & _LC4_A9 & _LC7_F35; - --- Node name is '|video2:SVIDEO|RSVA1~1' from file "video2.tdf" line 490, column 11 --- Equation name is '_LC2_F25', type is buried --- synthesized logic cell -_LC2_F25 = LCELL( _EQ894); - _EQ894 = _LC4_A9 & !_LC7_D35 & !_LC7_F35 - # _LC4_A9 & !_LC7_B27 & _LC7_F35; - --- Node name is '|video2:SVIDEO|RSVA6~1' from file "video2.tdf" line 490, column 11 --- Equation name is '_LC6_F21', type is buried --- synthesized logic cell -_LC6_F21 = LCELL( _EQ895); - _EQ895 = _LC3_F34 & _LC4_A9 & !_LC7_F35 - # _LC4_A9 & _LC5_F21 & _LC7_F35; - --- Node name is '|video2:SVIDEO|RSVA7~1' from file "video2.tdf" line 490, column 11 --- Equation name is '_LC7_F25', type is buried --- synthesized logic cell -_LC7_F25 = LCELL( _EQ896); - _EQ896 = _LC3_F25 & _LC4_A9 & !_LC7_F35 - # _LC4_A9 & _LC6_F25 & _LC7_F35; - --- Node name is '|video2:SVIDEO|RSVA8~1' from file "video2.tdf" line 490, column 11 --- Equation name is '_LC5_F14', type is buried --- synthesized logic cell -_LC5_F14 = LCELL( _EQ897); - _EQ897 = _LC4_A9 & _LC4_F14 & !_LC7_F35 - # _LC4_A9 & _LC5_F2 & _LC7_F35; - --- Node name is '|video2:SVIDEO|SVA0' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC6_F35', type is buried -_LC6_F35 = DFFE( _EQ898, GLOBAL( TG42), VCC, VCC, VCC); - _EQ898 = _LC4_F35 - # _LC2_F35 & !_LC4_A9; - --- Node name is '|video2:SVIDEO|SVA1' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC7_F20', type is buried -_LC7_F20 = DFFE( _EQ899, GLOBAL( TG42), VCC, VCC, VCC); - _EQ899 = _LC2_F25 - # !_LC4_A9 & _LC4_F20; - --- Node name is '|video2:SVIDEO|SVA2' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC1_F30', type is buried -_LC1_F30 = DFFE( _EQ900, GLOBAL( TG42), VCC, VCC, VCC); - _EQ900 = !_LC4_A9 & _LC7_F21 - # _LC2_D22 & _LC4_A9 & !_LC7_F35; - --- Node name is '|video2:SVIDEO|SVA3' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC6_F30', type is buried -_LC6_F30 = DFFE( _EQ901, GLOBAL( TG42), VCC, VCC, VCC); - _EQ901 = _LC2_B4 & _LC4_A9 - # _LC4_A9 & _LC7_F35 - # _LC3_F34 & !_LC4_A9; - --- Node name is '|video2:SVIDEO|SVA4' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC8_F25', type is buried -_LC8_F25 = DFFE( _EQ902, GLOBAL( TG42), VCC, VCC, VCC); - _EQ902 = _LC4_A9 & _LC7_B27 - # _LC4_A9 & _LC7_F35 - # _LC3_F25 & !_LC4_A9; - --- Node name is '|video2:SVIDEO|SVA5' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC7_F14', type is buried -_LC7_F14 = DFFE( _EQ903, GLOBAL( TG42), VCC, VCC, VCC); - _EQ903 = _LC4_A9 & _LC8_D13 - # !_LC4_A9 & _LC4_F14; - --- Node name is '|video2:SVIDEO|SVA6' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC5_B13', type is buried -_LC5_B13 = DFFE( _LC1_B8, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|SVA7' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC5_A11', type is buried -_LC5_A11 = DFFE( _LC8_A11, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|SVA8' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC2_B13', type is buried -_LC2_B13 = DFFE( _LC1_B16, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|SVA9' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC8_B15', type is buried -_LC8_B15 = DFFE( _LC2_B8, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|SVA10' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC8_F21', type is buried -_LC8_F21 = DFFE( _EQ904, GLOBAL( TG42), VCC, VCC, VCC); - _EQ904 = _LC6_F21 - # !_LC4_A9 & _LC4_F21; - --- Node name is '|video2:SVIDEO|SVA11' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC4_F25', type is buried -_LC4_F25 = DFFE( _EQ905, GLOBAL( TG42), VCC, VCC, VCC); - _EQ905 = _LC7_F25 - # _LC1_F25 & !_LC4_A9; - --- Node name is '|video2:SVIDEO|SVA12' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC3_F14', type is buried -_LC3_F14 = DFFE( _EQ906, GLOBAL( TG42), VCC, VCC, VCC); - _EQ906 = _LC5_F14 - # !_LC4_A9 & _LC5_F25; - --- Node name is '|video2:SVIDEO|SVA13' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC6_B9', type is buried -_LC6_B9 = DFFE( _EQ907, GLOBAL( TG42), VCC, VCC, VCC); - _EQ907 = _LC4_A9 & _LC7_F35 & _LC8_B8 - # _LC6_B8 & !_LC7_F35 - # !_LC4_A9 & _LC6_B8; - --- Node name is '|video2:SVIDEO|SVA14' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC3_B11', type is buried -_LC3_B11 = DFFE( _EQ908, GLOBAL( TG42), VCC, VCC, VCC); - _EQ908 = _LC2_B16 & _LC4_A9 & _LC7_F35 - # !_LC7_F35 & _LC8_B9 - # !_LC4_A9 & _LC8_B9; - --- Node name is '|video2:SVIDEO|SVA15' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC7_A15', type is buried -_LC7_A15 = DFFE( _EQ909, GLOBAL( TG42), VCC, VCC, VCC); - _EQ909 = _LC4_A9 & _LC7_A9 & _LC7_F35 - # _LC6_A9 & !_LC7_F35 - # !_LC4_A9 & _LC6_A9; - --- Node name is '|video2:SVIDEO|SVA16' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC5_B9', type is buried -_LC5_B9 = DFFE( _EQ910, GLOBAL( TG42), VCC, VCC, VCC); - _EQ910 = _LC3_B4 & _LC4_A9 & _LC7_F35 - # _LC1_B4 & !_LC7_F35 - # _LC1_B4 & !_LC4_A9; - --- Node name is '|video2:SVIDEO|SVA17' from file "video2.tdf" line 108, column 5 --- Equation name is '_LC8_A15', type is buried -_LC8_A15 = DFFE( _EQ911, GLOBAL( TG42), VCC, VCC, VCC); - _EQ911 = _LC2_A9 & _LC4_A9 & _LC7_F35 - # !_LC7_F35 & _LC8_A9 - # !_LC4_A9 & _LC8_A9; - --- Node name is '|video2:SVIDEO|VCM0' from file "video2.tdf" line 114, column 5 --- Equation name is '_LC3_F1', type is buried -_LC3_F1 = DFFE( _EQ912, GLOBAL( TG42), VCC, VCC, VCC); - _EQ912 = _LC3_F35 & !_LC7_F1 - # !_LC3_E28 & !_LC7_F1; - --- Node name is '|video2:SVIDEO|VCM1' from file "video2.tdf" line 114, column 5 --- Equation name is '_LC5_F35', type is buried -_LC5_F35 = DFFE( _EQ913, GLOBAL( TG42), VCC, VCC, VCC); - _EQ913 = _LC3_E28 & !_LC3_F35 & !_LC7_F1 - # !_LC3_E28 & _LC3_F35 & !_LC7_F1; - --- Node name is '|video2:SVIDEO|VCM2' from file "video2.tdf" line 114, column 5 --- Equation name is '_LC7_F35', type is buried -_LC7_F35 = DFFE( _EQ914, GLOBAL( TG42), VCC, VCC, VCC); - _EQ914 = _LC3_E28 & _LC3_F35 & !_LC7_F1 - # !_LC3_E28 & !_LC3_F35 & _LC7_F1; - --- Node name is '|video2:SVIDEO|V_EN0' from file "video2.tdf" line 652, column 10 --- Equation name is '_LC5_F7', type is buried -_LC5_F7 = DFFE( _EQ915, GLOBAL( TG42), _LC1_F7, VCC, VCC); - _EQ915 = !_LC4_C17 & !_LC6_F7 - # !_LC3_C10; - --- Node name is '|video2:SVIDEO|V_EN1' from file "video2.tdf" line 651, column 10 --- Equation name is '_LC8_F7', type is buried -_LC8_F7 = DFFE( _EQ916, GLOBAL( TG42), _LC1_F7, VCC, VCC); - _EQ916 = _LC4_C17 & !_LC6_F7 - # !_LC3_C10; - --- Node name is '|video2:SVIDEO|V_EN2' from file "video2.tdf" line 650, column 10 --- Equation name is '_LC3_F7', type is buried -_LC3_F7 = DFFE( _EQ917, GLOBAL( TG42), _LC1_F7, VCC, VCC); - _EQ917 = !_LC4_C17 & !_LC6_F7 - # _LC3_C10; - --- Node name is '|video2:SVIDEO|V_EN3' from file "video2.tdf" line 649, column 10 --- Equation name is '_LC7_F7', type is buried -_LC7_F7 = DFFE( _EQ918, GLOBAL( TG42), _LC1_F7, VCC, VCC); - _EQ918 = _LC3_C10 - # _LC4_C17 & !_LC6_F7; - --- Node name is '|video2:SVIDEO|VLA0' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC1_F35', type is buried -_LC1_F35 = DFFE( _EQ919, GLOBAL( TG42), VCC, VCC, VCC); - _EQ919 = !_LC3_F1 & _LC4_C17 & _LC5_F35 - # _LC3_F1 & !_LC5_F35 & _LC6_F35; - --- Node name is '|video2:SVIDEO|VLA1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC1_F20', type is buried -_LC1_F20 = DFFE( _EQ920, GLOBAL( TG42), VCC, VCC, VCC); - _EQ920 = _LC3_C10 & !_LC3_F1 & _LC5_F35 - # _LC3_F1 & !_LC5_F35 & _LC7_F20; - --- Node name is '|video2:SVIDEO|VLA2~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC1_F3', type is buried --- synthesized logic cell -_LC1_F3 = LCELL(!_LC3_F30); - --- Node name is '|video2:SVIDEO|VLA3~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC1_F5', type is buried --- synthesized logic cell -_LC1_F5 = LCELL(!_LC5_F30); - --- Node name is '|video2:SVIDEO|VLA4~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC2_F7', type is buried --- synthesized logic cell -_LC2_F7 = LCELL(!_LC8_F30); - --- Node name is '|video2:SVIDEO|VLA10~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC6_F11', type is buried --- synthesized logic cell -_LC6_F11 = LCELL(!_LC6_F20); - --- Node name is '|video2:SVIDEO|VLA11~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC5_F9', type is buried --- synthesized logic cell -_LC5_F9 = LCELL(!_LC8_F12); - --- Node name is '|video2:SVIDEO|VLA12~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC8_F5', type is buried --- synthesized logic cell -_LC8_F5 = LCELL(!_LC5_F12); - --- Node name is '|video2:SVIDEO|VLA13~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC1_B9', type is buried --- synthesized logic cell -_LC1_B9 = LCELL(!_LC4_B9); - --- Node name is '|video2:SVIDEO|VLA14~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC1_B19', type is buried --- synthesized logic cell -_LC1_B19 = LCELL(!_LC3_B19); - --- Node name is '|video2:SVIDEO|VLA15~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC7_A14', type is buried --- synthesized logic cell -_LC7_A14 = LCELL(!_LC5_A15); - --- Node name is '|video2:SVIDEO|VLA16~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC2_B20', type is buried --- synthesized logic cell -_LC2_B20 = LCELL(!_LC6_B20); - --- Node name is '|video2:SVIDEO|VLA17~fit~in1' from file "video2.tdf" line 106, column 5 --- Equation name is '_LC1_F21', type is buried --- synthesized logic cell -_LC1_F21 = LCELL(!_LC3_F21); - --- Node name is '|video2:SVIDEO|V_WE' from file "video2.tdf" line 116, column 2 --- Equation name is '_LC6_F12', type is buried -!_LC6_F12 = _LC6_F12~NOT; -_LC6_F12~NOT = DFFE( _EQ921, GLOBAL( TG42), _LC5_F11, VCC, VCC); - _EQ921 = !_LC3_F1 & !_LC5_F1 & _LC5_F35; - --- Node name is '|video2:SVIDEO|V_WEM' from file "video2.tdf" line 646, column 10 --- Equation name is '_LC2_F18', type is buried -_LC2_F18 = LCELL( _EQ922); - _EQ922 = _LC3_F12 & _LC3_F15; - --- Node name is '|video2:SVIDEO|V_WEMMM' from file "video2.tdf" line 638, column 12 --- Equation name is '_LC3_F12', type is buried -_LC3_F12 = LCELL( _LC6_F12); - --- Node name is '|video2:SVIDEO|V_WEMMN' from file "video2.tdf" line 639, column 12 --- Equation name is '_LC2_F12', type is buried -_LC2_F12 = LCELL( _LC3_F12); - --- Node name is '|video2:SVIDEO|V_WEMMO' from file "video2.tdf" line 640, column 12 --- Equation name is '_LC3_F15', type is buried -_LC3_F15 = LCELL( _LC2_F12); - --- Node name is '|video2:SVIDEO|V_WEM2' from file "video2.tdf" line 647, column 11 --- Equation name is '_LC2_F20', type is buried -_LC2_F20 = LCELL( _EQ923); - _EQ923 = _LC3_F12 & _LC3_F15; - --- Node name is '|video2:SVIDEO|V_WE_R' from file "video2.tdf" line 625, column 12 --- Equation name is '_LC5_F11', type is buried -!_LC5_F11 = _LC5_F11~NOT; -_LC5_F11~NOT = DFFE( VCC, GLOBAL(!TG42), !_LC6_F12, VCC, VCC); - --- Node name is '|video2:SVIDEO|V_WEY0' from file "video2.tdf" line 195, column 7 --- Equation name is '_LC2_F17', type is buried -_LC2_F17 = LCELL( _EQ924); - _EQ924 = _LC5_F7 - # _LC2_F18; - --- Node name is '|video2:SVIDEO|V_WEY1' from file "video2.tdf" line 195, column 7 --- Equation name is '_LC2_F16', type is buried -_LC2_F16 = LCELL( _EQ925); - _EQ925 = _LC8_F7 - # _LC2_F18; - --- Node name is '|video2:SVIDEO|V_WEY2' from file "video2.tdf" line 195, column 7 --- Equation name is '_LC2_F19', type is buried -_LC2_F19 = LCELL( _EQ926); - _EQ926 = _LC2_F20 - # _LC3_F7; - --- Node name is '|video2:SVIDEO|V_WEY3' from file "video2.tdf" line 195, column 7 --- Equation name is '_LC2_F14', type is buried -_LC2_F14 = LCELL( _EQ927); - _EQ927 = _LC7_F7 - # _LC2_F18; - --- Node name is '|video2:SVIDEO|V_WRM' from file "video2.tdf" line 643, column 10 --- Equation name is '_LC8_F18', type is buried -_LC8_F18 = LCELL( _EQ928); - _EQ928 = _LC2_F12 & _LC3_F12; - --- Node name is '|video2:SVIDEO|V_WRM2' from file "video2.tdf" line 644, column 11 --- Equation name is '_LC8_F20', type is buried -_LC8_F20 = LCELL( _EQ929); - _EQ929 = _LC2_F12 & _LC3_F12; - --- Node name is '|video2:SVIDEO|V_WR_0' from file "video2.tdf" line 194, column 7 --- Equation name is '_LC8_F17', type is buried -_LC8_F17 = LCELL( _EQ930); - _EQ930 = _LC8_F18 - # _LC5_F7; - --- Node name is '|video2:SVIDEO|V_WR_1' from file "video2.tdf" line 194, column 7 --- Equation name is '_LC8_F16', type is buried -_LC8_F16 = LCELL( _EQ931); - _EQ931 = _LC8_F18 - # _LC8_F7; - --- Node name is '|video2:SVIDEO|V_WR_2' from file "video2.tdf" line 194, column 7 --- Equation name is '_LC8_F19', type is buried -_LC8_F19 = LCELL( _EQ932); - _EQ932 = _LC8_F20 - # _LC3_F7; - --- Node name is '|video2:SVIDEO|V_WR_3' from file "video2.tdf" line 194, column 7 --- Equation name is '_LC8_F14', type is buried -_LC8_F14 = LCELL( _EQ933); - _EQ933 = _LC8_F18 - # _LC7_F7; - --- Node name is '|video2:SVIDEO|VXA0' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC4_C17', type is buried -_LC4_C17 = DFFE( _EQ934, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ934 = !_LC6_C11 & _LC8_C22 - # _LC1_C22 & _LC6_C11; - --- Node name is '|video2:SVIDEO|VXA1' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC3_C10', type is buried -_LC3_C10 = DFFE( _EQ935, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ935 = _LC1_C24 & !_LC6_C11 - # _LC2_C36 & _LC6_C11; - --- Node name is '|video2:SVIDEO|VXA2' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC7_C17', type is buried -_LC7_C17 = DFFE( _EQ936, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ936 = !_LC6_C11 & _LC6_C31 - # _LC2_C22 & _LC6_C11; - --- Node name is '|video2:SVIDEO|VXA3' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC3_C16', type is buried -_LC3_C16 = DFFE( _EQ937, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ937 = !_LC6_C11 & _LC7_C27 - # _LC3_C22 & _LC6_C11; - --- Node name is '|video2:SVIDEO|VXA4' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC6_C16', type is buried -_LC6_C16 = DFFE( _EQ938, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ938 = _LC2_C11 & !_LC6_C11 - # _LC4_C22 & _LC6_C11; - --- Node name is '|video2:SVIDEO|VXA5' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC4_C11', type is buried -_LC4_C11 = DFFE( _EQ939, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ939 = _LC1_C36 & !_LC6_C11 - # _LC5_C22 & _LC6_C11; - --- Node name is '|video2:SVIDEO|VXA6' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC5_C17', type is buried -_LC5_C17 = DFFE( _EQ940, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ940 = _LC3_C36 & !_LC6_C11 - # _LC6_C11 & _LC6_C22; - --- Node name is '|video2:SVIDEO|VXA7' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC5_C11', type is buried -_LC5_C11 = DFFE( _EQ941, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ941 = _LC3_C19 & !_LC6_C11 - # _LC6_C11 & _LC7_C22; - --- Node name is '|video2:SVIDEO|VXA8' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC7_C11', type is buried -_LC7_C11 = DFFE( _EQ942, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ942 = _LC4_C19 & !_LC6_C11 - # _LC6_C11 & _LC8_C22; - --- Node name is '|video2:SVIDEO|VXA9' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC6_C10', type is buried -_LC6_C10 = DFFE( _EQ943, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ943 = _LC5_C19 & !_LC6_C11 - # _LC1_C24 & _LC6_C11; - --- Node name is '|video2:SVIDEO|VXA10' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC8_C17', type is buried -_LC8_C17 = DFFE( _EQ944, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ944 = _LC1_C22 & !_LC6_C11 - # _LC6_C11 & _LC6_C31; - --- Node name is '|video2:SVIDEO|VXA11' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC7_C16', type is buried -_LC7_C16 = DFFE( _EQ945, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ945 = _LC2_C36 & !_LC6_C11 - # _LC6_C11 & _LC7_C27; - --- Node name is '|video2:SVIDEO|VXA12' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC3_C5', type is buried -_LC3_C5 = DFFE( _EQ946, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ946 = _LC2_C22 & !_LC6_C11 - # _LC2_C11 & _LC6_C11; - --- Node name is '|video2:SVIDEO|VXA13' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC8_C16', type is buried -_LC8_C16 = DFFE( _EQ947, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ947 = _LC3_C22 & !_LC6_C11 - # _LC6_C11 & _LC8_C27; - --- Node name is '|video2:SVIDEO|VXA14' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC2_C2', type is buried -_LC2_C2 = DFFE( _EQ948, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ948 = _LC6_C11 & _LC8_C7 - # _LC4_C22 & !_LC6_C11; - --- Node name is '|video2:SVIDEO|VXA15' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC8_A34', type is buried -_LC8_A34 = DFFE( _EQ949, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ949 = _LC1_C19 & _LC6_C11 - # _LC5_C22 & !_LC6_C11; - --- Node name is '|video2:SVIDEO|VXA16' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC3_C17', type is buried -_LC3_C17 = DFFE( _EQ950, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ950 = _LC6_C11 & _LC8_C35 - # !_LC6_C11 & _LC6_C22; - --- Node name is '|video2:SVIDEO|VXA17' from file "video2.tdf" line 91, column 5 --- Equation name is '_LC7_B1', type is buried -_LC7_B1 = DFFE( _EQ951, GLOBAL( TG42), VCC, VCC, !_LC2_C17); - _EQ951 = _LC3_C11 & _LC6_C11 - # !_LC6_C11 & _LC7_C22; - --- Node name is '|video2:SVIDEO|VXD00' from file "video2.tdf" line 93, column 6 --- Equation name is '_LC5_A1', type is buried -_LC5_A1 = DFFE( _LC3_A1, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD01' from file "video2.tdf" line 93, column 6 --- Equation name is '_LC5_F29', type is buried -_LC5_F29 = DFFE( _LC3_D35, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD02' from file "video2.tdf" line 93, column 6 --- Equation name is '_LC1_F1', type is buried -_LC1_F1 = DFFE( _LC5_D33, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD03' from file "video2.tdf" line 93, column 6 --- Equation name is '_LC3_E14', type is buried -_LC3_E14 = DFFE( _LC3_D28, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD04' from file "video2.tdf" line 93, column 6 --- Equation name is '_LC5_D3', type is buried -_LC5_D3 = DFFE( _LC5_D24, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD05' from file "video2.tdf" line 93, column 6 --- Equation name is '_LC8_D1', type is buried -_LC8_D1 = DFFE( _LC1_D21, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD06' from file "video2.tdf" line 93, column 6 --- Equation name is '_LC7_E14', type is buried -_LC7_E14 = DFFE( _LC6_D19, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD07' from file "video2.tdf" line 93, column 6 --- Equation name is '_LC6_F1', type is buried -_LC6_F1 = DFFE( _LC1_D17, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD10' from file "video2.tdf" line 94, column 6 --- Equation name is '_LC6_D1', type is buried -_LC6_D1 = DFFE( _LC2_D28, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD11' from file "video2.tdf" line 94, column 6 --- Equation name is '_LC8_F1', type is buried -_LC8_F1 = DFFE( _LC5_D25, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD12' from file "video2.tdf" line 94, column 6 --- Equation name is '_LC5_E14', type is buried -_LC5_E14 = DFFE( _LC2_D21, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD13' from file "video2.tdf" line 94, column 6 --- Equation name is '_LC3_D3', type is buried -_LC3_D3 = DFFE( _LC8_D19, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD14' from file "video2.tdf" line 94, column 6 --- Equation name is '_LC6_C5', type is buried -_LC6_C5 = DFFE( _LC8_D5, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD15' from file "video2.tdf" line 94, column 6 --- Equation name is '_LC4_C5', type is buried -_LC4_C5 = DFFE( _LC4_D5, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD16' from file "video2.tdf" line 94, column 6 --- Equation name is '_LC5_C5', type is buried -_LC5_C5 = DFFE( _LC3_D5, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD17' from file "video2.tdf" line 94, column 6 --- Equation name is '_LC1_E1', type is buried -_LC1_E1 = DFFE( _LC6_D3, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD20' from file "video2.tdf" line 95, column 6 --- Equation name is '_LC1_A1', type is buried -_LC1_A1 = DFFE( _LC3_A1, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD21' from file "video2.tdf" line 95, column 6 --- Equation name is '_LC3_F2', type is buried -_LC3_F2 = DFFE( _LC3_D35, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD22' from file "video2.tdf" line 95, column 6 --- Equation name is '_LC3_C1', type is buried -_LC3_C1 = DFFE( _LC5_D33, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD23' from file "video2.tdf" line 95, column 6 --- Equation name is '_LC6_B3', type is buried -_LC6_B3 = DFFE( _LC3_D28, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD24' from file "video2.tdf" line 95, column 6 --- Equation name is '_LC5_B18', type is buried -_LC5_B18 = DFFE( _LC5_D24, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD25' from file "video2.tdf" line 95, column 6 --- Equation name is '_LC8_A1', type is buried -_LC8_A1 = DFFE( _LC1_D21, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD26' from file "video2.tdf" line 95, column 6 --- Equation name is '_LC3_B18', type is buried -_LC3_B18 = DFFE( _LC6_D19, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD27' from file "video2.tdf" line 95, column 6 --- Equation name is '_LC8_C1', type is buried -_LC8_C1 = DFFE( _LC1_D17, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD30' from file "video2.tdf" line 96, column 6 --- Equation name is '_LC4_F1', type is buried -_LC4_F1 = DFFE( _LC2_D28, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD31' from file "video2.tdf" line 96, column 6 --- Equation name is '_LC1_C5', type is buried -_LC1_C5 = DFFE( _LC5_D25, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD32' from file "video2.tdf" line 96, column 6 --- Equation name is '_LC1_B3', type is buried -_LC1_B3 = DFFE( _LC2_D21, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD33' from file "video2.tdf" line 96, column 6 --- Equation name is '_LC6_A15', type is buried -_LC6_A15 = DFFE( _LC8_D19, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD34' from file "video2.tdf" line 96, column 6 --- Equation name is '_LC3_A15', type is buried -_LC3_A15 = DFFE( _LC8_D5, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD35' from file "video2.tdf" line 96, column 6 --- Equation name is '_LC2_B18', type is buried -_LC2_B18 = DFFE( _LC4_D5, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD36' from file "video2.tdf" line 96, column 6 --- Equation name is '_LC7_B18', type is buried -_LC7_B18 = DFFE( _LC3_D5, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|VXD37' from file "video2.tdf" line 96, column 6 --- Equation name is '_LC1_D3', type is buried -_LC1_D3 = DFFE( _LC6_D3, GLOBAL( TG42), VCC, VCC, !_LC2_E1); - --- Node name is '|video2:SVIDEO|WR_COL' from file "video2.tdf" line 144, column 2 --- Equation name is '_LC3_B21', type is buried -_LC3_B21 = DFFE( _EQ952, GLOBAL( TG42), VCC, VCC, VCC); - _EQ952 = _LC7_F35 - # !_LC3_F1 - # _LC5_F35; - --- Node name is '|video2:SVIDEO|WR_MODE' from file "video2.tdf" line 170, column 2 --- Equation name is '_LC8_B19', type is buried -_LC8_B19 = DFFE( _EQ953, GLOBAL( TG42), VCC, VCC, VCC); - _EQ953 = !_LC5_A29 - # _LC6_B19 - # !_LC3_F1 - # !_LC5_F35; - --- Node name is '|video2:SVIDEO|WR_PIC' from file "video2.tdf" line 143, column 2 --- Equation name is '_LC4_B21', type is buried -_LC4_B21 = DFFE( _EQ954, GLOBAL( TG42), VCC, VCC, VCC); - _EQ954 = !_LC3_F1 - # _LC2_B21 & _LC5_F35 - # !_LC5_F35 & !_LC7_F35 - # _LC2_B21 & !_LC7_F35; - --- Node name is '|video2:SVIDEO|X_MODE4' from file "video2.tdf" line 555, column 12 --- Equation name is '_LC6_B34', type is buried -_LC6_B34 = DFFE( _LC4_A9, _LC1_B21, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|X_MODE5' from file "video2.tdf" line 554, column 12 --- Equation name is '_LC2_B21', type is buried -_LC2_B21 = DFFE( _LC5_B19, _LC1_B21, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|X_MODE6' from file "video2.tdf" line 553, column 12 --- Equation name is '_LC2_B34', type is buried -_LC2_B34 = DFFE( _LC2_B4, _LC1_B21, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|X_MODE7' from file "video2.tdf" line 552, column 12 --- Equation name is '_LC5_B26', type is buried -_LC5_B26 = DFFE( _LC7_B27, _LC1_B21, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|:292' from file "video2.tdf" line 86, column 4 --- Equation name is '_LC6_A29', type is buried -_LC6_A29 = DFFE( _EQ955, GLOBAL( TG42), !copy_sinc_h, VCC, _LC2_A29); - _EQ955 = !_LC5_A29 & _LC6_A29 - # _LC6_A29 & !_LC7_A29 - # _LC5_A29 & !_LC6_A29 & _LC7_A29; - --- Node name is '|video2:SVIDEO|:293' from file "video2.tdf" line 86, column 4 --- Equation name is '_LC7_A29', type is buried -_LC7_A29 = DFFE( _EQ956, GLOBAL( TG42), VCC, VCC, _LC2_A29); - _EQ956 = _LC5_A29 & !_LC7_A29 - # !_LC5_A29 & _LC7_A29; - --- Node name is '|video2:SVIDEO|:294' from file "video2.tdf" line 86, column 4 --- Equation name is '_LC5_A29', type is buried -_LC5_A29 = DFFE(!_LC5_A29, GLOBAL( TG42), VCC, VCC, _LC2_A29); - --- Node name is '|video2:SVIDEO|:295' from file "video2.tdf" line 86, column 4 --- Equation name is '_LC3_E28', type is buried -_LC3_E28 = DFFE( _EQ957, GLOBAL( TG42), VCC, VCC, VCC); - _EQ957 = !_LC3_E28 & _LC3_F35 - # _LC3_E28 & !_LC3_F35; - --- Node name is '|video2:SVIDEO|:296' from file "video2.tdf" line 86, column 4 --- Equation name is '_LC3_F35', type is buried -_LC3_F35 = DFFE( _EQ958, GLOBAL( TG42), VCC, VCC, VCC); - _EQ958 = !_LC3_F35 & _LC7_F1; - --- Node name is '|video2:SVIDEO|:297' from file "video2.tdf" line 86, column 4 --- Equation name is '_LC7_F1', type is buried -_LC7_F1 = DFFE( _EQ959, GLOBAL( TG42), VCC, VCC, VCC); - _EQ959 = !_LC3_F35 & !_LC7_F1; - --- Node name is '|video2:SVIDEO|:298' from file "video2.tdf" line 87, column 5 --- Equation name is '_LC6_A30', type is buried -!_LC6_A30 = _LC6_A30~NOT; -_LC6_A30~NOT = DFFE(!_LC5_A30_CARRY, GLOBAL( TG42), !copy_sinc_h, VCC, _LC7_A30); - --- Node name is '|video2:SVIDEO|:299' from file "video2.tdf" line 87, column 5 --- Equation name is '_LC4_A30', type is buried --- |video2:SVIDEO|:299 is in Up/Down Counter Mode --- synchronous load = _LC7_A36 -!_LC4_A30 = _LC4_A30~NOT; -_LC4_A30~NOT = DFFE(( _EQ960 & _LC7_A36 # !_LC7_A36), GLOBAL( TG42), !copy_sinc_h, VCC, _LC7_A30); - _EQ960 = _LC3_A30_CARRY & _LC4_A30 - # !_LC3_A30_CARRY & !_LC4_A30; - --- Node name is '|video2:SVIDEO|:300' from file "video2.tdf" line 87, column 5 --- Equation name is '_LC3_A30', type is buried --- |video2:SVIDEO|:300 is in Clearable Counter Mode --- synchronous clear = _LC7_A36 -_LC3_A30 = DFFE( _EQ961 & _LC7_A36, GLOBAL( TG42), !copy_sinc_h, VCC, _LC7_A30); - _EQ961 = !_LC2_A30_CARRY & _LC3_A30 - # _LC2_A30_CARRY & !_LC3_A30; - --- Node name is '|video2:SVIDEO|:301' from file "video2.tdf" line 87, column 5 --- Equation name is '_LC2_A30', type is buried --- |video2:SVIDEO|:301 is in Clearable Counter Mode --- synchronous clear = _LC7_A36 -_LC2_A30 = DFFE( _EQ962 & _LC7_A36, GLOBAL( TG42), !copy_sinc_h, VCC, _LC7_A30); - _EQ962 = !_LC1_A30_CARRY & _LC2_A30 - # _LC1_A30_CARRY & !_LC2_A30; - --- Node name is '|video2:SVIDEO|:302' from file "video2.tdf" line 87, column 5 --- Equation name is '_LC8_A30', type is buried -!_LC8_A30 = _LC8_A30~NOT; -_LC8_A30~NOT = DFFE( _EQ963, GLOBAL( TG42), !copy_sinc_h, VCC, _LC7_A30); - _EQ963 = _LC1_A30 & _LC8_A30 - # !_LC1_A30 & !_LC8_A30 - # !_LC7_A36; - --- Node name is '|video2:SVIDEO|:303' from file "video2.tdf" line 87, column 5 --- Equation name is '_LC1_A30', type is buried --- |video2:SVIDEO|:303 is in Up/Down Counter Mode -_LC1_A30 = DFFE(!_LC1_A30, GLOBAL( TG42), !copy_sinc_h, VCC, _LC7_A30); - --- Node name is '|video2:SVIDEO|:304' from file "video2.tdf" line 88, column 5 --- Equation name is '_LC8_D22', type is buried -!_LC8_D22 = _LC8_D22~NOT; -_LC8_D22~NOT = DFFE( _EQ964, GLOBAL( TG42), !copy_sinc_v, VCC, _LC3_A36); - _EQ964 = _LC7_D22_CARRY & _LC8_D22 - # !_LC7_D22_CARRY & !_LC8_D22 - # !_LC4_D31; - --- Node name is '|video2:SVIDEO|:305' from file "video2.tdf" line 88, column 5 --- Equation name is '_LC7_D22', type is buried --- |video2:SVIDEO|:305 is in Clearable Counter Mode --- synchronous clear = _LC4_D31 -_LC7_D22 = DFFE( _EQ965 & _LC4_D31, GLOBAL( TG42), !copy_sinc_v, VCC, _LC3_A36); - _EQ965 = !_LC6_D22_CARRY & _LC7_D22 - # _LC6_D22_CARRY & !_LC7_D22; - --- Node name is '|video2:SVIDEO|:306' from file "video2.tdf" line 88, column 5 --- Equation name is '_LC6_D22', type is buried --- |video2:SVIDEO|:306 is in Clearable Counter Mode --- synchronous clear = _LC4_D31 -_LC6_D22 = DFFE( _EQ966 & _LC4_D31, GLOBAL( TG42), !copy_sinc_v, VCC, _LC3_A36); - _EQ966 = !_LC5_D22_CARRY & _LC6_D22 - # _LC5_D22_CARRY & !_LC6_D22; - --- Node name is '|video2:SVIDEO|:307' from file "video2.tdf" line 88, column 5 --- Equation name is '_LC5_D22', type is buried --- |video2:SVIDEO|:307 is in Up/Down Counter Mode --- synchronous load = _LC4_D31 -!_LC5_D22 = _LC5_D22~NOT; -_LC5_D22~NOT = DFFE(( _EQ967 & _LC4_D31 # !_LC4_D31), GLOBAL( TG42), !copy_sinc_v, VCC, _LC3_A36); - _EQ967 = _LC4_D22_CARRY & _LC5_D22 - # !_LC4_D22_CARRY & !_LC5_D22; - --- Node name is '|video2:SVIDEO|:308' from file "video2.tdf" line 88, column 5 --- Equation name is '_LC4_D22', type is buried --- |video2:SVIDEO|:308 is in Clearable Counter Mode --- synchronous clear = _LC4_D31 -_LC4_D22 = DFFE( _EQ968 & _LC4_D31, GLOBAL( TG42), !copy_sinc_v, VCC, _LC3_A36); - _EQ968 = !_LC3_D22_CARRY & _LC4_D22 - # _LC3_D22_CARRY & !_LC4_D22; - --- Node name is '|video2:SVIDEO|:309' from file "video2.tdf" line 88, column 5 --- Equation name is '_LC3_D22', type is buried --- |video2:SVIDEO|:309 is in Clearable Counter Mode --- synchronous clear = _LC4_D31 -_LC3_D22 = DFFE( _EQ969 & _LC4_D31, GLOBAL( TG42), !copy_sinc_v, VCC, _LC3_A36); - _EQ969 = !_LC2_D22_CARRY & _LC3_D22 - # _LC2_D22_CARRY & !_LC3_D22; - --- Node name is '|video2:SVIDEO|:310' from file "video2.tdf" line 88, column 5 --- Equation name is '_LC2_D22', type is buried --- |video2:SVIDEO|:310 is in Clearable Counter Mode --- synchronous clear = _LC4_D31 -_LC2_D22 = DFFE( _EQ970 & _LC4_D31, GLOBAL( TG42), !copy_sinc_v, VCC, _LC3_A36); - _EQ970 = !_LC1_D22_CARRY & _LC2_D22 - # _LC1_D22_CARRY & !_LC2_D22; - --- Node name is '|video2:SVIDEO|:311' from file "video2.tdf" line 88, column 5 --- Equation name is '_LC7_D35', type is buried -!_LC7_D35 = _LC7_D35~NOT; -_LC7_D35~NOT = DFFE( _EQ971, GLOBAL( TG42), !copy_sinc_v, VCC, _LC3_A36); - _EQ971 = !_LC4_D31 - # _LC1_D22 & _LC7_D35 - # !_LC1_D22 & !_LC7_D35; - --- Node name is '|video2:SVIDEO|:312' from file "video2.tdf" line 88, column 5 --- Equation name is '_LC1_D22', type is buried --- |video2:SVIDEO|:312 is in Up/Down Counter Mode -_LC1_D22 = DFFE(!_LC1_D22, GLOBAL( TG42), !copy_sinc_v, VCC, _LC3_A36); - --- Node name is '|video2:SVIDEO|:315' from file "video2.tdf" line 89, column 5 --- Equation name is '_LC5_B30', type is buried -_LC5_B30 = DFFE( _LC4_B30_CARRY, _LC8_D22, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|:316' from file "video2.tdf" line 89, column 5 --- Equation name is '_LC3_B30', type is buried --- |video2:SVIDEO|:316 is in Up/Down Counter Mode -_LC3_B30 = DFFE( _EQ972, _LC8_D22, VCC, VCC, VCC); - _EQ972 = !_LC2_B30_CARRY & _LC3_B30 - # _LC2_B30_CARRY & !_LC3_B30; - --- Node name is '|video2:SVIDEO|:317' from file "video2.tdf" line 89, column 5 --- Equation name is '_LC2_B30', type is buried --- |video2:SVIDEO|:317 is in Up/Down Counter Mode -_LC2_B30 = DFFE( _EQ973, _LC8_D22, VCC, VCC, VCC); - _EQ973 = !_LC1_B30_CARRY & _LC2_B30 - # _LC1_B30_CARRY & !_LC2_B30; - --- Node name is '|video2:SVIDEO|:318' from file "video2.tdf" line 89, column 5 --- Equation name is '_LC8_B30', type is buried -_LC8_B30 = DFFE( _EQ974, _LC8_D22, VCC, VCC, VCC); - _EQ974 = _LC1_B30 & !_LC8_B30 - # !_LC1_B30 & _LC8_B30; - --- Node name is '|video2:SVIDEO|:319' from file "video2.tdf" line 89, column 5 --- Equation name is '_LC1_B30', type is buried --- |video2:SVIDEO|:319 is in Up/Down Counter Mode -_LC1_B30 = DFFE(!_LC1_B30, _LC8_D22, VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|:623' from file "video2.tdf" line 297, column 17 --- Equation name is '_LC2_A29', type is buried -_LC2_A29 = DFFE( _EQ975, GLOBAL( TG42), VCC, VCC, VCC); - _EQ975 = _LC3_E28 & _LC7_F1; - --- Node name is '|video2:SVIDEO|:624' from file "video2.tdf" line 307, column 15 --- Equation name is '_LC7_A30', type is buried -_LC7_A30 = DFFE( _EQ976, GLOBAL( TG42), VCC, VCC, VCC); - _EQ976 = _LC3_A34 & _LC3_E28 & _LC5_A29 & _LC6_A29; - --- Node name is '|video2:SVIDEO|:625' from file "video2.tdf" line 308, column 15 --- Equation name is '_LC3_A36', type is buried -_LC3_A36 = DFFE( _EQ977, GLOBAL( TG42), VCC, VCC, VCC); - _EQ977 = !_LC1_A30 & _LC1_A36 & _LC6_A29 & _LC6_A36; - --- Node name is '|video2:SVIDEO|:628' from file "video2.tdf" line 366, column 47 --- Equation name is '_LC5_C6', type is buried -_LC5_C6 = DFFE( _LC2_C18, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|:630' from file "video2.tdf" line 383, column 40 --- Equation name is '_LC1_C36', type is buried -_LC1_C36 = LCELL( _EQ978); - _EQ978 = _LC2_C19 & _LC4_C36 & _LC8_C27 - # !_LC2_C19 & _LC4_C36 & !_LC8_C27 - # !_LC2_C19 & !_LC4_C36 & _LC8_C27 - # _LC2_C19 & !_LC4_C36 & !_LC8_C27; - --- Node name is '|video2:SVIDEO|:632' from file "video2.tdf" line 391, column 10 --- Equation name is '_LC6_B26', type is buried -_LC6_B26 = DFFE( _EQ979, _LC1_B21, VCC, VCC, VCC); - _EQ979 = _LC1_B16 & _LC2_B8 & _LC3_B34; - --- Node name is '|video2:SVIDEO|:634' from file "video2.tdf" line 394, column 9 --- Equation name is '_LC3_F19', type is buried -_LC3_F19 = DFFE( _EQ980, _LC6_A29, VCC, VCC, VCC); - _EQ980 = !_LC2_B26 - # !_LC7_D35 - # !_LC1_D22 - # !_LC2_D22; - --- Node name is '|video2:SVIDEO|:642' from file "video2.tdf" line 501, column 29 --- Equation name is '_LC5_B34', type is buried -_LC5_B34 = DFFE( _EQ981, GLOBAL( TG42), VCC, VCC, VCC); - _EQ981 = !_LC5_A29 & !_LC6_A29 & !_LC7_A29; - --- Node name is '|video2:SVIDEO|:643' from file "video2.tdf" line 501, column 80 --- Equation name is '_LC6_B30', type is buried -_LC6_B30 = DFFE( _EQ982, GLOBAL( TG42), VCC, VCC, VCC); - _EQ982 = !_LC3_E28 & !_LC5_A29 & !_LC7_A29; - --- Node name is '|video2:SVIDEO|:644' from file "video2.tdf" line 523, column 26 --- Equation name is '_LC1_B1', type is buried -_LC1_B1 = DFFE( _LC1_F35, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|:645' from file "video2.tdf" line 523, column 8 --- Equation name is '_LC3_F20', type is buried -_LC3_F20 = DFFE( _LC1_F20, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is '|video2:SVIDEO|:647' from file "video2.tdf" line 539, column 20 --- Equation name is '_LC4_B19', type is buried -_LC4_B19 = LCELL( _LC8_B19); - --- Node name is '|video2:SVIDEO|:654' from file "video2.tdf" line 586, column 5 --- Equation name is '_LC7_B33', type is buried -_LC7_B33 = DFFE( _EQ983, _LC4_B21, VCC, VCC, VCC); - _EQ983 = _LC2_B4 & _LC4_A9 & _LC5_B19 & _LC7_B27; - --- Node name is '|video2:SVIDEO|:655' from file "video2.tdf" line 600, column 8 --- Equation name is '_LC1_B34', type is buried -_LC1_B34 = DFFE( _EQ984, _LC1_B21, VCC, VCC, VCC); - _EQ984 = _LC4_A9 - # _LC5_B19; - --- Node name is '|video2:SVIDEO|~944~1' from file "video2.tdf" line 310, column 11 --- Equation name is '_LC5_A36', type is buried --- synthesized logic cell -!_LC5_A36 = _LC5_A36~NOT; -_LC5_A36~NOT = LCELL( _EQ985); - _EQ985 = !_LC4_A30 - # _LC3_A30 - # !_LC2_A30; - --- Node name is '|video2:SVIDEO|:944' from file "video2.tdf" line 310, column 11 --- Equation name is '_LC7_A36', type is buried -_LC7_A36 = LCELL( _EQ986); - _EQ986 = !_LC8_A30 - # !_LC6_A30 - # !_LC5_A36 - # !_LC1_A30; - --- Node name is '|video2:SVIDEO|:951' from file "video2.tdf" line 313, column 17 --- Equation name is '_LC1_A30_CARRY', type is buried --- |video2:SVIDEO|:951 is in Up/Down Counter Mode -_LC1_A30_CARRY = CARRY( _EQ987); - _EQ987 = _LC1_A30 & _LC8_A30; - --- Node name is '|video2:SVIDEO|:955' from file "video2.tdf" line 313, column 17 --- Equation name is '_LC2_A30_CARRY', type is buried --- |video2:SVIDEO|:955 is in Clearable Counter Mode -_LC2_A30_CARRY = CARRY( _EQ988); - _EQ988 = _LC1_A30_CARRY & _LC2_A30; - --- Node name is '|video2:SVIDEO|:959' from file "video2.tdf" line 313, column 17 --- Equation name is '_LC3_A30_CARRY', type is buried --- |video2:SVIDEO|:959 is in Clearable Counter Mode -_LC3_A30_CARRY = CARRY( _EQ989); - _EQ989 = _LC2_A30_CARRY & _LC3_A30; - --- Node name is '|video2:SVIDEO|:963' from file "video2.tdf" line 313, column 17 --- Equation name is '_LC4_A30_CARRY', type is buried --- |video2:SVIDEO|:963 is in Up/Down Counter Mode -_LC4_A30_CARRY = CARRY( _EQ990); - _EQ990 = _LC3_A30_CARRY & _LC4_A30; - --- Node name is '|video2:SVIDEO|:973' from file "video2.tdf" line 313, column 9 --- Equation name is '_LC5_A30_CARRY', type is buried -!_LC5_A30_CARRY = _LC5_A30_CARRY~NOT; -_LC5_A30_CARRY~NOT = CARRY( _EQ991); - _EQ991 = _LC4_A30_CARRY & _LC6_A30 - # !_LC4_A30_CARRY & !_LC6_A30 - # !_LC7_A36; - --- Node name is '|video2:SVIDEO|~988~1' from file "video2.tdf" line 316, column 11 --- Equation name is '_LC3_D31', type is buried --- synthesized logic cell -!_LC3_D31 = _LC3_D31~NOT; -_LC3_D31~NOT = LCELL( _EQ992); - _EQ992 = !_LC5_D22 - # !_LC2_D22 - # !_LC1_D22 - # !_LC7_D35; - --- Node name is '|video2:SVIDEO|~988~2' from file "video2.tdf" line 316, column 11 --- Equation name is '_LC1_D31', type is buried --- synthesized logic cell -!_LC1_D31 = _LC1_D31~NOT; -_LC1_D31~NOT = LCELL( _EQ993); - _EQ993 = !_LC3_D31 - # !_LC8_D22 - # _LC7_D22 - # _LC6_D22; - --- Node name is '|video2:SVIDEO|:988' from file "video2.tdf" line 316, column 11 --- Equation name is '_LC4_D31', type is buried -_LC4_D31 = LCELL( _EQ994); - _EQ994 = !_LC1_D31 - # !_LC4_D22 - # !_LC3_D22; - --- Node name is '|video2:SVIDEO|:995' from file "video2.tdf" line 319, column 17 --- Equation name is '_LC1_D22_CARRY', type is buried --- |video2:SVIDEO|:995 is in Up/Down Counter Mode -_LC1_D22_CARRY = CARRY( _EQ995); - _EQ995 = _LC1_D22 & _LC7_D35; - --- Node name is '|video2:SVIDEO|:999' from file "video2.tdf" line 319, column 17 --- Equation name is '_LC2_D22_CARRY', type is buried --- |video2:SVIDEO|:999 is in Clearable Counter Mode -_LC2_D22_CARRY = CARRY( _EQ996); - _EQ996 = _LC1_D22_CARRY & _LC2_D22; - --- Node name is '|video2:SVIDEO|:1003' from file "video2.tdf" line 319, column 17 --- Equation name is '_LC3_D22_CARRY', type is buried --- |video2:SVIDEO|:1003 is in Clearable Counter Mode -_LC3_D22_CARRY = CARRY( _EQ997); - _EQ997 = _LC2_D22_CARRY & _LC3_D22; - --- Node name is '|video2:SVIDEO|:1007' from file "video2.tdf" line 319, column 17 --- Equation name is '_LC4_D22_CARRY', type is buried --- |video2:SVIDEO|:1007 is in Clearable Counter Mode -_LC4_D22_CARRY = CARRY( _EQ998); - _EQ998 = _LC3_D22_CARRY & _LC4_D22; - --- Node name is '|video2:SVIDEO|:1011' from file "video2.tdf" line 319, column 17 --- Equation name is '_LC5_D22_CARRY', type is buried --- |video2:SVIDEO|:1011 is in Up/Down Counter Mode -_LC5_D22_CARRY = CARRY( _EQ999); - _EQ999 = _LC4_D22_CARRY & _LC5_D22; - --- Node name is '|video2:SVIDEO|:1015' from file "video2.tdf" line 319, column 17 --- Equation name is '_LC6_D22_CARRY', type is buried --- |video2:SVIDEO|:1015 is in Clearable Counter Mode -_LC6_D22_CARRY = CARRY( _EQ1000); - _EQ1000= _LC5_D22_CARRY & _LC6_D22; - --- Node name is '|video2:SVIDEO|:1019' from file "video2.tdf" line 319, column 17 --- Equation name is '_LC7_D22_CARRY', type is buried --- |video2:SVIDEO|:1019 is in Clearable Counter Mode -_LC7_D22_CARRY = CARRY( _EQ1001); - _EQ1001= _LC6_D22_CARRY & _LC7_D22; - --- Node name is '|video2:SVIDEO|:1039' from file "video2.tdf" line 323, column 16 --- Equation name is '_LC1_B30_CARRY', type is buried --- |video2:SVIDEO|:1039 is in Up/Down Counter Mode -_LC1_B30_CARRY = CARRY( _EQ1002); - _EQ1002= _LC1_B30 & _LC8_B30; - --- Node name is '|video2:SVIDEO|:1043' from file "video2.tdf" line 323, column 16 --- Equation name is '_LC2_B30_CARRY', type is buried --- |video2:SVIDEO|:1043 is in Up/Down Counter Mode -_LC2_B30_CARRY = CARRY( _EQ1003); - _EQ1003= _LC1_B30_CARRY & _LC2_B30; - --- Node name is '|video2:SVIDEO|:1047' from file "video2.tdf" line 323, column 16 --- Equation name is '_LC3_B30_CARRY', type is buried --- |video2:SVIDEO|:1047 is in Up/Down Counter Mode -_LC3_B30_CARRY = CARRY( _EQ1004); - _EQ1004= _LC2_B30_CARRY & _LC3_B30; - --- Node name is '|video2:SVIDEO|:1049' from file "video2.tdf" line 323, column 16 --- Equation name is '_LC4_B30_CARRY', type is buried --- |video2:SVIDEO|:1049 is in Up/Down Counter Mode -_LC4_B30_CARRY = CARRY( _EQ1005); - _EQ1005= !_LC3_B30_CARRY & _LC5_B30 - # _LC3_B30_CARRY & !_LC5_B30; - --- Node name is '|video2:SVIDEO|:1219' from file "video2.tdf" line 409, column 3 --- Equation name is '_LC2_F1', type is buried -!_LC2_F1 = _LC2_F1~NOT; -_LC2_F1~NOT = LCELL( _EQ1006); - _EQ1006= !_LC3_F1 & !_LC5_F35; - --- Node name is '|video2:SVIDEO|~1408~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC2_F30', type is buried --- synthesized logic cell -!_LC2_F30 = _LC2_F30~NOT; -_LC2_F30~NOT = LCELL( _EQ1007C); - _EQ1007C = _EQ1007; - _EQ1007= _LC5_F35 - # !_LC1_F30 & _LC3_F1 - # !_LC3_F1 & !_LC8_B23 - # !_LC1_F30 & !_LC8_B23; - --- Node name is '|video2:SVIDEO|:1408' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC3_F30', type is buried -!_LC3_F30 = _LC3_F30~NOT; -_LC3_F30~NOT = LCELL( _EQ1008C); - _EQ1008C = _EQ1008 & CASCADE( _EQ1007C); - _EQ1008= !_LC5_F35 - # !_LC3_D22 & _LC3_F1 - # !_LC3_F1 & !_LC7_C17 - # !_LC3_D22 & !_LC7_C17; - --- Node name is '|video2:SVIDEO|~1411~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC4_F30', type is buried --- synthesized logic cell -!_LC4_F30 = _LC4_F30~NOT; -_LC4_F30~NOT = LCELL( _EQ1009C); - _EQ1009C = _EQ1009; - _EQ1009= _LC5_F35 - # _LC3_F1 & !_LC6_F30 - # !_LC3_F1 & !_LC4_B30 - # !_LC4_B30 & !_LC6_F30; - --- Node name is '|video2:SVIDEO|:1411' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC5_F30', type is buried -!_LC5_F30 = _LC5_F30~NOT; -_LC5_F30~NOT = LCELL( _EQ1010C); - _EQ1010C = _EQ1010 & CASCADE( _EQ1009C); - _EQ1010= !_LC5_F35 - # _LC3_F1 & !_LC4_D22 - # !_LC3_C16 & !_LC3_F1 - # !_LC3_C16 & !_LC4_D22; - --- Node name is '|video2:SVIDEO|~1414~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC7_F30', type is buried --- synthesized logic cell -!_LC7_F30 = _LC7_F30~NOT; -_LC7_F30~NOT = LCELL( _EQ1011C); - _EQ1011C = _EQ1011; - _EQ1011= _LC5_F35 - # _LC3_F1 & !_LC8_F25 - # !_LC3_F1 & !_LC7_B30 - # !_LC7_B30 & !_LC8_F25; - --- Node name is '|video2:SVIDEO|:1414' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC8_F30', type is buried -!_LC8_F30 = _LC8_F30~NOT; -_LC8_F30~NOT = LCELL( _EQ1012C); - _EQ1012C = _EQ1012 & CASCADE( _EQ1011C); - _EQ1012= !_LC5_F35 - # _LC3_F1 & !_LC5_D22 - # !_LC3_F1 & !_LC6_C16 - # !_LC5_D22 & !_LC6_C16; - --- Node name is '|video2:SVIDEO|~1417~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC6_F14', type is buried --- synthesized logic cell -_LC6_F14 = LCELL( _EQ1013); - _EQ1013= !_LC3_F1 & _LC4_C11 & _LC5_F35 - # _LC3_F1 & !_LC5_F35 & _LC7_F14; - --- Node name is '|video2:SVIDEO|:1417' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC4_F7', type is buried -_LC4_F7 = LCELL( _EQ1014); - _EQ1014= _LC6_F14 - # !_LC3_F1 & !_LC5_F35 - # _LC3_F1 & _LC5_F35 & _LC6_D22; - --- Node name is '|video2:SVIDEO|~1420~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC8_B13', type is buried --- synthesized logic cell -_LC8_B13 = LCELL( _EQ1015); - _EQ1015= !_LC3_F1 & _LC5_C17 & _LC5_F35 - # _LC3_F1 & _LC5_B13 & !_LC5_F35; - --- Node name is '|video2:SVIDEO|:1420' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC2_B9', type is buried -_LC2_B9 = LCELL( _EQ1016); - _EQ1016= _LC8_B13 - # !_LC3_F1 & !_LC5_F35 - # _LC3_F1 & _LC5_F35 & _LC7_D22; - --- Node name is '|video2:SVIDEO|~1423~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC3_A11', type is buried --- synthesized logic cell -_LC3_A11 = LCELL( _EQ1017); - _EQ1017= !_LC3_F1 & _LC5_C11 & _LC5_F35 - # _LC3_F1 & _LC5_A11 & !_LC5_F35; - --- Node name is '|video2:SVIDEO|:1423' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC1_A11', type is buried -_LC1_A11 = LCELL( _EQ1018); - _EQ1018= _LC3_A11 - # !_LC3_F1 & !_LC5_F35 - # _LC3_F1 & _LC5_F35 & _LC8_D22; - --- Node name is '|video2:SVIDEO|:1425' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC1_B13', type is buried -_LC1_B13 = LCELL( _EQ1019); - _EQ1019= !_LC3_F1 & !_LC5_F35 - # _LC3_F1 & _LC5_F35 - # _LC2_B13 & !_LC5_F35 - # !_LC3_F1 & _LC7_C11; - --- Node name is '|video2:SVIDEO|:1427' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC1_B15', type is buried -_LC1_B15 = LCELL( _EQ1020); - _EQ1020= !_LC3_F1 & !_LC5_F35 - # _LC3_F1 & _LC5_F35 - # !_LC5_F35 & _LC8_B15 - # !_LC3_F1 & _LC6_C10; - --- Node name is '|video2:SVIDEO|~1430~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC5_F20', type is buried --- synthesized logic cell -!_LC5_F20 = _LC5_F20~NOT; -_LC5_F20~NOT = LCELL( _EQ1021C); - _EQ1021C = _EQ1021; - _EQ1021= _LC5_F35 - # _LC3_F1 & !_LC8_F21 - # !_LC3_B29 & !_LC3_F1 - # !_LC3_B29 & !_LC8_F21; - --- Node name is '|video2:SVIDEO|:1430' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC6_F20', type is buried -!_LC6_F20 = _LC6_F20~NOT; -_LC6_F20~NOT = LCELL( _EQ1022C); - _EQ1022C = _EQ1022 & CASCADE( _EQ1021C); - _EQ1022= !_LC5_F35 - # _LC3_F1 & !_LC6_A29 - # !_LC3_F1 & !_LC8_C17 - # !_LC6_A29 & !_LC8_C17; - --- Node name is '|video2:SVIDEO|~1433~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC7_F12', type is buried --- synthesized logic cell -!_LC7_F12 = _LC7_F12~NOT; -_LC7_F12~NOT = LCELL( _EQ1023C); - _EQ1023C = _EQ1023; - _EQ1023= _LC5_F35 - # _LC3_F1 & !_LC4_F25 - # !_LC3_F1 & !_LC5_B21 - # !_LC4_F25 & !_LC5_B21; - --- Node name is '|video2:SVIDEO|:1433' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC8_F12', type is buried -!_LC8_F12 = _LC8_F12~NOT; -_LC8_F12~NOT = LCELL( _EQ1024C); - _EQ1024C = _EQ1024 & CASCADE( _EQ1023C); - _EQ1024= !_LC5_F35 - # !_LC1_A30 & _LC3_F1 - # !_LC3_F1 & !_LC7_C16 - # !_LC1_A30 & !_LC7_C16; - --- Node name is '|video2:SVIDEO|~1436~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC4_F12', type is buried --- synthesized logic cell -!_LC4_F12 = _LC4_F12~NOT; -_LC4_F12~NOT = LCELL( _EQ1025C); - _EQ1025C = _EQ1025; - _EQ1025= _LC5_F35 - # _LC3_F1 & !_LC3_F14 - # !_LC3_F1 & !_LC4_B33 - # !_LC3_F14 & !_LC4_B33; - --- Node name is '|video2:SVIDEO|:1436' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC5_F12', type is buried -!_LC5_F12 = _LC5_F12~NOT; -_LC5_F12~NOT = LCELL( _EQ1026C); - _EQ1026C = _EQ1026 & CASCADE( _EQ1025C); - _EQ1026= !_LC5_F35 - # _LC3_F1 & !_LC8_A30 - # !_LC3_C5 & !_LC3_F1 - # !_LC3_C5 & !_LC8_A30; - --- Node name is '|video2:SVIDEO|~1439~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC3_B9', type is buried --- synthesized logic cell -!_LC3_B9 = _LC3_B9~NOT; -_LC3_B9~NOT = LCELL( _EQ1027C); - _EQ1027C = _EQ1027; - _EQ1027= _LC5_F35 - # _LC3_F1 & !_LC6_B9 - # !_LC3_F1 & !_LC6_B29 - # !_LC6_B9 & !_LC6_B29; - --- Node name is '|video2:SVIDEO|:1439' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC4_B9', type is buried -!_LC4_B9 = _LC4_B9~NOT; -_LC4_B9~NOT = LCELL( _EQ1028C); - _EQ1028C = _EQ1028 & CASCADE( _EQ1027C); - _EQ1028= !_LC5_F35 - # !_LC2_A30 & _LC3_F1 - # !_LC3_F1 & !_LC8_C16 - # !_LC2_A30 & !_LC8_C16; - --- Node name is '|video2:SVIDEO|~1442~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC2_B19', type is buried --- synthesized logic cell -!_LC2_B19 = _LC2_B19~NOT; -_LC2_B19~NOT = LCELL( _EQ1029C); - _EQ1029C = _EQ1029; - _EQ1029= _LC5_F35 - # !_LC3_B11 & _LC3_F1 - # !_LC2_B29 & !_LC3_F1 - # !_LC2_B29 & !_LC3_B11; - --- Node name is '|video2:SVIDEO|:1442' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC3_B19', type is buried -!_LC3_B19 = _LC3_B19~NOT; -_LC3_B19~NOT = LCELL( _EQ1030C); - _EQ1030C = _EQ1030 & CASCADE( _EQ1029C); - _EQ1030= !_LC5_F35 - # !_LC3_A30 & _LC3_F1 - # !_LC2_C2 & !_LC3_F1 - # !_LC2_C2 & !_LC3_A30; - --- Node name is '|video2:SVIDEO|~1445~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC4_A15', type is buried --- synthesized logic cell -!_LC4_A15 = _LC4_A15~NOT; -_LC4_A15~NOT = LCELL( _EQ1031C); - _EQ1031C = _EQ1031; - _EQ1031= _LC5_F35 - # _LC3_F1 & !_LC7_A15 - # !_LC3_F1 & !_LC8_B21 - # !_LC7_A15 & !_LC8_B21; - --- Node name is '|video2:SVIDEO|:1445' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC5_A15', type is buried -!_LC5_A15 = _LC5_A15~NOT; -_LC5_A15~NOT = LCELL( _EQ1032C); - _EQ1032C = _EQ1032 & CASCADE( _EQ1031C); - _EQ1032= !_LC5_F35 - # _LC3_F1 & !_LC4_A30 - # !_LC3_F1 & !_LC8_A34 - # !_LC4_A30 & !_LC8_A34; - --- Node name is '|video2:SVIDEO|~1448~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC5_B20', type is buried --- synthesized logic cell -!_LC5_B20 = _LC5_B20~NOT; -_LC5_B20~NOT = LCELL( _EQ1033C); - _EQ1033C = _EQ1033; - _EQ1033= _LC5_F35 - # _LC3_F1 & !_LC5_B9 - # !_LC3_B33 & !_LC3_F1 - # !_LC3_B33 & !_LC5_B9; - --- Node name is '|video2:SVIDEO|:1448' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC6_B20', type is buried -!_LC6_B20 = _LC6_B20~NOT; -_LC6_B20~NOT = LCELL( _EQ1034C); - _EQ1034C = _EQ1034 & CASCADE( _EQ1033C); - _EQ1034= !_LC5_F35 - # _LC3_F1 & !_LC6_A30 - # !_LC3_C17 & !_LC3_F1 - # !_LC3_C17 & !_LC6_A30; - --- Node name is '|video2:SVIDEO|~1451~1' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC2_F21', type is buried --- synthesized logic cell -!_LC2_F21 = _LC2_F21~NOT; -_LC2_F21~NOT = LCELL( _EQ1035C); - _EQ1035C = _EQ1035; - _EQ1035= _LC5_F35 - # !_LC1_B29 & !_LC3_F1 - # !_LC1_B29 & !_LC8_A15 - # _LC3_F1 & !_LC8_A15; - --- Node name is '|video2:SVIDEO|:1451' from file "video2.tdf" line 437, column 13 --- Equation name is '_LC3_F21', type is buried -!_LC3_F21 = _LC3_F21~NOT; -_LC3_F21~NOT = LCELL( _EQ1036C); - _EQ1036C = _EQ1036 & CASCADE( _EQ1035C); - _EQ1036= !_LC5_F35 - # _LC3_F1 & !RGMOD0 - # !_LC3_F1 & !_LC7_B1 - # !_LC7_B1 & !RGMOD0; - --- Node name is '|video2:SVIDEO|~1461~1' from file "video2.tdf" line 438, column 38 --- Equation name is '_LC6_B19', type is buried --- synthesized logic cell -_LC6_B19 = LCELL( _EQ1037); - _EQ1037= !_LC7_A29 - # _LC5_B19 & !_LC6_A29; - --- Node name is '|video2:SVIDEO|~1847~1' from file "video2.tdf" line 611, column 32 --- Equation name is '_LC7_B26', type is buried --- synthesized logic cell -_LC7_B26 = LCELL( _EQ1038); - _EQ1038= _LC5_B30 & !_LC6_B26; - --- Node name is '|video2:SVIDEO|~2007~1' from file "video2.tdf" line 308, column 43 --- Equation name is '_LC6_A36', type is buried --- synthesized logic cell -_LC6_A36 = LCELL( _EQ1039); - _EQ1039= _LC7_A29 & _LC7_F1; - --- Node name is '|video2:SVIDEO|~2007~2' from file "video2.tdf" line 308, column 43 --- Equation name is '_LC8_A36', type is buried --- synthesized logic cell -_LC8_A36 = LCELL( _EQ1040); - _EQ1040= !_LC2_A30 & !_LC3_A30 & _LC4_A30 & _LC6_A30; - --- Node name is '|video2:SVIDEO|~2007~3' from file "video2.tdf" line 308, column 43 --- Equation name is '_LC1_A36', type is buried --- synthesized logic cell -_LC1_A36 = LCELL( _EQ1041); - _EQ1041= _LC3_E28 & _LC5_A29 & !_LC8_A30 & _LC8_A36; - --- Node name is '|video2:SVIDEO|~2016~1' from file "video2.tdf" line 307, column 37 --- Equation name is '_LC3_A34', type is buried --- synthesized logic cell -_LC3_A34 = LCELL( _EQ1042); - _EQ1042= _LC7_A29 & _LC7_F1; - --- Node name is '~GND~' --- Equation name is '~GND~', location is LC8_E14, type is buried. --- synthesized logic cell -_LC8_E14 = LCELL( GND); - --- Node name is '/IORD' from file "sp2_acex.tdf" line 311, column 11 --- Equation name is '/IORD', location is LC7_C25, type is buried. -!/IORD = /IORD~NOT; -/IORD~NOT = DFFE(!/rd, GLOBAL( TG42), GLOBAL(!/io), VCC, VCC); - --- Node name is '/IOWR' from file "sp2_acex.tdf" line 310, column 11 --- Equation name is '/IOWR', location is LC5_C9, type is buried. -!/IOWR = /IOWR~NOT; -/IOWR~NOT = DFFE(!/wr, GLOBAL( TG42), GLOBAL(!/io), VCC, VCC); - --- Node name is '/reset' from file "sp2_acex.tdf" line 296, column 2 --- Equation name is '/reset', type is bidir -/reset = OPNDRN(_LC4_C28); - --- Node name is '/rf~1' from file "sp2_acex.tdf" line 32, column 2 --- Equation name is '/rf~1', location is LC5_D31, type is buried. --- synthesized logic cell -!_LC5_D31 = _LC5_D31~NOT; -_LC5_D31~NOT = LCELL(!/rf); - --- Node name is '/SYS' from file "sp2_acex.tdf" line 571, column 9 --- Equation name is '/SYS', location is LC6_C26, type is buried. -/SYS = DFFE(!A6, /IOWR, /reset, VCC, SYS_ENA2); - --- Node name is '/wait' from file "sp2_acex.tdf" line 908, column 2 --- Equation name is '/wait', type is bidir -/wait = TRI(/WAIT_ALL, _LC1_C28); - --- Node name is '/WAIT_ALL' from file "sp2_acex.tdf" line 904, column 40 --- Equation name is '/WAIT_ALL', location is LC3_C34, type is buried. -!/WAIT_ALL = /WAIT_ALL~NOT; -/WAIT_ALL~NOT = LCELL( _EQ1043); - _EQ1043= !WAIT_ORIG - # !_LC4_C34 - # _LC1_C34; - --- Node name is '/WAIT_ALL~1' from file "sp2_acex.tdf" line 904, column 40 --- Equation name is '/WAIT_ALL~1', location is LC1_C34, type is buried. --- synthesized logic cell -_LC1_C34 = LCELL( _EQ1044); - _EQ1044= !_LC5_C34 - # !_LC8_B18 & !WAIT_ROMX; - --- Node name is '/WE' from file "sp2_acex.tdf" line 878, column 2 --- Equation name is '/WE', type is output -/WE = _LC1_C18; - --- Node name is '/WE_OUT' from file "sp2_acex.tdf" line 883, column 12 --- Equation name is '/WE_OUT', location is LC8_C18, type is buried. -/WE_OUT = LCELL( _EQ1045); - _EQ1045= BLK_MR - # _LC5_C1 - # !_LC8_C3 - # blk_mem; - --- Node name is ':862' from file "sp2_acex.tdf" line 254, column 2 --- Equation name is '_LC1_F9', type is buried -!_LC1_F9 = _LC1_F9~NOT; -_LC1_F9~NOT = DFFE( _EQ1046, !_LC2_F9, _LC4_F9, VCC, VCC); - _EQ1046= !A14 & !A15 & ROM_RG4; - --- Node name is ':1332' from file "sp2_acex.tdf" line 296, column 20 --- Equation name is '_LC4_C28', type is buried -_LC4_C28 = DFFE( _EQ1047, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1047= _LC4_E34 & !SOFT_RES0 & !SOFT_RES1; - --- Node name is ':1335' from file "sp2_acex.tdf" line 314, column 17 --- Equation name is '_LC2_F28', type is buried -_LC2_F28 = DFFE( _EQ1048, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1048= !_LC4_D26 & !_LC5_D34 & !_LC7_D19 & _LC8_F28; - --- Node name is ':1336' from file "sp2_acex.tdf" line 323, column 17 --- Equation name is '_LC4_A34', type is buried -_LC4_A34 = LCELL( _EQ1049); - _EQ1049= ALL_MODE0 & ALL_MODE3; - --- Node name is ':1341' from file "sp2_acex.tdf" line 373, column 15 --- Equation name is '_LC8_D9', type is buried -_LC8_D9 = LCELL( _EQ1050); - _EQ1050= /rd & /wr - # _LC4_D3 & /wr; - --- Node name is ':1342' from file "sp2_acex.tdf" line 376, column 7 --- Equation name is '_LC1_D9', type is buried -_LC1_D9 = DFFE( /wr, _LC6_F32, VCC, VCC, VCC); - --- Node name is ':1343' from file "sp2_acex.tdf" line 393, column 81 --- Equation name is '_LC5_A26', type is buried -_LC5_A26 = LCELL( _EQ1051); - _EQ1051= CBL_XX7 & _LC8_D22; - --- Node name is ':1344' from file "sp2_acex.tdf" line 393, column 18 --- Equation name is '_LC3_A31', type is buried -_LC3_A31 = LCELL( _EQ1052); - _EQ1052= !CBL_XX7 & _LC7_B12 - # CBL_CNT7 & !CBL_WA7 & CBL_XX7 - # !CBL_CNT7 & CBL_WA7 & CBL_XX7; - --- Node name is ':1345' from file "sp2_acex.tdf" line 413, column 21 --- Equation name is '_LC5_C25', type is buried -_LC5_C25 = LCELL( _EQ1053); - _EQ1053= !_LC1_D34 & !_LC3_D20 & !_LC4_D34 & !_LC5_D34 - # !_LC1_D34 & _LC3_D20 & !_LC4_D34 & _LC5_D34; - --- Node name is ':1404' from file "sp2_acex.tdf" line 531, column 13 --- Equation name is '_LC2_B3', type is buried -_LC2_B3 = DFFE( _EQ1054, GLOBAL( TG42), VCC, VCC, _LC7_F1); - _EQ1054= _LC3_E28 - # !KEY_IO; - --- Node name is ':1406' from file "sp2_acex.tdf" line 559, column 34 --- Equation name is '_LC3_C30', type is buried -_LC3_C30 = DFFE( _EQ1055, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1055= _LC1_D34 & _LC3_D20 & _LC4_D34 & _LC5_D34; - --- Node name is ':1408' from file "sp2_acex.tdf" line 564, column 7 --- Equation name is '_LC3_C33', type is buried -_LC3_C33 = LCELL( _EQ1056); - _EQ1056= A15 & !_LC7_D31 - # _LC6_D24 - # !A14; - --- Node name is ':1409' from file "sp2_acex.tdf" line 567, column 20 --- Equation name is '_LC6_C13', type is buried -_LC6_C13 = DFFE( _LC3_C13, _LC2_F9, /reset, VCC, VCC); - --- Node name is ':1410' from file "sp2_acex.tdf" line 567, column 24 --- Equation name is '_LC3_C13', type is buried -_LC3_C13 = DFFE( _EQ1057, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1057= _LC1_C9 & _LC4_C13; - --- Node name is ':1411' from file "sp2_acex.tdf" line 567, column 29 --- Equation name is '_LC1_C9', type is buried -_LC1_C9 = LCELL( _EQ1058); - _EQ1058= A14 & A15 & _LC3_D12; - --- Node name is ':1412' from file "sp2_acex.tdf" line 568, column 9 --- Equation name is '_LC4_C13', type is buried -_LC4_C13 = LCELL( _EQ1059); - _EQ1059= !_EC1_C & !_EC7_C & _EC10_C & _EC12_C; - --- Node name is ':1415' from file "sp2_acex.tdf" line 577, column 23 --- Equation name is '_LC3_F28', type is buried -_LC3_F28 = DFFE( _EQ1060, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1060= _LC1_D26 & _LC4_F28 & _LC5_F28 & !_LC7_D19; - --- Node name is ':1417' from file "sp2_acex.tdf" line 582, column 34 --- Equation name is '_LC1_C29', type is buried -_LC1_C29 = DFFE( _EQ1061, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1061= a1 & a5 & A6 & _LC7_C29; - --- Node name is ':1419' from file "sp2_acex.tdf" line 586, column 20 --- Equation name is '_LC2_C9', type is buried -_LC2_C9 = LCELL( _EQ1062); - _EQ1062= ISA_PORT4 & !ISA_PORT5 & ISA_PORT6 & ISA_PORT7; - --- Node name is ':1423' from file "sp2_acex.tdf" line 593, column 27 --- Equation name is '_LC8_B18', type is buried -_LC8_B18 = DFFE( _EQ1063, GLOBAL( TG42), !WAIT_ROMX, VCC, VCC); - _EQ1063= !WT_R0 & !WT_R1 & !WT_R2; - --- Node name is ':1425' from file "sp2_acex.tdf" line 603, column 40 --- Equation name is '_LC1_C33', type is buried -_LC1_C33 = LCELL( _EQ1064); - _EQ1064= !/mr - # CS_ISA; - --- Node name is ':1427' from file "sp2_acex.tdf" line 604, column 54 --- Equation name is '_LC2_C33', type is buried -_LC2_C33 = LCELL( _EQ1065); - _EQ1065= CS_ROMT - # !/mr; - --- Node name is ':1429' from file "sp2_acex.tdf" line 605, column 54 --- Equation name is '_LC4_C23', type is buried -_LC4_C23 = LCELL( _EQ1066); - _EQ1066= !/mr - # CS_CASHT; - --- Node name is ':1431' from file "sp2_acex.tdf" line 642, column 17 --- Equation name is '_LC5_F23', type is buried -_LC5_F23 = DFFE( _EQ1067, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1067= _LC1_D26 & _LC7_D19 & _LC7_F23 & _LC8_F23; - --- Node name is ':1432' from file "sp2_acex.tdf" line 643, column 16 --- Equation name is '_LC5_C29', type is buried -_LC5_C29 = DFFE( _EQ1068, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1068= !a5 & A6 & !A7 & _LC6_C29; - --- Node name is ':1433' from file "sp2_acex.tdf" line 727, column 30 --- Equation name is '_LC2_C1', type is buried -_LC2_C1 = LCELL( _LC4_C1); - --- Node name is ':1434' from file "sp2_acex.tdf" line 727, column 36 --- Equation name is '_LC4_C1', type is buried -_LC4_C1 = DFFE( _LC8_C21, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is ':1435' from file "sp2_acex.tdf" line 749, column 12 --- Equation name is '_LC7_A22', type is buried -!_LC7_A22 = _LC7_A22~NOT; -_LC7_A22~NOT = DFFE( VCC, _LC2_A22, _LC4_A22, VCC, VCC); - --- Node name is ':1436' from file "sp2_acex.tdf" line 749, column 62 --- Equation name is '_LC6_A22', type is buried -_LC6_A22 = DFFE( _LC8_A22, _LC2_A30, VCC, VCC, VCC); - --- Node name is ':1437' from file "sp2_acex.tdf" line 749, column 66 --- Equation name is '_LC8_A22', type is buried -_LC8_A22 = DFFE(!INT_X, _LC2_A30, VCC, VCC, VCC); - --- Node name is '~1442~1' from file "sp2_acex.tdf" line 775, column 10 --- Equation name is '~1442~1', location is LC6_D28, type is buried. --- synthesized logic cell -!_LC6_D28 = _LC6_D28~NOT; -_LC6_D28~NOT = LCELL(!_IOC_7); - --- Node name is ':1458' from file "sp2_acex.tdf" line 819, column 32 --- Equation name is '_LC3_F27', type is buried -_LC3_F27 = DFFE( SINC_1M, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is ':1460' from file "sp2_acex.tdf" line 820, column 32 --- Equation name is '_LC4_F19', type is buried -_LC4_F19 = DFFE( SINC_2M, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is ':1464' from file "sp2_acex.tdf" line 829, column 15 --- Equation name is '_LC4_F31', type is buried -_LC4_F31 = DFFE( _EQ1069, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1069= _LC1_D26 & _LC5_F31 & _LC6_F31 & !_LC7_D19; - --- Node name is ':1475' from file "sp2_acex.tdf" line 878, column 9 --- Equation name is '_LC1_C18', type is buried -!_LC1_C18 = _LC1_C18~NOT; -_LC1_C18~NOT = DFFE( _EQ1070, GLOBAL( TG42), /reset, VCC, VCC); - _EQ1070= !_LC6_F32 & !/WE_OUT; - --- Node name is ':1478' from file "sp2_acex.tdf" line 908, column 26 --- Equation name is '_LC1_C28', type is buried -_LC1_C28 = LCELL(!/WAIT_ALL); - --- Node name is ':1480' from file "sp2_acex.tdf" line 960, column 16 --- Equation name is '_LC6_F28', type is buried -_LC6_F28 = DFFE( _EQ1071, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1071= _LC1_F28 & _LC4_D26 & !_LC5_D34 & _LC7_D19; - --- Node name is ':1484' from file "sp2_acex.tdf" line 992, column 15 --- Equation name is '_LC2_C18', type is buried -!_LC2_C18 = _LC2_C18~NOT; -_LC2_C18~NOT = DFFE( _EQ1072, GLOBAL(!TG42), /reset, VCC, VCC); - _EQ1072= !glisser & !_LC5_C1 & !_LC7_F32; - --- Node name is ':1485' from file "sp2_acex.tdf" line 1014, column 39 --- Equation name is '_LC7_C31', type is buried -_LC7_C31 = LCELL( _EQ1073); - _EQ1073= !A13 & !_LC7_C19 & _LC8_C31 - # !_LC7_C19 & _LC8_C19 & _LC8_C31; - --- Node name is ':1486' from file "sp2_acex.tdf" line 1044, column 23 --- Equation name is '_LC2_F31', type is buried -_LC2_F31 = DFFE( _EQ1074, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1074= _LC1_D26 & !_LC7_D19 & _LC7_F31 & _LC8_F31; - --- Node name is ':1487' from file "sp2_acex.tdf" line 1052, column 13 --- Equation name is '_LC6_A1', type is buried -_LC6_A1 = DFFE( _LC8_A3, !_LC3_E28, VCC, VCC, VCC); - --- Node name is ':1488' from file "sp2_acex.tdf" line 1052, column 18 --- Equation name is '_LC8_A3', type is buried -_LC8_A3 = DFFE( AUDIO_R15, _LC3_E28, VCC, VCC, VCC); - --- Node name is ':1489' from file "sp2_acex.tdf" line 1057, column 12 --- Equation name is '_LC1_E3', type is buried -_LC1_E3 = DFFE( _LC8_A30, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is ':1490' from file "sp2_acex.tdf" line 1058, column 13 --- Equation name is '_LC1_A3', type is buried -_LC1_A3 = DFFE( _LC3_E28, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is ':1494' from file "sp2_acex.tdf" line 1081, column 17 --- Equation name is '_LC1_F23', type is buried -_LC1_F23 = DFFE( _EQ1075, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1075= !_LC1_D26 & _LC2_F23 & _LC3_F23 & !_LC7_D19; - --- Node name is ':1495' from file "sp2_acex.tdf" line 1114, column 19 --- Equation name is '_LC1_C31', type is buried -_LC1_C31 = LCELL(!_LC2_E30); - --- Node name is ':1496' from file "sp2_acex.tdf" line 1126, column 12 --- Equation name is '_LC4_C8', type is buried -_LC4_C8 = DFFE( _EQ1076, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1076= !_LC1_D26 & _LC2_C30 & _LC2_C32 & !_LC7_D19; - --- Node name is ':1497' from file "sp2_acex.tdf" line 1127, column 6 --- Equation name is '_LC3_C8', type is buried -_LC3_C8 = DFFE( _EQ1077, GLOBAL( TG42), _LC6_A10, VCC, VCC); - _EQ1077= _EC10_C & _EC12_C & _LC7_C8 & _LC8_C8; - --- Node name is ':1498' from file "sp2_acex.tdf" line 1128, column 7 --- Equation name is '_LC5_C18', type is buried -!_LC5_C18 = _LC5_C18~NOT; -_LC5_C18~NOT = DFFE( _EQ1078, GLOBAL( TG42), /reset, VCC, VCC); - _EQ1078= !_LC5_C1 & !_LC7_F32; - --- Node name is '~1499~1' from file "sp2_acex.tdf" line 1131, column 27 --- Equation name is '~1499~1', location is LC6_A5, type is buried. --- synthesized logic cell -!_LC6_A5 = _LC6_A5~NOT; -_LC6_A5~NOT = LCELL( _LC5_C8); - --- Node name is ':1499' from file "sp2_acex.tdf" line 1131, column 27 --- Equation name is '_LC5_C8', type is buried -!_LC5_C8 = _LC5_C8~NOT; -_LC5_C8~NOT = DFFE( CBL_WAE, !CBL_WR, CBL_INT, VCC, VCC); - --- Node name is ':1500' from file "sp2_acex.tdf" line 1159, column 35 --- Equation name is '_LC8_A25', type is buried -_LC8_A25 = LCELL( _EQ1079); - _EQ1079= CBL_CNT0 & !CBL_XX6 - # AUDIO_CH & CBL_XX6; - --- Node name is ':1501' from file "sp2_acex.tdf" line 1163, column 16 --- Equation name is '_LC6_A14', type is buried -_LC6_A14 = DFFE( _EQ1080, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1080= !/IOWR & _LC4_C8 - # _LC1_C8 - # CBL_XX7; - --- Node name is ':1502' from file "sp2_acex.tdf" line 1180, column 17 --- Equation name is '_LC2_F24', type is buried -_LC2_F24 = DFFE( _EQ1081, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1081= _LC7_D27 - # /wr - # !_LC1_F31; - --- Node name is ':1503' from file "sp2_acex.tdf" line 1180, column 46 --- Equation name is '_LC1_F31', type is buried -_LC1_F31 = DFFE( _EQ1082, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1082= !_LC1_D26 & _LC3_F31 & _LC6_F34 & !_LC7_D19; - --- Node name is ':1504' from file "sp2_acex.tdf" line 1181, column 17 --- Equation name is '_LC5_F3', type is buried -_LC5_F3 = DFFE( _EQ1083, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1083= _LC7_D27 - # /wr - # !_LC4_F23; - --- Node name is ':1505' from file "sp2_acex.tdf" line 1181, column 46 --- Equation name is '_LC4_F23', type is buried -_LC4_F23 = DFFE( _EQ1084, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1084= !_LC1_D26 & _LC5_F34 & _LC6_F23 & !_LC7_D19; - --- Node name is ':1506' from file "sp2_acex.tdf" line 1195, column 18 --- Equation name is '_LC4_A36', type is buried -_LC4_A36 = DFFE( _EQ1085, GLOBAL( TG42), VCC, VCC, VCC); - _EQ1085= _LC1_A30 & _LC8_A30 - # !_LC6_A29 & _LC8_A30; - --- Node name is ':1508' from file "sp2_acex.tdf" line 1212, column 12 --- Equation name is '_LC5_A30', type is buried -_LC5_A30 = DFFE( _LC6_A30, GLOBAL( TG42), VCC, VCC, VCC); - --- Node name is ':1561' from file "sp2_acex.tdf" line 366, column 23 --- Equation name is '_LC4_D11', type is buried -_LC4_D11 = LCELL( _EQ1086); - _EQ1086= !_EC6_C & !_LC5_C14 & md0 - # !_EC6_C & !_LC1_C14 & md0; - --- Node name is ':1563' from file "sp2_acex.tdf" line 366, column 23 --- Equation name is '_LC3_D11', type is buried -_LC3_D11 = LCELL( _EQ1087); - _EQ1087= !_EC6_C & !_LC5_C14 & md1 - # !_EC6_C & !_LC1_C14 & md1; - --- Node name is ':1565' from file "sp2_acex.tdf" line 366, column 23 --- Equation name is '_LC3_D15', type is buried -_LC3_D15 = LCELL( _EQ1088); - _EQ1088= !_EC6_C & !_LC5_C14 & md2 - # !_EC6_C & !_LC1_C14 & md2; - --- Node name is ':1567' from file "sp2_acex.tdf" line 366, column 23 --- Equation name is '_LC8_D15', type is buried -_LC8_D15 = LCELL( _EQ1089); - _EQ1089= !_EC6_C & !_LC5_C14 & md3 - # !_EC6_C & !_LC1_C14 & md3; - --- Node name is ':1569' from file "sp2_acex.tdf" line 366, column 23 --- Equation name is '_LC1_D4', type is buried -_LC1_D4 = LCELL( _EQ1090); - _EQ1090= !_EC6_C & !_LC5_C14 & md4 - # !_EC6_C & !_LC1_C14 & md4; - --- Node name is ':1571' from file "sp2_acex.tdf" line 366, column 23 --- Equation name is '_LC2_D15', type is buried -_LC2_D15 = LCELL( _EQ1091); - _EQ1091= !_EC6_C & !_LC5_C14 & md5 - # !_EC6_C & !_LC1_C14 & md5; - --- Node name is ':1573' from file "sp2_acex.tdf" line 366, column 23 --- Equation name is '_LC1_D14', type is buried -_LC1_D14 = LCELL( _EQ1092); - _EQ1092= !_EC6_C & !_LC5_C14 & md6 - # !_EC6_C & !_LC1_C14 & md6; - --- Node name is ':1575' from file "sp2_acex.tdf" line 366, column 23 --- Equation name is '_LC2_D4', type is buried -_LC2_D4 = LCELL( _EQ1093); - _EQ1093= !_EC6_C & !_LC5_C14 & md7 - # !_EC6_C & !_LC1_C14 & md7; - --- Node name is ':1579' from file "sp2_acex.tdf" line 367, column 23 --- Equation name is '_LC7_D11', type is buried -_LC7_D11 = LCELL( _EQ1094); - _EQ1094= !_EC6_C & hddr0 & _LC1_C14 & _LC5_C14; - --- Node name is ':1582' from file "sp2_acex.tdf" line 367, column 23 --- Equation name is '_LC8_D11', type is buried -_LC8_D11 = LCELL( _EQ1095); - _EQ1095= !_EC6_C & hddr1 & _LC1_C14 & _LC5_C14; - --- Node name is ':1585' from file "sp2_acex.tdf" line 367, column 23 --- Equation name is '_LC5_D15', type is buried -_LC5_D15 = LCELL( _EQ1096); - _EQ1096= !_EC6_C & hddr2 & _LC1_C14 & _LC5_C14; - --- Node name is ':1588' from file "sp2_acex.tdf" line 367, column 23 --- Equation name is '_LC4_D15', type is buried -_LC4_D15 = LCELL( _EQ1097); - _EQ1097= !_EC6_C & hddr3 & _LC1_C14 & _LC5_C14; - --- Node name is ':1591' from file "sp2_acex.tdf" line 367, column 23 --- Equation name is '_LC6_D4', type is buried -_LC6_D4 = LCELL( _EQ1098); - _EQ1098= !_EC6_C & hddr4 & _LC1_C14 & _LC5_C14; - --- Node name is ':1594' from file "sp2_acex.tdf" line 367, column 23 --- Equation name is '_LC2_D11', type is buried -_LC2_D11 = LCELL( _EQ1099); - _EQ1099= !_EC6_C & hddr5 & _LC1_C14 & _LC5_C14; - --- Node name is ':1597' from file "sp2_acex.tdf" line 367, column 23 --- Equation name is '_LC4_D14', type is buried -_LC4_D14 = LCELL( _EQ1100); - _EQ1100= !_EC6_C & hddr6 & _LC1_C14 & _LC5_C14; - --- Node name is ':1600' from file "sp2_acex.tdf" line 367, column 23 --- Equation name is '_LC8_D4', type is buried -_LC8_D4 = LCELL( _EQ1101); - _EQ1101= !_EC6_C & hddr7 & _LC1_C14 & _LC5_C14; - --- Node name is ':1619' from file "sp2_acex.tdf" line 374, column 32 --- Equation name is '_LC8_D14', type is buried -_LC8_D14 = LCELL( _EQ1102); - _EQ1102= _LC5_C14 & !_LC7_D27; - --- Node name is '~1789~1' from file "sp2_acex.tdf" line 404, column 23 --- Equation name is '~1789~1', location is LC5_D26, type is buried. --- synthesized logic cell -_LC5_D26 = LCELL( _EQ1103); - _EQ1103= !_EC9_C & KEY/KEMS0 - # !_EC3_C & !_EC9_C - # _EC3_C & _EC9_C & MDP0; - --- Node name is '~1791~1' from file "sp2_acex.tdf" line 404, column 23 --- Equation name is '~1791~1', location is LC2_D36, type is buried. --- synthesized logic cell -_LC2_D36 = LCELL( _EQ1104); - _EQ1104= !_EC9_C & KEY/KEMS1 - # !_EC3_C & !_EC9_C - # _EC3_C & _EC9_C & MDP1; - --- Node name is '~1793~1' from file "sp2_acex.tdf" line 404, column 23 --- Equation name is '~1793~1', location is LC4_D23, type is buried. --- synthesized logic cell -_LC4_D23 = LCELL( _EQ1105); - _EQ1105= !_EC9_C & KEY/KEMS2 - # !_EC3_C & !_EC9_C - # _EC3_C & _EC9_C & MDP2; - --- Node name is '~1795~1' from file "sp2_acex.tdf" line 404, column 23 --- Equation name is '~1795~1', location is LC2_D32, type is buried. --- synthesized logic cell -_LC2_D32 = LCELL( _EQ1106); - _EQ1106= !_EC9_C & KEY/KEMS3 - # !_EC3_C & !_EC9_C - # _EC3_C & _EC9_C & MDP3; - --- Node name is '~1797~1' from file "sp2_acex.tdf" line 404, column 23 --- Equation name is '~1797~1', location is LC3_D32, type is buried. --- synthesized logic cell -_LC3_D32 = LCELL( _EQ1107); - _EQ1107= !_EC9_C & KEY/KEMS4 - # !_EC3_C & !_EC9_C - # _EC3_C & _EC9_C & MDP4; - --- Node name is '~1799~1' from file "sp2_acex.tdf" line 404, column 23 --- Equation name is '~1799~1', location is LC4_A26, type is buried. --- synthesized logic cell -_LC4_A26 = LCELL( _EQ1108); - _EQ1108= !_EC9_C & KEY/KEMS5 - # !_EC3_C & !_EC9_C - # _EC3_C & _EC9_C & MDP5; - --- Node name is '~1801~1' from file "sp2_acex.tdf" line 404, column 23 --- Equation name is '~1801~1', location is LC4_D29, type is buried. --- synthesized logic cell -_LC4_D29 = LCELL( _EQ1109); - _EQ1109= !_EC9_C & KEY/KEMS6 - # !_EC3_C & !_EC9_C - # _EC3_C & _EC9_C & MDP6; - --- Node name is '~1803~1' from file "sp2_acex.tdf" line 404, column 23 --- Equation name is '~1803~1', location is LC6_A31, type is buried. --- synthesized logic cell -_LC6_A31 = LCELL( _EQ1110); - _EQ1110= !_EC9_C & KEY/KEMS7 - # !_EC3_C & !_EC9_C - # _EC3_C & _EC9_C & MDP7; - --- Node name is ':1884' from file "sp2_acex.tdf" line 559, column 32 --- Equation name is '_LC6_C30', type is buried -_LC6_C30 = LCELL( _EQ1111); - _EQ1111= _LC3_C30 & _LC3_D12; - --- Node name is ':1967' from file "sp2_acex.tdf" line 609, column 30 --- Equation name is '_LC2_C26', type is buried -_LC2_C26 = LCELL( _EQ1112); - _EQ1112= CS_CASHT & CS_ISA & !_LC3_F28 - # CS_CASHT & CS_ISA & /IOWR; - --- Node name is ':1973' from file "sp2_acex.tdf" line 618, column 37 --- Equation name is '_LC5_F26', type is buried -_LC5_F26 = LCELL( _EQ1113); - _EQ1113= ROM_RG3 & SYS_PG - # !ROM_RG3 & !SYS_PG; - --- Node name is ':2013' from file "sp2_acex.tdf" line 626, column 19 --- Equation name is '_LC4_F9', type is buried -_LC4_F9 = LCELL( _EQ1114); - _EQ1114= _LC1_F9 - # !/mr & ROM_RG4; - --- Node name is ':2015' from file "sp2_acex.tdf" line 634, column 25 --- Equation name is '_LC6_C25', type is buried -!_LC6_C25 = _LC6_C25~NOT; -_LC6_C25~NOT = LCELL( _EQ1115); - _EQ1115= !blk_mem & !/mr & !/rd; - --- Node name is ':2020' from file "sp2_acex.tdf" line 642, column 48 --- Equation name is '_LC8_C29', type is buried -_LC8_C29 = LCELL( _EQ1116); - _EQ1116= _LC5_F23 - # _LC5_C29 & !/SYS; - --- Node name is '~2028~1' from file "sp2_acex.tdf" line 723, column 32 --- Equation name is '~2028~1', location is LC4_A31, type is buried. --- synthesized logic cell -_LC4_A31 = LCELL( _EQ1117); - _EQ1117= !_EC9_C - # _LC7_D27 - # !_EC6_C; - --- Node name is ':2028' from file "sp2_acex.tdf" line 723, column 32 --- Equation name is '_LC5_A31', type is buried -_LC5_A31 = LCELL( _EQ1118); - _EQ1118= _LC4_A31 - # !_EC3_C - # _EC11_C - # /rd; - --- Node name is ':2043' from file "sp2_acex.tdf" line 807, column 48 --- Equation name is '_LC2_F36', type is buried -_LC2_F36 = LCELL( _EQ1119); - _EQ1119= SINC_HOLD0 & !SINC_HOLD1 - # !SINC_HOLD0 & SINC_HOLD1; - --- Node name is ':2047' from file "sp2_acex.tdf" line 807, column 48 --- Equation name is '_LC3_F36', type is buried -_LC3_F36 = LCELL( _EQ1120); - _EQ1120= !SINC_HOLD0 & SINC_HOLD2 - # !SINC_HOLD1 & SINC_HOLD2 - # SINC_HOLD0 & SINC_HOLD1 & !SINC_HOLD2; - --- Node name is ':2051' from file "sp2_acex.tdf" line 807, column 48 --- Equation name is '_LC4_F36', type is buried -_LC4_F36 = LCELL( _EQ1121); - _EQ1121= !SINC_HOLD0 & SINC_HOLD3 - # !SINC_HOLD1 & SINC_HOLD3 - # !SINC_HOLD2 & SINC_HOLD3 - # SINC_HOLD0 & SINC_HOLD1 & SINC_HOLD2 & !SINC_HOLD3; - --- Node name is ':2082' from file "sp2_acex.tdf" line 816, column 48 --- Equation name is '_LC7_F22', type is buried -_LC7_F22 = LCELL( _EQ1122); - _EQ1122= !SINC_HOLD4 & SINC_HOLD5 - # SINC_HOLD4 & !SINC_HOLD5; - --- Node name is ':2084' from file "sp2_acex.tdf" line 816, column 48 --- Equation name is '_LC1_F22_CARRY', type is buried --- :2084 is in Up/Down Counter Mode -_LC1_F22_CARRY = CARRY( _EQ1123); - _EQ1123= SINC_HOLD4 & SINC_HOLD5; - --- Node name is ':2088' from file "sp2_acex.tdf" line 816, column 48 --- Equation name is '_LC2_F22_CARRY', type is buried --- :2088 is in Up/Down Counter Mode -_LC2_F22_CARRY = CARRY( _EQ1124); - _EQ1124= _LC1_F22_CARRY & SINC_HOLD6; - --- Node name is ':2092' from file "sp2_acex.tdf" line 816, column 48 --- Equation name is '_LC3_F22_CARRY', type is buried --- :2092 is in Up/Down Counter Mode -_LC3_F22_CARRY = CARRY( _EQ1125); - _EQ1125= _LC2_F22_CARRY & SINC_HOLD7; - --- Node name is ':2094' from file "sp2_acex.tdf" line 816, column 48 --- Equation name is '_LC4_F22_CARRY', type is buried -_LC4_F22_CARRY = CARRY( _EQ1126); - _EQ1126= !_LC3_F22_CARRY & SINC_HOLD8 - # _LC3_F22_CARRY & !SINC_HOLD8; - --- Node name is '~2130~1' from file "sp2_acex.tdf" line 841, column 38 --- Equation name is '~2130~1', location is LC8_C10, type is buried. --- synthesized logic cell -_LC8_C10 = LCELL( _EQ1127); - _EQ1127= A10 & a11 & A12 & A13; - --- Node name is ':2130' from file "sp2_acex.tdf" line 841, column 38 --- Equation name is '_LC7_C10', type is buried -_LC7_C10 = LCELL( _EQ1128); - _EQ1128= A8 & !a9 & _LC6_D13 & _LC8_C10; - --- Node name is ':2139' from file "sp2_acex.tdf" line 1061, column 28 --- Equation name is '_LC1_A35', type is buried -_LC1_A35 = LCELL( _EQ1129); - _EQ1129= _LC2_E14 & !_LC3_E28; - --- Node name is ':2356' from file "sp2_acex.tdf" line 1111, column 27 --- Equation name is '_LC3_E30', type is buried -_LC3_E30 = LCELL( _EQ1130); - _EQ1130= CBL_CTX0 - # CBL_CTX1; - --- Node name is ':2361' from file "sp2_acex.tdf" line 1111, column 27 --- Equation name is '_LC4_E30', type is buried -_LC4_E30 = LCELL( _EQ1131); - _EQ1131= CBL_CTX0 - # CBL_CTX1 - # CBL_CTX2; - --- Node name is ':2366' from file "sp2_acex.tdf" line 1111, column 27 --- Equation name is '_LC5_E30', type is buried -_LC5_E30 = LCELL( _EQ1132); - _EQ1132= CBL_CTX0 - # CBL_CTX1 - # CBL_CTX2 - # CBL_CTX3; - --- Node name is ':2398' from file "sp2_acex.tdf" line 1116, column 3 --- Equation name is '_LC6_A34', type is buried -!_LC6_A34 = _LC6_A34~NOT; -_LC6_A34~NOT = LCELL( _EQ1133); - _EQ1133= !CBL_XX6 & _LC1_C31; - --- Node name is '~2405~1' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '~2405~1', location is LC5_A19, type is buried. --- synthesized logic cell -_LC5_A19 = LCELL( _LC4_A19_CARRY); - --- Node name is ':2405' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '_LC4_A19_CARRY', type is buried --- :2405 is in Up/Down Counter Mode -_LC4_A19_CARRY = CARRY( _EQ1134); - _EQ1134= CBL_CNT0 & CBL_CNT1; - --- Node name is '~2409~1' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '~2409~1', location is LC6_A19_CARRY, type is buried. --- synthesized logic cell -_LC6_A19_CARRY = CARRY( _LC5_A19_CARRY); - --- Node name is '~2409~2' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '~2409~2', location is LC6_A19, type is buried. --- synthesized logic cell -_LC6_A19 = LCELL( _LC5_A19_CARRY); - --- Node name is ':2409' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '_LC5_A19_CARRY', type is buried -_LC5_A19_CARRY = CARRY( _EQ1135); - _EQ1135= CBL_CNT2 & _LC4_A19_CARRY; - --- Node name is '~2413~1' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '~2413~1', location is LC8_A19, type is buried. --- synthesized logic cell -_LC8_A19 = LCELL( _LC7_A19_CARRY); - --- Node name is ':2413' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '_LC7_A19_CARRY', type is buried --- :2413 is in Up/Down Counter Mode -_LC7_A19_CARRY = CARRY( _EQ1136); - _EQ1136= CBL_CNT3 & _LC6_A19_CARRY; - --- Node name is '~2417~1' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '~2417~1', location is LC1_A21, type is buried. --- synthesized logic cell -_LC1_A21 = LCELL( _LC8_A19_CARRY); - --- Node name is ':2417' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '_LC8_A19_CARRY', type is buried -_LC8_A19_CARRY = CARRY( _EQ1137); - _EQ1137= CBL_CNT4 & _LC7_A19_CARRY; - --- Node name is '~2421~1' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '~2421~1', location is LC2_A21_CARRY, type is buried. --- synthesized logic cell -_LC2_A21_CARRY = CARRY( _LC1_A21_CARRY); - --- Node name is '~2421~2' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '~2421~2', location is LC2_A21, type is buried. --- synthesized logic cell -_LC2_A21 = LCELL( _LC1_A21_CARRY); - --- Node name is ':2421' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '_LC1_A21_CARRY', type is buried -_LC1_A21_CARRY = CARRY( _EQ1138); - _EQ1138= CBL_CNT5 & _LC8_A19_CARRY; - --- Node name is ':2425' from file "sp2_acex.tdf" line 1116, column 36 --- Equation name is '_LC3_A21_CARRY', type is buried --- :2425 is in Up/Down Counter Mode -_LC3_A21_CARRY = CARRY( _EQ1139); - _EQ1139= CBL_CNT6 & _LC2_A21_CARRY; - --- Node name is ':2440' from file "sp2_acex.tdf" line 1116, column 25 --- Equation name is '_LC1_A19', type is buried -_LC1_A19 = LCELL( _EQ1140); - _EQ1140= CBL_CNT3 & !CBL_XX6 & _LC1_C31 & !_LC6_A19 - # !CBL_CNT3 & !CBL_XX6 & _LC1_C31 & _LC6_A19; - --- Node name is ':2449' from file "sp2_acex.tdf" line 1116, column 25 --- Equation name is '_LC7_A21', type is buried -_LC7_A21 = LCELL( _EQ1141); - _EQ1141= CBL_CNT6 & !CBL_XX6 & _LC1_C31 & !_LC2_A21 - # !CBL_CNT6 & !CBL_XX6 & _LC1_C31 & _LC2_A21; - --- Node name is ':2456' from file "sp2_acex.tdf" line 1117, column 3 --- Equation name is '_LC8_A28', type is buried -!_LC8_A28 = _LC8_A28~NOT; -_LC8_A28~NOT = LCELL( _EQ1142); - _EQ1142= CBL_XX6 & _LC1_C31; - --- Node name is ':2465' from file "sp2_acex.tdf" line 1117, column 36 --- Equation name is '_LC1_A24_CARRY', type is buried --- :2465 is in Up/Down Counter Mode -_LC1_A24_CARRY = CARRY( _EQ1143); - _EQ1143= CBL_CNT1 & CBL_CNT2; - --- Node name is ':2469' from file "sp2_acex.tdf" line 1117, column 36 --- Equation name is '_LC2_A24_CARRY', type is buried -_LC2_A24_CARRY = CARRY( _EQ1144); - _EQ1144= CBL_CNT3 & _LC1_A24_CARRY; - --- Node name is ':2473' from file "sp2_acex.tdf" line 1117, column 36 --- Equation name is '_LC3_A24_CARRY', type is buried --- :2473 is in Up/Down Counter Mode -_LC3_A24_CARRY = CARRY( _EQ1145); - _EQ1145= CBL_CNT4 & _LC2_A24_CARRY; - --- Node name is ':2477' from file "sp2_acex.tdf" line 1117, column 36 --- Equation name is '_LC4_A24_CARRY', type is buried --- :2477 is in Up/Down Counter Mode -_LC4_A24_CARRY = CARRY( _EQ1146); - _EQ1146= CBL_CNT5 & _LC3_A24_CARRY; - --- Node name is ':2481' from file "sp2_acex.tdf" line 1117, column 36 --- Equation name is '_LC5_A24_CARRY', type is buried -_LC5_A24_CARRY = CARRY( _EQ1147); - _EQ1147= CBL_CNT6 & _LC4_A24_CARRY; - --- Node name is '~2487~1' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '~2487~1', location is LC3_A28, type is buried. --- synthesized logic cell -_LC3_A28 = LCELL( _EQ1148); - _EQ1148= CBL_XX6 - # !_LC1_C31; - --- Node name is ':2493' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '_LC7_A24', type is buried -_LC7_A24 = LCELL( _EQ1149); - _EQ1149= CBL_CNT1 & !CBL_CNT2 & CBL_XX6 & _LC1_C31 - # !CBL_CNT1 & CBL_CNT2 & CBL_XX6 & _LC1_C31; - --- Node name is '~2494~1' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '~2494~1', location is LC7_A25, type is buried. --- synthesized logic cell -!_LC7_A25 = _LC7_A25~NOT; -_LC7_A25~NOT = LCELL( _EQ1150); - _EQ1150= !CBL_CNT2 & !_LC5_A19 - # !CBL_CNT2 & CBL_XX6 - # CBL_XX6 & _LC1_C31 - # !CBL_CNT2 & !_LC1_C31 - # CBL_CNT2 & _LC1_C31 & _LC5_A19; - --- Node name is ':2496' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '_LC2_A24', type is buried -_LC2_A24 = LCELL( _EQ1151); - _EQ1151= CBL_CNT3 & !_LC1_A24_CARRY & !_LC8_A28 - # !CBL_CNT3 & _LC1_A24_CARRY & !_LC8_A28; - --- Node name is '~2497~1' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '~2497~1', location is LC2_A19, type is buried. --- synthesized logic cell -!_LC2_A19 = _LC2_A19~NOT; -_LC2_A19~NOT = LCELL( _EQ1152); - _EQ1152= !CBL_CNT3 & !_LC2_A24 - # _LC1_C31 & !_LC2_A24; - --- Node name is '~2500~1' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '~2500~1', location is LC4_A33, type is buried. --- synthesized logic cell -!_LC4_A33 = _LC4_A33~NOT; -_LC4_A33~NOT = LCELL( _EQ1153); - _EQ1153= !CBL_CNT4 & !_LC8_A19 - # !CBL_CNT4 & CBL_XX6 - # CBL_XX6 & _LC1_C31 - # !CBL_CNT4 & !_LC1_C31 - # CBL_CNT4 & _LC1_C31 & _LC8_A19; - --- Node name is '~2503~1' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '~2503~1', location is LC6_A21, type is buried. --- synthesized logic cell -!_LC6_A21 = _LC6_A21~NOT; -_LC6_A21~NOT = LCELL( _EQ1154); - _EQ1154= !CBL_CNT5 & !_LC1_A21 - # !CBL_CNT5 & CBL_XX6 - # CBL_XX6 & _LC1_C31 - # !CBL_CNT5 & !_LC1_C31 - # CBL_CNT5 & _LC1_A21 & _LC1_C31; - --- Node name is ':2505' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '_LC5_A24', type is buried -_LC5_A24 = LCELL( _EQ1155); - _EQ1155= CBL_CNT6 & !_LC4_A24_CARRY & !_LC8_A28 - # !CBL_CNT6 & _LC4_A24_CARRY & !_LC8_A28; - --- Node name is '~2506~1' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '~2506~1', location is LC5_A21, type is buried. --- synthesized logic cell -!_LC5_A21 = _LC5_A21~NOT; -_LC5_A21~NOT = LCELL( _EQ1156); - _EQ1156= !CBL_CNT6 & !_LC5_A24 - # _LC1_C31 & !_LC5_A24; - --- Node name is '~2509~1' from file "sp2_acex.tdf" line 1117, column 25 --- Equation name is '~2509~1', location is LC4_A21, type is buried. --- synthesized logic cell -_LC4_A21 = LCELL( _EQ1157); - _EQ1157= CBL_CNT7 & !_LC1_C31 - # CBL_CNT7 & !CBL_XX6 & !_LC3_A21_CARRY - # !CBL_CNT7 & !CBL_XX6 & _LC1_C31 & _LC3_A21_CARRY; - --- Node name is ':2514' from file "sp2_acex.tdf" line 1127, column 82 --- Equation name is '_LC1_C8', type is buried -!_LC1_C8 = _LC1_C8~NOT; -_LC1_C8~NOT = LCELL( _EQ1158); - _EQ1158= _LC5_C18 - # !_LC3_C8; - --- Node name is '~2536~1' from file "sp2_acex.tdf" line 1136, column 42 --- Equation name is '~2536~1', location is LC2_A26, type is buried. --- synthesized logic cell -_LC2_A26 = LCELL( _EQ1159); - _EQ1159= CBL_XX4 & CBL_XX7; - --- Node name is ':2539' from file "sp2_acex.tdf" line 1139, column 45 --- Equation name is '_LC6_A33', type is buried -_LC6_A33 = LCELL( _EQ1160); - _EQ1160= CBL_INT & CBL_XX4 & CBL_XX7; - --- Node name is ':2546' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC1_A32_CARRY', type is buried -_LC1_A32_CARRY = CARRY( _EQ1161); - _EQ1161= CBL_WA0 & CBL_WA1; - --- Node name is ':2548' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC2_A32', type is buried -_LC2_A32 = LCELL( _EQ1162); - _EQ1162= CBL_WA2 & !_LC1_A32_CARRY - # !CBL_WA2 & _LC1_A32_CARRY; - --- Node name is ':2550' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC2_A32_CARRY', type is buried -_LC2_A32_CARRY = CARRY( _EQ1163); - _EQ1163= CBL_WA2 & _LC1_A32_CARRY; - --- Node name is ':2552' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC3_A32', type is buried -_LC3_A32 = LCELL( _EQ1164); - _EQ1164= CBL_WA3 & !_LC2_A32_CARRY - # !CBL_WA3 & _LC2_A32_CARRY; - --- Node name is ':2554' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC3_A32_CARRY', type is buried -_LC3_A32_CARRY = CARRY( _EQ1165); - _EQ1165= CBL_WA3 & _LC2_A32_CARRY; - --- Node name is ':2556' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC4_A32', type is buried -_LC4_A32 = LCELL( _EQ1166); - _EQ1166= CBL_WA4 & !_LC3_A32_CARRY - # !CBL_WA4 & _LC3_A32_CARRY; - --- Node name is ':2558' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC4_A32_CARRY', type is buried -_LC4_A32_CARRY = CARRY( _EQ1167); - _EQ1167= CBL_WA4 & _LC3_A32_CARRY; - --- Node name is ':2560' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC5_A32', type is buried -_LC5_A32 = LCELL( _EQ1168); - _EQ1168= CBL_WA5 & !_LC4_A32_CARRY - # !CBL_WA5 & _LC4_A32_CARRY; - --- Node name is ':2562' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC5_A32_CARRY', type is buried -_LC5_A32_CARRY = CARRY( _EQ1169); - _EQ1169= CBL_WA5 & _LC4_A32_CARRY; - --- Node name is ':2564' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC6_A32', type is buried -_LC6_A32 = LCELL( _EQ1170); - _EQ1170= CBL_WA6 & !_LC5_A32_CARRY - # !CBL_WA6 & _LC5_A32_CARRY; - --- Node name is ':2566' from file "sp2_acex.tdf" line 1141, column 25 --- Equation name is '_LC6_A32_CARRY', type is buried -_LC6_A32_CARRY = CARRY( _EQ1171); - _EQ1171= CBL_WA6 & _LC5_A32_CARRY; - --- Node name is ':2580' from file "sp2_acex.tdf" line 1149, column 23 --- Equation name is '_LC3_A14', type is buried -_LC3_A14 = LCELL( _EQ1172); - _EQ1172= !CBL_WAE & !/IOWR & _LC4_C8 - # !CBL_WAE & _LC1_C8; - --- Node name is ':2581' from file "sp2_acex.tdf" line 1152, column 29 --- Equation name is '_LC1_A14', type is buried -_LC1_A14 = LCELL( _EQ1173); - _EQ1173= !CBL_XX5 & _LC1_D17 - # CBL_XX5 & !_LC1_D17; - --- Node name is ':2606' from file "sp2_acex.tdf" line 1154, column 49 --- Equation name is '_LC3_A29', type is buried -_LC3_A29 = LCELL( _EQ1174); - _EQ1174= !A8 & !CBL_WA0 & !CBL_XX4 - # CBL_WA0 & CBL_XX4 - # A8 & CBL_WA0; - --- Node name is ':2607' from file "sp2_acex.tdf" line 1154, column 49 --- Equation name is '_LC3_A27', type is buried -_LC3_A27 = LCELL( _EQ1175); - _EQ1175= !a9 & !CBL_WA1 & !CBL_XX4 - # CBL_WA1 & CBL_XX4 - # a9 & CBL_WA1; - --- Node name is ':2608' from file "sp2_acex.tdf" line 1154, column 49 --- Equation name is '_LC3_A26', type is buried -_LC3_A26 = LCELL( _EQ1176); - _EQ1176= !A10 & !CBL_WA2 & !CBL_XX4 - # CBL_WA2 & CBL_XX4 - # A10 & CBL_WA2; - --- Node name is ':2609' from file "sp2_acex.tdf" line 1154, column 49 --- Equation name is '_LC2_A27', type is buried -_LC2_A27 = LCELL( _EQ1177); - _EQ1177= !a11 & !CBL_WA3 & !CBL_XX4 - # CBL_WA3 & CBL_XX4 - # a11 & CBL_WA3; - --- Node name is ':2610' from file "sp2_acex.tdf" line 1154, column 49 --- Equation name is '_LC5_A27', type is buried -_LC5_A27 = LCELL( _EQ1178); - _EQ1178= !A12 & !CBL_WA4 & !CBL_XX4 - # CBL_WA4 & CBL_XX4 - # A12 & CBL_WA4; - --- Node name is ':2611' from file "sp2_acex.tdf" line 1154, column 49 --- Equation name is '_LC3_A22', type is buried -_LC3_A22 = LCELL( _EQ1179); - _EQ1179= !A13 & !CBL_WA5 & !CBL_XX4 - # CBL_WA5 & CBL_XX4 - # A13 & CBL_WA5; - --- Node name is ':2612' from file "sp2_acex.tdf" line 1154, column 49 --- Equation name is '_LC7_A26', type is buried -_LC7_A26 = LCELL( _EQ1180); - _EQ1180= !A14 & !CBL_WA6 & !CBL_XX4 - # CBL_WA6 & CBL_XX4 - # A14 & CBL_WA6; - --- Node name is ':2613' from file "sp2_acex.tdf" line 1154, column 49 --- Equation name is '_LC1_A22', type is buried -_LC1_A22 = LCELL( _EQ1181); - _EQ1181= !A15 & !CBL_WA7 & !CBL_XX4 - # CBL_WA7 & CBL_XX4 - # A15 & CBL_WA7; - --- Node name is ':2717' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC3_C2_CARRY', type is buried --- :2717 is in Up/Down Counter Mode -_LC3_C2_CARRY = CARRY( _EQ1182); - _EQ1182= AY_FULL1 & CBL_R6; - --- Node name is ':2736' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC4_C2_CARRY', type is buried -_LC4_C2_CARRY = CARRY( _EQ1183); - _EQ1183= AY_FULL2 & CBL_R7 - # AY_FULL2 & _LC3_C2_CARRY - # CBL_R7 & _LC3_C2_CARRY; - --- Node name is ':2746' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC5_C2_CARRY', type is buried -_LC5_C2_CARRY = CARRY( _EQ1184); - _EQ1184= AY_FULL3 & _LC4_C2_CARRY - # CBL_R8 & _LC4_C2_CARRY - # AY_FULL3 & CBL_R8; - --- Node name is ':2757' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC6_C2_CARRY', type is buried -_LC6_C2_CARRY = CARRY( _EQ1185); - _EQ1185= AY_FULL4 & _LC5_C2_CARRY - # CBL_R9 & _LC5_C2_CARRY - # AY_FULL4 & CBL_R9; - --- Node name is ':2767' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC7_C2_CARRY', type is buried -_LC7_C2_CARRY = CARRY( _EQ1186); - _EQ1186= AY_FULL5 & _LC6_C2_CARRY - # CBL_R10 & _LC6_C2_CARRY - # AY_FULL5 & CBL_R10; - --- Node name is ':2777' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC8_C2_CARRY', type is buried -_LC8_C2_CARRY = CARRY( _EQ1187); - _EQ1187= AY_FULL6 & _LC7_C2_CARRY - # CBL_R11 & _LC7_C2_CARRY - # AY_FULL6 & CBL_R11; - --- Node name is ':2788' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC1_C4_CARRY', type is buried -_LC1_C4_CARRY = CARRY( _EQ1188); - _EQ1188= AY_FULL7 & _LC8_C2_CARRY - # CBL_R12 & _LC8_C2_CARRY - # AY_FULL7 & CBL_R12; - --- Node name is ':2798' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC2_C4_CARRY', type is buried -_LC2_C4_CARRY = CARRY( _EQ1189); - _EQ1189= AY_FULL8 & _LC1_C4_CARRY - # CBL_R13 & _LC1_C4_CARRY - # AY_FULL8 & CBL_R13; - --- Node name is ':2808' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC3_C4_CARRY', type is buried -_LC3_C4_CARRY = CARRY( _EQ1190); - _EQ1190= AY_FULL9 & _LC2_C4_CARRY - # CBL_R14 & _LC2_C4_CARRY - # AY_FULL9 & CBL_R14; - --- Node name is ':2816' from file "sp2_acex.tdf" line 1208, column 34 --- Equation name is '_LC4_C4_CARRY', type is buried -_LC4_C4_CARRY = CARRY( _EQ1191); - _EQ1191= !AY_FULL10 & CBL_R15 & !_LC3_C4_CARRY - # AY_FULL10 & !CBL_R15 & !_LC3_C4_CARRY - # !AY_FULL10 & !CBL_R15 & _LC3_C4_CARRY - # AY_FULL10 & CBL_R15 & _LC3_C4_CARRY; - --- Node name is '~2864~1' from file "sp2_acex.tdf" line 1218, column 22 --- Equation name is '~2864~1', location is LC2_B22, type is buried. --- synthesized logic cell -_LC2_B22 = LCELL( _EQ1192); - _EQ1192= A8 & A10 & !_LC1_B26 - # !A8 & !_LC6_B22; - --- Node name is '~2868~1' from file "sp2_acex.tdf" line 1218, column 22 --- Equation name is '~2868~1', location is LC1_B25, type is buried. --- synthesized logic cell -_LC1_B25 = LCELL( _EQ1193); - _EQ1193= A8 & A10 & !_LC1_B28 - # !A8 & !_LC3_B25; - --- Node name is '~2907~1' from file "sp2_acex.tdf" line 1181, column 58 --- Equation name is '~2907~1', location is LC5_F34, type is buried. --- synthesized logic cell -_LC5_F34 = LCELL( _EQ1194); - _EQ1194= _LC3_D20 & !_LC4_D26 & !_LC5_D34; - --- Node name is '~2907~2' from file "sp2_acex.tdf" line 1181, column 58 --- Equation name is '~2907~2', location is LC6_F23, type is buried. --- synthesized logic cell -_LC6_F23 = LCELL( _EQ1195); - _EQ1195= !_LC1_D33 & !_LC1_D34 & _LC4_D34; - --- Node name is '~2921~1' from file "sp2_acex.tdf" line 1180, column 58 --- Equation name is '~2921~1', location is LC6_F34, type is buried. --- synthesized logic cell -_LC6_F34 = LCELL( _EQ1196); - _EQ1196= _LC3_D20 & _LC4_D26 & !_LC5_D34; - --- Node name is '~2921~2' from file "sp2_acex.tdf" line 1180, column 58 --- Equation name is '~2921~2', location is LC3_F31, type is buried. --- synthesized logic cell -_LC3_F31 = LCELL( _EQ1197); - _EQ1197= !_LC1_D33 & !_LC1_D34 & _LC4_D34; - --- Node name is ':2931' from file "sp2_acex.tdf" line 1127, column 64 --- Equation name is '_LC6_A10', type is buried -_LC6_A10 = LCELL( _EQ1198); - _EQ1198= CBL_XX4 & _LC6_F10; - --- Node name is '~2945~1' from file "sp2_acex.tdf" line 1127, column 29 --- Equation name is '~2945~1', location is LC7_C8, type is buried. --- synthesized logic cell -_LC7_C8 = LCELL( _EQ1199); - _EQ1199= _EC1_C & _EC7_C; - --- Node name is '~2945~2' from file "sp2_acex.tdf" line 1127, column 29 --- Equation name is '~2945~2', location is LC8_C8, type is buried. --- synthesized logic cell -_LC8_C8 = LCELL( _EQ1200); - _EQ1200= _EC2_C & _EC5_C & _EC14_C & !_EC16_C; - --- Node name is '~2955~1' from file "sp2_acex.tdf" line 1126, column 24 --- Equation name is '~2955~1', location is LC2_C30, type is buried. --- synthesized logic cell -_LC2_C30 = LCELL( _EQ1201); - _EQ1201= !_LC3_D20 & !_LC4_D26 & !_LC5_D34; - --- Node name is '~2955~2' from file "sp2_acex.tdf" line 1126, column 24 --- Equation name is '~2955~2', location is LC2_C32, type is buried. --- synthesized logic cell -_LC2_C32 = LCELL( _EQ1202); - _EQ1202= _LC1_D33 & !_LC1_D34 & _LC4_D34; - --- Node name is '~2960~1' from file "sp2_acex.tdf" line 1114, column 35 --- Equation name is '~2960~1', location is LC1_E30, type is buried. --- synthesized logic cell -_LC1_E30 = LCELL( _EQ1203); - _EQ1203= !CBL_CTX0 & !CBL_CTX1 & !CBL_CTX2; - --- Node name is ':2960' from file "sp2_acex.tdf" line 1114, column 35 --- Equation name is '_LC2_E30', type is buried -!_LC2_E30 = _LC2_E30~NOT; -_LC2_E30~NOT = LCELL( _EQ1204); - _EQ1204= !CBL_CTX3 & !CBL_CTX4 & _LC1_E30; - --- Node name is '~2971~1' from file "sp2_acex.tdf" line 1081, column 29 --- Equation name is '~2971~1', location is LC2_F23, type is buried. --- synthesized logic cell -_LC2_F23 = LCELL( _EQ1205); - _EQ1205= !_LC3_D20 & _LC4_D26 & !_LC5_D34; - --- Node name is '~2971~2' from file "sp2_acex.tdf" line 1081, column 29 --- Equation name is '~2971~2', location is LC3_F23, type is buried. --- synthesized logic cell -_LC3_F23 = LCELL( _EQ1206); - _EQ1206= _LC1_D33 & !_LC1_D34 & _LC4_D34; - --- Node name is ':2974' from file "sp2_acex.tdf" line 1078, column 46 --- Equation name is '_LC5_A22', type is buried -_LC5_A22 = LCELL( _EQ1207); - _EQ1207= CBL_XX4 & /io - # CBL_XX4 & /m1; - --- Node name is '~2995~1' from file "sp2_acex.tdf" line 1044, column 35 --- Equation name is '~2995~1', location is LC7_F31, type is buried. --- synthesized logic cell -_LC7_F31 = LCELL( _EQ1208); - _EQ1208= !_LC3_D20 & _LC4_D26 & !_LC5_D34; - --- Node name is '~2995~2' from file "sp2_acex.tdf" line 1044, column 35 --- Equation name is '~2995~2', location is LC8_F31, type is buried. --- synthesized logic cell -_LC8_F31 = LCELL( _EQ1209); - _EQ1209= !_LC1_D33 & _LC1_D34 & _LC4_D34; - --- Node name is '~3026~1' from file "sp2_acex.tdf" line 960, column 28 --- Equation name is '~3026~1', location is LC1_F28, type is buried. --- synthesized logic cell -_LC1_F28 = LCELL( _EQ1210); - _EQ1210= !_LC1_D26 & _LC1_D34 & !_LC3_D20 & _LC4_D34; - --- Node name is ':3056' from file "sp2_acex.tdf" line 842, column 24 --- Equation name is '_LC4_C10', type is buried -!_LC4_C10 = _LC4_C10~NOT; -_LC4_C10~NOT = LCELL( _EQ1211); - _EQ1211= !/mr & !/m1; - --- Node name is '~3069~1' from file "sp2_acex.tdf" line 829, column 27 --- Equation name is '~3069~1', location is LC6_F31, type is buried. --- synthesized logic cell -_LC6_F31 = LCELL( _EQ1212); - _EQ1212= !_LC3_D20 & _LC4_D26 & !_LC5_D34; - --- Node name is '~3069~2' from file "sp2_acex.tdf" line 829, column 27 --- Equation name is '~3069~2', location is LC5_F31, type is buried. --- synthesized logic cell -_LC5_F31 = LCELL( _EQ1213); - _EQ1213= _LC1_D33 & _LC1_D34 & _LC4_D34; - --- Node name is '~3081~1' from file "sp2_acex.tdf" line 810, column 34 --- Equation name is '~3081~1', location is LC6_F22, type is buried. --- synthesized logic cell -_LC6_F22 = LCELL( _EQ1214); - _EQ1214= !SINC_HOLD5 - # !SINC_HOLD6 - # !SINC_HOLD7; - --- Node name is ':3093' from file "sp2_acex.tdf" line 775, column 19 --- Equation name is '_LC1_A29', type is buried -_LC1_A29 = LCELL( _EQ1215); - _EQ1215= _LC3_E28 & !_LC5_A29 - # !_LC3_E28 & _LC5_A29; - --- Node name is ':3101' from file "sp2_acex.tdf" line 764, column 37 --- Equation name is '_LC1_E14', type is buried -!_LC1_E14 = _LC1_E14~NOT; -_LC1_E14~NOT = LCELL( _EQ1216); - _EQ1216= !_LC3_E28 & _LC3_F35 - # !_LC3_E28 & _LC7_F1 - # !_LC3_F35 & _LC7_F1 - # _LC3_E28 & !_LC3_F35; - --- Node name is ':3104' from file "sp2_acex.tdf" line 749, column 60 --- Equation name is '_LC4_A22', type is buried -_LC4_A22 = LCELL( _EQ1217); - _EQ1217= /io & _LC6_A22 - # _LC6_A22 & /m1; - --- Node name is ':3105' from file "sp2_acex.tdf" line 749, column 33 --- Equation name is '_LC2_A22', type is buried -_LC2_A22 = LCELL( _EQ1218); - _EQ1218= _LC3_F19 & _LC4_A27; - --- Node name is '~3117~1' from file "sp2_acex.tdf" line 643, column 29 --- Equation name is '~3117~1', location is LC4_C29, type is buried. --- synthesized logic cell -_LC4_C29 = LCELL( _EQ1219); - _EQ1219= !a0 & a2 & a3; - --- Node name is '~3117~2' from file "sp2_acex.tdf" line 643, column 29 --- Equation name is '~3117~2', location is LC6_C29, type is buried. --- synthesized logic cell -_LC6_C29 = LCELL( _EQ1220); - _EQ1220= !a1 & a4 & _LC4_C29; - --- Node name is '~3130~1' from file "sp2_acex.tdf" line 642, column 29 --- Equation name is '~3130~1', location is LC8_F23, type is buried. --- synthesized logic cell -_LC8_F23 = LCELL( _EQ1221); - _EQ1221= !_LC3_D20 & _LC4_D26 & !_LC5_D34; - --- Node name is '~3130~2' from file "sp2_acex.tdf" line 642, column 29 --- Equation name is '~3130~2', location is LC7_F23, type is buried. --- synthesized logic cell -_LC7_F23 = LCELL( _EQ1222); - _EQ1222= _LC1_D33 & !_LC1_D34 & _LC4_D34; - --- Node name is '~3192~1' from file "sp2_acex.tdf" line 582, column 47 --- Equation name is '~3192~1', location is LC7_C29, type is buried. --- synthesized logic cell -_LC7_C29 = LCELL( _EQ1223); - _EQ1223= a0 & !a2 & a3 & a4; - --- Node name is '~3204~1' from file "sp2_acex.tdf" line 577, column 35 --- Equation name is '~3204~1', location is LC5_F28, type is buried. --- synthesized logic cell -_LC5_F28 = LCELL( _EQ1224); - _EQ1224= _LC3_D20 & _LC4_D26 & !_LC5_D34; - --- Node name is '~3204~2' from file "sp2_acex.tdf" line 577, column 35 --- Equation name is '~3204~2', location is LC4_F28, type is buried. --- synthesized logic cell -_LC4_F28 = LCELL( _EQ1225); - _EQ1225= _LC1_D33 & !_LC1_D34 & !_LC4_D34; - --- Node name is ':3207' from file "sp2_acex.tdf" line 574, column 51 --- Equation name is '_LC4_C27', type is buried -_LC4_C27 = LCELL( _EQ1226); - _EQ1226= !D1 & SYS_ENA2; - --- Node name is ':3210' from file "sp2_acex.tdf" line 568, column 57 --- Equation name is '_LC2_F9', type is buried -_LC2_F9 = LCELL( _EQ1227); - _EQ1227= /mr - # /wr; - --- Node name is '~3248~1' from file "sp2_acex.tdf" line 555, column 26 --- Equation name is '~3248~1', location is LC2_C29, type is buried. --- synthesized logic cell -_LC2_C29 = LCELL( _EQ1228); - _EQ1228= !a0 & a2 & a3 & a4; - --- Node name is ':3252' from file "sp2_acex.tdf" line 530, column 44 --- Equation name is '_LC2_F32', type is buried -_LC2_F32 = LCELL( _EQ1229); - _EQ1229= _LC3_E28 & _LC3_F35; - --- Node name is ':3254' from file "sp2_acex.tdf" line 530, column 22 --- Equation name is '_LC5_D19', type is buried -_LC5_D19 = LCELL( _EQ1230); - _EQ1230= /io - # !/m1; - --- Node name is ':3261' from file "sp2_acex.tdf" line 429, column 39 --- Equation name is '_LC1_C1', type is buried -_LC1_C1 = LCELL( _EQ1231); - _EQ1231= !/WE_OUT - # !/io & _LC2_C1 & !/wr; - --- Node name is '~3321~1' from file "sp2_acex.tdf" line 314, column 29 --- Equation name is '~3321~1', location is LC8_F28, type is buried. --- synthesized logic cell -_LC8_F28 = LCELL( _EQ1232); - _EQ1232= _LC1_D26 & _LC1_D34 & !_LC3_D20 & _LC4_D34; - --- Node name is '|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_0' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC1_D', type is memory -_EC1_D = MEMORY_SEGMENT( _LC3_D8, GLOBAL( TG42), GLOBAL( TG42), _LC3_F3, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_1' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC14_D', type is memory -_EC14_D = MEMORY_SEGMENT( _LC1_D8, GLOBAL( TG42), GLOBAL( TG42), _LC3_F3, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_2' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC2_D', type is memory -_EC2_D = MEMORY_SEGMENT( _LC7_D8, GLOBAL( TG42), GLOBAL( TG42), _LC3_F3, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_3' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC11_D', type is memory -_EC11_D = MEMORY_SEGMENT( _LC8_D8, GLOBAL( TG42), GLOBAL( TG42), _LC3_F3, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_4' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC4_D', type is memory -_EC4_D = MEMORY_SEGMENT( _LC5_D4, GLOBAL( TG42), GLOBAL( TG42), _LC3_F3, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_5' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC10_D', type is memory -_EC10_D = MEMORY_SEGMENT( _LC5_D2, GLOBAL( TG42), GLOBAL( TG42), _LC3_F3, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_6' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC3_D', type is memory -_EC3_D = MEMORY_SEGMENT( _LC6_D2, GLOBAL( TG42), GLOBAL( TG42), _LC3_F3, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_7' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC9_D', type is memory -_EC9_D = MEMORY_SEGMENT( _LC1_D2, GLOBAL( TG42), GLOBAL( TG42), _LC3_F3, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, _LC7_A34, _LC5_C28, _LC6_E19, _LC5_E15, _LC3_A23, _LC4_E15, _LC6_E13, _LC3_E15, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_0' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC5_E', type is memory -_EC5_E = MEMORY_SEGMENT( _LC3_E17, GLOBAL( TG42), GLOBAL( TG42), _LC1_E10, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_1' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC11_E', type is memory -_EC11_E = MEMORY_SEGMENT( _LC4_E10, GLOBAL( TG42), GLOBAL( TG42), _LC1_E10, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_2' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC3_E', type is memory -_EC3_E = MEMORY_SEGMENT( _LC6_E1, GLOBAL( TG42), GLOBAL( TG42), _LC1_E10, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_3' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC12_E', type is memory -_EC12_E = MEMORY_SEGMENT( _LC4_E17, GLOBAL( TG42), GLOBAL( TG42), _LC1_E10, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_4' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC4_E', type is memory -_EC4_E = MEMORY_SEGMENT( _LC8_E1, GLOBAL( TG42), GLOBAL( TG42), _LC1_E10, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_5' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC13_E', type is memory -_EC13_E = MEMORY_SEGMENT( _LC6_E8, GLOBAL( TG42), GLOBAL( TG42), _LC1_E10, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_6' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC2_E', type is memory -_EC2_E = MEMORY_SEGMENT( _LC8_E8, GLOBAL( TG42), GLOBAL( TG42), _LC1_E10, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_7' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC9_E', type is memory -_EC9_E = MEMORY_SEGMENT( _LC4_E8, GLOBAL( TG42), GLOBAL( TG42), _LC1_E10, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, _LC3_E9, _LC1_E6, _LC2_E9, _LC1_E2, _LC2_E3, _LC3_E3, _LC8_E14,!_LC3_E1, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_0' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC2_C', type is memory -_EC2_C = MEMORY_SEGMENT( D0, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_1' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC16_C', type is memory -_EC16_C = MEMORY_SEGMENT( D1, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_2' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC5_C', type is memory -_EC5_C = MEMORY_SEGMENT( d2, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_3' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC14_C', type is memory -_EC14_C = MEMORY_SEGMENT( d3, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_4' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC7_C', type is memory -_EC7_C = MEMORY_SEGMENT( d4, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_5' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC12_C', type is memory -_EC12_C = MEMORY_SEGMENT( d5, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_6' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC1_C', type is memory -_EC1_C = MEMORY_SEGMENT( d6, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_7' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC10_C', type is memory -_EC10_C = MEMORY_SEGMENT( d7, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_8' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC8_C', type is memory -_EC8_C = MEMORY_SEGMENT( _EC8_C, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_9' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC13_C', type is memory -_EC13_C = MEMORY_SEGMENT( _EC13_C, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_10' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC4_C', type is memory -_EC4_C = MEMORY_SEGMENT( _EC4_C, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_11' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC15_C', type is memory -_EC15_C = MEMORY_SEGMENT( _EC15_C, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_12' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC6_C', type is memory -_EC6_C = MEMORY_SEGMENT( _EC6_C, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_13' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC9_C', type is memory -_EC9_C = MEMORY_SEGMENT( _EC9_C, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_14' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC3_C', type is memory -_EC3_C = MEMORY_SEGMENT( _EC3_C, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_15' from file "altdpram.tdf" line 190, column 12 --- Equation name is '_EC11_C', type is memory -_EC11_C = MEMORY_SEGMENT( _EC11_C, GLOBAL( TG42), GLOBAL( TG42), _LC1_C32, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, _LC3_C20, _LC8_C20, _LC5_C20, _LC3_C21, _LC6_C20, _LC7_C21, _LC7_C20, _LC1_C20, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_0' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC1_B', type is memory -_EC1_B = MEMORY_SEGMENT( _LC3_B13, GLOBAL( TG42), VCC,!_LC3_B3, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_1' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC14_B', type is memory -_EC14_B = MEMORY_SEGMENT( _LC5_B17, GLOBAL( TG42), VCC,!_LC3_B3, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_2' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC5_B', type is memory -_EC5_B = MEMORY_SEGMENT( _LC6_B17, GLOBAL( TG42), VCC,!_LC3_B3, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_3' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC13_B', type is memory -_EC13_B = MEMORY_SEGMENT( _LC4_B13, GLOBAL( TG42), VCC,!_LC3_B3, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_4' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC2_B', type is memory -_EC2_B = MEMORY_SEGMENT( _LC6_B13, GLOBAL( TG42), VCC,!_LC3_B3, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_5' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC10_B', type is memory -_EC10_B = MEMORY_SEGMENT( _LC7_B13, GLOBAL( TG42), VCC,!_LC3_B3, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_6' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC4_B', type is memory -_EC4_B = MEMORY_SEGMENT( VCC, GLOBAL( TG42), VCC,!_LC3_B3, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_7' from file "altram.tdf" line 111, column 12 --- Equation name is '_EC12_B', type is memory -_EC12_B = MEMORY_SEGMENT( VCC, GLOBAL( TG42), VCC,!_LC3_B3, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, _LC2_B10, _LC7_B10, _LC6_B10, _LC5_B10, _LC8_B2, _LC2_B14, _LC4_B14, _LC5_B14, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_1' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC10_A', type is memory -_EC10_A = MEMORY_SEGMENT( CBD1, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_2' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC8_A', type is memory -_EC8_A = MEMORY_SEGMENT( CBD2, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_3' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC9_A', type is memory -_EC9_A = MEMORY_SEGMENT( CBD3, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_4' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC1_A', type is memory -_EC1_A = MEMORY_SEGMENT( CBD4, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_5' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC11_A', type is memory -_EC11_A = MEMORY_SEGMENT( CBD5, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_6' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC6_A', type is memory -_EC6_A = MEMORY_SEGMENT( CBD6, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_7' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC15_A', type is memory -_EC15_A = MEMORY_SEGMENT( CBD7, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_8' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC2_A', type is memory -_EC2_A = MEMORY_SEGMENT( _LC3_A1, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_9' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC14_A', type is memory -_EC14_A = MEMORY_SEGMENT( _LC3_D35, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_10' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC3_A', type is memory -_EC3_A = MEMORY_SEGMENT( _LC5_D33, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_11' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC12_A', type is memory -_EC12_A = MEMORY_SEGMENT( _LC3_D28, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_12' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC5_A', type is memory -_EC5_A = MEMORY_SEGMENT( _LC5_D24, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_13' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC13_A', type is memory -_EC13_A = MEMORY_SEGMENT( _LC1_D21, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_14' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC7_A', type is memory -_EC7_A = MEMORY_SEGMENT( _LC6_D19, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - --- Node name is '|lpm_ram_dp:CBL|altdpram:sram|segment0_15' from file "altdpram.tdf" line 163, column 13 --- Equation name is '_EC4_A', type is memory -_EC4_A = MEMORY_SEGMENT( _LC1_A14, GLOBAL( TG42), GLOBAL( TG42), _LC3_A14, VCC, _LC3_A29, _LC3_A27, _LC3_A26, _LC2_A27, _LC5_A27, _LC3_A22, _LC7_A26, _LC1_A22, VCC, VCC, VCC, _LC8_A25, CBL_CNT1, CBL_CNT2, CBL_CNT3, CBL_CNT4, CBL_CNT5, CBL_CNT6, CBL_CNT7, VCC, VCC, VCC, VCC, VCC, VCC); - - - -Project Information c:\sprinter\src\altera\acex\sp2_acex.rpt - -** TIMING ASSIGNMENTS ** - - -INFORMATION: One or more paths have been found between register controlled by different clocks--can't calculate fmax for those paths - - User Actual -Type Location Assignment Value Status Critical Path - -fmax 100.00 MHz 200.00 MHz /io to register |dcp:DECODE|AROM16.Q to register |dcp:DECODE|AROM16.Q -fmax 100.00 MHz 166.66 MHz /mr to register |acceler:ACC|ED_CMD.Q to register |acceler:ACC|RETI.Q -fmax 100.00 MHz 200.00 MHz /m1 to register |dcp:DECODE|AROM16.Q to register |dcp:DECODE|AROM16.Q -fmax 100.00 MHz 49.26 MHz Failed TG42 to register CBL_CTX0.Q to register CBL_CNT3.Q -fmax 100.00 MHz 200.00 MHz /wr to register |dcp:DECODE|AROM16.Q to register |dcp:DECODE|AROM16.Q - - -Project Information c:\sprinter\src\altera\acex\sp2_acex.rpt - -** COMPILATION SETTINGS & TIMES ** - -Processing Menu Commands ------------------------- - -Design Doctor = off - -Logic Synthesis: - - Synthesis Type Used = Multi-Level - - Default Synthesis Style = FAST - - Logic option settings in 'FAST' style for 'ACEX1K' family - - CARRY_CHAIN = auto - CARRY_CHAIN_LENGTH = 32 - CASCADE_CHAIN = auto - CASCADE_CHAIN_LENGTH = 2 - DECOMPOSE_GATES = on - DUPLICATE_LOGIC_EXTRACTION = on - MINIMIZATION = full - MULTI_LEVEL_FACTORING = on - NOT_GATE_PUSH_BACK = on - REDUCE_LOGIC = on - REFACTORIZATION = off - REGISTER_OPTIMIZATION = on - RESYNTHESIZE_NETWORK = on - SLOW_SLEW_RATE = on - SUBFACTOR_EXTRACTION = off - IGNORE_SOFT_BUFFERS = on - USE_LPM_FOR_AHDL_OPERATORS = off - - Other logic synthesis settings: - - Automatic Global Clock = on - Automatic Global Clear = on - Automatic Global Preset = on - Automatic Global Output Enable = on - Automatic Fast I/O = off - Automatic Register Packing = off - Automatic Open-Drain Pins = on - Automatic Implement in EAB = off - Optimize = 5 - -Default Timing Specifications: - - fmax = 100MHz - -Cut All Bidir Feedback Timing Paths = on -Cut All Clear & Preset Timing Paths = on - -Ignore Timing Assignments = off - -Functional SNF Extractor = off - -Linked SNF Extractor = off -Timing SNF Extractor = on -Optimize Timing SNF = off -Generate AHDL TDO File = off -Fitter Settings = CUSTOM -Use Quartus Fitter = off -Smart Recompile = off -Total Recompile = off - -Interfaces Menu Commands ------------------------- - -EDIF Netlist Writer = off -Verilog Netlist Writer = off -VHDL Netlist Writer = off - -Compilation Times ------------------ - - Compiler Netlist Extractor 00:00:00 - Database Builder 00:00:00 - Logic Synthesizer 00:00:02 - Partitioner 00:00:01 - Fitter 00:00:11 - Timing SNF Extractor 00:00:02 - Assembler 00:00:00 - -------------------------- -------- - Total Time 00:00:16 - - -Memory Allocated ------------------ - -Peak memory allocated during compilation = 50,567K diff --git a/src/altera/max/7064/SP2_MAX.ACF b/src/altera/max/7064/SP2_MAX.ACF index 22c888e..40052de 100644 --- a/src/altera/max/7064/SP2_MAX.ACF +++ b/src/altera/max/7064/SP2_MAX.ACF @@ -38,43 +38,43 @@ BEGIN |WR_PDOS : OUTPUT_PIN = 8; |/WG_WR : OUTPUT_PIN = 93; |/WG_RD : OUTPUT_PIN = 97; - |WDAT : OUTPUT_PIN = 98; + |WDAT : OUTPUT_PIN = 98; |TG42_OUT : OUTPUT_PIN = 85; |TG42_BUF : OUTPUT_PIN = 36; |SINC_2 : OUTPUT_PIN = 19; |SINC_1 : OUTPUT_PIN = 20; |SINC_V : OUTPUT_PIN = 64; |SINC_H : OUTPUT_PIN = 68; - |SINC : OUTPUT_PIN = 67; - |QDAT : OUTPUT_PIN = 16; + |SINC : OUTPUT_PIN = 67; + |QDAT : OUTPUT_PIN = 16; |HD_DIR : OUTPUT_PIN = 48; |HD_CS : OUTPUT_PIN = 52; - |FDAT : OUTPUT_PIN = 14; + |FDAT : OUTPUT_PIN = 14; |DENS_X : OUTPUT_PIN = 96; |CMOS_DWR : OUTPUT_PIN = 100; |CMOS_DRD : OUTPUT_PIN = 99; |CMOS_AS : OUTPUT_PIN = 6; |CLK14 : OUTPUT_PIN = 31; |CLK_WG : OUTPUT_PIN = 13; - |BEEP : OUTPUT_PIN = 84; - |AUD : OUTPUT_PIN = 35; + |BEEP : OUTPUT_PIN = 84; + |AUD : OUTPUT_PIN = 35; |XHR_RDY : INPUT_PIN = 88; - |XA2 : INPUT_PIN = 23; - |XA1 : INPUT_PIN = 21; - |XA0 : INPUT_PIN = 17; - |XACS : INPUT_PIN = 37; - |WSTB : INPUT_PIN = 10; + |XA2 : INPUT_PIN = 23; + |XA1 : INPUT_PIN = 21; + |XA0 : INPUT_PIN = 17; + |XACS : INPUT_PIN = 37; + |WSTB : INPUT_PIN = 10; |WR_CNF : INPUT_PIN = 57; - |WD : INPUT_PIN = 9; + |WD : INPUT_PIN = 9; |VGA_IN : INPUT_PIN = 61; - |TR43 : INPUT_PIN = 12; + |TR43 : INPUT_PIN = 12; |TG42_IN : INPUT_PIN = 87; - |STE : INPUT_PIN = 94; - |SR : INPUT_PIN = 29; - |SL : INPUT_PIN = 30; + |STE : INPUT_PIN = 94; + |SR : INPUT_PIN = 29; + |SL : INPUT_PIN = 30; |SINC_IN : INPUT_PIN = 69; - |RSTB : INPUT_PIN = 25; - |RDAT : INPUT_PIN = 92; + |RSTB : INPUT_PIN = 25; + |RDAT : INPUT_PIN = 92; |PW_GOOD : INPUT_PIN = 90; |HDD_C3 : INPUT_PIN = 40; |HDD_C2 : INPUT_PIN = 41; @@ -84,7 +84,7 @@ BEGIN |FDD_C1 : INPUT_PIN = 45; |FDD_C0 : INPUT_PIN = 44; |EPM_RES : INPUT_PIN = 89; - |D0 : INPUT_PIN = 60; + |D0 : INPUT_PIN = 60; END; DEFAULT_DEVICES diff --git a/src/altera/max/7064/SP2_MAX.SCF b/src/altera/max/7064/SP2_MAX.SCF deleted file mode 100644 index 38a9ff0..0000000 Binary files a/src/altera/max/7064/SP2_MAX.SCF and /dev/null differ diff --git a/src/altera/max/7064/scf/SP2_MAX.SCF b/src/altera/max/7064/scf/SP2_MAX.SCF deleted file mode 100644 index 38a9ff0..0000000 Binary files a/src/altera/max/7064/scf/SP2_MAX.SCF and /dev/null differ diff --git a/src/altera/max/7064/SP2_MAX.TDF b/src/altera/max/7064/sp2_max.tdf similarity index 86% rename from src/altera/max/7064/SP2_MAX.TDF rename to src/altera/max/7064/sp2_max.tdf index 5bd21a3..b24582c 100644 --- a/src/altera/max/7064/SP2_MAX.TDF +++ b/src/altera/max/7064/sp2_max.tdf @@ -85,8 +85,27 @@ SUBDESIGN SP2_MAX EPM_RES : INPUT; PW_GOOD : INPUT; - GND65 : INPUT; - GND33 : INPUT; + UNUSED65 : INPUT; -- was GND65, hack for 3000 family + UNUSED33 : INPUT; -- was GND33, hack for 3000 family + UNUSED1 : INPUT; + UNUSED2 : INPUT; + UNUSED5 : INPUT; + UNUSED7 : INPUT; + UNUSED22 : INPUT; + UNUSED24 : INPUT; + UNUSED27 : INPUT; + UNUSED28 : INPUT; + UNUSED49 : INPUT; + UNUSED50 : INPUT; + UNUSED53 : INPUT; + UNUSED55 : INPUT; + UNUSED63 : INPUT; + UNUSED70 : INPUT; + UNUSED72 : INPUT; + UNUSED77 : INPUT; + UNUSED78 : INPUT; + + ) VARIABLE @@ -435,13 +454,16 @@ BEGIN HD_DIR = XHD_RD; -- HD_CS = GND; - HD_CS = CTV8M; +-- HD_CS = CTV8M; + HD_CS = (CTV8M and /RESET); + -- HD_CS = !/RESET; -- XHD_RES = VCC; - XHD_RES = DFF(PW_GOOD,SINC_V,,); +-- XHD_RES = DFF(PW_GOOD,SINC_V,,); + XHD_RES = DFF(PW_GOOD,SINC_V,EPM_RES,); -- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),CLK42,,); -- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),CLK42,,); @@ -451,8 +473,10 @@ BEGIN -- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1 or !HDD_CLK),CLK42,,HDD_C0); -- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1 or !HDD_CLK),CLK42,,HDD_C0); - XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,HDD_C0); - XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,HDD_C0); +-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,HDD_C0); +-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,HDD_C0); + XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,(HDD_C0 and /RESET)); + XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,(HDD_C0 and /RESET)); -- XHD1_CS1 = DFF(!((HDD_C[] == B"010X") & NTHDD),CLK42,,); -- XHD1_CS2 = DFF(!((HDD_C[] == B"110X") & NTHDD),CLK42,,); @@ -460,11 +484,16 @@ BEGIN -- XHD2_CS1 = DFF(!((HDD_C[] == B"010X") & THDD),CLK42,,); -- XHD2_CS2 = DFF(!((HDD_C[] == B"110X") & THDD),CLK42,,); - XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,); - XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,); +-- XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,); +-- XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,); + XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,/RESET); + XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,/RESET); + +-- XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,); +-- XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,); + XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,/RESET); + XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,/RESET); - XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,); - XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,); END; diff --git a/src/altera/max/7128/SP2_MAX.ACF b/src/altera/max/7128/SP2_MAX.ACF index 3be71be..689ae3e 100644 --- a/src/altera/max/7128/SP2_MAX.ACF +++ b/src/altera/max/7128/SP2_MAX.ACF @@ -22,69 +22,115 @@ CHIP SP2_MAX BEGIN DEVICE = EPM7128STC100-10; - |GND65 : INPUT_PIN = 65; - |GND33 : INPUT_PIN = 33; - |/CONF_X : BIDIR_PIN = 54; - |10K_D0 : OUTPUT_PIN = 58; - |CLKZZ : BIDIR_PIN = 32; - |10K_CLK : OUTPUT_PIN = 56; - |XHD2_CS2 : OUTPUT_PIN = 83; - |XHD2_CS1 : OUTPUT_PIN = 81; - |XHD1_CS2 : OUTPUT_PIN = 80; - |XHD1_CS1 : OUTPUT_PIN = 79; - |XHD_WR : OUTPUT_PIN = 75; - |XHD_RES : OUTPUT_PIN = 71; - |XHD_RD : OUTPUT_PIN = 76; - |WR_PDOS : OUTPUT_PIN = 8; - |/WG_WR : OUTPUT_PIN = 93; - |/WG_RD : OUTPUT_PIN = 97; - |WDAT : OUTPUT_PIN = 98; - |TG42_OUT : OUTPUT_PIN = 85; - |TG42_BUF : OUTPUT_PIN = 36; - |SINC_2 : OUTPUT_PIN = 19; - |SINC_1 : OUTPUT_PIN = 20; - |SINC_V : OUTPUT_PIN = 64; - |SINC_H : OUTPUT_PIN = 68; - |SINC : OUTPUT_PIN = 67; - |QDAT : OUTPUT_PIN = 16; - |HD_DIR : OUTPUT_PIN = 48; - |HD_CS : OUTPUT_PIN = 52; - |FDAT : OUTPUT_PIN = 14; - |DENS_X : OUTPUT_PIN = 96; - |CMOS_DWR : OUTPUT_PIN = 100; - |CMOS_DRD : OUTPUT_PIN = 99; + |UNUSED1: INPUT_PIN = 1; -- 7064 N.C. + |UNUSED2: INPUT_PIN = 2; -- 7064 N.C. +-- |VCCIO +-- |#TDI + |UNUSED5: INPUT_PIN = 5; -- 7064 N.C. |CMOS_AS : OUTPUT_PIN = 6; - |CLK14 : OUTPUT_PIN = 31; + |UNUSED7: INPUT_PIN = 7; -- 7064 N.C. + |WR_PDOS : OUTPUT_PIN = 8; + |WD : INPUT_PIN = 9; + + |WSTB : INPUT_PIN = 10; +-- |GND + |TR43 : INPUT_PIN = 12; |CLK_WG : OUTPUT_PIN = 13; - |BEEP : OUTPUT_PIN = 84; - |AUD : OUTPUT_PIN = 35; - |XHR_RDY : INPUT_PIN = 88; - |XA2 : INPUT_PIN = 23; - |XA1 : INPUT_PIN = 21; - |XA0 : INPUT_PIN = 17; - |XACS : INPUT_PIN = 37; - |WSTB : INPUT_PIN = 10; - |WR_CNF : INPUT_PIN = 57; - |WD : INPUT_PIN = 9; - |VGA_IN : INPUT_PIN = 61; - |TR43 : INPUT_PIN = 12; - |TG42_IN : INPUT_PIN = 87; - |STE : INPUT_PIN = 94; - |SR : INPUT_PIN = 29; - |SL : INPUT_PIN = 30; - |SINC_IN : INPUT_PIN = 69; - |RSTB : INPUT_PIN = 25; - |RDAT : INPUT_PIN = 92; - |PW_GOOD : INPUT_PIN = 90; + |FDAT : OUTPUT_PIN = 14; +-- |#TMS + |QDAT : OUTPUT_PIN = 16; + |XA0 : INPUT_PIN = 17; +-- |VCCIO + |SINC_2 : OUTPUT_PIN = 19; + + |SINC_1 : OUTPUT_PIN = 20; + |XA1 : INPUT_PIN = 21; + |UNUSED22: INPUT_PIN = 22; -- 7064 N.C. + |XA2 : INPUT_PIN = 23; + |UNUSED24: INPUT_PIN = 24; -- 7064 N.C. + |RSTB : INPUT_PIN = 25; +-- |GND + |UNUSED27: INPUT_PIN = 27; -- 7064 N.C. + |UNUSED28: INPUT_PIN = 28; -- 7064 N.C. + |SR : INPUT_PIN = 29; + + |SL : INPUT_PIN = 30; + |CLK14 : OUTPUT_PIN = 31; + |CLKZZ : BIDIR_PIN = 32; + |UNUSED33 : INPUT_PIN = 33; -- be careful! at 3000 family the pin 33 is GND +-- |VCCIO + |AUD : OUTPUT_PIN = 35; + |TG42_BUF : OUTPUT_PIN = 36; + |XACS : INPUT_PIN = 37; +-- |GND +-- |VCCINT + |HDD_C3 : INPUT_PIN = 40; |HDD_C2 : INPUT_PIN = 41; |HDD_C1 : INPUT_PIN = 42; - |HDD_C0 : INPUT_PIN = 47; - |FDD_C2 : INPUT_PIN = 46; - |FDD_C1 : INPUT_PIN = 45; +-- |GND |FDD_C0 : INPUT_PIN = 44; + |FDD_C1 : INPUT_PIN = 45; + |FDD_C2 : INPUT_PIN = 46; + |HDD_C0 : INPUT_PIN = 47; + |HD_DIR : OUTPUT_PIN = 48; + |UNUSED49: INPUT_PIN = 49; -- 7064 N.C. + + |UNUSED50: INPUT_PIN = 50; -- 7064 N.C. +-- |VCCIO + |HD_CS : OUTPUT_PIN = 52; + |UNUSED53 : INPUT_PIN = 53; -- 7064 N.C. + |/CONF_X : BIDIR_PIN = 54; + |UNUSED55: INPUT_PIN = 55; -- 7064 N.C. + |10K_CLK : OUTPUT_PIN = 56; + |WR_CNF : INPUT_PIN = 57; + |10K_D0 : OUTPUT_PIN = 58; +-- |GND + + |D0 : INPUT_PIN = 60; + |VGA_IN : INPUT_PIN = 61; +-- |#TCK + |UNUSED63: INPUT_PIN = 63; + |SINC_V : OUTPUT_PIN = 64; + |UNUSED65 : INPUT_PIN = 65; -- be careful! at 3000 family the pin 33 is GND +-- |VCCIO + |SINC : OUTPUT_PIN = 67; + |SINC_H : OUTPUT_PIN = 68; + |SINC_IN : INPUT_PIN = 69; + + |UNUSED70: INPUT_PIN = 70; -- 7064 N.C. + |XHD_RES : OUTPUT_PIN = 71; + |UNUSED72: INPUT_PIN = 72; -- 7064 N.C. +-- |#TDO +-- |GND + |XHD_WR : OUTPUT_PIN = 75; + |XHD_RD : OUTPUT_PIN = 76; + |UNUSED77: INPUT_PIN = 77; -- 7064 N.C. + |UNUSED78 : INPUT_PIN = 78; -- 7064 N.C. + |XHD1_CS1 : OUTPUT_PIN = 79; + + |XHD1_CS2 : OUTPUT_PIN = 80; + |XHD2_CS1 : OUTPUT_PIN = 81; +-- |VCCIO + |XHD2_CS2 : OUTPUT_PIN = 83; + |BEEP : OUTPUT_PIN = 84; + |TG42_OUT : OUTPUT_PIN = 85; +-- |GND + |TG42_IN : INPUT_PIN = 87; + |XHR_RDY : INPUT_PIN = 88; |EPM_RES : INPUT_PIN = 89; - |D0 : INPUT_PIN = 60; + + |PW_GOOD : INPUT_PIN = 90; +-- |VCCINT + |RDAT : INPUT_PIN = 92; + |/WG_WR : OUTPUT_PIN = 93; + |STE : INPUT_PIN = 94; +-- |GND + |DENS_X : OUTPUT_PIN = 96; + |/WG_RD : OUTPUT_PIN = 97; + |WDAT : OUTPUT_PIN = 98; + |CMOS_DRD : OUTPUT_PIN = 99; + |CMOS_DWR : OUTPUT_PIN = 100; END; DEFAULT_DEVICES diff --git a/src/altera/max/7128/scf/SP2_MAX.SCF b/src/altera/max/7128/scf/SP2_MAX.SCF deleted file mode 100644 index 38a9ff0..0000000 Binary files a/src/altera/max/7128/scf/SP2_MAX.SCF and /dev/null differ diff --git a/src/altera/max/7128/sp2_max.tdf b/src/altera/max/7128/sp2_max.tdf new file mode 100644 index 0000000..b24582c --- /dev/null +++ b/src/altera/max/7128/sp2_max.tdf @@ -0,0 +1,499 @@ + +TITLE "SINC_controller"; + +PARAMETERS + ( + G_MODE = 1, -- 1 on LCELL, 0 - on EXP + + NUM = "NO", + NUMBER1 = B"00100000X", -- 0 - sinc + NUMBER2 = B"00110111X", -- 7 + NUMBER3 = B"01001101X", -- D + NUMBER4 = B"01010010X", -- 2 + NUMBER5 = B"00100000X", -- + NUMBER6 = B"00100000X", -- + NUMBER7 = B"00100000X" -- + ); + +SUBDESIGN SP2_MAX + ( + + TG42_IN : INPUT; + TG42_OUT : OUTPUT; + TG42_BUF : OUTPUT; + CLKZZ : BIDIR; + CLK14 : OUTPUT; + + AUD : OUTPUT; -- clk for timers + BEEP : OUTPUT; + + CMOS_DRD : OUTPUT; + CMOS_AS : OUTPUT; + CMOS_DWR : OUTPUT; + + WR_PDOS : OUTPUT; + WD : INPUT; + WSTB : INPUT; + SR,SL : INPUT; + RSTB : INPUT; + TR43 : INPUT; + CLK_WG : OUTPUT; + FDAT : OUTPUT; + QDAT : OUTPUT; + RDAT : INPUT; + /WG_WR : OUTPUT; + /WG_RD : OUTPUT; + STE : INPUT; + DENS_X : OUTPUT; + WDAT : OUTPUT; + + +-- XA[2..0] : BIDIR; + XA[2..0] : INPUT; + XACS : INPUT; +-- SINC_1 : OUTPUT; + SINC_1 : BIDIR; + SINC_2 : BIDIR; + + HDD_C[3..0] : INPUT; + FDD_C[2..0] : INPUT; + + HD_DIR : OUTPUT; + HD_CS : OUTPUT; + + /CONF_X : BIDIR; + 10K_CLK : OUTPUT; + WR_CNF : INPUT; + 10K_D0 : OUTPUT; + D0 : INPUT; + + VGA_IN : INPUT; +-- WR_COL : INPUT; + SINC_V : OUTPUT; + SINC_H : OUTPUT; + SINC : OUTPUT; + SINC_IN : INPUT; + + XHD_RES : OUTPUT; + XHD_WR : OUTPUT; + XHD_RD : OUTPUT; + + XHD1_CS[2..1] : OUTPUT; + XHD2_CS[2..1] : OUTPUT; + XHR_RDY : INPUT; + + EPM_RES : INPUT; + PW_GOOD : INPUT; + + UNUSED65 : INPUT; -- was GND65, hack for 3000 family + UNUSED33 : INPUT; -- was GND33, hack for 3000 family + UNUSED1 : INPUT; + UNUSED2 : INPUT; + UNUSED5 : INPUT; + UNUSED7 : INPUT; + UNUSED22 : INPUT; + UNUSED24 : INPUT; + UNUSED27 : INPUT; + UNUSED28 : INPUT; + UNUSED49 : INPUT; + UNUSED50 : INPUT; + UNUSED53 : INPUT; + UNUSED55 : INPUT; + UNUSED63 : INPUT; + UNUSED70 : INPUT; + UNUSED72 : INPUT; + UNUSED77 : INPUT; + UNUSED78 : INPUT; + + + + ) +VARIABLE + + XCT[2..0] : DFF; + CNF_ON : NODE; + CNF_OFF : NODE; + + CLK42 : NODE; + + CT[3..0] : DFF; + CTH[5..0] : DFF; + CTV[8..0] : DFFE; + + SINC_HT : DFF; + SINC_VT : DFFE; + + TURBING : NODE; + FDD_1440 : NODE; + NFDD_1440 : NODE; + + CT_WG : NODE; + CT_WG1 : NODE; + + STWG[2..0] : DFF; + CLK_PRC : NODE; + WGR[4..0] : DFF; + RDAT_X : NODE; + + REG_P[2..0] : DFF; + + /RESET : NODE; + + + S144,S720 : NODE; + + SHDD1,SHDD2 : NODE; + THDD : NODE; + NTHDD : NODE; + + NO_HDD : NODE; + + S320,S312 : NODE; + T320 : NODE; + NT320 : NODE; + + SOFT_RESET : NODE; + SOFT_RESET2 : NODE; + + HDD_CLK : NODE; + + LR_T[1..0] : DFF; + + EXP_X : NODE; + EXP_Y : NODE; + + CTV8M : DFF; + + CTV8C : NODE; + + FN_NUM : NODE; + +BEGIN + + /RESET = DFF((EPM_RES & XHD_RES),!CT3,SOFT_RESET,); + +-- /RESET = (EXP(!EPM_RES & EXP(EXP(EXP(EPM_RES)))) & SOFT_RESET); + + EXP_X = EXP(TG42_IN); + EXP_Y = EXP(TG42_IN); + + IF (G_MODE == 0) GENERATE + TG42_OUT = LCELL(EXP_X); + ELSE GENERATE + TG42_OUT = LCELL(TG42_BUF); + END GENERATE; + + TG42_BUF = LCELL(!TG42_IN); + + CLK42 = TG42_IN; + +-- CT[].clk = CLK14; + CT[].clk = XCT1; + CT[] = CT[] + 1; + +-- === horizontal sinc ===== + + CTH[].clk = !CT3; + SINC_HT.clk = !CT3; + + IF !((CTH[] == B"XXXX11") & SINC_HT) THEN + CTH[] = CTH[] + 1; + ELSE + CTH[] = GND; + END IF; + +-- SINC_1 = CTH5; + SINC_1 = TRI(CTH5,VCC); + SINC_2 = TRI(CTV8,VCC); + + SINC_HT.d = (CTH[] == B"1101XX"); + + SINC_H = SINC_HT; + +-- === vertical sinc ======= + +-- CTV[].clk = !CT3; +-- SINC_VT.clk = !CT3; + + CTV[].clk = SINC_HT; + SINC_VT.clk = SINC_HT; + + CTV8M.clk = SINC_HT; + +-- CTV[].ena = (CTH[] == B"110111"); +-- SINC_VT.ena = (CTH[] == B"110111"); + CTV[].ena = VCC; + SINC_VT.ena = VCC; + +-- IF (CTV[] == B"100111111") THEN + + IF (NUM == "YES") GENERATE + + FN_NUM =( + (CTV[8..0] == NUMBER1) or + (CTV[8..0] == NUMBER2) or + (CTV[8..0] == NUMBER3) or + (CTV[8..0] == NUMBER4) or + (CTV[8..0] == NUMBER5) or + (CTV[8..0] == NUMBER6) or + (CTV[8..0] == NUMBER7) + ) & !NO_HDD; + + ELSE GENERATE + + FN_NUM = GND; + + END GENERATE; + + + IF EXP((CTV[] == B"XXXXXXX11") & SINC_VT) THEN + + (CTV[8..0]) = ((CTV[8..0]) + 1) xor (CTV8M,B"00000000"); + CTV8M = FN_NUM; + + ELSE + CTV[7..0] = GND; + CTV8M = GND; + CTV8 = GND; + END IF; + + SINC_VT.d = ((CTV[8..0] == B"1001111XX") or ((CTV[8..0] == B"1001101XX")) & NT320); + + SINC_V = SINC_VT; + + SINC = SINC_V xor SINC_H; + +-- ============================= + +-- ========================================= +-- divide by 6 + + XCT[].clk = (TG42_IN xor !XCT1); + XCT[].d = XCT[] + 1; + +-- CLKZZ = 14 MHz + + CLKZZ = TRI(XCT1,CNF_OFF); + CLK14 = DFF(!CLK14,XCT0,,); + +-- test exists + +-- CNF_OFF = EXP(CNF_ON & /RESET); +-- CNF_ON = EXP(CNF_OFF & XACS); + + CNF_OFF = DFF(GND,GND,XACS,/RESET); + CNF_ON = !CNF_OFF; + +-- ========================================= + +-- ======== FDD controller ================== + + TURBING = EXP(EXP(TURBING & !WSTB & !RSTB) & !STE & NFDD_1440); +-- TURBING = GND; + + CT_WG = TFF(VCC,(XCT1 xor (CT_WG & TURBING)),,); + + STWG[].clk = (CT_WG xor STWG2); + STWG[].d = STWG[] + 1; + + CLK_WG = STWG2; + +-- CLK_PRC = STWG0; + CLK_PRC = CT_WG; + + CT_WG1 = EXP(EXP(XCT1 & FDD_1440) & EXP(CT0 & NFDD_1440)); + + WGR[].clk = CT_WG1; + + IF !FDAT THEN + TABLE WGR[3..0] => WGR[3..0].d; + 0 => 4; 1 => 5; 2 => 4; 3 => 5; + 4 => 6; 5 => 7; 6 => 8; 7 => 8; + 8 => 9; 9 => 9; 10 => 10; 11 => 11; + 12 => 12; 13 => 13; 14 => 14; 15 => 15; + END TABLE; + WGR4.d = WGR4; + ELSE + IF WGR[3..0] == 0 THEN + WGR[3..0].d = 3; + WGR4.d = WGR4; + ELSE + WGR[].d = WGR[] + 1; + END IF; + END IF; + + QDAT = WGR4; + RDAT_X = EXP(EXP(RDAT_X & EXP(!RDAT & !CT_WG1)) & EXP(RDAT & !CT_WG1)); +-- FDAT = DFF((RDAT_X or !DFF(RDAT_X,CT_WG1,,)),CT_WG1,,); + FDAT = DFF((RDAT_X or EXP(DFF(RDAT_X,CT_WG1,,))),CT_WG1,,); +-- ========================================================== +-- now not complete! + + AUD = CT3; + BEEP = GND; + +-- /CONF_X = TRI(GND,!/RESET); + + /CONF_X = OPNDRN(/RESET); + +-- 10K_CLK = WR_CNF; -- now not protect! + + 10K_CLK = DFF((WR_CNF & CNF_OFF) or ((HDD_C0 or FDD_C2) & CNF_ON),CLK42,,); + + 10K_D0 = DFFE(D0,10K_CLK,S720,(S144 & /RESET),CNF_OFF); + + DENS_X = VCC; + +-- === now NOT PRECOMP! ===== + +-- WDAT = WD; + + WDAT = REG_P2; + + REG_P[].clk = !CLK_PRC; + +-- CASE WD IS +-- WHEN 1 => REG_P[].d = (GND,SL,!(SL or SR),SR); +-- WHEN 0 => REG_P[].d = (EXP(EXP(REG_P2)),REG_P[1..0],GND); +-- END CASE; + +-- CASE (DFF(WD,CLK_WG,,),DFF((SL & TR43),CLK_WG,,),DFF((SR & TR43),CLK_WG,,)) IS + + LR_T[].clk = STWG2; +-- LR_T[].clk = CLK_WG; + + LR_T[].d = ((WD & !(SL & TR43)),(WD & !(SR & TR43))); + + CASE LR_T[] IS + WHEN 0 => REG_P[1..0] = (REG_P[1..0] - 1) & EXP(REG_P[1..0] == 0); + REG_P[2] = EXP(EXP(REG_P[1..0] == 1)); +-- REG_P[2] = (REG_P[1..0] == 1); + WHEN 1 => REG_P[1..0] = 1; REG_P[2] = GND; + WHEN 2 => REG_P[1..0] = 3; REG_P[2] = GND; + WHEN 3 => REG_P[1..0] = 2; REG_P[2] = GND; + END CASE; +% + CASE (WD,DFF((SL & TR43),CLK_WG,,),DFF((SR & TR43),CLK_WG,,)) IS + WHEN B"0XX" => REG_P[1..0] = (REG_P[1..0] - 1) & EXP(REG_P[1..0] == 0); + WHEN B"100" => REG_P[1..0] = 2; + WHEN B"110" => REG_P[1..0] = 1; + WHEN B"101" => REG_P[1..0] = 3; + WHEN B"111" => REG_P[1..0] = 2; + END CASE; +% + +% + CASE WD IS + WHEN 0 => REG_P[3] = EXP(EXP(REG_P[1..0] == 1)); + WHEN 1 => REG_P[3] = GND; + END CASE; +% + +-- === Port Controls ==================================== +% + FDD_C0 - 0 - WG93 / 1 - kmps/ p_dos + FDD_C1 - 0 - write / 1 - read + FDD_C2 - 0 - no / 1 - CS_WG/ strobe + + HDD_C0 - strobe + HDD_C[2..1] = 00 - SYS_FN, 01 - SYS_FN, 10 - HDD1/2, 11 - CMOS + HDD_C3 - 0 - HD_CS1, 1 HD_CS3 / 0 CMOS_DAT, 1 - CMOS_ADR + + HDD_C[3..0] = 0001, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set 1.44/720 + HDD_C[3..0] = 1001, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set 320/312 lines + HDD_C[3..0] = 0011, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set HDD1/HDD2 + HDD_C[3..0] = 1011, FDD_C[2..1] = 00; -> FDD_C0 = 0 -> soft_reset! + HDD_C[3..0] = X101, FDD_C[2..1] = XX; -> HDD1/2 rd/wr + +% + + SOFT_RESET = !((HDD_C[] == B"1011") & (FDD_C[] == B"000")); + SOFT_RESET2 = !((HDD_C[] == B"1011") & (FDD_C[] == B"001")); + +-- FDD switch + +-- NFDD_1440 = EXP(FDD_1440 & S720 & /RESET); +-- FDD_1440 = EXP(NFDD_1440 & S144); + FDD_1440 = 10K_D0; + NFDD_1440 = !10K_D0; + + S144 = EXP((HDD_C[] == B"0001") & (FDD_C[] == B"001")); + S720 = EXP((HDD_C[] == B"0001") & (FDD_C[] == B"000")); + +-- Screen Switch + + T320 = EXP(NT320 & S320 & /RESET); + NT320 = EXP(T320 & S312); + + S312 = EXP((HDD_C[] == B"1001") & (FDD_C[] == B"001")); + S320 = EXP((HDD_C[] == B"1001") & (FDD_C[] == B"000")); + +-- HDD Switch + +-- THDD = EXP(NTHDD & SHDD2 & /RESET); +-- NTHDD = EXP(THDD & SHDD1); + + THDD = EXP(NTHDD & NO_HDD & SHDD2 & /RESET & SOFT_RESET2); + NTHDD = EXP(THDD & NO_HDD & SHDD1 & /RESET & SOFT_RESET2); + NO_HDD = EXP(NTHDD & THDD & SHDD1 & SHDD2); + + SHDD2 = EXP((HDD_C[] == B"0011") & (FDD_C[] == B"001")); + SHDD1 = EXP((HDD_C[] == B"0011") & (FDD_C[] == B"000")); + +-- Control signals + + WR_PDOS = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2); + /WG_WR = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X00")),HDD_CLK,,FDD_C2); + /WG_RD = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X10")),HDD_CLK,,FDD_C2); + + CMOS_DWR = DFF(!((HDD_C[] == B"1110") & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2); + CMOS_AS =!DFF(!((HDD_C[] == B"0110") & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2); + CMOS_DRD = DFF(!((HDD_C[] == B"1110") & (FDD_C[] == B"X10")),HDD_CLK,,FDD_C2); + +-- HD_DIR = !HDD_C1; -- ???????????? + HD_DIR = XHD_RD; + +-- HD_CS = GND; +-- HD_CS = CTV8M; + HD_CS = (CTV8M and /RESET); + + +-- HD_CS = !/RESET; + +-- XHD_RES = VCC; + +-- XHD_RES = DFF(PW_GOOD,SINC_V,,); + XHD_RES = DFF(PW_GOOD,SINC_V,EPM_RES,); + +-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),CLK42,,); +-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),CLK42,,); + +-- HDD_CLK = EXP(EXP(HDD_C0)); + HDD_CLK = 10K_CLK; + +-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1 or !HDD_CLK),CLK42,,HDD_C0); +-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1 or !HDD_CLK),CLK42,,HDD_C0); +-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,HDD_C0); +-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,HDD_C0); + XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,(HDD_C0 and /RESET)); + XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,(HDD_C0 and /RESET)); + +-- XHD1_CS1 = DFF(!((HDD_C[] == B"010X") & NTHDD),CLK42,,); +-- XHD1_CS2 = DFF(!((HDD_C[] == B"110X") & NTHDD),CLK42,,); + +-- XHD2_CS1 = DFF(!((HDD_C[] == B"010X") & THDD),CLK42,,); +-- XHD2_CS2 = DFF(!((HDD_C[] == B"110X") & THDD),CLK42,,); + +-- XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,); +-- XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,); + XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,/RESET); + XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,/RESET); + +-- XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,); +-- XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,); + XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,/RESET); + XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,/RESET); + + +END; + diff --git a/src/altera/max/7128_make.bat b/src/altera/max/7128_make.bat new file mode 100644 index 0000000..c03174c --- /dev/null +++ b/src/altera/max/7128_make.bat @@ -0,0 +1,4 @@ +C: +cd "C:\users\tolik\Documents\SP_Projects\ASM\GIT\SP_Core\Build\MAX\tmp\" +"C:\Program Files (x86)\MAXPLUS2\MAXPLUS2.EXE" -compile SP2_MAX >> compile.log +exit \ No newline at end of file diff --git a/src/altera/max/SP2_MAX.TDF b/src/altera/max/SP2_MAX.TDF index 065a5d7..b24582c 100644 --- a/src/altera/max/SP2_MAX.TDF +++ b/src/altera/max/SP2_MAX.TDF @@ -85,8 +85,27 @@ SUBDESIGN SP2_MAX EPM_RES : INPUT; PW_GOOD : INPUT; - GND65 : INPUT; - GND33 : INPUT; + UNUSED65 : INPUT; -- was GND65, hack for 3000 family + UNUSED33 : INPUT; -- was GND33, hack for 3000 family + UNUSED1 : INPUT; + UNUSED2 : INPUT; + UNUSED5 : INPUT; + UNUSED7 : INPUT; + UNUSED22 : INPUT; + UNUSED24 : INPUT; + UNUSED27 : INPUT; + UNUSED28 : INPUT; + UNUSED49 : INPUT; + UNUSED50 : INPUT; + UNUSED53 : INPUT; + UNUSED55 : INPUT; + UNUSED63 : INPUT; + UNUSED70 : INPUT; + UNUSED72 : INPUT; + UNUSED77 : INPUT; + UNUSED78 : INPUT; + + ) VARIABLE diff --git a/src/altera/max/SP2_MAX_7064.pof b/src/altera/max/SP2_MAX_7064.pof deleted file mode 100644 index a007125..0000000 Binary files a/src/altera/max/SP2_MAX_7064.pof and /dev/null differ diff --git a/src/altera/max/SP2_MAX_7128.pof b/src/altera/max/SP2_MAX_7128.pof index fb189cd..7cc9468 100644 Binary files a/src/altera/max/SP2_MAX_7128.pof and b/src/altera/max/SP2_MAX_7128.pof differ diff --git a/src/altera/max/clean.bat b/src/altera/max/clean.bat index d7e8d5b..4496ad1 100644 --- a/src/altera/max/clean.bat +++ b/src/altera/max/clean.bat @@ -12,7 +12,7 @@ del *.mtb del *.hex del *.ndb del *.pin -rem del *.pof +del *.pof del *.snf del *.fit del *.jam diff --git a/src/altera/max/compile.log b/src/altera/max/compile.log index c74cadf..d1f3d16 100644 --- a/src/altera/max/compile.log +++ b/src/altera/max/compile.log @@ -1 +1,214 @@ -06.07.2022 05:20: [2/2] ALTERA MAX-7128 STREAM +07.09.2022 00:27: [2/2] ALTERA MAX-7128 STREAM +7128\SP2_MAX.ACF +Скопировано файлов: 1. + +********************************************************************** +MAX+plus II +Version 10.0 9/14/2000 +Copyright (c) 1988-2000 Altera Corporation. All rights reserved. + +This material is made available for use under a license from Altera +and its use is subject to all conditions and restrictions provided +by the license agreement. U.S. and foreign patents apply to the +software program and the semiconductor components which are programmed +using the software program. + +This program, these components, and the system comprising both +are covered by one or more of the following U.S. patents: + +6,097,211; 6,094,064; 6,091,258; 6,091,102; 6,085,317; 6,084,427; +6,081,449; 6,080,204; 6,078,521; 6,076,179; 6,075,380; 6,072,358; +6,072,332; 6,069,487; 6,066,960; 6,064,599; 6,060,903; 6,058,452; +6,057,707; 6,052,755; 6,052,309; 6,052,327; 6,049,223; 6,049,225; +6,045,252; 6,043,676; 6,040,712; 6,038,171; 6,037,829; 6,034,857; +6,034,540; 6,034,536; 6,032,159; 6,031,763; 6,031,391; 6,029,236; +6,028,809; 6,028,808; 6,028,787; 6,026,226; 6,025,737; 6,023,439; +6,020,760; 6,020,759; 6,020,758; 6,018,490; 6,018,476; 6,014,334; +6,011,744; 6,011,730; 6,011,406; 6,005,379; 5,999,016; 5,999,015; +5,998,295; 5,996,039; 5,986,470; 5,986,465; 5,983,277; 5,982,195; +5,978,476; 5,977,793; 5,977,791; 5,968,161; 5,970,255; 5,966,597; +5,963,565; 5,969,051; 5,963,069; 5,963,049; 5,959,891; 5,953;537; +5,949,991; 5,949,710; 5,949,250; 5,949,239; 5,954,751; 5,943,267; +5,942,914; 5,940,852; 5,939,790; 5,936,425; 5,926,036; 5,925,904; +5,923,567; 5,915,756; 5,915,017; 5,909,450; 5,909,375; 5,909,126; +5,905,675; 5,904,524; 5,900,743; 5,898,628; 5,898,318; 5,894,228; +5,893,088; 5,892,683; 5,883,526; 5,880,725; 5,880,597; 5,880,596; +5,878,250; 5,875,112; 5,873,113; 5,872,529; 5,872,463; 5,870,410; +5,869,980; 5,869,979; 5,861,760; 5,859,544; 5,859,542; 5,850,365; +5,850,152; 5,850,151; 5,848,005; 5,847,617; 5,845,385; 5,844,854; +RE35,977; 5,838,628; 5,838,584; 5,835,998; 5,834,849; 5,828,229; +5,825,197; 5,821,787: 5,821,773; 5,821,771; 5,815,726; 5,815,024; +5,815,003; 5,812,479; 5,812,450; 5,809,281; 5,809,034; 5,805,516; +5,802,540; 5,801,541; 5,796,267; 5,793,246; 5,790,469; 5,787,009; +5,771,264; 5,768,562; 5,768,372; 5,767,734; 5,764,583; 5,764,569; +5,764,080; 5,764,079; 5,761,099; 5,760,624; 5,757,207; 5,757,070; +5,744,991; 5,744,383; 5,740,110; 5,732,020; 5,729,495; 5,717,901; +5,705,939; 5,699,020; 5,699,312; 5,696,455; 5,693,540; 5,694,058; +5,691,653; 5,689,195; 5,668,771; 5,680,061; 5,672,985; 5,670,895; +5,659,717; 5,650,734; 5,649,163; 5,642,262; 5,642,082; 5,633,830; +5,631,576; 5,621,312; 5,614,840; 5,612,642; 5,608,337; 5,606,276; +5,606,266; 5,604,453; 5,598,109; 5,598,108; 5,592,106; 5,592,102; +5,590,305; 5,583,749; 5,581,501; 5,574,893; 5,572,717; 5,572,148; +5,572,067; 5,570,040; 5,567,177; 5,565,793; 5,563,592; 5,561,757; +5,557,217; 5,555,214; 5,550,842; 5,550,782; 5,548,552; 5,548,228; +5,543,732; 5,543,730; 5,541,530; 5,537,295; 5,537,057; 5,525,917; +5,525,827; 5,523,706; 5,523,247; 5,517,186; 5,498,975; 5,495,182; +5,493,526; 5,493,519; 5,490,266; 5,488,586; 5,487,143; 5,486,775; +5,485,103; 5,485,102; 5,483,178; 5,477,474; 5,473,266; 5,463,328, +5,444,394; 5,438,295; 5,436,575; 5,436,574; 5,434,514; 5,432,467; +5,414,312; 5,399,922; 5,384,499; 5,376,844; 5,371,422; 5,369,314; +5,359,243; 5,359,242; 5,353,248; 5,352,940; 5,309,046; 5,350,954; +5,349,255; 5,341,308; 5,341,048; 5,341,044; 5,329,487; 5,317,210; +5,315,172; 5,301,416; 5,294,975; 5,285,153; 5,280,203; 5,274,581; +5,272,368; 5,268,598; 5,266,037; 5,260,611; 5,260,610; 5,258,668; +5,247,478; 5,247,477; 5,243,233; 5,241,224; 5,237,219; 5,220,533; +5,220,214; 5,200,920; 5,187,392; 5,166,604; 5,162,680; 5,144,167; +5,138,576; 5,128,565; 5,121,006; 5,111,423; 5,097,208; 5,091,661; +5,066,873; 5,045,772; 4,969,121; 4,930,107; 4,930,098; 4,930,097; +4,912,342; 4,903,223; 4,899,070; 4,899,067; 4,871,930; 4,864,161; +4,831,573; 4,785,423; 4,774,421; 4,713,792; 4,677,318; 4,617,479; +4,609,986; 4,020,469; Additional patents are pending. + +Altera Corporation acknowledges the trademarks of other organizations +for their respective products or services mentioned in this software. + +********************************************************************** +Compiling project f:\sprinter\src\altera\max\sp2_max .... + +**** Compiler Netlist Extractor **** + +Processing . -- 0% done +Warning: Line 106, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED78" was declared but never used +Warning: Line 52, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "XA2" was declared but never used +Warning: Line 167, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "CTV8C" was declared but never used +Warning: Line 89, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED33" was declared but never used +Warning: Line 52, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "XA1" was declared but never used +Warning: Line 93, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED7" was declared but never used +Warning: Line 83, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "XHR_RDY" was declared but never used +Warning: Line 52, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "XA0" was declared but never used +Warning: Line 103, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED70" was declared but never used +Warning: Line 101, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED55" was declared but never used +Warning: Line 92, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED5" was declared but never used +Warning: Line 162, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "EXP_X" was declared but never used +Warning: Line 94, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED22" was declared but never used +Warning: Line 91, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED2" was declared but never used +Warning: Line 98, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED49" was declared but never used +Warning: Line 104, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED72" was declared but never used +Warning: Line 163, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "EXP_Y" was declared but never used +Warning: Line 100, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED53" was declared but never used +Warning: Line 70, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "VGA_IN" was declared but never used +Warning: Line 95, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED24" was declared but never used +Warning: Line 99, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED50" was declared but never used +Warning: Line 88, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED65" was declared but never used +Warning: Line 90, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED1" was declared but never used +Warning: Line 105, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED77" was declared but never used +Warning: Line 75, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "SINC_IN" was declared but never used +Warning: Line 102, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED63" was declared but never used +Warning: Line 96, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED27" was declared but never used +Warning: Line 97, File f:\sprinter\src\altera\max\sp2_max.tdf: +Symbolic name "UNUSED28" was declared but never used +Processing .. -- 100% done +Warning: Timing requirement assignments influence compilation only for FLEX 6000, FLEX 8000, and FLEX 10K devices. However, the Compiler will check whether it can meet your timing requirements. + +**** Database Builder **** + +Processing . -- 0% done +Processing .. -- 100% done + +**** Logic Synthesizer **** + +Processing . -- 0% done +Warning: Flipflop 'CTV8M' stuck at GND +Warning: No Clock transition on flipflop 'CNF_OFF' +Warning: Primitive 'BEEP' is stuck at GND +Warning: Primitive 'DENS_X' is stuck at VCC +Warning: Primitive 'HD_CS' is stuck at GND +Info: NOT Gate Push-Back has occurred on some registers -- if the power-up condition is crucial to the operation of the circuit, use the asynchronous Clear/Preset on the register to ensure proper operation +Processing .. -- 100% done + +**** Partitioner **** + +Processing . -- 0% done +Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead. +Info: Reserved unused input pin 'XA2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'XA1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'XA0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'VGA_IN' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'SINC_IN' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'XHR_RDY' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED65' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED33' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED22' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED24' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED27' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED28' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED49' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED50' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED53' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED55' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED63' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED70' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED72' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED77' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED78' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Processing .. -- 100% done + +**** Fitter **** + +Processing . -- 0% done +Info: Chip 'SP2_MAX' in device 'EPM7128STC100-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device +Processing .. -- 100% done + +**** Timing SNF Extractor **** + +Processing . -- 0% done +Processing .. -- 100% done +Warning: Found ripple clock -- warning messages and Report File information on tco, tsu, and fmax may be inaccurate +Info: One or more paths have been found between registers controlled by different clocks -- can't calculate fmax for those paths +Warning: Can't provide fmax of 100.00 MHz on Clock pin "RSTB". Current fmax is 43.47 MHz. +Warning: Can't provide fmax of 100.00 MHz on Clock pin "STE". Current fmax is 43.47 MHz. +Warning: Can't provide fmax of 100.00 MHz on Clock pin "TG42_IN". Current fmax is 27.02 MHz. +Warning: Can't provide fmax of 100.00 MHz on Clock pin "WSTB". Current fmax is 43.47 MHz. +Info: Found a total of 4 timing assignments that were not implemented +Project compilation was successful + 0 errors + 39 warnings +Не удается найти F:\Sprinter\src\altera\max\*.txt +Не удается найти F:\Sprinter\src\altera\max\*.bak +Не удается найти F:\Sprinter\src\altera\max\*.db? +Не удается найти F:\Sprinter\src\altera\max\*.mtb +Не удается найти F:\Sprinter\src\altera\max\*.hex +Не удается найти F:\Sprinter\src\altera\max\*.SCF +Не удается найти F:\Sprinter\src\altera\max\*.INC +Не удается найти F:\Sprinter\src\altera\max\*.MIF diff --git a/src/altera/max/make.cmd b/src/altera/max/make.cmd index bca748a..faeff7e 100644 --- a/src/altera/max/make.cmd +++ b/src/altera/max/make.cmd @@ -1,49 +1,46 @@ -@set BIN=..\..\bin\ -@set CHIP=7128 +@echo off +@echo off +set BIN=..\..\bin\ +set LOG=compile.log +for /F %%i in ('date /t') do set mydate=%%i +for /F %%i in ('time /t') do set mytime=%%i +set mydt=%mydate% %mytime% -@echo STEP 0, Task [2/2] ALTERA MAX-%CHIP% STREAM +set CHIP=7128 -@if exist SP2_MAX_%CHIP%.pof goto quit +echo 0. [2/2] ALTERA MAX-%CHIP% STREAM +echo %mydt%: [2/2] ALTERA MAX-%CHIP% STREAM > %LOG% -@copy %CHIP%\*.ACF .\*.* +if exist SP2_MAX_%CHIP%.pof goto quit -@C:\MAXPLUS2\MAXPLUS2.EXE -compile SP2_MAX +copy %CHIP%\*.ACF .\*.* >> %LOG% 2>&1 -@del *.txt -@del *.bak -@del *.cnf -@del *.db? +C:\MAXPLUS2\MAXPLUS2.EXE -compile SP2_MAX >> %LOG% -@del *.hif -@del *.mmf -@del *.mtf -@del *.mtb -@del *.hex -@del *.ndb -@del *.pin -@rem del *.pof -@del *.snf -@del *.fit -@del *.jam -@del *.jbc +del *.txt >> %LOG% 2>&1 +del *.bak >> %LOG% 2>&1 +del *.cnf >> %LOG% 2>&1 +del *.db? >> %LOG% 2>&1 -@del *.SCF -@del *.ACF -@rem del *.TDF -@del *.INC -@del *.MIF +del *.hif >> %LOG% 2>&1 +del *.mmf >> %LOG% 2>&1 +del *.mtf >> %LOG% 2>&1 +del *.mtb >> %LOG% 2>&1 +del *.hex >> %LOG% 2>&1 +del *.ndb >> %LOG% 2>&1 +del *.pin >> %LOG% 2>&1 +rem del *.pof >> %LOG% 2>&1 +del *.snf >> %LOG% 2>&1 +del *.fit >> %LOG% 2>&1 +del *.jam >> %LOG% 2>&1 +del *.jbc >> %LOG% 2>&1 -@ren SP2_MAX.pof SP2_MAX_%CHIP%.pof -@if errorlevel 1 goto error +del *.SCF >> %LOG% 2>&1 +del *.ACF >> %LOG% 2>&1 +rem del *.TDF >> %LOG% 2>&1 +del *.INC >> %LOG% 2>&1 +del *.MIF >> %LOG% 2>&1 + +ren SP2_MAX.pof SP2_MAX_%CHIP%.pof >> %LOG% 2>&1 :quit -@echo [OK ] -@echo --------------------------------------------------------------------------[Compiling bitstreams DONE] -@goto :eof - -:error -@color 04 -@echo ---------------------------------------------------------------------[Compiling bitstream ERROR!!!] -@echo. -@pause 0 -@exit 3 diff --git a/src/altera/max/sp2_max.rpt b/src/altera/max/sp2_max.rpt index e80fe87..92b7c72 100644 --- a/src/altera/max/sp2_max.rpt +++ b/src/altera/max/sp2_max.rpt @@ -1,8 +1,8 @@ -Project Information c:\sprinter\src\altera\max\sp2_max.rpt +Project Information f:\sprinter\src\altera\max\sp2_max.rpt MAX+plus II Compiler Report File Version 10.0 9/14/2000 -Compiled: 07/02/2022 02:06:11 +Compiled: 09/07/2022 00:27:59 Copyright (C) 1988-2000 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), @@ -37,38 +37,72 @@ SINC_controller Chip/ Input Output Bidir Shareable POF Device Pins Pins Pins LCs Expanders % Utilized -SP2_MAX EPM7128STC100-10 29 30 4 64 40 50 % +SP2_MAX EPM7128STC100-10 46 30 4 64 40 50 % -User Pins: 29 30 4 +User Pins: 46 30 4 -Project Information c:\sprinter\src\altera\max\sp2_max.rpt +Project Information f:\sprinter\src\altera\max\sp2_max.rpt ** PROJECT COMPILATION MESSAGES ** -Warning: Line 52, File c:\sprinter\src\altera\max\sp2_max.tdf: +Warning: Line 106, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED78" was declared but never used +Warning: Line 52, File f:\sprinter\src\altera\max\sp2_max.tdf: Symbolic name "XA2" was declared but never used -Warning: Line 148, File c:\sprinter\src\altera\max\sp2_max.tdf: +Warning: Line 167, File f:\sprinter\src\altera\max\sp2_max.tdf: Symbolic name "CTV8C" was declared but never used -Warning: Line 88, File c:\sprinter\src\altera\max\sp2_max.tdf: - Symbolic name "GND65" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\max\sp2_max.tdf: +Warning: Line 89, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED33" was declared but never used +Warning: Line 52, File f:\sprinter\src\altera\max\sp2_max.tdf: Symbolic name "XA1" was declared but never used -Warning: Line 83, File c:\sprinter\src\altera\max\sp2_max.tdf: +Warning: Line 93, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED7" was declared but never used +Warning: Line 83, File f:\sprinter\src\altera\max\sp2_max.tdf: Symbolic name "XHR_RDY" was declared but never used -Warning: Line 52, File c:\sprinter\src\altera\max\sp2_max.tdf: +Warning: Line 52, File f:\sprinter\src\altera\max\sp2_max.tdf: Symbolic name "XA0" was declared but never used -Warning: Line 143, File c:\sprinter\src\altera\max\sp2_max.tdf: +Warning: Line 103, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED70" was declared but never used +Warning: Line 101, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED55" was declared but never used +Warning: Line 92, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED5" was declared but never used +Warning: Line 162, File f:\sprinter\src\altera\max\sp2_max.tdf: Symbolic name "EXP_X" was declared but never used -Warning: Line 144, File c:\sprinter\src\altera\max\sp2_max.tdf: +Warning: Line 94, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED22" was declared but never used +Warning: Line 91, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED2" was declared but never used +Warning: Line 98, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED49" was declared but never used +Warning: Line 104, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED72" was declared but never used +Warning: Line 163, File f:\sprinter\src\altera\max\sp2_max.tdf: Symbolic name "EXP_Y" was declared but never used -Warning: Line 70, File c:\sprinter\src\altera\max\sp2_max.tdf: +Warning: Line 100, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED53" was declared but never used +Warning: Line 70, File f:\sprinter\src\altera\max\sp2_max.tdf: Symbolic name "VGA_IN" was declared but never used -Warning: Line 75, File c:\sprinter\src\altera\max\sp2_max.tdf: +Warning: Line 95, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED24" was declared but never used +Warning: Line 99, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED50" was declared but never used +Warning: Line 88, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED65" was declared but never used +Warning: Line 90, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED1" was declared but never used +Warning: Line 105, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED77" was declared but never used +Warning: Line 75, File f:\sprinter\src\altera\max\sp2_max.tdf: Symbolic name "SINC_IN" was declared but never used -Warning: Line 89, File c:\sprinter\src\altera\max\sp2_max.tdf: - Symbolic name "GND33" was declared but never used +Warning: Line 102, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED63" was declared but never used +Warning: Line 96, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED27" was declared but never used +Warning: Line 97, File f:\sprinter\src\altera\max\sp2_max.tdf: + Symbolic name "UNUSED28" was declared but never used Warning: Flipflop 'CTV8M' stuck at GND Warning: No Clock transition on flipflop 'CNF_OFF' Warning: Primitive 'BEEP' is stuck at GND @@ -81,8 +115,25 @@ Info: Reserved unused input pin 'XA0' for future use because it has a pin assign Info: Reserved unused input pin 'VGA_IN' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'SINC_IN' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board Info: Reserved unused input pin 'XHR_RDY' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board -Info: Reserved unused input pin 'GND65' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board -Info: Reserved unused input pin 'GND33' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED65' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED33' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED22' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED24' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED27' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED28' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED49' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED50' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED53' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED55' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED63' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED70' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED72' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED77' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board +Info: Reserved unused input pin 'UNUSED78' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board ** PROJECT TIMING MESSAGES ** @@ -94,7 +145,7 @@ Warning: Can't provide fmax of 100.00 MHz on Clock pin "TG42_IN". Current fmax i Warning: Can't provide fmax of 100.00 MHz on Clock pin "WSTB". Current fmax is 43.47 MHz. -Project Information c:\sprinter\src\altera\max\sp2_max.rpt +Project Information f:\sprinter\src\altera\max\sp2_max.rpt ** PIN/LOCATION/CHIP ASSIGNMENTS ** @@ -118,8 +169,6 @@ SP2_MAX@14 FDAT SP2_MAX@44 FDD_C0 SP2_MAX@45 FDD_C1 SP2_MAX@46 FDD_C2 -SP2_MAX@33 GND33 -SP2_MAX@65 GND65 SP2_MAX@52 HD_CS SP2_MAX@47 HDD_C0 SP2_MAX@42 HDD_C1 @@ -143,6 +192,25 @@ SP2_MAX@36 TG42_BUF SP2_MAX@87 TG42_IN SP2_MAX@85 TG42_OUT SP2_MAX@12 TR43 +SP2_MAX@1 UNUSED1 +SP2_MAX@2 UNUSED2 +SP2_MAX@5 UNUSED5 +SP2_MAX@7 UNUSED7 +SP2_MAX@22 UNUSED22 +SP2_MAX@24 UNUSED24 +SP2_MAX@27 UNUSED27 +SP2_MAX@28 UNUSED28 +SP2_MAX@33 UNUSED33 +SP2_MAX@49 UNUSED49 +SP2_MAX@50 UNUSED50 +SP2_MAX@53 UNUSED53 +SP2_MAX@55 UNUSED55 +SP2_MAX@63 UNUSED63 +SP2_MAX@65 UNUSED65 +SP2_MAX@70 UNUSED70 +SP2_MAX@72 UNUSED72 +SP2_MAX@77 UNUSED77 +SP2_MAX@78 UNUSED78 SP2_MAX@61 VGA_IN SP2_MAX@9 WD SP2_MAX@98 WDAT @@ -167,7 +235,7 @@ SP2_MAX@56 10K_CLK SP2_MAX@58 10K_D0 -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ***** Logic for device 'SP2_MAX' compiled without errors. @@ -184,30 +252,38 @@ Device Options: User Code = ffff MultiVolt I/O = OFF - C C T X X X X R R - M M P E X T G H H H H E E - O O / D / V W P H G 4 D D D D S S X - S S W E W C _ M R 4 2 2 V 2 1 1 E E H - _ _ W G N G R C G _ _ 2 _ B _ C _ _ _ R R D - D D D _ S G S _ D I O R R _ G O E C C C C C V V _ - W R A R _ N T W A N O E D I N U E S I S S S E E R - R D T D X D E R T T D S Y N D T P 2 O 1 2 1 D D D + + +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt +SP2_MAX + +** ERROR SUMMARY ** + +Info: Chip 'SP2_MAX' in device 'EPM7128STC100-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device + C C T X X X X U U + M M P E X T G H H H H N N + O O / D / V W P H G 4 D D D D U U X + S S W E W C _ M R 4 2 2 V 2 1 1 S S H + _ _ W G N G R C G _ _ 2 _ B _ C _ _ _ E E D + D D D _ S G S _ D I O R R _ G O E C C C C C D D _ + W R A R _ N T W A N O E D I N U E S I S S S 7 7 R + R D T D X D E R T T D S Y N D T P 2 O 1 2 1 8 7 D ----------------------------------------------------_ / 100 98 96 94 92 90 88 86 84 82 80 78 76 |_ / 99 97 95 93 91 89 87 85 83 81 79 77 | -RESERVED | 1 75 | XHD_WR -RESERVED | 2 74 | GND + UNUSED1 | 1 75 | XHD_WR + UNUSED2 | 2 74 | GND VCCIO | 3 73 | #TDO - #TDI | 4 72 | RESERVED -RESERVED | 5 71 | XHD_RES - CMOS_AS | 6 70 | RESERVED -RESERVED | 7 69 | SINC_IN + #TDI | 4 72 | UNUSED72 + UNUSED5 | 5 71 | XHD_RES + CMOS_AS | 6 70 | UNUSED70 + UNUSED7 | 7 69 | SINC_IN WR_PDOS | 8 68 | SINC_H WD | 9 67 | SINC WSTB | 10 66 | VCCIO - GND | 11 65 | GND65 + GND | 11 65 | UNUSED65 TR43 | 12 64 | SINC_V - CLK_WG | 13 EPM7128STC100-10 63 | RESERVED + CLK_WG | 13 EPM7128STC100-10 63 | UNUSED63 FDAT | 14 62 | #TCK #TMS | 15 61 | VGA_IN QDAT | 16 60 | D0 @@ -215,22 +291,22 @@ RESERVED | 7 69 | SINC_IN VCCIO | 18 58 | 10K_D0 SINC_2 | 19 57 | WR_CNF SINC_1 | 20 56 | 10K_CLK - XA1 | 21 55 | RESERVED -RESERVED | 22 54 | /CONF_X - XA2 | 23 53 | RESERVED -RESERVED | 24 52 | HD_CS + XA1 | 21 55 | UNUSED55 +UNUSED22 | 22 54 | /CONF_X + XA2 | 23 53 | UNUSED53 +UNUSED24 | 24 52 | HD_CS RSTB | 25 51 | VCCIO | 27 29 31 33 35 37 39 41 43 45 47 49 _| \ 26 28 30 32 34 36 38 40 42 44 46 48 50 | \----------------------------------------------------- - G R R S S C C G V A T X G V H H H G F F F H H R R - N E E R L L L N C U G A N C D D D N D D D D D E E - D S S K K D C D 4 C D C D D D D D D D D _ S S - E E 1 Z 3 I 2 S I _ _ _ _ _ _ _ D E E - R R 4 Z 3 O _ N C C C C C C C I R R - V V B T 3 2 1 0 1 2 0 R V V - E E U E E - D D F D D + G U U S S C C U V A T X G V H H H G F F F H H U U + N N N R L L L N C U G A N C D D D N D D D D D N N + D U U K K U C D 4 C D C D D D D D D D D _ U U + S S 1 Z S I 2 S I _ _ _ _ _ _ _ D S S + E E 4 Z E O _ N C C C C C C C I E E + D D D B T 3 2 1 0 1 2 0 R D D + 2 2 3 U 4 5 + 7 8 3 F 9 0 N.C. = No Connect. This pin has no internal connection to the device. @@ -248,7 +324,7 @@ PDn = Power Down pin. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** RESOURCE USAGE ** @@ -256,18 +332,18 @@ SP2_MAX Shareable External Logic Array Block Logic Cells I/O Pins Expanders Interconnect -A: LC1 - LC16 6/16( 37%) 8/10( 80%) 2/16( 12%) 13/36( 36%) -B: LC17 - LC32 14/16( 87%) 8/10( 80%) 16/16(100%) 29/36( 80%) -C: LC33 - LC48 16/16(100%) 8/10( 80%) 6/16( 37%) 26/36( 72%) -D: LC49 - LC64 6/16( 37%) 8/10( 80%) 2/16( 12%) 6/36( 16%) -E: LC65 - LC80 1/16( 6%) 8/10( 80%) 1/16( 6%) 6/36( 16%) -F: LC81 - LC96 4/16( 25%) 8/10( 80%) 3/16( 18%) 17/36( 47%) -G: LC97 - LC112 8/16( 50%) 7/10( 70%) 5/16( 31%) 31/36( 86%) -H: LC113 - LC128 9/16( 56%) 8/10( 80%) 7/16( 43%) 12/36( 33%) +A: LC1 - LC16 6/16( 37%) 10/10(100%) 2/16( 12%) 13/36( 36%) +B: LC17 - LC32 14/16( 87%) 10/10(100%) 11/16( 68%) 28/36( 77%) +C: LC33 - LC48 16/16(100%) 10/10(100%) 6/16( 37%) 26/36( 72%) +D: LC49 - LC64 6/16( 37%) 10/10(100%) 2/16( 12%) 6/36( 16%) +E: LC65 - LC80 2/16( 12%) 10/10(100%) 6/16( 37%) 12/36( 33%) +F: LC81 - LC96 4/16( 25%) 10/10(100%) 3/16( 18%) 17/36( 47%) +G: LC97 - LC112 8/16( 50%) 10/10(100%) 5/16( 31%) 31/36( 86%) +H: LC113 - LC128 8/16( 50%) 10/10(100%) 7/16( 43%) 11/36( 30%) Total dedicated input pins used: 4/4 (100%) -Total I/O pins used: 63/80 ( 78%) +Total I/O pins used: 80/80 (100%) Total logic cells used: 64/128 ( 50%) Total shareable expanders used: 40/128 ( 31%) Total Turbo logic cells used: 55/128 ( 42%) @@ -275,7 +351,7 @@ Total shareable expanders not available (n/a): 2/128 ( 1%) Average fan-in: 5.73 Total fan-in: 367 -Total input pins required: 29 +Total input pins required: 46 Total fast input logic cells required: 0 Total output pins required: 30 Total bidirectional pins required: 4 @@ -290,7 +366,7 @@ Synthesized logic cells: 0/ 128 ( 0%) -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** INPUTS ** @@ -305,8 +381,6 @@ SP2_MAX 44 (70) (E) INPUT 0 0 0 0 0 13 0 FDD_C0 45 (72) (E) INPUT 0 0 0 0 0 16 0 FDD_C1 46 (73) (E) INPUT 0 0 0 0 0 14 0 FDD_C2 - 33 (54) (D) INPUT 0 0 0 0 0 0 0 GND33 - 65 (101) (G) INPUT 0 0 0 0 0 0 0 GND65 47 (75) (E) INPUT 0 0 0 0 0 17 0 HDD_C0 42 (69) (E) INPUT 0 0 0 0 0 16 0 HDD_C1 41 (67) (E) INPUT 0 0 0 0 0 16 0 HDD_C2 @@ -322,6 +396,25 @@ SP2_MAX 94 (13) (A) INPUT 0 0 0 0 0 0 1 STE 87 - - INPUT 0 0 0 0 0 7 1 TG42_IN 12 (21) (B) INPUT 0 0 0 0 0 0 2 TR43 + 1 (3) (A) INPUT 0 0 0 0 0 0 0 UNUSED1 + 2 (1) (A) INPUT 0 0 0 0 0 0 0 UNUSED2 + 5 (30) (B) INPUT 0 0 0 0 0 0 0 UNUSED5 + 7 (27) (B) INPUT 0 0 0 0 0 0 0 UNUSED7 + 22 (38) (C) INPUT 0 0 0 0 0 0 0 UNUSED22 + 24 (35) (C) INPUT 0 0 0 0 0 0 0 UNUSED24 + 27 (64) (D) INPUT 0 0 0 0 0 0 0 UNUSED27 + 28 (62) (D) INPUT 0 0 0 0 0 0 0 UNUSED28 + 33 (54) (D) INPUT 0 0 0 0 0 0 0 UNUSED33 + 49 (78) (E) INPUT 0 0 0 0 0 0 0 UNUSED49 + 50 (80) (E) INPUT 0 0 0 0 0 0 0 UNUSED50 + 53 (83) (F) INPUT 0 0 0 0 0 0 0 UNUSED53 + 55 (86) (F) INPUT 0 0 0 0 0 0 0 UNUSED55 + 63 (97) (G) INPUT 0 0 0 0 0 0 0 UNUSED63 + 65 (101) (G) INPUT 0 0 0 0 0 0 0 UNUSED65 + 70 (107) (G) INPUT 0 0 0 0 0 0 0 UNUSED70 + 72 (110) (G) INPUT 0 0 0 0 0 0 0 UNUSED72 + 77 (117) (H) INPUT 0 0 0 0 0 0 0 UNUSED77 + 78 (118) (H) INPUT 0 0 0 0 0 0 0 UNUSED78 61 (94) (F) INPUT 0 0 0 0 0 0 0 VGA_IN 9 (24) (B) INPUT 0 0 0 0 0 0 2 WD 57 (89) (F) INPUT 0 0 0 0 0 1 0 WR_CNF @@ -343,7 +436,7 @@ t = Turbo logic cell r = Fitter-inserted logic cell -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** OUTPUTS ** @@ -397,7 +490,7 @@ t = Turbo logic cell r = Fitter-inserted logic cell -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** BURIED LOGIC ** @@ -405,36 +498,36 @@ SP2_MAX Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name - (77) 117 H DFFE t 0 0 0 1 1 2 0 CNF_OFF + (12) 21 B DFFE t 0 0 0 1 1 2 0 CNF_OFF (21) 40 C TFFE t 0 0 0 0 1 1 4 CTH0 - 39 C TFFE t 0 0 0 0 2 1 3 CTH1 - (15) 48 C TFFE t 0 0 0 0 5 2 3 CTH2 - (23) 37 C TFFE t 0 0 0 0 6 2 2 CTH3 - (17) 45 C TFFE t 0 0 0 0 7 2 1 CTH4 - - 103 G DFFE t 1 1 0 0 4 1 8 CTV0 - (69) 105 G DFFE t 1 1 0 0 4 1 8 CTV1 - (25) 33 C DFFE t 1 1 0 0 5 2 6 CTV2 - (24) 35 C TFFE t 1 1 0 0 6 2 5 CTV3 - - 44 C TFFE t 1 1 0 0 7 2 4 CTV4 - (22) 38 C TFFE t 1 1 0 0 8 2 3 CTV5 - - 34 C TFFE t 1 1 0 0 9 2 2 CTV6 - - 47 C TFFE t 1 1 0 0 10 2 1 CTV7 - - 20 B TFFE t 5 0 0 3 3 2 5 CT_WG - (12) 21 B TFFE t 0 0 0 0 1 3 7 CT0 - - 18 B TFFE t 0 0 0 0 2 1 1 CT1 + (17) 45 C TFFE t 0 0 0 0 5 2 3 CTH2 + (24) 35 C TFFE t 0 0 0 0 6 2 2 CTH3 + (23) 37 C TFFE t 0 0 0 0 7 2 1 CTH4 + (69) 105 G DFFE t 1 1 0 0 4 1 8 CTV0 + - 103 G DFFE t 1 1 0 0 4 1 8 CTV1 + (22) 38 C DFFE t 1 1 0 0 5 2 6 CTV2 + - 36 C TFFE t 1 1 0 0 6 2 5 CTV3 + - 34 C TFFE t 1 1 0 0 7 2 4 CTV4 + - 47 C TFFE t 1 1 0 0 8 2 3 CTV5 + (15) 48 C TFFE t 1 1 0 0 9 2 2 CTV6 + - 44 C TFFE t 1 1 0 0 10 2 1 CTV7 + (40) 65 E TFFE t 5 0 0 3 3 2 5 CT_WG + - 23 B TFFE t 0 0 0 0 1 3 7 CT0 + - 20 B TFFE t 0 0 0 0 2 1 1 CT1 - 58 D TFFE t 0 0 0 0 3 1 0 CT2 - (65) 101 G DFFE t 0 0 0 3 1 1 2 LR_T0 - - 100 G DFFE t 0 0 0 3 1 1 2 LR_T1 - - 23 B DFFE t 1 1 0 0 5 1 2 REG_P0 - - 26 B DFFE t 1 1 0 0 5 1 2 REG_P1 - (9) 24 B TFFE t 2 2 0 0 2 1 1 STWG0 - (7) 27 B TFFE t 2 2 0 0 3 1 0 STWG1 + - 98 G DFFE t 0 0 0 3 1 1 2 LR_T0 + (65) 101 G DFFE t 0 0 0 3 1 1 2 LR_T1 + - 26 B DFFE t 1 1 0 0 5 1 2 REG_P0 + (10) 22 B DFFE t 1 1 0 0 5 1 2 REG_P1 + (7) 27 B TFFE t 2 2 0 0 2 1 1 STWG0 + (5) 30 B TFFE t 2 2 0 0 3 1 0 STWG1 - 42 C TFFE t 3 3 0 0 8 1 4 WGR0 - - 36 C TFFE t 4 3 1 0 8 1 4 WGR1 + (25) 33 C TFFE t 4 3 1 0 8 1 4 WGR1 - 28 B TFFE t 3 3 0 0 8 1 4 WGR2 (4) 32 B TFFE t 3 3 0 0 8 1 4 WGR3 (37) 49 D TFFE t 2 2 0 1 1 2 0 XCT0 - (10) 22 B DFFE t 7 7 0 1 3 1 0 :180 + (9) 24 B DFFE t 7 7 0 1 3 1 0 :197 Code: @@ -447,7 +540,7 @@ t = Turbo logic cell r = Fitter-inserted logic cell -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** LOGIC CELL INTERCONNECTIONS ** @@ -478,11 +571,11 @@ Pin 90 -> - - - - - - | - - - - - - * - | <-- PW_GOOD 87 -> - - - - - - | - - - * - * - * | <-- TG42_IN 88 -> - - - - - - | - - - - - - - - | <-- XHR_RDY -LC20 -> - - - * - - | * * - - - - - - | <-- CT_WG -LC101-> - - - * - - | * * - - - - - - | <-- LR_T0 -LC100-> - - - * - - | * * - - - - - - | <-- LR_T1 -LC23 -> - - - * - - | * * - - - - - - | <-- REG_P0 -LC26 -> - - - * - - | * * - - - - - - | <-- REG_P1 +LC65 -> - - - * - - | * * - - * - - - | <-- CT_WG +LC98 -> - - - * - - | * * - - - - - - | <-- LR_T0 +LC101-> - - - * - - | * * - - - - - - | <-- LR_T1 +LC26 -> - - - * - - | * * - - - - - - | <-- REG_P0 +LC22 -> - - - * - - | * * - - - - - - | <-- REG_P1 LC88 -> * * - - * * | * * - - * * - * | <-- 10K_CLK @@ -490,7 +583,7 @@ LC88 -> * * - - * * | * * - - * * - * | <-- 10K_CLK - = The logic cell or pin is not an input to the logic cell (or LAB). -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** LOGIC CELL INTERCONNECTIONS ** @@ -500,33 +593,32 @@ Logic Array Block 'B': Logic cells placed in LAB 'B' +--------------------------- LC19 CLK_WG | +------------------------- LC29 CMOS_AS - | | +----------------------- LC20 CT_WG - | | | +--------------------- LC21 CT0 - | | | | +------------------- LC18 CT1 + | | +----------------------- LC21 CNF_OFF + | | | +--------------------- LC23 CT0 + | | | | +------------------- LC20 CT1 | | | | | +----------------- LC17 FDAT - | | | | | | +--------------- LC23 REG_P0 - | | | | | | | +------------- LC26 REG_P1 - | | | | | | | | +----------- LC24 STWG0 - | | | | | | | | | +--------- LC27 STWG1 + | | | | | | +--------------- LC26 REG_P0 + | | | | | | | +------------- LC22 REG_P1 + | | | | | | | | +----------- LC27 STWG0 + | | | | | | | | | +--------- LC30 STWG1 | | | | | | | | | | +------- LC28 WGR2 | | | | | | | | | | | +----- LC32 WGR3 | | | | | | | | | | | | +--- LC25 WR_PDOS - | | | | | | | | | | | | | +- LC22 :180 + | | | | | | | | | | | | | +- LC24 :197 | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | | | | | that feed LAB 'B' LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B': LC19 -> * - - - - - - - * * - - - - | - * - - - - * - | <-- CLK_WG -LC20 -> * - * - - - * * * * - - - - | * * - - - - - - | <-- CT_WG -LC21 -> - - - * * * - - - - * * - * | - * * * - - - - | <-- CT0 +LC23 -> - - - * * * - - - - * * - * | - * * * - - - - | <-- CT0 LC17 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- FDAT -LC23 -> - - - - - - * * - - - - - - | * * - - - - - - | <-- REG_P0 -LC26 -> - - - - - - * * - - - - - - | * * - - - - - - | <-- REG_P1 -LC24 -> * - - - - - - - * * - - - - | - * - - - - - - | <-- STWG0 -LC27 -> * - - - - - - - - * - - - - | - * - - - - - - | <-- STWG1 +LC26 -> - - - - - - * * - - - - - - | * * - - - - - - | <-- REG_P0 +LC22 -> - - - - - - * * - - - - - - | * * - - - - - - | <-- REG_P1 +LC27 -> * - - - - - - - * * - - - - | - * - - - - - - | <-- STWG0 +LC30 -> * - - - - - - - - * - - - - | - * - - - - - - | <-- STWG1 LC28 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- WGR2 LC32 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- WGR3 -LC22 -> - - - - - * - - - - - - - - | - * - - - - - - | <-- :180 +LC24 -> - - - - - * - - - - - - - - | - * - - - - - - | <-- :197 Pin 89 -> - - - - - - - - - - - - - - | - - - - - * * - | <-- EPM_RES @@ -539,25 +631,25 @@ Pin 40 -> - * - - - - - - - - - - * - | * * - - - * * * | <-- HDD_C3 90 -> - - - - - - - - - - - - - - | - - - - - - * - | <-- PW_GOOD 92 -> - - - - - * - - - - - - - * | - * - - - - - - | <-- RDAT -25 -> - - * - - - - - - - - - - - | - * - - - - - - | <-- RSTB -94 -> - - * - - - - - - - - - - - | - * - - - - - - | <-- STE 87 -> - - - - - - - - - - - - - - | - - - * - * - * | <-- TG42_IN -10 -> - - * - - - - - - - - - - - | - * - - - - - - | <-- WSTB +37 -> - - * - - - - - - - - - - - | - * - - - - - - | <-- XACS 88 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- XHR_RDY -LC56 -> - - * * * * - - - - * * - * | - * * * - - - - | <-- CLKZZ -LC101-> - - - - - - * * - - - - - - | * * - - - - - - | <-- LR_T0 -LC100-> - - - - - - * * - - - - - - | * * - - - - - - | <-- LR_T1 +LC56 -> - - - * * * - - - - * * - * | - * * * * - - - | <-- CLKZZ +LC85 -> - - * - - - - - - - - - - - | - * - - * * * * | <-- /CONF_X +LC65 -> * - - - - - * * * * - - - - | * * - - * - - - | <-- CT_WG +LC98 -> - - - - - - * * - - - - - - | * * - - - - - - | <-- LR_T0 +LC101-> - - - - - - * * - - - - - - | * * - - - - - - | <-- LR_T1 LC42 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- WGR0 -LC36 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- WGR1 +LC33 -> - - - - - - - - - - * * - - | - * * - - - - - | <-- WGR1 LC88 -> - * - - - - - - - - - - * - | * * - - * * - * | <-- 10K_CLK -LC91 -> - - * - - * - - - - * * - * | - * * - - * - - | <-- 10K_D0 +LC91 -> - - - - - * - - - - * * - * | - * * - * * - - | <-- 10K_D0 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** LOGIC CELL INTERCONNECTIONS ** @@ -567,39 +659,39 @@ Logic Array Block 'C': Logic cells placed in LAB 'C' +------------------------------- LC40 CTH0 | +----------------------------- LC39 CTH1 - | | +--------------------------- LC48 CTH2 - | | | +------------------------- LC37 CTH3 - | | | | +----------------------- LC45 CTH4 - | | | | | +--------------------- LC33 CTV2 - | | | | | | +------------------- LC35 CTV3 - | | | | | | | +----------------- LC44 CTV4 - | | | | | | | | +--------------- LC38 CTV5 - | | | | | | | | | +------------- LC34 CTV6 - | | | | | | | | | | +----------- LC47 CTV7 + | | +--------------------------- LC45 CTH2 + | | | +------------------------- LC35 CTH3 + | | | | +----------------------- LC37 CTH4 + | | | | | +--------------------- LC38 CTV2 + | | | | | | +------------------- LC36 CTV3 + | | | | | | | +----------------- LC34 CTV4 + | | | | | | | | +--------------- LC47 CTV5 + | | | | | | | | | +------------- LC48 CTV6 + | | | | | | | | | | +----------- LC44 CTV7 | | | | | | | | | | | +--------- LC46 QDAT | | | | | | | | | | | | +------- LC41 SINC_1 | | | | | | | | | | | | | +----- LC43 SINC_2 | | | | | | | | | | | | | | +--- LC42 WGR0 - | | | | | | | | | | | | | | | +- LC36 WGR1 + | | | | | | | | | | | | | | | +- LC33 WGR1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | | | | | | | that feed LAB 'C' LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C': LC40 -> * * * * * - - - - - - - * - - - | - - * - - - - - | <-- CTH0 LC39 -> - * * * * - - - - - - - * - - - | - - * - - - - - | <-- CTH1 -LC48 -> - - * * * - - - - - - - * - - - | - - * - - - * - | <-- CTH2 -LC37 -> - - - * * - - - - - - - * - - - | - - * - - - * - | <-- CTH3 -LC45 -> - - - - * - - - - - - - * - - - | - - * - - - * - | <-- CTH4 -LC33 -> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- CTV2 -LC35 -> - - - - - - * * * * * - - * - - | - - * - - - * - | <-- CTV3 -LC44 -> - - - - - - - * * * * - - * - - | - - * - - - * - | <-- CTV4 -LC38 -> - - - - - - - - * * * - - * - - | - - * - - - * - | <-- CTV5 -LC34 -> - - - - - - - - - * * - - * - - | - - * - - - * - | <-- CTV6 -LC47 -> - - - - - - - - - - * - - * - - | - - * - - - * - | <-- CTV7 +LC45 -> - - * * * - - - - - - - * - - - | - - * - - - * - | <-- CTH2 +LC35 -> - - - * * - - - - - - - * - - - | - - * - - - * - | <-- CTH3 +LC37 -> - - - - * - - - - - - - * - - - | - - * - - - * - | <-- CTH4 +LC38 -> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- CTV2 +LC36 -> - - - - - - * * * * * - - * - - | - - * - - - * - | <-- CTV3 +LC34 -> - - - - - - - * * * * - - * - - | - - * - - - * - | <-- CTV4 +LC47 -> - - - - - - - - * * * - - * - - | - - * - - - * - | <-- CTV5 +LC48 -> - - - - - - - - - * * - - * - - | - - * - - - * - | <-- CTV6 +LC44 -> - - - - - - - - - - * - - * - - | - - * - - - * - | <-- CTV7 LC41 -> - - - - - - - - - - - - * - - - | - - * - - - * - | <-- SINC_1 LC43 -> - - - - - - - - - - - - - * - - | - - * - - - * - | <-- SINC_2 LC42 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- WGR0 -LC36 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- WGR1 +LC33 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- WGR1 Pin 89 -> - - - - - - - - - - - - - - - - | - - - - - * * - | <-- EPM_RES @@ -607,23 +699,23 @@ Pin 87 -> - - - - - - - - - - - - - - - - | - - - * - * - * | <-- TG42_IN 88 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- XHR_RDY LC53 -> * * * * * - - - - - - - * - - - | - - * - - * * - | <-- AUD -LC56 -> - - - - - - - - - - - * - - * * | - * * * - - - - | <-- CLKZZ -LC103-> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- CTV0 -LC105-> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- CTV1 -LC21 -> - - - - - - - - - - - * - - * * | - * * * - - - - | <-- CT0 +LC56 -> - - - - - - - - - - - * - - * * | - * * * * - - - | <-- CLKZZ +LC105-> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- CTV0 +LC103-> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- CTV1 +LC23 -> - - - - - - - - - - - * - - * * | - * * * - - - - | <-- CT0 LC17 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- FDAT LC104-> - - * * * * * * * * * - * * - - | - - * - - - * - | <-- SINC_H LC99 -> - - - - - * * * * * * - - * - - | - - * - - - * - | <-- SINC_V LC28 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- WGR2 LC32 -> - - - - - - - - - - - * - - * * | - * * - - - - - | <-- WGR3 -LC91 -> - - - - - - - - - - - * - - * * | - * * - - * - - | <-- 10K_D0 +LC91 -> - - - - - - - - - - - * - - * * | - * * - * * - - | <-- 10K_D0 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** LOGIC CELL INTERCONNECTIONS ** @@ -641,7 +733,7 @@ Logic Array Block 'D': | | | | | | Other LABs fed by signals | | | | | | that feed LAB 'D' LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D': -LC56 -> * * - * - * | - * * * - - - - | <-- CLKZZ +LC56 -> * * - * - * | - * * * * - - - | <-- CLKZZ LC58 -> * - - * - - | - - - * - - - - | <-- CT2 LC49 -> - * * - - * | - - - * - - - - | <-- XCT0 @@ -650,46 +742,53 @@ Pin 90 -> - - - - - - | - - - - - - * - | <-- PW_GOOD 87 -> - * - - * * | - - - * - * - * | <-- TG42_IN 88 -> - - - - - - | - - - - - - - - | <-- XHR_RDY -LC21 -> * - - * - - | - * * * - - - - | <-- CT0 -LC18 -> * - - * - - | - - - * - - - - | <-- CT1 +LC23 -> * - - * - - | - * * * - - - - | <-- CT0 +LC20 -> * - - * - - | - - - * - - - - | <-- CT1 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'E': - Logic cells placed in LAB 'E' - +- LC77 HD_DIR - | - | Other LABs fed by signals - | that feed LAB 'E' -LC | | A B C D E F G H | Logic cells that feed LAB 'E': + Logic cells placed in LAB 'E' + +--- LC65 CT_WG + | +- LC77 HD_DIR + | | + | | Other LABs fed by signals + | | that feed LAB 'E' +LC | | | A B C D E F G H | Logic cells that feed LAB 'E': +LC65 -> * - | * * - - * - - - | <-- CT_WG Pin -89 -> - | - - - - - * * - | <-- EPM_RES -45 -> * | * * - - * * * * | <-- FDD_C1 -47 -> * | * * - - * * * * | <-- HDD_C0 -42 -> * | * * - - * * * * | <-- HDD_C1 -41 -> * | * * - - * * * * | <-- HDD_C2 -90 -> - | - - - - - - * - | <-- PW_GOOD -87 -> - | - - - * - * - * | <-- TG42_IN -88 -> - | - - - - - - - - | <-- XHR_RDY -LC85 -> * | - - - - * * * * | <-- /CONF_X -LC88 -> * | * * - - * * - * | <-- 10K_CLK +89 -> - - | - - - - - * * - | <-- EPM_RES +45 -> - * | * * - - * * * * | <-- FDD_C1 +47 -> - * | * * - - * * * * | <-- HDD_C0 +42 -> - * | * * - - * * * * | <-- HDD_C1 +41 -> - * | * * - - * * * * | <-- HDD_C2 +90 -> - - | - - - - - - * - | <-- PW_GOOD +25 -> * - | - - - - * - - - | <-- RSTB +94 -> * - | - - - - * - - - | <-- STE +87 -> - - | - - - * - * - * | <-- TG42_IN +10 -> * - | - - - - * - - - | <-- WSTB +88 -> - - | - - - - - - - - | <-- XHR_RDY +LC56 -> * - | - * * * * - - - | <-- CLKZZ +LC85 -> - * | - * - - * * * * | <-- /CONF_X +LC88 -> - * | * * - - * * - * | <-- 10K_CLK +LC91 -> * - | - * * - * * - - | <-- 10K_D0 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** LOGIC CELL INTERCONNECTIONS ** @@ -705,9 +804,9 @@ Logic Array Block 'F': | | | | Other LABs fed by signals | | | | that feed LAB 'F' LC | | | | | A B C D E F G H | Logic cells that feed LAB 'F': -LC85 -> - - - * | - - - - * * * * | <-- /CONF_X +LC85 -> - - - * | - * - - * * * * | <-- /CONF_X LC88 -> - - - * | * * - - * * - * | <-- 10K_CLK -LC91 -> - - - * | - * * - - * - - | <-- 10K_D0 +LC91 -> - - - * | - * * - * * - - | <-- 10K_D0 Pin 60 -> - - - * | - - - - - * - - | <-- D0 @@ -724,7 +823,7 @@ Pin 57 -> - - * - | - - - - - * - - | <-- WR_CNF 88 -> - - - - | - - - - - - - - | <-- XHR_RDY LC53 -> * - - - | - - * - - * * - | <-- AUD -LC117-> - - * * | - - - - - * - - | <-- CNF_OFF +LC21 -> - - * * | - - - - - * - - | <-- CNF_OFF LC109-> * - - - | - - - - - * - - | <-- XHD_RES @@ -732,7 +831,7 @@ LC109-> * - - - | - - - - - * - - | <-- XHD_RES - = The logic cell or pin is not an input to the logic cell (or LAB). -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** LOGIC CELL INTERCONNECTIONS ** @@ -740,10 +839,10 @@ SP2_MAX Logic Array Block 'G': Logic cells placed in LAB 'G' - +--------------- LC103 CTV0 - | +------------- LC105 CTV1 - | | +----------- LC101 LR_T0 - | | | +--------- LC100 LR_T1 + +--------------- LC105 CTV0 + | +------------- LC103 CTV1 + | | +----------- LC98 LR_T0 + | | | +--------- LC101 LR_T1 | | | | +------- LC102 SINC | | | | | +----- LC104 SINC_H | | | | | | +--- LC99 SINC_V @@ -752,8 +851,8 @@ Logic Array Block 'G': | | | | | | | | Other LABs fed by signals | | | | | | | | that feed LAB 'G' LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G': -LC103-> * * - - - - - - | - - * - - - * - | <-- CTV0 -LC105-> * * - - - - - - | - - * - - - * - | <-- CTV1 +LC105-> * * - - - - - - | - - * - - - * - | <-- CTV0 +LC103-> * * - - - - - - | - - * - - - * - | <-- CTV1 LC104-> * * - - * - * - | - - * - - - * - | <-- SINC_H LC99 -> * * - - * - - * | - - * - - - * - | <-- SINC_V @@ -775,16 +874,16 @@ Pin 88 -> - - - - - - - - | - - - - - - - - | <-- XHR_RDY LC53 -> - - - - - * - - | - - * - - * * - | <-- AUD LC19 -> - - * * - - - - | - * - - - - * - | <-- CLK_WG -LC85 -> - - - - - - * - | - - - - * * * * | <-- /CONF_X -LC48 -> - - - - - * - - | - - * - - - * - | <-- CTH2 -LC37 -> - - - - - * - - | - - * - - - * - | <-- CTH3 -LC45 -> - - - - - * - - | - - * - - - * - | <-- CTH4 -LC33 -> - - - - - - * - | - - * - - - * - | <-- CTV2 -LC35 -> - - - - - - * - | - - * - - - * - | <-- CTV3 -LC44 -> - - - - - - * - | - - * - - - * - | <-- CTV4 -LC38 -> - - - - - - * - | - - * - - - * - | <-- CTV5 -LC34 -> - - - - - - * - | - - * - - - * - | <-- CTV6 -LC47 -> - - - - - - * - | - - * - - - * - | <-- CTV7 +LC85 -> - - - - - - * - | - * - - * * * * | <-- /CONF_X +LC45 -> - - - - - * - - | - - * - - - * - | <-- CTH2 +LC35 -> - - - - - * - - | - - * - - - * - | <-- CTH3 +LC37 -> - - - - - * - - | - - * - - - * - | <-- CTH4 +LC38 -> - - - - - - * - | - - * - - - * - | <-- CTV2 +LC36 -> - - - - - - * - | - - * - - - * - | <-- CTV3 +LC34 -> - - - - - - * - | - - * - - - * - | <-- CTV4 +LC47 -> - - - - - - * - | - - * - - - * - | <-- CTV5 +LC48 -> - - - - - - * - | - - * - - - * - | <-- CTV6 +LC44 -> - - - - - - * - | - - * - - - * - | <-- CTV7 LC41 -> - - - - - * - - | - - * - - - * - | <-- SINC_1 LC43 -> - - - - - - * - | - - * - - - * - | <-- SINC_2 @@ -793,51 +892,49 @@ LC43 -> - - - - - - * - | - - * - - - * - | <-- SINC_2 - = The logic cell or pin is not an input to the logic cell (or LAB). -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'H': - Logic cells placed in LAB 'H' - +----------------- LC126 BEEP - | +--------------- LC117 CNF_OFF - | | +------------- LC128 TG42_OUT - | | | +----------- LC115 XHD_RD - | | | | +--------- LC113 XHD_WR - | | | | | +------- LC120 XHD1_CS1 - | | | | | | +----- LC121 XHD1_CS2 - | | | | | | | +--- LC123 XHD2_CS1 - | | | | | | | | +- LC125 XHD2_CS2 - | | | | | | | | | - | | | | | | | | | Other LABs fed by signals - | | | | | | | | | that feed LAB 'H' -LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H': + Logic cells placed in LAB 'H' + +--------------- LC126 BEEP + | +------------- LC128 TG42_OUT + | | +----------- LC115 XHD_RD + | | | +--------- LC113 XHD_WR + | | | | +------- LC120 XHD1_CS1 + | | | | | +----- LC121 XHD1_CS2 + | | | | | | +--- LC123 XHD2_CS1 + | | | | | | | +- LC125 XHD2_CS2 + | | | | | | | | + | | | | | | | | Other LABs fed by signals + | | | | | | | | that feed LAB 'H' +LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H': Pin -89 -> - - - - - - - - - | - - - - - * * - | <-- EPM_RES -44 -> - - - - - * * * * | * * - - - * * * | <-- FDD_C0 -45 -> - - - * * * * * * | * * - - * * * * | <-- FDD_C1 -46 -> - - - - - * * * * | * * - - - * * * | <-- FDD_C2 -47 -> - - - * * * * * * | * * - - * * * * | <-- HDD_C0 -42 -> - - - * * * * * * | * * - - * * * * | <-- HDD_C1 -41 -> - - - * * * * * * | * * - - * * * * | <-- HDD_C2 -40 -> - - - - - * * * * | * * - - - * * * | <-- HDD_C3 -90 -> - - - - - - - - - | - - - - - - * - | <-- PW_GOOD -87 -> - - - - - * * * * | - - - * - * - * | <-- TG42_IN -37 -> - * - - - - - - - | - - - - - - - * | <-- XACS -88 -> - - - - - - - - - | - - - - - - - - | <-- XHR_RDY -LC85 -> - * - * * * * * * | - - - - * * * * | <-- /CONF_X -LC51 -> - - * - - - - - - | - - - - - - - * | <-- TG42_BUF -LC88 -> - - - * * - - - - | * * - - * * - * | <-- 10K_CLK +89 -> - - - - - - - - | - - - - - * * - | <-- EPM_RES +44 -> - - - - * * * * | * * - - - * * * | <-- FDD_C0 +45 -> - - * * * * * * | * * - - * * * * | <-- FDD_C1 +46 -> - - - - * * * * | * * - - - * * * | <-- FDD_C2 +47 -> - - * * * * * * | * * - - * * * * | <-- HDD_C0 +42 -> - - * * * * * * | * * - - * * * * | <-- HDD_C1 +41 -> - - * * * * * * | * * - - * * * * | <-- HDD_C2 +40 -> - - - - * * * * | * * - - - * * * | <-- HDD_C3 +90 -> - - - - - - - - | - - - - - - * - | <-- PW_GOOD +87 -> - - - - * * * * | - - - * - * - * | <-- TG42_IN +88 -> - - - - - - - - | - - - - - - - - | <-- XHR_RDY +LC85 -> - - * * * * * * | - * - - * * * * | <-- /CONF_X +LC51 -> - * - - - - - - | - - - - - - - * | <-- TG42_BUF +LC88 -> - - * * - - - - | * * - - * * - * | <-- 10K_CLK * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). -Device-Specific Information: c:\sprinter\src\altera\max\sp2_max.rpt +Device-Specific Information: f:\sprinter\src\altera\max\sp2_max.rpt SP2_MAX ** EQUATIONS ** @@ -847,8 +944,6 @@ EPM_RES : INPUT; FDD_C0 : INPUT; FDD_C1 : INPUT; FDD_C2 : INPUT; -GND33 : INPUT; -GND65 : INPUT; HDD_C0 : INPUT; HDD_C1 : INPUT; HDD_C2 : INPUT; @@ -862,6 +957,25 @@ SR : INPUT; STE : INPUT; TG42_IN : INPUT; TR43 : INPUT; +UNUSED1 : INPUT; +UNUSED2 : INPUT; +UNUSED5 : INPUT; +UNUSED7 : INPUT; +UNUSED22 : INPUT; +UNUSED24 : INPUT; +UNUSED27 : INPUT; +UNUSED28 : INPUT; +UNUSED33 : INPUT; +UNUSED49 : INPUT; +UNUSED50 : INPUT; +UNUSED53 : INPUT; +UNUSED55 : INPUT; +UNUSED63 : INPUT; +UNUSED65 : INPUT; +UNUSED70 : INPUT; +UNUSED72 : INPUT; +UNUSED77 : INPUT; +UNUSED78 : INPUT; VGA_IN : INPUT; WD : INPUT; WR_CNF : INPUT; @@ -872,7 +986,7 @@ XA1 : INPUT; XA2 : INPUT; XHR_RDY : INPUT; --- Node name is 'AUD' = 'CT3' from file "sp2_max.tdf" line 100, column 4 +-- Node name is 'AUD' = 'CT3' from file "sp2_max.tdf" line 119, column 4 -- Equation name is 'AUD', location is LC053, type is output. AUD = TFFE( _EQ001, XCT1, VCC, VCC, VCC); _EQ001 = CT0 & CT1 & CT2; @@ -881,7 +995,7 @@ XHR_RDY : INPUT; -- Equation name is 'BEEP', location is LC126, type is output. BEEP = LCELL( GND $ GND); --- Node name is 'CLK_WG' = 'STWG2' from file "sp2_max.tdf" line 114, column 6 +-- Node name is 'CLK_WG' = 'STWG2' from file "sp2_max.tdf" line 133, column 6 -- Equation name is 'CLK_WG', location is LC019, type is output. CLK_WG = TFFE( _EQ002, _EQ003, VCC, VCC, VCC); _EQ002 = STWG0 & STWG1; @@ -889,7 +1003,7 @@ XHR_RDY : INPUT; _X001 = EXP(!CLK_WG & !CT_WG); _X002 = EXP( CLK_WG & CT_WG); --- Node name is 'CLKZZ' = 'XCT1' from file "sp2_max.tdf" line 94, column 5 +-- Node name is 'CLKZZ' = 'XCT1' from file "sp2_max.tdf" line 113, column 5 -- Equation name is 'CLKZZ', location is LC056, type is bidir. CLKZZ = TRI(XCT1, CNF_OFF); XCT1 = TFFE( XCT0, _EQ004, VCC, VCC, VCC); @@ -897,113 +1011,113 @@ XCT1 = TFFE( XCT0, _EQ004, VCC, VCC, VCC); _X003 = EXP(!TG42_IN & XCT1); _X004 = EXP( TG42_IN & !XCT1); --- Node name is 'CLK14' = ':166' from file "sp2_max.tdf" line 258, column 11 +-- Node name is 'CLK14' = ':183' from file "sp2_max.tdf" line 277, column 11 -- Equation name is 'CLK14', type is output CLK14 = TFFE( VCC, XCT0, VCC, VCC, VCC); --- Node name is 'CMOS_AS' = ':202' from file "sp2_max.tdf" line 431, column 13 +-- Node name is 'CMOS_AS' = ':219' from file "sp2_max.tdf" line 450, column 13 -- Equation name is 'CMOS_AS', type is output CMOS_AS = _LC029~NOT; _LC029~NOT = DFFE( _EQ005 $ GND, 10K_CLK, FDD_C2, VCC, VCC); _EQ005 = FDD_C0 & !FDD_C1 & !HDD_C0 & HDD_C1 & HDD_C2 & !HDD_C3; --- Node name is 'CMOS_DRD' = ':203' from file "sp2_max.tdf" line 432, column 13 +-- Node name is 'CMOS_DRD' = ':220' from file "sp2_max.tdf" line 451, column 13 -- Equation name is 'CMOS_DRD', type is output CMOS_DRD = DFFE( _EQ006 $ VCC, 10K_CLK, VCC, FDD_C2, VCC); _EQ006 = !FDD_C0 & FDD_C1 & !HDD_C0 & HDD_C1 & HDD_C2 & HDD_C3; --- Node name is 'CMOS_DWR' = ':201' from file "sp2_max.tdf" line 430, column 13 +-- Node name is 'CMOS_DWR' = ':218' from file "sp2_max.tdf" line 449, column 13 -- Equation name is 'CMOS_DWR', type is output CMOS_DWR = DFFE( _EQ007 $ VCC, 10K_CLK, VCC, FDD_C2, VCC); _EQ007 = FDD_C0 & !FDD_C1 & !HDD_C0 & HDD_C1 & HDD_C2 & HDD_C3; --- Node name is 'CNF_OFF' from file "sp2_max.tdf" line 265, column 12 --- Equation name is 'CNF_OFF', location is LC117, type is buried. +-- Node name is 'CNF_OFF' from file "sp2_max.tdf" line 284, column 12 +-- Equation name is 'CNF_OFF', location is LC021, type is buried. CNF_OFF = DFFE( GND $ GND, GND, XACS, /CONF_X, VCC); --- Node name is 'CTH0' from file "sp2_max.tdf" line 101, column 5 +-- Node name is 'CTH0' from file "sp2_max.tdf" line 120, column 5 -- Equation name is 'CTH0', location is LC040, type is buried. CTH0 = TFFE( VCC, !AUD, VCC, VCC, VCC); --- Node name is 'CTH1' from file "sp2_max.tdf" line 101, column 5 +-- Node name is 'CTH1' from file "sp2_max.tdf" line 120, column 5 -- Equation name is 'CTH1', location is LC039, type is buried. CTH1 = TFFE( CTH0, !AUD, VCC, VCC, VCC); --- Node name is 'CTH2' from file "sp2_max.tdf" line 101, column 5 --- Equation name is 'CTH2', location is LC048, type is buried. +-- Node name is 'CTH2' from file "sp2_max.tdf" line 120, column 5 +-- Equation name is 'CTH2', location is LC045, type is buried. CTH2 = TFFE( _EQ008, !AUD, VCC, VCC, VCC); _EQ008 = CTH0 & CTH1 & !CTH2 & !SINC_H # CTH0 & CTH1 & CTH2; --- Node name is 'CTH3' from file "sp2_max.tdf" line 101, column 5 --- Equation name is 'CTH3', location is LC037, type is buried. +-- Node name is 'CTH3' from file "sp2_max.tdf" line 120, column 5 +-- Equation name is 'CTH3', location is LC035, type is buried. CTH3 = TFFE( _EQ009, !AUD, VCC, VCC, VCC); _EQ009 = CTH0 & CTH1 & CTH2 & !CTH3 & !SINC_H # CTH0 & CTH1 & CTH2 & CTH3 # CTH0 & CTH1 & CTH3 & SINC_H; --- Node name is 'CTH4' from file "sp2_max.tdf" line 101, column 5 --- Equation name is 'CTH4', location is LC045, type is buried. +-- Node name is 'CTH4' from file "sp2_max.tdf" line 120, column 5 +-- Equation name is 'CTH4', location is LC037, type is buried. CTH4 = TFFE( _EQ010, !AUD, VCC, VCC, VCC); _EQ010 = CTH0 & CTH1 & CTH2 & CTH3 & !CTH4 & !SINC_H # CTH0 & CTH1 & CTH2 & CTH3 & CTH4 # CTH0 & CTH1 & CTH4 & SINC_H; --- Node name is 'CTV0' from file "sp2_max.tdf" line 102, column 5 --- Equation name is 'CTV0', location is LC103, type is buried. +-- Node name is 'CTV0' from file "sp2_max.tdf" line 121, column 5 +-- Equation name is 'CTV0', location is LC105, type is buried. CTV0 = DFFE( _EQ011 $ GND, SINC_H, VCC, VCC, VCC); _EQ011 = !CTV0 & _X005; _X005 = EXP( CTV0 & CTV1 & SINC_V); --- Node name is 'CTV1' from file "sp2_max.tdf" line 102, column 5 --- Equation name is 'CTV1', location is LC105, type is buried. +-- Node name is 'CTV1' from file "sp2_max.tdf" line 121, column 5 +-- Equation name is 'CTV1', location is LC103, type is buried. CTV1 = DFFE( _EQ012 $ GND, SINC_H, VCC, VCC, VCC); _EQ012 = !CTV0 & CTV1 & _X005 # CTV0 & !CTV1 & _X005; _X005 = EXP( CTV0 & CTV1 & SINC_V); --- Node name is 'CTV2' from file "sp2_max.tdf" line 102, column 5 --- Equation name is 'CTV2', location is LC033, type is buried. +-- Node name is 'CTV2' from file "sp2_max.tdf" line 121, column 5 +-- Equation name is 'CTV2', location is LC038, type is buried. CTV2 = DFFE( _EQ013 $ GND, SINC_H, VCC, VCC, VCC); _EQ013 = CTV0 & CTV1 & !CTV2 & _X005 # !CTV0 & CTV2 & _X005 # !CTV1 & CTV2 & _X005; _X005 = EXP( CTV0 & CTV1 & SINC_V); --- Node name is 'CTV3' from file "sp2_max.tdf" line 102, column 5 --- Equation name is 'CTV3', location is LC035, type is buried. +-- Node name is 'CTV3' from file "sp2_max.tdf" line 121, column 5 +-- Equation name is 'CTV3', location is LC036, type is buried. CTV3 = TFFE( _EQ014, SINC_H, VCC, VCC, VCC); _EQ014 = CTV0 & CTV1 & CTV2 & !CTV3 & _X005 # CTV0 & CTV1 & CTV2 & CTV3 # CTV0 & CTV1 & CTV3 & SINC_V; _X005 = EXP( CTV0 & CTV1 & SINC_V); --- Node name is 'CTV4' from file "sp2_max.tdf" line 102, column 5 --- Equation name is 'CTV4', location is LC044, type is buried. +-- Node name is 'CTV4' from file "sp2_max.tdf" line 121, column 5 +-- Equation name is 'CTV4', location is LC034, type is buried. CTV4 = TFFE( _EQ015, SINC_H, VCC, VCC, VCC); _EQ015 = CTV0 & CTV1 & CTV2 & CTV3 & !CTV4 & _X005 # CTV0 & CTV1 & CTV2 & CTV3 & CTV4 # CTV0 & CTV1 & CTV4 & SINC_V; _X005 = EXP( CTV0 & CTV1 & SINC_V); --- Node name is 'CTV5' from file "sp2_max.tdf" line 102, column 5 --- Equation name is 'CTV5', location is LC038, type is buried. +-- Node name is 'CTV5' from file "sp2_max.tdf" line 121, column 5 +-- Equation name is 'CTV5', location is LC047, type is buried. CTV5 = TFFE( _EQ016, SINC_H, VCC, VCC, VCC); _EQ016 = CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & !CTV5 & _X005 # CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 # CTV0 & CTV1 & CTV5 & SINC_V; _X005 = EXP( CTV0 & CTV1 & SINC_V); --- Node name is 'CTV6' from file "sp2_max.tdf" line 102, column 5 --- Equation name is 'CTV6', location is LC034, type is buried. +-- Node name is 'CTV6' from file "sp2_max.tdf" line 121, column 5 +-- Equation name is 'CTV6', location is LC048, type is buried. CTV6 = TFFE( _EQ017, SINC_H, VCC, VCC, VCC); _EQ017 = CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & !CTV6 & _X005 # CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & CTV6 # CTV0 & CTV1 & CTV6 & SINC_V; _X005 = EXP( CTV0 & CTV1 & SINC_V); --- Node name is 'CTV7' from file "sp2_max.tdf" line 102, column 5 --- Equation name is 'CTV7', location is LC047, type is buried. +-- Node name is 'CTV7' from file "sp2_max.tdf" line 121, column 5 +-- Equation name is 'CTV7', location is LC044, type is buried. CTV7 = TFFE( _EQ018, SINC_H, VCC, VCC, VCC); _EQ018 = CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & CTV6 & !CTV7 & _X005 @@ -1011,8 +1125,8 @@ CTV7 = TFFE( _EQ018, SINC_H, VCC, VCC, VCC); # CTV0 & CTV1 & CTV7 & SINC_V; _X005 = EXP( CTV0 & CTV1 & SINC_V); --- Node name is 'CT_WG' from file "sp2_max.tdf" line 275, column 11 --- Equation name is 'CT_WG', location is LC020, type is buried. +-- Node name is 'CT_WG' from file "sp2_max.tdf" line 294, column 11 +-- Equation name is 'CT_WG', location is LC065, type is buried. CT_WG = TFFE( VCC, _EQ019, VCC, VCC, VCC); _EQ019 = _X006 & _X007 & _X008; _X006 = EXP(!CT_WG & !XCT1); @@ -1021,15 +1135,15 @@ CT_WG = TFFE( VCC, _EQ019, VCC, VCC, VCC); _X009 = EXP(!STE & _X010 & !10K_D0); _X010 = EXP(!RSTB & !WSTB & _X009); --- Node name is 'CT0' from file "sp2_max.tdf" line 100, column 4 --- Equation name is 'CT0', location is LC021, type is buried. +-- Node name is 'CT0' from file "sp2_max.tdf" line 119, column 4 +-- Equation name is 'CT0', location is LC023, type is buried. CT0 = TFFE( VCC, XCT1, VCC, VCC, VCC); --- Node name is 'CT1' from file "sp2_max.tdf" line 100, column 4 --- Equation name is 'CT1', location is LC018, type is buried. +-- Node name is 'CT1' from file "sp2_max.tdf" line 119, column 4 +-- Equation name is 'CT1', location is LC020, type is buried. CT1 = TFFE( CT0, XCT1, VCC, VCC, VCC); --- Node name is 'CT2' from file "sp2_max.tdf" line 100, column 4 +-- Node name is 'CT2' from file "sp2_max.tdf" line 119, column 4 -- Equation name is 'CT2', location is LC058, type is buried. CT2 = TFFE( _EQ020, XCT1, VCC, VCC, VCC); _EQ020 = CT0 & CT1; @@ -1038,10 +1152,10 @@ CT2 = TFFE( _EQ020, XCT1, VCC, VCC, VCC); -- Equation name is 'DENS_X', location is LC011, type is output. DENS_X = LCELL( GND $ VCC); --- Node name is 'FDAT' = ':178' from file "sp2_max.tdf" line 309, column 9 +-- Node name is 'FDAT' = ':195' from file "sp2_max.tdf" line 328, column 9 -- Equation name is 'FDAT', type is output FDAT = DFFE( _EQ021 $ VCC, _EQ022, VCC, VCC, VCC); - _EQ021 = _LC022 & _X011 & _X012; + _EQ021 = _LC024 & _X011 & _X012; _X011 = EXP( RDAT & _X013 & _X014); _X012 = EXP( _X015 & _X016); _X013 = EXP( CT0 & !10K_D0); @@ -1058,24 +1172,24 @@ CT2 = TFFE( _EQ020, XCT1, VCC, VCC, VCC); -- Equation name is 'HD_CS', location is LC081, type is output. HD_CS = LCELL( GND $ GND); --- Node name is 'HD_DIR' = ':206' from file "sp2_max.tdf" line 460, column 27 +-- Node name is 'HD_DIR' = ':223' from file "sp2_max.tdf" line 479, column 27 -- Equation name is 'HD_DIR', type is output HD_DIR = DFFE( _EQ023 $ VCC, 10K_CLK, VCC, !_EQ024, VCC); _EQ023 = FDD_C1 & HDD_C0 & !HDD_C1 & HDD_C2; _EQ024 = _X019; _X019 = EXP( /CONF_X & HDD_C0); --- Node name is 'LR_T0' from file "sp2_max.tdf" line 141, column 6 --- Equation name is 'LR_T0', location is LC101, type is buried. +-- Node name is 'LR_T0' from file "sp2_max.tdf" line 160, column 6 +-- Equation name is 'LR_T0', location is LC098, type is buried. LR_T0 = DFFE( _EQ025 $ WD, CLK_WG, VCC, VCC, VCC); _EQ025 = SR & TR43 & WD; --- Node name is 'LR_T1' from file "sp2_max.tdf" line 141, column 6 --- Equation name is 'LR_T1', location is LC100, type is buried. +-- Node name is 'LR_T1' from file "sp2_max.tdf" line 160, column 6 +-- Equation name is 'LR_T1', location is LC101, type is buried. LR_T1 = DFFE( _EQ026 $ WD, CLK_WG, VCC, VCC, VCC); _EQ026 = SL & TR43 & WD; --- Node name is 'QDAT' = 'WGR4' from file "sp2_max.tdf" line 116, column 5 +-- Node name is 'QDAT' = 'WGR4' from file "sp2_max.tdf" line 135, column 5 -- Equation name is 'QDAT', location is LC046, type is output. QDAT = TFFE( _EQ027, _EQ028, VCC, VCC, VCC); _EQ027 = FDAT & WGR0 & WGR1 & WGR2 & WGR3; @@ -1084,15 +1198,15 @@ LR_T1 = DFFE( _EQ026 $ WD, CLK_WG, VCC, VCC, VCC); _X013 = EXP( CT0 & !10K_D0); _X014 = EXP( XCT1 & 10K_D0); --- Node name is 'REG_P0' from file "sp2_max.tdf" line 119, column 7 --- Equation name is 'REG_P0', location is LC023, type is buried. +-- Node name is 'REG_P0' from file "sp2_max.tdf" line 138, column 7 +-- Equation name is 'REG_P0', location is LC026, type is buried. REG_P0 = DFFE( _EQ029 $ LR_T0, !CT_WG, VCC, VCC, VCC); _EQ029 = !LR_T0 & !LR_T1 & !REG_P0 & _X020 # LR_T1; _X020 = EXP(!REG_P0 & !REG_P1); --- Node name is 'REG_P1' from file "sp2_max.tdf" line 119, column 7 --- Equation name is 'REG_P1', location is LC026, type is buried. +-- Node name is 'REG_P1' from file "sp2_max.tdf" line 138, column 7 +-- Equation name is 'REG_P1', location is LC022, type is buried. REG_P1 = DFFE( _EQ030 $ LR_T1, !CT_WG, VCC, VCC, VCC); _EQ030 = !LR_T0 & !LR_T1 & REG_P0 & REG_P1 & _X020 # !LR_T0 & !LR_T1 & !REG_P0 & !REG_P1 & _X020; @@ -1102,12 +1216,12 @@ REG_P1 = DFFE( _EQ030 $ LR_T1, !CT_WG, VCC, VCC, VCC); -- Equation name is 'SINC', location is LC102, type is output. SINC = LCELL( SINC_V $ SINC_H); --- Node name is 'SINC_H' = 'SINC_HT' from file "sp2_max.tdf" line 104, column 2 +-- Node name is 'SINC_H' = 'SINC_HT' from file "sp2_max.tdf" line 123, column 2 -- Equation name is 'SINC_H', location is LC104, type is output. SINC_H = DFFE( _EQ031 $ GND, !AUD, VCC, VCC, VCC); _EQ031 = CTH2 & !CTH3 & CTH4 & SINC_1; --- Node name is 'SINC_V' = 'SINC_VT' from file "sp2_max.tdf" line 105, column 2 +-- Node name is 'SINC_V' = 'SINC_VT' from file "sp2_max.tdf" line 124, column 2 -- Equation name is 'SINC_V', location is LC099, type is output. SINC_V = DFFE( _EQ032 $ GND, SINC_H, VCC, VCC, VCC); _EQ032 = CTV2 & !CTV3 & CTV4 & CTV5 & !CTV6 & !CTV7 & SINC_2 & _X021 @@ -1119,7 +1233,7 @@ REG_P1 = DFFE( _EQ030 $ LR_T1, !CT_WG, VCC, VCC, VCC); _X024 = EXP(!FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & !HDD_C1 & !HDD_C2 & HDD_C3); --- Node name is 'SINC_1' = 'CTH5' from file "sp2_max.tdf" line 101, column 5 +-- Node name is 'SINC_1' = 'CTH5' from file "sp2_max.tdf" line 120, column 5 -- Equation name is 'SINC_1', location is LC041, type is bidir. SINC_1 = TRI(CTH5, VCC); CTH5 = TFFE( _EQ033, !AUD, VCC, VCC, VCC); @@ -1127,7 +1241,7 @@ CTH5 = TFFE( _EQ033, !AUD, VCC, VCC, VCC); # CTH0 & CTH1 & CTH2 & CTH3 & CTH4 & SINC_1 # CTH0 & CTH1 & SINC_H & SINC_1; --- Node name is 'SINC_2' = 'CTV8' from file "sp2_max.tdf" line 102, column 5 +-- Node name is 'SINC_2' = 'CTV8' from file "sp2_max.tdf" line 121, column 5 -- Equation name is 'SINC_2', location is LC043, type is bidir. SINC_2 = TRI(CTV8, VCC); CTV8 = DFFE( _EQ034 $ GND, SINC_H, VCC, VCC, VCC); @@ -1137,36 +1251,36 @@ CTV8 = DFFE( _EQ034 $ GND, SINC_H, VCC, VCC, VCC); _X005 = EXP( CTV0 & CTV1 & SINC_V); _X025 = EXP( CTV0 & CTV1 & CTV2 & CTV3 & CTV4 & CTV5 & CTV6 & CTV7); --- Node name is 'STWG0' from file "sp2_max.tdf" line 114, column 6 --- Equation name is 'STWG0', location is LC024, type is buried. +-- Node name is 'STWG0' from file "sp2_max.tdf" line 133, column 6 +-- Equation name is 'STWG0', location is LC027, type is buried. STWG0 = TFFE( VCC, _EQ035, VCC, VCC, VCC); _EQ035 = _X001 & _X002; _X001 = EXP(!CLK_WG & !CT_WG); _X002 = EXP( CLK_WG & CT_WG); --- Node name is 'STWG1' from file "sp2_max.tdf" line 114, column 6 --- Equation name is 'STWG1', location is LC027, type is buried. +-- Node name is 'STWG1' from file "sp2_max.tdf" line 133, column 6 +-- Equation name is 'STWG1', location is LC030, type is buried. STWG1 = TFFE( STWG0, _EQ036, VCC, VCC, VCC); _EQ036 = _X001 & _X002; _X001 = EXP(!CLK_WG & !CT_WG); _X002 = EXP( CLK_WG & CT_WG); --- Node name is 'TG42_BUF' = ':161' from file "sp2_max.tdf" line 167, column 13 +-- Node name is 'TG42_BUF' = ':178' from file "sp2_max.tdf" line 186, column 13 -- Equation name is 'TG42_BUF', type is output TG42_BUF = LCELL(!TG42_IN $ GND); --- Node name is 'TG42_OUT' = ':160' from file "sp2_max.tdf" line 164, column 14 +-- Node name is 'TG42_OUT' = ':177' from file "sp2_max.tdf" line 183, column 14 -- Equation name is 'TG42_OUT', type is output TG42_OUT = LCELL( TG42_BUF $ GND); --- Node name is 'WDAT' = 'REG_P2' from file "sp2_max.tdf" line 119, column 7 +-- Node name is 'WDAT' = 'REG_P2' from file "sp2_max.tdf" line 138, column 7 -- Equation name is 'WDAT', location is LC008, type is output. WDAT = DFFE( _EQ037 $ GND, !CT_WG, VCC, VCC, VCC); _EQ037 = !LR_T0 & !LR_T1 & _X026; _X026 = EXP( _X027); _X027 = EXP( REG_P0 & !REG_P1); --- Node name is 'WGR0' from file "sp2_max.tdf" line 116, column 5 +-- Node name is 'WGR0' from file "sp2_max.tdf" line 135, column 5 -- Equation name is 'WGR0', location is LC042, type is buried. WGR0 = TFFE( _EQ038, _EQ039, VCC, VCC, VCC); _EQ038 = WGR0 & WGR1 & WGR2 & !WGR3 @@ -1177,8 +1291,8 @@ WGR0 = TFFE( _EQ038, _EQ039, VCC, VCC, VCC); _X013 = EXP( CT0 & !10K_D0); _X014 = EXP( XCT1 & 10K_D0); --- Node name is 'WGR1' from file "sp2_max.tdf" line 116, column 5 --- Equation name is 'WGR1', location is LC036, type is buried. +-- Node name is 'WGR1' from file "sp2_max.tdf" line 135, column 5 +-- Equation name is 'WGR1', location is LC033, type is buried. WGR1 = TFFE( _EQ040, _EQ041, VCC, VCC, VCC); _EQ040 = FDAT & !WGR0 & !WGR1 & !WGR2 & !WGR3 # !FDAT & !WGR1 & WGR2 & !WGR3 @@ -1189,7 +1303,7 @@ WGR1 = TFFE( _EQ040, _EQ041, VCC, VCC, VCC); _X013 = EXP( CT0 & !10K_D0); _X014 = EXP( XCT1 & 10K_D0); --- Node name is 'WGR2' from file "sp2_max.tdf" line 116, column 5 +-- Node name is 'WGR2' from file "sp2_max.tdf" line 135, column 5 -- Equation name is 'WGR2', location is LC028, type is buried. WGR2 = TFFE( _EQ042, _EQ043, VCC, VCC, VCC); _EQ042 = !FDAT & WGR1 & WGR2 & !WGR3 @@ -1200,7 +1314,7 @@ WGR2 = TFFE( _EQ042, _EQ043, VCC, VCC, VCC); _X013 = EXP( CT0 & !10K_D0); _X014 = EXP( XCT1 & 10K_D0); --- Node name is 'WGR3' from file "sp2_max.tdf" line 116, column 5 +-- Node name is 'WGR3' from file "sp2_max.tdf" line 135, column 5 -- Equation name is 'WGR3', location is LC032, type is buried. WGR3 = TFFE( _EQ044, _EQ045, VCC, VCC, VCC); _EQ044 = FDAT & WGR0 & WGR1 & WGR2 & WGR3 @@ -1211,34 +1325,34 @@ WGR3 = TFFE( _EQ044, _EQ045, VCC, VCC, VCC); _X013 = EXP( CT0 & !10K_D0); _X014 = EXP( XCT1 & 10K_D0); --- Node name is 'WR_PDOS' = ':198' from file "sp2_max.tdf" line 426, column 13 +-- Node name is 'WR_PDOS' = ':215' from file "sp2_max.tdf" line 445, column 13 -- Equation name is 'WR_PDOS', type is output WR_PDOS = DFFE( _EQ046 $ VCC, 10K_CLK, VCC, FDD_C2, VCC); _EQ046 = FDD_C0 & !FDD_C1 & !HDD_C0 & !HDD_C1 & !HDD_C2 & !HDD_C3; --- Node name is 'XCT0' from file "sp2_max.tdf" line 94, column 5 +-- Node name is 'XCT0' from file "sp2_max.tdf" line 113, column 5 -- Equation name is 'XCT0', location is LC049, type is buried. XCT0 = TFFE( VCC, _EQ047, VCC, VCC, VCC); _EQ047 = _X003 & _X004; _X003 = EXP(!TG42_IN & XCT1); _X004 = EXP( TG42_IN & !XCT1); --- Node name is 'XHD_RD' = '~206~1' from file "sp2_max.tdf" line 460, column 27 +-- Node name is 'XHD_RD' = '~223~1' from file "sp2_max.tdf" line 479, column 27 -- Equation name is 'XHD_RD', location is LC115, type is output. XHD_RD = DFFE( _EQ023 $ VCC, 10K_CLK, VCC, !_EQ024, VCC); --- Node name is 'XHD_RES' = ':204' from file "sp2_max.tdf" line 447, column 27 +-- Node name is 'XHD_RES' = ':221' from file "sp2_max.tdf" line 466, column 27 -- Equation name is 'XHD_RES', type is output XHD_RES = DFFE( PW_GOOD $ GND, SINC_V, EPM_RES, VCC, VCC); --- Node name is 'XHD_WR' = ':205' from file "sp2_max.tdf" line 459, column 27 +-- Node name is 'XHD_WR' = ':222' from file "sp2_max.tdf" line 478, column 27 -- Equation name is 'XHD_WR', type is output XHD_WR = DFFE( _EQ048 $ VCC, 10K_CLK, VCC, !_EQ049, VCC); _EQ048 = !FDD_C1 & HDD_C0 & !HDD_C1 & HDD_C2; _EQ049 = _X019; _X019 = EXP( /CONF_X & HDD_C0); --- Node name is 'XHD1_CS1' = ':207' from file "sp2_max.tdf" line 470, column 20 +-- Node name is 'XHD1_CS1' = ':224' from file "sp2_max.tdf" line 489, column 20 -- Equation name is 'XHD1_CS1', type is output XHD1_CS1 = DFFE( _EQ050 $ VCC, TG42_IN, VCC, /CONF_X, VCC); _EQ050 = /CONF_X & !HDD_C1 & HDD_C2 & !HDD_C3 & _X028 & _X029 & _X030 & @@ -1253,7 +1367,7 @@ XCT0 = TFFE( VCC, _EQ047, VCC, VCC, VCC); _X033 = EXP(!FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 & !HDD_C3); --- Node name is 'XHD1_CS2' = ':208' from file "sp2_max.tdf" line 471, column 20 +-- Node name is 'XHD1_CS2' = ':225' from file "sp2_max.tdf" line 490, column 20 -- Equation name is 'XHD1_CS2', type is output XHD1_CS2 = DFFE( _EQ051 $ VCC, TG42_IN, VCC, /CONF_X, VCC); _EQ051 = /CONF_X & !HDD_C1 & HDD_C2 & HDD_C3 & _X028 & _X029 & _X030 & @@ -1268,7 +1382,7 @@ XCT0 = TFFE( VCC, _EQ047, VCC, VCC, VCC); _X033 = EXP(!FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 & !HDD_C3); --- Node name is 'XHD2_CS1' = ':209' from file "sp2_max.tdf" line 475, column 20 +-- Node name is 'XHD2_CS1' = ':226' from file "sp2_max.tdf" line 494, column 20 -- Equation name is 'XHD2_CS1', type is output XHD2_CS1 = DFFE( _EQ052 $ VCC, TG42_IN, VCC, /CONF_X, VCC); _EQ052 = /CONF_X & !HDD_C1 & HDD_C2 & !HDD_C3 & _X029 & _X030 & _X032 & @@ -1283,7 +1397,7 @@ XCT0 = TFFE( VCC, _EQ047, VCC, VCC, VCC); _X031 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 & !HDD_C3); --- Node name is 'XHD2_CS2' = ':210' from file "sp2_max.tdf" line 476, column 20 +-- Node name is 'XHD2_CS2' = ':227' from file "sp2_max.tdf" line 495, column 20 -- Equation name is 'XHD2_CS2', type is output XHD2_CS2 = DFFE( _EQ053 $ VCC, TG42_IN, VCC, /CONF_X, VCC); _EQ053 = /CONF_X & !HDD_C1 & HDD_C2 & HDD_C3 & _X029 & _X030 & _X032 & @@ -1298,13 +1412,13 @@ XCT0 = TFFE( VCC, _EQ047, VCC, VCC, VCC); _X031 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 & !HDD_C3); --- Node name is '10K_CLK' = ':182' from file "sp2_max.tdf" line 322, column 13 +-- Node name is '10K_CLK' = ':199' from file "sp2_max.tdf" line 341, column 13 -- Equation name is '10K_CLK', type is output 10K_CLK = DFFE( _EQ054 $ !CNF_OFF, TG42_IN, VCC, VCC, VCC); _EQ054 = !CNF_OFF & !FDD_C2 & !HDD_C0 # CNF_OFF & WR_CNF; --- Node name is '10K_D0' = ':183' from file "sp2_max.tdf" line 324, column 12 +-- Node name is '10K_D0' = ':200' from file "sp2_max.tdf" line 343, column 12 -- Equation name is '10K_D0', type is output 10K_D0 = DFFE( _EQ055 $ GND, 10K_CLK, !_EQ056, !_EQ057, VCC); _EQ055 = CNF_OFF & D0 @@ -1316,7 +1430,7 @@ XCT0 = TFFE( VCC, _EQ047, VCC, VCC, VCC); _X035 = EXP( FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & !HDD_C1 & !HDD_C2 & !HDD_C3); --- Node name is '/CONF_X' = '/RESET' from file "sp2_max.tdf" line 154, column 12 +-- Node name is '/CONF_X' = '/RESET' from file "sp2_max.tdf" line 173, column 12 -- Equation name is '/CONF_X', location is LC085, type is bidir. /CONF_X = OPNDRN(/RESET); /RESET = DFFE( _EQ058 $ GND, !AUD, !_EQ059, VCC, VCC); @@ -1324,19 +1438,19 @@ XCT0 = TFFE( VCC, _EQ047, VCC, VCC, VCC); _EQ059 = !FDD_C0 & !FDD_C1 & !FDD_C2 & HDD_C0 & HDD_C1 & !HDD_C2 & HDD_C3; --- Node name is '/WG_RD' = ':200' from file "sp2_max.tdf" line 428, column 12 +-- Node name is '/WG_RD' = ':217' from file "sp2_max.tdf" line 447, column 12 -- Equation name is '/WG_RD', type is output /WG_RD = DFFE( _EQ060 $ VCC, 10K_CLK, VCC, FDD_C2, VCC); _EQ060 = !FDD_C0 & FDD_C1 & !HDD_C0 & !HDD_C1 & !HDD_C2 & !HDD_C3; --- Node name is '/WG_WR' = ':199' from file "sp2_max.tdf" line 427, column 12 +-- Node name is '/WG_WR' = ':216' from file "sp2_max.tdf" line 446, column 12 -- Equation name is '/WG_WR', type is output /WG_WR = DFFE( _EQ061 $ VCC, 10K_CLK, VCC, FDD_C2, VCC); _EQ061 = !FDD_C0 & !FDD_C1 & !HDD_C0 & !HDD_C1 & !HDD_C2 & !HDD_C3; --- Node name is ':180' from file "sp2_max.tdf" line 309, column 28 --- Equation name is '_LC022', type is buried -_LC022 = DFFE( _EQ062 $ GND, _EQ063, VCC, VCC, VCC); +-- Node name is ':197' from file "sp2_max.tdf" line 328, column 28 +-- Equation name is '_LC024', type is buried +_LC024 = DFFE( _EQ062 $ GND, _EQ063, VCC, VCC, VCC); _EQ062 = _X016; _X016 = EXP( _X012 & _X017); _X012 = EXP( _X015 & _X016); @@ -1361,7 +1475,7 @@ _LC022 = DFFE( _EQ062 $ GND, _EQ063, VCC, VCC, VCC); -Project Information c:\sprinter\src\altera\max\sp2_max.rpt +Project Information f:\sprinter\src\altera\max\sp2_max.rpt ** TIMING ASSIGNMENTS ** @@ -1377,7 +1491,7 @@ fmax 100.00 MHz 27.02 MHz Failed TG42_IN to register SINC_ fmax 100.00 MHz 43.47 MHz Failed WSTB to register STWG2.Q to register STWG0.Q -Project Information c:\sprinter\src\altera\max\sp2_max.rpt +Project Information f:\sprinter\src\altera\max\sp2_max.rpt ** COMPILATION SETTINGS & TIMES ** @@ -1458,8 +1572,8 @@ Compilation Times Database Builder 00:00:00 Logic Synthesizer 00:00:00 Partitioner 00:00:00 - Fitter 00:00:01 - Timing SNF Extractor 00:00:00 + Fitter 00:00:00 + Timing SNF Extractor 00:00:01 Assembler 00:00:00 -------------------------- -------- Total Time 00:00:01 @@ -1468,4 +1582,4 @@ Compilation Times Memory Allocated ----------------- -Peak memory allocated during compilation = 3,347K +Peak memory allocated during compilation = 3,543K diff --git a/src/altera/quartus/acex/ACCELER.ACF b/src/altera/quartus/acex/ACCELER.ACF new file mode 100644 index 0000000..5480845 --- /dev/null +++ b/src/altera/quartus/acex/ACCELER.ACF @@ -0,0 +1,568 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP acceler +BEGIN + DEVICE = EP1K30QC208-3; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EP1K100FC484-1; + AUTO_DEVICE = EP1K100FC256-1; + AUTO_DEVICE = EP1K100QC208-1; + AUTO_DEVICE = EP1K50FC484-1; + AUTO_DEVICE = EP1K50FC256-1; + AUTO_DEVICE = EP1K50QC208-1; + AUTO_DEVICE = EP1K50TC144-1; + AUTO_DEVICE = EP1K30FC256-1; + AUTO_DEVICE = EP1K30QC208-1; + AUTO_DEVICE = EP1K30TC144-1; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3; + FREQUENCY = 200MHz; + MAINTAIN_STABLE_SYNTHESIS = OFF; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; +END; + +IGNORED_ASSIGNMENTS +BEGIN + FIT_IGNORE_TIMING = OFF; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + MAX7000B_ENABLE_VREFB = OFF; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + FLEX_CONFIGURATION_EPROM = AUTO; + MAX7000AE_ENABLE_JTAG = ON; + MAX7000AE_USER_CODE = FFFFFFFF; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + MULTIVOLT_IO = OFF; + MAX7000S_ENABLE_JTAG = ON; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_USER_CODE = FFFF; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + nCEO = UNRESERVED; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + DATA0 = RESERVED_TRI_STATED; + FLEX8000_ENABLE_JTAG = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + DISABLE_TIME_OUT = OFF; + ENABLE_DCLK_OUTPUT = OFF; + RELEASE_CLEARS = OFF; + AUTO_RESTART = OFF; + USER_CLOCK = OFF; + SECURITY_BIT = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + STYLE = FAST; + DEVICE_FAMILY = ACEX1K; + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_REGISTER_PACKING = OFF; + AUTO_FAST_IO = OFF; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_PRESET = ON; + AUTO_GLOBAL_CLEAR = ON; + AUTO_GLOBAL_CLOCK = ON; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; + OPTIMIZE_FOR_SPEED = 5; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + USE_QUARTUS_FITTER = ON; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; + FITTER_SETTINGS = NORMAL; + SMART_RECOMPILE = OFF; + GENERATE_AHDL_TDO_FILE = OFF; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + TIMING_SNF_EXTRACTOR = ON; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + DESIGN_DOCTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VHDL_WRITER_VERSION = VHDL87; + VHDL_READER_VERSION = VHDL87; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + MASTER_RESET = OFF; + EXPANDER_NETWORKS = ON; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + ASYNCHRONOUS_INPUTS = ON; + PRESET_CLEAR_NETWORKS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_CLOCK_NETWORKS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + END_TIME = 5.0us; + BIDIR_PIN = STRONG; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + ANALYSIS_MODE = REGISTERED_PERFORMANCE; + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; + LIST_PATH_FREQUENCY = 10MHz; + LIST_PATH_COUNT = 10; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; +END; + +OTHER_CONFIGURATION +BEGIN + LAST_MAXPLUS2_VERSION = 10.0; + ROW_PINS_LCELL_INSERT = ON; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + NORMAL_LCELL_INSERT = ON; + EXPLICIT_FAMILY = 1; + FLEX_10K_52_COLUMNS = 40; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ROW_PINS_PERCENT = 50; + ORIGINAL_MAXPLUS2_VERSION = 9.6; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = ON; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + CARRY_CHAIN_LENGTH = 32; + CASCADE_CHAIN_LENGTH = 2; + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN = AUTO; + MINIMIZATION = FULL; + IGNORE_SOFT_BUFFERS = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/src/altera/quartus/acex/ACCELER.INC b/src/altera/quartus/acex/ACCELER.INC new file mode 100644 index 0000000..8610479 --- /dev/null +++ b/src/altera/quartus/acex/ACCELER.INC @@ -0,0 +1,26 @@ +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. + +-- MAX+plus II Include File +-- Version 10.0 9/14/2000 +-- Created: Fri Jan 25 12:59:19 2002 + +FUNCTION acceler (clk42, /reset, ct[2..0], ras, cas, clk_z80, mc_end, mc_begin, mc_type, mc_write, ai[15..0], di[7..0], /io, /rd, /wr, /mr, /rf, /m1, /iom, dcp[7..0], mdi[15..0], acc_ena, hddr[7..0], hdd_flip) + RETURNS (continue, ao[15..0], do[7..0], mdo[15..0], md[7..0], g_line[7..0], glisser, acc_on, double_cas, acc_dir[7..0]); diff --git a/src/altera/quartus/acex/ACCELER.TDF b/src/altera/quartus/acex/ACCELER.TDF new file mode 100644 index 0000000..45ccc00 --- /dev/null +++ b/src/altera/quartus/acex/ACCELER.TDF @@ -0,0 +1,374 @@ + + TITLE "ACCELERATOR"; + +INCLUDE "lpm_ram_dp"; + +SUBDESIGN acceler + ( + CLK42 : INPUT; + /RESET : INPUT; + CT[2..0] : INPUT; + + RAS : INPUT; + CAS : INPUT; + CLK_Z80 : INPUT; + + CONTINUE : OUTPUT; + + MC_END : INPUT; + MC_BEGIN : INPUT; + MC_TYPE : INPUT; + MC_WRITE : INPUT; +-- MCA[1..0] : INPUT; + + AI[15..0] : INPUT; + DI[7..0] : INPUT; + + AO[15..0] : OUTPUT; + DO[7..0] : OUTPUT; + + /IO : INPUT; + /RD : INPUT; + /WR : INPUT; + /MR : INPUT; + /RF : INPUT; + /M1 : INPUT; + /IOM : INPUT; + + DCP[7..0] : INPUT; + + MDI[15..0] : INPUT; + MDO[15..0] : OUTPUT; + MD[7..0] : OUTPUT; + + G_LINE[7..0]: OUTPUT; + + GLISSER : OUTPUT; + + ACC_ON : OUTPUT; + + ACC_ENA : INPUT; + + DOUBLE_CAS : OUTPUT; + + HDDR[7..0] : INPUT; + HDD_FLIP : INPUT; + + ACC_DIR[7..0] : OUTPUT; + + ) +VARIABLE + + RAM : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8); + + DO[7..0] : DFFE; + MDO[15..0] : DFFE; + + PRF_CMD : DFFE; + ED_CMD : DFFE; + CB_CMD : DFFE; + ID_CMD : DFFE; + IN_OUT_CMD : DFFE; + + CORRECT_1F : NODE; + + ACC_BLK : DFF; + + RETI : DFFE; + RETN : DFFE; + + AA[15..0] : DFFE; + + RGACC[7..0] : DFFE; + AGR[7..0] : DFFE; + ACC_CNT[7..0] : DFFE; + + START_ACC : NODE; + ACC_END : DFFE; + FN_ACC[2..0]: DFFE; + ACC_MODE[3..0] : DFFE; + + MD[7..0] : LCELL; + XMD[7..0] : DFF; + XMDH[7..0] : DFF; + + ACC_DIR[7..0] : LCELL; + + /M1M : NODE; + + ACC_GO : NODE; + ACC_GO_1 : NODE; + + RAM_WR : NODE; + + STATE_EI : DFFE; + +-- HDDR[7..0] : DFFE; + + XAGR[7..0] : DFFE; + AAGR[9..0] : DFFE; + XCNT[7..0] : DFFE; + ALT_ACC : NODE; + + RAM_ADR[7..0] : NODE; + ACC_C : NODE; + WR_C7 : NODE; + + XCNT_AGR[15..0] : NODE; + + MDOX[7..0] : DFF; + MDOY[7..0] : DFF; + + GLISS_R : DFF; + + ACC_TIME : NODE; + +BEGIN + + ACC_ON = ACC_DIR0; + + /M1M = DFF(!/M1,CLK_Z80,/RESET,); + + PRF_CMD.clk = /MR; + PRF_CMD.ena = /M1M; + PRF_CMD.d = (DI[] == B"11XX1XX1") & + ((DI[] == B"XX00X01X") or -- CB + (DI[] == B"XX01X10X") or -- DD + (DI[] == B"XX10X10X") or -- ED + (DI[] == B"XX11X10X")); -- FD + +-- === interrupt === 0 - disable; 1 - enable + + STATE_EI.clk = /MR; + STATE_EI.ena = /M1M & !PRF_CMD & (DI[] == B"1111X011"); + STATE_EI.d = DI3; + +-- RETI comand + + ED_CMD.clk = /MR; + ED_CMD.ena = /M1M; + ED_CMD.d = (DI[] == H"ED"); + + RETI.clk = /MR; + RETI.ena = /M1M; + RETI.d = ED_CMD & (DI[] == H"4D"); + +-- "1" on the RETI triger is the end of interupt sycle. + + RETN.clk = /MR; + RETN.ena = /M1M; + RETN.d = ED_CMD & (DI[] == H"45"); + +-- The end of NMI sycle. + + ACC_BLK.clk = /M1; + ACC_BLK.d = DFF(((/IO & ACC_BLK) or (!ACC_BLK & RETI)),CLK_Z80,,); + ACC_BLK.prn = /RESET & ACC_MODE3; + + CB_CMD.clk = /MR; + ID_CMD.clk = /MR; + CB_CMD.ena = /M1M; + ID_CMD.ena = /M1M; + + CB_CMD.d = (DI[] == H"CB"); + ID_CMD.d = (DI[] == B"11X11101"); + + IN_OUT_CMD.clk = /MR; + IN_OUT_CMD.ena = /M1M; + IN_OUT_CMD.d = (DI[] == B"1101X011") & !PRF_CMD; -- D3/DB + IN_OUT_CMD.clrn = /IO; + + CORRECT_1F = LCELL(IN_OUT_CMD & (DO[] == H"1F") & !/MR & !/RD); + DO[4..3].clrn = !CORRECT_1F; + + ACC_GO = DFFE((CAS or START_ACC),CLK42,,(!/MR & /M1),CT1); + ACC_GO_1 = DFF(ACC_GO,CLK42,,); + +-- == accelerator number == + + RGACC[].clk = /MR; + RGACC[].ena = DFF((/M1 & /RF & ACC_DIR3),CLK_Z80,,); + RGACC[].d = DI[]; + +-- == accelerator grafic line == + + AGR[].clk = CLK42; + AGR[].ena = !DFF((/IOM or /WR or !DFF((DCP[] == B"1100X100"),CLK42,,)),CLK42,,) or + !(!ACC_DIR4 or ACC_GO or !ACC_GO_1); + + CASE DFF(START_ACC,CLK42,,) IS + WHEN 0 => AGR[].d = AGR[] + 1; + WHEN 1 => AGR[].d = DI[]; + END CASE; + + AGR[].clrn = /RESET; + + G_LINE[] = AGR[]; + +-- == accelerator counter == + + ACC_C = (!ACC_GO & DFF(((CT0 & !/RD) or (CT1 & !/WR)),CLK42,,)); + ACC_CNT[].clk = CLK42; +-- ACC_CNT[].ena = START_ACC or (ACC_C & ACC_DIR2); + ACC_CNT[].ena = LCELL(START_ACC or (ACC_C & ACC_DIR2)); + + CASE DFF(START_ACC,CLK42,,) IS + WHEN 1 => ACC_CNT[].d = RGACC[]; + WHEN 0 => ACC_CNT[].d = ACC_CNT[] - 1; + END CASE; + + WR_C7 = DFF((/IOM or DFF(!/IOM,CLK42,,) or /WR or DFF(!(DCP[] == B"1100X111"),CLK42,,)),CLK42,,); + ALT_ACC = DFF(VCC,WR_C7,/RESET,); + + (AAGR[].ena,XCNT[].ena,XAGR[].ena) = LCELL(!WR_C7 or (ACC_DIR1 & ACC_C)); + (AAGR[].clk,XCNT[].clk,XAGR[].clk) = CLK42; + + XCNT_AGR[15..0] = (XCNT[],XAGR[]) + (B"000000",AAGR[]); + + CASE !DFF(START_ACC,CLK42,,) IS + WHEN 1 => AAGR[].d = AAGR[]; + (XCNT[].d,XAGR[].d) = XCNT_AGR[15..0]; + WHEN 0 => AAGR[].d = (AI9,AI8,DI[]); + (XCNT[].d,XAGR[].d) = (B"00",AI[15..10],B"00000000"); + END CASE; + +-- == accelerator dir == + + START_ACC = LCELL(LCELL(/MR or !/M1 or !/RF or !ACC_BLK) or (!ACC_DIR0 or MC_TYPE)); + + DOUBLE_CAS= LCELL(ACC_DIR6 & !START_ACC); + + ACC_END.clk = CLK42; + ACC_END.ena = !ACC_GO & ACC_GO_1; + ACC_END.prn = /M1; + ACC_END.d = (ACC_CNT[] == 1) or !ACC_DIR2; + + CONTINUE = ACC_END; + + CASE ACC_MODE[2..0] IS + WHEN 0 => ACC_DIR[] = B"00000000"; % LD B,B % + WHEN 1 => ACC_DIR[] = B"00100101"; % LD C,C % % fill by constant % + WHEN 2 => ACC_DIR[] = B"00001001"; % LD D,D % % load count accelerator % + WHEN 3 => ACC_DIR[] = B"00010101"; % LD E,E % % fill by constant VERTICAL % + WHEN 4 => ACC_DIR[] = B"01000001"; % LD H,H % % duble byte fn % + WHEN 5 => ACC_DIR[] = B"00100111"; % LD L,L % % copy line % + WHEN 6 => ACC_DIR[] = B"00000000"; % HALT % + WHEN 7 => ACC_DIR[] = B"00010111"; % LD A,A % % copy line VERTICAL % + END CASE; + +-- == accelerator mode == + + ACC_MODE[].clk = /MR; + ACC_MODE[].ena = DFF((!/M1 & !PRF_CMD & + LCELL((DI[] == B"XXX00X00") or + (DI[] == B"XXX01X01") or + (DI[] == B"XXX10X10") or + (DI[] == B"XXX11X11")) & + LCELL((DI[] == B"010XX0XX") or + (DI[] == B"011XX1XX"))),CLK_Z80,,); + ACC_MODE[].d = (VCC,DI[2..0]); + ACC_MODE[2..0].clrn = /RESET & ACC_ENA; + ACC_MODE[3].clrn = /RESET & !DFF(ACC_MODE3,CLK_Z80,,); + +-- == accelerator datas == + + CASE DFFE(AA0,CLK42,,,(CT2 & CT1)) IS + WHEN 0 => MD[] = MDI[7..0]; +-- GLISSER = DFF((MDO[7..0] == H"FF"),CLK42,,); + WHEN 1 => MD[] = MDI[15..8]; +-- GLISSER = DFF((MDO[15..8] == H"FF"),CLK42,,); + END CASE; + + GLISS_R.clk = CLK42; + CASE ACC_DIR1 IS + WHEN 0 => GLISS_R = LCELL(DI[] == H"FF"); + WHEN 1 => GLISS_R = LCELL(RAM.q[7..4] == H"F") & LCELL(RAM.q[3..0] == H"F"); + END CASE; + GLISSER = GLISS_R; + +-- MDO[].clk = !CLK42; + MDO[].clk = CLK42; + + MDO[].ena = CAS; + + MDOX[].clk = CLK42; + MDOY[].clk = CLK42; + + CASE LCELL(MC_END & HDD_FLIP) IS + WHEN 0 => MDOX[7..0] = DI[]; + WHEN 1 => MDOX[7..0] = HDDR[]; + END CASE; + + CASE ACC_DIR6 IS + WHEN 0 => MDOY[7..0] = DI[]; + WHEN 1 => MDOY[7..0] = HDDR[]; + END CASE; + + CASE LCELL(/IO & ACC_DIR1) IS + WHEN 0 => MDO[].d = (MDOY[],MDOX[]); + WHEN 1 => MDO[].d = (RAM.q[7..0],RAM.q[7..0]); + END CASE; + + DO[].clk = DFF(MC_END,!CLK42,,); +-- DO[].clk = !CLK42; + DO[].ena = VCC; +-- DO[].ena = DFF(!MC_END,CLK42,,); + DO[].d = MD[]; + +-- == accelerator functions == + + FN_ACC[].clk = /MR; + FN_ACC[].ena = /M1M; + FN_ACC[].d = LCELL(DI7 & !DI6 & !PRF_CMD) & !(DI[5..3]); + + XMDH[].clk = !CLK42; + XMDH[] = MDI[15..8]; + + XMD[].clk = !CLK42; + CASE FN_ACC[1..0] IS + WHEN 0 => + XMD[] = MD[]; % BE % + WHEN 1 => + XMD[] = MD[] or RAM.q[7..0]; % B6 % + WHEN 2 => + XMD[] = MD[] xor RAM.q[7..0]; % AE % + WHEN 3 => + XMD[] = MD[] & RAM.q[7..0]; % A6 % + END CASE; + + CASE ALT_ACC IS + WHEN 0 => RAM_ADR[] = ACC_CNT[]; + WHEN 1 => RAM_ADR[] = XCNT[]; + END CASE; + + ACC_TIME = LCELL((!ACC_END or !DFFE(ACC_END,CLK42,,,(CT1 & CT2)))); + +-- RAM_WR = DFF((!/RD & (!ACC_GO & CT0) & ACC_TIME),CLK42,,); + RAM_WR = DFF((!/RD & (!ACC_GO & CT0) & ACC_DIR1),CLK42,,); + + RAM.wren = RAM_WR; + RAM.data[] = (XMD[],XMD[]); +-- RAM.wraddress[] = ACC_CNT[]; + RAM.wraddress[] = RAM_ADR[]; + RAM.wrclock = CLK42; + RAM.wrclken = VCC; + RAM.rden = VCC; +-- RAM.rdaddress[] = ACC_CNT[]; + RAM.rdaddress[] = RAM_ADR[]; + RAM.rdclock = CLK42; + RAM.rdclken = VCC; + + AA[].clk = CLK42; +-- AA[].ena = START_ACC or (ACC_DIR5 & !ACC_GO & ACC_GO_1); + AA[].ena = LCELL(START_ACC or (ACC_DIR5 & !(CAS or START_ACC) & (ACC_GO or (ACC_GO_1 & ACC_DIR6)))); + + CASE DFF(START_ACC,CLK42,,) IS + WHEN 1 => AA[].d = AI[]; +-- WHEN 0 => AA[].d = AA[] + (B"00000000000000",ACC_DIR6,!ACC_DIR6); + WHEN 0 => AA[].d = AA[] + 1; + END CASE; + + AO[] = (AA[15..0]); + +END; + diff --git a/src/altera/quartus/acex/AY.ACF b/src/altera/quartus/acex/AY.ACF new file mode 100644 index 0000000..2f068ab --- /dev/null +++ b/src/altera/quartus/acex/AY.ACF @@ -0,0 +1,578 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP ay +BEGIN + DEVICE = EP1K30QC208-3; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EP1K100FC484-1; + AUTO_DEVICE = EP1K100FC256-1; + AUTO_DEVICE = EP1K100QC208-1; + AUTO_DEVICE = EP1K50FC484-1; + AUTO_DEVICE = EP1K50FC256-1; + AUTO_DEVICE = EP1K50QC208-1; + AUTO_DEVICE = EP1K50TC144-1; + AUTO_DEVICE = EP1K30FC256-1; + AUTO_DEVICE = EP1K30QC208-1; + AUTO_DEVICE = EP1K30TC144-1; + AUTO_DEVICE = EP1K10FC256-1; + AUTO_DEVICE = EP1K10QC208-1; + AUTO_DEVICE = EP1K10TC144-1; + AUTO_DEVICE = EP1K10TC100-1; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3; + FREQUENCY = 100MHz; + MAINTAIN_STABLE_SYNTHESIS = OFF; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; +END; + +IGNORED_ASSIGNMENTS +BEGIN + FIT_IGNORE_TIMING = ON; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + MAX7000B_ENABLE_VREFB = OFF; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + FLEX_CONFIGURATION_EPROM = AUTO; + MAX7000AE_ENABLE_JTAG = ON; + MAX7000AE_USER_CODE = FFFFFFFF; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + MULTIVOLT_IO = OFF; + MAX7000S_ENABLE_JTAG = ON; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_USER_CODE = FFFF; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + nCEO = UNRESERVED; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + DATA0 = RESERVED_TRI_STATED; + FLEX8000_ENABLE_JTAG = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + DISABLE_TIME_OUT = OFF; + ENABLE_DCLK_OUTPUT = OFF; + RELEASE_CLEARS = OFF; + AUTO_RESTART = OFF; + USER_CLOCK = OFF; + SECURITY_BIT = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_REGISTER_PACKING = OFF; + DEVICE_FAMILY = ACEX1K; + STYLE = NORMAL; + AUTO_FAST_IO = OFF; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_PRESET = ON; + AUTO_GLOBAL_CLEAR = ON; + AUTO_GLOBAL_CLOCK = ON; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; + OPTIMIZE_FOR_SPEED = 5; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + USE_QUARTUS_FITTER = ON; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; + FITTER_SETTINGS = NORMAL; + SMART_RECOMPILE = OFF; + GENERATE_AHDL_TDO_FILE = OFF; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + TIMING_SNF_EXTRACTOR = ON; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + DESIGN_DOCTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VHDL_WRITER_VERSION = VHDL93; + VHDL_READER_VERSION = VHDL93; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + MASTER_RESET = OFF; + EXPANDER_NETWORKS = ON; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + ASYNCHRONOUS_INPUTS = ON; + PRESET_CLEAR_NETWORKS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_CLOCK_NETWORKS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + BIDIR_PIN = STRONG; + END_TIME = 0.0ns; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + ANALYSIS_MODE = REGISTERED_PERFORMANCE; + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; + LIST_PATH_FREQUENCY = 10MHz; + LIST_PATH_COUNT = 10; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; +END; + +OTHER_CONFIGURATION +BEGIN + ROW_PINS_LCELL_INSERT = ON; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + NORMAL_LCELL_INSERT = ON; + EXPLICIT_FAMILY = 1; + LAST_MAXPLUS2_VERSION = 10.0; + FLEX_10K_52_COLUMNS = 40; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ROW_PINS_PERCENT = 50; + ORIGINAL_MAXPLUS2_VERSION = 10.0; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = ON; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = AUTO; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/src/altera/quartus/acex/AY.INC b/src/altera/quartus/acex/AY.INC new file mode 100644 index 0000000..aec944a --- /dev/null +++ b/src/altera/quartus/acex/AY.INC @@ -0,0 +1,26 @@ +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. + +-- MAX+plus II Include File +-- Version 10.0 9/14/2000 +-- Created: Sat May 26 07:09:40 2001 + +FUNCTION ay (/reset, clk42, ay_t[8..0], ay_d_wr, ay_a_wr, d[7..0], beeper) + RETURNS (do[7..0], ay_ch_a[3..0], ay_ch_b[3..0], ay_ch_c[3..0], ay_ch_l[9..0], ay_ch_r[9..0], ay_ch_val); diff --git a/src/altera/quartus/acex/AY.MIF b/src/altera/quartus/acex/AY.MIF new file mode 100644 index 0000000..1ed1d5e --- /dev/null +++ b/src/altera/quartus/acex/AY.MIF @@ -0,0 +1,154 @@ +DEPTH = 256; % Memory depth and width are required % +WIDTH = 8; % Enter a decimal number % + +ADDRESS_RADIX = HEX; % Address and value radixes are optional % +DATA_RADIX = BIN; % Enter BIN, DEC, HEX, or OCT; unless % + % otherwise specified, radixes = HEX % + +-- Specify values for addresses, which can be single address or range + +CONTENT +BEGIN + [0..7F] : 00000000; + 0 : 00000000 00000000 + 00000000 00000000 + 00000000 00000000 + 00000000 11111111 + 00000000 00000000 + 00000000 00000000 + 00000000 00000000 + 00000000 00000000 + + 11111111 11111111 + 11111111 11111111 + 11111111 11111111 + 11111111 11111111 + 11111111 11111111 + 11111111 11111111 + 11111111 00000001 + 00000000 11111111 + ; + 1E : 00000000; + 1F : 11111111; + + 30 : 00000000 + 00000010 + 00000011 + 00000100 + 00000110 + 00001000 + 00001011 + 00010000 + 00010110 + 00100000 + 00101101 + 01000000 + 01011010 + 10000000 + 10110100 + 11111111; + + [80..FF]: 00000000; + +% + 000 - set CX, load & sub 1 + 001 - load + 010 - save, if NZ,reset CX + 011 - bit_out + 100 - load & sub 1 + 101 - load & sub C + 110 - if CX, save + 111 - read states /RESET, AY_F_RES +% + + 80 : + 00010000 -- set C,CX load reg10 & sub C + 01010000 -- save reg10 & reset CX if NZ + 10110001 -- load reg11 & sub C + 01010001 -- save reg11 & reset CX if NZ + + 00100000 -- set C load reg00 & sub C + 11010000 -- save reg10 if CX + 00100001 -- load reg01 & sub C + 11010001 -- save reg11 if CX + + 00101000 -- load reg08 + 01100001 -- set AY_OUT1 + + + 00010010 -- set C,CX load reg12 & sub C + 01010010 -- save reg12 & reset CX if NZ + 10110011 -- load reg13 & sub C + 01010011 -- save reg13 & reset CX if NZ + + 00100010 -- set C load reg02 & sub C + 11010010 -- save reg12 if CX + 00100011 -- load reg03 & reset CX if NZ + 11010011 -- save reg13 if CX + + 00101001 -- load reg09 + 01100010 -- set AY_OUT2 + + + 00010100 -- set C,CX load reg14 & sub C + 01010100 -- save reg14 & reset CX if NZ + 10110101 -- load reg15 & sub C + 01010101 -- save reg15 & reset CX if NZ + + 00100100 -- set C load reg04 & sub C + 11010100 -- save reg14 if CX + 00100101 -- load reg05 & reset CX if NZ + 11010101 -- save reg15 if CX + + 00101010 -- load reg0A + 01100011 -- set AY_OUT3 + + + 00010111 -- set C,CX load reg17 & dec 1 + 01010111 -- save reg17 & reset CX if NZ + 00100110 -- load reg06 dec 1 *********** + 11010111 -- save reg17 if CX + + 01100100 -- set AY_SH + 00000000 -- NOP + + 00011000 -- set C,CX load reg18 & sub C + 01011000 -- save reg18 & reset CX if NZ + 10111001 -- load reg19 & sub C + 01011001 -- save reg19 & reset CX if NZ + + 00101011 -- load reg0B & sub 1 + 11011000 -- save reg18 if CX + 00101100 -- load reg0C & sub C + 11011001 -- save reg19 if CX + + 01100101 -- set FORM_CLK + + 11100000 -- set CX = AY_F_RES + +-- 00101011 -- load reg0B & sub 1 +-- 11011000 -- save reg18 if CX +-- 00101100 -- load reg0C & sub C +-- 11011001 -- save reg19 if CX + + 11100001 -- set CX = /RESET + + 00111111 -- load reg1F - FF *********** + 11000111 -- save reg07 if CX + 00111110 -- load reg1E - 00 *********** + + 11001101 -- save reg0D if CX + 11001000 -- save reg08 if CX + 11001001 -- save reg09 if CX + 11001010 -- save reg0a if CX + + 00100111 -- load reg07 *********** + 01100110 -- set keys_bits + + 00101101 -- load reg0D *********** + 01100111 -- set keys_bits SET-FORM-bits + +-- 01100000 -- set AY_OUT_ALL + + ; +END ; diff --git a/src/altera/quartus/acex/AY.TDF b/src/altera/quartus/acex/AY.TDF new file mode 100644 index 0000000..c090bef --- /dev/null +++ b/src/altera/quartus/acex/AY.TDF @@ -0,0 +1,368 @@ + + TITLE "AY-3-8910"; + +include "lpm_ram_dq"; +include "lpm_add_sub"; + +SUBDESIGN ay + ( + /RESET : INPUT; + CLK42 : INPUT; -- такты 42 + AY_T[8..0] : INPUT; -- внешний счетчик тактов + + AY_D_WR : INPUT; + AY_A_WR : INPUT; + + D[7..0] : INPUT; + DO[7..0] : OUTPUT; + + AY_CH_A[3..0] : OUTPUT; + AY_CH_B[3..0] : OUTPUT; + AY_CH_C[3..0] : OUTPUT; + + AY_CH_L[9..0] : OUTPUT; + AY_CH_R[9..0] : OUTPUT; + + AY_CH_VAL : OUTPUT; -- chanels data valid + BEEPER : INPUT; + + ) +VARIABLE + + BD[7..0] : DFFE; + BWR : DFFE; + AWR : DFFE; + + AY_DI[7..0] : NODE; + AY_DO[7..0] : NODE; + + AY_F_RES : NODE; + AY_F_R1 : NODE; + + AY_ADR[7..0] : DFF; + AY_AAX[1..0] : DFF; + + AY_X_[5..0] : DFFE; + AY_GF[3..0] : DFFE; + + AY_OUT[3..1] : DFFE; + AY_OUTS[3..1] : NODE; + + AY_CLK1 : NODE; + AY_SH[16..0] : DFFE; + AY_AA[3..0] : DFF; + AY_SH_Q : NODE; + + AY_ABLK : NODE; + AY_BBLK : NODE; + AY_AINV : NODE; + AY_BINV : NODE; + + AY_ADRX[7..0] : NODE; + AY_CCC[8..0] : DFF; + AY_AX[7..0] : NODE; + AY_C : DFFE; + AY_CX : DFFE; + AY_CXX : DFFE; + AY_WR : NODE; + AY_VA[3..0] : DFFE; + AY_VAR : DFFE; + AY_VX : DFFE; + + AY_DAT_WR : DFF; + AY_DAT[7..0] : DFFE; + + AY_DQ1[3..0] : DFFE; + AY_DQ2[3..0] : DFFE; + AY_DQ3[3..0] : DFFE; + + AY_DQX[3..0] : DFFE; + AY_OUTSX : NODE; + AY_CH_MIX : DFF; + + AY_AMP[3..0] : DFF; + + AY_DD[7..0] : DFFE; + + AY_CH_A[3..0] : DFF; + AY_CH_B[3..0] : DFF; + AY_CH_C[3..0] : DFF; + + AY_CH_CS[8..0] : DFF; + AY_CH_LX[10..0] : DFFE; + AY_CH_RX[10..0] : DFFE; + +-- AY_CH_L[9..0] : DFF; +-- AY_CH_R[9..0] : DFF; + + AY_CH_DIR[7..0] : DFFE; + + AY_OUTS1X : NODE; + AY_OUTS2X : NODE; + AY_OUTS3X : NODE; + + AY_OUTS1Y : NODE; +-- AY_OUTS2Y : NODE; + AY_OUTS3Y : NODE; + +BEGIN + +-- ====== AY8910 III version ========= + + BD[].clk = CLK42; + AWR.clk = CLK42; + BWR.clk = CLK42; + + BD[].ena = AY_CCC1; + BWR.ena = AY_CCC1; + AWR.ena = AY_CCC1; + + BD[7..5].clrn = !((AY_ADR[3..0] == B"00X1") or -- ch 1,2 + (AY_ADR[3..0] == B"0101") or -- ch 3 + (AY_ADR[3..0] == B"0110") -- ch shum + ); + BD4.clrn = !((AY_ADR[3..0] == B"00X1") or -- ch 1,2 + (AY_ADR[3..0] == B"0101") -- ch 3 + ); + + BD[] = D[]; + + AWR = AY_A_WR; +-- BWR = (AY_D_WR or !(AY_ADR[5..4] == 0)); + BWR = AY_D_WR; + + AY_CH_DIR[].clk = AY_D_WR; + AY_CH_DIR[].ena = (AY_ADR[] == B"XXX10000"); + AY_CH_DIR[].d = D[]; + AY_CH_DIR[].clrn= /RESET; + + AY_CCC[].clk = CLK42; + AY_CCC[8..0].d = AY_T[]; + + (AY_AAX[].clk,AY_ADR[].clk) = AY_A_WR; + AY_ADR[].d = D[]; + + -- Write to 0D register + AY_AAX0.d = (D[3..0] == B"1101"); + -- Write to AMP registers 08,09,0A + AY_AAX1.d = (D[3..0] == B"1000") or (D[3..0] == B"1001") or (D[3..0] == B"1010"); + + -- reset signal for form generator +-- AY_F_RES = DFF(VCC,DFF((!((AY_DO[7..5] == B"111") & AY_CCC1 & !AY_DO0) or AY_F_RES),CLK42,,),LCELL(!(AY_AAX0 or (AY_AAX1 & BD4)) or BWR),); + +-- AY_F_R1 = DFF((!(AY_AAX0 or (AY_AAX1)) or BWR),CLK42,,); + AY_F_R1 = DFF((!AY_AAX0 or BWR),CLK42,,); + AY_F_RES = DFF(DFF(VCC,AY_CCC7,AY_F_R1,),AY_CCC7,AY_F_R1,); + + AY_X_[].prn = VCC; + +-- AY_GF[3..0].clrn = /RESET; +-- AY_GF[3..0].clk = AY_D_WR; +-- AY_GF[3..0].ena = AY_ADR[] == B"XXXX1101"; +-- AY_GF[3..0].d = D[3..0]; + + AY_DAT_WR.clk = CLK42; + + CASE AY_CCC[1..0] IS + WHEN B"00" => + AY_AX[] = (VCC,GND,AY_CCC[7..2]); -- CMD adress + AY_WR = GND; + AY_DI[] = AY_DAT[]; + + AY_DAT_WR = VCC; + + WHEN B"01" => + AY_AX[] = (B"0000",AY_ADR[3..0]); + AY_WR = !BWR; + AY_DI[] = BD[]; + + AY_DAT_WR = VCC; + + WHEN B"1X" => + AY_AX[] = (GND,GND,GND,AY_DO[4..0]); + AY_DAT_WR = AY_DO6; + AY_WR = !LCELL(!(AY_DO[7..5] == B"010") & + !((AY_DO[7..5] == B"110") & AY_CXX)); +-- !((AY_DO[7..5] == B"110") & AY_CX)); + AY_DI[] = AY_DAT[]; + END CASE; + + AY_DD[].clk = CLK42; + AY_DD[].ena = !AY_CCC1 & !AY_CCC0; + AY_DD[] = AY_DO[]; + + AY_DO[] = lpm_ram_dq(AY_DI[],AY_AX[],AY_WR,CLK42,CLK42) + WITH (lpm_width=8,lpm_widthad=8,lpm_file="AY.MIF"); + +-- AY_CX.prn = !DFF((((AY_DO[7..5] == B"00X") & AY_CCC1) & (!AY_DO5 or AY_C)),CLK42,,); + AY_CX.prn = !DFF(((AY_DO[7..5] == B"000") & AY_CCC1),CLK42,,); + AY_CXX.prn = !DFF(((AY_DO[7..5] == B"000") & AY_CCC1),CLK42,,); + AY_C.prn = VCC; + + AY_CX.clk = CLK42; + AY_CXX.clk = CLK42; + (AY_CXX.ena,AY_CX.ena) = DFF((((AY_DO[7..5] == B"010") or (AY_DO[7..5] == B"111")) & AY_CCC1),CLK42,,); + + IF DFF(((AY_DO[7..5] == B"010")),CLK42,,) THEN + AY_CX = (LCELL(AY_DAT[] == 0) & AY_CX); +-- AY_CXX = (LCELL(AY_DAT[] == 0) & AY_CXX); +-- AY_CX = (LCELL(AY_DAT[] == 0) & AY_CX) or (AY_C & DFF(AY_DO0,CLK42,,)); + AY_CXX = (LCELL(AY_DAT[] == 0) & AY_CXX) or (AY_C & DFF(AY_DO0,CLK42,,)); + ELSE + AY_CXX = DFF(((!/RESET & AY_DO0) or (!AY_F_RES & !AY_DO0)),CLK42,,); + AY_CX = DFF(((!/RESET & AY_DO0) or (!AY_F_RES & !AY_DO0)),CLK42,,); + END IF; + + (AY_C.clk,AY_DAT[].clk) = CLK42; + (AY_C.ena,AY_DAT[].ena) = !DFF(AY_DAT_WR,CLK42,,); + (AY_C,AY_DAT[]) = (GND,AY_DO[]) - (B"00000000",DFF((DFF(!AY_DO5,CLK42,,) or (AY_C & DFF(AY_DO7,CLK42,,))),CLK42,,)); + + AY_OUT[].clk = CLK42; + + AY_AMP[].clk = CLK42; + AY_AMP[] = ((AY_DAT[3..0] or AY_DAT[4]) & (AY_AA[] or !AY_DAT[4])); + + AY_DQ1[].clk = CLK42; + AY_OUTS1 = DFF(((AY_DO[7..0] == B"011XX001") & AY_CCC1),CLK42,,); + AY_OUT1.ena = AY_OUTS1; + AY_OUT1 = AY_CX xor AY_OUT1; + AY_DQ1[].ena = AY_OUTS1; + AY_DQ1[] = AY_AMP[] & LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0)); + + AY_DQ2[].clk = CLK42; + AY_OUTS2 = DFF(((AY_DO[7..0] == B"011XX010") & AY_CCC1),CLK42,,); + AY_OUT2.ena = AY_OUTS2; + AY_OUT2 = AY_CX xor AY_OUT2; + AY_DQ2[].ena = AY_OUTS2; + AY_DQ2[] = AY_AMP[] & LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0)); + + AY_DQ3[].clk = CLK42; + AY_OUTS3 = DFF(((AY_DO[7..0] == B"011XX011") & AY_CCC1),CLK42,,); + AY_OUT3.ena = AY_OUTS3; + AY_OUT3 = AY_CX xor AY_OUT3; + AY_DQ3[].ena = AY_OUTS3; + AY_DQ3[] = AY_AMP[] & LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0)); + + AY_OUTSX = DFF((((AY_DO[7..0] == B"011XX01X") or + (AY_DO[7..0] == B"011XX0X1")) & AY_CCC1),CLK42,,); + AY_DQX[].clk = CLK42; + AY_DQX[].ena = AY_OUTSX; + AY_DQX[] = AY_AMP[] & AY_CH_MIX; + + AY_DQX[].clrn = !AY_SH_Q; + AY_DQX[].prn = (B"0010") or !DFF((AY_SH_Q & BEEPER),CLK42,,); + + AY_CH_MIX.clk = CLK42; + CASE AY_DO[1..0] IS + WHEN 0,1 => AY_CH_MIX = LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0)); + WHEN 2 => AY_CH_MIX = LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0)); + WHEN 3 => AY_CH_MIX = LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0)); + END CASE; + + AY_SH_Q = DFF(((AY_DO[7..0] == B"011XX100") & AY_CCC1),CLK42,,); + + AY_SH[].clk = CLK42; + AY_SH[].prn = /RESET; + AY_SH[].ena = AY_SH_Q & AY_CXX; + AY_SH[] = ((AY_SH3 xor AY_SH0),AY_SH[16..1]); + + AY_VAR.clk = CLK42; + AY_VX.clk = CLK42; + AY_VA[].clk = CLK42; + + (AY_VAR.clrn,AY_VA[].clrn) = AY_F_RES; + AY_VX.clrn = AY_F_RES; + + (AY_VX.ena,AY_VA[].ena,AY_VAR.ena) = DFF(((AY_DO[7..0] == B"011XX101") & AY_CCC1 & !AY_BBLK & AY_CX),CLK42,,); + (AY_VX,AY_VA[],AY_VAR) = (AY_VX,AY_VA[],AY_VAR) + 1; + + AY_X_[].clk = CLK42; + AY_X_[].ena = DFF(((AY_DO[7..0] == B"011XX110") & AY_CCC1),CLK42,,); + AY_X_[] = AY_DAT[5..0]; + + AY_GF[].clk = CLK42; + AY_GF[].ena = DFF(((AY_DO[7..0] == B"011XX111") & AY_CCC1),CLK42,,); + AY_GF[] = AY_DAT[3..0]; + + -- block count when 1-st period end + AY_BBLK = DFF((AY_VX & (AY_GF0 or !AY_GF3)),CLK42,,); -- VA_COUNT_STOP + + -- set ALL ZERO when 1-st period end + AY_ABLK = DFF((!AY_GF3 & AY_VX),CLK42,,); + + -- inverse 2-nd-s periods + AY_BINV = DFF((AY_VX & ((AY_GF[] == B"1X10") or (AY_GF == B"1X01"))),CLK42,,); + + -- inverse ALL + AY_AINV = AY_GF2; + + AY_AA[].clrn= VCC; + AY_AA[].clk = CLK42; + AY_AA[].d = (AY_VA[] xor AY_BINV xor !AY_AINV) & !AY_ABLK; + +% + AY_AA[].clrn= VCC; + AY_AA[].prn = GND; + AY_AA[].clk = CLK42; + AY_AA[] = VCC; +% + + AY_CH_A[3..0].clk = AY_CCC7; + AY_CH_B[3..0].clk = AY_CCC7; + AY_CH_C[3..0].clk = AY_CCC7; + + AY_CH_A[3..0] = AY_DQ1[3..0]; + AY_CH_B[3..0] = AY_DQ2[3..0]; + AY_CH_C[3..0] = AY_DQ3[3..0]; + + DO[7..0] = AY_DD[]; + + AY_CH_CS[].clk = CLK42; + CASE AY_DQX[] IS + WHEN 15 => AY_CH_CS[] = 360 ; + WHEN 14 => AY_CH_CS[] = 255 ; + WHEN 13 => AY_CH_CS[] = 180 ; + WHEN 12 => AY_CH_CS[] = 127 ; + WHEN 11 => AY_CH_CS[] = 90 ; + WHEN 10 => AY_CH_CS[] = 64 ; + WHEN 9 => AY_CH_CS[] = 45 ; + WHEN 8 => AY_CH_CS[] = 32 ; + WHEN 7 => AY_CH_CS[] = 22 ; + WHEN 6 => AY_CH_CS[] = 16 ; + WHEN 5 => AY_CH_CS[] = 11 ; + WHEN 4 => AY_CH_CS[] = 8 ; + WHEN 3 => AY_CH_CS[] = 6 ; + WHEN 2 => AY_CH_CS[] = 4 ; + WHEN 1 => AY_CH_CS[] = 2 ; + WHEN 0 => AY_CH_CS[] = 0 ; + END CASE; + + AY_OUTS1X = DFF(AY_OUTS1,CLK42,,); + AY_OUTS2X = DFF((AY_OUTS2 or AY_SH_Q),CLK42,,); + AY_OUTS3X = DFF(AY_OUTS3,CLK42,,); + + AY_OUTS1Y = DFF(AY_OUTS1 or AY_OUTS1X,CLK42,,); +-- AY_OUTS2Y = DFF(AY_OUTS2 or AY_OUTS2X,CLK42,,); + AY_OUTS3Y = DFF(AY_OUTS3 or AY_OUTS3X,CLK42,,); + + (AY_CH_LX[].clrn,AY_CH_RX[].clrn) = !DFF((AY_CCC[7..2] == 0),CLK42,,); + + (AY_CH_LX[],,) = LPM_ADD_SUB (,AY_CH_LX[],(B"00",AY_CH_CS[]),,,,) + WITH(LPM_WIDTH=11,LPM_REPRESENTATION="UNSIGNED"); + (AY_CH_RX[],,) = LPM_ADD_SUB (,AY_CH_RX[],(B"00",AY_CH_CS[]),,,,) + WITH (LPM_WIDTH=11,LPM_REPRESENTATION="UNSIGNED"); + + AY_CH_LX[].clk = CLK42; + AY_CH_RX[].clk = CLK42; + AY_CH_LX[].ena = DFF(DFF((AY_OUTS1 or AY_OUTS1Y or AY_OUTS2X or AY_OUTS2),CLK42,,),CLK42,,); + AY_CH_RX[].ena = DFF(DFF((AY_OUTS3 or AY_OUTS3Y or AY_OUTS2X or AY_OUTS2),CLK42,,),CLK42,,); + + AY_CH_VAL = DFF((AY_CCC[7..2] == B"111100"),CLK42,,); + +-- AY_CH_L[].clk = AY_CH_VAL; +-- AY_CH_R[].clk = AY_CH_VAL; + AY_CH_L[] = AY_CH_LX[10..1]; + AY_CH_R[] = AY_CH_RX[10..1]; + +END; + diff --git a/src/altera/quartus/acex/DCP.ACF b/src/altera/quartus/acex/DCP.ACF new file mode 100644 index 0000000..b8616b1 --- /dev/null +++ b/src/altera/quartus/acex/DCP.ACF @@ -0,0 +1,568 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP dcp +BEGIN + DEVICE = EP1K30FC256-3; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EP1K100FC484-1; + AUTO_DEVICE = EP1K100FC256-1; + AUTO_DEVICE = EP1K100QC208-1; + AUTO_DEVICE = EP1K50FC484-1; + AUTO_DEVICE = EP1K50FC256-1; + AUTO_DEVICE = EP1K50QC208-1; + AUTO_DEVICE = EP1K50TC144-1; + AUTO_DEVICE = EP1K30FC256-1; + AUTO_DEVICE = EP1K30QC208-1; + AUTO_DEVICE = EP1K30TC144-1; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EP1K30FC256-3; + FREQUENCY = 200MHz; + MAINTAIN_STABLE_SYNTHESIS = OFF; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; +END; + +IGNORED_ASSIGNMENTS +BEGIN + FIT_IGNORE_TIMING = OFF; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + MAX7000B_ENABLE_VREFB = OFF; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + FLEX_CONFIGURATION_EPROM = AUTO; + MAX7000AE_ENABLE_JTAG = ON; + MAX7000AE_USER_CODE = FFFFFFFF; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + MULTIVOLT_IO = OFF; + MAX7000S_ENABLE_JTAG = ON; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_USER_CODE = FFFF; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + nCEO = UNRESERVED; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + DATA0 = RESERVED_TRI_STATED; + FLEX8000_ENABLE_JTAG = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + DISABLE_TIME_OUT = OFF; + ENABLE_DCLK_OUTPUT = OFF; + RELEASE_CLEARS = OFF; + AUTO_RESTART = OFF; + USER_CLOCK = OFF; + SECURITY_BIT = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + STYLE = FAST; + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_REGISTER_PACKING = OFF; + DEVICE_FAMILY = ACEX1K; + AUTO_FAST_IO = OFF; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_PRESET = ON; + AUTO_GLOBAL_CLEAR = ON; + AUTO_GLOBAL_CLOCK = ON; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; + OPTIMIZE_FOR_SPEED = 5; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + USE_QUARTUS_FITTER = ON; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; + FITTER_SETTINGS = NORMAL; + SMART_RECOMPILE = OFF; + GENERATE_AHDL_TDO_FILE = OFF; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + TIMING_SNF_EXTRACTOR = ON; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + DESIGN_DOCTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VHDL_WRITER_VERSION = VHDL87; + VHDL_READER_VERSION = VHDL87; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + MASTER_RESET = OFF; + EXPANDER_NETWORKS = ON; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + ASYNCHRONOUS_INPUTS = ON; + PRESET_CLEAR_NETWORKS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_CLOCK_NETWORKS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + END_TIME = 5.0us; + BIDIR_PIN = STRONG; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + ANALYSIS_MODE = REGISTERED_PERFORMANCE; + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; + LIST_PATH_FREQUENCY = 10MHz; + LIST_PATH_COUNT = 10; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; +END; + +OTHER_CONFIGURATION +BEGIN + LAST_MAXPLUS2_VERSION = 10.0; + EXPLICIT_FAMILY = 1; + ROW_PINS_LCELL_INSERT = ON; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + NORMAL_LCELL_INSERT = ON; + FLEX_10K_52_COLUMNS = 40; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ROW_PINS_PERCENT = 50; + ORIGINAL_MAXPLUS2_VERSION = 9.6; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = ON; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = AUTO; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/src/altera/quartus/acex/DCP.INC b/src/altera/quartus/acex/DCP.INC new file mode 100644 index 0000000..12ce88f --- /dev/null +++ b/src/altera/quartus/acex/DCP.INC @@ -0,0 +1,27 @@ +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. + +-- MAX+plus II Include File +-- Version 10.0 9/14/2000 +-- Created: Thu Feb 07 21:14:23 2002 + +FUNCTION dcp (clk42, /reset, ct[2..0], continue, a[15..0], di[7..0], turbo_hand, /io, /rd, /wr, /mr, /rf, /m1, md[7..0], dos, refresh, g_line[9..0], test_r, acc_on, double_cas, blk_mem) + WITH (UPDATE) + RETURNS (/res, ras, cas, mc_end, mc_begin, mc_type, mc_write, do[7..0], ma[11..0], mca[1..0], clk_z80, turbo, /wait, /iom, /iomm, ra[17..14], page[11..0], type[3..0], cs_rom, cs_ram, v_ram, port, wr_dwg, wr_tm9, wr_awg, rd_kp11, kp11_mix, ga[9..0], graf, sp_scr, sp_sa, scr128, hdd_data, hdd_flip, ram, blk_r, pn4q, dcpp[7..0]); diff --git a/src/altera/quartus/acex/DCP.MIF b/src/altera/quartus/acex/DCP.MIF new file mode 100644 index 0000000..aee8502 --- /dev/null +++ b/src/altera/quartus/acex/DCP.MIF @@ -0,0 +1,119 @@ +DEPTH = 256; % Memory depth and width are required % +WIDTH = 16; % Enter a decimal number % + +ADDRESS_RADIX = HEX; % Address and value radixes are optional % +DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % + % otherwise specified, radixes = HEX % + +-- Specify values for addresses, which can be single address or range + +CONTENT +BEGIN + [0..FF] : 1000; + + 0 : 1040 % DCP PAGE %; + +% + MA[11..0] bit0 - WG_A5 + bit1 - WG_A6 + + bit2 - MUX_KP11, 0 - WG,CMOS 1 - KMPS,TM9 + bit3 - RD/WR 0 - WRITE 1 - READ + bit4 - CS_WG93 or WR_TM9 + + bit5 - HDD/CMOS strobe + bit6,7 - 00 - FDD/Scr switches + 01 - HDD Switch/ Reset + 10 - HDD1/HDD2 + 11 - CMOS + bit8 - HDD CS1/CS3 or CMOS data/adr + bit9,10,11 - HDD_A[2..0] +% + 10 : + 7018 % RD WG93 1F,0F % + 7019 % RD WG93 3F % + 701A % RD WG93 5F % + 701B % RD WG93 7F % + + 7017 % WR_PDOS FF % + 701F % RD_KEYS/ WR_A20 % + + 7023 % Set 720 % + 7027 % Set 1440 %; + +-- 18 : +-- 1000 % No_function % + +-- 1B : 1000; % ISA_A20 WR % + + 1C : 71D8 % CMOS_DAT_RD %; + 1D : 70D4 % CMOS_ADR_WR %; + 1E : 71D4 % CMOS_DAT_WR %; + + 20 : + 60A8 % HD_CS1 ports % + 62A8 + 64A8 + 66A8 + 68A8 + 6AA8 + 6CA8 + 6EA8 + + 6DA8 % HD_CS3 3F6 port % + 6FA8 % HD_CS3 3F7 port % + + 7060 % Set HDD1 % + 7064 % Set HDD2 % + + 7120 % Set 320 Lines % + 7124 % Set 312 Lines % + + 7160 % Soft Reset % + 7164 % ??? %; + + + 30 : + 7000 % slot 1 ports % + 7001 % slot 2 ports % + 7002 % slot 1 mem % + 7003 % slot 2 mem % + ; + + 40 : 4000; % kb read % + + 52 : 3000; -- AY_D READ + + 58 : 5000; -- KEMPSTON-Mouse + + [80..FF]: C000; + + 88 : 2000; -- COVOX + 89 : 2000; -- COVOX-Mode + + 8C : 3000; -- AY_D READ + 8D : 2000; -- AY_A WRITE + 8E : 2000; -- AY_D WRITE + + 8F : 2000; -- port for ROM_WRITE + +-- 80 : 7F 7F 7F 7F 7F 7F 7F 7F % KBD_DAT %; +-- 90 : 7F % PORT FF %; + + 90 : 3030 3031 2032 2033 2034 2035 2036 2037 + 2038 2039 203A 203B 203C 203D 203E 203F; % RAM PAGES % + + B0 : 2020 2021 2022 2023 2024 2025 2026 2027 + 2028 2029 202A 202B 202C 202D 202E 202F; % RAM PAGES % + + [C0..CF]: 2000 % SYS PORTS COPYES %; + + D0 : 2010 2011 2012 2013 2014 2015 2016 2017 + 2018 2019 201A 201B 201C 201D 201E 201F; % RAM PAGES % + E0 : 2041 2041 2041 2041 2041 2041 2041 2041 + 2000 2005 2002 2041 20FF 2000 2000 2041; % ROM PAGES % +-- E0 : 41 42 43 44 45 46 47 48 00 05 02 E0 F0 00 00 E8; % ROM PAGES % + F0 : 2000 2001 2002 2003 2004 2005 2006 2007 + 2008 2009 200A 200B 200C 200D 200E 200F; % RAM PAGES % + +END ; diff --git a/src/altera/quartus/acex/DCP.TDF b/src/altera/quartus/acex/DCP.TDF new file mode 100644 index 0000000..d73e33f --- /dev/null +++ b/src/altera/quartus/acex/DCP.TDF @@ -0,0 +1,750 @@ + + TITLE "DCP"; + +PARAMETERS + ( + UPDATE = 1 + ); + +INCLUDE "lpm_ram_dp"; +-- INCLUDE "DC_PORT2"; + +SUBDESIGN dcp + ( + CLK42 : INPUT; + /RESET : INPUT; + + /RES : OUTPUT; + + CT[2..0] : INPUT; + + CONTINUE : INPUT; + RAS : OUTPUT; + CAS : OUTPUT; + MC_END : OUTPUT; + MC_BEGIN : OUTPUT; + MC_TYPE : OUTPUT; + MC_WRITE : OUTPUT; + + A[15..0] : INPUT; + DI[7..0] : INPUT; + DO[7..0] : OUTPUT; + MA[11..0] : OUTPUT; + MCA[1..0] : OUTPUT; + + TURBO_HAND : INPUT; + CLK_Z80 : OUTPUT; + TURBO : OUTPUT; + + /IO : INPUT; + /RD : INPUT; + /WR : INPUT; + /MR : INPUT; + /RF : INPUT; + /M1 : INPUT; + + /WAIT : OUTPUT; + /IOM : OUTPUT; + /IOMM : OUTPUT; + + MD[7..0] : INPUT; + RA[17..14] : OUTPUT; + PAGE[11..0] : OUTPUT; + + TYPE[3..0] : OUTPUT; + + CS_ROM : OUTPUT; + CS_RAM : OUTPUT; + V_RAM : OUTPUT; + PORT : OUTPUT; +-- DOS : OUTPUT; + DOS : INPUT; + + WR_DWG : OUTPUT; + + WR_TM9 : OUTPUT; + WR_AWG : OUTPUT; + RD_KP11 : OUTPUT; + KP11_MIX : OUTPUT; + + REFRESH : INPUT; + + G_LINE[9..0]: INPUT; + GA[9..0] : OUTPUT; + GRAF : OUTPUT; + + SP_SCR : OUTPUT; + SP_SA : OUTPUT; + SCR128 : OUTPUT; + + TEST_R : INPUT; + + HDD_DATA : OUTPUT; + HDD_FLIP : OUTPUT; + RAM : OUTPUT; + BLK_R : OUTPUT; + + PN4Q : OUTPUT; + + ACC_ON : INPUT; -- asselerator state - 1 - present + + DCPP[7..0] : OUTPUT; + + DOUBLE_CAS : INPUT; + + BLK_MEM : INPUT; + + ) +VARIABLE + + CLK21 : NODE; + +-- DC : DC_PORT2; + + CLK84 : NODE; + CLK42X : NODE; + + CTZ[1..0] : DFF; + +-- CT[2..0] : DFF; + + MEM : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="DCP.MIF"); + + D[7..0] : NODE; + ADR8_MEM : NODE; + MEM_D[15..0]: NODE; + MEM_WR : NODE; + + DCP_CX : NODE; + SC_LCELL : NODE; + + PG3[5..0] : NODE; + PG0[5..0] : NODE; + MPGS[7..0] : LCELL; + PGS[7..0] : DFF; +-- PGS[7..0] : NODE; + + PN[7..0] : DFFE; + SC[7..0] : DFFE; + SYS : DFFE; + CNF[7..0] : DFFE; + AROM16 : DFFE; + TB_SW : DFFE; + + CASH_ON : NODE; + NMI_ENA : NODE; + + DD[7..0] : DFFE; + STARTING : NODE; + +-- DOS_ : NODE; +-- DOS : NODE; +-- DOS_ON_ : NODE; + + MC_RQ : NODE; + MC_END : DFFE; + MC_BEGIN : DFFE; + MC_TYPE : DFFE; + MC_WRITE : DFFE; + RAS : DFFE; + CAS : DFFE; + + MA_[11..0] : DFFE; + MCA[1..0] : DFFE; + + /IOM : DFFE; + /IOMM : DFFE; + /IOMX : DFFE; + /IOMY : DFFE; + + WT_CT[3..0] : DFFE; + W_TAB[3..0] : LCELL; + HDD_W[3..0] : NODE; + /IO_WAIT : NODE; + /MR_WAIT : NODE; + + MEM_RW : NODE; + IO_RW : NODE; + IO_RWM : NODE; + + MA_CT[1..0] : DFFE; + + WR_TM9 : DFFE; + RD_KP11 : DFFE; + + /RES : NODE; + + RFT : DFF; + RFC : DFFE; + + GRAF : DFFE; + GRAF_X : NODE; + GA[9..0] : LCELL; + + SP_SCR : LCELL; + SP_SA : LCELL; + + HDD_FLIP : DFFE; + /IOMZ : DFFE; + + HDD_DATA : NODE; + HDD_ENA : NODE; + + BLK_C : NODE; + /CASH : NODE; + + DCPP[7..0] : DFFE; + + PORTS_X : NODE; + + NO_IO_WAIT : NODE; + + DCP_RES : NODE; + + HDD_A[3..0] : DFF; + + X_ADR[11..0]: LCELL; + X_MA_[11..0]: LCELL; + + WR_AWGX : NODE; + + /IOWR : NODE; + + RA[17..14] : LCELL; + +-- SPR_[1..0] : NODE; + SPR_[1..0] : LCELL; + + SYS_ENA : NODE; + +BEGIN + +% + DC.CLK42 = CLK42; + DC./RESET = /RESET; + + DC.A[15..0] = A[15..0]; + + DC./IO = /IO; + DC./WR = /WR; + DC./M1 = /M1; + +-- DC./IOM; +-- DC./IOMM; +-- DC.DCP[7..0]; + + DC.DOS = DOS; + DC.CNF[1..0]= CNF[4..3]; + + DC.SYS = SYS; + +-- DC.PORT_X; +% + + +-- ============================================================== +% + CT[].clk = CLK42; + + IF CT1 THEN + CT[1..0] = GND; + CT2 = !CT2; + ELSE + CT[1..0] = CT[1..0]+1; + CT2 = CT2; + END IF; +% + + /RES = DFFE(VCC,CLK42,,,CT0); +-- ============================================================== + +-- TURBO = DFFE((TB_SW & TURBO_HAND),CLK42,,/RESET,CLK_Z80); + TURBO = DFF(DFFE((TB_SW & TURBO_HAND),CLK_Z80,,/RESET,!/RF),CLK42,,); + + CLK84 = CLK42 xor LCELL(CLK42X); + CLK42X = DFF(!CLK42X,CLK84,,); + + CTZ[].clk = CLK84 xor CTZ1; + CTZ[] = CTZ[]+1; + +-- CLK_Z80 = CTZ1; + +-- CLK_Z80 = DFF((!CLK21 & TURBO) or (TFF((CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,); +-- CLK_Z80 = DFF((CLK21 & TURBO) or (TFF((CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,); + + CLK_Z80 = DFF((CLK21 & TURBO) or (TFF((!CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,); +-- CLK_Z80 = DFF((!CLK21 & TURBO) or (TFF((!CT2 & CT1),CLK42,,) & !TURBO),!CLK42,,); + +-- ============================================================== + CLK21 = DFF((!CT0 xor CT2),CLK42,,); +-- === Adress Multiplexer ======================================= + + MA_[].clk = CLK42; +-- MA_[].ena = (CT2 xor CT0); + MA_[].ena = CLK21; + + WR_TM9.clk = CLK42; +-- WR_TM9.ena = (CT2 xor CT0); + WR_TM9.ena = CLK21; + WR_TM9.prn = /RES; + + RD_KP11.clk = !CLK42; +-- RD_KP11.ena = (CT2 xor CT0); + RD_KP11.ena = CLK21; + RD_KP11.prn = /RES; + RD_KP11.d = !(MA_CT[] == 0); + +-- WR_AWGX = DFF((WR_TM9 or CLK21),!CLK42,,); + WR_AWGX = DFF(GND,!WR_TM9,,DFF(WR_AWGX,CLK42,,)); + +-- WR_TM9 = (!MA_CT1 or (!IO_RW & !PORTS_X)); + WR_TM9 = (!MA_CT1 or (!/IO & !PORTS_X)); + + WR_AWG = WR_AWGX; + + KP11_MIX = TFF(VCC,RD_KP11,,); + + WR_DWG = !MC_BEGIN; +-- WR_DWG = DFF(!MC_BEGIN,CLK42,,); +-- WR_DWG = LCELL(!MC_BEGIN); + +-- MA_CT[].ena = (CT2 xor CT0); + MA_CT[].ena = CLK21; + MA_CT[].clk = CLK42; + + IF !LCELL(CT2 & !CT1) THEN + MA_CT[] = MA_CT[]+1; + ELSE + MA_CT[] = GND; + END IF; + +% + MA_[11..0] bit0 - WG_A5 + bit1 - WG_A6 + bit2 - MUX_KP11, 0 - WG,CMOS 1 - KMPS,TM9 + bit3 - RD/WR 0 - WRITE 1 - READ + bit4 - CS_WG93 or WR_TM9 + bit5 - HDD/CMOS strobe + bit7,6 - 00 - not + 01 - ???? + 10 - HDD1/2 + 11 - CMOS + bit8 - HDD CS1/CS3 or CMOS data/adr + bit9,10,11 - HDD_A[2..0] +% + CASE A[15..14] IS + WHEN 0 => SP_SCR = GND; SP_SA = GND; + WHEN 1 => SP_SCR = !GRAF; SP_SA = GND; + WHEN 2 => SP_SCR = GND; SP_SA = PG3[1]; + WHEN 3 => SP_SCR = !GRAF & LCELL(PG3[] == B"1101X1"); SP_SA = PG3[1]; + END CASE; + + CASE GRAF IS + WHEN 0 => GA[] = (GND,GND,MEM.q[3..0],A[13..10]); +-- WHEN 1 => GA[] = (VCC,(G_LINE[8..0] + (B"00000",A[13..10]))); + WHEN 1 => GA[] = (VCC,G_LINE[8..0]); + END CASE; + + CASE (IO_RW,MA_CT0) IS + WHEN 0 => X_ADR[] = (GND,CNF4,PN5,DOS,/WR,A15,A14,A[6..5],A13,A7,A[2]); + WHEN 1 => X_ADR[] = (GND,GND,CNF[4..3],B"01000000"); + WHEN 2 => X_ADR[] = (GND,GA3,GA[1..0],A[9..2]); + WHEN 3 => X_ADR[] = (GND,GND,GA[3..2],MEM.q[7..4],GA[7..4]); + END CASE; + + CASE IO_RW IS + WHEN 0 => X_MA_[] = (HDD_A[2..0],MEM.q[8..6],((MEM.q[5..4]) & (!/IOMZ,!/IOMY)),/WR,MEM.q2,A[6..5]); + WHEN 1 => X_MA_[] = (HDD_A[2..0],B"00000",/WR,VCC,A[6..5]); + END CASE; +% + CASE MA_CT1 IS +-- WHEN 0 => MA_[] = X_ADR[]; + WHEN 0 => MA_[] = (GND,X_ADR[10..0]); + WHEN 1 => MA_[] = (HDD_A[2..0],X_MA_[8..4],/WR,X_MA_[3],A[6..5]); + END CASE; +% + + CASE (IO_RW,MA_CT1) IS + WHEN B"00" => + MA_[] = (X_ADR[11..0]); + WHEN B"01" => + MA_[] = (HDD_A[2..0],MEM.q[8..6],((MEM.q[5..4]) & (!/IOMZ,!/IOMY)),/WR,MEM.q2,A[6..5]); + WHEN B"10" => + MA_[] = (X_ADR[11..0]); + WHEN B"11" => + MA_[] = (HDD_A[2..0],B"00000",/WR,VCC,A[6..5]); + END CASE; + + MA[] = MA_[]; + + MCA[].ena = CT2 & CT1; + MCA[].clk = CLK42; + MCA[] = A[1..0]; -- adress for CAS + + HDD_A[].clk = CLK42; + CASE (A[14],A[2..0]) IS + WHEN 0 => HDD_A[] = 0; + WHEN 1 => HDD_A[] = 1; + WHEN 2 => HDD_A[] = 2; + WHEN 3 => HDD_A[] = 3; + WHEN 4 => HDD_A[] = 4; + WHEN 5 => HDD_A[] = 5; + WHEN 6 => HDD_A[] = 0; + WHEN 7 => HDD_A[] = 0; + WHEN 8 => HDD_A[] = 0; + WHEN 9 => HDD_A[] = 0; + WHEN 10 => HDD_A[] = 6; + WHEN 11 => HDD_A[] = 7; + WHEN 12 => HDD_A[] = 14; + WHEN 13 => HDD_A[] = 15; + WHEN 14 => HDD_A[] = 0; + WHEN 15 => HDD_A[] = 0; + END CASE; + + +-- === Memory Sinchronizer ====================================== + + +% RF | MEM | RF + ____ | | _______ +/MR \__________/ + | | + _____| | _______ +MC_BEGIN \________/ + | |__ +MC_END ____________/ \_______ + ______ |__________ +MC_TYPE \_____/ + | | +RAS __ _ ___ __ + \__/|\__/ | \__/ + ____ _ __ +CAS \__/ | \__/|\__/ + | | + +% + +-- MC_RQ = DFF(((/MR & DFF(/IO,CLK42,,)) or (/RD & /WR)),CLK42,,); + +-- MC_RQ = DFF(((/MR & DFFE(GND,!CLK42,,!/IO,CT0)) or (/RD & /WR)),!CLK42,,); + +-- MC_RQ = DFF((((/MR or !/RF) & DFF(/IO,CLK42,,/M1)) or (/RD & /WR)),CLK42,,); + +-- MC_RQ = DFF((((/MR or !/RF) & IO_RW) or (/RD & /WR)),CLK42,,); + +-- MC_RQ = DFF(((MEM_RW & IO_RW) or (/RD & /WR)),CLK42,,); + + MC_RQ = DFF(((MEM_RW & DFF(DFF(IO_RW,CLK42,,!/IO),CLK42,,!/IO)) or (/RD & /WR)),!CLK42,,); + + MC_BEGIN.clk= CLK42; + MC_BEGIN.ena= CT1 & CT2; + MC_BEGIN.d = MC_RQ; + MC_BEGIN.prn= !(/MR & /IO); + + MC_END.clk = CLK42; + MC_END.d = VCC; + MC_END.ena = (CT0 & CT2) & !MC_BEGIN & CONTINUE & !BLK_C; + MC_END.clrn = !(/MR & /IO); + + MC_TYPE.clk = CLK42; + MC_TYPE.ena = CT1 & CT2; + MC_TYPE.d = MC_RQ or MC_END; + MC_TYPE.prn = /RES; + + MC_WRITE.clk= CLK42; + MC_WRITE.ena= CT1 & CT2; + MC_WRITE.d = MC_RQ or CS_RAM or /WR or MC_END; + MC_WRITE.prn= /RES; + + RFT.clk = REFRESH; + RFT.d = GND; + RFT.prn = RFC; +-- RFT.prn = VCC; + + RFC.clk = CLK42; + RFC.d = !MC_RQ or RFT; +-- RFC.d = !MC_RQ; + RFC.ena = CT1 & CT2; + + RAS.ena = (!(CT1 or (CT0 xor MC_TYPE))) & (!MC_TYPE or !RFC); + CAS.ena = (!(CT1 or (CT0 xor !MC_TYPE))) & (!MC_TYPE or !RFC); +-- RAS.ena = (!(CT1 or (CT0 xor MC_TYPE))); +-- CAS.ena = (!(CT1 or (CT0 xor !MC_TYPE))); + + RAS.clk = CLK42; CAS.clk = CLK42; + RAS.d = CT2; CAS.d = CT2 or BLK_C; + + RAS.prn = /RES; + CAS.prn = /RES; +-- CAS.prn = !BLK_C; + +-- /MR_WAIT = (MEM_RW or /CASH or DFF(MC_END,CLK42,!/MR,)) or (!TURBO & !ACC_ON); +-- /MR_WAIT = MC_END or LCELL(MEM_RW or /CASH or (!TURBO & !ACC_ON)); + + /MR_WAIT = LCELL(MC_END or MEM_RW or /CASH or (!TURBO & !ACC_ON)); + +-- MEM_RW = LCELL(/MR or !/RF); + + -- anti gluk! + MEM_RW = DFF((!/RF or BLK_MEM),!/MR,,LCELL(MEM_RW or !/MR)); + IO_RWM = DFF(!/M1,!/IO,,LCELL(IO_RW or !/IO)); + + IO_RW = DFF(/IO,CLK42,,/M1); + + /IOMM.clk = CLK42; +-- /IOMM.ena = CT0 xor CT2; + /IOMM.ena = CLK21; + /IOMM.d = IO_RW or !MC_END or DFF((WT_CT[] == 0),CLK42,,); + /IOMM.prn = /RES; + + /IOMX.clk = CLK42; +-- /IOMX.ena = CT0 xor CT2; + /IOMX.ena = CLK21; + /IOMX.d = /IOMM; + /IOMX.prn = /RES; + + /IOMY.clk = CLK42; +-- /IOMY.ena = CT0 xor CT2; + /IOMY.ena = CLK21; + /IOMY.d = /IOMX or !MC_END or DFF((WT_CT[] == B"000X"),CLK42,,); +-- /IOMY.prn = /RES; + /IOMY.prn = PORTS_X; + + PORTS_X = DFF(((DCPP[7..4] == B"0010") or (DCPP[7..4] == B"0001")),CLK42,,); + + /IOMZ.clk = CLK42; +-- /IOMZ.ena = CT0 xor CT2; + /IOMZ.ena = CLK21; + /IOMZ.d = (A8 xor /RD) or /IOMX or !MC_END or DFF((WT_CT[] == B"000X"),CLK42,,); + /IOMZ.prn = PORTS_X; + + HDD_DATA = DFF((HDD_ENA & DFF((MEM.q[11..8] == 0),CLK42,,) & PORTS_X),CLK42,,); + HDD_ENA = (MEM.q[7..5] == B"101"); + + HDD_FLIP.clk = /IOM; + HDD_FLIP.ena = HDD_ENA & DFF((DCPP[] == B"0010XXXX"),CLK42,,); + HDD_FLIP.d = !HDD_FLIP & (MEM.q[11..8] == 0); + HDD_FLIP.clrn = /RESET & DFF(GND,!DOUBLE_CAS,,HDD_FLIP); + + /IOM.clk = CLK42; +-- /IOM.ena = CT0 xor CT2; + /IOM.ena = CLK21; + /IOM.d = (/IOMX & /IOM); + /IOM.prn = !/IO & /M1; + +-- /IO_WAIT = LCELL(/IO or !/M1 or DFF(DFFE((WT_CT[] == 0),CLK42,,,CLK21),CLK42,,NO_IO_WAIT)); + + /IO_WAIT = LCELL(IO_RWM or DFF(DFFE((WT_CT[] == 0),CLK42,,,CLK21),CLK42,,NO_IO_WAIT)); + + NO_IO_WAIT = !DFF(((A[7..0] == B"111XX1XX") & !TURBO & DOS),CLK42,,); +-- NO_IO_WAIT = TURBO; + + WT_CT[].clk = CLK42; +-- WT_CT[].ena = (CT2 xor CT0); + WT_CT[].ena = CLK21; +-- WT_CT[].ena = CT1; + WT_CT[].prn = MC_END; + + CASE (/IOM,DFF((WT_CT[] == 0),CLK42,,)) IS + WHEN B"1X" => WT_CT[].d = W_TAB[]; + WHEN B"00" => WT_CT[].d = WT_CT[]-1; + WHEN B"01" => WT_CT[].d = GND; + END CASE; + + CASE (TURBO,MEM.q[14..12]) IS + WHEN 0 => W_TAB[] = 2; WHEN 8 => W_TAB[] = 2; + WHEN 1 => W_TAB[] = 2; WHEN 9 => W_TAB[] = 2; + WHEN 2 => W_TAB[] = 1; WHEN 10 => W_TAB[] = 4; + WHEN 3 => W_TAB[] = 1; WHEN 11 => W_TAB[] = 4; + WHEN 4 => W_TAB[] = 1; WHEN 12 => W_TAB[] = 7; + WHEN 5 => W_TAB[] = 2; WHEN 13 => W_TAB[] = 7; +-- WHEN 6 => W_TAB[] = 10; WHEN 14 => W_TAB[] = 10; + WHEN 6 => W_TAB[] = 7; WHEN 14 => W_TAB[] = 7; +-- WHEN 6 => W_TAB[] = 13; WHEN 14 => W_TAB[] = 13; + WHEN 7 => W_TAB[] = 10; WHEN 15 => W_TAB[] = 10; + END CASE; + + CASE LCELL(MEM.q[11..8] == 0) IS + WHEN 0 => HDD_W[] = 10; -- registers wait + WHEN 1 => HDD_W[] = 4; -- datas wait + END CASE; + + /WAIT = (/IO_WAIT & /MR_WAIT); + + +-- === Other Devicese CASHE, ISA, ROM... === + + V_RAM = PN2; -- for ORIGINAL Waits + +IF UPDATE == 1 GENERATE + -- all ROM/RAM switches in main .tdf + BLK_R = SC4; + -- all cashes in main .tdf + /CASH = GND; + -- cashe dir in main .tdf + CASH_ON = GND; +ELSE GENERATE + -- for blk wait + /CASH = DFF((MEM.q[7..4] == 15),!CLK42,BLK_R,); +-- when BLK_R = 1 => Other Devices stay Active! + BLK_R = DFF( (LCELL((MEM.q7 & MEM.q6 & RAM) or + (MEM.q7 & LCELL(A14 & A15 & SC4))) & + !DFF(DFF(MC_RQ,CLK42,,!/MR),CLK42,,!/MR)),!CLK42,!/MR,); + CASH_ON = DFFE(A7,(/IO or /RD),/RESET,,DFF((DCPP[] == H"88"),CLK42,,)); +END GENERATE; + + RAM = !LCELL(A14 or A15 or (SC0 & SYS)); + + CS_ROM = LCELL(/MR or !RAM or !/RF); + CS_RAM = LCELL(/MR or RAM or !/RF); + +-- ============================================== + +-- graf screen enable for pages + + GRAF_X = LCELL(MEM.q[7..4] == B"0101"); + + GRAF.clk = CLK42; + GRAF.ena = (CT0 & CT2); + GRAF.d = GRAF_X; + + BLK_C = LCELL((GRAF_X xor GRAF) & !MC_TYPE); + +----------------------------------------- + + SCR128 = PN3; + + D[] = DI[]; + -- when not IO - reset DCPP! + + DCP_RES = DFF((STARTING & !/IO & /M1),CLK42,,); + + DCPP[].clk = CLK42; + DCPP[].ena = !DFF(MC_END,CLK42,,); + DCPP[].clrn = MC_END & DCP_RES; -- not in/out when START + DCPP[].d = MD[]; + +-- DD[].clk = !CLK42; +-- DD[].ena = !DFF(MC_END,!CLK42,,); + + DD[].clk = CLK42; + DD[].ena = !DFF(MC_END,CLK42,,); + DD[].clrn = MC_END & DCP_RES; + + CASE LCELL(MD[7..4] == 15) IS + WHEN 0 => DD[].d = MD[]; + WHEN 1 => DD[].d = (VCC,VCC,PG3[]); + END CASE; + +-- === Port Decoder ============================================= + + DCP_CX = (DCPP[] == B"1100XXXX"); + SYS_ENA = DFF((DCP_CX & (DCPP[] == B"XXXXX110")),CLK42,,); + +-- /IOWR = DFF((/WR or /IO),CLK42,,!/IO); + /IOWR = LCELL(/IO or /WR or !/M1); + + CNF[].ena = SYS_ENA; CNF[].d = (DI[] & DI2) or (CNF[] & !DI2); + AROM16.ena = SYS_ENA; AROM16.d = (DI0 & !DI1) or (AROM16 & DI1); + TB_SW.ena = SYS_ENA; TB_SW.d = (DI0 & DI1) or (TB_SW & !DI1); + SYS.ena = SYS_ENA; SYS.d = !A6; + + SC[].ena = DFF((DCP_CX & (DCPP[] == B"XXXXX000")),CLK42,,) ;SC[].d = DI[]; + PN[].ena = DFF((DCP_CX & (DCPP[] == B"XXXXX001")),CLK42,,) ;PN[].d = DI[]; + + TB_SW.clk = /IOWR; + AROM16.clk = /IOWR; + PN[].clk = /IOWR; + SC[].clk = /IOWR; + SYS.clk = /IOWR; + CNF[].clk = /IOWR; + + AROM16.clrn = /RESET; + TB_SW.prn = /RESET; + SYS.clrn = /RESET; + CNF[].clrn = /RESET; + + SC[].clrn = /RESET & !CNF6; -- Scorpion-OFF + + PN[5..0].clrn = /RESET & !CNF5; -- reset PN5 + PN[7..5].clrn = /RESET & CNF7; -- set Pentagon-512 + + PN4Q = PN4; + +-- ==================================== + +-- ********** Pages decoder *********** + +-- ==================================== + + PG3[] = (!PN7,VCC,LCELL((SC4 & !CNF7) or (CNF7 & PN6)),PN[2..0]); + +-- SC0,SC1,SYS,DOS,PN4,AROM16,CASH_ON,NMI_ENA + PG0[] = (VCC,GND, + LCELL(SC0 or !SYS or CASH_ON or !NMI_ENA), + LCELL(((AROM16 & !(SC0 & SYS)) or (CASH_ON & NMI_ENA))), + LCELL((SPR_1 & SC_LCELL) or !SYS or !NMI_ENA), + LCELL((SPR_0 & SC_LCELL) or !SYS or !NMI_ENA)); + +-- SC_LCELL = LCELL(!(SC0 & SYS) & !CASH_ON); + SC_LCELL = (!(SC0 & SYS) & !CASH_ON); + + NMI_ENA = VCC; + + SPR_[] = !SC1 & (DOS,(PN4 or !DOS)); -- expansion/dos/basic128/basic48 + + CASE (TEST_R,SYS) IS + WHEN B"X0" => RA[] = (!AROM16,B"000"); -- system 0/1 + WHEN B"01" => RA[] = (!AROM16,GND,SPR_[]); -- expansion/dos/basic + WHEN B"11" => RA[] = (B"001",SPR_0); -- test + END CASE; + +-- ==================================== + + CASE A[15..14] IS + WHEN 0 => MPGS[5..0] = PG0[]; + WHEN 1 => MPGS[5..0] = B"101001"; %H"E9"% + WHEN 2 => MPGS[5..0] = B"101010"; %H"EA"% + WHEN 3 => MPGS[5..0] = PG3[]; + END CASE; + MPGS[7..6] = VCC; + +-- STARTING = DFF(GND,VCC,/RESET,(/IO or /RD)); + STARTING = LCELL(/RESET & (STARTING or !(/IO or /RD))); + + PGS[].clk = !CLK42; + CASE (LCELL(/IO & !(A14 & A15 & !STARTING)),MC_END) IS + WHEN B"1X" => PGS[] = (VCC,VCC,MPGS[5..0]); + WHEN B"01" => PGS[] = DD[]; + WHEN B"00" => PGS[] = GND; + END CASE; + + MEM_WR = DFFE((DCPP[7] & DCPP[6] & STARTING & DFF(DFF((MC_END & !/WR),CLK42,,),CLK42,,)),CLK42,!/IO,,CT1); + + ADR8_MEM = GND; + + CASE ADR8_MEM IS + WHEN 1 => MEM_D[] = (DI[],MEM.q[7..0]); DO[] = MEM.q[15..8]; + WHEN 0 => MEM_D[] = (MEM.q[15..8],DI[]); DO[] = MEM.q[7..0]; + END CASE; + + MEM.wren = MEM_WR; + MEM.data[] = MEM_D[]; + MEM.wraddress[] = PGS[]; + MEM.wrclock = CLK42; + MEM.wrclken = VCC; + MEM.rden = VCC; + MEM.rdaddress[] = PGS[]; + MEM.rdclock = CLK42; + MEM.rdclken = VCC; +-- = MEM.q[]; + + PAGE[] = MEM.q[11..0]; + TYPE[] = MEM.q[15..12]; + + + PORT = !(MEM.q[15..12] == 0) or /IO or (/RD & /WR); + +END; + + diff --git a/src/altera/quartus/acex/KBD.ACF b/src/altera/quartus/acex/KBD.ACF new file mode 100644 index 0000000..6ef977a --- /dev/null +++ b/src/altera/quartus/acex/KBD.ACF @@ -0,0 +1,568 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP kbd +BEGIN + DEVICE = EP1K30QC208-3; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EP1K100FC484-1; + AUTO_DEVICE = EP1K100FC256-1; + AUTO_DEVICE = EP1K100QC208-1; + AUTO_DEVICE = EP1K50FC484-1; + AUTO_DEVICE = EP1K50FC256-1; + AUTO_DEVICE = EP1K50QC208-1; + AUTO_DEVICE = EP1K50TC144-1; + AUTO_DEVICE = EP1K30FC256-1; + AUTO_DEVICE = EP1K30QC208-1; + AUTO_DEVICE = EP1K30TC144-1; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3; + FREQUENCY = 100MHz; + MAINTAIN_STABLE_SYNTHESIS = OFF; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; +END; + +IGNORED_ASSIGNMENTS +BEGIN + FIT_IGNORE_TIMING = OFF; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + MAX7000B_ENABLE_VREFB = OFF; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + FLEX_CONFIGURATION_EPROM = AUTO; + MAX7000AE_ENABLE_JTAG = ON; + MAX7000AE_USER_CODE = FFFFFFFF; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + MULTIVOLT_IO = OFF; + MAX7000S_ENABLE_JTAG = ON; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_USER_CODE = FFFF; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + nCEO = UNRESERVED; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + DATA0 = RESERVED_TRI_STATED; + FLEX8000_ENABLE_JTAG = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + DISABLE_TIME_OUT = OFF; + ENABLE_DCLK_OUTPUT = OFF; + RELEASE_CLEARS = OFF; + AUTO_RESTART = OFF; + USER_CLOCK = OFF; + SECURITY_BIT = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + STYLE = FAST; + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_REGISTER_PACKING = OFF; + DEVICE_FAMILY = ACEX1K; + AUTO_FAST_IO = OFF; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_PRESET = ON; + AUTO_GLOBAL_CLEAR = ON; + AUTO_GLOBAL_CLOCK = ON; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; + OPTIMIZE_FOR_SPEED = 5; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + USE_QUARTUS_FITTER = ON; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; + FITTER_SETTINGS = NORMAL; + SMART_RECOMPILE = OFF; + GENERATE_AHDL_TDO_FILE = OFF; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + TIMING_SNF_EXTRACTOR = ON; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + DESIGN_DOCTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VHDL_WRITER_VERSION = VHDL87; + VHDL_READER_VERSION = VHDL87; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + MASTER_RESET = OFF; + EXPANDER_NETWORKS = ON; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + ASYNCHRONOUS_INPUTS = ON; + PRESET_CLEAR_NETWORKS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_CLOCK_NETWORKS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + BIDIR_PIN = STRONG; + END_TIME = 0.0ns; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + ANALYSIS_MODE = REGISTERED_PERFORMANCE; + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; + LIST_PATH_FREQUENCY = 10MHz; + LIST_PATH_COUNT = 10; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; +END; + +OTHER_CONFIGURATION +BEGIN + LAST_MAXPLUS2_VERSION = 10.0; + EXPLICIT_FAMILY = 1; + ROW_PINS_LCELL_INSERT = ON; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + NORMAL_LCELL_INSERT = ON; + FLEX_10K_52_COLUMNS = 40; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ROW_PINS_PERCENT = 50; + ORIGINAL_MAXPLUS2_VERSION = 9.6; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = ON; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = AUTO; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/src/altera/quartus/acex/KBD.INC b/src/altera/quartus/acex/KBD.INC new file mode 100644 index 0000000..a6b7f8d --- /dev/null +++ b/src/altera/quartus/acex/KBD.INC @@ -0,0 +1,26 @@ +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. + +-- MAX+plus II Include File +-- Version 10.0 9/14/2000 +-- Created: Thu May 03 21:43:31 2001 + +FUNCTION kbd (clk42, clk_k, kbd_cc, kbd_dd, /rf, /io, /iom, /m1, a[15..8], ena, int_ena) + RETURNS (kbo[7..0], kb_reset, kb_f12, kb_ctrl, kb_alt, kb_sh, int); diff --git a/src/altera/quartus/acex/KBD.TDF b/src/altera/quartus/acex/KBD.TDF new file mode 100644 index 0000000..20e40be --- /dev/null +++ b/src/altera/quartus/acex/KBD.TDF @@ -0,0 +1,180 @@ + + TITLE "ZX-Keyboard"; + +INCLUDE "lpm_ram_dq"; + +SUBDESIGN kbd + ( + CLK42 : INPUT; -- full sinc 42MHz + CLK_K : INPUT; -- sinc input 15KHz + KBD_CC : INPUT; -- sinc KBD + KBD_DD : INPUT; -- data KBD + + /RF : INPUT; -- /rfsh + /IO : INPUT; -- /iorq + /IOM : INPUT; + /M1 : INPUT; + + A[15..8] : INPUT; + + KBO[7..0] : OUTPUT; -- output + + KB_RESET : OUTPUT; + + KB_F12 : OUTPUT; + KB_CTRL : OUTPUT; + KB_ALT : OUTPUT; + KB_SH : OUTPUT; + + ENA : INPUT; + INT_ENA : INPUT; + INT : OUTPUT; + ) +VARIABLE + + KB_CT[2..0] : DFF; + KB_D[10..0] : DFF; + KB_OFF : DFFE; + + KB_EXT : DFF; + KB_ALT : DFF; + KB_CTRL : DFF; + KB_SH : DFF; + + KB_CTRL_X : NODE; + KB_ALT_X : NODE; + KB_SH_X : NODE; + KB_XXX : NODE; + KB_RESET : DFF; + RXA[1..0] : DFFE; + + K_CLK : NODE; + KA[15..0] : NODE; + KB_MA[2..0] : DFF; + KB_MXA : NODE; + KDCA[2..0] : LCELL; + + KDD[7..0] : DFF; + KBD[5..0] : DFF; + KD[7..0] : NODE; + KDX[5..0] : DFF; + KDXX[5..0] : DFF; + WR_KBD : NODE; + KB_OFL : NODE; + +BEGIN + + INT = DFF((KB_CT[] == 0),CLK42,,INT_ENA); + +-- KB_CT[].clk = DFF(CLK_K,CLK42,,); + KB_CT[].clk = CLK_K; + KB_CT[].prn = DFF(KBD_CC,CLK42,,); + + CASE KB_CT[] IS + WHEN 0 => KB_CT[].d = GND; + WHEN 1,2,3,4,5,6,7 => KB_CT[].d = KB_CT[] - 1; + END CASE; + + KB_D[].clk = DFF(!KBD_CC,CLK42,,); + KB_D[].d = (KBD_DD,KB_D[10..1]); + + KB_OFF.ena = !KB_EXT; + KB_OFF.clk = DFF((KB_CT[] == 0),CLK42,,); + KB_OFF.d = KB_D[] == B"XX11110000X"; + + KB_EXT.clk = DFF((KB_CT[] == 1),CLK42,,); + KB_EXT.d = KB_D[] == B"XX11100000X"; + + KB_CTRL.clk = !KB_CT2; + KB_ALT.clk = !KB_CT2; + KB_SH.clk = !KB_CT2; + + KB_CTRL_X = LCELL(KB_D[] == B"XXXXX1X100X"); + KB_ALT_X = LCELL(KB_D[] == B"XXXXX1X001X"); + KB_SH_X = LCELL(KB_D[] == B"XX0X01X0XXX") & + CASCADE((KB_D[] == B"XXX1XX1X01X") or (KB_D[] == B"XXX0XX0X10X")); + KB_XXX = LCELL(KB_D[] == B"XX000X0XXXX"); + + CASE KB_OFF IS + WHEN 0 => + KB_CTRL.d = (KB_CTRL_X & KB_XXX) or KB_CTRL; + KB_ALT.d = (KB_ALT_X & KB_XXX) or KB_ALT; + KB_SH.d = (KB_SH_X) or KB_SH; + WHEN 1 => + KB_CTRL.d = !(KB_CTRL_X & KB_XXX) & KB_CTRL; + KB_ALT.d = !(KB_ALT_X & KB_XXX) & KB_ALT; + KB_SH.d = !(KB_SH_X) & KB_SH; + END CASE; + + KB_F12 = DFF(!((KB_XXX & LCELL(KB_D[] == B"XXXXX0X111X")) & !KB_OFF), + !KB_CT2,,!(KB_CT[] == 1)); + + KB_RESET.clk = !KB_CT2; + KB_RESET.d = !(KB_ALT_X & (KB_D[] == B"XX011X0XXXX") & !KB_OFF & KB_CTRL & KB_ALT); + KB_RESET.prn = !DFF((KB_CT[] == 1),CLK42,,); + + K_CLK = DFF(/RF,CLK42,,); + + RXA[].ena = VCC; + RXA[].clk = K_CLK; + + CASE DFF((!(KB_CT[] == B"01X") & (RXA[] == 0)),CLK42,,) IS + WHEN B"1" => RXA[] = GND; + WHEN B"0" => RXA[] = (RXA0,!RXA1); + END CASE; + + CASE (DFF((/IO & (RXA[] == 0),CLK42,,)),LCELL(KDD7 & KDD6)) IS + WHEN B"0X" => KA[15..8] = (B"101",KDCA[],B"11"); + WHEN B"10" => KA[15..8] = (B"110000",KDD7,KDD6); + WHEN B"11" => KA[15..8] = KB_D[8..1]; + END CASE; + + KB_MA[].clk = CLK42; + KB_MA[].d = KB_MA[] + 1; + KB_MA[].clrn = !DFF(/IO,CLK42,,); + + KB_MXA = DFF(( (((KB_MA[] == 7) & A15) or ((KB_MA[] == 6) & A14)) + or (((KB_MA[] == 5) & A13) or ((KB_MA[] == 4) & A12)) + or (((KB_MA[] == 3) & A11) or ((KB_MA[] == 2) & A10)) + or (((KB_MA[] == 1) & A9 ) or ((KB_MA[] == 0) & A8 ))),CLK42,,); + + IF !DFF(/IO,CLK42,,) THEN + KDCA[] = KB_MA[]; + ELSE + KDCA[] = KDD[5..3]; + END IF; + + KDD[].clk = RXA0; + KDD[].d = KD[]; + KDD[7..6].prn = !KB_CT2; + + KDXX[].clk = RXA0; + KDXX[].d = !((KD[2..0] == 5),(KD[2..0] == 4), + (KD[2..0] == 3),(KD[2..0] == 2), + (KD[2..0] == 1),(KD[2..0] == 0)); + + KDX[].clk = RXA1; + + CASE KB_OFF IS + WHEN B"0" => KDX[].d = (KD[5..0] & KDXX[]); + WHEN B"1" => KDX[].d = (KD[5..0] or !KDXX[]); + END CASE; + +-- ============================== + + WR_KBD = K_CLK or !DFF((KB_CT[] == 2),CLK42,,) or !(RXA[] == 3); + + KD[] = lpm_ram_dq((B"11",KDX[5..0]),KA[15..8],!WR_KBD,CLK42,) + WITH (lpm_width=8,lpm_widthad=8,lpm_file="KBD_INI2.MIF", + lpm_outdata="UNREGISTERED"); + + KBD[].clk = CLK42; + KBD[].prn = DFF(VCC,KB_MA2,(!/IO & ENA),); + +-- KBD[].prn = DFF(!/IOM,CLK42,,); + KBD[].d = KBD[] & (KD[5..0] or KB_MXA); + + KBO[] = (VCC,VCC,KBD[]); + +END; + diff --git a/src/altera/quartus/acex/KBD_INI2.MIF b/src/altera/quartus/acex/KBD_INI2.MIF new file mode 100644 index 0000000..43e7390 --- /dev/null +++ b/src/altera/quartus/acex/KBD_INI2.MIF @@ -0,0 +1,167 @@ +DEPTH = 256; % Memory depth and width are required % +WIDTH = 8; % Enter a decimal number % + +ADDRESS_RADIX = HEX; % Address and value radixes are optional % +DATA_RADIX = BIN; % Enter BIN, DEC, HEX, or OCT; unless % + % otherwise specified, radixes = HEX % + +-- Specify values for addresses, which can be single address or range + +CONTENT + BEGIN +[0..FF] : 11111111; +0 : + 11111111 % .. % + 00100001 % F9 % + 11111111 % .. % + 00011100 % F5 % + 00011010 % F3 % + 00011000 % F1 % + 00011001 % F2 % + 11111111 % F12 % + 11111111 % .. % + 00100000 % F10 % + + 00100010 % F8 % + 00100100 % F6 % + 00011011 % F4 % + 01011000 % Tab % + 10001000 % ~` % + 11111111 % .. % + 11111111 % .. % + 01111001 % Alt % + 11000000 % Left Shift % + 11111111 % .. % + + 11111001 % Ctrl % + 11010000 % 'Q' % + 11011000 % '1' % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11000001 % 'Z' % + 11001001 % 'S' % + 11001000 % 'A' % + 11010001 % 'W' % + + 11011001 % '2' % + 01110000 % left WIN % + 11111111 % .. % + 11000011 % 'C' % + 11000010 % 'X' % + 11001010 % 'D' % + 11010010 % 'E' % + 11011011 % '4' % + 11011010 % '3' % + 10110000 % Right WIN % + + 11111111 % .. % + 11111000 % ' ' % + 11000100 % 'V' % + 11001011 % 'F' % + 11010100 % 'T' % + 11010011 % 'R' % + 11011100 % '5' % + 10111000 % Right Mouse % + 11111111 % .. % + 11111011 % 'N' % + + 11111100 % 'B' % + 11110100 % 'H' % + 11001100 % 'G' % + 11101100 % 'Y' % + 11100100 % '6' % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11111010 % 'M' % + 11110011 % 'J' % + + 11101011 % 'U' % + 11100011 % '7' % + 11100010 % '8' % + 11111111 % .. % + 11111111 % .. % + 10111011 % ',' % + 11110010 % 'K' % + 11101010 % 'I' % + 11101001 % 'O' % + 11100000 % '0' % + + 11100001 % '9' % + 11111111 % .. % + 11111111 % .. % + 10111010 % '.' % + 10000100 % '/' % + 11110001 % 'L' % + 10101001 % ';' % + 11101000 % 'P' % + 10110011 % '-' % + 11111111 % .. % + + 11111111 % .. % + 11111111 % .. % + 10101000 % "'" % + 11111111 % .. % + 10101100 % '[' % + 10110001 % '=' % + 11111111 % .. % + 11111111 % .. % + 01011001 % Caps Lock % + 11000000 % Right SHIFT % + + 11110000 % ENTER % + 10101011 % ']' % + 11111111 % .. % + 10001010 % '\' % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + + 11111111 % .. % + 11111111 % .. % + 01100000 % Back % + 11111111 % .. % + 11111111 % .. % + 10010010 % End % + 11111111 % .. % + 01011100 % <- % + 10010000 % Home % + 11111111 % .. % + + 11111111 % .. % + 11111111 % .. % + 10010001 % ins % + 01100001 % DEL % + 01100100 % Dn % + 10101010 % grey 5 ; ctrl + I % + 01100010 % -> % + 01100011 % Up % + 01111000 % ESC % + 00111111 % Num % + + 11111111 % F11 % + 10110010 % G+ % + 01011011 % PDn ; caps + 4 % + 10110011 % G- % + 10111100 % G* % + 01011010 % PUp ; caps + 3 % + 00000000 % Scrol Lock % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + + 11111111 % .. % + 00100011 % F7 % ; +% !! DATA FOR CAPS !! % +C0 : + 11111101 % Function shift % + 11000000 % Left Shift % + 11111001 % Ctrl % + 11111111 ; % no shift % +END ; + + diff --git a/src/altera/quartus/acex/MOUSE.ACF b/src/altera/quartus/acex/MOUSE.ACF new file mode 100644 index 0000000..ba8c48d --- /dev/null +++ b/src/altera/quartus/acex/MOUSE.ACF @@ -0,0 +1,571 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP mouse +BEGIN + DEVICE = EP1K30QC208-3; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EP1K100FC484-1; + AUTO_DEVICE = EP1K100FC256-1; + AUTO_DEVICE = EP1K100QC208-1; + AUTO_DEVICE = EP1K50FC484-1; + AUTO_DEVICE = EP1K50FC256-1; + AUTO_DEVICE = EP1K50QC208-1; + AUTO_DEVICE = EP1K50TC144-1; + AUTO_DEVICE = EP1K30FC256-1; + AUTO_DEVICE = EP1K30QC208-1; + AUTO_DEVICE = EP1K30TC144-1; + AUTO_DEVICE = EP1K10FC256-1; + AUTO_DEVICE = EP1K10QC208-1; + AUTO_DEVICE = EP1K10TC144-1; + AUTO_DEVICE = EP1K10TC100-1; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3; + FREQUENCY = 200MHz; + MAINTAIN_STABLE_SYNTHESIS = OFF; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; +END; + +IGNORED_ASSIGNMENTS +BEGIN + FIT_IGNORE_TIMING = OFF; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + MAX7000B_ENABLE_VREFB = OFF; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + FLEX_CONFIGURATION_EPROM = AUTO; + MAX7000AE_ENABLE_JTAG = ON; + MAX7000AE_USER_CODE = FFFFFFFF; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + MULTIVOLT_IO = OFF; + MAX7000S_ENABLE_JTAG = ON; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_USER_CODE = FFFF; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + nCEO = UNRESERVED; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + DATA0 = RESERVED_TRI_STATED; + FLEX8000_ENABLE_JTAG = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + DISABLE_TIME_OUT = OFF; + ENABLE_DCLK_OUTPUT = OFF; + RELEASE_CLEARS = OFF; + AUTO_RESTART = OFF; + USER_CLOCK = OFF; + SECURITY_BIT = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + STYLE = FAST; + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_REGISTER_PACKING = OFF; + DEVICE_FAMILY = ACEX1K; + AUTO_FAST_IO = OFF; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_PRESET = ON; + AUTO_GLOBAL_CLEAR = ON; + AUTO_GLOBAL_CLOCK = ON; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; + OPTIMIZE_FOR_SPEED = 5; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + USE_QUARTUS_FITTER = ON; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; + FITTER_SETTINGS = NORMAL; + SMART_RECOMPILE = OFF; + GENERATE_AHDL_TDO_FILE = OFF; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + TIMING_SNF_EXTRACTOR = ON; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + DESIGN_DOCTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VHDL_WRITER_VERSION = VHDL93; + VHDL_READER_VERSION = VHDL93; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + MASTER_RESET = OFF; + EXPANDER_NETWORKS = ON; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + ASYNCHRONOUS_INPUTS = ON; + PRESET_CLEAR_NETWORKS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_CLOCK_NETWORKS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + END_TIME = 10.0us; + BIDIR_PIN = STRONG; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; + LIST_PATH_FREQUENCY = 10MHz; + LIST_PATH_COUNT = 10; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; + ANALYSIS_MODE = DELAY_MATRIX; +END; + +OTHER_CONFIGURATION +BEGIN + EXPLICIT_FAMILY = 1; + ROW_PINS_LCELL_INSERT = ON; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + NORMAL_LCELL_INSERT = ON; + LAST_MAXPLUS2_VERSION = 10.0; + FLEX_10K_52_COLUMNS = 40; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ROW_PINS_PERCENT = 50; + ORIGINAL_MAXPLUS2_VERSION = 10.0; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = ON; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = AUTO; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/src/altera/quartus/acex/MOUSE.INC b/src/altera/quartus/acex/MOUSE.INC new file mode 100644 index 0000000..580ab4b --- /dev/null +++ b/src/altera/quartus/acex/MOUSE.INC @@ -0,0 +1,26 @@ +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. + +-- MAX+plus II Include File +-- Version 10.0 9/14/2000 +-- Created: Sat Jun 16 17:49:35 2001 + +FUNCTION mouse (mouse_d, clk) + RETURNS (out_x[9..0], out_y[9..0], out_k[1..0], int); diff --git a/src/altera/quartus/acex/MOUSE.MIF b/src/altera/quartus/acex/MOUSE.MIF new file mode 100644 index 0000000..c6f96ef --- /dev/null +++ b/src/altera/quartus/acex/MOUSE.MIF @@ -0,0 +1,65 @@ +DEPTH = 256; % Memory depth and width are required % +WIDTH = 16; % Enter a decimal number % + +ADDRESS_RADIX = HEX; % Address and value radixes are optional % +DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % + % otherwise specified, radixes = HEX % + +-- Specify values for addresses, which can be single address or range + +CONTENT +BEGIN + + [0..FF] : 0; + +% + 11 + 1211 + 122211 + 12222211 + 1222222211 + 122222222211 + 1222222211 + 12222221 + 12222221 + 121112221 + 11 12221 + 1 1221 + 111 + + + +% + + 00 : 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0; + 10 : 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0; + 20 : 1 2 2 2 1 1 0 0 0 0 0 0 0 0 0 0; + 30 : 1 2 2 2 2 2 1 1 0 0 0 0 0 0 0 0; + 40 : 1 2 2 2 2 2 2 2 1 1 0 0 0 0 0 0; + 50 : 1 2 2 2 2 2 2 2 2 2 1 1 0 0 0 0; + 60 : 1 2 2 2 2 2 2 2 1 1 0 0 0 0 0 0; + E0 : 1 2 2 2 2 2 2 1 0 0 0 0 0 0 0 0; + 70 : 1 2 2 2 2 2 2 1 0 0 0 0 0 0 0 0; + 80 : 1 2 1 1 1 2 2 2 1 0 0 0 0 0 0 0; + 90 : 1 1 0 0 0 1 2 2 2 1 0 0 0 0 0 0; + A0 : 1 0 0 0 0 0 1 2 2 1 0 0 0 0 0 0; + B0 : 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0; + C0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0; + D0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0; + E0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0; + F0 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0; + +% + + 1110 0000 0000 0 00 0000 0000 0000 0000 + 1000 0000 0000 0100 0000 0100 0000 0000 + 1000 1100 1010 0000 1100 1110 0100 1010 + 1110 1010 1100 0100 1010 0100 1010 1100 + 0010 1010 1000 0100 1010 0100 1110 1000 + 0010 1100 1000 0100 1010 0100 1000 1000 + 1110 1000 1000 0100 1010 0010 0110 1000 + 0000 1000 0000 0000 0000 0000 0000 0000 + +% + +END; diff --git a/src/altera/quartus/acex/MOUSE.TDF b/src/altera/quartus/acex/MOUSE.TDF new file mode 100644 index 0000000..bb5770d --- /dev/null +++ b/src/altera/quartus/acex/MOUSE.TDF @@ -0,0 +1,76 @@ + + TITLE "Sp-Mouse"; + +INCLUDE "lpm_add_sub"; + +SUBDESIGN mouse + ( + MOUSE_D : INPUT; + CLK : INPUT; + OUT_X[9..0] : OUTPUT; + OUT_Y[9..0] : OUTPUT; + OUT_K[1..0] : OUTPUT; + INT : OUTPUT; + ) +VARIABLE + + SUM_X[9..0] : DFFE; + SUM_Y[9..0] : DFFE; + + CT[3..0] : DFF; + RG[9..0] : DFFE; + STATE[1..0] : DFFE; + RGK[5..0] : DFFE; + + MOUSE_IMP : NODE; + + DDX[7..0] : NODE; + DDY[7..0] : NODE; + +BEGIN + + CT[].clk = CLK; + + MOUSE_IMP = MOUSE_D xor !DFF(MOUSE_D,CLK,,); + + CT[].clrn = MOUSE_IMP; + + IF CT[] == 12 THEN + CT[] = GND; + ELSE + CT[] = CT[]+1; + END IF; + + RG[].clk = CLK; + RG[].ena = (CT[] == 4) or !RG0; + RG[].d = ((MOUSE_D,RG[9..1]) or !RG0); + RG[].prn = VCC; + + STATE[].ena = !RG0; + STATE[].clk = CLK; + + STATE[].d = (STATE0,RG7); + + RGK[].clk = CLK; + RGK[].ena = (RG7 & !RG0); + RGK[].d = RG[6..1]; + + DDX[] = (RGK[1..0],RG[6..1]); + DDY[] = (RGK[3..2],RG[6..1]); + + SUM_X[].ena = LCELL(!RG7 & (STATE[] == 1) & !RG0); + SUM_Y[].ena = LCELL(!RG7 & (STATE[] == 2) & !RG0); + + SUM_X[].clk = CLK; + SUM_Y[].clk = CLK; + + SUM_X[] = SUM_X[] + (DDX7,DDX7,DDX[]); + SUM_Y[] = SUM_Y[] + (DDY7,DDY7,DDY[]); + + OUT_X[] = SUM_X[]; + OUT_Y[] = SUM_Y[]; + OUT_K[] = RGK[5..4]; + + INT = DFF(((STATE[] == 2) & !RG0),CLK,,); + +END; diff --git a/src/altera/quartus/acex/SP2_ACEX.ACF b/src/altera/quartus/acex/SP2_ACEX.ACF new file mode 100644 index 0000000..063fc3a --- /dev/null +++ b/src/altera/quartus/acex/SP2_ACEX.ACF @@ -0,0 +1,1366 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP SP2_ACEX +BEGIN + DEVICE = EP1K30QC208-3; + |CASXE1 : LOCATION = LC8_B36; + |CASXE0 : LOCATION = LC7_B36; + |CASX_3 : LOCATION = LC6_B36; + |CASX_2 : LOCATION = LC2_B36; + |CASX_1 : LOCATION = LC5_B36; + |CASX_0 : LOCATION = LC1_B36; + "|video2:SVIDEO|V_WRM" : LOCATION = LC8_F18; + "|video2:SVIDEO|V_WEM2" : LOCATION = LC2_F20; + "|video2:SVIDEO|V_WE_R" : LOCATION = LC5_F11; + "|video2:SVIDEO|V_WEMMO" : LOCATION = LC3_F15; + "|video2:SVIDEO|V_WEM" : LOCATION = LC2_F18; + "|video2:SVIDEO|V_WRM2" : LOCATION = LC8_F20; + "|video2:SVIDEO|V_WEMMM" : LOCATION = LC3_F12; + "|video2:SVIDEO|V_WEMMN" : LOCATION = LC2_F12; + "|video2:SVIDEO|V_WE" : LOCATION = LC6_F12; + "|video2:SVIDEO|V_CSX2" : LOCATION = LC5_F4; + "|video2:SVIDEO|V_CSX1" : LOCATION = LC5_F5; + "|video2:SVIDEO|V_CSX0" : LOCATION = LC5_F3; + "|dcp:DECODE|WR_AWGX" : LOCATION = LC2_A15; + "|video2:SVIDEO|V_WEMM" : LOCATION = LC4_F17; + "|video2:SVIDEO|V_WEY2" : LOCATION = LC2_F19; + "|video2:SVIDEO|V_WEY3" : LOCATION = LC2_F14; + "|video2:SVIDEO|V_WEY1" : LOCATION = LC2_F16; + "|video2:SVIDEO|V_WEY0" : LOCATION = LC2_F17; + "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_0" : LOCATION = EAB_D; + "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_1" : LOCATION = EAB_D; + "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_2" : LOCATION = EAB_D; + "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_3" : LOCATION = EAB_D; + "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_4" : LOCATION = EAB_D; + "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_5" : LOCATION = EAB_D; + "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_6" : LOCATION = EAB_D; + "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_7" : LOCATION = EAB_D; + |V_WRX3 : LOCATION = LC1_F14; + |V_WRX1 : LOCATION = LC1_F16; + |V_WRX0 : LOCATION = LC1_F17; + "|video2:SVIDEO|V_WR_1" : LOCATION = LC8_F16; + "|video2:SVIDEO|V_WR_0" : LOCATION = LC8_F17; + "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_0" : LOCATION = EAB_E; + "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_1" : LOCATION = EAB_E; + "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_2" : LOCATION = EAB_E; + "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_3" : LOCATION = EAB_E; + "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_4" : LOCATION = EAB_E; + "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_5" : LOCATION = EAB_E; + "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_6" : LOCATION = EAB_E; + "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_7" : LOCATION = EAB_E; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_0" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_1" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_2" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_3" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_4" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_5" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_6" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_7" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_8" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_9" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_10" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_11" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_12" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_13" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_14" : LOCATION = EAB_C; + "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_15" : LOCATION = EAB_C; + "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_0" : LOCATION = EAB_B; + "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_1" : LOCATION = EAB_B; + "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_2" : LOCATION = EAB_B; + "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_3" : LOCATION = EAB_B; + "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_4" : LOCATION = EAB_B; + "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_5" : LOCATION = EAB_B; + "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_6" : LOCATION = EAB_B; + "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_7" : LOCATION = EAB_B; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_5" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_6" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_7" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_8" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_9" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_10" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_11" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_12" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_13" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_14" : LOCATION = EAB_A; + "|lpm_ram_dp:CBL|altdpram:sram|segment0_15" : LOCATION = EAB_A; + |V_WRX2 : LOCATION = LC1_F19; + "|video2:SVIDEO|V_WR_2" : LOCATION = LC8_F19; + "|video2:SVIDEO|V_WR_3" : LOCATION = LC8_F14; + "|dcp:DECODE|:285" : LOCATION = LC2_A32; + |RASX_0 : LOCATION = LC2_A35; + |RASX_1 : LOCATION = LC2_A34; + |XA3 : BIDIR_PIN = 17; + |XA1 : BIDIR_PIN = 9; + |XA2 : BIDIR_PIN = 200; + |XA0 : BIDIR_PIN = 180; + |VD30 : BIDIR_PIN = 114; + |VD31 : BIDIR_PIN = 136; + |VD32 : BIDIR_PIN = 144; + |VD33 : BIDIR_PIN = 148; + |VD34 : BIDIR_PIN = 149; + |VD35 : BIDIR_PIN = 143; + |VD36 : BIDIR_PIN = 139; + |VD37 : BIDIR_PIN = 128; + |VD20 : BIDIR_PIN = 150; + |VD21 : BIDIR_PIN = 115; + |VD22 : BIDIR_PIN = 135; + |VD23 : BIDIR_PIN = 140; + |VD24 : BIDIR_PIN = 141; + |VD25 : BIDIR_PIN = 147; + |VD26 : BIDIR_PIN = 142; + |VD27 : BIDIR_PIN = 131; + |VD10 : BIDIR_PIN = 104; + |VD11 : BIDIR_PIN = 111; + |VD12 : BIDIR_PIN = 120; + |VD13 : BIDIR_PIN = 127; + |VD14 : BIDIR_PIN = 132; + |VD15 : BIDIR_PIN = 134; + |VD16 : BIDIR_PIN = 133; + |VD17 : BIDIR_PIN = 122; + |VD00 : BIDIR_PIN = 103; + |VD01 : BIDIR_PIN = 113; + |VD02 : BIDIR_PIN = 116; + |VD03 : BIDIR_PIN = 121; + |VD04 : BIDIR_PIN = 126; + |VD05 : BIDIR_PIN = 125; + |VD06 : BIDIR_PIN = 119; + |VD07 : BIDIR_PIN = 112; + |/RESET : BIDIR_PIN = 19; + |MD15 : BIDIR_PIN = 179; + |MD14 : BIDIR_PIN = 187; + |MD12 : BIDIR_PIN = 192; + |MD11 : BIDIR_PIN = 198; + |MD10 : BIDIR_PIN = 204; + |MD9 : BIDIR_PIN = 208; + |MD8 : BIDIR_PIN = 8; + |MD7 : BIDIR_PIN = 161; + |MD6 : BIDIR_PIN = 162; + |MD5 : BIDIR_PIN = 163; + |MD4 : BIDIR_PIN = 164; + |MD3 : BIDIR_PIN = 186; + |MD2 : BIDIR_PIN = 190; + |MD1 : BIDIR_PIN = 193; + |MD0 : BIDIR_PIN = 196; + |D7 : BIDIR_PIN = 61; + |D6 : BIDIR_PIN = 60; + |D5 : BIDIR_PIN = 58; + |D4 : BIDIR_PIN = 57; + |D3 : BIDIR_PIN = 56; + |D2 : BIDIR_PIN = 55; + |D1 : BIDIR_PIN = 54; + |D0 : BIDIR_PIN = 53; + |XACS : OUTPUT_PIN = 169; + |WR_DWG : OUTPUT_PIN = 11; + |WR_COL : OUTPUT_PIN = 157; + |WR_AWG : OUTPUT_PIN = 176; + |/WE : OUTPUT_PIN = 16; + |V_WR3 : OUTPUT_PIN = 88; + |V_WR2 : OUTPUT_PIN = 75; + |V_WR1 : OUTPUT_PIN = 85; + |V_WR0 : OUTPUT_PIN = 83; + |V_CS0 : OUTPUT_PIN = 101; + |V_CS1 : OUTPUT_PIN = 70; + |VA15 : OUTPUT_PIN = 71; + |VA14 : OUTPUT_PIN = 73; + |VA13 : OUTPUT_PIN = 87; + |VA12 : OUTPUT_PIN = 74; + |VA11 : OUTPUT_PIN = 95; + |VA10 : OUTPUT_PIN = 99; + |VA9 : OUTPUT_PIN = 93; + |VA4 : OUTPUT_PIN = 94; + |VA5 : OUTPUT_PIN = 92; + |VA8 : OUTPUT_PIN = 90; + |VA7 : OUTPUT_PIN = 86; + |VA6 : OUTPUT_PIN = 89; + |VA3 : OUTPUT_PIN = 96; + |VA2 : OUTPUT_PIN = 97; + |VA1 : OUTPUT_PIN = 100; + |VA0 : OUTPUT_PIN = 102; + |SXA : OUTPUT_PIN = 7; + |RDXA : OUTPUT_PIN = 173; + |RD_KMPS : OUTPUT_PIN = 10; + |RA17 : OUTPUT_PIN = 67; + |RA16 : OUTPUT_PIN = 68; + |RA15 : OUTPUT_PIN = 69; + |RA14 : OUTPUT_PIN = 65; + |RAS_1 : OUTPUT_PIN = 205; + |RAS_0 : OUTPUT_PIN = 207; + |MA14 : OUTPUT_PIN = 191; + |MA13 : OUTPUT_PIN = 195; + |MA12 : OUTPUT_PIN = 206; + |MA11 : OUTPUT_PIN = 199; + |MA10 : OUTPUT_PIN = 177; + |MA9 : OUTPUT_PIN = 203; + |MA8 : OUTPUT_PIN = 202; + |MA7 : OUTPUT_PIN = 197; + |MA6 : OUTPUT_PIN = 175; + |MA5 : OUTPUT_PIN = 174; + |MA4 : OUTPUT_PIN = 172; + |MA3 : OUTPUT_PIN = 170; + |MA2 : OUTPUT_PIN = 168; + |MA1 : OUTPUT_PIN = 167; + |MA0 : OUTPUT_PIN = 166; + |DAC_WS : OUTPUT_PIN = 159; + |DAC_DATA : OUTPUT_PIN = 158; + |DAC_BCK : OUTPUT_PIN = 160; + |CS_CASH : OUTPUT_PIN = 64; + |CS_ROM : OUTPUT_PIN = 63; + |CLKZ1 : OUTPUT_PIN = 62; + |CAS_3 : OUTPUT_PIN = 15; + |CAS_2 : OUTPUT_PIN = 13; + |CAS_1 : OUTPUT_PIN = 14; + |CAS_0 : OUTPUT_PIN = 12; + |/WAIT : BIDIR_PIN = 18; + |/RF : INPUT_PIN = 25; + |/M1 : INPUT_PIN = 24; + |/WR : INPUT_PIN = 79; + |TG42 : INPUT_PIN = 183; + |/RD : INPUT_PIN = 80; + |/IO : INPUT_PIN = 78; + |/MR : INPUT_PIN = 184; + |/HALT : INPUT_PIN = 182; + |A15 : INPUT_PIN = 47; + |A14 : INPUT_PIN = 46; + |A13 : INPUT_PIN = 45; + |A12 : INPUT_PIN = 44; + |A11 : INPUT_PIN = 41; + |A10 : INPUT_PIN = 40; + |A9 : INPUT_PIN = 39; + |A8 : INPUT_PIN = 38; + |A7 : INPUT_PIN = 37; + |A6 : INPUT_PIN = 36; + |A5 : INPUT_PIN = 31; + |A4 : INPUT_PIN = 30; + |A3 : INPUT_PIN = 29; + |A2 : INPUT_PIN = 28; + |A1 : INPUT_PIN = 27; + |A0 : INPUT_PIN = 26; + |MD13 : BIDIR_PIN = 189; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EP1K100FC484-1; + AUTO_DEVICE = EP1K100FC256-1; + AUTO_DEVICE = EP1K100QC208-1; + AUTO_DEVICE = EP1K50FC484-1; + AUTO_DEVICE = EP1K50FC256-1; + AUTO_DEVICE = EP1K50QC208-1; + AUTO_DEVICE = EP1K50TC144-1; + AUTO_DEVICE = EP1K30FC256-1; + AUTO_DEVICE = EP1K30QC208-1; + AUTO_DEVICE = EP1K30TC144-1; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EP1K30QC208-3; + FREQUENCY = 100MHz; + MAINTAIN_STABLE_SYNTHESIS = OFF; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; +END; + +IGNORED_ASSIGNMENTS +BEGIN + FIT_IGNORE_TIMING = OFF; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +LOGIC_OPTIONS +BEGIN + |/wait : SLOW_SLEW_RATE = ON; + |wr_dwg : SLOW_SLEW_RATE = ON; + |wr_dwg : INCREASE_INPUT_DELAY = ON; + |wr_dwg : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |RDXA : FAST_IO = ON; + |SXA : FAST_IO = ON; + |VD00 : INCREASE_INPUT_DELAY = ON; + |VD01 : INCREASE_INPUT_DELAY = ON; + |VD02 : INCREASE_INPUT_DELAY = ON; + |VD03 : INCREASE_INPUT_DELAY = ON; + |VD04 : INCREASE_INPUT_DELAY = ON; + |VD05 : INCREASE_INPUT_DELAY = ON; + |VD06 : INCREASE_INPUT_DELAY = ON; + |VD07 : INCREASE_INPUT_DELAY = ON; + |VD10 : INCREASE_INPUT_DELAY = ON; + |VD11 : INCREASE_INPUT_DELAY = ON; + |VD12 : INCREASE_INPUT_DELAY = ON; + |VD13 : INCREASE_INPUT_DELAY = ON; + |VD14 : INCREASE_INPUT_DELAY = ON; + |VD15 : INCREASE_INPUT_DELAY = ON; + |VD16 : INCREASE_INPUT_DELAY = ON; + |VD17 : INCREASE_INPUT_DELAY = ON; + |VD20 : INCREASE_INPUT_DELAY = ON; + |VD21 : INCREASE_INPUT_DELAY = ON; + |VD22 : INCREASE_INPUT_DELAY = ON; + |VD23 : INCREASE_INPUT_DELAY = ON; + |VD24 : INCREASE_INPUT_DELAY = ON; + |VD25 : INCREASE_INPUT_DELAY = ON; + |VD26 : INCREASE_INPUT_DELAY = ON; + |VD27 : INCREASE_INPUT_DELAY = ON; + |VD30 : INCREASE_INPUT_DELAY = ON; + |VD31 : INCREASE_INPUT_DELAY = ON; + |VD32 : INCREASE_INPUT_DELAY = ON; + |VD33 : INCREASE_INPUT_DELAY = ON; + |VD34 : INCREASE_INPUT_DELAY = ON; + |VD35 : INCREASE_INPUT_DELAY = ON; + |VD36 : INCREASE_INPUT_DELAY = ON; + |VD37 : INCREASE_INPUT_DELAY = ON; + |RAS_0 : INCREASE_INPUT_DELAY = ON; + |RAS_1 : INCREASE_INPUT_DELAY = ON; + |CAS_0 : INCREASE_INPUT_DELAY = ON; + |CAS_0 : SLOW_SLEW_RATE = ON; + |CAS_1 : INCREASE_INPUT_DELAY = ON; + |CAS_1 : SLOW_SLEW_RATE = ON; + |CAS_2 : INCREASE_INPUT_DELAY = ON; + |CAS_2 : SLOW_SLEW_RATE = ON; + |CAS_3 : INCREASE_INPUT_DELAY = ON; + |CAS_3 : SLOW_SLEW_RATE = ON; + |RAS_0 : SLOW_SLEW_RATE = ON; + |RAS_1 : SLOW_SLEW_RATE = ON; + |XACS : INCREASE_INPUT_DELAY = ON; + |/wr : INCREASE_INPUT_DELAY = ON; + |/WE : INCREASE_INPUT_DELAY = ON; + |/wait : INCREASE_INPUT_DELAY = ON; + |VA0 : INCREASE_INPUT_DELAY = ON; + |VA1 : INCREASE_INPUT_DELAY = ON; + |VA2 : INCREASE_INPUT_DELAY = ON; + |VA3 : INCREASE_INPUT_DELAY = ON; + |VA4 : INCREASE_INPUT_DELAY = ON; + |VA5 : INCREASE_INPUT_DELAY = ON; + |VA6 : INCREASE_INPUT_DELAY = ON; + |VA7 : INCREASE_INPUT_DELAY = ON; + |VA8 : INCREASE_INPUT_DELAY = ON; + |VA9 : INCREASE_INPUT_DELAY = ON; + |VA10 : INCREASE_INPUT_DELAY = ON; + |VA11 : INCREASE_INPUT_DELAY = ON; + |VA12 : INCREASE_INPUT_DELAY = ON; + |VA13 : INCREASE_INPUT_DELAY = ON; + |VA14 : INCREASE_INPUT_DELAY = ON; + |VA15 : INCREASE_INPUT_DELAY = ON; + |/rf : INCREASE_INPUT_DELAY = ON; + |/reset : INCREASE_INPUT_DELAY = ON; + |/rd : INCREASE_INPUT_DELAY = ON; + |ra14 : INCREASE_INPUT_DELAY = ON; + |ra14 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ra15 : INCREASE_INPUT_DELAY = ON; + |ra15 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ra16 : INCREASE_INPUT_DELAY = ON; + |ra16 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ra17 : INCREASE_INPUT_DELAY = ON; + |ra17 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |/mr : INCREASE_INPUT_DELAY = ON; + |/m1 : INCREASE_INPUT_DELAY = ON; + |ma12 : INCREASE_INPUT_DELAY = ON; + |ma13 : INCREASE_INPUT_DELAY = ON; + |ma14 : INCREASE_INPUT_DELAY = ON; + |ma0 : INCREASE_INPUT_DELAY = ON; + |ma1 : INCREASE_INPUT_DELAY = ON; + |ma2 : INCREASE_INPUT_DELAY = ON; + |ma3 : INCREASE_INPUT_DELAY = ON; + |ma4 : INCREASE_INPUT_DELAY = ON; + |ma5 : INCREASE_INPUT_DELAY = ON; + |ma6 : INCREASE_INPUT_DELAY = ON; + |ma7 : INCREASE_INPUT_DELAY = ON; + |ma8 : INCREASE_INPUT_DELAY = ON; + |ma9 : INCREASE_INPUT_DELAY = ON; + |ma10 : INCREASE_INPUT_DELAY = ON; + |ma11 : INCREASE_INPUT_DELAY = ON; + |/io : INCREASE_INPUT_DELAY = ON; + |/HALT : INCREASE_INPUT_DELAY = ON; + |d0 : INCREASE_INPUT_DELAY = ON; + |d1 : INCREASE_INPUT_DELAY = ON; + |d2 : INCREASE_INPUT_DELAY = ON; + |d3 : INCREASE_INPUT_DELAY = ON; + |d4 : INCREASE_INPUT_DELAY = ON; + |d5 : INCREASE_INPUT_DELAY = ON; + |d6 : INCREASE_INPUT_DELAY = ON; + |d7 : INCREASE_INPUT_DELAY = ON; + |CS_CASH : PCI_IO = OFF; + |CS_CASH : INCREASE_INPUT_DELAY = ON; + |CS_CASH : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |cs_rom : PCI_IO = OFF; + |cs_rom : INCREASE_INPUT_DELAY = ON; + |cs_rom : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |a0 : INCREASE_INPUT_DELAY = ON; + |a1 : INCREASE_INPUT_DELAY = ON; + |a2 : INCREASE_INPUT_DELAY = ON; + |a3 : INCREASE_INPUT_DELAY = ON; + |a4 : INCREASE_INPUT_DELAY = ON; + |a5 : INCREASE_INPUT_DELAY = ON; + |a6 : INCREASE_INPUT_DELAY = ON; + |a7 : INCREASE_INPUT_DELAY = ON; + |A8 : INCREASE_INPUT_DELAY = ON; + |a9 : INCREASE_INPUT_DELAY = ON; + |A10 : INCREASE_INPUT_DELAY = ON; + |a11 : INCREASE_INPUT_DELAY = ON; + |A12 : INCREASE_INPUT_DELAY = ON; + |A13 : INCREASE_INPUT_DELAY = ON; + |A14 : INCREASE_INPUT_DELAY = ON; + |A15 : INCREASE_INPUT_DELAY = ON; + |md0 : INCREASE_INPUT_DELAY = ON; + |md1 : INCREASE_INPUT_DELAY = ON; + |md2 : INCREASE_INPUT_DELAY = ON; + |md3 : INCREASE_INPUT_DELAY = ON; + |md4 : INCREASE_INPUT_DELAY = ON; + |md5 : INCREASE_INPUT_DELAY = ON; + |md6 : INCREASE_INPUT_DELAY = ON; + |md7 : INCREASE_INPUT_DELAY = ON; + |md8 : INCREASE_INPUT_DELAY = ON; + |md9 : INCREASE_INPUT_DELAY = ON; + |md10 : INCREASE_INPUT_DELAY = ON; + |md11 : INCREASE_INPUT_DELAY = ON; + |md12 : INCREASE_INPUT_DELAY = ON; + |md13 : INCREASE_INPUT_DELAY = ON; + |md14 : INCREASE_INPUT_DELAY = ON; + |md15 : INCREASE_INPUT_DELAY = ON; + |wr_awg : SLOW_SLEW_RATE = OFF; + |XA0 : INCREASE_INPUT_DELAY = ON; + |XA1 : INCREASE_INPUT_DELAY = ON; + |XA2 : INCREASE_INPUT_DELAY = ON; + |XA3 : INCREASE_INPUT_DELAY = ON; + |ma0 : SLOW_SLEW_RATE = ON; + |ma1 : SLOW_SLEW_RATE = ON; + |ma2 : SLOW_SLEW_RATE = ON; + |ma3 : SLOW_SLEW_RATE = ON; + |ma4 : SLOW_SLEW_RATE = ON; + |ma5 : SLOW_SLEW_RATE = ON; + |ma6 : SLOW_SLEW_RATE = ON; + |ma7 : SLOW_SLEW_RATE = ON; + |ma8 : SLOW_SLEW_RATE = ON; + |ma9 : SLOW_SLEW_RATE = ON; + |ma10 : SLOW_SLEW_RATE = ON; + |ma11 : SLOW_SLEW_RATE = ON; + |VD00 : SLOW_SLEW_RATE = OFF; + |VD01 : SLOW_SLEW_RATE = OFF; + |VD02 : SLOW_SLEW_RATE = OFF; + |VD03 : SLOW_SLEW_RATE = OFF; + |VD04 : SLOW_SLEW_RATE = OFF; + |VD05 : SLOW_SLEW_RATE = OFF; + |VD06 : SLOW_SLEW_RATE = OFF; + |VD07 : SLOW_SLEW_RATE = OFF; + |VD10 : SLOW_SLEW_RATE = OFF; + |VD11 : SLOW_SLEW_RATE = OFF; + |VD12 : SLOW_SLEW_RATE = OFF; + |VD13 : SLOW_SLEW_RATE = OFF; + |VD14 : SLOW_SLEW_RATE = OFF; + |VD15 : SLOW_SLEW_RATE = OFF; + |VD16 : SLOW_SLEW_RATE = OFF; + |VD17 : SLOW_SLEW_RATE = OFF; + |VD20 : SLOW_SLEW_RATE = OFF; + |VD21 : SLOW_SLEW_RATE = OFF; + |VD22 : SLOW_SLEW_RATE = OFF; + |VD23 : SLOW_SLEW_RATE = OFF; + |VD24 : SLOW_SLEW_RATE = OFF; + |VD25 : SLOW_SLEW_RATE = OFF; + |VD26 : SLOW_SLEW_RATE = OFF; + |VD27 : SLOW_SLEW_RATE = OFF; + |VD30 : SLOW_SLEW_RATE = OFF; + |VD31 : SLOW_SLEW_RATE = OFF; + |VD32 : SLOW_SLEW_RATE = OFF; + |VD33 : SLOW_SLEW_RATE = OFF; + |VD34 : SLOW_SLEW_RATE = OFF; + |VD35 : SLOW_SLEW_RATE = OFF; + |VD36 : SLOW_SLEW_RATE = OFF; + |VD37 : SLOW_SLEW_RATE = OFF; + |VA0 : PCI_IO = OFF; + |VA1 : PCI_IO = OFF; + |VA2 : PCI_IO = OFF; + |VA3 : PCI_IO = OFF; + |VA4 : PCI_IO = OFF; + |VA6 : PCI_IO = OFF; + |VA5 : PCI_IO = OFF; + |VA7 : PCI_IO = OFF; + |VA8 : PCI_IO = OFF; + |VA9 : PCI_IO = OFF; + |VA10 : PCI_IO = OFF; + |VA11 : PCI_IO = OFF; + |VA12 : PCI_IO = OFF; + |VA13 : PCI_IO = OFF; + |VA14 : PCI_IO = OFF; + |VA15 : PCI_IO = OFF; + |VD00 : PCI_IO = OFF; + |VD01 : PCI_IO = OFF; + |VD02 : PCI_IO = OFF; + |VD03 : PCI_IO = OFF; + |VD04 : PCI_IO = OFF; + |VD05 : PCI_IO = OFF; + |VD06 : PCI_IO = OFF; + |VD07 : PCI_IO = OFF; + |VD10 : PCI_IO = OFF; + |VD11 : PCI_IO = OFF; + |VD12 : PCI_IO = OFF; + |VD13 : PCI_IO = OFF; + |VD14 : PCI_IO = OFF; + |VD15 : PCI_IO = OFF; + |VD16 : PCI_IO = OFF; + |VD17 : PCI_IO = OFF; + |VD20 : PCI_IO = OFF; + |VD21 : PCI_IO = OFF; + |VD22 : PCI_IO = OFF; + |VD23 : PCI_IO = OFF; + |VD24 : PCI_IO = OFF; + |VD25 : PCI_IO = OFF; + |VD26 : PCI_IO = OFF; + |VD27 : PCI_IO = OFF; + |VD30 : PCI_IO = OFF; + |VD31 : PCI_IO = OFF; + |VD32 : PCI_IO = OFF; + |VD33 : PCI_IO = OFF; + |VD34 : PCI_IO = OFF; + |VD35 : PCI_IO = OFF; + |VD36 : PCI_IO = OFF; + |VD37 : PCI_IO = OFF; + |WR_COL : SLOW_SLEW_RATE = ON; + |VA0 : SLOW_SLEW_RATE = ON; + |VA1 : SLOW_SLEW_RATE = ON; + |VA2 : SLOW_SLEW_RATE = ON; + |VA3 : SLOW_SLEW_RATE = ON; + |VA4 : SLOW_SLEW_RATE = ON; + |VA5 : SLOW_SLEW_RATE = ON; + |VA6 : SLOW_SLEW_RATE = ON; + |VA7 : SLOW_SLEW_RATE = ON; + |VA8 : SLOW_SLEW_RATE = ON; + |VA9 : SLOW_SLEW_RATE = ON; + |VA10 : SLOW_SLEW_RATE = ON; + |VA11 : SLOW_SLEW_RATE = ON; + |VA12 : SLOW_SLEW_RATE = ON; + |VA13 : SLOW_SLEW_RATE = ON; + |VA14 : SLOW_SLEW_RATE = ON; + |VA15 : SLOW_SLEW_RATE = ON; + |V_WR0 : SLOW_SLEW_RATE = OFF; + |V_WR1 : SLOW_SLEW_RATE = OFF; + |V_WR2 : SLOW_SLEW_RATE = OFF; + |V_WR3 : SLOW_SLEW_RATE = OFF; + |XA0 : SLOW_SLEW_RATE = ON; + |XA1 : SLOW_SLEW_RATE = ON; + |XA2 : SLOW_SLEW_RATE = ON; + |XA3 : SLOW_SLEW_RATE = ON; + |XACS : SLOW_SLEW_RATE = ON; + |/wait : PCI_IO = OFF; + |SXA : SLOW_SLEW_RATE = ON; + |/rf : PCI_IO = OFF; + |/reset : PCI_IO = OFF; + |RDXA : SLOW_SLEW_RATE = ON; + |/rd : PCI_IO = OFF; + |/m1 : PCI_IO = OFF; + |/mr : PCI_IO = OFF; + |/io : PCI_IO = OFF; + |/HALT : PCI_IO = OFF; + |/WE : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |/WE : SLOW_SLEW_RATE = ON; + |RAS_0 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |RAS_1 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |CAS_0 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |CAS_1 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |CAS_2 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |CAS_3 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma0 : PCI_IO = OFF; + |ma1 : FAST_IO = ON; + |ma2 : FAST_IO = ON; + |ma3 : FAST_IO = ON; + |ma4 : FAST_IO = ON; + |ma5 : FAST_IO = ON; + |ma6 : FAST_IO = ON; + |ma7 : FAST_IO = ON; + |ma8 : FAST_IO = ON; + |ma9 : FAST_IO = ON; + |ma10 : FAST_IO = ON; + |ma11 : FAST_IO = ON; + |ma1 : PCI_IO = OFF; + |ma2 : PCI_IO = OFF; + |ma3 : PCI_IO = OFF; + |ma4 : PCI_IO = OFF; + |ma5 : PCI_IO = OFF; + |ma6 : PCI_IO = OFF; + |ma7 : PCI_IO = OFF; + |ma8 : PCI_IO = OFF; + |ma9 : PCI_IO = OFF; + |ma10 : PCI_IO = OFF; + |ma11 : PCI_IO = OFF; + |ma12 : PCI_IO = OFF; + |ma12 : SLOW_SLEW_RATE = ON; + |ma13 : PCI_IO = OFF; + |ma13 : SLOW_SLEW_RATE = ON; + |ma14 : PCI_IO = OFF; + |ma14 : SLOW_SLEW_RATE = ON; + |SXA : PCI_IO = OFF; + |RDXA : PCI_IO = OFF; + |RDXA : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |/mr : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |/m1 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |/rd : SLOW_SLEW_RATE = ON; + |wr_awg : PCI_IO = OFF; + |wr_awg : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ra14 : PCI_IO = OFF; + |ra14 : SLOW_SLEW_RATE = ON; + |ra15 : PCI_IO = OFF; + |ra15 : SLOW_SLEW_RATE = ON; + |ra16 : PCI_IO = OFF; + |ra16 : SLOW_SLEW_RATE = ON; + |ra17 : PCI_IO = OFF; + |ra17 : SLOW_SLEW_RATE = ON; + |CS_CASH : SLOW_SLEW_RATE = ON; + |cs_rom : SLOW_SLEW_RATE = ON; + |/WE : PCI_IO = OFF; + |RAS_0 : PCI_IO = OFF; + |RAS_1 : PCI_IO = OFF; + |CAS_0 : PCI_IO = OFF; + |CAS_1 : PCI_IO = OFF; + |CAS_2 : PCI_IO = OFF; + |CAS_3 : PCI_IO = OFF; + |V_WR0 : PCI_IO = OFF; + |V_WR1 : PCI_IO = OFF; + |V_WR2 : PCI_IO = OFF; + |V_WR3 : PCI_IO = OFF; + |v_cs0 : PCI_IO = OFF; + |v_cs1 : PCI_IO = OFF; + |XACS : PCI_IO = OFF; + |/wr : PCI_IO = OFF; + |XA0 : PCI_IO = OFF; + |XA1 : PCI_IO = OFF; + |XA2 : PCI_IO = OFF; + |XA3 : PCI_IO = OFF; + |TG42 : PCI_IO = OFF; + |d0 : PCI_IO = OFF; + |d1 : PCI_IO = OFF; + |d2 : PCI_IO = OFF; + |d3 : PCI_IO = OFF; + |d4 : PCI_IO = OFF; + |d5 : PCI_IO = OFF; + |d6 : PCI_IO = OFF; + |d7 : PCI_IO = OFF; + |md0 : PCI_IO = OFF; + |md1 : PCI_IO = OFF; + |md2 : PCI_IO = OFF; + |md3 : PCI_IO = OFF; + |md4 : PCI_IO = OFF; + |md5 : PCI_IO = OFF; + |md6 : PCI_IO = OFF; + |md7 : PCI_IO = OFF; + |md8 : PCI_IO = OFF; + |md9 : PCI_IO = OFF; + |md10 : PCI_IO = OFF; + |md11 : PCI_IO = OFF; + |md12 : PCI_IO = OFF; + |md13 : PCI_IO = OFF; + |md14 : PCI_IO = OFF; + |md15 : PCI_IO = OFF; + |a0 : PCI_IO = OFF; + |a1 : PCI_IO = OFF; + |a2 : PCI_IO = OFF; + |a3 : PCI_IO = OFF; + |a4 : PCI_IO = OFF; + |a5 : PCI_IO = OFF; + |a6 : PCI_IO = OFF; + |A8 : PCI_IO = OFF; + |a7 : PCI_IO = OFF; + |A10 : PCI_IO = OFF; + |a9 : PCI_IO = OFF; + |a11 : PCI_IO = OFF; + |A12 : PCI_IO = OFF; + |A13 : PCI_IO = OFF; + |A14 : PCI_IO = OFF; + |A15 : PCI_IO = OFF; + |/reset : SLOW_SLEW_RATE = ON; + |/rf : SLOW_SLEW_RATE = ON; + |a0 : SLOW_SLEW_RATE = ON; + |a1 : SLOW_SLEW_RATE = ON; + |a2 : SLOW_SLEW_RATE = ON; + |a3 : SLOW_SLEW_RATE = ON; + |a4 : SLOW_SLEW_RATE = ON; + |a5 : SLOW_SLEW_RATE = ON; + |a6 : SLOW_SLEW_RATE = ON; + |a7 : SLOW_SLEW_RATE = ON; + |a8 : SLOW_SLEW_RATE = ON; + |a9 : SLOW_SLEW_RATE = ON; + |a10 : SLOW_SLEW_RATE = ON; + |a11 : SLOW_SLEW_RATE = ON; + |A12 : SLOW_SLEW_RATE = ON; + |A13 : SLOW_SLEW_RATE = ON; + |A14 : SLOW_SLEW_RATE = ON; + |A15 : SLOW_SLEW_RATE = ON; + |/mr : SLOW_SLEW_RATE = ON; + |/m1 : SLOW_SLEW_RATE = ON; + |/HALT : SLOW_SLEW_RATE = ON; + |/io : SLOW_SLEW_RATE = ON; + |d0 : SLOW_SLEW_RATE = ON; + |d1 : SLOW_SLEW_RATE = ON; + |d2 : SLOW_SLEW_RATE = ON; + |d3 : SLOW_SLEW_RATE = ON; + |d4 : SLOW_SLEW_RATE = ON; + |d5 : SLOW_SLEW_RATE = ON; + |d6 : SLOW_SLEW_RATE = ON; + |d7 : SLOW_SLEW_RATE = ON; + |DAC_BCK : SLOW_SLEW_RATE = ON; + |DAC_DATA : SLOW_SLEW_RATE = ON; + |DAC_WS : SLOW_SLEW_RATE = ON; + |WR_COL : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |WR_COL : FAST_IO = ON; + |v_cs0 : SLOW_SLEW_RATE = ON; + |v_cs1 : SLOW_SLEW_RATE = ON; + |ma0 : FAST_IO = ON; + |ma0 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma1 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma2 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma3 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma4 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma5 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma6 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma7 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma8 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma9 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma10 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma11 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma12 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma13 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |ma14 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md0 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md0 : SLOW_SLEW_RATE = ON; + |md1 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md1 : SLOW_SLEW_RATE = ON; + |md2 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md2 : SLOW_SLEW_RATE = ON; + |md3 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md3 : SLOW_SLEW_RATE = ON; + |md4 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md4 : SLOW_SLEW_RATE = ON; + |md5 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md5 : SLOW_SLEW_RATE = ON; + |md6 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md6 : SLOW_SLEW_RATE = ON; + |md7 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md7 : SLOW_SLEW_RATE = ON; + |md8 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md8 : SLOW_SLEW_RATE = ON; + |md9 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md9 : SLOW_SLEW_RATE = ON; + |md10 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md10 : SLOW_SLEW_RATE = ON; + |md11 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md11 : SLOW_SLEW_RATE = ON; + |md12 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md12 : SLOW_SLEW_RATE = ON; + |md13 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md13 : SLOW_SLEW_RATE = ON; + |md14 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md14 : SLOW_SLEW_RATE = ON; + |md15 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |md15 : SLOW_SLEW_RATE = ON; + "|video2:SVIDEO|SVA12" : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + "|video2:SVIDEO|SVA11" : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + "|video2:SVIDEO|SVA10" : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + "|video2:SVIDEO|SVA0" : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + "|video2:SVIDEO|SVA1" : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + "|video2:SVIDEO|SVA2" : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + "|video2:SVIDEO|SVA3" : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + "|video2:SVIDEO|SVA4" : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + "|video2:SVIDEO|SVA5" : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |v_cs0 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |v_cs1 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD00 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD01 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD02 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD03 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD04 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD05 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD06 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD07 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD10 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD11 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD12 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD13 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD14 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD15 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD16 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD17 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD20 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD21 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD22 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD23 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD24 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD25 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD26 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD27 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD30 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD31 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD32 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD33 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD34 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD35 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD36 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VD37 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |CLKZ1 : SLOW_SLEW_RATE = OFF; + "|video2:SVIDEO|D_PIC00" : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + "|video2:SVIDEO|D_PIC01" : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + "|video2:SVIDEO|D_PIC02" : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + "|video2:SVIDEO|D_PIC03" : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + "|video2:SVIDEO|D_PIC04" : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + "|video2:SVIDEO|D_PIC05" : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + "|video2:SVIDEO|D_PIC06" : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + "|video2:SVIDEO|D_PIC07" : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA0 : FAST_IO = ON; + |VA1 : FAST_IO = ON; + |VA2 : FAST_IO = ON; + |VA3 : FAST_IO = ON; + |VA4 : FAST_IO = ON; + |VA5 : FAST_IO = ON; + |VA6 : FAST_IO = ON; + |VA7 : FAST_IO = ON; + |VA8 : FAST_IO = ON; + |VA9 : FAST_IO = ON; + |VA10 : FAST_IO = ON; + |VA11 : FAST_IO = ON; + |VA12 : FAST_IO = ON; + |VA13 : FAST_IO = ON; + |VA14 : FAST_IO = ON; + |VA15 : FAST_IO = ON; + |V_WR0 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |V_WR1 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |V_WR2 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |V_WR3 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA0 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA1 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA2 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA3 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA4 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA5 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA6 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA7 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA8 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA9 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA10 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA11 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA12 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA13 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA14 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; + |VA15 : INSERT_ADDITIONAL_LOGIC_CELL = OFF; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + MULTIVOLT_IO = ON; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + RELEASE_CLEARS = ON; + AUTO_RESTART = ON; + MAX7000B_ENABLE_VREFB = OFF; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + FLEX_CONFIGURATION_EPROM = AUTO; + MAX7000AE_ENABLE_JTAG = ON; + MAX7000AE_USER_CODE = FFFFFFFF; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + MAX7000S_ENABLE_JTAG = ON; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_USER_CODE = FFFF; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + nCEO = UNRESERVED; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + DATA0 = RESERVED_TRI_STATED; + FLEX8000_ENABLE_JTAG = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + DISABLE_TIME_OUT = OFF; + ENABLE_DCLK_OUTPUT = OFF; + USER_CLOCK = OFF; + SECURITY_BIT = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + STYLE = FAST; + OPTIMIZE_FOR_SPEED = 5; + DEVICE_FAMILY = ACEX1K; + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_REGISTER_PACKING = OFF; + AUTO_FAST_IO = OFF; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_PRESET = ON; + AUTO_GLOBAL_CLEAR = ON; + AUTO_GLOBAL_CLOCK = ON; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + SMART_RECOMPILE = OFF; + FITTER_SETTINGS = CUSTOM; + USE_QUARTUS_FITTER = OFF; + DESIGN_DOCTOR_RULES = CUSTOM; + RPT_FILE_LCELL_INTERCONNECT = OFF; + RPT_FILE_HIERARCHY = OFF; + DESIGN_DOCTOR = OFF; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; + GENERATE_AHDL_TDO_FILE = OFF; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + TIMING_SNF_EXTRACTOR = ON; + FUNCTIONAL_SNF_EXTRACTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VHDL_WRITER_VERSION = VHDL87; + VHDL_READER_VERSION = VHDL87; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + EXPANDER_NETWORKS = OFF; + ASYNCHRONOUS_INPUTS = OFF; + PRESET_CLEAR_NETWORKS = OFF; + MULTI_CLOCK_NETWORKS = OFF; + MASTER_RESET = OFF; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + END_TIME = 12.0us; + BIDIR_PIN = STRONG; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + ANALYSIS_MODE = REGISTERED_PERFORMANCE; + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; + LIST_PATH_FREQUENCY = 10MHz; + LIST_PATH_COUNT = 10; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; +END; + +OTHER_CONFIGURATION +BEGIN + LAST_MAXPLUS2_VERSION = 10.0; + CARRY_OUT_PINS_LCELL_INSERT = ON; + ROW_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + EXPLICIT_FAMILY = 1; + FLEX_10K_52_COLUMNS = 40; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ROW_PINS_PERCENT = 50; + ORIGINAL_MAXPLUS2_VERSION = 9.6; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + CARRY_CHAIN = AUTO; + CASCADE_CHAIN = AUTO; + SLOW_SLEW_RATE = ON; + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CASCADE_CHAIN_LENGTH = 2; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = ON; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + USE_LPM_FOR_AHDL_OPERATORS = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + IGNORE_SOFT_BUFFERS = ON; + REGISTER_OPTIMIZATION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SLOW_SLEW_RATE = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + NOT_GATE_PUSH_BACK = ON; + SOFT_BUFFER_INSERTION = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = AUTO; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/src/altera/quartus/acex/SP2_ACEX.TDF b/src/altera/quartus/acex/SP2_ACEX.TDF new file mode 100644 index 0000000..dfa3d6e --- /dev/null +++ b/src/altera/quartus/acex/SP2_ACEX.TDF @@ -0,0 +1,1227 @@ + + TITLE "Main"; + +PARAMETERS + ( + UPDATE = 1, -- 1 for UPDATE sheet + MODE = "SPRINTER", -- or MODE = "SPECTRUM" + NMI_ON = "OFF", -- "ON" - for use NMI + SCREEN_OFF = "NOT_USE" -- "USE" - for use screen on/off + ); + +INCLUDE "lpm_ram_dp"; +INCLUDE "kbd"; +--INCLUDE "video"; +INCLUDE "video2"; + +INCLUDE "dcp"; +--INCLUDE "dcp2"; + +INCLUDE "acceler"; +INCLUDE "ay"; +INCLUDE "mouse"; + +SUBDESIGN SP2_ACEX + ( + TG42 : INPUT; + CLKZ1 : OUTPUT; + + /WAIT : BIDIR; + /RESET : BIDIR; + /M1 : INPUT; + /RF : INPUT; + /IO : INPUT; + /WR : INPUT; + /RD : INPUT; + /HALT : INPUT; + /MR : INPUT; + A[15..0] : INPUT; + D[7..0] : BIDIR; + + CS_ROM : OUTPUT; + CS_CASH : OUTPUT; + RA[17..14] : OUTPUT; + + V_CS[1..0] : OUTPUT; + VA[15..0] : OUTPUT; + V_WR[3..0] : OUTPUT; + VD3[7..0] : BIDIR; + VD2[7..0] : BIDIR; + VD1[7..0] : BIDIR; + VD0[7..0] : BIDIR; + + WR_COL : OUTPUT; + + DAC_DATA : OUTPUT; + DAC_WS : OUTPUT; + DAC_BCK : OUTPUT; + + MD[15..0] : BIDIR; + MA[14..0] : OUTPUT; + RAS_[1..0] : OUTPUT; + CAS_[3..0] : OUTPUT; + /WE : OUTPUT; + + XACS : OUTPUT; -- ROM_WE + XA[3..0] : BIDIR; + SXA : OUTPUT; + + RDXA : OUTPUT; + WR_AWG : OUTPUT; + RD_KMPS : OUTPUT; + WR_DWG : OUTPUT; + + + + ) +VARIABLE + + MS : MOUSE; + KEYS : KBD; + SVIDEO : VIDEO2 WITH (MODE=MODE); + + DECODE : DCP WITH (UPDATE=UPDATE); +-- DECODE : DCP2; + + ACC : ACCELER; + AY3 : AY; + + CBL : lpm_ram_dp WITH (lpm_width=16,lpm_widthad=8); + + CT[5..0] : NODE; + CTH[5..0] : NODE; + CTV[8..0] : NODE; + CTF[6..0] : NODE; + + CLK42 : NODE; + + DD[7..0] : NODE; + D_OUT : NODE; + RD_RAM : NODE; + + MCA[1..0] : NODE; + + DVD3[7..0] : NODE; + DVD2[7..0] : NODE; + DVD1[7..0] : NODE; + DVD0[7..0] : NODE; + + DMD[15..0] : NODE; + DMDX[7..0] : NODE; + + COPY_SINC_H : NODE; + COPY_SINC_V : NODE; + + START_UP : NODE; + + BLANK : NODE; + +-- WGA[1..0] : NODE; -- to MA[1..0] / WR_AWG^ +-- FDD_C[2..0] : NODE; -- to MA[4..2] / WR_AWG^ +-- HDD_C[3..0] : NODE; -- to MA[8..5] / WR_AWG^ +-- HD_A[2..0] : NODE; -- to MA[11..9] / WR_AWG^ + NMI_X : NODE; -- to MA12 / WR_AWG^ + INT_X : NODE; -- to MA13 / WR_AWG^ + TURBO : NODE; -- to MA14 / WR_AWG^ + KBD_CX : NODE; -- to XA0 / WR_AWG^ + KBD_DX : NODE; -- to XA1 / WR_AWG^ + TAPE_OUT : NODE; -- to XA2 / WR_AWG^ + + KBD_CC : NODE; -- from XA0 / SXA=0 / RD_XA=0 + KBD_DD : NODE; -- from XA1 / SXA=0 / RD_XA=0 + TAPE_IN : NODE; -- from XA2 / SXA=0 / RD_XA=0 + MOUSE_D : NODE; -- from XA3 / SXA=0 / RD_XA=0 + + FDD_CH : NODE; -- from XA0 / SXA=1 / RD_XA=0 + FDD_W : NODE; -- from XA1 / SXA=1 / RD_XA=0 + SINC_1 : NODE; -- from XA2 / SXA=1 / RD_XA=0 + SINC_2 : NODE; -- from XA3 / SXA=1 / RD_XA=0 + SINC_1M : NODE; + SINC_2M : NODE; + + WR_TM9 : NODE; + +-- ==================== + TEST_SWITCH : NODE; + + T_SIGNAL : NODE; +-- TEST_1 : LCELL; +-- KTA[7..0] : LCELL; +-- KTD[7..0] : DFF; +-- KTT : LCELL; + + K_DATA[10..0] : NODE; + KEY_D[10..0] : DFF; + KEY_WRITE : NODE; + KD[7..0] : DFF; + K_XOR : NODE; + NEXT_K : NODE; + + RED[7..0] : NODE; + GREEN[7..0] : NODE; + BLUE[7..0] : NODE; + + BORDER[7..0] : DFFE; + KBD_BLK : NODE; + + DOS : NODE; + DOS_ : NODE; + + MDR[7..0] : NODE; + DCPP[7..0] : NODE; + + MDP[7..0] : DFFE; +-- MDP[7..0] : LCELL; + + PDD[7..0] : LCELL; + WR_PORT : NODE; + + RGMOD[7..0] : DFFE; + + HDDR[7..0] : DFFE; + + GLISSER : NODE; + BLK_MR : NODE; + VIDEO_PG : NODE; + + AUDIO_CH : NODE; + + CBL_MODE : NODE; + CBL_STEREO : NODE; + CBL_MODE16 : NODE; + CBL_INT_ENA : NODE; + CBL_INT : NODE; + CBL_WR : NODE; + CBL_XX[7..0] : DFFE; + CBL_CNT[7..0] : DFF; + CBL_CTX[4..0] : DFFE; + CBL_WA[7..0] : DFFE; + CBL_WAE : NODE; + CBL_IND : NODE; + + CBL_TAB[4..0] : LCELL; + + CBL_R[15..0] : DFFE; + CBD[7..0] : DFFE; + + AUDIO_R[15..0] : DFFE; + + + /WAIT_ALL : NODE; + + BLK_MEM : NODE; + + SYS_ENA : NODE; + SYS_ENA2 : NODE; + + /SYS : NODE; + SYS_PG : NODE; + + CS_ISA : NODE; + + ISA_CASH : NODE; + ISA_A[3..0] : NODE; + + PRE_ISA : NODE; + PRE_ROM : NODE; + PRE_CASH : NODE; + + WAIT_ORIG : NODE; + WAIT_ROM : NODE; + WAIT_ROMX : NODE; + WT_R[2..0] : DFF; + +-- BLK_WAIT : NODE; + + ISA_A20 : NODE; + CASH_ON : NODE; + BLK_MWR2 : NODE; + + ROM_RG[7..0]: DFFE; + ROM_WRITE_MODE : NODE; + + AY_CHS[15..0] : DFFE; + + SOFT_RESET : NODE; + SOFT_RES[1..0] : DFF; + + AY_FULL[10..0] : DFF; + + ALL_MODE[7..0] : DFFE; + + DOUBLE_CAS : NODE; + + XACS : DFF; + + KEMPS[7..0] : LCELL; + + KEY/KEMS[7..0] : LCELL; + AY/PORTS[7..0] : LCELL; + + V_WRXX[3..0]: LCELL; + V_WRX[3..0] : LCELL; +-- V_WRX[3..0] : NODE; + + KEY_IO : NODE; + + /IOWR : NODE; + /IORD : NODE; + + RASX_[1..0] : NODE; + CASX_[3..0] : NODE; + CASXE[1..0] : NODE; + CAS_A : NODE; + +-- ISA_CELL[1..0] : LCELL; + + T_RDXA : NODE; + + /WE_OUT : NODE; + + SINC_HOLD[8..0] : DFF; + + HOLD[7..0] : DFFE; + + CS_ROMT : NODE; + CS_CASHT : NODE; + + ISA_PORT[7..0] : DFFE; + +BEGIN + + CLK42 = TG42; + +-- /RESET = TRI(GND,!DFF((KEYS.kb_reset & START_UP & SOFT_RESET),CLK42,,)); + -- start_up from SOFT_RESET + /RESET = TRI(GND,!DFF((KEYS.kb_reset & SOFT_RESET),CLK42,,)); + +-- SOFT_RES[].prn = DFF((!DECODE.BLK_R or /WR or !(DECODE.PAGE[7..0] == H"A0")),CLK42,,); + + SOFT_RES[].clk = !CT4; + CASE SOFT_RES[] IS + WHEN 0,1 => SOFT_RES[] = GND; + WHEN 2 => SOFT_RES[] = 1; + WHEN 3 => SOFT_RES[] = 2; + END CASE; + SOFT_RESET = (SOFT_RES[] == 0); -- when no_Z - RESET! + +-- ===== Spectrum-Ports =================== + + /IOWR = DFF((/WR or /IO),CLK42,,!/IO); + /IORD = DFF((/RD or /IO),CLK42,,!/IO); + + BORDER[].clk = /IOWR; + BORDER[].ena = DFF((DCPP[] == B"1100X010"),CLK42,,); -- C2/C8 + BORDER[].d = D[]; + +-- ===== keyboard ========================= + +-- ======================================== +-- NEW 30.06.2022 +-- KEYS.int_ena = ALL_MODE0; -- int in all keys +-- KEYS.ena = !ALL_MODE0; -- ZX-Keyboard +-- new bit3 in ALL_MODE, disables keyboard interruptions w/o accellerator affected + KEYS.int_ena = LCELL(ALL_MODE0 & ALL_MODE3); + KEYS.ena = VCC; -- ZX-Keyboard always enabled +-- ======================================== + + KEYS.clk42 = CLK42; + KEYS.clk_k = DFF(CTH5,CLK42,,); + KEYS.kbd_cc = KBD_CC or !KBD_BLK; + KEYS.kbd_dd = KBD_DD; + + KD[].clk = CLK42; + NEXT_K = TFF(VCC,KEY_WRITE,,); + + CASE (NEXT_K) IS + WHEN 0 => KD[] = H"ED"; + WHEN 1 => KD[] = (B"00000",CTF[6..4]); + END CASE; + + K_XOR = !(KD7 xor KD6 xor KD5 xor KD4 xor KD3 xor KD2 xor KD1 xor KD0); + K_DATA[] = (VCC,K_XOR,KD[],GND); + + KEY_D[].clk = KBD_CC; + KEY_D[].d = (GND,KEY_D[10..1]); + + FOR i in 0 to 10 GENERATE + KEY_D[i].prn = K_DATA[i] or KEY_WRITE; + END GENERATE; + KEY_D[].clrn = /RESET; + + KEY_WRITE = DFF((!DFF(CTF1,CLK42,,) or CTF1),CLK42,,); + +-- KBD_DX = KEY_D0; +-- KBD_BLK = DFF(VCC,CTV7,KEY_WRITE,); + + KBD_BLK = VCC; + KBD_DX = GND; + +-- ======================================== +-- == Data Paths ========================== +-- ======================================== + + MDP[].clk = DECODE./IOMM; + + CASE (DECODE.TYPE[0],(DECODE.HDD_FLIP & DECODE.HDD_DATA)) IS + WHEN B"00" => MDP[] = MD[7..0]; + WHEN B"01" => MDP[] = HDDR[7..0]; + WHEN B"1X" => MDP[] = MD[15..8]; + END CASE; + +-- HDDR[].clk = DECODE./IOM; + + HDDR[].clk = LCELL(/WR & (/RD or DECODE./IOMM)); + HDDR[].ena = (DECODE.HDD_DATA & !DECODE./IOM); + + CASE DFF(/WR,DECODE.RAS,,) IS + WHEN 0 => HDDR[].d = D[]; + WHEN 1 => HDDR[].d = MD[15..8]; + END CASE; +% + CASE (DECODE.MC_END & DECODE.HDD_FLIP) IS + WHEN 0 => DMDX[] = (ACC.MDO[7..0]); + WHEN 1 => DMDX[] = (HDDR[]); + END CASE; +% + DMDX[] = (ACC.MDO[7..0]); + + ACC.HDDR[] = HDDR[]; + ACC.HDD_FLIP = DECODE.HDD_FLIP; + + CASE DECODE.TYPE0 IS + WHEN 0 => + KEY/KEMS[] = (LCELL((KEYS.kbo5 & !CBL_MODE) or (CBL_IND & CBL_MODE)),TAPE_IN,LCELL(CBL_MODE & CTV8),KEYS.kbo[4..0]); + AY/PORTS[] = DECODE.DO[]; + WHEN 1 => + KEY/KEMS[] = KEMPS[]; + AY/PORTS[] = AY3.DO[]; + END CASE; + + CASE DECODE.TYPE[2..1] IS + WHEN B"11" => PDD[] = MDP[]; + WHEN B"10" => PDD[] = KEY/KEMS[]; + WHEN B"01" => PDD[] = AY/PORTS[]; + WHEN B"00" => PDD[] = VCC; + END CASE; + + CASE /IO IS + WHEN 1 => DD[] = ACC.DO[]; + WHEN 0 => DD[] = PDD[]; + END CASE; + +-- D_OUT = !(/IO or /RD or LCELL((DCPP[7..4] == 0) or (DCPP[7..4] == 3))) or RD_RAM; + D_OUT = !(/IORD or LCELL((DCPP[7..4] == 0) or (DCPP[7..4] == 3))) or RD_RAM; + + V_WRXX[] = !SVIDEO.V_WEN[]; + + V_WRX3 = !SVIDEO.V_WEN3; + V_WRX2 = !SVIDEO.V_WEN2; + V_WRX1 = !SVIDEO.V_WEN1; + V_WRX0 = !SVIDEO.V_WEN0; + + FOR i IN 0 TO 7 GENERATE + D[i] = TRI(DD[i],D_OUT); + VD3[i] = TRI(DVD3[i],V_WRX3); + VD2[i] = TRI(DVD2[i],V_WRX2); + VD1[i] = TRI(DVD1[i],V_WRX1); + VD0[i] = TRI(DVD0[i],V_WRX0); + MD[i] = TRI(DMDX[i],!/WE_OUT or WR_PORT); + MD[i+8] = TRI(ACC.MDO[i+8],!/WE_OUT or WR_PORT); +-- MD[i+8] = TRI(DMDY[i],!/WE or WR_PORT); + END GENERATE; + +-- ======================================== +-- ======================================== +-- ======================================== +-- ======================================== +% +IF MODE == "SPECTRUM" GENERATE + + TEST_SWITCH = TFF((!KEYS.kb_sh & !KEYS.kb_ctrl),KEYS.kb_F12,,); + + CASE TEST_SWITCH IS + WHEN 0 => + KEYS./rf = /RF; + KEYS./io = /IO; + KEYS.a[15..8] = A[15..8]; + KEYS./iom = /IO; + + WHEN 1 => + + KEYS./rf = DFF((CT4 or CT5),CT2,,); + KEYS./io = DFF((CT4 or !CT5),CT2,,); + KEYS.a[15..8] = !KTA[]; + KEYS./iom = DFF((CT4 or !CT5),CT2,,); + + END CASE; + + CASE TEST_SWITCH IS + WHEN 0 => + RED[] = (SVIDEO.zx_color1 & (VCC,SVIDEO.zx_color3,B"000000")); + GREEN[] = (SVIDEO.zx_color2 & (VCC,SVIDEO.zx_color3,B"000000")); + BLUE[] = (SVIDEO.zx_color0 & (VCC,SVIDEO.zx_color3,B"000000")); + WHEN 1 => + RED[] = (CTH[4..0],CT[5..3]) & CTV[4] & BLANK & T_SIGNAL or TEST_1; + GREEN[] = (CTH[4..0],CT[5..3]) & CTV[5] & BLANK & T_SIGNAL or TEST_1; + BLUE[] = (CTH[4..0],CT[5..3]) & CTV[6] & BLANK & T_SIGNAL or TEST_1; + END CASE; + + DVD0[] = SVIDEO.vdo0[]; + DVD3[] = RED[]; + DVD2[] = GREEN[]; + DVD1[] = BLUE[]; + + V_WR0 = SVIDEO.v_wr0; + V_WR[3..1] = WR_COL; + + DECODE.TURBO_HAND = VCC; + +-- ===== TEST CODES ============================================ + + KTD[].clk = DFF((CT4 or !CT5),CT2,,); + KTD[] = KEYS.kbo[]; + + KTA0 = (CTV[5..3] == 0); + KTA1 = (CTV[5..3] == 1); + KTA2 = (CTV[5..3] == 2); + KTA3 = (CTV[5..3] == 3); + KTA4 = (CTV[5..3] == 4); + KTA5 = (CTV[5..3] == 5); + KTA6 = (CTV[5..3] == 6); + KTA7 = (CTV[5..3] == 7); + + CASE CTH[2..0] IS + WHEN 0 => KTT = KTD0; + WHEN 1 => KTT = KTD1; + WHEN 2 => KTT = KTD2; + WHEN 3 => KTT = KTD3; + WHEN 4 => KTT = KTD4; + WHEN 5 => KTT = KTD5; + WHEN 6 => KTT = KTD6; + WHEN 7 => KTT = KTD7; + END CASE; + + T_SIGNAL = DFF(((!CTH5 or TAPE_IN) & (CTH5 or MOUSE_D) & KBD_CC),CLK42,,); + + CASE (CTH[5..3],CTV[8..6]) IS + WHEN B"1XXXXX" => TEST_1 = GND; + WHEN B"XXX100" => TEST_1 = GND; + WHEN B"XXXX11" => TEST_1 = GND; + WHEN B"000000" => TEST_1 = TFF(VCC,KEYS.kb_ctrl,,); + WHEN B"001000" => TEST_1 = GND; + WHEN B"010000" => TEST_1 = GND; + WHEN B"011000" => TEST_1 = KTT; + WHEN B"000001" => TEST_1 = TFF(VCC,KEYS.kb_alt,,); + WHEN B"001001" => TEST_1 = GND; + WHEN B"010001" => TEST_1 = GND; + WHEN B"011001" => TEST_1 = GND; + WHEN B"000010" => TEST_1 = TFF(VCC,KEYS.kb_sh,,); + WHEN B"001010" => TEST_1 = GND; + WHEN B"010010" => TEST_1 = GND; + WHEN B"011010" => TEST_1 = GND; + END CASE; + +ELSE GENERATE +% + TEST_SWITCH = TFF((!KEYS.kb_sh & !KEYS.kb_ctrl & !KEYS.kb_alt),KEYS.kb_F12,,/RESET); + + DECODE.TURBO_HAND = TEST_SWITCH; + + KEY_IO = DFFE((/IO or !/M1),CLK42,,,(CT1 & CT2)); + KEYS./rf = DFFE((CT2 or !KEY_IO),CLK42,,,CT0); + KEYS./iom = KEY_IO; + KEYS./io = KEY_IO; + KEYS./m1 = VCC; + + KEYS.a[15..8] = A[15..8]; + + DVD0[] = SVIDEO.vdo0[]; + DVD1[] = SVIDEO.vdo1[]; + DVD2[] = SVIDEO.vdo2[]; + DVD3[] = SVIDEO.vdo3[]; + + V_WR[3..0] = SVIDEO.V_WR[]; +% +END GENERATE; +% +-- ===================================================== +-- ===================================================== + + SYS_ENA = (!/SYS or ROM_RG4) or + (A[15..4] == B"001111111111") or + (A[15..4] == B"00000000000X"); + +-- SYS_ENA2 = DFFE(SYS_ENA,/MR,,,/RF) & DFF((A[7..0] == B"0X111100"),CLK42,,); + SYS_ENA2 = DFF((A[7..0] == B"0X111100"),CLK42,,); + + ISA_PORT[].clk = /IOWR; + ISA_PORT[].d = D[]; + ISA_PORT[].ena = DECODE.BLK_R & DFF((DCPP[] == B"1111XXXX"),CLK42,,); + +IF (UPDATE == 1) GENERATE + + WAIT_ORIG = LCELL(/MR or CT5 or ALL_MODE2 or + LCELL((!(DECODE.V_RAM & (A14 & A15)) & !(A14 & !A15)) or TURBO)); + + + SOFT_RES[].prn = !DFF(DFF((LCELL(DECODE.BLK_R & A14 & A15) & + LCELL(DECODE.PAGE[7..4] == H"A")),CLK42,,),(/WR or /MR),/RESET,); + + -- /SYS=0 - system ROM on + /SYS = DFFE(!A6,/IOWR,/RESET,,SYS_ENA2); + + -- SYS_PG - system ROM0/ROM1 switch + SYS_PG = DFFE(D0,/IOWR,/RESET,!ROM_RG4,(SYS_ENA2 & !D1)); + + -- 0 - write A20 for ISA + ISA_A20 = (/IOWR or !DFF((DCPP[] == B"00011011"),CLK42,,)); -- 1B +-- ISA_A20 = VCC; + + -- 1 - CASHE on IN A,(0FBh/07Bh) +-- CASH_ON = DFFE(A7,/IORD,/RESET,,DFF((DCPP[] == H"88"),CLK42,,));-- 88 + CASH_ON = DFFE(A7,/IORD,/RESET,,DFF((A[7..0] == B"X1111011"),CLK42,,)); + + -- 0 - CS_ISA + + PRE_ISA = LCELL(!LCELL(ISA_PORT[] == B"1101XXXX") or !DECODE.BLK_R or !A14 or !A15); + PRE_ROM = LCELL(/SYS or A14 or A15 or CASH_ON); + PRE_CASH = LCELL(A14 or A15 or !CASH_ON); + +-- BLK_WAIT = LCELL(LCELL(PRE_CASH or !PRE_ROM) or (/RD & /WR) or /MR); + + WAIT_ROMX = LCELL(CS_ROM & CS_ISA); + WAIT_ROM = (WAIT_ROMX or DFF((WT_R[] == 0),CLK42,!WAIT_ROMX,)); + WT_R[].clk = CLK42; + CASE (WAIT_ROMX,WT_R[]) IS + WHEN 0 => WT_R[] = 0; + WHEN B"0001" => WT_R[] = WT_R[] - 1; + WHEN B"001X" => WT_R[] = WT_R[] - 1; + WHEN B"01XX" => WT_R[] = WT_R[] - 1; + WHEN B"1XXX" => WT_R[] = 4; + END CASE; + + CS_ISA = DFF((!/RF or PRE_ISA),!/MR,,LCELL(CS_ISA or !/MR)); + CS_ROMT = DFF((!/RF or PRE_ROM or !PRE_CASH),!/MR,,LCELL(CS_ROMT or !/MR)); + CS_CASHT = DFF((!/RF or !PRE_ROM or PRE_CASH),!/MR,,LCELL(CS_CASHT or !/MR)); + + CS_ROM = CS_ROMT; + + CS_CASH = CS_CASHT & CS_ISA & ISA_A20; + +-- CS_ROM = LCELL(LCELL(PRE_ROM or !PRE_CASH) or (/RD & /WR) or /MR); + +-- CS_CASH = LCELL(LCELL(PRE_CASH or !PRE_ROM) or (/RD & /WR) or /MR) & +-- CS_ISA & ISA_A20; + + CASE (PRE_ROM,PRE_CASH) IS + WHEN B"00" => ISA_A[] = B"1000"; -- error -> ISA + WHEN B"01" => ISA_A[] = ((ROM_RG3 xor !SYS_PG),ROM_RG[2..0]); -- ROM_ADRESS + WHEN B"10" => ISA_A[] = (B"01",ROM_RG[1..0]); -- CASHE_ADRESS + WHEN B"11" => ISA_A[] = (!PRE_ISA,GND,ISA_PORT[2..1]); -- for ISA_A20 + END CASE; + RA[] = ISA_A[3..0]; + + XACS.clk = !(/MR or /WR); + XACS.d = (!ROM_RG4 or A14 or A15); + XACS.prn = (XACS or (!/MR & ROM_RG4)); + +-- XACS.clk = CLK42; +-- XACS = (WAIT_ROM or /WR or A14 or A15); +-- XACS.prn = !/MR & ROM_RG4; + + BLK_MEM = LCELL(!PRE_ROM or !PRE_CASH or !PRE_ISA); + + RD_RAM = !(/MR or /RD or BLK_MEM); + + BLK_MWR2 = DECODE.RAM or BLK_MEM; + + DECODE.BLK_MEM = BLK_MEM; + + ROM_RG[].clk = /IOWR; + ROM_RG[].d = D[]; + ROM_RG[].ena = DFF((DCPP[] == H"8F"),CLK42,,) or + (!/SYS & DFF((A[7..0] == B"01011100"),CLK42,,)); -- 5C + ROM_RG[].clrn = /RESET; + +ELSE GENERATE + + SOFT_RES[].prn = DFF((!DFF(DECODE.BLK_R,CLK42,,) or /WR or !(DECODE.PAGE[7..4] == H"A")),CLK42,,!/MR); + + WT_R[].clk = GND; + WT_R[] = 0; + + WAIT_ROM = VCC; + + DECODE.BLK_MEM = GND; + + BLK_MWR2 = DECODE.BLK_R; + + XACS.clk = CLK42; + CASE ROM_WRITE_MODE IS + WHEN 0 => + CS_ROM = ROM_RG[4] or !/RF or LCELL(DECODE.CS_ROM or /RD or (DECODE.BLK_R & !LCELL(DECODE.PAGE[7..4] == 14))); + XACS = VCC; + WHEN 1 => + CS_ROM = /MR or !/RF or DFF((/RD & /WR),CLK42,,); +-- XACS = /MR or DFF((/WR or DECODE.MC_END),!CLK42,,); + XACS = /MR or DFF(/WR or !DFF(/WR,!CT2,,!/WR),!CT2,,!/WR); + END CASE; + +-- CS_CASH = !DECODE.BLK_R or !(DECODE.PAGE[7..4] == 15); + +-- CS for CASHE & ISA-Slots + + CS_CASH = (DFF(!(DECODE.PAGE[7..4] == B"11X1"),CLK42,,DECODE.BLK_R) & + +-- CS for ISA_A20 signal + + LCELL(DECODE./IOM or /WR or !(DCPP[] == B"00011011")) -- 1B + + ); + +-- Switcher for ISA/CASHE adress + + ISA_CASH = LCELL(DECODE.BLK_R & (DECODE.PAGE[7..4] == B"11X1")) or !/IOWR; + + CASE /IO IS + WHEN 0 => ISA_A[3..2] = B"00"; -- for Write to A20 port + ISA_A[1..0] = DECODE.PAGE[1..0]; -- ANY + + WHEN 1 => +-- ISA_A[3..2] = B"10"; -- for ISA Slots + ISA_A[3..2] = (!DECODE.PAGE5,DECODE.PAGE5); + +-- ISA_A[1..0] = DECODE.PAGE[1..0]; -- ISA select + ISA_A[1..0] = (DECODE.PAGE2,DECODE.PAGE1); -- ISA select + END CASE; + + RD_RAM = !(DECODE.CS_RAM or /RD or DECODE.BLK_R); + + CASE ROM_WRITE_MODE IS + WHEN 0 => + CASE (ISA_CASH,DECODE.RAM) IS + WHEN 0 => RA[] = (B"01",A[15..14]); -- for CASHE in RAM + WHEN 1 => RA[] = DECODE.RA[]; -- ROM Adresses + WHEN 2,3 => RA[] = ISA_A[3..0]; -- CASHE & ISA + END CASE; + WHEN 1 => + RA[] = ROM_RG[3..0]; + END CASE; + ROM_WRITE_MODE = DFF((ROM_RG[4] & !(A14 or A14)),CLK42,,); + + ROM_RG[].clk = /IOWR; + ROM_RG[].d = D[]; + ROM_RG[].ena = DFF((DCPP[] == H"8F"),CLK42,,); + ROM_RG[].clrn = /RESET; + +END GENERATE; + + +-- ===================================================== +-- ===================================================== + + RD_KMPS = DECODE./IOM or /RD or !(DECODE.TYPE[] == 7); + +-- WR_PORT = !(/IO or DFF(!DECODE.MC_END,CLK42,,) or /WR) or !(DECODE.WR_DWG or /IO or /WR); + + WR_PORT = (!(/IO or /WR) & LCELL(DFF(DECODE.MC_TYPE,CLK42,,))); + +-- WR_PORT = DFF((!(/IO or /WR) & DECODE.MC_TYPE),CLK42,,); + + WR_DWG = DECODE.WR_DWG; + +-- (NMI_X,KBD_CX) = GND; + (KBD_CX) = GND; + + IF (NMI_ON == "ON") GENERATE + NMI_X = (!KEYS.kb_f12 & KEYS.kb_alt); + ELSE GENERATE + NMI_X = GND; + END GENERATE; + +-- TFF(KEYS.kb_ctrl,KEYS.kb_f12,,); + +-- INT_X = !DFF(GND,CTV8,,((/IO or /M1) & DFF(!INT_X,CTH3,,))); + +-- INT_X = !DFF(GND,SVIDEO.INTT,,((/IO or /M1) & DFF(!INT_X,CTH3,,))); + +-- INT_X = !DFF(GND,(SVIDEO.INTT & KEYS.int),,((/IO or /M1) & DFF(!INT_X,CTH3,,))); + INT_X = !DFF(GND,(SVIDEO.INTT & KEYS.int),,((/IO or /M1) & DFF(DFF(!INT_X,CTH2,,),CTH2,,))) + or !CBL_INT; + + TAPE_OUT = LCELL(BORDER3); + +-- *************************************** + +-- RDXA = LCELL(DECODE.RD_KP11); +-- T_RDXA = DFF(GND,DECODE.RD_KP11,,DFF((T_RDXA),CLK42,,)); + +-- WR_TM9 = !DFF(VCC,!CLK42,DECODE.WR_TM9,); +-- WR_TM9 = LCELL(DFF(DECODE.RD_KP11,CLK42,,)); + +-- RDXA = LCELL(CT2 or DFFE(!CT2,!CLK42,,,CT1)); + + RDXA = DFF(!((CT[2..0] == B"11X") or (CT[2..0] == 0)),CLK42,,); + +-- T_RDXA = CT2; + T_RDXA = LCELL(RDXA); + +-- WR_TM9 = DFF(CT2,!CLK42,,); + WR_TM9 = LCELL(CT2); + + +-- SXA = TFF(VCC,T_RDXA,,); +-- SXA = DFF((CT3 xor (CT2 & CT1)),CLK42,,); + SXA = DFF((CT3 xor CT2),CLK42,,); + +-- WR_AWG = LCELL(LCELL(DECODE.WR_AWG)); +-- WR_AWG = LCELL(DECODE.WR_AWG); + WR_AWG = DECODE.WR_AWG; + +-- WR_AWG = DFF(DECODE.WR_AWG,CLK42,,); + +-- SXA = DFF(DECODE.KP11_MIX,CLK42,,); + + XA0 = TRI(KBD_CX,WR_TM9); + XA1 = TRI(KBD_DX,WR_TM9); + XA2 = TRI(TAPE_OUT,WR_TM9); + XA3 = TRI(GND,GND); + + KBD_DD = DFFE(XA1,T_RDXA,,,!SXA); + KBD_CC = DFFE(XA0,T_RDXA,,,!SXA); + TAPE_IN = DFFE(XA2,T_RDXA,,,!SXA); + MOUSE_D = DFFE(XA3,T_RDXA,,,!SXA); + + FDD_CH = DFFE(XA1,T_RDXA,,,SXA); + FDD_W = DFFE(XA0,T_RDXA,,,SXA); + SINC_1 = DFFE(XA2,T_RDXA,DECODE./RES,,SXA); + SINC_2 = DFFE(XA3,T_RDXA,DECODE./RES,,SXA); + + SINC_HOLD[3..0].clk = CT4; + SINC_HOLD[8..4].clk = CTH5; + + SINC_1M = DFF(!(SINC_HOLD[3..0] == 15),CLK42,,); + + CASE !SINC_1 IS + WHEN 0 => SINC_HOLD[3..0] = HOLD[3..0]; + WHEN 1 => SINC_HOLD[3..0] = (SINC_HOLD[3..0] + 1) or !SINC_1M; + END CASE; + + SINC_2M = DFF(!(SINC_HOLD[8..4] == B"1111X"),CLK42,,); + +-- CASE DFF((SINC_2 & DFF(SINC_2,CTV0,,)),CLK42,,) IS + + CASE SINC_2 IS + WHEN 1 => SINC_HOLD[8..4] = (HOLD[7..4],GND); + WHEN 0 => SINC_HOLD[8..4] = (SINC_HOLD[8..4] + 1) or !SINC_2M; + END CASE; + + COPY_SINC_H = DFF((!SINC_1M & DFF(SINC_1M,CLK42,,)),CLK42,,); + COPY_SINC_V = DFF((!SINC_2M & DFF(SINC_2M,CLK42,,)),CLK42,,); + +-- COPY_SINC_H = DFF(DFF(!SINC_1 & DFF(SINC_1,!CLK42,,),!CLK42,,),CLK42,,); +-- COPY_SINC_V = DFF(DFF(!SINC_2 & DFF(SINC_2,!CLK42,,),!CLK42,,),CLK42,,); + +-- START_UP = DFFE(DFFE(DFFE(VCC,CLK42,,,COPY_SINC_H),CLK42,,,COPY_SINC_V),CLK42,,,COPY_SINC_V); + START_UP = DFFE(DFFE(DFFE(VCC,CLK42,,,COPY_SINC_H),CLK42,,,COPY_SINC_H),CLK42,,,COPY_SINC_H); + + HOLD[].clk = /IOWR; + HOLD[].ena = DFF((DCPP[] == B"11001011"),CLK42,,); -- CB + HOLD[].d = D[]; + + HOLD[2..0].prn = DECODE./RES; + HOLD[3].clrn = DECODE./RES; + HOLD[6..4].prn = DECODE./RES; + HOLD[7].clrn = DECODE./RES; + +-- ===================================================== +-- ===== DCP =========================================== +-- ===================================================== + + DOS_ = (!((DECODE.PN4Q & A13 & A12) & (A[11..8] == B"1101")) & DOS) or (A14 or A15); + DOS = DFF(DOS_,!(/M1 or /MR),,/RESET); + DECODE.DOS = DOS; + + DECODE.REFRESH = CT4; + + DCPP[] = DECODE.DCPP[]; + + DECODE.CLK42 = CLK42; + DECODE./RESET = /RESET; + + DECODE.ACC_ON = ACC.ACC_ON; + + DECODE.CT[2..0] = CT[2..0]; + + RASX_[1..0] = (LCELL(DECODE.RAS),LCELL(DECODE.RAS)); + + RAS_[] = RASX_[]; + + MCA[] = DECODE.MCA[1..0]; + + DOUBLE_CAS = ACC.DOUBLE_CAS; + + CAS_A = LCELL(DECODE.CAS); +-- CAS_A = (DECODE.CAS); + + CASXE0 = LCELL((MCA0 == 0) or ((MCA0 == 1) & DOUBLE_CAS)); + CASXE1 = LCELL((MCA0 == 1) or ((MCA0 == 0) & DOUBLE_CAS)); + + CASX_0 = LCELL(CAS_A or !((!MCA1 & CASXE0) or DECODE.MC_TYPE)); + CASX_1 = LCELL(CAS_A or !((!MCA1 & CASXE1) or DECODE.MC_TYPE)); + CASX_2 = LCELL(CAS_A or !(( MCA1 & CASXE0) or DECODE.MC_TYPE)); + CASX_3 = LCELL(CAS_A or !(( MCA1 & CASXE1) or DECODE.MC_TYPE)); + + CAS_[] = CASX_[]; + +-- /WE = DFFE((/WE_OUT or DECODE.RAS),CLK42,,/RESET,); + /WE = DFFE((/WE_OUT or DECODE.RAS),CLK42,,/RESET,); + +-- /WE = LCELL(DFFE((/WE_OUT or DECODE.RAS),CLK42,,/RESET,)); +-- /WE = LCELL(/WE_OUT or CAS_A); + + /WE_OUT = LCELL(DECODE.MC_WRITE or BLK_MR or BLK_MWR2); + + DECODE.DOUBLE_CAS = DOUBLE_CAS; +-- DECODE.A[15..0] = A[]; + DECODE.A[15..0] = ACC.AO[]; + DECODE.DI[7..0] = D[]; + + MA[11..0] = DECODE.MA[11..0]; + MA[14..12] = (!TURBO,INT_X,NMI_X); + + CLKZ1 = DECODE.CLK_Z80; + + TURBO = DECODE.TURBO; + + DECODE./IO = /IO; + DECODE./RD = /RD; + DECODE./WR = /WR; + DECODE./MR = /MR; + DECODE./RF = /RF; + DECODE./M1 = /M1; + + /WAIT_ALL = (DECODE./WAIT & WAIT_ROM & WAIT_ORIG); + +-- /WAIT = TRI(DECODE./WAIT,LCELL(!(DECODE./WAIT & DFF(DECODE./WAIT,CLK42,,)))); + + /WAIT = TRI(/WAIT_ALL,LCELL(!/WAIT_ALL)); + + DECODE.TEST_R = TFF(KEYS.kb_ctrl,KEYS.kb_f12,,); + +-- DECODE.MD[7..0] = ACC.MD[]; + DECODE.MD[7..0] = ACC.DO[]; + +-- ===================================================== +-- == Accelerator ====================================== +-- ===================================================== + + ACC.ACC_ENA = ALL_MODE0; + + ACC.CLK42 = CLK42; + ACC./RESET = /RESET; + ACC.CT[2..0]= CT[2..0]; + ACC.CLK_Z80 = DECODE.CLK_Z80; + + ACC.RAS = DECODE.RAS; + ACC.CAS = DECODE.CAS; + + DECODE.CONTINUE = ACC.CONTINUE; +-- DECODE.CONTINUE = VCC; + + ACC.MC_END = DECODE.MC_END; + ACC.MC_BEGIN= DECODE.MC_BEGIN; + ACC.MC_TYPE = DECODE.MC_TYPE; + ACC.MC_WRITE= DECODE.MC_WRITE; +-- ACC.MCA[] = DECODE.MCA[]; + + ACC.AI[15..0] = A[]; + ACC.DI[7..0] = D[]; + + ACC./IO = /IO; + ACC./RD = /RD; + ACC./WR = /WR; + ACC./MR = /MR; + ACC./RF = /RF; + ACC./M1 = /M1; + ACC./IOM = DECODE./IOM; + + ACC.DCP[7..0] = DCPP[]; + + ACC.MDI[15..0] = MD[]; + +-- ACC.MDO[15..0]; + +-- ===================================================== +-- ===== Graf-Mode ===================================== +-- ===================================================== + + RGMOD[].clk = /IOWR; + RGMOD[].ena = DFF((DCPP[] == B"1100X101"),CLK42,,); +-- (DCPP[] == B"1100X101"); + RGMOD[].d = D[]; + RGMOD[].clrn= /RESET; + + DECODE.G_LINE[] = (GND,GND,ACC.G_LINE[7..0]); + +-- ===================================================== +-- ===== VIDEO ========================================= +-- ===================================================== + + VIDEO_PG = LCELL(DECODE.PAGE[7..4] == B"0101"); + BLK_MR = LCELL((VIDEO_PG & + (DECODE.PAGE2 or (DECODE.PAGE3 & ACC.GLISSER)))); + + GLISSER = LCELL(ACC.GLISSER & DECODE.PAGE[3] & VIDEO_PG); + + SVIDEO.clk42 = CLK42; + + CT[5..0] = SVIDEO.ct[5..0]; + CTH[5..0] = SVIDEO.cth[5..0]; + CTV[8..0] = SVIDEO.ctv[8..0]; + CTF[6..0] = SVIDEO.ctf[6..0]; + + BLANK = SVIDEO.blank; + + SVIDEO.start_up = VCC; + SVIDEO.copy_sinc_h = COPY_SINC_H; + SVIDEO.copy_sinc_v = COPY_SINC_V; + +-- SVIDEO.wr = (DECODE.MC_WRITE or DECODE.CAS or GLISSER); +-- SVIDEO.wr = DFF((DECODE.MC_WRITE or GLISSER or DECODE.RAS),CLK42,,/RESET); + SVIDEO.wr = DFF((DECODE.MC_WRITE or GLISSER or DECODE.CAS),!CLK42,,/RESET); + +-- SVIDEO.vai[] = (DECODE.GA[],A[9..0]); + SVIDEO.vai[] = (DECODE.GA[],ACC.AO[9..0]); + + VA[] = SVIDEO.vao[]; + + SVIDEO.D[] = D[]; + SVIDEO.MDI[] = ACC.MDO[]; + SVIDEO.DOUBLE_CAS = DOUBLE_CAS; + + SVIDEO.VDM0[7..0] = VD0[]; + SVIDEO.VDM1[7..0] = VD1[]; + SVIDEO.VDM2[7..0] = VD2[]; + SVIDEO.VDM3[7..0] = VD3[]; + + V_CS[1..0] = SVIDEO.v_cs[]; + WR_COL = SVIDEO.WR_PIX; + +-- ZX_COLOR[3..0] + + SVIDEO.ZX_PORT[5..0] = (ACC.G_LINE[5..0]); +-- SVIDEO.ZX_PORT[7..6] = (DECODE.SP_SA,LCELL(DECODE.SP_SCR & !(A13 & !ACC.G_LINE7) & !ACC.G_LINE6)); + +-- NEW 25.08.2022 +-- disable zx adressing due accelerator is on + SVIDEO.ZX_PORT[7..6] = (DECODE.SP_SA,LCELL(DECODE.SP_SCR & !(A13 & !ACC.G_LINE7) & !ACC.G_LINE6 & !ALL_MODE0)); + + SVIDEO.DIR_PORT[0] = DECODE.SCR128; + + SVIDEO.DIR_PORT[3] = RGMOD0; + + IF (SCREEN_OFF == "USE") GENERATE + SVIDEO.DIR_PORT[4] = RGMOD1; -- 1 screen off, 0 - screen on + ELSE GENERATE + SVIDEO.DIR_PORT[4] = GND; -- 1 screen off, 0 - screen on + END GENERATE; + + SVIDEO.DIR_PORT[2..1] = GND; + SVIDEO.DIR_PORT[7..5] = BORDER[2..0]; +-- SVIDEO.DIR_PORT[7..5] = MS.OUT_X[7..5]; + + SVIDEO.MOUSE_X[] = MS.OUT_X[]; + SVIDEO.MOUSE_Y[] = MS.OUT_Y[]; + +% + bit0 - Spectrum SCREEN Switch + bit1 - Spectrum Adress MODE + bit2 - Write to Spectrum Screen OFF + + bit7..5 - Border +% + +-- ===================================================== + + ALL_MODE[7..0].clk = /IOWR; + ALL_MODE[7..0].ena = DFF((DCPP[] == B"11000011"),CLK42,,); -- C3 + ALL_MODE[].d = D[]; + ALL_MODE[].prn = /RESET; + +-- ===================================================== +-- === AUDIO OUT ======================================= +-- ===================================================== + + DAC_DATA = DFFE(DFF(AUDIO_R15,CT2,,),!CT2,,,); + +-- DAC_DATA = DFF(AUDIO_R15,CLK42,,); +-- DAC_DATA = AUDIO_R15; + + DAC_WS = DFF(CTH1,CLK42,,); + DAC_BCK = DFF(CT2,CLK42,,); + + AUDIO_R[15..0].clk = CLK42; + AUDIO_R[15..0].ena = !CT2 & DFF(CT2,CLK42,,); + + AUDIO_CH = DFF(((CTH0,CT[5..3]) == 15),CT2,,); + + IF AUDIO_CH THEN + AUDIO_R[15..0].d = AY_CHS[15..0]; + ELSE + AUDIO_R[15..0].d = (AUDIO_R[14..0],GND); + END IF; + +-- ====== COVOX ========== + + CBL_MODE = CBL_XX7; + CBL_STEREO = CBL_XX6; + CBL_MODE16 = CBL_XX5; + CBL_INT_ENA = CBL_XX4; + + CBL_INT = DFF(GND,!CBL_CNT6,,(CBL_INT_ENA & (/IO or /M1))); + + CBL_XX[].clk = /IOWR; + CBL_XX[].ena = DFF((DCPP[] == B"10001001"),CLK42,,); -- 89 + CBL_XX[] = D[]; + + CBL_CTX[].clk = !CTH1; + CBL_CNT[].clk = !CTH1; + + CASE CBL_XX[3..0] IS + WHEN 0 => CBL_TAB[] = 13; -- 16khz -- mono/stereo + WHEN 1 => CBL_TAB[] = 9; -- 22khz -- mono/stereo + WHEN 2 => CBL_TAB[] = 0; -- reserved + WHEN 3 => CBL_TAB[] = 0; -- reserved + WHEN 4 => CBL_TAB[] = 0; -- reserved + WHEN 5 => CBL_TAB[] = 0; -- reserved + WHEN 6 => CBL_TAB[] = 0; -- reserved + WHEN 7 => CBL_TAB[] = 0; -- reserved + + WHEN 8 => CBL_TAB[] = 27; -- 7.8125 KHz -- mono/stereo 8/16 bit + WHEN 9 => CBL_TAB[] = 19; -- 10.9375 KHz -- mono/stereo 8/16 bit + WHEN 10=> CBL_TAB[] = 13; -- 15.625 KHz -- mono/stereo 8/16 bit + WHEN 11=> CBL_TAB[] = 9; -- 21.875 KHz -- mono/stereo 8/16 bit + WHEN 12=> CBL_TAB[] = 6; -- 31.25 KHz -- mono/stereo 8/16 bit + WHEN 13=> CBL_TAB[] = 4; -- 43.75 KHz -- mono/stereo 8/16 bit + WHEN 14=> CBL_TAB[] = 3; -- 54.6875 KHz -- mono/stereo 8/16 bit + WHEN 15=> CBL_TAB[] = 1; -- 109.375 KHz -- mono/stereo 8/16 bit +-- WHEN 15=> CBL_TAB[] = 0; -- (218.75)KHz -- stereo 110 only + END CASE; + + IF (CBL_CTX[] == 0) THEN + CBL_CTX[].d = CBL_TAB[]; + ELSE + CBL_CTX[].d = CBL_CTX[] - 1; + END IF; + + CASE (CBL_STEREO,LCELL(CBL_CTX[] == 0)) IS + WHEN 0,2 => CBL_CNT[].d = CBL_CNT[]; + WHEN 1 => CBL_CNT[].d = CBL_CNT[]+1; + WHEN 3 => CBL_CNT[].d = CBL_CNT[]+2; + END CASE; + + CBL_CNT[].clrn = CBL_MODE; + + CBL_IND = CBL_CNT7 xor CBL_WA7; + +-- CBL_WR = DFF((DCPP[] == B"10001000"),CLK42,,) & !/IOWR; -- 88 + + CBL_WR = (DFF((DCPP[] == B"10001000"),CLK42,,) & !/IOWR) or + (DFF((DECODE.PAGE[7..0] == B"11111101"),CLK42,(CBL_INT_ENA & ACC.ACC_DIR1),) & + !DFF((DECODE.MC_WRITE or DECODE.CAS),CLK42,,/RESET)); + + + CBL_WAE = CBL_MODE16 & DFF(!CBL_WAE,!CBL_WR,,CBL_INT); + + CBL_WA[].clk = !CBL_WR; + CBL_WA[].ena = !CBL_WAE; + + CBL_WA[7].clrn = CBL_MODE & CBL_INT_ENA & (CBL_INT or !CBL_CNT7); + CBL_WA[7].prn = (CBL_INT or CBL_CNT7); + + CBL_WA[6..0].clrn = CBL_MODE & CBL_INT_ENA & CBL_INT; + + CBL_WA[].d = CBL_WA[] + 1; + + CBD[].clk = !CBL_WR; + CBD[].ena = CBL_WAE; +-- CBD[].d = D[]; + CBD[].d = ACC.MDO[7..0]; + CBD[].clrn = CBL_MODE16; + + CBL.wren = (CBL_WR & !CBL_WAE); + +-- CBL.data[] = ((D7 xor CBL_MODE16),D[6..0],CBD[]); + CBL.data[] = ((ACC.MDO15 xor CBL_MODE16),ACC.MDO[14..8],CBD[]); + + CBL.wraddress[] = ((!A[15..8]) & !CBL_INT_ENA) xor CBL_WA[]; + + CBL.wrclock = CLK42; + CBL.wrclken = VCC; + CBL.rden = VCC; + CBL.rdaddress[] = (CBL_CNT[7..1],LCELL((CBL_CNT0 & !CBL_STEREO) or (AUDIO_CH & CBL_STEREO))); + CBL.rdclock = CLK42; + CBL.rdclken = VCC; + + CBL_R[].ena = DFF((CBL_MODE or (CBL_WR)),CLK42,,); + + CBL_R[].CLK = CLK42; + CBL_R[15].prn = /RESET; + CBL_R[14..0].clrn = /RESET; + CASE CBL_MODE IS + WHEN 0 => CBL_R[] = (D[7..0],B"00000000"); + WHEN 1 => CBL_R[] = CBL.q[]; + END CASE; + +-- ====== AY-3-8910 ======== + + AY3.CLK42 = CLK42; + + AY3./RESET = /RESET; + AY3.AY_T[8..0] = (CTH[2..0],CT[5..0]); + + AY3.AY_D_WR = DFF((DECODE./IOM or /WR) or !DFF((DCPP[] == H"91"),CLK42,,),CLK42,,); + AY3.AY_A_WR = DFF((DECODE./IOM or /WR) or !DFF((DCPP[] == H"90"),CLK42,,),CLK42,,); + + AY3.D[7..0] = D[]; + AY3.BEEPER = BORDER4; + +-- AY3.DO[7..0] : OUTPUT; + +-- AY3.AY_CH_A[3..0] : OUTPUT; +-- AY3.AY_CH_B[3..0] : OUTPUT; +-- AY3.AY_CH_C[3..0] : OUTPUT; + + AY_FULL[].clk = CLK42; + +-- AY_CHS[].clk = !CTH0; + AY_CHS[].clk = !DFF((CTH1 & (CTH0 or !CT5)),CLK42,,); + AY_CHS[].ena = VCC; + +-- AY_FULL[] = (GND,AY_CH_L[]) + (GND,AY_CH_R[]); + + CASE DFF(CTH0,CLK42,,) IS + WHEN 0 => AY_FULL[] = (AY3.AY_CH_L[],GND); + WHEN 1 => AY_FULL[] = (AY3.AY_CH_R[],GND); + END CASE; + +-- AY_CHS[].d = (((GND,AY_FULL[]) + (VCC,CBL.q[15..5])),B"0000"); + +-- AY_CHS[].d = (((GND,AY_FULL[]) + (VCC,CBL.q[15..8],B"000")),B"0000"); + AY_CHS[].d = (((GND,AY_FULL[]) + (VCC,CBL_R[15..5])),CBL_R[4..1]); + +-- ===== MOUSE ========================= + + MS.clk = DFF(CTH5,CLK42,,); + MS.mouse_d = MOUSE_D; + + CASE (A10,A8) IS + WHEN 0,2 => KEMPS[] = (B"111111",!MS.OUT_K0,!MS.OUT_K1); + WHEN 1 => KEMPS[] = (MS.OUT_X[7..0]); + WHEN 3 => KEMPS[] = !(MS.OUT_Y[7..0]); + END CASE; + +END; + diff --git a/src/altera/quartus/acex/SP2_ACEX.flow.rpt b/src/altera/quartus/acex/SP2_ACEX.flow.rpt new file mode 100644 index 0000000..9c51df3 --- /dev/null +++ b/src/altera/quartus/acex/SP2_ACEX.flow.rpt @@ -0,0 +1,103 @@ +Flow report for SP2_ACEX +Sun Aug 28 15:25:51 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------+ +; Flow Summary ; ++-------------------------+----------------------------------------------+ +; Flow Status ; Flow Failed - Sun Aug 28 15:25:51 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; SP2_ACEX ; +; Top-level Entity Name ; SP2_ACEX ; +; Family ; ACEX1K ; +; Device ; EP1K30QC208-3 ; +; Timing Models ; Final ; +; Met timing requirements ; N/A ; ++-------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 08/28/2022 15:25:50 ; +; Main task ; Compilation ; +; Revision Name ; SP2_ACEX ; ++-------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++---------------------------------+-----------------------------+---------------+-------------+----------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++---------------------------------+-----------------------------+---------------+-------------+----------------------+ +; COMPILER_SIGNATURE_ID ; 52243291855.166168955009032 ; -- ; -- ; -- ; +; CUT_OFF_READ_DURING_WRITE_PATHS ; Off ; On ; -- ; -- ; +; EDA_INPUT_GND_NAME ; Gnd ; -- ; -- ; eda_design_synthesis ; +; EDA_INPUT_VCC_NAME ; Vcc ; -- ; -- ; eda_design_synthesis ; +; EDA_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; eda_design_synthesis ; +; EXCLUDE_TPD_PATHS_LESS_THAN ; 0 ns ; -- ; -- ; -- ; +; FMAX_REQUIREMENT ; 100 MHz ; -- ; -- ; -- ; ++---------------------------------+-----------------------------+---------------+-------------+----------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 228 MB ; 00:00:01 ; +; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-72JG930 ; Windows Vista ; 6.2 ; x86_64 ; ++----------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off SP2_ACEX -c SP2_ACEX + + + diff --git a/src/altera/quartus/acex/SP2_ACEX.map.rpt b/src/altera/quartus/acex/SP2_ACEX.map.rpt new file mode 100644 index 0000000..9a8db38 --- /dev/null +++ b/src/altera/quartus/acex/SP2_ACEX.map.rpt @@ -0,0 +1,184 @@ +Analysis & Synthesis report for SP2_ACEX +Sun Aug 28 15:25:51 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Failed - Sun Aug 28 15:25:51 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; SP2_ACEX ; +; Top-level Entity Name ; SP2_ACEX ; +; Family ; ACEX1K ; ++-----------------------------+----------------------------------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++--------------------------------------------------------------+---------------+---------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------+---------------+---------------+ +; Device ; EP1K30QC208-3 ; ; +; Top-level entity name ; SP2_ACEX ; SP2_ACEX ; +; Family name ; ACEX1K ; Stratix II ; +; Use smart compilation ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Auto Implement in ROM ; Off ; Off ; +; Optimization Technique ; Area ; Area ; +; Carry Chain Length ; 32 ; 32 ; +; Cascade Chain Length ; 2 ; 2 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++--------------------------------------------------------------+---------------+---------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+-----------------------+-----------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+-----------------------+-----------------------------------------------------------------+ +; SP2_ACEX.tdf ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf ; +; lpm_ram_dp.inc ; yes ; Auto-Found AHDL File ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dp.inc ; +; kbd.inc ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/acex/kbd.inc ; +; video2.inc ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/acex/video2.inc ; +; dcp.inc ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/acex/dcp.inc ; +; acceler.inc ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/acex/acceler.inc ; +; ay.inc ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/acex/ay.inc ; +; mouse.inc ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/acex/mouse.inc ; +; MOUSE.tdf ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/acex/MOUSE.tdf ; +; lpm_add_sub.inc ; yes ; Auto-Found AHDL File ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.inc ; +; kbd.tdf ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/acex/kbd.tdf ; +; lpm_ram_dq.inc ; yes ; Auto-Found AHDL File ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.inc ; +; lpm_ram_dq.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf ; +; altram.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altram.inc ; +; lpm_mux.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_mux.inc ; +; lpm_decode.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_decode.inc ; +; aglobal90.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/aglobal90.inc ; +; altram.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altram.tdf ; +; memmodes.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/memmodes.inc ; +; altsyncram.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altsyncram.inc ; +; altqpram.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altqpram.inc ; ++----------------------------------+-----------------+-----------------------+-----------------------------------------------------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Sun Aug 28 15:25:50 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SP2_ACEX -c SP2_ACEX +Warning: Using design file SP2_ACEX.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: SP2_ACEX +Info: Elaborating entity "SP2_ACEX" for the top level hierarchy +Warning: Variable or input pin "DMD" is defined but never used +Warning: Variable or input pin "T_SIGNAL" is defined but never used +Warning: Variable or input pin "RED" is defined but never used +Warning: Variable or input pin "GREEN" is defined but never used +Warning: Variable or input pin "BLUE" is defined but never used +Warning: Variable or input pin "MDR" is defined but never used +Warning: Variable or input pin "ISA_CASH" is defined but never used +Warning: Variable or input pin "ROM_WRITE_MODE" is defined but never used +Warning: Variable or input pin "/HALT" is defined but never used +Warning: Using design file MOUSE.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: mouse +Info: Elaborating entity "MOUSE" for hierarchy "MOUSE:MS" +Warning: Variable or input pin "KB_OFL" is defined but never used +Warning: Using design file kbd.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: kbd +Info: Elaborating entity "kbd" for hierarchy "kbd:KEYS" +Warning: Variable or input pin "/IOM" is defined but never used +Warning: Variable or input pin "/M1" is defined but never used +Info: Elaborating entity "lpm_ram_dq" for hierarchy "kbd:KEYS|lpm_ram_dq:$00021" +Info: Elaborated megafunction instantiation "kbd:KEYS|lpm_ram_dq:$00021" +Info: Instantiated megafunction "kbd:KEYS|lpm_ram_dq:$00021" with the following parameter: + Info: Parameter "LPM_WIDTH" = "8" + Info: Parameter "LPM_WIDTHAD" = "8" + Info: Parameter "LPM_FILE" = "KBD_INI2.MIF" + Info: Parameter "LPM_OUTDATA" = "UNREGISTERED" +Info: Elaborating entity "altram" for hierarchy "kbd:KEYS|lpm_ram_dq:$00021|altram:sram" +Error: Memory Initialization File or Hexadecimal (Intel-Format) File "KBD_INI2.MIF" contains illegal syntax at line 13 File: C:/Sprinter/src/altera/quartus/acex/KBD_INI2.MIF Line: 13 +Critical Warning: Can't read Memory Initialization File or Hexadecimal (Intel-Format) File KBD_INI2.MIF -- setting all initial values to 0 +Error: Can't elaborate user hierarchy "kbd:KEYS|lpm_ram_dq:$00021|altram:sram" File: c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf Line: 101 +Info: Elaborated megafunction instantiation "kbd:KEYS|lpm_ram_dq:$00021|altram:sram", which is child of megafunction instantiation "kbd:KEYS|lpm_ram_dq:$00021" +Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 16 warnings + Error: Peak virtual memory: 228 megabytes + Error: Processing ended: Sun Aug 28 15:25:51 2022 + Error: Elapsed time: 00:00:01 + Error: Total CPU time (on all processors): 00:00:01 + + diff --git a/src/altera/quartus/acex/SP2_ACEX.map.summary b/src/altera/quartus/acex/SP2_ACEX.map.summary new file mode 100644 index 0000000..38ca8c9 --- /dev/null +++ b/src/altera/quartus/acex/SP2_ACEX.map.summary @@ -0,0 +1,5 @@ +Analysis & Synthesis Status : Failed - Sun Aug 28 15:25:51 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : SP2_ACEX +Top-level Entity Name : SP2_ACEX +Family : ACEX1K diff --git a/src/altera/quartus/acex/SP2_ACEX.qpf b/src/altera/quartus/acex/SP2_ACEX.qpf new file mode 100644 index 0000000..4abdd48 --- /dev/null +++ b/src/altera/quartus/acex/SP2_ACEX.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 03:32:05 August 28, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "03:32:05 August 28, 2022" + +# Revisions + +PROJECT_REVISION = "SP2_ACEX" diff --git a/src/altera/quartus/acex/SP2_ACEX.qsf b/src/altera/quartus/acex/SP2_ACEX.qsf new file mode 100644 index 0000000..19dbb7b --- /dev/null +++ b/src/altera/quartus/acex/SP2_ACEX.qsf @@ -0,0 +1,1918 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 03:32:05 August 28, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# SP2_ACEX_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY ACEX1K +set_global_assignment -name DEVICE "EP1K30QC208-3" +set_global_assignment -name TOP_LEVEL_ENTITY SP2_ACEX +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "03:32:05 AUGUST 28, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" +set_location_assignment LC8_B36 -to CASXE1 +set_location_assignment LC8_B36 -to CASXE[1] +set_location_assignment LC7_B36 -to CASXE0 +set_location_assignment LC7_B36 -to CASXE[0] +set_location_assignment LC6_B36 -to CASX_3 +set_location_assignment LC6_B36 -to CASX_[3] +set_location_assignment LC2_B36 -to CASX_2 +set_location_assignment LC2_B36 -to CASX_[2] +set_location_assignment LC5_B36 -to CASX_1 +set_location_assignment LC5_B36 -to CASX_[1] +set_location_assignment LC1_B36 -to CASX_0 +set_location_assignment LC1_B36 -to CASX_[0] +set_location_assignment LC8_F18 -to "video2:SVIDEO|V_WRM" +set_location_assignment LC2_F20 -to "video2:SVIDEO|V_WEM2" +set_location_assignment LC2_F20 -to "video2:SVIDEO|V_WEM[2]" +set_location_assignment LC5_F11 -to "video2:SVIDEO|V_WE_R" +set_location_assignment LC3_F15 -to "video2:SVIDEO|V_WEMMO" +set_location_assignment LC2_F18 -to "video2:SVIDEO|V_WEM" +set_location_assignment LC8_F20 -to "video2:SVIDEO|V_WRM2" +set_location_assignment LC8_F20 -to "video2:SVIDEO|V_WRM[2]" +set_location_assignment LC3_F12 -to "video2:SVIDEO|V_WEMMM" +set_location_assignment LC2_F12 -to "video2:SVIDEO|V_WEMMN" +set_location_assignment LC6_F12 -to "video2:SVIDEO|V_WE" +set_location_assignment LC5_F4 -to "video2:SVIDEO|V_CSX2" +set_location_assignment LC5_F4 -to "video2:SVIDEO|V_CSX[2]" +set_location_assignment LC5_F5 -to "video2:SVIDEO|V_CSX1" +set_location_assignment LC5_F5 -to "video2:SVIDEO|V_CSX[1]" +set_location_assignment LC5_F3 -to "video2:SVIDEO|V_CSX0" +set_location_assignment LC5_F3 -to "video2:SVIDEO|V_CSX[0]" +set_location_assignment LC2_A15 -to "dcp:DECODE|WR_AWGX" +set_location_assignment LC4_F17 -to "video2:SVIDEO|V_WEMM" +set_location_assignment LC2_F19 -to "video2:SVIDEO|V_WEY2" +set_location_assignment LC2_F19 -to "video2:SVIDEO|V_WEY[2]" +set_location_assignment LC2_F14 -to "video2:SVIDEO|V_WEY3" +set_location_assignment LC2_F14 -to "video2:SVIDEO|V_WEY[3]" +set_location_assignment LC2_F16 -to "video2:SVIDEO|V_WEY1" +set_location_assignment LC2_F16 -to "video2:SVIDEO|V_WEY[1]" +set_location_assignment LC2_F17 -to "video2:SVIDEO|V_WEY0" +set_location_assignment LC2_F17 -to "video2:SVIDEO|V_WEY[0]" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_0" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][0]" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_1" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][1]" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_2" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][2]" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_3" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][3]" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_4" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][4]" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_5" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][5]" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_6" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][6]" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_7" +set_location_assignment EAB_D -to "acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][7]" +set_location_assignment LC1_F14 -to V_WRX3 +set_location_assignment LC1_F14 -to V_WRX[3] +set_location_assignment LC1_F16 -to V_WRX1 +set_location_assignment LC1_F16 -to V_WRX[1] +set_location_assignment LC1_F17 -to V_WRX0 +set_location_assignment LC1_F17 -to V_WRX[0] +set_location_assignment LC8_F16 -to "video2:SVIDEO|V_WR_1" +set_location_assignment LC8_F16 -to "video2:SVIDEO|V_WR_[1]" +set_location_assignment LC8_F17 -to "video2:SVIDEO|V_WR_0" +set_location_assignment LC8_F17 -to "video2:SVIDEO|V_WR_[0]" +set_location_assignment EAB_E -to "ay:AY3|lpm_ram_dq:90|altram:sram|segment0_0" +set_location_assignment EAB_E -to "ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][0]" +set_location_assignment EAB_E -to "ay:AY3|lpm_ram_dq:90|altram:sram|segment0_1" +set_location_assignment EAB_E -to "ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][1]" +set_location_assignment EAB_E -to "ay:AY3|lpm_ram_dq:90|altram:sram|segment0_2" +set_location_assignment EAB_E -to "ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][2]" +set_location_assignment EAB_E -to "ay:AY3|lpm_ram_dq:90|altram:sram|segment0_3" +set_location_assignment EAB_E -to "ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][3]" +set_location_assignment EAB_E -to "ay:AY3|lpm_ram_dq:90|altram:sram|segment0_4" +set_location_assignment EAB_E -to "ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][4]" +set_location_assignment EAB_E -to "ay:AY3|lpm_ram_dq:90|altram:sram|segment0_5" +set_location_assignment EAB_E -to "ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][5]" +set_location_assignment EAB_E -to "ay:AY3|lpm_ram_dq:90|altram:sram|segment0_6" +set_location_assignment EAB_E -to "ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][6]" +set_location_assignment EAB_E -to "ay:AY3|lpm_ram_dq:90|altram:sram|segment0_7" +set_location_assignment EAB_E -to "ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][7]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_0" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][0]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_1" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][1]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_2" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][2]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_3" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][3]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_4" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][4]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_5" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][5]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_6" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][6]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_7" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][7]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_8" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][8]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_9" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][9]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_10" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][10]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_11" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][11]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_12" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][12]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_13" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][13]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_14" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][14]" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_15" +set_location_assignment EAB_C -to "dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][15]" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_0" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][0]" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_1" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][1]" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_2" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][2]" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_3" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][3]" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_4" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][4]" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_5" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][5]" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_6" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][6]" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_7" +set_location_assignment EAB_B -to "kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][7]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_5" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][5]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_6" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][6]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_7" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][7]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_8" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][8]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_9" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][9]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_10" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][10]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_11" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][11]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_12" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][12]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_13" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][13]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_14" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][14]" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment0_15" +set_location_assignment EAB_A -to "lpm_ram_dp:CBL|altdpram:sram|segment[0][15]" +set_location_assignment LC1_F19 -to V_WRX2 +set_location_assignment LC1_F19 -to V_WRX[2] +set_location_assignment LC8_F19 -to "video2:SVIDEO|V_WR_2" +set_location_assignment LC8_F19 -to "video2:SVIDEO|V_WR_[2]" +set_location_assignment LC8_F14 -to "video2:SVIDEO|V_WR_3" +set_location_assignment LC8_F14 -to "video2:SVIDEO|V_WR_[3]" +set_location_assignment LC2_A32 -to "dcp:DECODE|285" +set_location_assignment LC2_A35 -to RASX_0 +set_location_assignment LC2_A35 -to RASX_[0] +set_location_assignment LC2_A34 -to RASX_1 +set_location_assignment LC2_A34 -to RASX_[1] +set_location_assignment PIN_17 -to XA3 +set_location_assignment PIN_17 -to XA[3] +set_location_assignment PIN_9 -to XA1 +set_location_assignment PIN_9 -to XA[1] +set_location_assignment PIN_200 -to XA2 +set_location_assignment PIN_200 -to XA[2] +set_location_assignment PIN_180 -to XA0 +set_location_assignment PIN_180 -to XA[0] +set_location_assignment PIN_114 -to VD30 +set_location_assignment PIN_114 -to VD[30] +set_location_assignment PIN_136 -to VD31 +set_location_assignment PIN_136 -to VD[31] +set_location_assignment PIN_144 -to VD32 +set_location_assignment PIN_144 -to VD[32] +set_location_assignment PIN_148 -to VD33 +set_location_assignment PIN_148 -to VD[33] +set_location_assignment PIN_149 -to VD34 +set_location_assignment PIN_149 -to VD[34] +set_location_assignment PIN_143 -to VD35 +set_location_assignment PIN_143 -to VD[35] +set_location_assignment PIN_139 -to VD36 +set_location_assignment PIN_139 -to VD[36] +set_location_assignment PIN_128 -to VD37 +set_location_assignment PIN_128 -to VD[37] +set_location_assignment PIN_150 -to VD20 +set_location_assignment PIN_150 -to VD[20] +set_location_assignment PIN_115 -to VD21 +set_location_assignment PIN_115 -to VD[21] +set_location_assignment PIN_135 -to VD22 +set_location_assignment PIN_135 -to VD[22] +set_location_assignment PIN_140 -to VD23 +set_location_assignment PIN_140 -to VD[23] +set_location_assignment PIN_141 -to VD24 +set_location_assignment PIN_141 -to VD[24] +set_location_assignment PIN_147 -to VD25 +set_location_assignment PIN_147 -to VD[25] +set_location_assignment PIN_142 -to VD26 +set_location_assignment PIN_142 -to VD[26] +set_location_assignment PIN_131 -to VD27 +set_location_assignment PIN_131 -to VD[27] +set_location_assignment PIN_104 -to VD10 +set_location_assignment PIN_104 -to VD[10] +set_location_assignment PIN_111 -to VD11 +set_location_assignment PIN_111 -to VD[11] +set_location_assignment PIN_120 -to VD12 +set_location_assignment PIN_120 -to VD[12] +set_location_assignment PIN_127 -to VD13 +set_location_assignment PIN_127 -to VD[13] +set_location_assignment PIN_132 -to VD14 +set_location_assignment PIN_132 -to VD[14] +set_location_assignment PIN_134 -to VD15 +set_location_assignment PIN_134 -to VD[15] +set_location_assignment PIN_133 -to VD16 +set_location_assignment PIN_133 -to VD[16] +set_location_assignment PIN_122 -to VD17 +set_location_assignment PIN_122 -to VD[17] +set_location_assignment PIN_103 -to VD00 +set_location_assignment PIN_103 -to VD[00] +set_location_assignment PIN_113 -to VD01 +set_location_assignment PIN_113 -to VD[01] +set_location_assignment PIN_116 -to VD02 +set_location_assignment PIN_116 -to VD[02] +set_location_assignment PIN_121 -to VD03 +set_location_assignment PIN_121 -to VD[03] +set_location_assignment PIN_126 -to VD04 +set_location_assignment PIN_126 -to VD[04] +set_location_assignment PIN_125 -to VD05 +set_location_assignment PIN_125 -to VD[05] +set_location_assignment PIN_119 -to VD06 +set_location_assignment PIN_119 -to VD[06] +set_location_assignment PIN_112 -to VD07 +set_location_assignment PIN_112 -to VD[07] +set_location_assignment PIN_19 -to /RESET +set_location_assignment PIN_179 -to MD15 +set_location_assignment PIN_179 -to MD[15] +set_location_assignment PIN_187 -to MD14 +set_location_assignment PIN_187 -to MD[14] +set_location_assignment PIN_192 -to MD12 +set_location_assignment PIN_192 -to MD[12] +set_location_assignment PIN_198 -to MD11 +set_location_assignment PIN_198 -to MD[11] +set_location_assignment PIN_204 -to MD10 +set_location_assignment PIN_204 -to MD[10] +set_location_assignment PIN_208 -to MD9 +set_location_assignment PIN_208 -to MD[9] +set_location_assignment PIN_8 -to MD8 +set_location_assignment PIN_8 -to MD[8] +set_location_assignment PIN_161 -to MD7 +set_location_assignment PIN_161 -to MD[7] +set_location_assignment PIN_162 -to MD6 +set_location_assignment PIN_162 -to MD[6] +set_location_assignment PIN_163 -to MD5 +set_location_assignment PIN_163 -to MD[5] +set_location_assignment PIN_164 -to MD4 +set_location_assignment PIN_164 -to MD[4] +set_location_assignment PIN_186 -to MD3 +set_location_assignment PIN_186 -to MD[3] +set_location_assignment PIN_190 -to MD2 +set_location_assignment PIN_190 -to MD[2] +set_location_assignment PIN_193 -to MD1 +set_location_assignment PIN_193 -to MD[1] +set_location_assignment PIN_196 -to MD0 +set_location_assignment PIN_196 -to MD[0] +set_location_assignment PIN_61 -to D7 +set_location_assignment PIN_61 -to D[7] +set_location_assignment PIN_60 -to D6 +set_location_assignment PIN_60 -to D[6] +set_location_assignment PIN_58 -to D5 +set_location_assignment PIN_58 -to D[5] +set_location_assignment PIN_57 -to D4 +set_location_assignment PIN_57 -to D[4] +set_location_assignment PIN_56 -to D3 +set_location_assignment PIN_56 -to D[3] +set_location_assignment PIN_55 -to D2 +set_location_assignment PIN_55 -to D[2] +set_location_assignment PIN_54 -to D1 +set_location_assignment PIN_54 -to D[1] +set_location_assignment PIN_53 -to D0 +set_location_assignment PIN_53 -to D[0] +set_location_assignment PIN_169 -to XACS +set_location_assignment PIN_11 -to WR_DWG +set_location_assignment PIN_157 -to WR_COL +set_location_assignment PIN_176 -to WR_AWG +set_location_assignment PIN_16 -to /WE +set_location_assignment PIN_88 -to V_WR3 +set_location_assignment PIN_88 -to V_WR[3] +set_location_assignment PIN_75 -to V_WR2 +set_location_assignment PIN_75 -to V_WR[2] +set_location_assignment PIN_85 -to V_WR1 +set_location_assignment PIN_85 -to V_WR[1] +set_location_assignment PIN_83 -to V_WR0 +set_location_assignment PIN_83 -to V_WR[0] +set_location_assignment PIN_101 -to V_CS0 +set_location_assignment PIN_101 -to V_CS[0] +set_location_assignment PIN_70 -to V_CS1 +set_location_assignment PIN_70 -to V_CS[1] +set_location_assignment PIN_71 -to VA15 +set_location_assignment PIN_71 -to VA[15] +set_location_assignment PIN_73 -to VA14 +set_location_assignment PIN_73 -to VA[14] +set_location_assignment PIN_87 -to VA13 +set_location_assignment PIN_87 -to VA[13] +set_location_assignment PIN_74 -to VA12 +set_location_assignment PIN_74 -to VA[12] +set_location_assignment PIN_95 -to VA11 +set_location_assignment PIN_95 -to VA[11] +set_location_assignment PIN_99 -to VA10 +set_location_assignment PIN_99 -to VA[10] +set_location_assignment PIN_93 -to VA9 +set_location_assignment PIN_93 -to VA[9] +set_location_assignment PIN_94 -to VA4 +set_location_assignment PIN_94 -to VA[4] +set_location_assignment PIN_92 -to VA5 +set_location_assignment PIN_92 -to VA[5] +set_location_assignment PIN_90 -to VA8 +set_location_assignment PIN_90 -to VA[8] +set_location_assignment PIN_86 -to VA7 +set_location_assignment PIN_86 -to VA[7] +set_location_assignment PIN_89 -to VA6 +set_location_assignment PIN_89 -to VA[6] +set_location_assignment PIN_96 -to VA3 +set_location_assignment PIN_96 -to VA[3] +set_location_assignment PIN_97 -to VA2 +set_location_assignment PIN_97 -to VA[2] +set_location_assignment PIN_100 -to VA1 +set_location_assignment PIN_100 -to VA[1] +set_location_assignment PIN_102 -to VA0 +set_location_assignment PIN_102 -to VA[0] +set_location_assignment PIN_7 -to SXA +set_location_assignment PIN_173 -to RDXA +set_location_assignment PIN_10 -to RD_KMPS +set_location_assignment PIN_67 -to RA17 +set_location_assignment PIN_67 -to RA[17] +set_location_assignment PIN_68 -to RA16 +set_location_assignment PIN_68 -to RA[16] +set_location_assignment PIN_69 -to RA15 +set_location_assignment PIN_69 -to RA[15] +set_location_assignment PIN_65 -to RA14 +set_location_assignment PIN_65 -to RA[14] +set_location_assignment PIN_205 -to RAS_1 +set_location_assignment PIN_205 -to RAS_[1] +set_location_assignment PIN_207 -to RAS_0 +set_location_assignment PIN_207 -to RAS_[0] +set_location_assignment PIN_191 -to MA14 +set_location_assignment PIN_191 -to MA[14] +set_location_assignment PIN_195 -to MA13 +set_location_assignment PIN_195 -to MA[13] +set_location_assignment PIN_206 -to MA12 +set_location_assignment PIN_206 -to MA[12] +set_location_assignment PIN_199 -to MA11 +set_location_assignment PIN_199 -to MA[11] +set_location_assignment PIN_177 -to MA10 +set_location_assignment PIN_177 -to MA[10] +set_location_assignment PIN_203 -to MA9 +set_location_assignment PIN_203 -to MA[9] +set_location_assignment PIN_202 -to MA8 +set_location_assignment PIN_202 -to MA[8] +set_location_assignment PIN_197 -to MA7 +set_location_assignment PIN_197 -to MA[7] +set_location_assignment PIN_175 -to MA6 +set_location_assignment PIN_175 -to MA[6] +set_location_assignment PIN_174 -to MA5 +set_location_assignment PIN_174 -to MA[5] +set_location_assignment PIN_172 -to MA4 +set_location_assignment PIN_172 -to MA[4] +set_location_assignment PIN_170 -to MA3 +set_location_assignment PIN_170 -to MA[3] +set_location_assignment PIN_168 -to MA2 +set_location_assignment PIN_168 -to MA[2] +set_location_assignment PIN_167 -to MA1 +set_location_assignment PIN_167 -to MA[1] +set_location_assignment PIN_166 -to MA0 +set_location_assignment PIN_166 -to MA[0] +set_location_assignment PIN_159 -to DAC_WS +set_location_assignment PIN_158 -to DAC_DATA +set_location_assignment PIN_160 -to DAC_BCK +set_location_assignment PIN_64 -to CS_CASH +set_location_assignment PIN_63 -to CS_ROM +set_location_assignment PIN_62 -to CLKZ1 +set_location_assignment PIN_62 -to CLKZ[1] +set_location_assignment PIN_15 -to CAS_3 +set_location_assignment PIN_15 -to CAS_[3] +set_location_assignment PIN_13 -to CAS_2 +set_location_assignment PIN_13 -to CAS_[2] +set_location_assignment PIN_14 -to CAS_1 +set_location_assignment PIN_14 -to CAS_[1] +set_location_assignment PIN_12 -to CAS_0 +set_location_assignment PIN_12 -to CAS_[0] +set_location_assignment PIN_18 -to /WAIT +set_location_assignment PIN_25 -to /RF +set_location_assignment PIN_24 -to /M1 +set_location_assignment PIN_24 -to /M[1] +set_location_assignment PIN_79 -to /WR +set_location_assignment PIN_183 -to TG42 +set_location_assignment PIN_183 -to TG[42] +set_location_assignment PIN_80 -to /RD +set_location_assignment PIN_78 -to /IO +set_location_assignment PIN_184 -to /MR +set_location_assignment PIN_182 -to /HALT +set_location_assignment PIN_47 -to A15 +set_location_assignment PIN_47 -to A[15] +set_location_assignment PIN_46 -to A14 +set_location_assignment PIN_46 -to A[14] +set_location_assignment PIN_45 -to A13 +set_location_assignment PIN_45 -to A[13] +set_location_assignment PIN_44 -to A12 +set_location_assignment PIN_44 -to A[12] +set_location_assignment PIN_41 -to A11 +set_location_assignment PIN_41 -to A[11] +set_location_assignment PIN_40 -to A10 +set_location_assignment PIN_40 -to A[10] +set_location_assignment PIN_39 -to A9 +set_location_assignment PIN_39 -to A[9] +set_location_assignment PIN_38 -to A8 +set_location_assignment PIN_38 -to A[8] +set_location_assignment PIN_37 -to A7 +set_location_assignment PIN_37 -to A[7] +set_location_assignment PIN_36 -to A6 +set_location_assignment PIN_36 -to A[6] +set_location_assignment PIN_31 -to A5 +set_location_assignment PIN_31 -to A[5] +set_location_assignment PIN_30 -to A4 +set_location_assignment PIN_30 -to A[4] +set_location_assignment PIN_29 -to A3 +set_location_assignment PIN_29 -to A[3] +set_location_assignment PIN_28 -to A2 +set_location_assignment PIN_28 -to A[2] +set_location_assignment PIN_27 -to A1 +set_location_assignment PIN_27 -to A[1] +set_location_assignment PIN_26 -to A0 +set_location_assignment PIN_26 -to A[0] +set_location_assignment PIN_189 -to MD13 +set_location_assignment PIN_189 -to MD[13] +set_global_assignment -name FMAX_REQUIREMENT "100 MHz" +set_global_assignment -name CUT_OFF_CLEAR_AND_PRESET_PATHS ON +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK ON +set_instance_assignment -name SLOW_SLEW_RATE ON -to /wait -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to wr_dwg -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to wr_dwg -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to wr_dwg -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to wr_dwg -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RDXA -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to RDXA -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SXA -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SXA -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD00 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD00 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[00] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[00] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD01 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD01 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[01] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[01] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD02 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD02 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[02] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[02] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD03 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD03 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[03] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[03] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD04 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD04 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[04] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[04] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD05 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD05 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[05] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[05] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD06 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD06 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[06] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[06] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD07 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD07 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[07] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[07] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD10 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD10 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[10] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[10] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD11 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD11 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[11] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[11] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD12 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD12 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[12] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[12] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD13 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD13 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[13] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[13] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD14 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD14 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[14] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[14] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD15 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD15 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[15] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[15] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD16 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD16 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[16] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[16] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD17 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD17 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[17] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[17] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD20 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD20 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[20] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[20] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD21 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD21 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[21] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[21] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD22 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD22 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[22] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[22] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD23 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD23 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[23] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[23] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD24 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD24 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[24] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[24] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD25 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD25 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[25] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[25] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD26 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD26 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[26] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[26] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD27 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD27 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[27] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[27] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD30 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD30 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[30] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[30] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD31 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD31 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[31] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[31] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD32 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD32 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[32] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[32] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD33 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD33 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[33] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[33] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD34 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD34 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[34] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[34] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD35 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD35 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[35] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[35] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD36 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD36 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[36] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[36] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD37 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD37 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[37] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VD[37] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to RAS_0 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to RAS_0 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to RAS_[0] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to RAS_[0] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to RAS_1 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to RAS_1 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to RAS_[1] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to RAS_[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_0 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_0 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_[0] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to CAS_0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to CAS_[0] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_1 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_1 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_[1] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to CAS_1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to CAS_[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_2 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_2 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_[2] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_[2] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to CAS_2 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to CAS_[2] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_3 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_3 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_[3] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CAS_[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to CAS_3 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to CAS_[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to RAS_0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to RAS_[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to RAS_1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to RAS_[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XACS -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XACS -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /wr -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /wr -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /WE -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /WE -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /wait -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /wait -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA0 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA0 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[0] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[0] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA1 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA1 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[1] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA2 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA2 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[2] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[2] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA3 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA3 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[3] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[3] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA4 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA4 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[4] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[4] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA5 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA5 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[5] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[5] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA6 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA6 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[6] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[6] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA7 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA7 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[7] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[7] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA8 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA8 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[8] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[8] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA9 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA9 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[9] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[9] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA10 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA10 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[10] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[10] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA11 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA11 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[11] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[11] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA12 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA12 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[12] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[12] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA13 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA13 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[13] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[13] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA14 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA14 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[14] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[14] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA15 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA15 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[15] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to VA[15] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /rf -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /rf -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /reset -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /reset -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /rd -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /rd -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra14 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra14 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra[14] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra[14] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ra14 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ra[14] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra15 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra15 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra[15] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra[15] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ra15 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ra[15] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra16 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra16 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra[16] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra[16] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ra16 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ra[16] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra17 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra17 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra[17] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ra[17] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ra17 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ra[17] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /mr -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /mr -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /m1 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /m1 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /m[1] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /m[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma12 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma12 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[12] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[12] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma13 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma13 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[13] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[13] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma14 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma14 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[14] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[14] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma0 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma0 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[0] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[0] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma1 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma1 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[1] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma2 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma2 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[2] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[2] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma3 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma3 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[3] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[3] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma4 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma4 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[4] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[4] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma5 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma5 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[5] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[5] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma6 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma6 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[6] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[6] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma7 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma7 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[7] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[7] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma8 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma8 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[8] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[8] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma9 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma9 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[9] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[9] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma10 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma10 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[10] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[10] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma11 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma11 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[11] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to ma[11] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /io -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /io -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /HALT -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to /HALT -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d0 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d0 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[0] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[0] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d1 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d1 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[1] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d2 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d2 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[2] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[2] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d3 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d3 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[3] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[3] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d4 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d4 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[4] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[4] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d5 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d5 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[5] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[5] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d6 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d6 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[6] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[6] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d7 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d7 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[7] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to d[7] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to CS_CASH -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CS_CASH -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to CS_CASH -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to CS_CASH -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to cs_rom -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to cs_rom -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to cs_rom -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to cs_rom -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a0 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a0 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[0] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[0] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a1 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a1 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[1] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a2 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a2 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[2] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[2] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a3 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a3 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[3] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[3] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a4 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a4 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[4] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[4] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a5 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a5 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[5] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[5] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a6 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a6 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[6] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[6] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a7 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a7 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[7] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[7] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A8 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A8 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[8] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[8] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a9 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a9 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[9] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[9] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A10 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A10 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[10] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[10] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a11 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a11 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[11] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to a[11] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A12 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A12 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[12] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[12] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A13 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A13 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[13] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[13] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A14 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A14 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[14] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[14] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A15 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A15 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[15] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to A[15] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md0 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md0 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[0] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[0] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md1 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md1 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[1] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md2 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md2 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[2] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[2] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md3 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md3 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[3] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[3] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md4 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md4 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[4] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[4] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md5 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md5 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[5] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[5] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md6 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md6 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[6] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[6] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md7 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md7 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[7] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[7] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md8 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md8 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[8] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[8] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md9 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md9 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[9] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[9] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md10 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md10 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[10] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[10] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md11 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md11 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[11] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[11] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md12 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md12 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[12] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[12] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md13 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md13 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[13] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[13] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md14 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md14 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[14] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[14] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md15 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md15 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[15] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to md[15] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to wr_awg -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA0 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA0 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA[0] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA[0] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA1 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA1 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA[1] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA[1] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA2 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA2 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA[2] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA[2] -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA3 -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA3 -entity sp2_acex +set_instance_assignment -name FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA[3] -entity sp2_acex +set_instance_assignment -name FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS OFF -to XA[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma2 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[2] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma3 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma4 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[4] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma5 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[5] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma6 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[6] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma7 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[7] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma8 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[8] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma9 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[9] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma10 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[10] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma11 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[11] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD00 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[00] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD01 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[01] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD02 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[02] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD03 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[03] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD04 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[04] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD05 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[05] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD06 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[06] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD07 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[07] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD10 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[10] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD11 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[11] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD12 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[12] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD13 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[13] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD14 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[14] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD15 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[15] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD16 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[16] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD17 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[17] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD20 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[20] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD21 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[21] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD22 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[22] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD23 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[23] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD24 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[24] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD25 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[25] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD26 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[26] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD27 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[27] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD30 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[30] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD31 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[31] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD32 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[32] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD33 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[33] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD34 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[34] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD35 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[35] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD36 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[36] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD37 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to VD[37] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[0] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA2 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[2] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA3 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[3] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA4 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[4] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA6 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[6] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA5 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[5] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA7 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[7] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA8 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[8] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA9 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[9] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA10 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[10] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA11 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[11] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA12 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[12] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA13 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[13] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA14 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[14] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA15 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VA[15] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD00 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[00] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD01 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[01] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD02 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[02] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD03 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[03] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD04 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[04] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD05 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[05] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD06 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[06] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD07 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[07] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD10 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[10] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD11 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[11] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD12 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[12] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD13 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[13] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD14 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[14] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD15 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[15] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD16 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[16] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD17 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[17] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD20 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[20] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD21 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[21] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD22 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[22] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD23 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[23] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD24 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[24] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD25 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[25] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD26 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[26] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD27 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[27] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD30 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[30] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD31 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[31] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD32 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[32] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD33 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[33] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD34 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[34] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD35 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[35] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD36 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[36] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD37 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to VD[37] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to WR_COL -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA2 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[2] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA3 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA4 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[4] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA5 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[5] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA6 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[6] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA7 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[7] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA8 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[8] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA9 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[9] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA10 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[10] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA11 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[11] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA12 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[12] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA13 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[13] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA14 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[14] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA15 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to VA[15] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to V_WR0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to V_WR[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to V_WR1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to V_WR[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to V_WR2 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to V_WR[2] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to V_WR3 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to V_WR[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to XA0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to XA[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to XA1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to XA[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to XA2 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to XA[2] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to XA3 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to XA[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to XACS -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /wait -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to SXA -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /rf -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /reset -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to RDXA -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /rd -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /m1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /m[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /mr -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /io -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /HALT -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to /WE -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to /WE -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to RAS_0 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to RAS_[0] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to RAS_1 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to RAS_[1] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to CAS_0 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to CAS_[0] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to CAS_1 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to CAS_[1] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to CAS_2 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to CAS_[2] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to CAS_3 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to CAS_[3] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[0] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma1 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma1 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[1] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[1] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma2 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma2 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[2] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[2] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma3 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma3 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[3] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[3] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma4 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma4 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[4] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[4] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma5 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma5 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[5] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[5] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma6 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma6 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[6] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[6] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma7 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma7 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[7] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[7] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma8 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma8 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[8] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[8] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma9 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma9 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[9] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[9] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma10 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma10 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[10] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[10] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma11 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma11 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[11] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[11] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma2 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[2] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma3 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[3] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma4 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[4] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma5 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[5] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma6 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[6] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma7 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[7] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma8 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[8] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma9 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[9] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma10 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[10] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma11 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[11] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma12 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[12] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma12 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[12] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma13 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[13] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma13 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[13] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma14 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ma[14] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma14 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ma[14] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to SXA -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to RDXA -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to RDXA -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to /mr -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to /m1 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to /m[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to /rd -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to wr_awg -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to wr_awg -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ra14 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ra[14] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ra14 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ra[14] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ra15 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ra[15] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ra15 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ra[15] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ra16 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ra[16] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ra16 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ra[16] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ra17 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to ra[17] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ra17 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to ra[17] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to CS_CASH -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to cs_rom -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /WE -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to RAS_0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to RAS_[0] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to RAS_1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to RAS_[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to CAS_0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to CAS_[0] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to CAS_1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to CAS_[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to CAS_2 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to CAS_[2] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to CAS_3 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to CAS_[3] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to V_WR0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to V_WR[0] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to V_WR1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to V_WR[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to V_WR2 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to V_WR[2] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to V_WR3 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to V_WR[3] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to v_cs0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to v_cs[0] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to v_cs1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to v_cs[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to XACS -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to /wr -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to XA0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to XA[0] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to XA1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to XA[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to XA2 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to XA[2] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to XA3 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to XA[3] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to TG42 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to TG[42] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d[0] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d2 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d[2] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d3 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d[3] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d4 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d[4] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d5 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d[5] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d6 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d[6] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d7 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to d[7] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[0] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md2 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[2] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md3 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[3] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md4 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[4] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md5 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[5] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md6 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[6] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md7 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[7] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md8 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[8] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md9 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[9] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md10 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[10] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md11 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[11] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md12 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[12] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md13 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[13] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md14 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[14] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md15 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to md[15] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a0 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[0] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a1 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[1] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a2 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[2] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a3 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[3] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a4 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[4] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a5 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[5] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a6 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[6] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A8 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A[8] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a7 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[7] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A10 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A[10] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a9 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[9] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a11 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to a[11] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A12 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A[12] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A13 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A[13] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A14 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A[14] -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A15 -entity sp2_acex +set_instance_assignment -name PCI_IO OFF -to A[15] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to /reset -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to /rf -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a2 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[2] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a3 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a4 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[4] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a5 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[5] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a6 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[6] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a7 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[7] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a8 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[8] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a9 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[9] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a10 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[10] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a11 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to a[11] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to A12 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to A[12] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to A13 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to A[13] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to A14 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to A[14] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to A15 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to A[15] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to /mr -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to /m1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to /m[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to /HALT -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to /io -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d2 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d[2] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d3 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d4 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d[4] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d5 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d[5] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d6 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d[6] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d7 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to d[7] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to DAC_BCK -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to DAC_DATA -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to DAC_WS -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to WR_COL -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to WR_COL -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to WR_COL -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to v_cs0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to v_cs[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to v_cs1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to v_cs[1] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma0 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma0 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ma[0] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to ma[0] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma0 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[0] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma1 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[1] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma2 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[2] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma3 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[3] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma4 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[4] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma5 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[5] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma6 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[6] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma7 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[7] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma8 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[8] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma9 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[9] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma10 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[10] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma11 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[11] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma12 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[12] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma13 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[13] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma14 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to ma[14] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md0 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[0] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md0 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[0] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md1 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[1] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[1] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md2 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[2] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md2 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[2] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md3 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[3] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md3 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[3] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md4 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[4] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md4 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[4] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md5 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[5] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md5 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[5] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md6 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[6] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md6 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[6] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md7 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[7] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md7 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[7] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md8 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[8] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md8 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[8] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md9 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[9] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md9 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[9] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md10 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[10] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md10 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[10] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md11 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[11] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md11 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[11] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md12 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[12] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md12 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[12] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md13 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[13] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md13 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[13] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md14 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[14] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md14 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[14] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md15 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to md[15] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md15 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE ON -to md[15] -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA12" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA[12]" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA11" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA[11]" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA10" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA[10]" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA0" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA[0]" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA1" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA[1]" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA2" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA[2]" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA3" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA[3]" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA4" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA[4]" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA5" -entity sp2_acex +set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "video2:SVIDEO|SVA[5]" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to v_cs0 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to v_cs[0] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to v_cs1 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to v_cs[1] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD00 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[00] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD01 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[01] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD02 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[02] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD03 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[03] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD04 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[04] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD05 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[05] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD06 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[06] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD07 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[07] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD10 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[10] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD11 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[11] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD12 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[12] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD13 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[13] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD14 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[14] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD15 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[15] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD16 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[16] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD17 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[17] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD20 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[20] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD21 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[21] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD22 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[22] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD23 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[23] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD24 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[24] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD25 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[25] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD26 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[26] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD27 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[27] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD30 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[30] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD31 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[31] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD32 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[32] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD33 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[33] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD34 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[34] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD35 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[35] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD36 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[36] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD37 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VD[37] -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to CLKZ1 -entity sp2_acex +set_instance_assignment -name SLOW_SLEW_RATE OFF -to CLKZ[1] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC00" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC[00]" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC01" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC[01]" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC02" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC[02]" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC03" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC[03]" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC04" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC[04]" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC05" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC[05]" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC06" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC[06]" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC07" -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to "video2:SVIDEO|D_PIC[07]" -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA0 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA0 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[0] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[0] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA1 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA1 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[1] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[1] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA2 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA2 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[2] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[2] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA3 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA3 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[3] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[3] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA4 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA4 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[4] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[4] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA5 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA5 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[5] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[5] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA6 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA6 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[6] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[6] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA7 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA7 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[7] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[7] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA8 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA8 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[8] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[8] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA9 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA9 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[9] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[9] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA10 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA10 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[10] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[10] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA11 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA11 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[11] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[11] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA12 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA12 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[12] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[12] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA13 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA13 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[13] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[13] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA14 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA14 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[14] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[14] -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA15 -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA15 -entity sp2_acex +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VA[15] -entity sp2_acex +set_instance_assignment -name FAST_INPUT_REGISTER ON -to VA[15] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to V_WR0 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to V_WR[0] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to V_WR1 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to V_WR[1] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to V_WR2 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to V_WR[2] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to V_WR3 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to V_WR[3] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA0 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[0] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA1 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[1] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA2 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[2] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA3 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[3] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA4 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[4] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA5 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[5] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA6 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[6] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA7 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[7] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA8 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[8] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA9 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[9] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA10 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[10] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA11 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[11] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA12 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[12] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA13 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[13] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA14 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[14] -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA15 -entity sp2_acex +set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL OFF -to VA[15] -entity sp2_acex +set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD LVTTL/LVCMOS +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE OFF +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES ON +set_global_assignment -name AUTO_RESTART_CONFIGURATION ON +set_global_assignment -name ENABLE_VREFB_PIN OFF +set_global_assignment -name ENABLE_VREFA_PIN OFF +set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V +set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE OFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE OFF +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT OFF +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT OFF +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF +set_global_assignment -name ENABLE_DEVICE_WIDE_OE OFF +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET OFF +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name USER_START_UP_CLOCK OFF +set_global_assignment -name SECURITY_BIT OFF +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM OFF +set_global_assignment -name AUTO_OPEN_DRAIN_PINS ON +set_global_assignment -name STATE_MACHINE_PROCESSING AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS OFF +set_global_assignment -name AUTO_FAST_INPUT_REGISTERS OFF +set_global_assignment -name AUTO_FAST_OUTPUT_REGISTERS OFF +set_global_assignment -name AUTO_GLOBAL_OE ON +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS ON +set_global_assignment -name AUTO_GLOBAL_CLOCK ON +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name SAVE_DISK_SPACE ON +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES OFF -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis +set_global_assignment -name END_TIME "12 us" +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "0 ns" +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF +set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10 +set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN "0 ns" +set_global_assignment -name AUTO_LCELL_INSERTION ON -entity sp2_acex \ No newline at end of file diff --git a/src/altera/quartus/acex/SP2_ACEX.qws b/src/altera/quartus/acex/SP2_ACEX.qws new file mode 100644 index 0000000..f0c6eaa --- /dev/null +++ b/src/altera/quartus/acex/SP2_ACEX.qws @@ -0,0 +1,18 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 +[ProjectWorkspace.Frames.ChildFrames.Document-2] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0] +DocPathName=KBD_INI2.MIF +DocumentCLSID={0b720e69-67da-11d0-bf4f-0000c08cb0c0} +IsChildFrameDetached=False +IsActiveChildFrame=True +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap] +AFC_IN_REPORT=False diff --git a/src/altera/quartus/acex/VIDEO2.ACF b/src/altera/quartus/acex/VIDEO2.ACF new file mode 100644 index 0000000..57d4f1c --- /dev/null +++ b/src/altera/quartus/acex/VIDEO2.ACF @@ -0,0 +1,588 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP video2 +BEGIN + DEVICE = AUTO; +END; + +DEFAULT_DEVICES +BEGIN + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; + AUTO_DEVICE = EP1K30TC144-1; + AUTO_DEVICE = EP1K30QC208-1; + AUTO_DEVICE = EP1K30FC256-1; + AUTO_DEVICE = EP1K50TC144-1; + AUTO_DEVICE = EP1K50QC208-1; + AUTO_DEVICE = EP1K50FC256-1; + AUTO_DEVICE = EP1K50FC484-1; + AUTO_DEVICE = EP1K100QC208-1; + AUTO_DEVICE = EP1K100FC256-1; + AUTO_DEVICE = EP1K100FC484-1; +END; + +TIMING_POINT +BEGIN + MAINTAIN_STABLE_SYNTHESIS = ON; + DEVICE_FOR_TIMING_SYNTHESIS = EP1K30FC256-3; + CUT_ALL_BIDIR = ON; + CUT_ALL_CLEAR_PRESET = ON; + FREQUENCY = 200MHz; +END; + +IGNORED_ASSIGNMENTS +BEGIN + IGNORE_CLIQUE_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + FIT_IGNORE_TIMING = OFF; +END; + +LOGIC_OPTIONS +BEGIN + |VAO15 : FAST_IO = ON; + |VAO14 : FAST_IO = ON; + |VAO13 : FAST_IO = ON; + |VAO12 : FAST_IO = ON; + |VAO11 : FAST_IO = ON; + |VAO10 : FAST_IO = ON; + |VAO9 : FAST_IO = ON; + |VAO8 : FAST_IO = ON; + |VAO7 : FAST_IO = ON; + |VAO6 : FAST_IO = ON; + |VAO5 : FAST_IO = ON; + |VAO4 : FAST_IO = ON; + |VAO3 : FAST_IO = ON; + |VAO2 : FAST_IO = ON; + |VAO1 : FAST_IO = ON; + |VAO0 : FAST_IO = ON; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + RESERVED_LCELLS_PERCENT = 0; + RESERVED_PINS_PERCENT = 0; + SECURITY_BIT = OFF; + USER_CLOCK = OFF; + AUTO_RESTART = OFF; + RELEASE_CLEARS = OFF; + ENABLE_DCLK_OUTPUT = OFF; + DISABLE_TIME_OUT = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + FLEX8000_ENABLE_JTAG = OFF; + DATA0 = RESERVED_TRI_STATED; + DATA1_TO_DATA7 = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + RDYnBUSY = UNRESERVED; + RDCLK = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + ADD0_TO_ADD12 = UNRESERVED; + ADD13 = UNRESERVED; + ADD14 = UNRESERVED; + ADD15 = UNRESERVED; + ADD16 = UNRESERVED; + ADD17 = UNRESERVED; + CLKUSR = UNRESERVED; + nCEO = UNRESERVED; + ENABLE_CHIP_WIDE_RESET = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_INIT_DONE_OUTPUT = OFF; + FLEX10K_JTAG_USER_CODE = 7F; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + MAX7000S_USER_CODE = FFFF; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_ENABLE_JTAG = ON; + MULTIVOLT_IO = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + FLEX6000_ENABLE_JTAG = OFF; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + MAX7000AE_USER_CODE = FFFFFFFF; + MAX7000AE_ENABLE_JTAG = ON; + FLEX_CONFIGURATION_EPROM = AUTO; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_ENABLE_VREFB = OFF; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + OPTIMIZE_FOR_SPEED = 5; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; + AUTO_GLOBAL_CLOCK = ON; + AUTO_GLOBAL_CLEAR = ON; + AUTO_GLOBAL_PRESET = ON; + AUTO_GLOBAL_OE = ON; + AUTO_FAST_IO = OFF; + DEVICE_FAMILY = ACEX1K; + AUTO_REGISTER_PACKING = OFF; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + STYLE = FAST; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + USE_QUARTUS_FITTER = ON; + DESIGN_DOCTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + TIMING_SNF_EXTRACTOR = ON; + OPTIMIZE_TIMING_SNF = OFF; + LINKED_SNF_EXTRACTOR = OFF; + RPT_FILE_EQUATIONS = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_USER_ASSIGNMENTS = ON; + GENERATE_AHDL_TDO_FILE = OFF; + SMART_RECOMPILE = OFF; + FITTER_SETTINGS = NORMAL; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + EDIF_NETLIST_WRITER = OFF; + EDIF_OUTPUT_VERSION = 200; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_GENERATE_AHDL_TDX_FILE = ON; + VERILOG_NETLIST_WRITER = OFF; + VHDL_NETLIST_WRITER = OFF; + USE_SYNOPSYS_SYNTHESIS = OFF; + SYNOPSYS_COMPILER = DESIGN; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + VHDL_READER_VERSION = VHDL87; + VHDL_WRITER_VERSION = VHDL87; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_FLATTEN_BUS = OFF; + VHDL_FLATTEN_BUS = OFF; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + EDIF_INPUT_LMF1 = *.lmf; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_OUTPUT_GND = GND; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_FLATTEN_BUS = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + RIPPLE_CLOCKS = ON; + GATED_CLOCKS = ON; + MULTI_LEVEL_CLOCKS = ON; + MULTI_CLOCK_NETWORKS = ON; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + PRESET_CLEAR_NETWORKS = ON; + ASYNCHRONOUS_INPUTS = ON; + DELAY_CHAINS = ON; + RACE_CONDITIONS = ON; + EXPANDER_NETWORKS = ON; + MASTER_RESET = OFF; +END; + +SIMULATOR_CONFIGURATION +BEGIN + CHECK_OUTPUTS = OFF; + USE_DEVICE = OFF; + SETUP_HOLD = OFF; + OSCILLATION = OFF; + OSCILLATION_TIME = 0.0ns; + GLITCH = OFF; + GLITCH_TIME = 0.0ns; + START_TIME = 0.0ns; + BIDIR_PIN = STRONG; + END_TIME = 10.0us; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + ANALYSIS_MODE = REGISTERED_PERFORMANCE; + AUTO_RECALCULATE = OFF; + CUT_OFF_IO_PIN_FEEDBACK = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + LIST_ONLY_LONGEST_PATH = ON; + CELL_WIDTH = 18; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + INCLUDE_PATHS_GREATER_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + LIST_PATH_COUNT = 10; + LIST_PATH_FREQUENCY = 10MHz; + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; +END; + +OTHER_CONFIGURATION +BEGIN + LAST_MAXPLUS2_VERSION = 10.0; + EXPLICIT_FAMILY = 1; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; + ORIGINAL_MAXPLUS2_VERSION = 9.6; + ROW_PINS_PERCENT = 50; + EXP_PER_LCELL_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + LCELLS_PER_ROW_PERCENT = 100; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + FLEX_10K_52_COLUMNS = 40; + NORMAL_LCELL_INSERT = ON; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + ROW_PINS_LCELL_INSERT = ON; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + CASCADE_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CARRY_CHAIN_LENGTH = -1; + MINIMIZATION = FULL; + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = ON; + TURBO_BIT = OFF; + PARALLEL_EXPANDERS = OFF; + IGNORE_SOFT_BUFFERS = OFF; + FAST_IO = OFF; + SOFT_BUFFER_INSERTION = ON; + DECOMPOSE_GATES = ON; + REDUCE_LOGIC = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = ON; + SUBFACTOR_EXTRACTION = ON; + MULTI_LEVEL_FACTORING = ON; + RESYNTHESIZE_NETWORK = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + REGISTER_OPTIMIZATION = ON; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + CASCADE_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CARRY_CHAIN_LENGTH = -1; + MINIMIZATION = FULL; + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = ON; + TURBO_BIT = ON; + PARALLEL_EXPANDERS = OFF; + IGNORE_SOFT_BUFFERS = OFF; + FAST_IO = OFF; + SOFT_BUFFER_INSERTION = ON; + DECOMPOSE_GATES = ON; + REDUCE_LOGIC = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = ON; + SUBFACTOR_EXTRACTION = ON; + MULTI_LEVEL_FACTORING = ON; + RESYNTHESIZE_NETWORK = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + REGISTER_OPTIMIZATION = ON; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + CASCADE_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CARRY_CHAIN_LENGTH = -1; + MINIMIZATION = FULL; + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = OFF; + TURBO_BIT = ON; + PARALLEL_EXPANDERS = OFF; + IGNORE_SOFT_BUFFERS = OFF; + FAST_IO = OFF; + SOFT_BUFFER_INSERTION = ON; + DECOMPOSE_GATES = ON; + REDUCE_LOGIC = OFF; + DUPLICATE_LOGIC_EXTRACTION = OFF; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = OFF; + SUBFACTOR_EXTRACTION = OFF; + MULTI_LEVEL_FACTORING = OFF; + RESYNTHESIZE_NETWORK = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + REGISTER_OPTIMIZATION = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + CASCADE_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = 2; + CARRY_CHAIN = IGNORE; + CARRY_CHAIN_LENGTH = 32; + MINIMIZATION = FULL; + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = OFF; + TURBO_BIT = OFF; + PARALLEL_EXPANDERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + SOFT_BUFFER_INSERTION = ON; + DECOMPOSE_GATES = ON; + REDUCE_LOGIC = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = ON; + SUBFACTOR_EXTRACTION = ON; + MULTI_LEVEL_FACTORING = ON; + RESYNTHESIZE_NETWORK = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + REGISTER_OPTIMIZATION = ON; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = ON; + TURBO_BIT = OFF; + PARALLEL_EXPANDERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + IGNORE_SOFT_BUFFERS = OFF; + FAST_IO = OFF; + MINIMIZATION = FULL; + CASCADE_CHAIN = IGNORE; + CARRY_CHAIN = IGNORE; + SOFT_BUFFER_INSERTION = ON; + DECOMPOSE_GATES = ON; + REDUCE_LOGIC = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = OFF; + SUBFACTOR_EXTRACTION = OFF; + MULTI_LEVEL_FACTORING = ON; + RESYNTHESIZE_NETWORK = ON; + REGISTER_OPTIMIZATION = ON; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = ON; + TURBO_BIT = ON; + PARALLEL_EXPANDERS = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + IGNORE_SOFT_BUFFERS = OFF; + FAST_IO = OFF; + MINIMIZATION = FULL; + CASCADE_CHAIN = IGNORE; + CARRY_CHAIN = IGNORE; + SOFT_BUFFER_INSERTION = ON; + DECOMPOSE_GATES = ON; + REDUCE_LOGIC = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = OFF; + SUBFACTOR_EXTRACTION = OFF; + MULTI_LEVEL_FACTORING = ON; + RESYNTHESIZE_NETWORK = ON; + REGISTER_OPTIMIZATION = ON; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = OFF; + TURBO_BIT = ON; + PARALLEL_EXPANDERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + IGNORE_SOFT_BUFFERS = OFF; + FAST_IO = OFF; + MINIMIZATION = FULL; + CASCADE_CHAIN = IGNORE; + CARRY_CHAIN = IGNORE; + SOFT_BUFFER_INSERTION = ON; + DECOMPOSE_GATES = ON; + REDUCE_LOGIC = OFF; + DUPLICATE_LOGIC_EXTRACTION = OFF; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = OFF; + SUBFACTOR_EXTRACTION = OFF; + MULTI_LEVEL_FACTORING = OFF; + RESYNTHESIZE_NETWORK = ON; + REGISTER_OPTIMIZATION = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = OFF; + TURBO_BIT = OFF; + PARALLEL_EXPANDERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + IGNORE_SOFT_BUFFERS = ON; + MINIMIZATION = FULL; + CASCADE_CHAIN = AUTO; + CARRY_CHAIN = AUTO; + SOFT_BUFFER_INSERTION = ON; + DECOMPOSE_GATES = ON; + REDUCE_LOGIC = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = ON; + SUBFACTOR_EXTRACTION = ON; + MULTI_LEVEL_FACTORING = ON; + RESYNTHESIZE_NETWORK = ON; + REGISTER_OPTIMIZATION = ON; + CASCADE_CHAIN_LENGTH = 2; + CARRY_CHAIN_LENGTH = 32; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + CASCADE_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CARRY_CHAIN_LENGTH = -1; + MINIMIZATION = PARTIAL; + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = OFF; + TURBO_BIT = OFF; + PARALLEL_EXPANDERS = OFF; + IGNORE_SOFT_BUFFERS = OFF; + FAST_IO = OFF; + SOFT_BUFFER_INSERTION = OFF; + DECOMPOSE_GATES = OFF; + REDUCE_LOGIC = OFF; + DUPLICATE_LOGIC_EXTRACTION = OFF; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = OFF; + SUBFACTOR_EXTRACTION = OFF; + MULTI_LEVEL_FACTORING = OFF; + RESYNTHESIZE_NETWORK = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + REGISTER_OPTIMIZATION = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + CASCADE_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CARRY_CHAIN_LENGTH = -1; + MINIMIZATION = PARTIAL; + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = OFF; + TURBO_BIT = ON; + PARALLEL_EXPANDERS = OFF; + IGNORE_SOFT_BUFFERS = OFF; + FAST_IO = OFF; + SOFT_BUFFER_INSERTION = OFF; + DECOMPOSE_GATES = OFF; + REDUCE_LOGIC = OFF; + DUPLICATE_LOGIC_EXTRACTION = OFF; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = OFF; + SUBFACTOR_EXTRACTION = OFF; + MULTI_LEVEL_FACTORING = OFF; + RESYNTHESIZE_NETWORK = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + REGISTER_OPTIMIZATION = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + CASCADE_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CARRY_CHAIN_LENGTH = -1; + MINIMIZATION = PARTIAL; + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = OFF; + TURBO_BIT = ON; + PARALLEL_EXPANDERS = OFF; + IGNORE_SOFT_BUFFERS = OFF; + FAST_IO = OFF; + SOFT_BUFFER_INSERTION = OFF; + DECOMPOSE_GATES = ON; + REDUCE_LOGIC = OFF; + DUPLICATE_LOGIC_EXTRACTION = OFF; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = OFF; + SUBFACTOR_EXTRACTION = OFF; + MULTI_LEVEL_FACTORING = OFF; + RESYNTHESIZE_NETWORK = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + REGISTER_OPTIMIZATION = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + CASCADE_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CARRY_CHAIN = MANUAL; + CARRY_CHAIN_LENGTH = 32; + MINIMIZATION = PARTIAL; + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = OFF; + TURBO_BIT = OFF; + PARALLEL_EXPANDERS = OFF; + IGNORE_SOFT_BUFFERS = ON; + SOFT_BUFFER_INSERTION = ON; + DECOMPOSE_GATES = OFF; + REDUCE_LOGIC = OFF; + DUPLICATE_LOGIC_EXTRACTION = OFF; + NOT_GATE_PUSH_BACK = ON; + REFACTORIZATION = OFF; + SUBFACTOR_EXTRACTION = OFF; + MULTI_LEVEL_FACTORING = OFF; + RESYNTHESIZE_NETWORK = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + REGISTER_OPTIMIZATION = OFF; +END; + diff --git a/src/altera/quartus/acex/VIDEO2.INC b/src/altera/quartus/acex/VIDEO2.INC new file mode 100644 index 0000000..1c5f796 --- /dev/null +++ b/src/altera/quartus/acex/VIDEO2.INC @@ -0,0 +1,27 @@ +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. + +-- MAX+plus II Include File +-- Version 10.0 9/14/2000 +-- Created: Mon Nov 19 00:36:42 2001 + +FUNCTION video2 (clk42, start_up, copy_sinc_h, copy_sinc_v, wr, vai[19..0], d[7..0], mdi[15..0], vdm0[7..0], vdm1[7..0], vdm2[7..0], vdm3[7..0], zx_port[7..0], dir_port[7..0], double_cas, mouse_x[9..0], mouse_y[9..0]) + WITH (MODE, MOUSE) + RETURNS (ct[5..0], cth[5..0], ctv[8..0], ctf[6..0], blank, vao[15..0], vdo0[7..0], vdo1[7..0], vdo2[7..0], vdo3[7..0], v_wr[3..0], v_wen[3..0], v_cs[1..0], wr_pix, intt); diff --git a/src/altera/quartus/acex/VIDEO2.TDF b/src/altera/quartus/acex/VIDEO2.TDF new file mode 100644 index 0000000..c5b0fc4 --- /dev/null +++ b/src/altera/quartus/acex/VIDEO2.TDF @@ -0,0 +1,692 @@ + + TITLE "Video-controller"; + +INCLUDE "lpm_ram_dp"; + +PARAMETERS + ( + MODE = "SPRINTER", + MOUSE = "NO", + HOR_PLACE = H"50", + VER_PLACE = H"91" -- 122h/2 + ); + +SUBDESIGN video2 + ( + CLK42 : INPUT; + + CT[5..0] : OUTPUT; + CTH[5..0] : OUTPUT; + CTV[8..0] : OUTPUT; + CTF[6..0] : OUTPUT; + + BLANK : OUTPUT; + + START_UP : INPUT; + COPY_SINC_H : INPUT; + COPY_SINC_V : INPUT; + + WR : INPUT; + + VAI[19..0] : INPUT; -- input screen adress + + VAO[15..0] : OUTPUT; + + D[7..0] : INPUT; + MDI[15..0] : INPUT; + + VDO0[7..0] : OUTPUT; + VDO1[7..0] : OUTPUT; + VDO2[7..0] : OUTPUT; + VDO3[7..0] : OUTPUT; + + VDM0[7..0] : INPUT; + VDM1[7..0] : INPUT; + VDM2[7..0] : INPUT; + VDM3[7..0] : INPUT; + + V_WR[3..0] : OUTPUT; + V_WEN[3..0] : OUTPUT; + + V_CS[1..0] : OUTPUT; + WR_PIX : OUTPUT; + +-- ZX_COLOR[3..0] : OUTPUT; + + ZX_PORT[7..0] : INPUT; + DIR_PORT[7..0] : INPUT; + +% + bit0 - Spectrum SCREEN Switch + bit1 - Spectrum Adress MODE + bit2 - Write to Spectrum Screen OFF + bit3 - MODE page 0/1 + bit4 - MODE on/off screen + + bit7..5 - Border +% + + INTT : OUTPUT; + + DOUBLE_CAS : INPUT; + + MOUSE_X[9..0] : INPUT; + MOUSE_Y[9..0] : INPUT; + + + ) +VARIABLE + +-- CLK84 : NODE; +-- CLK84_X : NODE; +-- CLK84_Y : NODE; + + ZX_COLOR[3..0] : NODE; + + CT[5..0] : DFFE; + CTH[5..0] : DFFE; + CTV[8..0] : DFFE; + CTF[6..0] : DFF; + + VXA[19..0] : DFFE; + + VXD0[7..0] : DFFE; + VXD1[7..0] : DFFE; + VXD2[7..0] : DFFE; + VXD3[7..0] : DFFE; + + E_WR : NODE; + E_WRD : NODE; + + BLANK : NODE; + BORD : NODE; +-- INTT_T : NODE; + INTTX : NODE; + + VLA[17..0] : DFF; +-- SVA[17..0] : NODE; + SVA[17..0] : DFF; +-- RSVA[8..0] : LCELL; + RSVA[8..0] : NODE; +-- RSVA[8..0] : DFF; + + V_CST[1..0] : DFF; + VCM[2..0] : DFF; + TSN_W3 : DFF; + V_WE : DFF; + V_WEX : DFF; + + V_WEM : NODE; + V_WEM2 : NODE; + V_WRM : NODE; + V_WRM2 : NODE; + + V_WEMM : NODE; + V_WEMMM : NODE; + V_WEMMN : NODE; + V_WEMMO : NODE; + V_WET[3..0] : DFF; + + D_PIC0[7..0] : DFFE; +-- D_PIC0_[7..0] : LCELL; + + D_PIC0_[7..0] : DFFE; + D_PIC1_[7..0] : DFFE; + D_PIC2_[7..0] : DFFE; + D_PIC3_[7..0] : DFFE; + + D_PICX_[7..0] : NODE; + + LWR_PIC : NODE; + LWR_COL : NODE; + + WR_PIC : DFF; + WR_COL : DFF; + LD_PIC : NODE; +MXL: NODE; +MXR: NODE; + + RBRVA[10..8]: DFF; + BRVA[7..0] : DFF; + DCOL[7..0] : DFFE; + + MXWE : NODE; +-- MXCE : NODE; + + AX128 : NODE; + + BRD[2..0] : NODE; + + ZX_COL[3..0] : LCELL; + + ZXA15 : NODE; + ZXS[5..0] : NODE; + ZX_SCREEN : NODE; + SCR128 : NODE; + + MODE0[7..0] : DFFE; + MODE1[7..0] : DFFE; + MODE2[7..0] : DFFE; +-- MODE3[7..0] : DFF; + + WR_MODE : DFF; + LWR_MODE : NODE; + X_MODE[7..4]: NODE; + X_MODE_BOND : NODE; + +-- M_CTV[2..0] : DFF; +-- M_CT[5..3] : DFF; + M_CTV[2..0] : LCELL; + M_CT[5..3] : LCELL; + + DOUBLE : DFFE; + + PIC_CLK : NODE; + + MS_X[9..0] : DFF; + MS_Y[9..0] : DFF; + + MS_POINT : NODE; + MS_POINT2 : NODE; + MS_PNT : NODE; + + MS_DAT : LPM_RAM_DP WITH (LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_FILE="MOUSE.MIF"); + + SCR_ENA : DFFE; + V_WR_[3..0] : LCELL; + V_WEY[3..0] : LCELL; + + V_WE_R : NODE; + + V_CSX[3..0] : NODE; + + V_EN[3..0] : NODE; + + F_WR : NODE; + +BEGIN + + DEFAULTS + WR_MODE.d = VCC; -- WR_MODE2.d = VCC; -- WR_MODE2X.d = VCC; + V_CST[].d = VCC; V_WR[] = VCC; TSN_W3.d = VCC; + V_WE.d = VCC; WR_COL.d = VCC; WR_PIC.d = VCC; + V_WET[].d = VCC; + END DEFAULTS; + + ZX_COLOR[] = ZX_COL[]; + +-- === MOUSE counters ======== + + MS_X[].clk = !CT1; + CASE LCELL(CTH[5..2] == 12) IS + WHEN 0 => MS_X[] = MS_X[] + 1; + WHEN 1 => MS_X[] = (!MOUSE_X[9..0]); + END CASE; + + MS_Y[].clk = !CTH5; + CASE LCELL(CTV8 & !CTV5 & CTV4) IS + WHEN 0 => MS_Y[] = MS_Y[] + 1; + WHEN 1 => MS_Y[] = (GND,!MOUSE_Y[8..0]); + END CASE; + + MS_PNT = DFF(((MS_X[] == B"100000XXXX") & (MS_Y[] == B"100000XXXX")),CLK42,,); + + MS_DAT.wren = GND; + MS_DAT.data[] = GND; + MS_DAT.wraddress[] = GND; + MS_DAT.wrclock = CLK42; + MS_DAT.wrclken = GND; + MS_DAT.rden = VCC; + MS_DAT.rdaddress[] = (MS_Y[3..0],MS_X[3..0]); + MS_DAT.rdclock = CLK42; + MS_DAT.rdclken = VCC; + + IF MOUSE == "NO" GENERATE + MS_POINT = GND; + MS_POINT2 = GND; + ELSE GENERATE + MS_POINT = DFF((MS_PNT & MS_DAT.q0),CLK42,,); + MS_POINT2 = DFF((MS_PNT & MS_DAT.q1),CLK42,,); + END GENERATE; + +-- === Sinc-counts GENERATOR ============================================ + +-- CT[].clrn = START_UP; + +-- (,CTH[5..0].clrn,CT[5].clrn) = !COPY_SINC_H or HOR_PLACE; +-- (,CTH[5..0].prn ,CT[5].prn ) = !COPY_SINC_H or !HOR_PLACE; + +-- CTV[].clrn = !COPY_SINC_V or VER_PLACE; +-- CTV[].prn = !COPY_SINC_V or !VER_PLACE; + + CT[5].clrn = !COPY_SINC_H; + + -- set CTH to 50 (32h) + CTH[0].clrn = !COPY_SINC_H; + CTH[1].prn = !COPY_SINC_H; + CTH[2].clrn = !COPY_SINC_H; + CTH[3].clrn = !COPY_SINC_H; + CTH[4].prn = !COPY_SINC_H; + CTH[5].prn = !COPY_SINC_H; + + -- set CTV to 122h + CTV[0].clrn = !COPY_SINC_V; + CTV[1].prn = !COPY_SINC_V; + CTV[3..2].clrn = !COPY_SINC_V; + + CTV[4].clrn = !COPY_SINC_V; + CTV[5].prn = !COPY_SINC_V; + CTV[7..6].clrn = !COPY_SINC_V; + CTV[8].prn = !COPY_SINC_V; + + CT[5..0].clk = CLK42; + CTH[5..0].clk = CLK42; + CTV[8..0].clk = CLK42; + + CT[2..0].ena = VCC; + + CASE CT[2..0] IS + WHEN 0 => CT[2..0] = 1; + WHEN 1 => CT[2..0] = 2; + WHEN 2 => CT[2..0] = 4; + WHEN 3 => CT[2..0] = 4; + WHEN 4 => CT[2..0] = 5; + WHEN 5 => CT[2..0] = 6; + WHEN 6 => CT[2..0] = 0; + WHEN 7 => CT[2..0] = 0; + END CASE; + + -- for remove sinc jitter +-- CT[5..3].ena = DFF(((CT0 & CT2) or (COPY_SINC_H & !CT4)),CLK42,,); + CT[5..3].ena = DFF((CT0 & CT2),CLK42,,); + CT[5..3] = CT[5..3]+1; +% + CASE CT[4..3] IS + WHEN 0 => CT[5..3] = CT[5..3]+1; + WHEN 1 => CT[5..3] = CT[5..3]+1; + WHEN 2 => CT[5..3] = CT[5..3]+1; + WHEN 3 => CT[5..3] = CT[5..3]+1; + END CASE; +% + CTH[].ena = DFF(((CT[5..2] == 15) & CT0),CLK42,,); + CTV[].ena = DFF(((CT[5..2] == 15) & CT0 & (CTH[] == 48)),CLK42,,); + + IF CTH[] == 55 THEN + CTH[] = GND; + ELSE + CTH[] = CTH[] + 1; + END IF; + + IF CTV[] == 319 THEN + CTV[] = GND; + ELSE + CTV[] = CTV[] + 1; + END IF; + + CTF[].clk = CTV8; + CTF[] = CTF[]+1; + +-- ==== Video ========================================================== + + ZXS[] = ZX_PORT[5..0]; -- pages ZX Screens + ZX_SCREEN = ZX_PORT6; -- enable ZX Screen write + ZXA15 = ZX_PORT7; -- ZX A15' line + + SCR128 = DIR_PORT0; + +-- WR_PIX = LCELL(TSN_W3); + WR_PIX = (TSN_W3); + + DOUBLE.clk = CLK42; DOUBLE.ena = !E_WR; DOUBLE = DOUBLE_CAS; + VXA[].clk = CLK42; VXA[].ena = !E_WR; + + VXD0[].clk = CLK42; VXD0[].ena = !E_WRD; VDO0[] = VXD0[]; + VXD1[].clk = CLK42; VXD1[].ena = !E_WRD; VDO1[] = VXD1[]; + VXD2[].clk = CLK42; VXD2[].ena = !E_WRD; VDO2[] = VXD2[]; + VXD3[].clk = CLK42; VXD3[].ena = !E_WRD; VDO3[] = VXD3[]; + +-- VXD0[] = D[]; +-- VXD1[] = D[]; +-- VXD2[] = D[]; +-- VXD3[] = D[]; + + (VXD0[],VXD1[]) = MDI[]; + (VXD2[],VXD3[]) = MDI[]; + + BRD[] = DIR_PORT[7..5]; + + VCM[].clk = CLK42; + TSN_W3.clk = CLK42; + V_CST[].clk = CLK42; + V_WE.clk = CLK42; + V_WET[].clk = CLK42; + VLA[].clk = CLK42; + + SCR_ENA.clk = CLK42; + SCR_ENA.ena = !E_WR; + SCR_ENA.d = !(VAI19 or ZX_SCREEN); + + E_WRD = DFF(E_WR,CLK42,,); + E_WR = LCELL(WR or !(VAI19 or ZX_SCREEN) or !DFF(WR,CLK42,,)); +-- E_WR = LCELL(WR or !DFF(WR,CLK42,,)); + +-- **************************************************** + +IF MODE == "SPRINTER" GENERATE + +-- VAI[19] - switch adress mode 1 - graf mode, 0 - spectrum mode + +-- MXWE = DFF(((DFF(E_WR,CLK42,,) or SCR_ENA) & MXWE),CLK42,,V_WE); + MXWE = DFF(MXWE,CLK42,E_WR,V_WE); + + IF VAI[19] THEN + -- in graf mode all 256k(512k) range + VXA[] = VAI[]; + ELSE + -- in spectrum mode 8k/16k range pages + VXA[] = (GND,GND,VAI[7..0],ZXS[4..1],LCELL(ZXS0 xor ZXA15 xor VAI13),VAI[12..8]); + END IF; + +-- BORD = DFF((MODE0[7..4] == 15),WR_PIC,,); +-- BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,); +-- INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),WR_PIC,,); + + BORD = DFF((MODE0[7..4] == 15),LWR_COL,,); + BLANK = DFF(((BORD & MODE03 & MODE02) or DIR_PORT4),LWR_COL,,); + INTTX = DFF((BORD & MODE03 & MODE02 & MODE00),LWR_COL,,); + + INTT = DFF(!(INTTX & (CTV[2..0] == 7)),CT5,,); + +-- INTT = DFF((INTTX or DFF(INTTX,CT5,,)),CT5,,); +-- INTT = DFF(!(BLANK & (CTV[2..0] == 7)),CLK42,,MODE0[0]); + + CASE CT[2..0] IS + WHEN B"110" => VCM[2..0].d = 5; -- 110 -> 101 6 -> 5 + WHEN B"000" => VCM[2..0].d = 1; -- 000 -> 001 0 -> 1 + WHEN B"001" => VCM[2..0].d = 4; -- 001 -> 100 1 -> 4 + WHEN B"010" => VCM[2..0].d = 3; -- 010 -> 011 2 -> 3 + WHEN B"100" => VCM[2..0].d = 2; -- 100 -> 010 4 -> 2 + WHEN B"101" => VCM[2..0].d = 0; -- 101 -> 000 5 -> 0 + END CASE; + + CASE VCM[1..0] IS + WHEN 0 => + VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,RBRVA[10..8],GND,GND); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + IF VCM2 THEN +-- TSN_W3.d = X_MODE5; + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE5); + ELSE + TSN_W3.d = X_MODE_BOND; +-- V_CST[].d = (VCC,X_MODE_BOND); + END IF; + WHEN 1 => + WR_PIC.d = !VCM2; + WR_COL.d = VCM2; + VLA[].d = SVA[]; + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + WHEN 2 => + VLA[].d = VXA[17..0]; + V_CST[].d = (!VXA18,VXA18) or MXWE; + V_WE.d = MXWE; + V_WEX.d = GND; + V_WET[].d = MXWE or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + WHEN 3 => +-- WR_PIC.d = X_MODE5; +-- NEW 26.08.2022, fix bug with first column +-- it was reproducing when changes mode 320 -> 640, like any 320px screen squares -> text mode squares + WR_PIC.d = MODE0[5]; + VLA[].d = (DIR_PORT3,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND); + WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]); + V_CST[].d = (VCC,GND); + V_WE.d = VCC; + V_WEX.d = VCC; + END CASE; + +-- choose V-RAM komplect + + V_CST1.prn = GND; +-- V_CS0.clrn = GND; + V_CST0.prn = (LCELL(DFF(GND,!CLK42,,!V_CST0))); + V_CS1 = VCC; +-- V_CS0 = LCELL(V_CST0); + + V_CSX0 = LCELL(!CLK42); + V_CSX1 = LCELL(V_CSX0); + V_CSX2 = LCELL(V_CSX1 & V_CSX0); + V_CSX3 = LCELL(V_CSX2); + +-- V_CS0 = V_CSX3; + V_CS0 = GND; + +-- ===================== + + SVA[].clk = CLK42; + SVA[9..6] = MODE0[3..0]; +-- RSVA[].clk = CLK42; + (SVA[12..10],SVA[5..0]) = RSVA[]; + +-- M_CTV[2..0].clk = CLK42; +-- M_CT[5..3].clk = CLK42; + M_CTV[2..0] = (!MODE2[2] & CTV[2..0]) or MODE2[2] & (MODE2[1],CTV[2..1]); + M_CT[5..3] = (!MODE2[2] & (CT[5],!CT[4..3])) or MODE2[2] & (MODE2[0],!CT[5..4]); + + CASE (!VCM2,MODE0[4]) IS +-- CASE (!VCM1,MODE0[4]) IS + WHEN B"X0" => + -- Graf adress -- + RSVA[] = (M_CTV[2..0],MODE1[2..0],M_CT[5..3]); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = CTV[2..0]; +-- SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]); + WHEN B"01" => + -- ZX-atr adress -- + RSVA[] = (MODE2[2..0],SCR128,VCC,VCC,GND,!MODE0[7..6]); + SVA[17..13] = MODE2[7..3]; + +-- SVA[12..10] = MODE2[2..0]; +-- SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]); + WHEN B"11" => + -- ZX-pic adress -- + RSVA[] = (MODE1[2..0],SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + SVA[17..13] = MODE1[7..3]; + +-- SVA[12..10] = MODE1[2..0]; +-- SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + END CASE; + +-- X_MODE_BOND = LCELL(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,VCC,VCC)); + X_MODE_BOND = GND; + +-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); +-- LD_PIC = LCELL((MODE0[5] & DFF((CT[5..3] == B"000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + LD_PIC = LCELL((MODE0[5] & DFF((CT[5..2] == B"0000"),CLK42,,)) or (!MODE0[5] & DFF((CT[4..2] == B"000"),CLK42,,))); + + +-- CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS + +-- D_PIC0_[].clk = !CLK42; +-- D_PIC1_[].clk = !CLK42; +-- D_PIC2_[].clk = !CLK42; +-- D_PIC3_[].clk = !CLK42; + +-- PIC_CLK = LCELL(LCELL(CLK42)); + PIC_CLK = !CLK42; + + D_PIC0_[].clk = PIC_CLK; + D_PIC1_[].clk = PIC_CLK; + D_PIC2_[].clk = PIC_CLK; + D_PIC3_[].clk = PIC_CLK; + + D_PIC0_[] = VDM0[]; + D_PIC1_[] = VDM1[]; + D_PIC2_[] = VDM2[]; + D_PIC3_[] = VDM3[]; + + CASE (DFF(VLA1,CLK42,,),DFF(VLA0,CLK42,,)) IS + WHEN 0 => D_PICX_[] = D_PIC0_[]; + WHEN 1 => D_PICX_[] = D_PIC1_[]; + WHEN 2 => D_PICX_[] = D_PIC2_[]; + WHEN 3 => D_PICX_[] = D_PIC3_[]; + END CASE; + + MODE0[].ena = VCC; + MODE1[].ena = VCC; + MODE2[].ena = VCC; + MODE0[].clk = LWR_MODE; + MODE1[].clk = LWR_MODE; + MODE2[].clk = LWR_MODE; + MODE0[].d = VDM3[]; + MODE1[].d = VDM2[]; + MODE2[].d = VDM1[]; + LWR_MODE = LCELL(LCELL(WR_MODE)); +% + MODE0[].ena = LWR_MODE; + MODE1[].ena = LWR_MODE; + MODE2[].ena = LWR_MODE; + MODE0[].clk = CLK42; + MODE1[].clk = CLK42; + MODE2[].clk = CLK42; + MODE0[].d = D_PIC3_[]; + MODE1[].d = D_PIC2_[]; + MODE2[].d = D_PIC1_[]; + LWR_MODE = DFF(!WR_MODE,CLK42,,); +% + X_MODE7 = DFF(MODE0[7],LWR_COL,,); + X_MODE6 = DFF(MODE0[6],LWR_COL,,); + X_MODE5 = DFF(MODE0[5],LWR_COL,,); + X_MODE4 = DFF(MODE0[4],LWR_COL,,); + + VAO[] = VLA[17..2]; + + WR_PIC.clk = CLK42; + WR_COL.clk = CLK42; + WR_MODE.clk = CLK42; + +-- LWR_PIC = LCELL(LCELL(WR_PIC)); +-- LWR_COL = LCELL(LCELL(WR_COL)); +-- LWR_PIC = LCELL(WR_PIC); +-- LWR_COL = LCELL(WR_COL); + LWR_PIC = DFF(WR_PIC,CLK42,,); + LWR_COL = DFF(WR_COL,CLK42,,); + +-- D_PIC0[].ena = VCC; +-- D_PIC0[].clk = (LWR_PIC); + D_PIC0[].ena = !LWR_PIC; + D_PIC0[].clk = CLK42; + + + + + IF LD_PIC THEN +-- D_PIC0[] = D_PIC0_[]; + D_PIC0[] = D_PICX_[]; + ELSE + D_PIC0[] = (D_PIC0[6..0],GND); + END IF; + + +-- DCOL[].clk = (LWR_COL); + DCOL[].ena = !LWR_COL; + DCOL[].clk = CLK42; + + IF DFF((MODE0[7..4] == 15),WR_PIC,,) THEN + DCOL[].d = (B"00",BRD[2..0],BRD[2..0]); + ELSE +-- DCOL[].d = D_PIC0_[]; + DCOL[].d = D_PICX_[]; + END IF; + + DCOL[].clrn = !BLANK; + + BRVA[].clk = CLK42; + BRVA[].clrn = !MS_POINT; + BRVA[].prn = !MS_POINT2; + +-- MODE0[4] - graph / text +-- MODE0[5] - 320 / 640 resolution + +-- CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS + CASE (DFF((MODE0[4] or MODE0[5]),LWR_COL,,),CT2) IS + WHEN B"1X" => BRVA[7..0] = DCOL[]; + WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]); + WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]); + END CASE; + +-- BRVA[10..8] = (x_mode4,RBRVA[9..8]); + RBRVA[].clk = CLK42; + + CASE (BORD,X_MODE4) IS + WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]); + WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]); + END CASE; + + RBRVA[9..8].clrn = !BORD; + RBRVA[10].prn = !BORD; + + CASE (RBRVA[9..8],BRVA7) IS + WHEN 0,1,4,7 => ZX_COL[] = (BRVA[6],BRVA[5..3]); + WHEN 2,3,6,5 => ZX_COL[] = (BRVA[6],BRVA[2..0]); + END CASE; + +-- V_WET[].prn = LCELL(DFF(GND,!CLK42,,!V_WE)); +-- V_WE.prn = LCELL(DFF(GND,!CLK42,,!V_WE)); + + V_WE_R = DFF(GND,!CLK42,,!V_WE); + V_WE.prn = V_WE_R; + V_WET[].prn = V_WE_R; + +-- V_WR[] = LCELL(V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + +-- V_WR[] = (V_WE) or !( + + V_WEX.clk = CLK42; +-- V_WEX.d = V_WE; +-- V_WEX.prn = (DFF(GND,CLK42,,!V_WEX)); + + + V_WEMMM = LCELL(V_WE); + V_WEMMN = LCELL(V_WEMMM); + V_WEMMO = LCELL(V_WEMMN); + V_WEMM = LCELL(V_WEMMO); + + V_WRM = LCELL(V_WEMMN & V_WEMMM); + V_WRM2 = LCELL(V_WEMMN & V_WEMMM); + + V_WEM = LCELL(V_WEMMM & V_WEMMO); + V_WEM2 = LCELL(V_WEMMM & V_WEMMO); + + V_EN3 = DFF(!(!VXA1 & (!VXA0 or DOUBLE)),CLK42,F_WR,); + V_EN2 = DFF(!(!VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,); + V_EN1 = DFF(!(VXA1 & (!VXA0 or DOUBLE)) ,CLK42,F_WR,); + V_EN0 = DFF(!(VXA1 & (VXA0 or DOUBLE)) ,CLK42,F_WR,); + + F_WR = DFF(VCC,V_WE,,); + + V_WR_3 = V_WRM or V_EN3; + V_WR_2 = V_WRM2 or V_EN2; + V_WR_1 = V_WRM or V_EN1; + V_WR_0 = V_WRM or V_EN0; + + V_WEY3 = V_WEM or V_EN3; + V_WEY2 = V_WEM2 or V_EN2; + V_WEY1 = V_WEM or V_EN1; + V_WEY0 = V_WEM or V_EN0; + + V_WR[] = V_WR_[]; + V_WEN[] = V_WEY[]; + +-- CLK84 = LCELL(CLK42 xor CLK84_X); +-- CLK84_X = DFF(!CLK84_X,CLK84,,); +-- CLK84_Y = CLK84; + +END GENERATE; -- end "sprinter" mode + + +END; diff --git a/src/altera/quartus/acex/db/SP2_ACEX.(0).cnf.cdb b/src/altera/quartus/acex/db/SP2_ACEX.(0).cnf.cdb new file mode 100644 index 0000000..eafe8db Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.(0).cnf.cdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.(0).cnf.hdb b/src/altera/quartus/acex/db/SP2_ACEX.(0).cnf.hdb new file mode 100644 index 0000000..3ec6d5f Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.(0).cnf.hdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.(1).cnf.cdb b/src/altera/quartus/acex/db/SP2_ACEX.(1).cnf.cdb new file mode 100644 index 0000000..94c4ef0 Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.(1).cnf.cdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.(1).cnf.hdb b/src/altera/quartus/acex/db/SP2_ACEX.(1).cnf.hdb new file mode 100644 index 0000000..e3a0cf0 Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.(1).cnf.hdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.(2).cnf.cdb b/src/altera/quartus/acex/db/SP2_ACEX.(2).cnf.cdb new file mode 100644 index 0000000..2f4b8e7 Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.(2).cnf.cdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.(2).cnf.hdb b/src/altera/quartus/acex/db/SP2_ACEX.(2).cnf.hdb new file mode 100644 index 0000000..b1c337a Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.(2).cnf.hdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.(3).cnf.cdb b/src/altera/quartus/acex/db/SP2_ACEX.(3).cnf.cdb new file mode 100644 index 0000000..2d64609 Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.(3).cnf.cdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.(3).cnf.hdb b/src/altera/quartus/acex/db/SP2_ACEX.(3).cnf.hdb new file mode 100644 index 0000000..2cc0be3 Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.(3).cnf.hdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.cbx.xml b/src/altera/quartus/acex/db/SP2_ACEX.cbx.xml new file mode 100644 index 0000000..5f721b8 --- /dev/null +++ b/src/altera/quartus/acex/db/SP2_ACEX.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/src/altera/quartus/acex/db/SP2_ACEX.cmp.rdb b/src/altera/quartus/acex/db/SP2_ACEX.cmp.rdb new file mode 100644 index 0000000..b3eee15 Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.cmp.rdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.db_info b/src/altera/quartus/acex/db/SP2_ACEX.db_info new file mode 100644 index 0000000..85d27e7 --- /dev/null +++ b/src/altera/quartus/acex/db/SP2_ACEX.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +Version_Index = 167832322 +Creation_Time = Sun Aug 28 03:32:05 2022 diff --git a/src/altera/quartus/acex/db/SP2_ACEX.eco.cdb b/src/altera/quartus/acex/db/SP2_ACEX.eco.cdb new file mode 100644 index 0000000..4dfce69 Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.eco.cdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.hif b/src/altera/quartus/acex/db/SP2_ACEX.hif new file mode 100644 index 0000000..2316ce0 --- /dev/null +++ b/src/altera/quartus/acex/db/SP2_ACEX.hif @@ -0,0 +1,447 @@ +Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +2 +25 +OFF +OFF +OFF +ON +ON +OFF +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +SP2_ACEX +# storage +db|SP2_ACEX.(0).cnf +db|SP2_ACEX.(0).cnf +# case_insensitive +# source_file +SP2_ACEX.tdf +e1a512c7ccb99b9920cc5b6bdd99f78f +7 +# user_parameter { +UPDATE +1 +PARAMETER_UNKNOWN +DEF +MODE +SPRINTER +PARAMETER_UNKNOWN +DEF +NMI_ON +OFF +PARAMETER_UNKNOWN +DEF +SCREEN_OFF +NOT_USE +PARAMETER_UNKNOWN +DEF +} +# used_port { +0 +-1 +0 +} +# include_file { +video2.inc +442325f281c69a29c502cd73d5463bd +ay.inc +b7bbf416ab242c30663925c2494dac1c +acceler.inc +ba3f30e8f544b3289c4a8b774427d197 +kbd.inc +d95fc07fdbddf4beead37796f9d8 +dcp.inc +3ad9d1c98b85a6e2fa8234adbe4e62 +mouse.inc +3a5e806a69816f4041b35f81b0afc554 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_ram_dp.inc +654442a54e5e12427dca2ad67c24c46b +} +# hierarchies { +| +} +# macro_sequence + +# end +# entity +MOUSE +# storage +db|SP2_ACEX.(1).cnf +db|SP2_ACEX.(1).cnf +# case_insensitive +# source_file +MOUSE.tdf +94907776ef372fcfb98eeebc359b8f77 +7 +# used_port { +out_y9 +-1 +3 +out_y8 +-1 +3 +out_y7 +-1 +3 +out_y6 +-1 +3 +out_y5 +-1 +3 +out_y4 +-1 +3 +out_y3 +-1 +3 +out_y2 +-1 +3 +out_y1 +-1 +3 +out_y0 +-1 +3 +out_x9 +-1 +3 +out_x8 +-1 +3 +out_x7 +-1 +3 +out_x6 +-1 +3 +out_x5 +-1 +3 +out_x4 +-1 +3 +out_x3 +-1 +3 +out_x2 +-1 +3 +out_x1 +-1 +3 +out_x0 +-1 +3 +out_k1 +-1 +3 +out_k0 +-1 +3 +mouse_d +-1 +3 +clk +-1 +3 +} +# include_file { +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_add_sub.inc +7d9a33dd39f13aa690c3d0edd88351 +} +# hierarchies { +MOUSE:MS +} +# macro_sequence + +# end +# entity +kbd +# storage +db|SP2_ACEX.(2).cnf +db|SP2_ACEX.(2).cnf +# case_insensitive +# source_file +kbd.tdf +afaf2f48afdd456dd44d65de56c873a0 +7 +# used_port { +kbo5 +-1 +3 +kbo4 +-1 +3 +kbo3 +-1 +3 +kbo2 +-1 +3 +kbo1 +-1 +3 +kbo0 +-1 +3 +kbd_dd +-1 +3 +kbd_cc +-1 +3 +kb_sh +-1 +3 +kb_reset +-1 +3 +kb_f12 +-1 +3 +kb_ctrl +-1 +3 +kb_alt +-1 +3 +int_ena +-1 +3 +int +-1 +3 +clk_k +-1 +3 +clk42 +-1 +3 +a9 +-1 +3 +a8 +-1 +3 +a15 +-1 +3 +a14 +-1 +3 +a13 +-1 +3 +a12 +-1 +3 +a11 +-1 +3 +a10 +-1 +3 +/rf +-1 +3 +/iom +-1 +3 +/io +-1 +3 +ena +-1 +2 +/m1 +-1 +2 +} +# include_file { +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_ram_dq.inc +597f4cadef5751f17c6f4540c4ffcc84 +} +# hierarchies { +kbd:KEYS +} +# macro_sequence + +# end +# entity +lpm_ram_dq +# storage +db|SP2_ACEX.(3).cnf +db|SP2_ACEX.(3).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_ram_dq.tdf +7179e8cfd3a5bdbbfbdb2c4f1192e5 +7 +# user_parameter { +LPM_WIDTH +8 +PARAMETER_UNKNOWN +USR +LPM_WIDTHAD +8 +PARAMETER_UNKNOWN +USR +LPM_NUMWORDS +256 +PARAMETER_UNKNOWN +DEF +LPM_INDATA +REGISTERED +PARAMETER_UNKNOWN +DEF +LPM_ADDRESS_CONTROL +REGISTERED +PARAMETER_UNKNOWN +DEF +LPM_OUTDATA +UNREGISTERED +PARAMETER_UNKNOWN +USR +LPM_FILE +KBD_INI2.MIF +PARAMETER_UNKNOWN +USR +USE_EAB +ON +PARAMETER_UNKNOWN +DEF +DEVICE_FAMILY +ACEX1K +PARAMETER_UNKNOWN +USR +CBXI_PARAMETER +NOTHING +PARAMETER_UNKNOWN +DEF +AUTO_CARRY_CHAINS +ON +AUTO_CARRY +USR +IGNORE_CARRY_BUFFERS +OFF +IGNORE_CARRY +USR +AUTO_CASCADE_CHAINS +ON +AUTO_CASCADE +USR +IGNORE_CASCADE_BUFFERS +OFF +IGNORE_CASCADE +USR +} +# used_port { +we +-1 +3 +q7 +-1 +3 +q6 +-1 +3 +q5 +-1 +3 +q4 +-1 +3 +q3 +-1 +3 +q2 +-1 +3 +q1 +-1 +3 +q0 +-1 +3 +inclock +-1 +3 +data5 +-1 +3 +data4 +-1 +3 +data3 +-1 +3 +data2 +-1 +3 +data1 +-1 +3 +data0 +-1 +3 +address7 +-1 +3 +address6 +-1 +3 +address5 +-1 +3 +address4 +-1 +3 +address3 +-1 +3 +address2 +-1 +3 +address1 +-1 +3 +address0 +-1 +3 +data7 +-1 +2 +data6 +-1 +2 +} +# include_file { +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_decode.inc +bd0e2f5e01c1bd360461dceb53d48 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_mux.inc +c22bfd353214c01495b560fc34e47d79 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|aglobal90.inc +99832fdf63412df51d7531202d74e75 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|altram.inc +e66a83eccf6717bed97c99d891ad085 +} +# hierarchies { +kbd:KEYS|lpm_ram_dq:$00021 +} +# macro_sequence + +# end +# complete + \ No newline at end of file diff --git a/src/altera/quartus/acex/db/SP2_ACEX.map.hdb b/src/altera/quartus/acex/db/SP2_ACEX.map.hdb new file mode 100644 index 0000000..a131a2a Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.map.hdb differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.map.qmsg b/src/altera/quartus/acex/db/SP2_ACEX.map.qmsg new file mode 100644 index 0000000..f131c0c --- /dev/null +++ b/src/altera/quartus/acex/db/SP2_ACEX.map.qmsg @@ -0,0 +1,30 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 15:25:50 2022 " "Info: Processing started: Sun Aug 28 15:25:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SP2_ACEX -c SP2_ACEX " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SP2_ACEX -c SP2_ACEX" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "SP2_ACEX.tdf 1 1 " "Warning: Using design file SP2_ACEX.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SP2_ACEX " "Info: Found entity 1: SP2_ACEX" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "SP2_ACEX " "Info: Elaborating entity \"SP2_ACEX\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "DMD " "Warning: Variable or input pin \"DMD\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 109 5 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "T_SIGNAL " "Warning: Variable or input pin \"T_SIGNAL\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 147 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "RED " "Warning: Variable or input pin \"RED\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 160 5 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "GREEN " "Warning: Variable or input pin \"GREEN\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 161 7 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "BLUE " "Warning: Variable or input pin \"BLUE\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 162 6 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "MDR " "Warning: Variable or input pin \"MDR\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 170 5 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "ISA_CASH " "Warning: Variable or input pin \"ISA_CASH\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 222 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "ROM_WRITE_MODE " "Warning: Variable or input pin \"ROM_WRITE_MODE\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 241 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "/HALT " "Warning: Variable or input pin \"/HALT\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 36 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "MOUSE.tdf 1 1 " "Warning: Using design file MOUSE.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mouse " "Info: Found entity 1: mouse" { } { { "MOUSE.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/MOUSE.tdf" 6 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MOUSE MOUSE:MS " "Info: Elaborating entity \"MOUSE\" for hierarchy \"MOUSE:MS\"" { } { { "SP2_ACEX.tdf" "MS" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 79 2 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "KB_OFL " "Warning: Variable or input pin \"KB_OFL\" is defined but never used" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 63 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "kbd.tdf 1 1 " "Warning: Using design file kbd.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 kbd " "Info: Found entity 1: kbd" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 6 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "kbd kbd:KEYS " "Info: Elaborating entity \"kbd\" for hierarchy \"kbd:KEYS\"" { } { { "SP2_ACEX.tdf" "KEYS" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 80 2 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "/IOM " "Warning: Variable or input pin \"/IOM\" is defined but never used" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 15 2 0 } } { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 80 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "/M1 " "Warning: Variable or input pin \"/M1\" is defined but never used" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 16 2 0 } } { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 80 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Elaborating entity \"lpm_ram_dq\" for hierarchy \"kbd:KEYS\|lpm_ram_dq:\$00021\"" { } { { "kbd.tdf" "\$00021" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Elaborated megafunction instantiation \"kbd:KEYS\|lpm_ram_dq:\$00021\"" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Instantiated megafunction \"kbd:KEYS\|lpm_ram_dq:\$00021\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 8 " "Info: Parameter \"LPM_WIDTHAD\" = \"8\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE KBD_INI2.MIF " "Info: Parameter \"LPM_FILE\" = \"KBD_INI2.MIF\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram " "Info: Elaborating entity \"altram\" for hierarchy \"kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram\"" { } { { "lpm_ram_dq.tdf" "sram" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Error" "EMIO_MIO_INVALID_LINE" "KBD_INI2.MIF 13 " "Error: Memory Initialization File or Hexadecimal (Intel-Format) File \"KBD_INI2.MIF\" contains illegal syntax at line 13" { } { { "C:/Sprinter/src/altera/quartus/acex/KBD_INI2.MIF" "" { Text "C:/Sprinter/src/altera/quartus/acex/KBD_INI2.MIF" 13 -1 0 } } } 0 0 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains illegal syntax at line %2!d!" 0 0 "" 0 -1} +{ "Critical Warning" "WCDB_CDB_CANT_READ_CONTENT_FILE" "KBD_INI2.MIF " "Critical Warning: Can't read Memory Initialization File or Hexadecimal (Intel-Format) File KBD_INI2.MIF -- setting all initial values to 0" { } { { "altram.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/altram.tdf" 178 13 0 } } } 1 0 "Can't read Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0 "" 0 -1} +{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram " "Error: Can't elaborate user hierarchy \"kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram\"" { } { { "lpm_ram_dq.tdf" "sram" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } } 0 0 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Elaborated megafunction instantiation \"kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram\", which is child of megafunction instantiation \"kbd:KEYS\|lpm_ram_dq:\$00021\"" { } { { "lpm_ram_dq.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 16 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 16 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "228 " "Error: Peak virtual memory: 228 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Sun Aug 28 15:25:51 2022 " "Error: Processing ended: Sun Aug 28 15:25:51 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/acex/db/SP2_ACEX.sld_design_entry.sci b/src/altera/quartus/acex/db/SP2_ACEX.sld_design_entry.sci new file mode 100644 index 0000000..100faca Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.sld_design_entry.sci differ diff --git a/src/altera/quartus/acex/db/SP2_ACEX.tis_db_list.ddb b/src/altera/quartus/acex/db/SP2_ACEX.tis_db_list.ddb new file mode 100644 index 0000000..322a503 Binary files /dev/null and b/src/altera/quartus/acex/db/SP2_ACEX.tis_db_list.ddb differ diff --git a/src/altera/quartus/acex/db/prev_cmp_SP2_ACEX.map.qmsg b/src/altera/quartus/acex/db/prev_cmp_SP2_ACEX.map.qmsg new file mode 100644 index 0000000..65bbf1b --- /dev/null +++ b/src/altera/quartus/acex/db/prev_cmp_SP2_ACEX.map.qmsg @@ -0,0 +1,30 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:33:04 2022 " "Info: Processing started: Sun Aug 28 03:33:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SP2_ACEX -c SP2_ACEX " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SP2_ACEX -c SP2_ACEX" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "SP2_ACEX.tdf 1 1 " "Warning: Using design file SP2_ACEX.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SP2_ACEX " "Info: Found entity 1: SP2_ACEX" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "SP2_ACEX " "Info: Elaborating entity \"SP2_ACEX\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "DMD " "Warning: Variable or input pin \"DMD\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 109 5 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "T_SIGNAL " "Warning: Variable or input pin \"T_SIGNAL\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 147 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "RED " "Warning: Variable or input pin \"RED\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 160 5 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "GREEN " "Warning: Variable or input pin \"GREEN\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 161 7 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "BLUE " "Warning: Variable or input pin \"BLUE\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 162 6 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "MDR " "Warning: Variable or input pin \"MDR\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 170 5 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "ISA_CASH " "Warning: Variable or input pin \"ISA_CASH\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 222 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "ROM_WRITE_MODE " "Warning: Variable or input pin \"ROM_WRITE_MODE\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 241 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "/HALT " "Warning: Variable or input pin \"/HALT\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 36 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "MOUSE.tdf 1 1 " "Warning: Using design file MOUSE.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mouse " "Info: Found entity 1: mouse" { } { { "MOUSE.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/MOUSE.tdf" 6 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MOUSE MOUSE:MS " "Info: Elaborating entity \"MOUSE\" for hierarchy \"MOUSE:MS\"" { } { { "SP2_ACEX.tdf" "MS" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 79 2 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "KB_OFL " "Warning: Variable or input pin \"KB_OFL\" is defined but never used" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 63 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "kbd.tdf 1 1 " "Warning: Using design file kbd.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 kbd " "Info: Found entity 1: kbd" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 6 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "kbd kbd:KEYS " "Info: Elaborating entity \"kbd\" for hierarchy \"kbd:KEYS\"" { } { { "SP2_ACEX.tdf" "KEYS" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 80 2 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "/IOM " "Warning: Variable or input pin \"/IOM\" is defined but never used" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 15 2 0 } } { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 80 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "/M1 " "Warning: Variable or input pin \"/M1\" is defined but never used" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 16 2 0 } } { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 80 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Elaborating entity \"lpm_ram_dq\" for hierarchy \"kbd:KEYS\|lpm_ram_dq:\$00021\"" { } { { "kbd.tdf" "\$00021" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Elaborated megafunction instantiation \"kbd:KEYS\|lpm_ram_dq:\$00021\"" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Instantiated megafunction \"kbd:KEYS\|lpm_ram_dq:\$00021\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 8 " "Info: Parameter \"LPM_WIDTHAD\" = \"8\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE KBD_INI2.MIF " "Info: Parameter \"LPM_FILE\" = \"KBD_INI2.MIF\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram " "Info: Elaborating entity \"altram\" for hierarchy \"kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram\"" { } { { "lpm_ram_dq.tdf" "sram" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Error" "EMIO_MIO_INVALID_LINE" "KBD_INI2.MIF 13 " "Error: Memory Initialization File or Hexadecimal (Intel-Format) File \"KBD_INI2.MIF\" contains illegal syntax at line 13" { } { { "C:/Sprinter/src/altera/quartus/acex/KBD_INI2.MIF" "" { Text "C:/Sprinter/src/altera/quartus/acex/KBD_INI2.MIF" 13 -1 0 } } } 0 0 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains illegal syntax at line %2!d!" 0 0 "" 0 -1} +{ "Critical Warning" "WCDB_CDB_CANT_READ_CONTENT_FILE" "KBD_INI2.MIF " "Critical Warning: Can't read Memory Initialization File or Hexadecimal (Intel-Format) File KBD_INI2.MIF -- setting all initial values to 0" { } { { "altram.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/altram.tdf" 178 13 0 } } } 1 0 "Can't read Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0 "" 0 -1} +{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram " "Error: Can't elaborate user hierarchy \"kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram\"" { } { { "lpm_ram_dq.tdf" "sram" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } } 0 0 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Elaborated megafunction instantiation \"kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram\", which is child of megafunction instantiation \"kbd:KEYS\|lpm_ram_dq:\$00021\"" { } { { "lpm_ram_dq.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 16 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 16 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "228 " "Error: Peak virtual memory: 228 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Sun Aug 28 03:33:05 2022 " "Error: Processing ended: Sun Aug 28 03:33:05 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/acex/db/prev_cmp_SP2_ACEX.qmsg b/src/altera/quartus/acex/db/prev_cmp_SP2_ACEX.qmsg new file mode 100644 index 0000000..5bbc209 --- /dev/null +++ b/src/altera/quartus/acex/db/prev_cmp_SP2_ACEX.qmsg @@ -0,0 +1,31 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:32:19 2022 " "Info: Processing started: Sun Aug 28 03:32:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SP2_ACEX -c SP2_ACEX " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SP2_ACEX -c SP2_ACEX" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "SP2_ACEX.tdf 1 1 " "Warning: Using design file SP2_ACEX.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SP2_ACEX " "Info: Found entity 1: SP2_ACEX" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 24 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "SP2_ACEX " "Info: Elaborating entity \"SP2_ACEX\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "DMD " "Warning: Variable or input pin \"DMD\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 109 5 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "T_SIGNAL " "Warning: Variable or input pin \"T_SIGNAL\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 147 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "RED " "Warning: Variable or input pin \"RED\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 160 5 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "GREEN " "Warning: Variable or input pin \"GREEN\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 161 7 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "BLUE " "Warning: Variable or input pin \"BLUE\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 162 6 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "MDR " "Warning: Variable or input pin \"MDR\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 170 5 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "ISA_CASH " "Warning: Variable or input pin \"ISA_CASH\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 222 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "ROM_WRITE_MODE " "Warning: Variable or input pin \"ROM_WRITE_MODE\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 241 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "/HALT " "Warning: Variable or input pin \"/HALT\" is defined but never used" { } { { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 36 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "MOUSE.tdf 1 1 " "Warning: Using design file MOUSE.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mouse " "Info: Found entity 1: mouse" { } { { "MOUSE.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/MOUSE.tdf" 6 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MOUSE MOUSE:MS " "Info: Elaborating entity \"MOUSE\" for hierarchy \"MOUSE:MS\"" { } { { "SP2_ACEX.tdf" "MS" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 79 2 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "KB_OFL " "Warning: Variable or input pin \"KB_OFL\" is defined but never used" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 63 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "kbd.tdf 1 1 " "Warning: Using design file kbd.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 kbd " "Info: Found entity 1: kbd" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 6 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "kbd kbd:KEYS " "Info: Elaborating entity \"kbd\" for hierarchy \"kbd:KEYS\"" { } { { "SP2_ACEX.tdf" "KEYS" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 80 2 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "/IOM " "Warning: Variable or input pin \"/IOM\" is defined but never used" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 15 2 0 } } { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 80 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "/M1 " "Warning: Variable or input pin \"/M1\" is defined but never used" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 16 2 0 } } { "SP2_ACEX.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/SP2_ACEX.tdf" 80 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Elaborating entity \"lpm_ram_dq\" for hierarchy \"kbd:KEYS\|lpm_ram_dq:\$00021\"" { } { { "kbd.tdf" "\$00021" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Elaborated megafunction instantiation \"kbd:KEYS\|lpm_ram_dq:\$00021\"" { } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Instantiated megafunction \"kbd:KEYS\|lpm_ram_dq:\$00021\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 8 " "Info: Parameter \"LPM_WIDTHAD\" = \"8\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE KBD_INI2.MIF " "Info: Parameter \"LPM_FILE\" = \"KBD_INI2.MIF\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA UNREGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"UNREGISTERED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram " "Info: Elaborating entity \"altram\" for hierarchy \"kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram\"" { } { { "lpm_ram_dq.tdf" "sram" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Error" "EMIO_MIO_INVALID_LINE" "KBD_INI2.MIF 13 " "Error: Memory Initialization File or Hexadecimal (Intel-Format) File \"KBD_INI2.MIF\" contains illegal syntax at line 13" { } { { "C:/Sprinter/src/altera/quartus/acex/KBD_INI2.MIF" "" { Text "C:/Sprinter/src/altera/quartus/acex/KBD_INI2.MIF" 13 -1 0 } } } 0 0 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains illegal syntax at line %2!d!" 0 0 "" 0 -1} +{ "Critical Warning" "WCDB_CDB_CANT_READ_CONTENT_FILE" "KBD_INI2.MIF " "Critical Warning: Can't read Memory Initialization File or Hexadecimal (Intel-Format) File KBD_INI2.MIF -- setting all initial values to 0" { } { { "altram.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/altram.tdf" 178 13 0 } } } 1 0 "Can't read Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0 "" 0 -1} +{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram " "Error: Can't elaborate user hierarchy \"kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram\"" { } { { "lpm_ram_dq.tdf" "sram" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } } 0 0 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram kbd:KEYS\|lpm_ram_dq:\$00021 " "Info: Elaborated megafunction instantiation \"kbd:KEYS\|lpm_ram_dq:\$00021\|altram:sram\", which is child of megafunction instantiation \"kbd:KEYS\|lpm_ram_dq:\$00021\"" { } { { "lpm_ram_dq.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } { "kbd.tdf" "" { Text "C:/Sprinter/src/altera/quartus/acex/kbd.tdf" 167 9 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 16 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 16 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "225 " "Error: Peak virtual memory: 225 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Sun Aug 28 03:32:20 2022 " "Error: Processing ended: Sun Aug 28 03:32:20 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 16 s " "Error: Quartus II Full Compilation was unsuccessful. 4 errors, 16 warnings" { } { } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/acex/maxplusii_to_quartus_name_mapping.txt b/src/altera/quartus/acex/maxplusii_to_quartus_name_mapping.txt new file mode 100644 index 0000000..d8be4d7 --- /dev/null +++ b/src/altera/quartus/acex/maxplusii_to_quartus_name_mapping.txt @@ -0,0 +1,307 @@ + -- Copyright (C) 1991-2004 Altera Corporation + -- Any megafunction design, and related netlist (encrypted or decrypted), + -- support information, device programming or simulation file, and any other + -- associated documentation or information provided by Altera or a partner + -- under Altera's Megafunction Partnership Program may be used only + -- to program PLD devices (but not masked PLD devices) from Altera. Any + -- other use of such megafunction design, netlist, support information, + -- device programming or simulation file, or any other related documentation + -- or information is prohibited for any other purpose, including, but not + -- limited to modification, reverse engineering, de-compiling, or use with + -- any other silicon devices, unless such use is explicitly licensed under + -- a separate agreement with Altera or a megafunction partner. Title to the + -- intellectual property, including patents, copyrights, trademarks, trade + -- secrets, or maskworks, embodied in any such megafunction design, netlist, + -- support information, device programming or simulation file, or any other + -- related documentation or information provided by Altera or a megafunction + -- partner, remains with Altera, the megafunction partner, or their respective + -- licensors. No other licenses, including any licenses needed under any third + -- party's intellectual property, are provided herein. + + -- VERSION "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" + -- DATE "08/28/2022 15:25:41" + +Conversion results for sp2_acex ++--------------------------------------------------------+--------------------------------------------------------+ +| MAX+PLUS II node name | Quartus II node name | ++--------------------------------------------------------+--------------------------------------------------------+ +| |/M1 | /M[1] | +| |/m1 | /m[1] | +| |A0 | A[0] | +| |a0 | a[0] | +| |A1 | A[1] | +| |a1 | a[1] | +| |A2 | A[2] | +| |a2 | a[2] | +| |A3 | A[3] | +| |a3 | a[3] | +| |A4 | A[4] | +| |a4 | a[4] | +| |A5 | A[5] | +| |a5 | a[5] | +| |A6 | A[6] | +| |a6 | a[6] | +| |A7 | A[7] | +| |a7 | a[7] | +| |A8 | A[8] | +| |a8 | a[8] | +| |A9 | A[9] | +| |a9 | a[9] | +| |A10 | A[10] | +| |a10 | a[10] | +| |A11 | A[11] | +| |a11 | a[11] | +| |A12 | A[12] | +| |A13 | A[13] | +| |A14 | A[14] | +| |A15 | A[15] | +| |CAS_0 | CAS_[0] | +| |CAS_1 | CAS_[1] | +| |CAS_2 | CAS_[2] | +| |CAS_3 | CAS_[3] | +| |CASX_0 | CASX_[0] | +| |CASX_1 | CASX_[1] | +| |CASX_2 | CASX_[2] | +| |CASX_3 | CASX_[3] | +| |CASXE0 | CASXE[0] | +| |CASXE1 | CASXE[1] | +| |CLKZ1 | CLKZ[1] | +| |D0 | D[0] | +| |d0 | d[0] | +| |D1 | D[1] | +| |d1 | d[1] | +| |D2 | D[2] | +| |d2 | d[2] | +| |D3 | D[3] | +| |d3 | d[3] | +| |D4 | D[4] | +| |d4 | d[4] | +| |D5 | D[5] | +| |d5 | d[5] | +| |D6 | D[6] | +| |d6 | d[6] | +| |D7 | D[7] | +| |d7 | d[7] | +| |MA0 | MA[0] | +| |ma0 | ma[0] | +| |MA1 | MA[1] | +| |ma1 | ma[1] | +| |MA2 | MA[2] | +| |ma2 | ma[2] | +| |MA3 | MA[3] | +| |ma3 | ma[3] | +| |MA4 | MA[4] | +| |ma4 | ma[4] | +| |MA5 | MA[5] | +| |ma5 | ma[5] | +| |MA6 | MA[6] | +| |ma6 | ma[6] | +| |MA7 | MA[7] | +| |ma7 | ma[7] | +| |MA8 | MA[8] | +| |ma8 | ma[8] | +| |MA9 | MA[9] | +| |ma9 | ma[9] | +| |MA10 | MA[10] | +| |ma10 | ma[10] | +| |MA11 | MA[11] | +| |ma11 | ma[11] | +| |MA12 | MA[12] | +| |ma12 | ma[12] | +| |MA13 | MA[13] | +| |ma13 | ma[13] | +| |MA14 | MA[14] | +| |ma14 | ma[14] | +| |MD0 | MD[0] | +| |md0 | md[0] | +| |MD1 | MD[1] | +| |md1 | md[1] | +| |MD2 | MD[2] | +| |md2 | md[2] | +| |MD3 | MD[3] | +| |md3 | md[3] | +| |MD4 | MD[4] | +| |md4 | md[4] | +| |MD5 | MD[5] | +| |md5 | md[5] | +| |MD6 | MD[6] | +| |md6 | md[6] | +| |MD7 | MD[7] | +| |md7 | md[7] | +| |MD8 | MD[8] | +| |md8 | md[8] | +| |MD9 | MD[9] | +| |md9 | md[9] | +| |MD10 | MD[10] | +| |md10 | md[10] | +| |MD11 | MD[11] | +| |md11 | md[11] | +| |MD12 | MD[12] | +| |md12 | md[12] | +| |MD13 | MD[13] | +| |md13 | md[13] | +| |MD14 | MD[14] | +| |md14 | md[14] | +| |MD15 | MD[15] | +| |md15 | md[15] | +| |RA14 | RA[14] | +| |ra14 | ra[14] | +| |RA15 | RA[15] | +| |ra15 | ra[15] | +| |RA16 | RA[16] | +| |ra16 | ra[16] | +| |RA17 | RA[17] | +| |ra17 | ra[17] | +| |RAS_0 | RAS_[0] | +| |RAS_1 | RAS_[1] | +| |RASX_0 | RASX_[0] | +| |RASX_1 | RASX_[1] | +| |TG42 | TG[42] | +| |V_CS0 | V_CS[0] | +| |v_cs0 | v_cs[0] | +| |V_CS1 | V_CS[1] | +| |v_cs1 | v_cs[1] | +| |V_WR0 | V_WR[0] | +| |V_WR1 | V_WR[1] | +| |V_WR2 | V_WR[2] | +| |V_WR3 | V_WR[3] | +| |V_WRX0 | V_WRX[0] | +| |V_WRX1 | V_WRX[1] | +| |V_WRX2 | V_WRX[2] | +| |V_WRX3 | V_WRX[3] | +| |VA0 | VA[0] | +| |VA1 | VA[1] | +| |VA2 | VA[2] | +| |VA3 | VA[3] | +| |VA4 | VA[4] | +| |VA5 | VA[5] | +| |VA6 | VA[6] | +| |VA7 | VA[7] | +| |VA8 | VA[8] | +| |VA9 | VA[9] | +| |VA10 | VA[10] | +| |VA11 | VA[11] | +| |VA12 | VA[12] | +| |VA13 | VA[13] | +| |VA14 | VA[14] | +| |VA15 | VA[15] | +| |VD00 | VD[00] | +| |VD01 | VD[01] | +| |VD02 | VD[02] | +| |VD03 | VD[03] | +| |VD04 | VD[04] | +| |VD05 | VD[05] | +| |VD06 | VD[06] | +| |VD07 | VD[07] | +| |VD10 | VD[10] | +| |VD11 | VD[11] | +| |VD12 | VD[12] | +| |VD13 | VD[13] | +| |VD14 | VD[14] | +| |VD15 | VD[15] | +| |VD16 | VD[16] | +| |VD17 | VD[17] | +| |VD20 | VD[20] | +| |VD21 | VD[21] | +| |VD22 | VD[22] | +| |VD23 | VD[23] | +| |VD24 | VD[24] | +| |VD25 | VD[25] | +| |VD26 | VD[26] | +| |VD27 | VD[27] | +| |VD30 | VD[30] | +| |VD31 | VD[31] | +| |VD32 | VD[32] | +| |VD33 | VD[33] | +| |VD34 | VD[34] | +| |VD35 | VD[35] | +| |VD36 | VD[36] | +| |VD37 | VD[37] | +| |XA0 | XA[0] | +| |XA1 | XA[1] | +| |XA2 | XA[2] | +| |XA3 | XA[3] | +| "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_0" | acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][0] | +| "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_1" | acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][1] | +| "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_2" | acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][2] | +| "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_3" | acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][3] | +| "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_4" | acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][4] | +| "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_5" | acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][5] | +| "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_6" | acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][6] | +| "|acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment0_7" | acceler:ACC|lpm_ram_dp:RAM|altdpram:sram|segment[0][7] | +| "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_0" | ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][0] | +| "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_1" | ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][1] | +| "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_2" | ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][2] | +| "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_3" | ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][3] | +| "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_4" | ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][4] | +| "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_5" | ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][5] | +| "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_6" | ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][6] | +| "|ay:AY3|lpm_ram_dq:90|altram:sram|segment0_7" | ay:AY[3]|lpm_ram_dq:90|altram:sram|segment[0][7] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_0" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][0] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_1" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][1] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_2" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][2] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_3" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][3] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_4" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][4] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_5" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][5] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_6" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][6] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_7" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][7] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_8" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][8] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_9" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][9] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_10" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][10] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_11" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][11] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_12" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][12] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_13" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][13] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_14" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][14] | +| "|dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment0_15" | dcp:DECODE|lpm_ram_dp:MEM|altdpram:sram|segment[0][15] | +| "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_0" | kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][0] | +| "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_1" | kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][1] | +| "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_2" | kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][2] | +| "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_3" | kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][3] | +| "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_4" | kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][4] | +| "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_5" | kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][5] | +| "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_6" | kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][6] | +| "|kbd:KEYS|lpm_ram_dq:59|altram:sram|segment0_7" | kbd:KEYS|lpm_ram_dq:59|altram:sram|segment[0][7] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_5" | lpm_ram_dp:CBL|altdpram:sram|segment[0][5] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_6" | lpm_ram_dp:CBL|altdpram:sram|segment[0][6] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_7" | lpm_ram_dp:CBL|altdpram:sram|segment[0][7] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_8" | lpm_ram_dp:CBL|altdpram:sram|segment[0][8] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_9" | lpm_ram_dp:CBL|altdpram:sram|segment[0][9] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_10" | lpm_ram_dp:CBL|altdpram:sram|segment[0][10] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_11" | lpm_ram_dp:CBL|altdpram:sram|segment[0][11] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_12" | lpm_ram_dp:CBL|altdpram:sram|segment[0][12] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_13" | lpm_ram_dp:CBL|altdpram:sram|segment[0][13] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_14" | lpm_ram_dp:CBL|altdpram:sram|segment[0][14] | +| "|lpm_ram_dp:CBL|altdpram:sram|segment0_15" | lpm_ram_dp:CBL|altdpram:sram|segment[0][15] | +| "|video2:SVIDEO|D_PIC00" | video2:SVIDEO|D_PIC[00] | +| "|video2:SVIDEO|D_PIC01" | video2:SVIDEO|D_PIC[01] | +| "|video2:SVIDEO|D_PIC02" | video2:SVIDEO|D_PIC[02] | +| "|video2:SVIDEO|D_PIC03" | video2:SVIDEO|D_PIC[03] | +| "|video2:SVIDEO|D_PIC04" | video2:SVIDEO|D_PIC[04] | +| "|video2:SVIDEO|D_PIC05" | video2:SVIDEO|D_PIC[05] | +| "|video2:SVIDEO|D_PIC06" | video2:SVIDEO|D_PIC[06] | +| "|video2:SVIDEO|D_PIC07" | video2:SVIDEO|D_PIC[07] | +| "|video2:SVIDEO|SVA0" | video2:SVIDEO|SVA[0] | +| "|video2:SVIDEO|SVA1" | video2:SVIDEO|SVA[1] | +| "|video2:SVIDEO|SVA2" | video2:SVIDEO|SVA[2] | +| "|video2:SVIDEO|SVA3" | video2:SVIDEO|SVA[3] | +| "|video2:SVIDEO|SVA4" | video2:SVIDEO|SVA[4] | +| "|video2:SVIDEO|SVA5" | video2:SVIDEO|SVA[5] | +| "|video2:SVIDEO|SVA10" | video2:SVIDEO|SVA[10] | +| "|video2:SVIDEO|SVA11" | video2:SVIDEO|SVA[11] | +| "|video2:SVIDEO|SVA12" | video2:SVIDEO|SVA[12] | +| "|video2:SVIDEO|V_CSX0" | video2:SVIDEO|V_CSX[0] | +| "|video2:SVIDEO|V_CSX1" | video2:SVIDEO|V_CSX[1] | +| "|video2:SVIDEO|V_CSX2" | video2:SVIDEO|V_CSX[2] | +| "|video2:SVIDEO|V_WEM2" | video2:SVIDEO|V_WEM[2] | +| "|video2:SVIDEO|V_WEY0" | video2:SVIDEO|V_WEY[0] | +| "|video2:SVIDEO|V_WEY1" | video2:SVIDEO|V_WEY[1] | +| "|video2:SVIDEO|V_WEY2" | video2:SVIDEO|V_WEY[2] | +| "|video2:SVIDEO|V_WEY3" | video2:SVIDEO|V_WEY[3] | +| "|video2:SVIDEO|V_WR_0" | video2:SVIDEO|V_WR_[0] | +| "|video2:SVIDEO|V_WR_1" | video2:SVIDEO|V_WR_[1] | +| "|video2:SVIDEO|V_WR_2" | video2:SVIDEO|V_WR_[2] | +| "|video2:SVIDEO|V_WR_3" | video2:SVIDEO|V_WR_[3] | +| "|video2:SVIDEO|V_WRM2" | video2:SVIDEO|V_WRM[2] | ++--------------------------------------------------------+--------------------------------------------------------+ + + diff --git a/src/altera/quartus/max/db/add_sub_uch.tdf b/src/altera/quartus/max/db/add_sub_uch.tdf new file mode 100644 index 0000000..9f3f94c --- /dev/null +++ b/src/altera/quartus/max/db/add_sub_uch.tdf @@ -0,0 +1,42 @@ +--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=5 ONE_INPUT_IS_CONSTANT="YES" dataa datab result +--VERSION_BEGIN 9.0SP2 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ VERSION_END + + +-- Copyright (C) 1991-2009 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION carry_sum (cin, sin) +RETURNS ( cout, sout); + +--synthesis_resources = lut 5 +SUBDESIGN add_sub_uch +( + dataa[4..0] : input; + datab[4..0] : input; + result[4..0] : output; +) +VARIABLE + add_sub_cella[4..0] : carry_sum; + datab_node[4..0] : WIRE; + main_cin_wire : WIRE; + +BEGIN + add_sub_cella[].cin = ( ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire))); + add_sub_cella[].sin = ( ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire)); + datab_node[] = datab[]; + main_cin_wire = B"0"; + result[] = add_sub_cella[].sout; +END; +--VALID FILE diff --git a/src/altera/quartus/max/db/prev_cmp_sp2_max.asm.qmsg b/src/altera/quartus/max/db/prev_cmp_sp2_max.asm.qmsg new file mode 100644 index 0000000..7340a2f --- /dev/null +++ b/src/altera/quartus/max/db/prev_cmp_sp2_max.asm.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:23:30 2022 " "Info: Processing started: Sun Aug 28 03:23:30 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "199 " "Info: Peak virtual memory: 199 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:23:31 2022 " "Info: Processing ended: Sun Aug 28 03:23:31 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/prev_cmp_sp2_max.eda.qmsg b/src/altera/quartus/max/db/prev_cmp_sp2_max.eda.qmsg new file mode 100644 index 0000000..c64727f --- /dev/null +++ b/src/altera/quartus/max/db/prev_cmp_sp2_max.eda.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:26:23 2022 " "Info: Processing started: Sun Aug 28 03:26:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Warning" "WQNETO_NO_OUTPUT_FILES" "" "Warning: Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." { } { } 0 0 "Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Peak virtual memory: 163 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:26:23 2022 " "Info: Processing ended: Sun Aug 28 03:26:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/prev_cmp_sp2_max.fit.qmsg b/src/altera/quartus/max/db/prev_cmp_sp2_max.fit.qmsg new file mode 100644 index 0000000..900bf36 --- /dev/null +++ b/src/altera/quartus/max/db/prev_cmp_sp2_max.fit.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:23:29 2022 " "Info: Processing started: Sun Aug 28 03:23:29 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "sp2_max EPM7128STC100-10 " "Info: Selected device EPM7128STC100-10 for design \"sp2_max\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "10K_D\[0\] " "Warning: Node \"10K_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "10K_D\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLK\[14\] " "Warning: Node \"CLK\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[0\] " "Warning: Node \"D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FDD_C0 " "Warning: Node \"FDD_C0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FDD_C0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FDD_C1 " "Warning: Node \"FDD_C1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FDD_C1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FDD_C2 " "Warning: Node \"FDD_C2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FDD_C2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HDD_C0 " "Warning: Node \"HDD_C0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_C0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HDD_C1 " "Warning: Node \"HDD_C1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_C1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HDD_C2 " "Warning: Node \"HDD_C2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_C2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HDD_C3 " "Warning: Node \"HDD_C3\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_C3" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SINC_\[1\] " "Warning: Node \"SINC_\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SINC_\[2\] " "Warning: Node \"SINC_\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TR\[43\] " "Warning: Node \"TR\[43\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TR\[43\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UNUSED\[33\] " "Warning: Node \"UNUSED\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "UNUSED\[33\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UNUSED\[53\] " "Warning: Node \"UNUSED\[53\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "UNUSED\[53\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UNUSED\[65\] " "Warning: Node \"UNUSED\[65\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "UNUSED\[65\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UNUSED\[78\] " "Warning: Node \"UNUSED\[78\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "UNUSED\[78\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XA0 " "Warning: Node \"XA0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XA0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XA1 " "Warning: Node \"XA1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XA1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XA2 " "Warning: Node \"XA2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XA2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XHD1_CS1 " "Warning: Node \"XHD1_CS1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XHD1_CS1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XHD1_CS2 " "Warning: Node \"XHD1_CS2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XHD1_CS2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XHD2_CS1 " "Warning: Node \"XHD2_CS1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XHD2_CS1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XHD2_CS2 " "Warning: Node \"XHD2_CS2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XHD2_CS2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} } { } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 25 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:23:29 2022 " "Info: Processing ended: Sun Aug 28 03:23:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/prev_cmp_sp2_max.map.qmsg b/src/altera/quartus/max/db/prev_cmp_sp2_max.map.qmsg new file mode 100644 index 0000000..28269d0 --- /dev/null +++ b/src/altera/quartus/max/db/prev_cmp_sp2_max.map.qmsg @@ -0,0 +1,56 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:23:26 2022 " "Info: Processing started: Sun Aug 28 03:23:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "sp2_max.tdf 1 1 " "Warning: Using design file sp2_max.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SP2_MAX " "Info: Found entity 1: SP2_MAX" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 18 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "sp2_max " "Info: Elaborating entity \"sp2_max\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "CTV8C " "Warning: Variable or input pin \"CTV8C\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 167 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "XA " "Warning: Variable or input pin \"XA\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 52 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "VGA_IN " "Warning: Variable or input pin \"VGA_IN\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 70 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "SINC_IN " "Warning: Variable or input pin \"SINC_IN\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 75 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "XHR_RDY " "Warning: Variable or input pin \"XHR_RDY\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 83 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED65 " "Warning: Variable or input pin \"UNUSED65\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 88 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED33 " "Warning: Variable or input pin \"UNUSED33\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 89 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED1 " "Warning: Variable or input pin \"UNUSED1\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 90 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED2 " "Warning: Variable or input pin \"UNUSED2\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 91 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED5 " "Warning: Variable or input pin \"UNUSED5\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 92 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED7 " "Warning: Variable or input pin \"UNUSED7\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 93 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED22 " "Warning: Variable or input pin \"UNUSED22\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 94 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED24 " "Warning: Variable or input pin \"UNUSED24\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 95 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED27 " "Warning: Variable or input pin \"UNUSED27\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 96 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED28 " "Warning: Variable or input pin \"UNUSED28\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 97 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED49 " "Warning: Variable or input pin \"UNUSED49\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 98 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED50 " "Warning: Variable or input pin \"UNUSED50\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 99 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED53 " "Warning: Variable or input pin \"UNUSED53\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 100 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED55 " "Warning: Variable or input pin \"UNUSED55\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 101 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED63 " "Warning: Variable or input pin \"UNUSED63\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 102 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED70 " "Warning: Variable or input pin \"UNUSED70\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 103 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED72 " "Warning: Variable or input pin \"UNUSED72\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 104 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED77 " "Warning: Variable or input pin \"UNUSED77\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 105 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED78 " "Warning: Variable or input pin \"UNUSED78\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 106 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "CT\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"CT\[0\]~0\"" { } { { "sp2_max.tdf" "CT\[0\]~0" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 119 4 0 } } } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IOPT_LPM_COUNTER_INFERRED" "CTV\[0\]~9 9 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: \"CTV\[0\]~9\"" { } { { "sp2_max.tdf" "CTV\[0\]~9" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 121 5 0 } } } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IOPT_LPM_COUNTER_INFERRED" "CTH\[0\]~7 6 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: \"CTH\[0\]~7\"" { } { { "sp2_max.tdf" "CTH\[0\]~7" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 120 5 0 } } } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 -1} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "op_6 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"op_6\"" { } { } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:CT_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:CT_rtl_0\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:CT_rtl_0 " "Info: Instantiated megafunction \"lpm_counter:CT_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:CTV_rtl_1 " "Info: Elaborated megafunction instantiation \"lpm_counter:CTV_rtl_1\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:CTV_rtl_1 " "Info: Instantiated megafunction \"lpm_counter:CTV_rtl_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 9 " "Info: Parameter \"LPM_WIDTH\" = \"9\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:CTH_rtl_2 " "Info: Elaborated megafunction instantiation \"lpm_counter:CTH_rtl_2\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:CTH_rtl_2 " "Info: Instantiated megafunction \"lpm_counter:CTH_rtl_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 6 " "Info: Parameter \"LPM_WIDTH\" = \"6\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:op_6 " "Info: Instantiated megafunction \"lpm_add_sub:op_6\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 202 5 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 203 10 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 189 5 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|altshift:result_ext_latency_ffs lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|altshift:carry_ext_latency_ffs lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "6 " "Info: Ignored 6 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "6 " "Info: Ignored 6 SOFT buffer(s)" { } { } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0 "" 0 -1} } { } 0 0 "Ignored %1!d! buffer(s)" 0 0 "" 0 -1} +{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 451 13 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 450 13 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 449 13 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 445 13 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 446 12 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 447 12 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 479 27 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 478 27 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 489 20 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 495 20 0 } } } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 -1} +{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "\$00005 " "Warning: Node \"\$00005\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 206 12 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "\$00006 " "Warning: Node \"\$00006\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 207 12 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1} +{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "BEEP GND " "Warning (13410): Pin \"BEEP\" is stuck at GND" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 333 2 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DENS_X VCC " "Warning (13410): Pin \"DENS_X\" is stuck at VCC" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 345 2 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HD_CS GND " "Warning (13410): Pin \"HD_CS\" is stuck at GND" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 458 9 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1} +{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "TG42_IN " "Info: Promoted clock signal driven by pin \"TG42_IN\" to global clock signal" { } { } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "" 0 -1} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "EPM_RES " "Info: Promoted clear signal driven by pin \"EPM_RES\" to global clear signal" { } { } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "" 0 -1} } { } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0 "" 0 -1} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "XCT\[2\] " "Info: Register \"XCT\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "25 " "Warning: Design contains 25 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "XA\[0\] " "Warning (15610): No output dependent on input pin \"XA\[0\]\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 52 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "XA\[1\] " "Warning (15610): No output dependent on input pin \"XA\[1\]\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 52 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "XA\[2\] " "Warning (15610): No output dependent on input pin \"XA\[2\]\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 52 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "VGA_IN " "Warning (15610): No output dependent on input pin \"VGA_IN\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 70 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SINC_IN " "Warning (15610): No output dependent on input pin \"SINC_IN\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 75 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "XHR_RDY " "Warning (15610): No output dependent on input pin \"XHR_RDY\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 83 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED65 " "Warning (15610): No output dependent on input pin \"UNUSED65\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 88 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED33 " "Warning (15610): No output dependent on input pin \"UNUSED33\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 89 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED1 " "Warning (15610): No output dependent on input pin \"UNUSED1\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 90 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED2 " "Warning (15610): No output dependent on input pin \"UNUSED2\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 91 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED5 " "Warning (15610): No output dependent on input pin \"UNUSED5\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 92 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED7 " "Warning (15610): No output dependent on input pin \"UNUSED7\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 93 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED22 " "Warning (15610): No output dependent on input pin \"UNUSED22\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 94 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED24 " "Warning (15610): No output dependent on input pin \"UNUSED24\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 95 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED27 " "Warning (15610): No output dependent on input pin \"UNUSED27\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 96 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED28 " "Warning (15610): No output dependent on input pin \"UNUSED28\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 97 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED49 " "Warning (15610): No output dependent on input pin \"UNUSED49\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 98 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED50 " "Warning (15610): No output dependent on input pin \"UNUSED50\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 99 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED53 " "Warning (15610): No output dependent on input pin \"UNUSED53\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 100 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED55 " "Warning (15610): No output dependent on input pin \"UNUSED55\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 101 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED63 " "Warning (15610): No output dependent on input pin \"UNUSED63\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 102 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED70 " "Warning (15610): No output dependent on input pin \"UNUSED70\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 103 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED72 " "Warning (15610): No output dependent on input pin \"UNUSED72\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 104 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED77 " "Warning (15610): No output dependent on input pin \"UNUSED77\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 105 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED78 " "Warning (15610): No output dependent on input pin \"UNUSED78\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 106 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "163 " "Info: Implemented 163 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "46 " "Info: Implemented 46 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Info: Implemented 30 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "4 " "Info: Implemented 4 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_MCELLS" "74 " "Info: Implemented 74 macrocells" { } { } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_SEXPS" "9 " "Info: Implemented 9 shareable expanders" { } { } 0 0 "Implemented %1!d! shareable expanders" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 58 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 58 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:23:28 2022 " "Info: Processing ended: Sun Aug 28 03:23:28 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/prev_cmp_sp2_max.qmsg b/src/altera/quartus/max/db/prev_cmp_sp2_max.qmsg new file mode 100644 index 0000000..c64727f --- /dev/null +++ b/src/altera/quartus/max/db/prev_cmp_sp2_max.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:26:23 2022 " "Info: Processing started: Sun Aug 28 03:26:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Warning" "WQNETO_NO_OUTPUT_FILES" "" "Warning: Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." { } { } 0 0 "Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Peak virtual memory: 163 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:26:23 2022 " "Info: Processing ended: Sun Aug 28 03:26:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/prev_cmp_sp2_max.tan.qmsg b/src/altera/quartus/max/db/prev_cmp_sp2_max.tan.qmsg new file mode 100644 index 0000000..302f5b5 --- /dev/null +++ b/src/altera/quartus/max/db/prev_cmp_sp2_max.tan.qmsg @@ -0,0 +1,31 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:23:32 2022 " "Info: Processing started: Sun Aug 28 03:23:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" { } { } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0 -1} +{ "Warning" "WTAN_SCC_LOOP" "2 " "Warning: Found combinational loop of 2 nodes" { { "Warning" "WTAN_SCC_NODE" "RDAT_X~11 " "Warning: Node \"RDAT_X~11\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "RDAT_X~6 " "Warning: Node \"RDAT_X~6\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1} +{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "TURBING~5 " "Warning: Node \"TURBING~5\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1} +{ "Warning" "WTAN_SCC_LOOP" "3 " "Warning: Found combinational loop of 3 nodes" { { "Warning" "WTAN_SCC_NODE" "THDD~2 " "Warning: Node \"THDD~2\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "NTHDD~13 " "Warning: Node \"NTHDD~13\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "NTHDD~11 " "Warning: Node \"NTHDD~11\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1} +{ "Warning" "WTAN_SCC_LOOP" "2 " "Warning: Found combinational loop of 2 nodes" { { "Warning" "WTAN_SCC_NODE" "NT320~12 " "Warning: Node \"NT320~12\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 426 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "NT320~2 " "Warning: Node \"NT320~2\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 426 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 426 2 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1} +{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "TG42_IN " "Info: Assuming node \"TG42_IN\" is an undefined clock" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TG42_IN" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "STE " "Info: Assuming node \"STE\" is an undefined clock" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "STE" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "RSTB " "Info: Assuming node \"RSTB\" is an undefined clock" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "RSTB" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "WSTB " "Info: Assuming node \"WSTB\" is an undefined clock" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "WSTB" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} +{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "CT_WG1~8bal " "Info: Detected gated clock \"CT_WG1~8bal\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 304 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG1~8bal" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "STWG\[2\] " "Info: Detected ripple clock \"STWG\[2\]\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "STWG\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "STWG\[2\]~6bal " "Info: Detected gated clock \"STWG\[2\]~6bal\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "STWG\[2\]~6bal" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "CT_WG~6 " "Info: Detected gated clock \"CT_WG~6\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG~6" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "CT_WG~5 " "Info: Detected gated clock \"CT_WG~5\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG~5" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "CT_WG~4 " "Info: Detected gated clock \"CT_WG~4\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG~4" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "CT_WG " "Info: Detected ripple clock \"CT_WG\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "TURBING~5 " "Info: Detected gated clock \"TURBING~5\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TURBING~5" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "FDD_1440 " "Info: Detected ripple clock \"FDD_1440\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FDD_1440" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "HDD_CLK " "Info: Detected ripple clock \"HDD_CLK\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_CLK" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:CT_rtl_0\|dffs\[3\] " "Info: Detected ripple clock \"lpm_counter:CT_rtl_0\|dffs\[3\]\" as buffer" { } { { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:CT_rtl_0\|dffs\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "SINC_HT " "Info: Detected ripple clock \"SINC_HT\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 123 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_HT" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "SINC_VT " "Info: Detected ripple clock \"SINC_VT\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 124 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_VT" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:CT_rtl_0\|dffs\[0\] " "Info: Detected ripple clock \"lpm_counter:CT_rtl_0\|dffs\[0\]\" as buffer" { } { { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:CT_rtl_0\|dffs\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~4 " "Info: Detected gated clock \"XCT\[2\]~4\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~4" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~3 " "Info: Detected gated clock \"XCT\[2\]~3\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~3" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~12 " "Info: Detected gated clock \"XCT\[2\]~12\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~12" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~11 " "Info: Detected gated clock \"XCT\[2\]~11\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~11" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "XCT\[0\] " "Info: Detected ripple clock \"XCT\[0\]\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "XCT\[1\] " "Info: Detected ripple clock \"XCT\[1\]\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_SLACK_RESULT" "TG42_IN register /RESET register \$00051 -47.0 ns " "Info: Slack time is -47.0 ns for clock \"TG42_IN\" between source register \"/RESET\" and destination register \"\$00051\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "9.62 MHz 104.0 ns " "Info: Fmax is 9.62 MHz (period= 104.0 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-25.000 ns + Largest register register " "Info: + Largest register to register requirement is -25.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination TG42_IN 10.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"TG42_IN\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source TG42_IN 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"TG42_IN\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-26.000 ns + Largest " "Info: + Largest clock skew is -26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"TG42_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns \$00051 2 REG LC121 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC121; Fanout = 1; REG Node = '\$00051'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { TG42_IN $00051 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN source 27.500 ns - Longest register " "Info: - Longest clock path from clock \"TG42_IN\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 6.500 ns XCT\[2\]~4 2 COMB SEXP49 1 " "Info: 2: + IC(0.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP49; Fanout = 1; COMB Node = 'XCT\[2\]~4'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { TG42_IN XCT[2]~4 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 13.500 ns XCT\[1\] 3 REG LC56 18 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 13.500 ns; Loc. = LC56; Fanout = 18; REG Node = 'XCT\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { XCT[2]~4 XCT[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 21.500 ns lpm_counter:CT_rtl_0\|dffs\[3\] 4 REG LC53 10 " "Info: 4: + IC(1.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC53; Fanout = 10; REG Node = 'lpm_counter:CT_rtl_0\|dffs\[3\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { XCT[1] lpm_counter:CT_rtl_0|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns /RESET 5 REG LC85 19 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC85; Fanout = 19; REG Node = '/RESET'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 173 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 173 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.000 ns - Longest register register " "Info: - Longest register to register delay is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns /RESET 1 REG LC85 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC85; Fanout = 19; REG Node = '/RESET'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { /RESET } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 173 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(16.000 ns) 16.000 ns THDD~2 2 COMB LOOP LC114 14 " "Info: 2: + IC(0.000 ns) + CELL(16.000 ns) = 16.000 ns; Loc. = LC114; Fanout = 14; COMB LOOP Node = 'THDD~2'" { { "Info" "ITDB_PART_OF_SCC" "NTHDD~11 LC119 " "Info: Loc. = LC119; Node \"NTHDD~11\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "THDD~2 LC114 " "Info: Loc. = LC114; Node \"THDD~2\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "NTHDD~13 LC118 " "Info: Loc. = LC118; Node \"NTHDD~13\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { /RESET THDD~2 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 22.000 ns \$00051 3 REG LC121 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 22.000 ns; Loc. = LC121; Fanout = 1; REG Node = '\$00051'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { THDD~2 $00051 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns ( 95.45 % ) " "Info: Total cell delay = 21.000 ns ( 95.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 4.55 % ) " "Info: Total interconnect delay = 1.000 ns ( 4.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { /RESET THDD~2 $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { /RESET {} THDD~2 {} $00051 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 16.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { /RESET THDD~2 $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { /RESET {} THDD~2 {} $00051 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 16.000ns 5.000ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'TG42_IN' 57 " "Warning: Can't achieve timing requirement Clock Setup: 'TG42_IN' along 57 path(s). See Report window for details." { } { } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_SLACK_RESULT" "STE register LR_T\[0\] register REG_P\[2\] -21.0 ns " "Info: Slack time is -21.0 ns for clock \"STE\" between source register \"LR_T\[0\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "19.23 MHz 52.0 ns " "Info: Fmax is 19.23 MHz (period= 52.0 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-15.000 ns + Largest register register " "Info: + Largest register to register requirement is -15.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination STE 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"STE\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source STE 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"STE\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-16.000 ns + Largest " "Info: + Largest clock skew is -16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE destination 27.500 ns + Shortest register " "Info: + Shortest clock path from clock \"STE\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE source 43.500 ns - Longest register " "Info: - Longest clock path from clock \"STE\" to source register is 43.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns STWG\[2\]~6bal 5 COMB LC16 3 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 37.500 ns STWG\[2\] 6 REG LC19 6 " "Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 43.500 ns LR_T\[0\] 7 REG LC10 4 " "Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.500 ns ( 90.80 % ) " "Info: Total cell delay = 39.500 ns ( 90.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 9.20 % ) " "Info: Total interconnect delay = 4.000 ns ( 9.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Longest register register " "Info: - Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LR_T\[0\] 1 REG LC10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'STE' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'STE' along 6 path(s). See Report window for details." { } { } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_SLACK_RESULT" "RSTB register LR_T\[0\] register REG_P\[2\] -21.0 ns " "Info: Slack time is -21.0 ns for clock \"RSTB\" between source register \"LR_T\[0\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "19.23 MHz 52.0 ns " "Info: Fmax is 19.23 MHz (period= 52.0 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-15.000 ns + Largest register register " "Info: + Largest register to register requirement is -15.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination RSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"RSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source RSTB 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"RSTB\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-16.000 ns + Largest " "Info: + Largest clock skew is -16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB destination 27.500 ns + Shortest register " "Info: + Shortest clock path from clock \"RSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB source 43.500 ns - Longest register " "Info: - Longest clock path from clock \"RSTB\" to source register is 43.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns STWG\[2\]~6bal 5 COMB LC16 3 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 37.500 ns STWG\[2\] 6 REG LC19 6 " "Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 43.500 ns LR_T\[0\] 7 REG LC10 4 " "Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.500 ns ( 90.80 % ) " "Info: Total cell delay = 39.500 ns ( 90.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 9.20 % ) " "Info: Total interconnect delay = 4.000 ns ( 9.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Longest register register " "Info: - Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LR_T\[0\] 1 REG LC10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'RSTB' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'RSTB' along 6 path(s). See Report window for details." { } { } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_SLACK_RESULT" "WSTB register LR_T\[0\] register REG_P\[2\] -21.0 ns " "Info: Slack time is -21.0 ns for clock \"WSTB\" between source register \"LR_T\[0\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "19.23 MHz 52.0 ns " "Info: Fmax is 19.23 MHz (period= 52.0 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-15.000 ns + Largest register register " "Info: + Largest register to register requirement is -15.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination WSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"WSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source WSTB 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"WSTB\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-16.000 ns + Largest " "Info: + Largest clock skew is -16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB destination 27.500 ns + Shortest register " "Info: + Shortest clock path from clock \"WSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB source 43.500 ns - Longest register " "Info: - Longest clock path from clock \"WSTB\" to source register is 43.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns STWG\[2\]~6bal 5 COMB LC16 3 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 37.500 ns STWG\[2\] 6 REG LC19 6 " "Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 43.500 ns LR_T\[0\] 7 REG LC10 4 " "Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.500 ns ( 90.80 % ) " "Info: Total cell delay = 39.500 ns ( 90.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 9.20 % ) " "Info: Total interconnect delay = 4.000 ns ( 9.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Longest register register " "Info: - Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LR_T\[0\] 1 REG LC10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'WSTB' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'WSTB' along 6 path(s). See Report window for details." { } { } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "TG42_IN register FDD_1440 register \$00021 -12.2 ns " "Info: Minimum slack time is -12.2 ns for clock \"TG42_IN\" between source register \"FDD_1440\" and destination register \"\$00021\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.800 ns + Shortest register register " "Info: + Shortest register to register delay is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FDD_1440 1 REG LC91 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.800 ns) 8.800 ns RDAT_X~6 2 COMB LOOP LC21 6 " "Info: 2: + IC(0.000 ns) + CELL(8.800 ns) = 8.800 ns; Loc. = LC21; Fanout = 6; COMB LOOP Node = 'RDAT_X~6'" { { "Info" "ITDB_PART_OF_SCC" "RDAT_X~6 LC21 " "Info: Loc. = LC21; Node \"RDAT_X~6\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~6 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "RDAT_X~11 LC20 " "Info: Loc. = LC20; Node \"RDAT_X~11\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~11 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~11 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.800 ns" { FDD_1440 RDAT_X~6 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.800 ns \$00021 3 REG LC17 12 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.800 ns; Loc. = LC17; Fanout = 12; REG Node = '\$00021'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { RDAT_X~6 $00021 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 328 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.800 ns ( 93.24 % ) " "Info: Total cell delay = 13.800 ns ( 93.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 6.76 % ) " "Info: Total interconnect delay = 1.000 ns ( 6.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { FDD_1440 RDAT_X~6 $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { FDD_1440 {} RDAT_X~6 {} $00021 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 8.800ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "27.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 27.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination TG42_IN 10.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"TG42_IN\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source TG42_IN 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"TG42_IN\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "26.000 ns + Smallest " "Info: + Smallest clock skew is 26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 35.500 ns + Longest register " "Info: + Longest clock path from clock \"TG42_IN\" to destination register is 35.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 6.500 ns XCT\[2\]~4 2 COMB SEXP49 1 " "Info: 2: + IC(0.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP49; Fanout = 1; COMB Node = 'XCT\[2\]~4'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { TG42_IN XCT[2]~4 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 13.500 ns XCT\[1\] 3 REG LC56 18 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 13.500 ns; Loc. = LC56; Fanout = 18; REG Node = 'XCT\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { XCT[2]~4 XCT[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 21.500 ns lpm_counter:CT_rtl_0\|dffs\[0\] 4 REG LC122 9 " "Info: 4: + IC(1.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC122; Fanout = 9; REG Node = 'lpm_counter:CT_rtl_0\|dffs\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { XCT[1] lpm_counter:CT_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns CT_WG1~8bal 5 COMB LC28 7 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC28; Fanout = 7; COMB Node = 'CT_WG1~8bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 304 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 35.500 ns \$00021 6 REG LC17 12 " "Info: 6: + IC(1.000 ns) + CELL(5.000 ns) = 35.500 ns; Loc. = LC17; Fanout = 12; REG Node = '\$00021'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG1~8bal $00021 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 328 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "32.500 ns ( 91.55 % ) " "Info: Total cell delay = 32.500 ns ( 91.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 8.45 % ) " "Info: Total interconnect delay = 3.000 ns ( 8.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN source 9.500 ns - Shortest register " "Info: - Shortest clock path from clock \"TG42_IN\" to source register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns HDD_CLK 2 REG LC88 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TG42_IN HDD_CLK } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns FDD_1440 3 REG LC91 13 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { HDD_CLK FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 328 9 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { FDD_1440 RDAT_X~6 $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { FDD_1440 {} RDAT_X~6 {} $00021 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 8.800ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "TG42_IN 48 " "Warning: Can't achieve minimum setup and hold requirement TG42_IN along 48 path(s). See Report window for details." { } { } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "STE register REG_P\[1\] register REG_P\[2\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"STE\" between source register \"REG_P\[1\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_P\[1\] 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination STE 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"STE\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source STE 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"STE\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE destination 27.500 ns + Longest register " "Info: + Longest clock path from clock \"STE\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE source 27.500 ns - Shortest register " "Info: - Shortest clock path from clock \"STE\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[1\] 5 REG LC2 3 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "RSTB register REG_P\[1\] register REG_P\[2\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"RSTB\" between source register \"REG_P\[1\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_P\[1\] 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination RSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"RSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source RSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"RSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB destination 27.500 ns + Longest register " "Info: + Longest clock path from clock \"RSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB source 27.500 ns - Shortest register " "Info: - Shortest clock path from clock \"RSTB\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[1\] 5 REG LC2 3 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "WSTB register REG_P\[1\] register REG_P\[2\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"WSTB\" between source register \"REG_P\[1\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_P\[1\] 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination WSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"WSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source WSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"WSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB destination 27.500 ns + Longest register " "Info: + Longest clock path from clock \"WSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB source 27.500 ns - Shortest register " "Info: - Shortest clock path from clock \"WSTB\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[1\] 5 REG LC2 3 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Info" "ITDB_TSU_RESULT" "\$00052 FDD_C\[2\] TG42_IN 23.800 ns register " "Info: tsu for register \"\$00052\" (data pin = \"FDD_C\[2\]\", clock pin = \"TG42_IN\") is 23.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.300 ns + Longest pin register " "Info: + Longest pin to register delay is 23.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns FDD_C\[2\] 1 PIN PIN_46 20 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_46; Fanout = 20; PIN Node = 'FDD_C\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FDD_C[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 59 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(16.800 ns) 17.300 ns NTHDD~11 2 COMB LOOP LC119 10 " "Info: 2: + IC(0.000 ns) + CELL(16.800 ns) = 17.300 ns; Loc. = LC119; Fanout = 10; COMB LOOP Node = 'NTHDD~11'" { { "Info" "ITDB_PART_OF_SCC" "NTHDD~11 LC119 " "Info: Loc. = LC119; Node \"NTHDD~11\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "THDD~2 LC114 " "Info: Loc. = LC114; Node \"THDD~2\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "NTHDD~13 LC118 " "Info: Loc. = LC118; Node \"NTHDD~13\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "16.800 ns" { FDD_C[2] NTHDD~11 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 23.300 ns \$00052 3 REG LC123 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 23.300 ns; Loc. = LC123; Fanout = 1; REG Node = '\$00052'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { NTHDD~11 $00052 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "22.300 ns ( 95.71 % ) " "Info: Total cell delay = 22.300 ns ( 95.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 4.29 % ) " "Info: Total interconnect delay = 1.000 ns ( 4.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "23.300 ns" { FDD_C[2] NTHDD~11 $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "23.300 ns" { FDD_C[2] {} FDD_C[2]~out {} NTHDD~11 {} $00052 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 16.800ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"TG42_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns \$00052 2 REG LC123 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC123; Fanout = 1; REG Node = '\$00052'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { TG42_IN $00052 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00052 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "23.300 ns" { FDD_C[2] NTHDD~11 $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "23.300 ns" { FDD_C[2] {} FDD_C[2]~out {} NTHDD~11 {} $00052 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 16.800ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00052 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TCO_RESULT" "TG42_IN CLK_WG STWG\[2\] 50.000 ns register " "Info: tco from clock \"TG42_IN\" to destination pin \"CLK_WG\" through register \"STWG\[2\]\" is 50.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN source 46.500 ns + Longest register " "Info: + Longest clock path from clock \"TG42_IN\" to source register is 46.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns HDD_CLK 2 REG LC88 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TG42_IN HDD_CLK } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.500 ns FDD_1440 3 REG LC91 13 " "Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 11.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { HDD_CLK FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 19.500 ns TURBING~5 4 COMB LOOP LC32 3 " "Info: 4: + IC(0.000 ns) + CELL(8.000 ns) = 19.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { FDD_1440 TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 25.500 ns CT_WG~6 5 COMB SEXP17 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 25.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 32.500 ns CT_WG 6 REG LC26 8 " "Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 32.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 40.500 ns STWG\[2\]~6bal 7 COMB LC16 3 " "Info: 7: + IC(1.000 ns) + CELL(7.000 ns) = 40.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 46.500 ns STWG\[2\] 8 REG LC19 6 " "Info: 8: + IC(1.000 ns) + CELL(5.000 ns) = 46.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "42.500 ns ( 91.40 % ) " "Info: Total cell delay = 42.500 ns ( 91.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 8.60 % ) " "Info: Total interconnect delay = 4.000 ns ( 8.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "46.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "46.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STWG\[2\] 1 REG LC19 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_WG 2 PIN PIN_13 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'CLK_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { STWG[2] CLK_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 299 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { STWG[2] CLK_WG } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { STWG[2] {} CLK_WG {} } { 0.000ns 0.000ns } { 0.000ns 1.500ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "46.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "46.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { STWG[2] CLK_WG } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { STWG[2] {} CLK_WG {} } { 0.000ns 0.000ns } { 0.000ns 1.500ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TPD_RESULT" "TG42_IN TG42_OUT 10.000 ns Longest " "Info: Longest tpd from source pin \"TG42_IN\" to destination pin \"TG42_OUT\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 8.500 ns \$00003~3 2 COMB LC128 1 " "Info: 2: + IC(0.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC128; Fanout = 1; COMB Node = '\$00003~3'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { TG42_IN $00003~3 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 183 14 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 10.000 ns TG42_OUT 3 PIN PIN_85 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 10.000 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'TG42_OUT'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { $00003~3 TG42_OUT } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 183 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 100.00 % ) " "Info: Total cell delay = 10.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { TG42_IN $00003~3 TG42_OUT } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { TG42_IN {} TG42_IN~out {} $00003~3 {} TG42_OUT {} } { 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 7.000ns 1.500ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_TH_RESULT" "LR_T\[0\] SR TG42_IN 51.000 ns register " "Info: th for register \"LR_T\[0\]\" (data pin = \"SR\", clock pin = \"TG42_IN\") is 51.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 54.500 ns + Longest register " "Info: + Longest clock path from clock \"TG42_IN\" to destination register is 54.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns HDD_CLK 2 REG LC88 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TG42_IN HDD_CLK } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.500 ns FDD_1440 3 REG LC91 13 " "Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 11.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { HDD_CLK FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 19.500 ns TURBING~5 4 COMB LOOP LC32 3 " "Info: 4: + IC(0.000 ns) + CELL(8.000 ns) = 19.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { FDD_1440 TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 25.500 ns CT_WG~6 5 COMB SEXP17 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 25.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 32.500 ns CT_WG 6 REG LC26 8 " "Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 32.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 40.500 ns STWG\[2\]~6bal 7 COMB LC16 3 " "Info: 7: + IC(1.000 ns) + CELL(7.000 ns) = 40.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 48.500 ns STWG\[2\] 8 REG LC19 6 " "Info: 8: + IC(1.000 ns) + CELL(7.000 ns) = 48.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 54.500 ns LR_T\[0\] 9 REG LC10 4 " "Info: 9: + IC(1.000 ns) + CELL(5.000 ns) = 54.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "49.500 ns ( 90.83 % ) " "Info: Total cell delay = 49.500 ns ( 90.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns ( 9.17 % ) " "Info: Total interconnect delay = 5.000 ns ( 9.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "54.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "54.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SR 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'SR'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SR } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 37 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns LR_T\[0\] 2 REG LC10 4 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { SR LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { SR LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { SR {} SR~out {} LR_T[0] {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "54.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "54.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { SR LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { SR {} SR~out {} LR_T[0] {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Critical Warning" "WTAN_REQUIREMENTS_NOT_MET_SLOW" "" "Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details." { } { } 1 0 "Timing requirements for slow timing model timing analysis were not met. See Report window for details." 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 21 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:23:32 2022 " "Info: Processing ended: Sun Aug 28 03:23:32 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/sp2_max.(0).cnf.cdb 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b/src/altera/quartus/max/db/sp2_max.(9).cnf.hdb differ diff --git a/src/altera/quartus/max/db/sp2_max.asm.qmsg b/src/altera/quartus/max/db/sp2_max.asm.qmsg new file mode 100644 index 0000000..420657a --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.asm.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:30:42 2022 " "Info: Processing started: Sun Aug 28 03:30:42 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "199 " "Info: Peak virtual memory: 199 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:30:42 2022 " "Info: Processing ended: Sun Aug 28 03:30:42 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/sp2_max.cbx.xml b/src/altera/quartus/max/db/sp2_max.cbx.xml new file mode 100644 index 0000000..dc247dc --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.cbx.xml @@ -0,0 +1,6 @@ + + + + + + diff --git a/src/altera/quartus/max/db/sp2_max.cmp.cdb b/src/altera/quartus/max/db/sp2_max.cmp.cdb new file mode 100644 index 0000000..6fc7fa8 Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.cmp.cdb differ diff --git a/src/altera/quartus/max/db/sp2_max.cmp.hdb b/src/altera/quartus/max/db/sp2_max.cmp.hdb new file mode 100644 index 0000000..28f4b81 Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.cmp.hdb differ diff --git a/src/altera/quartus/max/db/sp2_max.cmp.logdb b/src/altera/quartus/max/db/sp2_max.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/src/altera/quartus/max/db/sp2_max.cmp.rdb b/src/altera/quartus/max/db/sp2_max.cmp.rdb new file mode 100644 index 0000000..027f2a0 Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.cmp.rdb differ diff --git a/src/altera/quartus/max/db/sp2_max.cmp.tdb b/src/altera/quartus/max/db/sp2_max.cmp.tdb new file mode 100644 index 0000000..e8eb0ac Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.cmp.tdb differ diff --git a/src/altera/quartus/max/db/sp2_max.cmp0.ddb b/src/altera/quartus/max/db/sp2_max.cmp0.ddb new file mode 100644 index 0000000..51a46a5 Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.cmp0.ddb differ diff --git a/src/altera/quartus/max/db/sp2_max.db_info b/src/altera/quartus/max/db/sp2_max.db_info new file mode 100644 index 0000000..b1c9e83 --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +Version_Index = 167832322 +Creation_Time = Sun Aug 28 03:22:36 2022 diff --git a/src/altera/quartus/max/db/sp2_max.eco.cdb b/src/altera/quartus/max/db/sp2_max.eco.cdb new file mode 100644 index 0000000..4a66dbf Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.eco.cdb differ diff --git a/src/altera/quartus/max/db/sp2_max.eda.qmsg b/src/altera/quartus/max/db/sp2_max.eda.qmsg new file mode 100644 index 0000000..c64727f --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.eda.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:26:23 2022 " "Info: Processing started: Sun Aug 28 03:26:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Warning" "WQNETO_NO_OUTPUT_FILES" "" "Warning: Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." { } { } 0 0 "Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Peak virtual memory: 163 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:26:23 2022 " "Info: Processing ended: Sun Aug 28 03:26:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/sp2_max.fit.qmsg b/src/altera/quartus/max/db/sp2_max.fit.qmsg new file mode 100644 index 0000000..b118750 --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.fit.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:30:40 2022 " "Info: Processing started: Sun Aug 28 03:30:40 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "sp2_max EPM7128STC100-10 " "Info: Selected device EPM7128STC100-10 for design \"sp2_max\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "10K_D\[0\] " "Warning: Node \"10K_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "10K_D\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLK\[14\] " "Warning: Node \"CLK\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[0\] " "Warning: Node \"D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FDD_C0 " "Warning: Node \"FDD_C0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FDD_C0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FDD_C1 " "Warning: Node \"FDD_C1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FDD_C1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FDD_C2 " "Warning: Node \"FDD_C2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FDD_C2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HDD_C0 " "Warning: Node \"HDD_C0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_C0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HDD_C1 " "Warning: Node \"HDD_C1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_C1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HDD_C2 " "Warning: Node \"HDD_C2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_C2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HDD_C3 " "Warning: Node \"HDD_C3\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_C3" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SINC_\[1\] " "Warning: Node \"SINC_\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SINC_\[2\] " "Warning: Node \"SINC_\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TR\[43\] " "Warning: Node \"TR\[43\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TR\[43\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UNUSED\[33\] " "Warning: Node \"UNUSED\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "UNUSED\[33\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UNUSED\[53\] " "Warning: Node \"UNUSED\[53\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "UNUSED\[53\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UNUSED\[65\] " "Warning: Node \"UNUSED\[65\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "UNUSED\[65\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UNUSED\[78\] " "Warning: Node \"UNUSED\[78\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "UNUSED\[78\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XA0 " "Warning: Node \"XA0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XA0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XA1 " "Warning: Node \"XA1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XA1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XA2 " "Warning: Node \"XA2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XA2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XHD1_CS1 " "Warning: Node \"XHD1_CS1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XHD1_CS1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XHD1_CS2 " "Warning: Node \"XHD1_CS2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XHD1_CS2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XHD2_CS1 " "Warning: Node \"XHD2_CS1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XHD2_CS1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "XHD2_CS2 " "Warning: Node \"XHD2_CS2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XHD2_CS2" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1} } { } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 25 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:30:41 2022 " "Info: Processing ended: Sun Aug 28 03:30:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/sp2_max.hier_info b/src/altera/quartus/max/db/sp2_max.hier_info new file mode 100644 index 0000000..c4c0b94 --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.hier_info @@ -0,0 +1,76 @@ +|sp2_max +TG42_IN => EXP_X.DATAIN +TG42_IN => EXP_Y.DATAIN +TG42_IN => HDD_CLK.CLK +TG42_IN => $00050.CLK +TG42_IN => $00051.CLK +TG42_IN => $00052.CLK +TG42_IN => $00053.CLK +TG42_OUT <= $00003.DB_MAX_OUTPUT_PORT_TYPE +TG42_BUF <= $00004.DB_MAX_OUTPUT_PORT_TYPE +CLKZZ <= $00008 +CLK14 <= $00009.DB_MAX_OUTPUT_PORT_TYPE +AUD <= CT[3].DB_MAX_OUTPUT_PORT_TYPE +BEEP <= +CMOS_DRD <= $00046.DB_MAX_OUTPUT_PORT_TYPE +CMOS_DWR <= $00044.DB_MAX_OUTPUT_PORT_TYPE +WR_PDOS <= $00041.DB_MAX_OUTPUT_PORT_TYPE +CLK_WG <= STWG[2].DB_MAX_OUTPUT_PORT_TYPE +FDAT <= $00021.DB_MAX_OUTPUT_PORT_TYPE +QDAT <= WGR[4].DB_MAX_OUTPUT_PORT_TYPE +/WG_WR <= $00042.DB_MAX_OUTPUT_PORT_TYPE +/WG_RD <= $00043.DB_MAX_OUTPUT_PORT_TYPE +DENS_X <= +WDAT <= REG_P[2].DB_MAX_OUTPUT_PORT_TYPE +XA[0] => ~NO_FANOUT~ +XA[1] => ~NO_FANOUT~ +XA[2] => ~NO_FANOUT~ +XACS => CNF_OFF.ACLR +SINC_1 <= $00005 +SINC_2 <= $00006 +FDD_C[2] => $00041.PRESET +FDD_C[2] => $00042.PRESET +FDD_C[2] => $00043.PRESET +FDD_C[2] => $00044.PRESET +FDD_C[2] => $00045.PRESET +FDD_C[2] => $00046.PRESET +HD_DIR <= $00049.DB_MAX_OUTPUT_PORT_TYPE +/CONF_X <= $00024 +10K_CLK <= HDD_CLK.DB_MAX_OUTPUT_PORT_TYPE +10K_D0 <= FDD_1440.DB_MAX_OUTPUT_PORT_TYPE +D0 => FDD_1440.DATAIN +VGA_IN => ~NO_FANOUT~ +SINC_V <= SINC_VT.DB_MAX_OUTPUT_PORT_TYPE +SINC_H <= SINC_HT.DB_MAX_OUTPUT_PORT_TYPE +SINC_IN => ~NO_FANOUT~ +XHD_RES <= $00047.DB_MAX_OUTPUT_PORT_TYPE +XHD_WR <= $00048.DB_MAX_OUTPUT_PORT_TYPE +XHD_RD <= $00049.DB_MAX_OUTPUT_PORT_TYPE +XHD1_CS[1] <= $00050.DB_MAX_OUTPUT_PORT_TYPE +XHD1_CS[2] <= $00051.DB_MAX_OUTPUT_PORT_TYPE +XHD2_CS[1] <= $00052.DB_MAX_OUTPUT_PORT_TYPE +XHD2_CS[2] <= $00053.DB_MAX_OUTPUT_PORT_TYPE +XHR_RDY => ~NO_FANOUT~ +EPM_RES => $00047.ACLR +PW_GOOD => $00047.DATAIN +UNUSED65 => ~NO_FANOUT~ +UNUSED33 => ~NO_FANOUT~ +UNUSED1 => ~NO_FANOUT~ +UNUSED2 => ~NO_FANOUT~ +UNUSED5 => ~NO_FANOUT~ +UNUSED7 => ~NO_FANOUT~ +UNUSED22 => ~NO_FANOUT~ +UNUSED24 => ~NO_FANOUT~ +UNUSED27 => ~NO_FANOUT~ +UNUSED28 => ~NO_FANOUT~ +UNUSED49 => ~NO_FANOUT~ +UNUSED50 => ~NO_FANOUT~ +UNUSED53 => ~NO_FANOUT~ +UNUSED55 => ~NO_FANOUT~ +UNUSED63 => ~NO_FANOUT~ +UNUSED70 => ~NO_FANOUT~ +UNUSED72 => ~NO_FANOUT~ +UNUSED77 => ~NO_FANOUT~ +UNUSED78 => ~NO_FANOUT~ + + diff --git a/src/altera/quartus/max/db/sp2_max.hif b/src/altera/quartus/max/db/sp2_max.hif new file mode 100644 index 0000000..0c955da --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.hif @@ -0,0 +1,1184 @@ +Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +32 +1921 +OFF +OFF +OFF +ON +ON +OFF +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +sp2_max +# storage +db|sp2_max.(0).cnf +db|sp2_max.(0).cnf +# case_insensitive +# source_file +sp2_max.tdf +eea9fe738f5a8cf67a20667cd5c0c72e +7 +# user_parameter { +G_MODE +1 +PARAMETER_UNKNOWN +DEF +NUM +NO +PARAMETER_UNKNOWN +DEF +NUMBER1 +00100000X +PARAMETER_UNSIGNED_BIN +DEF +NUMBER2 +00110111X +PARAMETER_UNSIGNED_BIN +DEF +NUMBER3 +01001101X +PARAMETER_UNSIGNED_BIN +DEF +NUMBER4 +01010010X +PARAMETER_UNSIGNED_BIN +DEF +NUMBER5 +00100000X +PARAMETER_UNSIGNED_BIN +DEF +NUMBER6 +00100000X +PARAMETER_UNSIGNED_BIN +DEF +NUMBER7 +00100000X +PARAMETER_UNSIGNED_BIN +DEF +} +# used_port { +0 +-1 +0 +} +# hierarchies { +| +} +# macro_sequence + +# end +# entity +lpm_counter +# storage +db|sp2_max.(1).cnf +db|sp2_max.(1).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_counter.tdf +9583d6cd53fa119b14456768b85150d1 +7 +# user_parameter { +AUTO_CARRY_CHAINS +ON +AUTO_CARRY +USR +IGNORE_CARRY_BUFFERS +OFF +IGNORE_CARRY +USR +AUTO_CASCADE_CHAINS +ON +AUTO_CASCADE +USR +IGNORE_CASCADE_BUFFERS +OFF +IGNORE_CASCADE +USR +LPM_WIDTH +4 +PARAMETER_UNKNOWN +USR +LPM_DIRECTION +UP +PARAMETER_UNKNOWN +USR +LPM_MODULUS +0 +PARAMETER_UNKNOWN +DEF +LPM_AVALUE +UNUSED +PARAMETER_UNKNOWN +DEF +LPM_SVALUE +UNUSED +PARAMETER_UNKNOWN +DEF +LPM_PORT_UPDOWN +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +DEVICE_FAMILY +MAX7000S +PARAMETER_UNKNOWN +USR +CARRY_CHAIN +MANUAL +PARAMETER_UNKNOWN +USR +CARRY_CHAIN_LENGTH +48 +CARRY_CHAIN_LENGTH +USR +NOT_GATE_PUSH_BACK +ON +NOT_GATE_PUSH_BACK +USR +CARRY_CNT_EN +SMART +PARAMETER_UNKNOWN +DEF +LABWIDE_SCLR +ON +PARAMETER_UNKNOWN +DEF +USE_NEW_VERSION +TRUE +PARAMETER_UNKNOWN +DEF +CBXI_PARAMETER +NOTHING +PARAMETER_UNKNOWN +DEF +} +# used_port { +q3 +-1 +3 +q0 +-1 +3 +clock +-1 +3 +} +# include_file { +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_counter.inc +7f888b135ddf66f0653c44cb18ac5 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_add_sub.inc +7d9a33dd39f13aa690c3d0edd88351 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_synch_counter.inc +09966d10c3e95c888bf8e443df34d8 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_synch_counter_f.inc +93a5aae1d8bd19c9e8e8eef93ab2177d +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_counter_f10ke.inc +536f8da8218b4a93689416f9baea1880 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|cmpconst.inc +e61874547688138e6fc0b49ff8760 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_constant.inc +dcde44eee59335c1e2fe75d574f9646 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|dffeea.inc +55d29d20f7e852c37746bec4e2495ec +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_counter_stratix.inc +2251b94d26afaa53635df1aff6b6e7be +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_compare.inc +aec4ea1b78f4cda1c3effe18f1abbf63 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|aglobal90.inc +99832fdf63412df51d7531202d74e75 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_decode.inc +bd0e2f5e01c1bd360461dceb53d48 +} +# macro_sequence + +# end +# entity +lpm_counter +# storage +db|sp2_max.(2).cnf +db|sp2_max.(2).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_counter.tdf +9583d6cd53fa119b14456768b85150d1 +7 +# user_parameter { +AUTO_CARRY_CHAINS +ON +AUTO_CARRY +USR +IGNORE_CARRY_BUFFERS +OFF +IGNORE_CARRY +USR +AUTO_CASCADE_CHAINS +ON +AUTO_CASCADE +USR +IGNORE_CASCADE_BUFFERS +OFF +IGNORE_CASCADE +USR +LPM_WIDTH +9 +PARAMETER_UNKNOWN +USR +LPM_DIRECTION +UP +PARAMETER_UNKNOWN +USR +LPM_MODULUS +0 +PARAMETER_UNKNOWN +DEF +LPM_AVALUE +UNUSED +PARAMETER_UNKNOWN +DEF +LPM_SVALUE +UNUSED +PARAMETER_UNKNOWN +DEF +LPM_PORT_UPDOWN +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +DEVICE_FAMILY +MAX7000S +PARAMETER_UNKNOWN +USR +CARRY_CHAIN +MANUAL +PARAMETER_UNKNOWN +USR +CARRY_CHAIN_LENGTH +48 +CARRY_CHAIN_LENGTH +USR +NOT_GATE_PUSH_BACK +ON +NOT_GATE_PUSH_BACK +USR +CARRY_CNT_EN +SMART +PARAMETER_UNKNOWN +DEF +LABWIDE_SCLR +ON +PARAMETER_UNKNOWN +DEF +USE_NEW_VERSION +TRUE +PARAMETER_UNKNOWN +DEF +CBXI_PARAMETER +NOTHING +PARAMETER_UNKNOWN +DEF +} +# used_port { +sclr +-1 +3 +q8 +-1 +3 +q7 +-1 +3 +q6 +-1 +3 +q5 +-1 +3 +q4 +-1 +3 +q3 +-1 +3 +q2 +-1 +3 +q1 +-1 +3 +q0 +-1 +3 +clock +-1 +3 +} +# include_file { +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_counter.inc +7f888b135ddf66f0653c44cb18ac5 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_add_sub.inc +7d9a33dd39f13aa690c3d0edd88351 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_synch_counter.inc +09966d10c3e95c888bf8e443df34d8 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_synch_counter_f.inc +93a5aae1d8bd19c9e8e8eef93ab2177d +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_counter_f10ke.inc +536f8da8218b4a93689416f9baea1880 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|cmpconst.inc +e61874547688138e6fc0b49ff8760 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_constant.inc +dcde44eee59335c1e2fe75d574f9646 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|dffeea.inc +55d29d20f7e852c37746bec4e2495ec +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_counter_stratix.inc +2251b94d26afaa53635df1aff6b6e7be +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_compare.inc +aec4ea1b78f4cda1c3effe18f1abbf63 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|aglobal90.inc +99832fdf63412df51d7531202d74e75 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_decode.inc +bd0e2f5e01c1bd360461dceb53d48 +} +# macro_sequence + +# end +# entity +lpm_counter +# storage +db|sp2_max.(3).cnf +db|sp2_max.(3).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_counter.tdf +9583d6cd53fa119b14456768b85150d1 +7 +# user_parameter { +AUTO_CARRY_CHAINS +ON +AUTO_CARRY +USR +IGNORE_CARRY_BUFFERS +OFF +IGNORE_CARRY +USR +AUTO_CASCADE_CHAINS +ON +AUTO_CASCADE +USR +IGNORE_CASCADE_BUFFERS +OFF +IGNORE_CASCADE +USR +LPM_WIDTH +6 +PARAMETER_UNKNOWN +USR +LPM_DIRECTION +UP +PARAMETER_UNKNOWN +USR +LPM_MODULUS +0 +PARAMETER_UNKNOWN +DEF +LPM_AVALUE +UNUSED +PARAMETER_UNKNOWN +DEF +LPM_SVALUE +UNUSED +PARAMETER_UNKNOWN +DEF +LPM_PORT_UPDOWN +PORT_CONNECTIVITY +PARAMETER_UNKNOWN +DEF +DEVICE_FAMILY +MAX7000S +PARAMETER_UNKNOWN +USR +CARRY_CHAIN +MANUAL +PARAMETER_UNKNOWN +USR +CARRY_CHAIN_LENGTH +48 +CARRY_CHAIN_LENGTH +USR +NOT_GATE_PUSH_BACK +ON +NOT_GATE_PUSH_BACK +USR +CARRY_CNT_EN +SMART +PARAMETER_UNKNOWN +DEF +LABWIDE_SCLR +ON +PARAMETER_UNKNOWN +DEF +USE_NEW_VERSION +TRUE +PARAMETER_UNKNOWN +DEF +CBXI_PARAMETER +NOTHING +PARAMETER_UNKNOWN +DEF +} +# used_port { +sclr +-1 +3 +q5 +-1 +3 +q4 +-1 +3 +q3 +-1 +3 +q2 +-1 +3 +q1 +-1 +3 +q0 +-1 +3 +clock +-1 +3 +} +# include_file { +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_counter.inc +7f888b135ddf66f0653c44cb18ac5 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_add_sub.inc +7d9a33dd39f13aa690c3d0edd88351 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_synch_counter.inc +09966d10c3e95c888bf8e443df34d8 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_synch_counter_f.inc +93a5aae1d8bd19c9e8e8eef93ab2177d +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_counter_f10ke.inc +536f8da8218b4a93689416f9baea1880 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|cmpconst.inc +e61874547688138e6fc0b49ff8760 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_constant.inc +dcde44eee59335c1e2fe75d574f9646 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|dffeea.inc +55d29d20f7e852c37746bec4e2495ec +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_counter_stratix.inc +2251b94d26afaa53635df1aff6b6e7be +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_compare.inc +aec4ea1b78f4cda1c3effe18f1abbf63 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|aglobal90.inc +99832fdf63412df51d7531202d74e75 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_decode.inc +bd0e2f5e01c1bd360461dceb53d48 +} +# macro_sequence + +# end +# entity +lpm_add_sub +# storage +db|sp2_max.(4).cnf +db|sp2_max.(4).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|lpm_add_sub.tdf +2e51ebc96381892436afe139aaa6b25 +7 +# user_parameter { +LPM_WIDTH +5 +PARAMETER_UNKNOWN +USR +LPM_REPRESENTATION +UNSIGNED +PARAMETER_UNKNOWN +USR +LPM_DIRECTION +ADD +PARAMETER_UNKNOWN +USR +ONE_INPUT_IS_CONSTANT +YES +PARAMETER_UNKNOWN +USR +LPM_PIPELINE +0 +PARAMETER_UNKNOWN +DEF +MAXIMIZE_SPEED +5 +PARAMETER_UNKNOWN +DEF +REGISTERED_AT_END +0 +PARAMETER_UNKNOWN +DEF +OPTIMIZE_FOR_SPEED +9 +PARAMETER_UNKNOWN +USR +USE_CS_BUFFERS +1 +PARAMETER_UNKNOWN +DEF +CARRY_CHAIN +MANUAL +PARAMETER_UNKNOWN +USR +CARRY_CHAIN_LENGTH +48 +CARRY_CHAIN_LENGTH +USR +DEVICE_FAMILY +MAX7000S +PARAMETER_UNKNOWN +USR +USE_WYS +OFF +PARAMETER_UNKNOWN +DEF +STYLE +FAST +PARAMETER_UNKNOWN +USR +CBXI_PARAMETER +add_sub_uch +PARAMETER_UNKNOWN +USR +AUTO_CARRY_CHAINS +ON +AUTO_CARRY +USR +IGNORE_CARRY_BUFFERS +OFF +IGNORE_CARRY +USR +AUTO_CASCADE_CHAINS +ON +AUTO_CASCADE +USR +IGNORE_CASCADE_BUFFERS +OFF +IGNORE_CASCADE +USR +} +# used_port { +result4 +-1 +3 +result3 +-1 +3 +result2 +-1 +3 +result1 +-1 +3 +result0 +-1 +3 +dataa4 +-1 +3 +dataa3 +-1 +3 +dataa2 +-1 +3 +dataa1 +-1 +3 +dataa0 +-1 +3 +datab4 +-1 +1 +datab3 +-1 +1 +datab2 +-1 +1 +datab1 +-1 +1 +datab0 +-1 +2 +} +# include_file { +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_stratix_add_sub.inc +c08f604aefba5b4f1f554e565113c6 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|look_add.inc +ab9f577d30c5ef3166fab6c1c32c4a +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|alt_mercury_add_sub.inc +ae39f15ed67cc9a095d29f68f6ad0f8 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|bypassff.inc +8e8df160d449a63ec15dc86ecf2b373f +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|aglobal90.inc +99832fdf63412df51d7531202d74e75 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|altshift.inc +70fa13aee7d6d160ef20b2de32813a +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|addcore.inc +ff795e21e4847824c03218724f1a1252 +} +# macro_sequence + +# end +# entity +addcore +# storage +db|sp2_max.(5).cnf +db|sp2_max.(5).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|addcore.tdf +1b2b6ae11c95f15ac3d40e6c6c4170 +7 +# user_parameter { +AUTO_CARRY_CHAINS +ON +AUTO_CARRY +USR +IGNORE_CARRY_BUFFERS +OFF +IGNORE_CARRY +USR +AUTO_CASCADE_CHAINS +ON +AUTO_CASCADE +USR +IGNORE_CASCADE_BUFFERS +OFF +IGNORE_CASCADE +USR +width +5 +PARAMETER_UNKNOWN +USR +REPRESENTATION +UNSIGNED +PARAMETER_UNKNOWN +USR +DIRECTION +ADD +PARAMETER_UNKNOWN +USR +USE_CS_BUFFERS +1 +PARAMETER_UNKNOWN +USR +CARRY_CHAIN +MANUAL +PARAMETER_UNKNOWN +USR +CARRY_CHAIN_LENGTH +48 +CARRY_CHAIN_LENGTH +USR +DEVICE_FAMILY +MAX7000S +PARAMETER_UNKNOWN +USR +} +# used_port { +result4 +-1 +3 +result3 +-1 +3 +result2 +-1 +3 +result1 +-1 +3 +result0 +-1 +3 +datab4 +-1 +3 +datab3 +-1 +3 +datab2 +-1 +3 +datab1 +-1 +3 +datab0 +-1 +3 +dataa4 +-1 +3 +dataa3 +-1 +3 +dataa2 +-1 +3 +dataa1 +-1 +3 +dataa0 +-1 +3 +} +# include_file { +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|a_csnbuffer.inc +49de46f6a395e2e6edecabe6eac9d873 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|aglobal90.inc +99832fdf63412df51d7531202d74e75 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|addcore.inc +ff795e21e4847824c03218724f1a1252 +} +# macro_sequence + +# end +# entity +a_csnbuffer +# storage +db|sp2_max.(6).cnf +db|sp2_max.(6).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|a_csnbuffer.tdf +0a953daa377c9212d3c374d37725bd +7 +# user_parameter { +WIDTH +5 +PARAMETER_UNKNOWN +USR +NEED_CARRY +0 +PARAMETER_UNKNOWN +DEF +USE_CS_BUFFERS +1 +PARAMETER_UNKNOWN +USR +} +# used_port { +sout0 +-1 +3 +sin0 +-1 +3 +} +# macro_sequence + +# end +# entity +a_csnbuffer +# storage +db|sp2_max.(7).cnf +db|sp2_max.(7).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|a_csnbuffer.tdf +0a953daa377c9212d3c374d37725bd +7 +# user_parameter { +WIDTH +5 +PARAMETER_UNKNOWN +USR +NEED_CARRY +0 +PARAMETER_UNKNOWN +DEF +USE_CS_BUFFERS +1 +PARAMETER_UNKNOWN +USR +} +# used_port { +sout4 +-1 +3 +sout3 +-1 +3 +sout2 +-1 +3 +sout1 +-1 +3 +sout0 +-1 +3 +sin4 +-1 +3 +sin3 +-1 +3 +sin2 +-1 +3 +sin1 +-1 +3 +sin0 +-1 +3 +} +# macro_sequence + +# end +# entity +addcore +# storage +db|sp2_max.(8).cnf +db|sp2_max.(8).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|addcore.tdf +1b2b6ae11c95f15ac3d40e6c6c4170 +7 +# user_parameter { +AUTO_CARRY_CHAINS +ON +AUTO_CARRY +USR +IGNORE_CARRY_BUFFERS +OFF +IGNORE_CARRY +USR +AUTO_CASCADE_CHAINS +ON +AUTO_CASCADE +USR +IGNORE_CASCADE_BUFFERS +OFF +IGNORE_CASCADE +USR +width +8 +PARAMETER_UNKNOWN +USR +REPRESENTATION +UNSIGNED +PARAMETER_UNKNOWN +USR +DIRECTION +ADD +PARAMETER_UNKNOWN +USR +USE_CS_BUFFERS +1 +PARAMETER_UNKNOWN +USR +CARRY_CHAIN +MANUAL +PARAMETER_UNKNOWN +USR +CARRY_CHAIN_LENGTH +48 +CARRY_CHAIN_LENGTH +USR +DEVICE_FAMILY +MAX7000S +PARAMETER_UNKNOWN +USR +} +# used_port { +unreg_result4 +-1 +3 +unreg_result3 +-1 +3 +unreg_result2 +-1 +3 +unreg_result1 +-1 +3 +unreg_result0 +-1 +3 +result5 +-1 +3 +result4 +-1 +3 +result3 +-1 +3 +result2 +-1 +3 +result1 +-1 +3 +result0 +-1 +3 +datab4 +-1 +3 +datab3 +-1 +3 +datab2 +-1 +3 +datab1 +-1 +3 +datab0 +-1 +3 +dataa4 +-1 +3 +dataa3 +-1 +3 +dataa2 +-1 +3 +dataa1 +-1 +3 +dataa0 +-1 +3 +} +# include_file { +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|a_csnbuffer.inc +49de46f6a395e2e6edecabe6eac9d873 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|aglobal90.inc +99832fdf63412df51d7531202d74e75 +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|addcore.inc +ff795e21e4847824c03218724f1a1252 +} +# macro_sequence + +# end +# entity +a_csnbuffer +# storage +db|sp2_max.(9).cnf +db|sp2_max.(9).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|a_csnbuffer.tdf +0a953daa377c9212d3c374d37725bd +7 +# user_parameter { +WIDTH +8 +PARAMETER_UNKNOWN +USR +NEED_CARRY +0 +PARAMETER_UNKNOWN +DEF +USE_CS_BUFFERS +1 +PARAMETER_UNKNOWN +USR +} +# used_port { +sout0 +-1 +3 +sin0 +-1 +3 +} +# macro_sequence + +# end +# entity +a_csnbuffer +# storage +db|sp2_max.(10).cnf +db|sp2_max.(10).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|a_csnbuffer.tdf +0a953daa377c9212d3c374d37725bd +7 +# user_parameter { +WIDTH +8 +PARAMETER_UNKNOWN +USR +NEED_CARRY +0 +PARAMETER_UNKNOWN +DEF +USE_CS_BUFFERS +1 +PARAMETER_UNKNOWN +USR +} +# used_port { +sout7 +-1 +3 +sout6 +-1 +3 +sout5 +-1 +3 +sout4 +-1 +3 +sout3 +-1 +3 +sout2 +-1 +3 +sout1 +-1 +3 +sout0 +-1 +3 +sin7 +-1 +3 +sin6 +-1 +3 +sin5 +-1 +3 +sin4 +-1 +3 +sin3 +-1 +3 +sin2 +-1 +3 +sin1 +-1 +3 +sin0 +-1 +3 +} +# macro_sequence + +# end +# entity +altshift +# storage +db|sp2_max.(11).cnf +db|sp2_max.(11).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|altshift.tdf +b979c99547bac7dc31574fe678a95a9 +7 +# user_parameter { +WIDTH +5 +PARAMETER_UNKNOWN +USR +DEPTH +0 +PARAMETER_UNKNOWN +USR +} +# used_port { +result4 +-1 +3 +result3 +-1 +3 +result2 +-1 +3 +result1 +-1 +3 +result0 +-1 +3 +data4 +-1 +3 +data3 +-1 +3 +data2 +-1 +3 +data1 +-1 +3 +data0 +-1 +3 +} +# macro_sequence + +# end +# entity +altshift +# storage +db|sp2_max.(12).cnf +db|sp2_max.(12).cnf +# case_insensitive +# source_file +..|..|..|..|..|altera|90sp2|quartus|libraries|megafunctions|altshift.tdf +b979c99547bac7dc31574fe678a95a9 +7 +# user_parameter { +WIDTH +1 +PARAMETER_UNKNOWN +USR +DEPTH +0 +PARAMETER_UNKNOWN +USR +} +# used_port { +result0 +-1 +3 +data0 +-1 +3 +} +# macro_sequence + +# end +# complete + \ No newline at end of file diff --git a/src/altera/quartus/max/db/sp2_max.lpc.html b/src/altera/quartus/max/db/sp2_max.lpc.html new file mode 100644 index 0000000..1dae3d2 --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/src/altera/quartus/max/db/sp2_max.lpc.rdb b/src/altera/quartus/max/db/sp2_max.lpc.rdb new file mode 100644 index 0000000..8bd163a Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.lpc.rdb differ diff --git a/src/altera/quartus/max/db/sp2_max.lpc.txt b/src/altera/quartus/max/db/sp2_max.lpc.txt new file mode 100644 index 0000000..dbfe520 --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/src/altera/quartus/max/db/sp2_max.map.cdb b/src/altera/quartus/max/db/sp2_max.map.cdb new file mode 100644 index 0000000..3384886 Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.map.cdb differ diff --git a/src/altera/quartus/max/db/sp2_max.map.hdb b/src/altera/quartus/max/db/sp2_max.map.hdb new file mode 100644 index 0000000..e526ba3 Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.map.hdb differ diff --git a/src/altera/quartus/max/db/sp2_max.map.logdb b/src/altera/quartus/max/db/sp2_max.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/src/altera/quartus/max/db/sp2_max.map.qmsg b/src/altera/quartus/max/db/sp2_max.map.qmsg new file mode 100644 index 0000000..d196367 --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.map.qmsg @@ -0,0 +1,56 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:30:38 2022 " "Info: Processing started: Sun Aug 28 03:30:38 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "sp2_max.tdf 1 1 " "Warning: Using design file sp2_max.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SP2_MAX " "Info: Found entity 1: SP2_MAX" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 18 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "sp2_max " "Info: Elaborating entity \"sp2_max\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "CTV8C " "Warning: Variable or input pin \"CTV8C\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 167 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "XA " "Warning: Variable or input pin \"XA\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 52 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "VGA_IN " "Warning: Variable or input pin \"VGA_IN\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 70 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "SINC_IN " "Warning: Variable or input pin \"SINC_IN\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 75 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "XHR_RDY " "Warning: Variable or input pin \"XHR_RDY\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 83 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED65 " "Warning: Variable or input pin \"UNUSED65\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 88 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED33 " "Warning: Variable or input pin \"UNUSED33\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 89 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED1 " "Warning: Variable or input pin \"UNUSED1\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 90 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED2 " "Warning: Variable or input pin \"UNUSED2\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 91 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED5 " "Warning: Variable or input pin \"UNUSED5\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 92 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED7 " "Warning: Variable or input pin \"UNUSED7\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 93 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED22 " "Warning: Variable or input pin \"UNUSED22\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 94 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED24 " "Warning: Variable or input pin \"UNUSED24\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 95 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED27 " "Warning: Variable or input pin \"UNUSED27\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 96 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED28 " "Warning: Variable or input pin \"UNUSED28\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 97 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED49 " "Warning: Variable or input pin \"UNUSED49\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 98 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED50 " "Warning: Variable or input pin \"UNUSED50\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 99 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED53 " "Warning: Variable or input pin \"UNUSED53\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 100 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED55 " "Warning: Variable or input pin \"UNUSED55\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 101 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED63 " "Warning: Variable or input pin \"UNUSED63\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 102 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED70 " "Warning: Variable or input pin \"UNUSED70\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 103 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED72 " "Warning: Variable or input pin \"UNUSED72\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 104 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED77 " "Warning: Variable or input pin \"UNUSED77\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 105 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "UNUSED78 " "Warning: Variable or input pin \"UNUSED78\" is defined but never used" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 106 2 0 } } } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0 -1} +{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "CT\[0\]~0 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"CT\[0\]~0\"" { } { { "sp2_max.tdf" "CT\[0\]~0" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 119 4 0 } } } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IOPT_LPM_COUNTER_INFERRED" "CTV\[0\]~9 9 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: \"CTV\[0\]~9\"" { } { { "sp2_max.tdf" "CTV\[0\]~9" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 121 5 0 } } } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "IOPT_LPM_COUNTER_INFERRED" "CTH\[0\]~7 6 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: \"CTH\[0\]~7\"" { } { { "sp2_max.tdf" "CTH\[0\]~7" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 120 5 0 } } } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 -1} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "op_6 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"op_6\"" { } { } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:CT_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:CT_rtl_0\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:CT_rtl_0 " "Info: Instantiated megafunction \"lpm_counter:CT_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:CTV_rtl_1 " "Info: Elaborated megafunction instantiation \"lpm_counter:CTV_rtl_1\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:CTV_rtl_1 " "Info: Instantiated megafunction \"lpm_counter:CTV_rtl_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 9 " "Info: Parameter \"LPM_WIDTH\" = \"9\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:CTH_rtl_2 " "Info: Elaborated megafunction instantiation \"lpm_counter:CTH_rtl_2\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:CTH_rtl_2 " "Info: Instantiated megafunction \"lpm_counter:CTH_rtl_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 6 " "Info: Parameter \"LPM_WIDTH\" = \"6\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:op_6 " "Info: Instantiated megafunction \"lpm_add_sub:op_6\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 202 5 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 203 10 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "addcore.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf" 189 5 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|altshift:result_ext_latency_ffs lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:op_6\|altshift:carry_ext_latency_ffs lpm_add_sub:op_6 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:op_6\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:op_6\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "6 " "Info: Ignored 6 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "6 " "Info: Ignored 6 SOFT buffer(s)" { } { } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0 "" 0 -1} } { } 0 0 "Ignored %1!d! buffer(s)" 0 0 "" 0 -1} +{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 451 13 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 450 13 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 449 13 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 445 13 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 446 12 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 447 12 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 479 27 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 478 27 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 489 20 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 495 20 0 } } } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 -1} +{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "\$00005 " "Warning: Node \"\$00005\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 206 12 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "\$00006 " "Warning: Node \"\$00006\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 207 12 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1} +{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "BEEP GND " "Warning (13410): Pin \"BEEP\" is stuck at GND" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 333 2 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "DENS_X VCC " "Warning (13410): Pin \"DENS_X\" is stuck at VCC" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 345 2 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "HD_CS GND " "Warning (13410): Pin \"HD_CS\" is stuck at GND" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 458 9 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1} +{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "TG42_IN " "Info: Promoted clock signal driven by pin \"TG42_IN\" to global clock signal" { } { } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "" 0 -1} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "EPM_RES " "Info: Promoted clear signal driven by pin \"EPM_RES\" to global clear signal" { } { } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "" 0 -1} } { } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0 "" 0 -1} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "XCT\[2\] " "Info: Register \"XCT\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "25 " "Warning: Design contains 25 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "XA\[0\] " "Warning (15610): No output dependent on input pin \"XA\[0\]\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 52 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "XA\[1\] " "Warning (15610): No output dependent on input pin \"XA\[1\]\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 52 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "XA\[2\] " "Warning (15610): No output dependent on input pin \"XA\[2\]\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 52 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "VGA_IN " "Warning (15610): No output dependent on input pin \"VGA_IN\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 70 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SINC_IN " "Warning (15610): No output dependent on input pin \"SINC_IN\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 75 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "XHR_RDY " "Warning (15610): No output dependent on input pin \"XHR_RDY\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 83 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED65 " "Warning (15610): No output dependent on input pin \"UNUSED65\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 88 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED33 " "Warning (15610): No output dependent on input pin \"UNUSED33\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 89 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED1 " "Warning (15610): No output dependent on input pin \"UNUSED1\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 90 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED2 " "Warning (15610): No output dependent on input pin \"UNUSED2\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 91 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED5 " "Warning (15610): No output dependent on input pin \"UNUSED5\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 92 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED7 " "Warning (15610): No output dependent on input pin \"UNUSED7\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 93 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED22 " "Warning (15610): No output dependent on input pin \"UNUSED22\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 94 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED24 " "Warning (15610): No output dependent on input pin \"UNUSED24\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 95 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED27 " "Warning (15610): No output dependent on input pin \"UNUSED27\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 96 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED28 " "Warning (15610): No output dependent on input pin \"UNUSED28\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 97 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED49 " "Warning (15610): No output dependent on input pin \"UNUSED49\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 98 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED50 " "Warning (15610): No output dependent on input pin \"UNUSED50\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 99 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED53 " "Warning (15610): No output dependent on input pin \"UNUSED53\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 100 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED55 " "Warning (15610): No output dependent on input pin \"UNUSED55\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 101 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED63 " "Warning (15610): No output dependent on input pin \"UNUSED63\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 102 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED70 " "Warning (15610): No output dependent on input pin \"UNUSED70\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 103 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED72 " "Warning (15610): No output dependent on input pin \"UNUSED72\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 104 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED77 " "Warning (15610): No output dependent on input pin \"UNUSED77\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 105 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "UNUSED78 " "Warning (15610): No output dependent on input pin \"UNUSED78\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 106 2 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "163 " "Info: Implemented 163 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "46 " "Info: Implemented 46 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Info: Implemented 30 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "4 " "Info: Implemented 4 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_MCELLS" "74 " "Info: Implemented 74 macrocells" { } { } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_SEXPS" "9 " "Info: Implemented 9 shareable expanders" { } { } 0 0 "Implemented %1!d! shareable expanders" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 58 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 58 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:30:39 2022 " "Info: Processing ended: Sun Aug 28 03:30:39 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/sp2_max.pre_map.cdb b/src/altera/quartus/max/db/sp2_max.pre_map.cdb new file mode 100644 index 0000000..58843c7 Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.pre_map.cdb differ diff --git a/src/altera/quartus/max/db/sp2_max.pre_map.hdb b/src/altera/quartus/max/db/sp2_max.pre_map.hdb new file mode 100644 index 0000000..21994f9 Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.pre_map.hdb differ diff --git a/src/altera/quartus/max/db/sp2_max.rtlv.hdb b/src/altera/quartus/max/db/sp2_max.rtlv.hdb new file mode 100644 index 0000000..221dd6d Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.rtlv.hdb differ diff --git a/src/altera/quartus/max/db/sp2_max.rtlv_sg.cdb b/src/altera/quartus/max/db/sp2_max.rtlv_sg.cdb new file mode 100644 index 0000000..a3905ed Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.rtlv_sg.cdb differ diff --git a/src/altera/quartus/max/db/sp2_max.rtlv_sg_swap.cdb b/src/altera/quartus/max/db/sp2_max.rtlv_sg_swap.cdb new file mode 100644 index 0000000..bccc94e Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.rtlv_sg_swap.cdb differ diff --git a/src/altera/quartus/max/db/sp2_max.sgdiff.cdb b/src/altera/quartus/max/db/sp2_max.sgdiff.cdb new file mode 100644 index 0000000..5ddc0cc Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.sgdiff.cdb differ diff --git a/src/altera/quartus/max/db/sp2_max.sgdiff.hdb b/src/altera/quartus/max/db/sp2_max.sgdiff.hdb new file mode 100644 index 0000000..984bee0 Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.sgdiff.hdb differ diff --git a/src/altera/quartus/max/db/sp2_max.sld_design_entry.sci b/src/altera/quartus/max/db/sp2_max.sld_design_entry.sci new file mode 100644 index 0000000..7f9b4cb Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.sld_design_entry.sci differ diff --git a/src/altera/quartus/max/db/sp2_max.sld_design_entry_dsc.sci b/src/altera/quartus/max/db/sp2_max.sld_design_entry_dsc.sci new file mode 100644 index 0000000..d333b2d Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.sld_design_entry_dsc.sci differ diff --git a/src/altera/quartus/max/db/sp2_max.syn_hier_info b/src/altera/quartus/max/db/sp2_max.syn_hier_info new file mode 100644 index 0000000..e69de29 diff --git a/src/altera/quartus/max/db/sp2_max.tan.qmsg b/src/altera/quartus/max/db/sp2_max.tan.qmsg new file mode 100644 index 0000000..6d93a07 --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.tan.qmsg @@ -0,0 +1,31 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 03:30:43 2022 " "Info: Processing started: Sun Aug 28 03:30:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" { } { } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0 -1} +{ "Warning" "WTAN_SCC_LOOP" "2 " "Warning: Found combinational loop of 2 nodes" { { "Warning" "WTAN_SCC_NODE" "RDAT_X~11 " "Warning: Node \"RDAT_X~11\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "RDAT_X~6 " "Warning: Node \"RDAT_X~6\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1} +{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "TURBING~5 " "Warning: Node \"TURBING~5\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1} +{ "Warning" "WTAN_SCC_LOOP" "3 " "Warning: Found combinational loop of 3 nodes" { { "Warning" "WTAN_SCC_NODE" "THDD~2 " "Warning: Node \"THDD~2\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "NTHDD~13 " "Warning: Node \"NTHDD~13\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "NTHDD~11 " "Warning: Node \"NTHDD~11\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1} +{ "Warning" "WTAN_SCC_LOOP" "2 " "Warning: Found combinational loop of 2 nodes" { { "Warning" "WTAN_SCC_NODE" "NT320~12 " "Warning: Node \"NT320~12\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 426 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WTAN_SCC_NODE" "NT320~2 " "Warning: Node \"NT320~2\"" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 426 2 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 426 2 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 -1} +{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "TG42_IN " "Info: Assuming node \"TG42_IN\" is an undefined clock" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TG42_IN" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "STE " "Info: Assuming node \"STE\" is an undefined clock" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "STE" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "RSTB " "Info: Assuming node \"RSTB\" is an undefined clock" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "RSTB" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "WSTB " "Info: Assuming node \"WSTB\" is an undefined clock" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "WSTB" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} +{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "CT_WG1~8bal " "Info: Detected gated clock \"CT_WG1~8bal\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 304 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG1~8bal" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "STWG\[2\] " "Info: Detected ripple clock \"STWG\[2\]\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "STWG\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "STWG\[2\]~6bal " "Info: Detected gated clock \"STWG\[2\]~6bal\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "STWG\[2\]~6bal" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "CT_WG~6 " "Info: Detected gated clock \"CT_WG~6\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG~6" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "CT_WG~5 " "Info: Detected gated clock \"CT_WG~5\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG~5" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "CT_WG~4 " "Info: Detected gated clock \"CT_WG~4\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG~4" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "CT_WG " "Info: Detected ripple clock \"CT_WG\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CT_WG" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "TURBING~5 " "Info: Detected gated clock \"TURBING~5\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "TURBING~5" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "FDD_1440 " "Info: Detected ripple clock \"FDD_1440\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "FDD_1440" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "HDD_CLK " "Info: Detected ripple clock \"HDD_CLK\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_CLK" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:CT_rtl_0\|dffs\[3\] " "Info: Detected ripple clock \"lpm_counter:CT_rtl_0\|dffs\[3\]\" as buffer" { } { { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:CT_rtl_0\|dffs\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "SINC_HT " "Info: Detected ripple clock \"SINC_HT\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 123 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_HT" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "SINC_VT " "Info: Detected ripple clock \"SINC_VT\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 124 2 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "SINC_VT" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter:CT_rtl_0\|dffs\[0\] " "Info: Detected ripple clock \"lpm_counter:CT_rtl_0\|dffs\[0\]\" as buffer" { } { { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter:CT_rtl_0\|dffs\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~4 " "Info: Detected gated clock \"XCT\[2\]~4\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~4" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~3 " "Info: Detected gated clock \"XCT\[2\]~3\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~3" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~12 " "Info: Detected gated clock \"XCT\[2\]~12\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~12" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_GATED_CLK" "XCT\[2\]~11 " "Info: Detected gated clock \"XCT\[2\]~11\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[2\]~11" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "XCT\[0\] " "Info: Detected ripple clock \"XCT\[0\]\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "XCT\[1\] " "Info: Detected ripple clock \"XCT\[1\]\" as buffer" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "XCT\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_SLACK_RESULT" "TG42_IN register /RESET register \$00051 -47.0 ns " "Info: Slack time is -47.0 ns for clock \"TG42_IN\" between source register \"/RESET\" and destination register \"\$00051\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "9.62 MHz 104.0 ns " "Info: Fmax is 9.62 MHz (period= 104.0 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-25.000 ns + Largest register register " "Info: + Largest register to register requirement is -25.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination TG42_IN 10.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"TG42_IN\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source TG42_IN 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"TG42_IN\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-26.000 ns + Largest " "Info: + Largest clock skew is -26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"TG42_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns \$00051 2 REG LC121 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC121; Fanout = 1; REG Node = '\$00051'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { TG42_IN $00051 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN source 27.500 ns - Longest register " "Info: - Longest clock path from clock \"TG42_IN\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 6.500 ns XCT\[2\]~4 2 COMB SEXP49 1 " "Info: 2: + IC(0.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP49; Fanout = 1; COMB Node = 'XCT\[2\]~4'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { TG42_IN XCT[2]~4 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 13.500 ns XCT\[1\] 3 REG LC56 18 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 13.500 ns; Loc. = LC56; Fanout = 18; REG Node = 'XCT\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { XCT[2]~4 XCT[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 21.500 ns lpm_counter:CT_rtl_0\|dffs\[3\] 4 REG LC53 10 " "Info: 4: + IC(1.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC53; Fanout = 10; REG Node = 'lpm_counter:CT_rtl_0\|dffs\[3\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { XCT[1] lpm_counter:CT_rtl_0|dffs[3] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns /RESET 5 REG LC85 19 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC85; Fanout = 19; REG Node = '/RESET'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 173 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 173 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.000 ns - Longest register register " "Info: - Longest register to register delay is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns /RESET 1 REG LC85 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC85; Fanout = 19; REG Node = '/RESET'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { /RESET } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 173 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(16.000 ns) 16.000 ns THDD~2 2 COMB LOOP LC114 14 " "Info: 2: + IC(0.000 ns) + CELL(16.000 ns) = 16.000 ns; Loc. = LC114; Fanout = 14; COMB LOOP Node = 'THDD~2'" { { "Info" "ITDB_PART_OF_SCC" "NTHDD~11 LC119 " "Info: Loc. = LC119; Node \"NTHDD~11\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "THDD~2 LC114 " "Info: Loc. = LC114; Node \"THDD~2\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "NTHDD~13 LC118 " "Info: Loc. = LC118; Node \"NTHDD~13\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "16.000 ns" { /RESET THDD~2 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 22.000 ns \$00051 3 REG LC121 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 22.000 ns; Loc. = LC121; Fanout = 1; REG Node = '\$00051'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { THDD~2 $00051 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 490 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns ( 95.45 % ) " "Info: Total cell delay = 21.000 ns ( 95.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 4.55 % ) " "Info: Total interconnect delay = 1.000 ns ( 4.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { /RESET THDD~2 $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { /RESET {} THDD~2 {} $00051 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 16.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00051 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[3] /RESET } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[3] {} /RESET {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.000 ns" { /RESET THDD~2 $00051 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.000 ns" { /RESET {} THDD~2 {} $00051 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 16.000ns 5.000ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'TG42_IN' 57 " "Warning: Can't achieve timing requirement Clock Setup: 'TG42_IN' along 57 path(s). See Report window for details." { } { } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_SLACK_RESULT" "STE register LR_T\[0\] register REG_P\[2\] -21.0 ns " "Info: Slack time is -21.0 ns for clock \"STE\" between source register \"LR_T\[0\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "19.23 MHz 52.0 ns " "Info: Fmax is 19.23 MHz (period= 52.0 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-15.000 ns + Largest register register " "Info: + Largest register to register requirement is -15.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination STE 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"STE\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source STE 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"STE\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-16.000 ns + Largest " "Info: + Largest clock skew is -16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE destination 27.500 ns + Shortest register " "Info: + Shortest clock path from clock \"STE\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE source 43.500 ns - Longest register " "Info: - Longest clock path from clock \"STE\" to source register is 43.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns STWG\[2\]~6bal 5 COMB LC16 3 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 37.500 ns STWG\[2\] 6 REG LC19 6 " "Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 43.500 ns LR_T\[0\] 7 REG LC10 4 " "Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.500 ns ( 90.80 % ) " "Info: Total cell delay = 39.500 ns ( 90.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 9.20 % ) " "Info: Total interconnect delay = 4.000 ns ( 9.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Longest register register " "Info: - Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LR_T\[0\] 1 REG LC10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { STE TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'STE' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'STE' along 6 path(s). See Report window for details." { } { } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_SLACK_RESULT" "RSTB register LR_T\[0\] register REG_P\[2\] -21.0 ns " "Info: Slack time is -21.0 ns for clock \"RSTB\" between source register \"LR_T\[0\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "19.23 MHz 52.0 ns " "Info: Fmax is 19.23 MHz (period= 52.0 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-15.000 ns + Largest register register " "Info: + Largest register to register requirement is -15.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination RSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"RSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source RSTB 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"RSTB\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-16.000 ns + Largest " "Info: + Largest clock skew is -16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB destination 27.500 ns + Shortest register " "Info: + Shortest clock path from clock \"RSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB source 43.500 ns - Longest register " "Info: - Longest clock path from clock \"RSTB\" to source register is 43.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns STWG\[2\]~6bal 5 COMB LC16 3 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 37.500 ns STWG\[2\] 6 REG LC19 6 " "Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 43.500 ns LR_T\[0\] 7 REG LC10 4 " "Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.500 ns ( 90.80 % ) " "Info: Total cell delay = 39.500 ns ( 90.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 9.20 % ) " "Info: Total interconnect delay = 4.000 ns ( 9.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Longest register register " "Info: - Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LR_T\[0\] 1 REG LC10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'RSTB' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'RSTB' along 6 path(s). See Report window for details." { } { } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_SLACK_RESULT" "WSTB register LR_T\[0\] register REG_P\[2\] -21.0 ns " "Info: Slack time is -21.0 ns for clock \"WSTB\" between source register \"LR_T\[0\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "19.23 MHz 52.0 ns " "Info: Fmax is 19.23 MHz (period= 52.0 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-15.000 ns + Largest register register " "Info: + Largest register to register requirement is -15.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.000 ns + " "Info: + Setup relationship between source and destination is 5.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination WSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"WSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source WSTB 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"WSTB\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-16.000 ns + Largest " "Info: + Largest clock skew is -16.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB destination 27.500 ns + Shortest register " "Info: + Shortest clock path from clock \"WSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB source 43.500 ns - Longest register " "Info: - Longest clock path from clock \"WSTB\" to source register is 43.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns STWG\[2\]~6bal 5 COMB LC16 3 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 37.500 ns STWG\[2\] 6 REG LC19 6 " "Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 43.500 ns LR_T\[0\] 7 REG LC10 4 " "Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "39.500 ns ( 90.80 % ) " "Info: Total cell delay = 39.500 ns ( 90.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 9.20 % ) " "Info: Total interconnect delay = 4.000 ns ( 9.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns - " "Info: - Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Longest register register " "Info: - Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LR_T\[0\] 1 REG LC10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "43.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "43.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { LR_T[0] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { LR_T[0] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'WSTB' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'WSTB' along 6 path(s). See Report window for details." { } { } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "TG42_IN register FDD_1440 register \$00021 -12.2 ns " "Info: Minimum slack time is -12.2 ns for clock \"TG42_IN\" between source register \"FDD_1440\" and destination register \"\$00021\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.800 ns + Shortest register register " "Info: + Shortest register to register delay is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FDD_1440 1 REG LC91 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.800 ns) 8.800 ns RDAT_X~6 2 COMB LOOP LC21 6 " "Info: 2: + IC(0.000 ns) + CELL(8.800 ns) = 8.800 ns; Loc. = LC21; Fanout = 6; COMB LOOP Node = 'RDAT_X~6'" { { "Info" "ITDB_PART_OF_SCC" "RDAT_X~6 LC21 " "Info: Loc. = LC21; Node \"RDAT_X~6\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~6 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "RDAT_X~11 LC20 " "Info: Loc. = LC20; Node \"RDAT_X~11\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~11 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 326 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RDAT_X~11 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.800 ns" { FDD_1440 RDAT_X~6 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.800 ns \$00021 3 REG LC17 12 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.800 ns; Loc. = LC17; Fanout = 12; REG Node = '\$00021'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { RDAT_X~6 $00021 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 328 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.800 ns ( 93.24 % ) " "Info: Total cell delay = 13.800 ns ( 93.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 6.76 % ) " "Info: Total interconnect delay = 1.000 ns ( 6.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { FDD_1440 RDAT_X~6 $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { FDD_1440 {} RDAT_X~6 {} $00021 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 8.800ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "27.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 27.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination TG42_IN 10.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"TG42_IN\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source TG42_IN 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"TG42_IN\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "26.000 ns + Smallest " "Info: + Smallest clock skew is 26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 35.500 ns + Longest register " "Info: + Longest clock path from clock \"TG42_IN\" to destination register is 35.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 6.500 ns XCT\[2\]~4 2 COMB SEXP49 1 " "Info: 2: + IC(0.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP49; Fanout = 1; COMB Node = 'XCT\[2\]~4'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { TG42_IN XCT[2]~4 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 13.500 ns XCT\[1\] 3 REG LC56 18 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 13.500 ns; Loc. = LC56; Fanout = 18; REG Node = 'XCT\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { XCT[2]~4 XCT[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 113 5 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 21.500 ns lpm_counter:CT_rtl_0\|dffs\[0\] 4 REG LC122 9 " "Info: 4: + IC(1.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC122; Fanout = 9; REG Node = 'lpm_counter:CT_rtl_0\|dffs\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { XCT[1] lpm_counter:CT_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 29.500 ns CT_WG1~8bal 5 COMB LC28 7 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC28; Fanout = 7; COMB Node = 'CT_WG1~8bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 304 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 35.500 ns \$00021 6 REG LC17 12 " "Info: 6: + IC(1.000 ns) + CELL(5.000 ns) = 35.500 ns; Loc. = LC17; Fanout = 12; REG Node = '\$00021'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG1~8bal $00021 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 328 9 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "32.500 ns ( 91.55 % ) " "Info: Total cell delay = 32.500 ns ( 91.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 8.45 % ) " "Info: Total interconnect delay = 3.000 ns ( 8.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN source 9.500 ns - Shortest register " "Info: - Shortest clock path from clock \"TG42_IN\" to source register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns HDD_CLK 2 REG LC88 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TG42_IN HDD_CLK } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns FDD_1440 3 REG LC91 13 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { HDD_CLK FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 328 9 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { FDD_1440 RDAT_X~6 $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { FDD_1440 {} RDAT_X~6 {} $00021 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 8.800ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "35.500 ns" { TG42_IN XCT[2]~4 XCT[1] lpm_counter:CT_rtl_0|dffs[0] CT_WG1~8bal $00021 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "35.500 ns" { TG42_IN {} TG42_IN~out {} XCT[2]~4 {} XCT[1] {} lpm_counter:CT_rtl_0|dffs[0] {} CT_WG1~8bal {} $00021 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.500 ns" { TG42_IN HDD_CLK FDD_1440 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "9.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "TG42_IN 48 " "Warning: Can't achieve minimum setup and hold requirement TG42_IN along 48 path(s). See Report window for details." { } { } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "STE register REG_P\[1\] register REG_P\[2\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"STE\" between source register \"REG_P\[1\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_P\[1\] 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination STE 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"STE\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source STE 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"STE\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE destination 27.500 ns + Longest register " "Info: + Longest clock path from clock \"STE\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "STE source 27.500 ns - Shortest register " "Info: - Shortest clock path from clock \"STE\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns STE 1 CLK PIN_94 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STE } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 46 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STE TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[1\] 5 REG LC2 3 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { STE TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { STE {} STE~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "RSTB register REG_P\[1\] register REG_P\[2\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"RSTB\" between source register \"REG_P\[1\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_P\[1\] 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination RSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"RSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source RSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"RSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB destination 27.500 ns + Longest register " "Info: + Longest clock path from clock \"RSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RSTB source 27.500 ns - Shortest register " "Info: - Shortest clock path from clock \"RSTB\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns RSTB 1 CLK PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 38 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { RSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[1\] 5 REG LC2 3 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { RSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { RSTB {} RSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "WSTB register REG_P\[1\] register REG_P\[2\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"WSTB\" between source register \"REG_P\[1\]\" and destination register \"REG_P\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Shortest register register " "Info: + Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG_P\[1\] 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns REG_P\[2\] 2 REG LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination WSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"WSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.000 ns " "Info: - Launch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source WSTB 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Source clock \"WSTB\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB destination 27.500 ns + Longest register " "Info: + Longest clock path from clock \"WSTB\" to destination register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[2\] 5 REG LC8 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WSTB source 27.500 ns - Shortest register " "Info: - Shortest clock path from clock \"WSTB\" to source register is 27.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns WSTB 1 CLK PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { WSTB } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.500 ns TURBING~5 2 COMB LOOP LC32 3 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { WSTB TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns CT_WG~6 3 COMB SEXP17 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 21.500 ns CT_WG 4 REG LC26 8 " "Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 27.500 ns REG_P\[1\] 5 REG LC2 3 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P\[1\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { CT_WG REG_P[1] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.500 ns ( 92.73 % ) " "Info: Total cell delay = 25.500 ns ( 92.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 7.27 % ) " "Info: Total interconnect delay = 2.000 ns ( 7.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 138 7 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { REG_P[1] REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { REG_P[1] {} REG_P[2] {} } { 0.000ns 1.000ns } { 0.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "27.500 ns" { WSTB TURBING~5 CT_WG~6 CT_WG REG_P[1] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "27.500 ns" { WSTB {} WSTB~out {} TURBING~5 {} CT_WG~6 {} CT_WG {} REG_P[1] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 8.000ns 5.000ns 7.000ns 5.000ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1} +{ "Info" "ITDB_TSU_RESULT" "\$00052 FDD_C\[2\] TG42_IN 23.800 ns register " "Info: tsu for register \"\$00052\" (data pin = \"FDD_C\[2\]\", clock pin = \"TG42_IN\") is 23.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.300 ns + Longest pin register " "Info: + Longest pin to register delay is 23.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns FDD_C\[2\] 1 PIN PIN_46 20 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_46; Fanout = 20; PIN Node = 'FDD_C\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { FDD_C[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 59 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(16.800 ns) 17.300 ns NTHDD~11 2 COMB LOOP LC119 10 " "Info: 2: + IC(0.000 ns) + CELL(16.800 ns) = 17.300 ns; Loc. = LC119; Fanout = 10; COMB LOOP Node = 'NTHDD~11'" { { "Info" "ITDB_PART_OF_SCC" "NTHDD~11 LC119 " "Info: Loc. = LC119; Node \"NTHDD~11\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "THDD~2 LC114 " "Info: Loc. = LC114; Node \"THDD~2\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ITDB_PART_OF_SCC" "NTHDD~13 LC118 " "Info: Loc. = LC118; Node \"NTHDD~13\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~11 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 437 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { THDD~2 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 436 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { NTHDD~13 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "16.800 ns" { FDD_C[2] NTHDD~11 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 23.300 ns \$00052 3 REG LC123 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 23.300 ns; Loc. = LC123; Fanout = 1; REG Node = '\$00052'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { NTHDD~11 $00052 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "22.300 ns ( 95.71 % ) " "Info: Total cell delay = 22.300 ns ( 95.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 4.29 % ) " "Info: Total interconnect delay = 1.000 ns ( 4.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "23.300 ns" { FDD_C[2] NTHDD~11 $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "23.300 ns" { FDD_C[2] {} FDD_C[2]~out {} NTHDD~11 {} $00052 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 16.800ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"TG42_IN\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns \$00052 2 REG LC123 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC123; Fanout = 1; REG Node = '\$00052'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { TG42_IN $00052 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 494 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00052 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "23.300 ns" { FDD_C[2] NTHDD~11 $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "23.300 ns" { FDD_C[2] {} FDD_C[2]~out {} NTHDD~11 {} $00052 {} } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 16.800ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { TG42_IN $00052 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { TG42_IN {} TG42_IN~out {} $00052 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TCO_RESULT" "TG42_IN CLK_WG STWG\[2\] 50.000 ns register " "Info: tco from clock \"TG42_IN\" to destination pin \"CLK_WG\" through register \"STWG\[2\]\" is 50.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN source 46.500 ns + Longest register " "Info: + Longest clock path from clock \"TG42_IN\" to source register is 46.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns HDD_CLK 2 REG LC88 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TG42_IN HDD_CLK } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.500 ns FDD_1440 3 REG LC91 13 " "Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 11.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { HDD_CLK FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 19.500 ns TURBING~5 4 COMB LOOP LC32 3 " "Info: 4: + IC(0.000 ns) + CELL(8.000 ns) = 19.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { FDD_1440 TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 25.500 ns CT_WG~6 5 COMB SEXP17 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 25.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 32.500 ns CT_WG 6 REG LC26 8 " "Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 32.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 40.500 ns STWG\[2\]~6bal 7 COMB LC16 3 " "Info: 7: + IC(1.000 ns) + CELL(7.000 ns) = 40.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 46.500 ns STWG\[2\] 8 REG LC19 6 " "Info: 8: + IC(1.000 ns) + CELL(5.000 ns) = 46.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "42.500 ns ( 91.40 % ) " "Info: Total cell delay = 42.500 ns ( 91.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 8.60 % ) " "Info: Total interconnect delay = 4.000 ns ( 8.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "46.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "46.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STWG\[2\] 1 REG LC19 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK_WG 2 PIN PIN_13 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'CLK_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { STWG[2] CLK_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 299 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { STWG[2] CLK_WG } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { STWG[2] {} CLK_WG {} } { 0.000ns 0.000ns } { 0.000ns 1.500ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "46.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "46.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { STWG[2] CLK_WG } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { STWG[2] {} CLK_WG {} } { 0.000ns 0.000ns } { 0.000ns 1.500ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TPD_RESULT" "TG42_IN TG42_OUT 10.000 ns Longest " "Info: Longest tpd from source pin \"TG42_IN\" to destination pin \"TG42_OUT\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 8.500 ns \$00003~3 2 COMB LC128 1 " "Info: 2: + IC(0.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC128; Fanout = 1; COMB Node = '\$00003~3'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { TG42_IN $00003~3 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 183 14 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 10.000 ns TG42_OUT 3 PIN PIN_85 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 10.000 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'TG42_OUT'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { $00003~3 TG42_OUT } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 183 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 100.00 % ) " "Info: Total cell delay = 10.000 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { TG42_IN $00003~3 TG42_OUT } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { TG42_IN {} TG42_IN~out {} $00003~3 {} TG42_OUT {} } { 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 7.000ns 1.500ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_TH_RESULT" "LR_T\[0\] SR TG42_IN 51.000 ns register " "Info: th for register \"LR_T\[0\]\" (data pin = \"SR\", clock pin = \"TG42_IN\") is 51.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TG42_IN destination 54.500 ns + Longest register " "Info: + Longest clock path from clock \"TG42_IN\" to destination register is 54.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns TG42_IN 1 CLK PIN_87 11 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TG42_IN } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 21 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns HDD_CLK 2 REG LC88 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { TG42_IN HDD_CLK } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 472 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.500 ns FDD_1440 3 REG LC91 13 " "Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 11.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { HDD_CLK FDD_1440 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 417 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 19.500 ns TURBING~5 4 COMB LOOP LC32 3 " "Info: 4: + IC(0.000 ns) + CELL(8.000 ns) = 19.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5'" { { "Info" "ITDB_PART_OF_SCC" "TURBING~5 LC32 " "Info: Loc. = LC32; Node \"TURBING~5\"" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { TURBING~5 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 291 2 0 } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { FDD_1440 TURBING~5 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 25.500 ns CT_WG~6 5 COMB SEXP17 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 25.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { TURBING~5 CT_WG~6 } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 32.500 ns CT_WG 6 REG LC26 8 " "Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 32.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { CT_WG~6 CT_WG } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 294 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 40.500 ns STWG\[2\]~6bal 7 COMB LC16 3 " "Info: 7: + IC(1.000 ns) + CELL(7.000 ns) = 40.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG\[2\]~6bal'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { CT_WG STWG[2]~6bal } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 48.500 ns STWG\[2\] 8 REG LC19 6 " "Info: 8: + IC(1.000 ns) + CELL(7.000 ns) = 48.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG\[2\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { STWG[2]~6bal STWG[2] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 133 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 54.500 ns LR_T\[0\] 9 REG LC10 4 " "Info: 9: + IC(1.000 ns) + CELL(5.000 ns) = 54.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { STWG[2] LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "49.500 ns ( 90.83 % ) " "Info: Total cell delay = 49.500 ns ( 90.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns ( 9.17 % ) " "Info: Total interconnect delay = 5.000 ns ( 9.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "54.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "54.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" { } { { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SR 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'SR'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SR } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 37 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns LR_T\[0\] 2 REG LC10 4 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T\[0\]'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { SR LR_T[0] } "NODE_NAME" } } { "sp2_max.tdf" "" { Text "C:/Sprinter/src/altera/quartus/max/sp2_max.tdf" 160 6 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { SR LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { SR {} SR~out {} LR_T[0] {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "54.500 ns" { TG42_IN HDD_CLK FDD_1440 TURBING~5 CT_WG~6 CT_WG STWG[2]~6bal STWG[2] LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "54.500 ns" { TG42_IN {} TG42_IN~out {} HDD_CLK {} FDD_1440 {} TURBING~5 {} CT_WG~6 {} CT_WG {} STWG[2]~6bal {} STWG[2] {} LR_T[0] {} } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns 1.000ns 1.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 7.000ns 8.000ns 5.000ns 7.000ns 7.000ns 7.000ns 5.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { SR LR_T[0] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { SR {} SR~out {} LR_T[0] {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Critical Warning" "WTAN_REQUIREMENTS_NOT_MET_SLOW" "" "Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details." { } { } 1 0 "Timing requirements for slow timing model timing analysis were not met. See Report window for details." 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 21 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 03:30:43 2022 " "Info: Processing ended: Sun Aug 28 03:30:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/src/altera/quartus/max/db/sp2_max.tis_db_list.ddb b/src/altera/quartus/max/db/sp2_max.tis_db_list.ddb new file mode 100644 index 0000000..0bb4dde Binary files /dev/null and b/src/altera/quartus/max/db/sp2_max.tis_db_list.ddb differ diff --git a/src/altera/quartus/max/db/sp2_max.tmw_info b/src/altera/quartus/max/db/sp2_max.tmw_info new file mode 100644 index 0000000..ea806e0 --- /dev/null +++ b/src/altera/quartus/max/db/sp2_max.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:07 +start_analysis_synthesis:s:00:00:03-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:01-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/src/altera/quartus/max/incremental_db/README b/src/altera/quartus/max/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/src/altera/quartus/max/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/src/altera/quartus/max/incremental_db/compiled_partitions/sp2_max.root_partition.map.kpt b/src/altera/quartus/max/incremental_db/compiled_partitions/sp2_max.root_partition.map.kpt new file mode 100644 index 0000000..5a6b9cd --- /dev/null +++ b/src/altera/quartus/max/incremental_db/compiled_partitions/sp2_max.root_partition.map.kpt @@ -0,0 +1,246 @@ + + + + $00052 + + + $00051 + + + $00053 + + + $00050 + + + CTV8M + + SA0 + + + + $00049 + + + $00045 + + + $00046 + + + $00048 + + + XCT[2] + + NF + + + + $00041 + + + $00042 + + + $00043 + + + $00044 + + + + + + + $00052 + + + $00051 + + + $00053 + + + $00050 + + + $00049 + + + $00045 + + + $00046 + + + $00048 + + + $00041 + + + $00042 + + + $00043 + + + $00044 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 + + + -1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/altera/quartus/max/maxplusii_to_quartus_name_mapping.txt b/src/altera/quartus/max/maxplusii_to_quartus_name_mapping.txt new file mode 100644 index 0000000..dfa0e10 --- /dev/null +++ b/src/altera/quartus/max/maxplusii_to_quartus_name_mapping.txt @@ -0,0 +1,64 @@ + -- Copyright (C) 1991-2004 Altera Corporation + -- Any megafunction design, and related netlist (encrypted or decrypted), + -- support information, device programming or simulation file, and any other + -- associated documentation or information provided by Altera or a partner + -- under Altera's Megafunction Partnership Program may be used only + -- to program PLD devices (but not masked PLD devices) from Altera. Any + -- other use of such megafunction design, netlist, support information, + -- device programming or simulation file, or any other related documentation + -- or information is prohibited for any other purpose, including, but not + -- limited to modification, reverse engineering, de-compiling, or use with + -- any other silicon devices, unless such use is explicitly licensed under + -- a separate agreement with Altera or a megafunction partner. Title to the + -- intellectual property, including patents, copyrights, trademarks, trade + -- secrets, or maskworks, embodied in any such megafunction design, netlist, + -- support information, device programming or simulation file, or any other + -- related documentation or information provided by Altera or a megafunction + -- partner, remains with Altera, the megafunction partner, or their respective + -- licensors. No other licenses, including any licenses needed under any third + -- party's intellectual property, are provided herein. + + -- VERSION "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" + -- DATE "08/28/2022 03:22:37" + +Conversion results for sp2_max ++-----------------------+----------------------+ +| MAX+PLUS II node name | Quartus II node name | ++-----------------------+----------------------+ +| |10K_D0 | 10K_D[0] | +| |CLK14 | CLK[14] | +| |D0 | D[0] | +| |FDD_C0 | FDD_C[0] | +| |FDD_C1 | FDD_C[1] | +| |FDD_C2 | FDD_C[2] | +| |HDD_C0 | HDD_C[0] | +| |HDD_C1 | HDD_C[1] | +| |HDD_C2 | HDD_C[2] | +| |HDD_C3 | HDD_C[3] | +| |LR_T0 | LR_T[0] | +| |LR_T1 | LR_T[1] | +| |REG_P0 | REG_P[0] | +| |REG_P1 | REG_P[1] | +| |REG_P2 | REG_P[2] | +| |SINC_1 | SINC_[1] | +| |SINC_2 | SINC_[2] | +| |STWG0 | STWG[0] | +| |STWG1 | STWG[1] | +| |STWG2 | STWG[2] | +| |TR43 | TR[43] | +| |UNUSED33 | UNUSED[33] | +| |UNUSED53 | UNUSED[53] | +| |UNUSED65 | UNUSED[65] | +| |UNUSED78 | UNUSED[78] | +| |XA0 | XA[0] | +| |XA1 | XA[1] | +| |XA2 | XA[2] | +| |XCT0 | XCT[0] | +| |XCT1 | XCT[1] | +| |XHD1_CS1 | XHD1_CS[1] | +| |XHD1_CS2 | XHD1_CS[2] | +| |XHD2_CS1 | XHD2_CS[1] | +| |XHD2_CS2 | XHD2_CS[2] | ++-----------------------+----------------------+ + + diff --git a/src/altera/quartus/max/sp2_max.acf b/src/altera/quartus/max/sp2_max.acf new file mode 100644 index 0000000..689ae3e --- /dev/null +++ b/src/altera/quartus/max/sp2_max.acf @@ -0,0 +1,699 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP SP2_MAX +BEGIN + DEVICE = EPM7128STC100-10; + |UNUSED1: INPUT_PIN = 1; -- 7064 N.C. + |UNUSED2: INPUT_PIN = 2; -- 7064 N.C. +-- |VCCIO +-- |#TDI + |UNUSED5: INPUT_PIN = 5; -- 7064 N.C. + |CMOS_AS : OUTPUT_PIN = 6; + |UNUSED7: INPUT_PIN = 7; -- 7064 N.C. + |WR_PDOS : OUTPUT_PIN = 8; + |WD : INPUT_PIN = 9; + + |WSTB : INPUT_PIN = 10; +-- |GND + |TR43 : INPUT_PIN = 12; + |CLK_WG : OUTPUT_PIN = 13; + |FDAT : OUTPUT_PIN = 14; +-- |#TMS + |QDAT : OUTPUT_PIN = 16; + |XA0 : INPUT_PIN = 17; +-- |VCCIO + |SINC_2 : OUTPUT_PIN = 19; + + |SINC_1 : OUTPUT_PIN = 20; + |XA1 : INPUT_PIN = 21; + |UNUSED22: INPUT_PIN = 22; -- 7064 N.C. + |XA2 : INPUT_PIN = 23; + |UNUSED24: INPUT_PIN = 24; -- 7064 N.C. + |RSTB : INPUT_PIN = 25; +-- |GND + |UNUSED27: INPUT_PIN = 27; -- 7064 N.C. + |UNUSED28: INPUT_PIN = 28; -- 7064 N.C. + |SR : INPUT_PIN = 29; + + |SL : INPUT_PIN = 30; + |CLK14 : OUTPUT_PIN = 31; + |CLKZZ : BIDIR_PIN = 32; + |UNUSED33 : INPUT_PIN = 33; -- be careful! at 3000 family the pin 33 is GND +-- |VCCIO + |AUD : OUTPUT_PIN = 35; + |TG42_BUF : OUTPUT_PIN = 36; + |XACS : INPUT_PIN = 37; +-- |GND +-- |VCCINT + + |HDD_C3 : INPUT_PIN = 40; + |HDD_C2 : INPUT_PIN = 41; + |HDD_C1 : INPUT_PIN = 42; +-- |GND + |FDD_C0 : INPUT_PIN = 44; + |FDD_C1 : INPUT_PIN = 45; + |FDD_C2 : INPUT_PIN = 46; + |HDD_C0 : INPUT_PIN = 47; + |HD_DIR : OUTPUT_PIN = 48; + |UNUSED49: INPUT_PIN = 49; -- 7064 N.C. + + |UNUSED50: INPUT_PIN = 50; -- 7064 N.C. +-- |VCCIO + |HD_CS : OUTPUT_PIN = 52; + |UNUSED53 : INPUT_PIN = 53; -- 7064 N.C. + |/CONF_X : BIDIR_PIN = 54; + |UNUSED55: INPUT_PIN = 55; -- 7064 N.C. + |10K_CLK : OUTPUT_PIN = 56; + |WR_CNF : INPUT_PIN = 57; + |10K_D0 : OUTPUT_PIN = 58; +-- |GND + + |D0 : INPUT_PIN = 60; + |VGA_IN : INPUT_PIN = 61; +-- |#TCK + |UNUSED63: INPUT_PIN = 63; + |SINC_V : OUTPUT_PIN = 64; + |UNUSED65 : INPUT_PIN = 65; -- be careful! at 3000 family the pin 33 is GND +-- |VCCIO + |SINC : OUTPUT_PIN = 67; + |SINC_H : OUTPUT_PIN = 68; + |SINC_IN : INPUT_PIN = 69; + + |UNUSED70: INPUT_PIN = 70; -- 7064 N.C. + |XHD_RES : OUTPUT_PIN = 71; + |UNUSED72: INPUT_PIN = 72; -- 7064 N.C. +-- |#TDO +-- |GND + |XHD_WR : OUTPUT_PIN = 75; + |XHD_RD : OUTPUT_PIN = 76; + |UNUSED77: INPUT_PIN = 77; -- 7064 N.C. + |UNUSED78 : INPUT_PIN = 78; -- 7064 N.C. + |XHD1_CS1 : OUTPUT_PIN = 79; + + |XHD1_CS2 : OUTPUT_PIN = 80; + |XHD2_CS1 : OUTPUT_PIN = 81; +-- |VCCIO + |XHD2_CS2 : OUTPUT_PIN = 83; + |BEEP : OUTPUT_PIN = 84; + |TG42_OUT : OUTPUT_PIN = 85; +-- |GND + |TG42_IN : INPUT_PIN = 87; + |XHR_RDY : INPUT_PIN = 88; + |EPM_RES : INPUT_PIN = 89; + + |PW_GOOD : INPUT_PIN = 90; +-- |VCCINT + |RDAT : INPUT_PIN = 92; + |/WG_WR : OUTPUT_PIN = 93; + |STE : INPUT_PIN = 94; +-- |GND + |DENS_X : OUTPUT_PIN = 96; + |/WG_RD : OUTPUT_PIN = 97; + |WDAT : OUTPUT_PIN = 98; + |CMOS_DRD : OUTPUT_PIN = 99; + |CMOS_DWR : OUTPUT_PIN = 100; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EPM7256SQC208-7; + AUTO_DEVICE = EPM7256SRC208-7; + AUTO_DEVICE = EPM7192SQC160-7; + AUTO_DEVICE = EPM7160SQC160-6; + AUTO_DEVICE = EPM7160STC100-6; + AUTO_DEVICE = EPM7160SLC84-6; + AUTO_DEVICE = EPM7128SQC160-6; + AUTO_DEVICE = EPM7128STC100-6; + AUTO_DEVICE = EPM7128SQC100-6; + AUTO_DEVICE = EPM7128SLC84-6; + AUTO_DEVICE = EPM7064STC100-5; + AUTO_DEVICE = EPM7064SLC84-5; + AUTO_DEVICE = EPM7064STC44-5; + AUTO_DEVICE = EPM7064SLC44-5; + AUTO_DEVICE = EPM7032STC44-5; + AUTO_DEVICE = EPM7032SLC44-5; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EPM7128STC100-10; + FREQUENCY = 100MHz; + MAINTAIN_STABLE_SYNTHESIS = OFF; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; +END; + +IGNORED_ASSIGNMENTS +BEGIN + FIT_IGNORE_TIMING = ON; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +LOGIC_OPTIONS +BEGIN + |LR_T1 : TURBO_BIT = ON; + |LR_T0 : TURBO_BIT = ON; + |CLK_WG : TURBO_BIT = ON; + |TG42_BUF : STYLE = WYSIWYG; + |TG42_OUT : STYLE = WYSIWYG; + |XHD_RD : TURBO_BIT = OFF; + |XHD_RES : TURBO_BIT = OFF; + |XHD_WR : TURBO_BIT = OFF; + |XHD1_CS1 : TURBO_BIT = OFF; + |XHD1_CS2 : TURBO_BIT = OFF; + |XHD2_CS1 : TURBO_BIT = OFF; + |XHD2_CS2 : TURBO_BIT = OFF; + |10K_CLK : TURBO_BIT = OFF; + |10K_D0 : TURBO_BIT = OFF; + |REG_P0 : TURBO_BIT = ON; + |REG_P1 : TURBO_BIT = ON; + |REG_P2 : TURBO_BIT = ON; + |TG42_BUF : TURBO_BIT = ON; + |TG42_OUT : TURBO_BIT = ON; + |STWG0 : TURBO_BIT = ON; + |STWG1 : TURBO_BIT = ON; + |STWG2 : TURBO_BIT = ON; + |XCT0 : TURBO_BIT = ON; + |XCT1 : TURBO_BIT = ON; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + MULTIVOLT_IO = OFF; + SECURITY_BIT = ON; + MAX7000B_ENABLE_VREFB = OFF; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + FLEX_CONFIGURATION_EPROM = AUTO; + MAX7000AE_ENABLE_JTAG = ON; + MAX7000AE_USER_CODE = FFFFFFFF; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + MAX7000S_ENABLE_JTAG = ON; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_USER_CODE = FFFF; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + nCEO = UNRESERVED; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + DATA0 = RESERVED_TRI_STATED; + FLEX8000_ENABLE_JTAG = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + DISABLE_TIME_OUT = OFF; + ENABLE_DCLK_OUTPUT = OFF; + RELEASE_CLEARS = OFF; + AUTO_RESTART = OFF; + USER_CLOCK = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + STYLE = NORMAL; + AUTO_GLOBAL_CLEAR = OFF; + AUTO_GLOBAL_CLOCK = OFF; + DEVICE_FAMILY = MAX7000S; + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_REGISTER_PACKING = OFF; + AUTO_FAST_IO = OFF; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_PRESET = ON; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; + OPTIMIZE_FOR_SPEED = 5; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + FITTER_SETTINGS = ADVANCED; + USE_QUARTUS_FITTER = OFF; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; + SMART_RECOMPILE = OFF; + GENERATE_AHDL_TDO_FILE = OFF; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + TIMING_SNF_EXTRACTOR = ON; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + DESIGN_DOCTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VHDL_WRITER_VERSION = VHDL87; + VHDL_READER_VERSION = VHDL87; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + MASTER_RESET = OFF; + EXPANDER_NETWORKS = ON; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + ASYNCHRONOUS_INPUTS = ON; + PRESET_CLEAR_NETWORKS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_CLOCK_NETWORKS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + END_TIME = 25.0us; + BIDIR_PIN = STRONG; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + ANALYSIS_MODE = REGISTERED_PERFORMANCE; + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; + LIST_PATH_FREQUENCY = 10MHz; + LIST_PATH_COUNT = 10; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; +END; + +OTHER_CONFIGURATION +BEGIN + LAST_MAXPLUS2_VERSION = 10.0; + ROW_PINS_LCELL_INSERT = ON; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + NORMAL_LCELL_INSERT = ON; + EXPLICIT_FAMILY = 1; + FLEX_10K_52_COLUMNS = 40; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ROW_PINS_PERCENT = 50; + ORIGINAL_MAXPLUS2_VERSION = 9.6; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + TURBO_BIT = ON; + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + CARRY_CHAIN_LENGTH = 32; + CASCADE_CHAIN_LENGTH = 2; + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + IGNORE_SOFT_BUFFERS = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + TURBO_BIT = ON; + SLOW_SLEW_RATE = OFF; + XOR_SYNTHESIS = ON; + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = ON; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + CARRY_CHAIN_LENGTH = 32; + CASCADE_CHAIN_LENGTH = 2; + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN = AUTO; + MINIMIZATION = FULL; + IGNORE_SOFT_BUFFERS = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/src/altera/quartus/max/sp2_max.asm.rpt b/src/altera/quartus/max/sp2_max.asm.rpt new file mode 100644 index 0000000..64aa208 --- /dev/null +++ b/src/altera/quartus/max/sp2_max.asm.rpt @@ -0,0 +1,109 @@ +Assembler report for sp2_max +Sun Aug 28 03:30:42 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Sprinter/src/altera/quartus/max/sp2_max.pof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sun Aug 28 03:30:42 2022 ; +; Revision Name ; sp2_max ; +; Top-level Entity Name ; SP2_MAX ; +; Family ; MAX7000S ; +; Device ; EPM7128STC100-10 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Security bit ; On ; Off ; +; Use smart compilation ; Off ; Off ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------+ +; File Name ; ++------------------------------------------------+ +; C:/Sprinter/src/altera/quartus/max/sp2_max.pof ; ++------------------------------------------------+ + + ++--------------------------------------------------------------------------+ +; Assembler Device Options: C:/Sprinter/src/altera/quartus/max/sp2_max.pof ; ++----------------+---------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------+ +; Device ; EPM7128STC100-10 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x00197ABF ; ++----------------+---------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Sun Aug 28 03:30:42 2022 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 199 megabytes + Info: Processing ended: Sun Aug 28 03:30:42 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/src/altera/quartus/max/sp2_max.done b/src/altera/quartus/max/sp2_max.done new file mode 100644 index 0000000..f4d59a9 --- /dev/null +++ b/src/altera/quartus/max/sp2_max.done @@ -0,0 +1 @@ +Sun Aug 28 03:30:44 2022 diff --git a/src/altera/quartus/max/sp2_max.dpf b/src/altera/quartus/max/sp2_max.dpf new file mode 100644 index 0000000..f0b3ecc --- /dev/null +++ b/src/altera/quartus/max/sp2_max.dpf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/src/altera/quartus/max/sp2_max.eda.rpt b/src/altera/quartus/max/sp2_max.eda.rpt new file mode 100644 index 0000000..408201d --- /dev/null +++ b/src/altera/quartus/max/sp2_max.eda.rpt @@ -0,0 +1,59 @@ +EDA Netlist Writer report for sp2_max +Sun Aug 28 03:26:23 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+------------------------------------------------------+ +; EDA Netlist Writer Status ; No Output Files Generated - Sun Aug 28 03:26:23 2022 ; +; Revision Name ; sp2_max ; +; Top-level Entity Name ; SP2_MAX ; +; Family ; MAX7000S ; ++---------------------------+------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II EDA Netlist Writer + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Sun Aug 28 03:26:23 2022 +Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max +Warning: Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script. +Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 163 megabytes + Info: Processing ended: Sun Aug 28 03:26:23 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/src/altera/quartus/max/sp2_max.fit.rpt b/src/altera/quartus/max/sp2_max.fit.rpt new file mode 100644 index 0000000..c95d907 --- /dev/null +++ b/src/altera/quartus/max/sp2_max.fit.rpt @@ -0,0 +1,710 @@ +Fitter report for sp2_max +Sun Aug 28 03:30:41 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Pin-Out File + 6. Fitter Resource Usage Summary + 7. Input Pins + 8. Output Pins + 9. Bidir Pins + 10. All Package Pins + 11. I/O Standard + 12. Dedicated Inputs I/O + 13. Output Pin Default Load For Reported TCO + 14. Fitter Resource Utilization by Entity + 15. Control Signals + 16. Global & Other Fast Signals + 17. Non-Global High Fan-Out Signals + 18. Interconnect Usage Summary + 19. LAB External Interconnect + 20. LAB Macrocells + 21. Parallel Expander + 22. Shareable Expander + 23. Logic Cell Interconnection + 24. Fitter Device Options + 25. Fitter Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------+ +; Fitter Summary ; ++-----------------------+----------------------------------------------+ +; Fitter Status ; Successful - Sun Aug 28 03:30:40 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; sp2_max ; +; Top-level Entity Name ; SP2_MAX ; +; Family ; MAX7000S ; +; Device ; EPM7128STC100-10 ; +; Timing Models ; Final ; +; Total macrocells ; 74 / 128 ( 58 % ) ; +; Total pins ; 84 / 84 ( 100 % ) ; ++-----------------------+----------------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------+------------------+---------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------+------------------+---------------+ +; Device ; EPM7128STC100-10 ; ; +; Use smart compilation ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Slow Slew Rate ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++----------------------------------------------------+------------------+---------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Sprinter/src/altera/quartus/max/sp2_max.pin. + + ++-------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-----------------------------------+-------------------+ +; Resource ; Usage ; ++-----------------------------------+-------------------+ +; Logic cells ; 74 / 128 ( 58 % ) ; +; Registers ; 57 / 128 ( 45 % ) ; +; Number of pterms used ; 195 ; +; User inserted logic elements ; 0 ; +; I/O pins ; 84 / 84 ( 100 % ) ; +; -- Clock pins ; 2 / 2 ( 100 % ) ; +; -- Dedicated input pins ; 2 / 2 ( 100 % ) ; +; Global signals ; 2 ; +; Shareable expanders ; 11 / 128 ( 9 % ) ; +; Parallel expanders ; 3 / 120 ( 3 % ) ; +; Cells using turbo bit ; 74 / 128 ( 58 % ) ; +; Maximum fan-out node ; HDD_C[2] ; +; Maximum fan-out ; 21 ; +; Highest non-global fan-out signal ; HDD_C[2] ; +; Highest non-global fan-out ; 21 ; +; Total fan-out ; 438 ; +; Average fan-out ; 2.59 ; ++-----------------------------------+-------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ +; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ; ++----------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ +; D0 ; 60 ; -- ; 6 ; 1 ; 0 ; no ; no ; TTL ; User ; +; EPM_RES ; 89 ; -- ; -- ; 2 ; 0 ; yes ; no ; TTL ; User ; +; FDD_C[0] ; 44 ; -- ; 5 ; 14 ; 0 ; no ; no ; TTL ; User ; +; FDD_C[1] ; 45 ; -- ; 5 ; 17 ; 0 ; no ; no ; TTL ; User ; +; FDD_C[2] ; 46 ; -- ; 5 ; 15 ; 0 ; no ; no ; TTL ; User ; +; HDD_C[0] ; 47 ; -- ; 5 ; 16 ; 0 ; no ; no ; TTL ; User ; +; HDD_C[1] ; 42 ; -- ; 5 ; 19 ; 0 ; no ; no ; TTL ; User ; +; HDD_C[2] ; 41 ; -- ; 5 ; 21 ; 0 ; no ; no ; TTL ; User ; +; HDD_C[3] ; 40 ; -- ; 5 ; 18 ; 0 ; no ; no ; TTL ; User ; +; PW_GOOD ; 90 ; -- ; -- ; 1 ; 0 ; no ; no ; TTL ; User ; +; RDAT ; 92 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; +; RSTB ; 25 ; -- ; 3 ; 1 ; 0 ; no ; no ; TTL ; User ; +; SINC_IN ; 69 ; -- ; 7 ; 0 ; 0 ; no ; no ; TTL ; User ; +; SL ; 30 ; -- ; 4 ; 1 ; 0 ; no ; no ; TTL ; User ; +; SR ; 29 ; -- ; 4 ; 1 ; 0 ; no ; no ; TTL ; User ; +; STE ; 94 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ; +; TG42_IN ; 87 ; -- ; -- ; 11 ; 0 ; yes ; no ; TTL ; User ; +; TR43 ; 12 ; -- ; 2 ; 2 ; 0 ; no ; no ; TTL ; User ; +; UNUSED1 ; 50 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED2 ; 27 ; -- ; 4 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED22 ; 22 ; -- ; 3 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED24 ; 70 ; -- ; 7 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED27 ; 7 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED28 ; 28 ; -- ; 4 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED33 ; 33 ; -- ; 4 ; 0 ; 0 ; no ; no ; TTL ; User ; +; UNUSED49 ; 49 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED5 ; 72 ; -- ; 7 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED50 ; 24 ; -- ; 3 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED53 ; 53 ; -- ; 6 ; 0 ; 0 ; no ; no ; TTL ; User ; +; UNUSED55 ; 1 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED63 ; 55 ; -- ; 6 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED65 ; 65 ; -- ; 7 ; 0 ; 0 ; no ; no ; TTL ; User ; +; UNUSED7 ; 77 ; -- ; 8 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED70 ; 5 ; -- ; 2 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED72 ; 2 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED77 ; 63 ; -- ; 7 ; 0 ; 0 ; no ; no ; TTL ; Fitter ; +; UNUSED78 ; 78 ; -- ; 8 ; 0 ; 0 ; no ; no ; TTL ; User ; +; VGA_IN ; 61 ; -- ; 6 ; 0 ; 0 ; no ; no ; TTL ; User ; +; WD ; 9 ; -- ; 2 ; 2 ; 0 ; no ; no ; TTL ; User ; +; WR_CNF ; 57 ; -- ; 6 ; 1 ; 0 ; no ; no ; TTL ; User ; +; WSTB ; 10 ; -- ; 2 ; 1 ; 0 ; no ; no ; TTL ; User ; +; XACS ; 37 ; -- ; 4 ; 1 ; 0 ; no ; no ; TTL ; User ; +; XA[0] ; 17 ; -- ; 3 ; 0 ; 0 ; no ; no ; TTL ; User ; +; XA[1] ; 21 ; -- ; 3 ; 0 ; 0 ; no ; no ; TTL ; User ; +; XA[2] ; 23 ; -- ; 3 ; 0 ; 0 ; no ; no ; TTL ; User ; +; XHR_RDY ; 88 ; -- ; -- ; 0 ; 0 ; no ; no ; TTL ; User ; ++----------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+ +; Name ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load ; ++------------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+ +; /WG_RD ; 97 ; -- ; 1 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; /WG_WR ; 93 ; -- ; 1 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; 10K_CLK ; 56 ; -- ; 6 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; 10K_D0 ; 58 ; -- ; 6 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; AUD ; 35 ; -- ; 4 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; BEEP ; 84 ; -- ; 8 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; CLK14 ; 31 ; -- ; 4 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; CLK_WG ; 13 ; -- ; 2 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; CMOS_AS ; 6 ; -- ; 2 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; CMOS_DRD ; 99 ; -- ; 1 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; CMOS_DWR ; 100 ; -- ; 1 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; DENS_X ; 96 ; -- ; 1 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; FDAT ; 14 ; -- ; 2 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; HD_CS ; 52 ; -- ; 6 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; HD_DIR ; 48 ; -- ; 5 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; QDAT ; 16 ; -- ; 3 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; SINC ; 67 ; -- ; 7 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; SINC_H ; 68 ; -- ; 7 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; SINC_V ; 64 ; -- ; 7 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; TG42_BUF ; 36 ; -- ; 4 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; TG42_OUT ; 85 ; -- ; 8 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; WDAT ; 98 ; -- ; 1 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; WR_PDOS ; 8 ; -- ; 2 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; XHD1_CS[1] ; 79 ; -- ; 8 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; XHD1_CS[2] ; 80 ; -- ; 8 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; XHD2_CS[1] ; 81 ; -- ; 8 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; XHD2_CS[2] ; 83 ; -- ; 8 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; XHD_RD ; 76 ; -- ; 8 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; XHD_RES ; 71 ; -- ; 7 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; XHD_WR ; 75 ; -- ; 8 ; no ; no ; no ; no ; TTL ; User ; 10 pF ; ++------------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+ +; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Slow Slew Rate ; Open Drain ; I/O Standard ; Location assigned by ; Load ; ++---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+ +; /CONF_X ; 54 ; -- ; 6 ; 0 ; 0 ; no ; no ; no ; no ; yes ; TTL ; User ; 10 pF ; +; CLKZZ ; 32 ; -- ; 4 ; 0 ; 0 ; no ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; SINC_1 ; 20 ; -- ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; TTL ; User ; 10 pF ; +; SINC_2 ; 19 ; -- ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; TTL ; User ; 10 pF ; ++---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+-----------------+----------------+------------+--------------+----------------------+-------+ + + ++-------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+----------------+--------+--------------+---------+-----------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; User Assignment ; ++----------+------------+----------+----------------+--------+--------------+---------+-----------------+ +; 1 ; 12 ; -- ; UNUSED55 ; input ; TTL ; ; N ; +; 2 ; 13 ; -- ; UNUSED72 ; input ; TTL ; ; N ; +; 3 ; 14 ; -- ; VCCIO ; power ; ; 5.0V ; ; +; 4 ; 15 ; -- ; TDI ; input ; TTL ; ; N ; +; 5 ; 16 ; -- ; UNUSED70 ; input ; TTL ; ; N ; +; 6 ; 17 ; -- ; CMOS_AS ; output ; TTL ; ; Y ; +; 7 ; 18 ; -- ; UNUSED27 ; input ; TTL ; ; N ; +; 8 ; 19 ; -- ; WR_PDOS ; output ; TTL ; ; Y ; +; 9 ; 20 ; -- ; WD ; input ; TTL ; ; Y ; +; 10 ; 21 ; -- ; WSTB ; input ; TTL ; ; Y ; +; 11 ; 22 ; -- ; GND ; gnd ; ; ; ; +; 12 ; 23 ; -- ; TR43 ; input ; TTL ; ; Y ; +; 13 ; 24 ; -- ; CLK_WG ; output ; TTL ; ; Y ; +; 14 ; 25 ; -- ; FDAT ; output ; TTL ; ; Y ; +; 15 ; 26 ; -- ; TMS ; input ; TTL ; ; N ; +; 16 ; 27 ; -- ; QDAT ; output ; TTL ; ; Y ; +; 17 ; 28 ; -- ; XA[0] ; input ; TTL ; ; Y ; +; 18 ; 29 ; -- ; VCCIO ; power ; ; 5.0V ; ; +; 19 ; 30 ; -- ; SINC_2 ; bidir ; TTL ; ; Y ; +; 20 ; 31 ; -- ; SINC_1 ; bidir ; TTL ; ; Y ; +; 21 ; 32 ; -- ; XA[1] ; input ; TTL ; ; Y ; +; 22 ; 33 ; -- ; UNUSED22 ; input ; TTL ; ; N ; +; 23 ; 34 ; -- ; XA[2] ; input ; TTL ; ; Y ; +; 24 ; 35 ; -- ; UNUSED50 ; input ; TTL ; ; N ; +; 25 ; 36 ; -- ; RSTB ; input ; TTL ; ; Y ; +; 26 ; 37 ; -- ; GND ; gnd ; ; ; ; +; 27 ; 38 ; -- ; UNUSED2 ; input ; TTL ; ; N ; +; 28 ; 39 ; -- ; UNUSED28 ; input ; TTL ; ; N ; +; 29 ; 40 ; -- ; SR ; input ; TTL ; ; Y ; +; 30 ; 41 ; -- ; SL ; input ; TTL ; ; Y ; +; 31 ; 42 ; -- ; CLK14 ; output ; TTL ; ; Y ; +; 32 ; 43 ; -- ; CLKZZ ; bidir ; TTL ; ; Y ; +; 33 ; 44 ; -- ; UNUSED33 ; input ; TTL ; ; Y ; +; 34 ; 45 ; -- ; VCCIO ; power ; ; 5.0V ; ; +; 35 ; 46 ; -- ; AUD ; output ; TTL ; ; Y ; +; 36 ; 47 ; -- ; TG42_BUF ; output ; TTL ; ; Y ; +; 37 ; 48 ; -- ; XACS ; input ; TTL ; ; Y ; +; 38 ; 49 ; -- ; GND ; gnd ; ; ; ; +; 39 ; 50 ; -- ; VCCINT ; power ; ; 5.0V ; ; +; 40 ; 51 ; -- ; HDD_C[3] ; input ; TTL ; ; Y ; +; 41 ; 52 ; -- ; HDD_C[2] ; input ; TTL ; ; Y ; +; 42 ; 53 ; -- ; HDD_C[1] ; input ; TTL ; ; Y ; +; 43 ; 54 ; -- ; GND ; gnd ; ; ; ; +; 44 ; 55 ; -- ; FDD_C[0] ; input ; TTL ; ; Y ; +; 45 ; 56 ; -- ; FDD_C[1] ; input ; TTL ; ; Y ; +; 46 ; 57 ; -- ; FDD_C[2] ; input ; TTL ; ; Y ; +; 47 ; 58 ; -- ; HDD_C[0] ; input ; TTL ; ; Y ; +; 48 ; 59 ; -- ; HD_DIR ; output ; TTL ; ; Y ; +; 49 ; 60 ; -- ; UNUSED49 ; input ; TTL ; ; N ; +; 50 ; 61 ; -- ; UNUSED1 ; input ; TTL ; ; N ; +; 51 ; 62 ; -- ; VCCIO ; power ; ; 5.0V ; ; +; 52 ; 63 ; -- ; HD_CS ; output ; TTL ; ; Y ; +; 53 ; 64 ; -- ; UNUSED53 ; input ; TTL ; ; Y ; +; 54 ; 65 ; -- ; /CONF_X ; bidir ; TTL ; ; Y ; +; 55 ; 66 ; -- ; UNUSED63 ; input ; TTL ; ; N ; +; 56 ; 67 ; -- ; 10K_CLK ; output ; TTL ; ; Y ; +; 57 ; 68 ; -- ; WR_CNF ; input ; TTL ; ; Y ; +; 58 ; 69 ; -- ; 10K_D0 ; output ; TTL ; ; Y ; +; 59 ; 70 ; -- ; GND ; gnd ; ; ; ; +; 60 ; 71 ; -- ; D0 ; input ; TTL ; ; Y ; +; 61 ; 72 ; -- ; VGA_IN ; input ; TTL ; ; Y ; +; 62 ; 73 ; -- ; TCK ; input ; TTL ; ; N ; +; 63 ; 74 ; -- ; UNUSED77 ; input ; TTL ; ; N ; +; 64 ; 75 ; -- ; SINC_V ; output ; TTL ; ; Y ; +; 65 ; 76 ; -- ; UNUSED65 ; input ; TTL ; ; Y ; +; 66 ; 77 ; -- ; VCCIO ; power ; ; 5.0V ; ; +; 67 ; 78 ; -- ; SINC ; output ; TTL ; ; Y ; +; 68 ; 79 ; -- ; SINC_H ; output ; TTL ; ; Y ; +; 69 ; 80 ; -- ; SINC_IN ; input ; TTL ; ; Y ; +; 70 ; 81 ; -- ; UNUSED24 ; input ; TTL ; ; N ; +; 71 ; 82 ; -- ; XHD_RES ; output ; TTL ; ; Y ; +; 72 ; 83 ; -- ; UNUSED5 ; input ; TTL ; ; N ; +; 73 ; 84 ; -- ; TDO ; output ; TTL ; ; N ; +; 74 ; 85 ; -- ; GND ; gnd ; ; ; ; +; 75 ; 86 ; -- ; XHD_WR ; output ; TTL ; ; Y ; +; 76 ; 87 ; -- ; XHD_RD ; output ; TTL ; ; Y ; +; 77 ; 88 ; -- ; UNUSED7 ; input ; TTL ; ; N ; +; 78 ; 89 ; -- ; UNUSED78 ; input ; TTL ; ; Y ; +; 79 ; 90 ; -- ; XHD1_CS[1] ; output ; TTL ; ; Y ; +; 80 ; 91 ; -- ; XHD1_CS[2] ; output ; TTL ; ; Y ; +; 81 ; 92 ; -- ; XHD2_CS[1] ; output ; TTL ; ; Y ; +; 82 ; 93 ; -- ; VCCIO ; power ; ; 5.0V ; ; +; 83 ; 94 ; -- ; XHD2_CS[2] ; output ; TTL ; ; Y ; +; 84 ; 95 ; -- ; BEEP ; output ; TTL ; ; Y ; +; 85 ; 96 ; -- ; TG42_OUT ; output ; TTL ; ; Y ; +; 86 ; 97 ; -- ; GND ; gnd ; ; ; ; +; 87 ; 98 ; -- ; TG42_IN ; input ; TTL ; ; Y ; +; 88 ; 99 ; -- ; XHR_RDY ; input ; TTL ; ; Y ; +; 89 ; 0 ; -- ; EPM_RES ; input ; TTL ; ; Y ; +; 90 ; 1 ; -- ; PW_GOOD ; input ; TTL ; ; Y ; +; 91 ; 2 ; -- ; VCCINT ; power ; ; 5.0V ; ; +; 92 ; 3 ; -- ; RDAT ; input ; TTL ; ; Y ; +; 93 ; 4 ; -- ; /WG_WR ; output ; TTL ; ; Y ; +; 94 ; 5 ; -- ; STE ; input ; TTL ; ; Y ; +; 95 ; 6 ; -- ; GND ; gnd ; ; ; ; +; 96 ; 7 ; -- ; DENS_X ; output ; TTL ; ; Y ; +; 97 ; 8 ; -- ; /WG_RD ; output ; TTL ; ; Y ; +; 98 ; 9 ; -- ; WDAT ; output ; TTL ; ; Y ; +; 99 ; 10 ; -- ; CMOS_DRD ; output ; TTL ; ; Y ; +; 100 ; 11 ; -- ; CMOS_DWR ; output ; TTL ; ; Y ; ++----------+------------+----------+----------------+--------+--------------+---------+-----------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++--------------------------------------------------------------------------------------------------+ +; I/O Standard ; ++--------------+------------+----------------------+-------------------+-------------------+-------+ +; I/O Standard ; Input Vref ; Dedicated Input Pins ; Pins in I/O Bank1 ; Pins in I/O Bank2 ; Total ; ++--------------+------------+----------------------+-------------------+-------------------+-------+ +; TTL ; - ; 4 ; 0 ; 0 ; 4 ; ++--------------+------------+----------------------+-------------------+-------------------+-------+ + + ++-----------------------------------------------------------------------+ +; Dedicated Inputs I/O ; ++---------+-------+-------+-------+--------------+------------+---------+ +; Name ; Pin # ; Type ; VCCIO ; I/O Standard ; Input Vref ; Current ; ++---------+-------+-------+-------+--------------+------------+---------+ +; EPM_RES ; 89 ; Input ; -- ; TTL ; - ; 0 mA ; +; PW_GOOD ; 90 ; Input ; -- ; TTL ; - ; 0 mA ; +; TG42_IN ; 87 ; Input ; -- ; TTL ; - ; 0 mA ; +; XHR_RDY ; 88 ; Input ; -- ; TTL ; - ; 0 mA ; ++---------+-------+-------+-------+--------------+------------+---------+ + + ++-----------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++--------------+-------+------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++--------------+-------+------------------------+ +; 3.3-V LVTTL ; 10 pF ; Not Available ; +; 3.3-V LVCMOS ; 10 pF ; Not Available ; +; TTL ; 10 pF ; Not Available ; ++--------------+-------+------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+------------+------+--------------------------------+--------------+ +; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+------------+------+--------------------------------+--------------+ +; |SP2_MAX ; 74 ; 84 ; |SP2_MAX ; work ; +; |lpm_counter:CTH_rtl_2| ; 6 ; 0 ; |SP2_MAX|lpm_counter:CTH_rtl_2 ; work ; +; |lpm_counter:CTV_rtl_1| ; 9 ; 0 ; |SP2_MAX|lpm_counter:CTV_rtl_1 ; work ; +; |lpm_counter:CT_rtl_0| ; 4 ; 0 ; |SP2_MAX|lpm_counter:CT_rtl_0 ; work ; ++----------------------------+------------+------+--------------------------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------------------------------+----------+---------+----------------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++------------------------------+----------+---------+----------------------+--------+----------------------+------------------+ +; $00049~4 ; SEXP114 ; 2 ; Preset ; no ; -- ; -- ; +; /RESET ; LC85 ; 11 ; Preset ; no ; -- ; -- ; +; CT_WG ; LC26 ; 6 ; Clock ; no ; -- ; -- ; +; CT_WG1~8bal ; LC28 ; 7 ; Clock ; no ; -- ; -- ; +; CT_WG~4 ; SEXP19 ; 1 ; Clock ; no ; -- ; -- ; +; CT_WG~5 ; SEXP18 ; 1 ; Clock ; no ; -- ; -- ; +; CT_WG~6 ; SEXP17 ; 1 ; Clock ; no ; -- ; -- ; +; EPM_RES ; PIN_89 ; 2 ; Async. clear ; yes ; On ; -- ; +; FDD_1440~10 ; SEXP81 ; 1 ; Preset ; no ; -- ; -- ; +; FDD_C[0] ; PIN_44 ; 14 ; Async. clear ; no ; -- ; -- ; +; FDD_C[1] ; PIN_45 ; 17 ; Async. clear ; no ; -- ; -- ; +; FDD_C[2] ; PIN_46 ; 15 ; Async. clear, Preset ; no ; -- ; -- ; +; HDD_CLK ; LC88 ; 10 ; Clock ; no ; -- ; -- ; +; HDD_C[0] ; PIN_47 ; 16 ; Async. clear ; no ; -- ; -- ; +; HDD_C[1] ; PIN_42 ; 19 ; Async. clear ; no ; -- ; -- ; +; HDD_C[2] ; PIN_41 ; 21 ; Async. clear ; no ; -- ; -- ; +; HDD_C[3] ; PIN_40 ; 18 ; Async. clear ; no ; -- ; -- ; +; SINC_HT ; LC104 ; 16 ; Clock ; no ; -- ; -- ; +; SINC_VT ; LC99 ; 10 ; Clock ; no ; -- ; -- ; +; STWG[2] ; LC19 ; 4 ; Clock ; no ; -- ; -- ; +; STWG[2]~6bal ; LC16 ; 3 ; Clock ; no ; -- ; -- ; +; TG42_IN ; PIN_87 ; 11 ; Clock ; yes ; On ; -- ; +; XACS ; PIN_37 ; 1 ; Async. clear ; no ; -- ; -- ; +; XCT[0] ; LC124 ; 2 ; Clock ; no ; -- ; -- ; +; XCT[1] ; LC56 ; 15 ; Clock ; no ; -- ; -- ; +; XCT[2]~11 ; SEXP115 ; 1 ; Clock ; no ; -- ; -- ; +; XCT[2]~12 ; SEXP116 ; 1 ; Clock ; no ; -- ; -- ; +; XCT[2]~3 ; SEXP51 ; 1 ; Clock ; no ; -- ; -- ; +; XCT[2]~4 ; SEXP49 ; 1 ; Clock ; no ; -- ; -- ; +; lpm_counter:CT_rtl_0|dffs[3] ; LC53 ; 9 ; Clock ; no ; -- ; -- ; ++------------------------------+----------+---------+----------------------+--------+----------------------+------------------+ + + ++------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++---------+----------+---------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; ++---------+----------+---------+----------------------+------------------+ +; EPM_RES ; PIN_89 ; 2 ; On ; -- ; +; TG42_IN ; PIN_87 ; 11 ; On ; -- ; ++---------+----------+---------+----------------------+------------------+ + + ++-----------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-------------------------------+---------+ +; Name ; Fan-Out ; ++-------------------------------+---------+ +; HDD_C[2] ; 21 ; +; HDD_C[1] ; 19 ; +; HDD_C[3] ; 18 ; +; FDD_C[1] ; 17 ; +; HDD_C[0] ; 16 ; +; SINC_HT ; 16 ; +; FDD_C[2] ; 15 ; +; XCT[1] ; 15 ; +; FDD_C[0] ; 14 ; +; /RESET ; 11 ; +; HDD_CLK ; 10 ; +; SINC_VT ; 10 ; +; lpm_counter:CTV_rtl_1|dffs[0] ; 9 ; +; lpm_counter:CT_rtl_0|dffs[3] ; 9 ; +; lpm_counter:CTV_rtl_1|dffs[2] ; 8 ; +; CT_WG1~8bal ; 7 ; +; THDD~2 ; 7 ; +; lpm_counter:CTV_rtl_1|dffs[3] ; 7 ; +; lpm_counter:CTV_rtl_1|dffs[1] ; 7 ; +; $00021 ; 6 ; +; CT_WG ; 6 ; +; FDD_1440 ; 6 ; +; lpm_counter:CTV_rtl_1|dffs[4] ; 6 ; +; WGR[3] ; 5 ; +; WGR[1] ; 5 ; +; WGR[0] ; 5 ; +; WGR[2] ; 5 ; +; NTHDD~11 ; 5 ; +; lpm_counter:CTV_rtl_1|dffs[5] ; 5 ; +; lpm_counter:CTH_rtl_2|dffs[2] ; 5 ; +; lpm_counter:CTH_rtl_2|dffs[0] ; 5 ; +; lpm_counter:CT_rtl_0|dffs[0] ; 5 ; +; STWG[2] ; 4 ; +; RDAT_X~6 ; 4 ; +; lpm_counter:CTV_rtl_1|dffs[6] ; 4 ; +; lpm_counter:CTH_rtl_2|dffs[3] ; 4 ; +; lpm_counter:CTH_rtl_2|dffs[1] ; 4 ; +; STWG[2]~6bal ; 3 ; +; REG_P[1] ; 3 ; +; REG_P[0] ; 3 ; +; LR_T[0] ; 3 ; +; LR_T[1] ; 3 ; +; TURBING~5 ; 3 ; +; CNF_OFF ; 3 ; +; lpm_counter:CTV_rtl_1|dffs[8] ; 3 ; +; lpm_counter:CTV_rtl_1|dffs[7] ; 3 ; +; lpm_counter:CTH_rtl_2|dffs[5] ; 3 ; +; lpm_counter:CTH_rtl_2|dffs[4] ; 3 ; +; NT320~2 ; 3 ; +; TR43 ; 2 ; ++-------------------------------+---------+ + + ++-------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+--------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+--------------------+ +; Output enables ; 1 / 6 ( 17 % ) ; +; PIA buffers ; 119 / 288 ( 41 % ) ; +; PIAs ; 127 / 288 ( 44 % ) ; ++----------------------------+--------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB External Interconnect ; ++-----------------------------------------------+-----------------------------+ +; LAB External Interconnects (Average = 15.88) ; Number of LABs (Total = 8) ; ++-----------------------------------------------+-----------------------------+ +; 0 - 2 ; 1 ; +; 3 - 5 ; 0 ; +; 6 - 8 ; 1 ; +; 9 - 11 ; 0 ; +; 12 - 14 ; 1 ; +; 15 - 17 ; 2 ; +; 18 - 20 ; 0 ; +; 21 - 23 ; 1 ; +; 24 - 26 ; 1 ; +; 27 - 29 ; 1 ; ++-----------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------+ +; LAB Macrocells ; ++----------------------------------------+-----------------------------+ +; Number of Macrocells (Average = 9.25) ; Number of LABs (Total = 8) ; ++----------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 2 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 2 ; +; 16 ; 1 ; ++----------------------------------------+-----------------------------+ + + ++---------------------------------------------------------+ +; Parallel Expander ; ++--------------------------+------------------------------+ +; Parallel Expander Length ; Number of Parallel Expanders ; ++--------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 3 ; ++--------------------------+------------------------------+ + + ++-------------------------------------------------------------------------------+ +; Shareable Expander ; ++-------------------------------------------------+-----------------------------+ +; Number of shareable expanders (Average = 1.38) ; Number of LABs (Total = 4) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 4 ; +; 1 ; 0 ; +; 2 ; 2 ; +; 3 ; 1 ; +; 4 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Logic Cell Interconnection ; ++-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; LAB ; Logic Cell ; Input ; Output ; ++-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; A ; LC15 ; lpm_counter:CTV_rtl_1|dffs[0], SINC_HT ; lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8] ; +; A ; LC6 ; HDD_C[3], HDD_C[1], FDD_C[1], FDD_C[0], HDD_C[2], HDD_C[0], HDD_CLK, FDD_C[2] ; CMOS_DRD ; +; A ; LC12 ; SL, WD, TR43, STWG[2] ; REG_P[0], REG_P[1], REG_P[2] ; +; A ; LC16 ; STWG[2], CT_WG ; STWG[0], STWG[1], STWG[2] ; +; A ; LC10 ; WD, TR43, SR, STWG[2] ; REG_P[0], REG_P[1], REG_P[2] ; +; A ; LC5 ; HDD_C[3], HDD_C[1], FDD_C[1], FDD_C[0], HDD_C[2], HDD_C[0], HDD_CLK, FDD_C[2] ; CMOS_DWR ; +; A ; LC1 ; lpm_counter:CTV_rtl_1|dffs[0], SINC_HT ; lpm_counter:CTV_rtl_1|dffs[0], lpm_counter:CTV_rtl_1|dffs[1], lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8] ; +; A ; LC14 ; FDD_C[0], FDD_C[1], HDD_C[2], HDD_C[0], HDD_C[3], HDD_C[1], HDD_CLK, FDD_C[2] ; /WG_WR ; +; A ; LC9 ; FDD_C[1], FDD_C[0], HDD_C[2], HDD_C[0], HDD_C[3], HDD_C[1], HDD_CLK, FDD_C[2] ; /WG_RD ; +; A ; LC4 ; LR_T[0], LR_T[1], REG_P[0], REG_P[1], CT_WG ; REG_P[0], REG_P[1], REG_P[2] ; +; A ; LC2 ; LR_T[0], REG_P[0], REG_P[1], LR_T[1], CT_WG ; REG_P[0], REG_P[1], REG_P[2] ; +; A ; LC11 ; ; DENS_X ; +; A ; LC8 ; REG_P[1], REG_P[0], LR_T[1], LR_T[0], CT_WG ; WDAT ; +; A ; LC3 ; XACS, /RESET ; CLKZZ, HDD_CLK, FDD_1440 ; +; B ; LC29 ; HDD_C[3], HDD_C[1], FDD_C[1], FDD_C[0], HDD_C[2], HDD_C[0], HDD_CLK, FDD_C[2] ; CMOS_AS ; +; B ; LC17 ; RDAT_X~6, $00023, CT_WG1~8bal ; FDAT, WGR[2], WGR[0], WGR[1], WGR[3], WGR[4] ; +; B ; LC18 ; lpm_counter:CT_rtl_0|dffs[0], XCT[1] ; lpm_counter:CT_rtl_0|dffs[2], lpm_counter:CT_rtl_0|dffs[3] ; +; B ; LC23 ; STWG[0], STWG[2]~6bal ; STWG[2] ; +; B ; LC19 ; STWG[1], STWG[0], STWG[2]~6bal ; CLK_WG, LR_T[1], LR_T[0], STWG[2]~6bal ; +; B ; LC22 ; RDAT_X~6, CT_WG1~8bal ; $00021 ; +; B ; LC32 ; TURBING~5, FDD_1440, STE, RSTB, WSTB ; TURBING~5, CT_WG~5, CT_WG~6 ; +; B ; LC31 ; STWG[2]~6bal ; STWG[1], STWG[2] ; +; B ; LC25 ; FDD_C[0], FDD_C[1], HDD_C[2], HDD_C[0], HDD_C[3], HDD_C[1], HDD_CLK, FDD_C[2] ; WR_PDOS ; +; B ; LC27 ; WGR[2], WGR[3], $00021, WGR[1], WGR[0], CT_WG1~8bal ; WGR[2], WGR[0], WGR[1], WGR[3], WGR[4] ; +; B ; LC21 ; RDAT_X~11, RDAT_X~6, FDD_1440, lpm_counter:CT_rtl_0|dffs[0], RDAT, XCT[1] ; RDAT_X~6, $00023, $00021, RDAT_X~11 ; +; B ; LC20 ; RDAT_X~6, FDD_1440, XCT[1] ; RDAT_X~6 ; +; B ; LC26 ; CT_WG~4, CT_WG~5, CT_WG~6 ; CT_WG~4, CT_WG~6, REG_P[0], REG_P[1], REG_P[2], STWG[2]~6bal ; +; B ; LC28 ; FDD_1440, lpm_counter:CT_rtl_0|dffs[0], XCT[1] ; $00023, $00021, WGR[2], WGR[0], WGR[1], WGR[3], WGR[4] ; +; B ; LC24 ; $00021, WGR[2], WGR[1], WGR[3], WGR[0], CT_WG1~8bal ; WGR[2], WGR[0], WGR[1], WGR[3], WGR[4] ; +; C ; LC44 ; WGR[3], $00021, WGR[2], WGR[1], WGR[0], CT_WG1~8bal ; WGR[2], WGR[0], WGR[1], WGR[3], WGR[4] ; +; C ; LC35 ; lpm_counter:CT_rtl_0|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[1], lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CTH_rtl_2|dffs[5] ; +; C ; LC39 ; lpm_counter:CTH_rtl_2|dffs[0], lpm_counter:CT_rtl_0|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CTH_rtl_2|dffs[5] ; +; C ; LC37 ; SINC_HT, lpm_counter:CTH_rtl_2|dffs[1], lpm_counter:CTH_rtl_2|dffs[0], lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CT_rtl_0|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CTH_rtl_2|dffs[5], SINC_HT ; +; C ; LC42 ; SINC_HT, lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CTH_rtl_2|dffs[1], lpm_counter:CTH_rtl_2|dffs[0], lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CT_rtl_0|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CTH_rtl_2|dffs[5], SINC_HT ; +; C ; LC40 ; SINC_HT, lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CTH_rtl_2|dffs[1], lpm_counter:CTH_rtl_2|dffs[0], lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CT_rtl_0|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CTH_rtl_2|dffs[5], SINC_HT ; +; C ; LC41 ; SINC_HT, lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CTH_rtl_2|dffs[1], lpm_counter:CTH_rtl_2|dffs[0], lpm_counter:CTH_rtl_2|dffs[5], lpm_counter:CT_rtl_0|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[5], SINC_HT, SINC_1 ; +; C ; LC34 ; SINC_VT, lpm_counter:CTV_rtl_1|dffs[1], lpm_counter:CTV_rtl_1|dffs[0], lpm_counter:CTV_rtl_1|dffs[2], SINC_HT ; lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8], SINC_VT ; +; C ; LC47 ; SINC_VT, lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[1], lpm_counter:CTV_rtl_1|dffs[0], lpm_counter:CTV_rtl_1|dffs[3], SINC_HT ; lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8], SINC_VT ; +; C ; LC48 ; SINC_VT, lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[1], lpm_counter:CTV_rtl_1|dffs[0], lpm_counter:CTV_rtl_1|dffs[4], SINC_HT ; lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8], SINC_VT ; +; C ; LC45 ; SINC_VT, lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[1], lpm_counter:CTV_rtl_1|dffs[0], lpm_counter:CTV_rtl_1|dffs[6], SINC_HT ; lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8], SINC_VT ; +; C ; LC36 ; SINC_VT, lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[1], lpm_counter:CTV_rtl_1|dffs[0], lpm_counter:CTV_rtl_1|dffs[7], SINC_HT ; lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8], SINC_VT ; +; C ; LC43 ; SINC_VT, lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[1], lpm_counter:CTV_rtl_1|dffs[0], lpm_counter:CTV_rtl_1|dffs[8], SINC_HT ; lpm_counter:CTV_rtl_1|dffs[8], SINC_VT, SINC_2 ; +; C ; LC38 ; SINC_VT, lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[1], lpm_counter:CTV_rtl_1|dffs[0], lpm_counter:CTV_rtl_1|dffs[5], SINC_HT ; lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8], SINC_VT ; +; C ; LC33 ; WGR[3], WGR[1], WGR[2], WGR[0], $00021, CT_WG1~8bal ; WGR[2], WGR[0], WGR[1], WGR[3], WGR[4] ; +; C ; LC46 ; WGR[1], WGR[2], WGR[0], $00021, WGR[3], CT_WG1~8bal ; QDAT ; +; D ; LC49 ; lpm_counter:CT_rtl_0|dffs[1], lpm_counter:CT_rtl_0|dffs[0], XCT[1] ; lpm_counter:CT_rtl_0|dffs[3] ; +; D ; LC53 ; lpm_counter:CT_rtl_0|dffs[2], lpm_counter:CT_rtl_0|dffs[1], lpm_counter:CT_rtl_0|dffs[0], XCT[1] ; AUD, lpm_counter:CTH_rtl_2|dffs[0], lpm_counter:CTH_rtl_2|dffs[1], lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CTH_rtl_2|dffs[5], SINC_HT, /RESET ; +; D ; LC56 ; XCT[0], XCT[2]~3, XCT[2]~4 ; XCT[2]~3, XCT[2]~4, lpm_counter:CT_rtl_0|dffs[0], lpm_counter:CT_rtl_0|dffs[1], lpm_counter:CT_rtl_0|dffs[2], lpm_counter:CT_rtl_0|dffs[3], CLKZZ, CT_WG~4, CT_WG~5, CT_WG~6, RDAT_X~6, RDAT_X~11, CT_WG1~8bal, XCT[2]~11, XCT[2]~12 ; +; D ; LC51 ; TG42_IN ; TG42_BUF ; +; D ; LC57 ; XCT[0] ; CLK14 ; +; E ; LC77 ; $00049 ; HD_DIR ; +; F ; LC91 ; D0, CNF_OFF, FDD_1440, HDD_CLK, HDD_C[3], HDD_C[1], FDD_C[0], FDD_C[1], HDD_C[2], HDD_C[0], FDD_C[2], FDD_1440~10 ; FDD_1440, 10K_D0, TURBING~5, RDAT_X~6, RDAT_X~11, CT_WG1~8bal ; +; F ; LC88 ; TG42_IN, WR_CNF, CNF_OFF, HDD_C[0], FDD_C[2] ; 10K_CLK, FDD_1440, $00041, $00042, $00043, $00044, $00045, $00046, $00048, $00049 ; +; F ; LC81 ; ; HD_CS ; +; F ; LC85 ; $00047, EPM_RES, lpm_counter:CT_rtl_0|dffs[3], HDD_C[3], HDD_C[1], FDD_C[0], FDD_C[1], HDD_C[2], HDD_C[0], FDD_C[2] ; NT320~2, CNF_OFF, $00052, $00053, NTHDD~11, /CONF_X, FDD_1440~10, $00049~4, $00050, $00051, NT320~12 ; +; G ; LC102 ; SINC_VT, SINC_HT ; SINC ; +; G ; LC99 ; lpm_counter:CTV_rtl_1|dffs[8], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[3], NT320~2, SINC_HT ; lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8], SINC_V, SINC~1, $00047 ; +; G ; LC104 ; lpm_counter:CTH_rtl_2|dffs[5], lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CT_rtl_0|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[2], lpm_counter:CTH_rtl_2|dffs[3], lpm_counter:CTH_rtl_2|dffs[4], lpm_counter:CTH_rtl_2|dffs[5], SINC_H, lpm_counter:CTV_rtl_1|dffs[0], lpm_counter:CTV_rtl_1|dffs[1], lpm_counter:CTV_rtl_1|dffs[2], lpm_counter:CTV_rtl_1|dffs[3], lpm_counter:CTV_rtl_1|dffs[4], lpm_counter:CTV_rtl_1|dffs[5], lpm_counter:CTV_rtl_1|dffs[6], lpm_counter:CTV_rtl_1|dffs[7], lpm_counter:CTV_rtl_1|dffs[8], SINC_VT, SINC~1 ; +; G ; LC109 ; EPM_RES, PW_GOOD, SINC_VT ; XHD_RES, /RESET ; +; H ; LC117 ; NT320~12, FDD_C[0], NT320~2, /RESET, FDD_C[1], HDD_C[2], HDD_C[0], FDD_C[2] ; NT320~2, SINC_VT, NT320~12 ; +; H ; LC124 ; XCT[2]~11, XCT[2]~12 ; XCT[1], $00009 ; +; H ; LC128 ; TG42_IN ; TG42_OUT ; +; H ; LC122 ; XCT[1] ; lpm_counter:CT_rtl_0|dffs[1], lpm_counter:CT_rtl_0|dffs[2], lpm_counter:CT_rtl_0|dffs[3], RDAT_X~6, CT_WG1~8bal ; +; H ; LC114 ; NTHDD~11, FDD_C[0], FDD_C[1], HDD_C[2], HDD_C[0], FDD_C[2], HDD_C[3], HDD_C[1], THDD~2 ; NTHDD~11, THDD~2, $00050, $00051, NTHDD~13, $00052, $00053 ; +; H ; LC119 ; NTHDD~13, NTHDD~11, THDD~2, HDD_C[0], FDD_C[2], HDD_C[1], FDD_C[0], FDD_C[1], HDD_C[2], HDD_C[3], /RESET ; NTHDD~11, THDD~2, NTHDD~13, $00052, $00053 ; +; H ; LC125 ; TG42_IN, HDD_C[3], /RESET, HDD_C[1], HDD_C[2], NTHDD~4sexpand0, NTHDD~11, THDD~2 ; XHD2_CS[2] ; +; H ; LC113 ; FDD_C[1], HDD_C[1], HDD_C[2], HDD_CLK, $00049~4 ; XHD_WR ; +; H ; LC115 ; FDD_C[1], HDD_C[1], HDD_C[2], HDD_CLK, $00049~4 ; XHD_RD, $00049~11 ; +; H ; LC116 ; /RESET, NT320~2, FDD_C[2], HDD_C[3], HDD_C[1], FDD_C[0], FDD_C[1], HDD_C[2], HDD_C[0] ; NT320~2 ; +; H ; LC118 ; NTHDD~11, THDD~2, HDD_C[3], FDD_C[1], HDD_C[2] ; NTHDD~11 ; +; H ; LC120 ; TG42_IN, HDD_C[3], HDD_C[1], HDD_C[2], THDD~2, /RESET ; XHD1_CS[1] ; +; H ; LC126 ; ; BEEP ; +; H ; LC121 ; TG42_IN, HDD_C[3], HDD_C[1], HDD_C[2], THDD~2, /RESET ; XHD1_CS[2] ; +; H ; LC123 ; TG42_IN, HDD_C[3], /RESET, HDD_C[1], HDD_C[2], NTHDD~4sexpand0, NTHDD~11, THDD~2 ; XHD2_CS[1] ; ++-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+----------------+ +; Option ; Setting ; ++----------------------------------------------+----------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Security bit ; On ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+----------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Sun Aug 28 03:30:40 2022 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max +Info: Selected device EPM7128STC100-10 for design "sp2_max" +Warning: Ignored locations or region assignments to the following nodes + Warning: Node "10K_D[0]" is assigned to location or region, but does not exist in design + Warning: Node "CLK[14]" is assigned to location or region, but does not exist in design + Warning: Node "D[0]" is assigned to location or region, but does not exist in design + Warning: Node "FDD_C0" is assigned to location or region, but does not exist in design + Warning: Node "FDD_C1" is assigned to location or region, but does not exist in design + Warning: Node "FDD_C2" is assigned to location or region, but does not exist in design + Warning: Node "HDD_C0" is assigned to location or region, but does not exist in design + Warning: Node "HDD_C1" is assigned to location or region, but does not exist in design + Warning: Node "HDD_C2" is assigned to location or region, but does not exist in design + Warning: Node "HDD_C3" is assigned to location or region, but does not exist in design + Warning: Node "SINC_[1]" is assigned to location or region, but does not exist in design + Warning: Node "SINC_[2]" is assigned to location or region, but does not exist in design + Warning: Node "TR[43]" is assigned to location or region, but does not exist in design + Warning: Node "UNUSED[33]" is assigned to location or region, but does not exist in design + Warning: Node "UNUSED[53]" is assigned to location or region, but does not exist in design + Warning: Node "UNUSED[65]" is assigned to location or region, but does not exist in design + Warning: Node "UNUSED[78]" is assigned to location or region, but does not exist in design + Warning: Node "XA0" is assigned to location or region, but does not exist in design + Warning: Node "XA1" is assigned to location or region, but does not exist in design + Warning: Node "XA2" is assigned to location or region, but does not exist in design + Warning: Node "XHD1_CS1" is assigned to location or region, but does not exist in design + Warning: Node "XHD1_CS2" is assigned to location or region, but does not exist in design + Warning: Node "XHD2_CS1" is assigned to location or region, but does not exist in design + Warning: Node "XHD2_CS2" is assigned to location or region, but does not exist in design +Info: Quartus II Fitter was successful. 0 errors, 25 warnings + Info: Peak virtual memory: 229 megabytes + Info: Processing ended: Sun Aug 28 03:30:41 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/src/altera/quartus/max/sp2_max.fit.summary b/src/altera/quartus/max/sp2_max.fit.summary new file mode 100644 index 0000000..78c0901 --- /dev/null +++ b/src/altera/quartus/max/sp2_max.fit.summary @@ -0,0 +1,9 @@ +Fitter Status : Successful - Sun Aug 28 03:30:40 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : sp2_max +Top-level Entity Name : SP2_MAX +Family : MAX7000S +Device : EPM7128STC100-10 +Timing Models : Final +Total macrocells : 74 / 128 ( 58 % ) +Total pins : 84 / 84 ( 100 % ) diff --git a/src/altera/quartus/max/sp2_max.flow.rpt b/src/altera/quartus/max/sp2_max.flow.rpt new file mode 100644 index 0000000..4c958e1 --- /dev/null +++ b/src/altera/quartus/max/sp2_max.flow.rpt @@ -0,0 +1,117 @@ +Flow report for sp2_max +Sun Aug 28 03:30:43 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------+ +; Flow Summary ; ++-------------------------+----------------------------------------------+ +; Flow Status ; Successful - Sun Aug 28 03:30:43 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; sp2_max ; +; Top-level Entity Name ; SP2_MAX ; +; Family ; MAX7000S ; +; Device ; EPM7128STC100-10 ; +; Timing Models ; Final ; +; Met timing requirements ; No ; +; Total macrocells ; 74 / 128 ( 58 % ) ; +; Total pins ; 84 / 84 ( 100 % ) ; ++-------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 08/28/2022 03:30:38 ; +; Main task ; Compilation ; +; Revision Name ; sp2_max ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++---------------------------------+------------------------------------------------+---------------+-------------+----------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++---------------------------------+------------------------------------------------+---------------+-------------+----------------------+ +; AUTO_GLOBAL_CLOCK ; Off ; On ; -- ; -- ; +; AUTO_GLOBAL_REGISTER_CONTROLS ; Off ; On ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 52243291855.166164663811364 ; -- ; -- ; -- ; +; CUT_OFF_READ_DURING_WRITE_PATHS ; Off ; On ; -- ; -- ; +; EDA_INPUT_GND_NAME ; Gnd ; -- ; -- ; eda_design_synthesis ; +; EDA_INPUT_VCC_NAME ; Vcc ; -- ; -- ; eda_design_synthesis ; +; EDA_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; eda_design_synthesis ; +; EXCLUDE_TPD_PATHS_LESS_THAN ; 0 ns ; -- ; -- ; -- ; +; FMAX_REQUIREMENT ; 100 MHz ; -- ; -- ; -- ; +; MISC_FILE ; C:/Sprinter/src/altera/quartus/max/sp2_max.dpf ; -- ; -- ; -- ; ++---------------------------------+------------------------------------------------+---------------+-------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 229 MB ; 00:00:01 ; +; Fitter ; 00:00:00 ; 1.0 ; 204 MB ; 00:00:00 ; +; Assembler ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; +; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 172 MB ; 00:00:00 ; +; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-72JG930 ; Windows Vista ; 6.2 ; x86_64 ; +; Fitter ; DESKTOP-72JG930 ; Windows Vista ; 6.2 ; x86_64 ; +; Assembler ; DESKTOP-72JG930 ; Windows Vista ; 6.2 ; x86_64 ; +; Classic Timing Analyzer ; DESKTOP-72JG930 ; Windows Vista ; 6.2 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max +quartus_fit --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max +quartus_asm --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max +quartus_tan --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max + + + diff --git a/src/altera/quartus/max/sp2_max.map.rpt b/src/altera/quartus/max/sp2_max.map.rpt new file mode 100644 index 0000000..202918a --- /dev/null +++ b/src/altera/quartus/max/sp2_max.map.rpt @@ -0,0 +1,491 @@ +Analysis & Synthesis report for sp2_max +Sun Aug 28 03:30:39 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. Registers Removed During Synthesis + 8. Source assignments for lpm_counter:CT_rtl_0 + 9. Source assignments for lpm_counter:CTV_rtl_1 + 10. Source assignments for lpm_counter:CTH_rtl_2 + 11. Source assignments for lpm_add_sub:op_6|addcore:adder + 12. Source assignments for lpm_add_sub:op_6|addcore:adder|addcore:adder[0] + 13. Parameter Settings for User Entity Instance: Top-level Entity: |sp2_max + 14. Parameter Settings for Inferred Entity Instance: lpm_counter:CT_rtl_0 + 15. Parameter Settings for Inferred Entity Instance: lpm_counter:CTV_rtl_1 + 16. Parameter Settings for Inferred Entity Instance: lpm_counter:CTH_rtl_2 + 17. Parameter Settings for Inferred Entity Instance: lpm_add_sub:op_6 + 18. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sun Aug 28 03:30:39 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; sp2_max ; +; Top-level Entity Name ; SP2_MAX ; +; Family ; MAX7000S ; +; Total macrocells ; 74 ; +; Total pins ; 80 ; ++-----------------------------+----------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++--------------------------------------------------------------+------------------+---------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------+------------------+---------------+ +; Device ; EPM7128STC100-10 ; ; +; Top-level entity name ; sp2_max ; sp2_max ; +; Family name ; MAX7000S ; Stratix II ; +; Use smart compilation ; Off ; Off ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Auto ; Auto ; +; Ignore SOFT Buffers ; Off ; Off ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Speed ; Speed ; +; Allow XOR Gate Usage ; On ; On ; +; Auto Logic Cell Insertion ; On ; On ; +; Parallel Expander Chain Length ; 4 ; 4 ; +; Auto Parallel Expanders ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Auto Resource Sharing ; Off ; Off ; +; Maximum Fan-in Per Macrocell ; 100 ; 100 ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++--------------------------------------------------------------+------------------+---------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+-----------------------+-------------------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+-----------------------+-------------------------------------------------------------------------+ +; sp2_max.tdf ; yes ; Auto-Found AHDL File ; C:/Sprinter/src/altera/quartus/max/sp2_max.tdf ; +; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.tdf ; +; lpm_constant.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_constant.inc ; +; lpm_decode.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_decode.inc ; +; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.inc ; +; cmpconst.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/cmpconst.inc ; +; lpm_compare.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_compare.inc ; +; lpm_counter.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_counter.inc ; +; dffeea.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/dffeea.inc ; +; alt_synch_counter.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_synch_counter.inc ; +; alt_synch_counter_f.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_synch_counter_f.inc ; +; alt_counter_f10ke.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_counter_f10ke.inc ; +; alt_counter_stratix.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_counter_stratix.inc ; +; aglobal90.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/aglobal90.inc ; +; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf ; +; addcore.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/addcore.inc ; +; look_add.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/look_add.inc ; +; bypassff.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/bypassff.inc ; +; altshift.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altshift.inc ; +; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; +; alt_mercury_add_sub.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ; +; addcore.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/addcore.tdf ; +; a_csnbuffer.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/a_csnbuffer.inc ; +; a_csnbuffer.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/a_csnbuffer.tdf ; +; altshift.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/altshift.tdf ; ++----------------------------------+-----------------+-----------------------+-------------------------------------------------------------------------+ + + ++---------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++----------------------+----------------------+ +; Resource ; Usage ; ++----------------------+----------------------+ +; Logic cells ; 74 ; +; Total registers ; 57 ; +; I/O pins ; 80 ; +; Shareable expanders ; 9 ; +; Parallel expanders ; 3 ; +; Maximum fan-out node ; HDD_C[2] ; +; Maximum fan-out ; 21 ; +; Total fan-out ; 434 ; +; Average fan-out ; 2.66 ; ++----------------------+----------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+------------+------+--------------------------------+--------------+ +; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+------------+------+--------------------------------+--------------+ +; |SP2_MAX ; 74 ; 80 ; |SP2_MAX ; work ; +; |lpm_counter:CTH_rtl_2| ; 6 ; 0 ; |SP2_MAX|lpm_counter:CTH_rtl_2 ; work ; +; |lpm_counter:CTV_rtl_1| ; 9 ; 0 ; |SP2_MAX|lpm_counter:CTV_rtl_1 ; work ; +; |lpm_counter:CT_rtl_0| ; 4 ; 0 ; |SP2_MAX|lpm_counter:CT_rtl_0 ; work ; ++----------------------------+------------+------+--------------------------------+--------------+ + + ++--------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------+----------------------------------------+ +; CTV8M ; Stuck at GND due to stuck port data_in ; +; XCT[2] ; Lost fanout ; +; Total Number of Removed Registers = 2 ; ; ++---------------------------------------+----------------------------------------+ + + ++-----------------------------------------------+ +; Source assignments for lpm_counter:CT_rtl_0 ; ++---------------------------+-------+------+----+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+----+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+----+ + + ++-----------------------------------------------+ +; Source assignments for lpm_counter:CTV_rtl_1 ; ++---------------------------+-------+------+----+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+----+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+----+ + + ++-----------------------------------------------+ +; Source assignments for lpm_counter:CTH_rtl_2 ; ++---------------------------+-------+------+----+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+----+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+----+ + + ++-------------------------------------------------------+ +; Source assignments for lpm_add_sub:op_6|addcore:adder ; ++---------------------------+-------+------+------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+------------+ +; SUPPRESS_DA_RULE_INTERNAL ; A103 ; - ; - ; ++---------------------------+-------+------+------------+ + + ++------------------------------------------------------------------------+ +; Source assignments for lpm_add_sub:op_6|addcore:adder|addcore:adder[0] ; ++---------------------------+-------+------+-----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-----------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; A103 ; - ; - ; ++---------------------------+-------+------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Top-level Entity: |sp2_max ; ++----------------+-----------+--------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-----------+--------------------------------------------+ +; G_MODE ; 1 ; Untyped ; +; NUM ; NO ; Untyped ; +; NUMBER1 ; 00100000X ; Unsigned Binary ; +; NUMBER2 ; 00110111X ; Unsigned Binary ; +; NUMBER3 ; 01001101X ; Unsigned Binary ; +; NUMBER4 ; 01010010X ; Unsigned Binary ; +; NUMBER5 ; 00100000X ; Unsigned Binary ; +; NUMBER6 ; 00100000X ; Unsigned Binary ; +; NUMBER7 ; 00100000X ; Unsigned Binary ; ++----------------+-----------+--------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: lpm_counter:CT_rtl_0 ; ++------------------------+-------------------+--------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------------+--------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 4 ; Untyped ; +; LPM_DIRECTION ; UP ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ; +; DEVICE_FAMILY ; MAX7000S ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; ++------------------------+-------------------+--------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: lpm_counter:CTV_rtl_1 ; ++------------------------+-------------------+---------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------------+---------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 9 ; Untyped ; +; LPM_DIRECTION ; UP ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ; +; DEVICE_FAMILY ; MAX7000S ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; ++------------------------+-------------------+---------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: lpm_counter:CTH_rtl_2 ; ++------------------------+-------------------+---------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------------+---------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 6 ; Untyped ; +; LPM_DIRECTION ; UP ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ; +; DEVICE_FAMILY ; MAX7000S ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; ++------------------------+-------------------+---------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: lpm_add_sub:op_6 ; ++------------------------+-------------+----------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+----------------------------+ +; LPM_WIDTH ; 5 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_DIRECTION ; ADD ; Untyped ; +; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; REGISTERED_AT_END ; 0 ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; +; USE_CS_BUFFERS ; 1 ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; DEVICE_FAMILY ; MAX7000S ; Untyped ; +; USE_WYS ; OFF ; Untyped ; +; STYLE ; FAST ; Untyped ; +; CBXI_PARAMETER ; add_sub_uch ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+----------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Sun Aug 28 03:30:38 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sp2_max -c sp2_max +Warning: Using design file sp2_max.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: SP2_MAX +Info: Elaborating entity "sp2_max" for the top level hierarchy +Warning: Variable or input pin "CTV8C" is defined but never used +Warning: Variable or input pin "XA" is defined but never used +Warning: Variable or input pin "VGA_IN" is defined but never used +Warning: Variable or input pin "SINC_IN" is defined but never used +Warning: Variable or input pin "XHR_RDY" is defined but never used +Warning: Variable or input pin "UNUSED65" is defined but never used +Warning: Variable or input pin "UNUSED33" is defined but never used +Warning: Variable or input pin "UNUSED1" is defined but never used +Warning: Variable or input pin "UNUSED2" is defined but never used +Warning: Variable or input pin "UNUSED5" is defined but never used +Warning: Variable or input pin "UNUSED7" is defined but never used +Warning: Variable or input pin "UNUSED22" is defined but never used +Warning: Variable or input pin "UNUSED24" is defined but never used +Warning: Variable or input pin "UNUSED27" is defined but never used +Warning: Variable or input pin "UNUSED28" is defined but never used +Warning: Variable or input pin "UNUSED49" is defined but never used +Warning: Variable or input pin "UNUSED50" is defined but never used +Warning: Variable or input pin "UNUSED53" is defined but never used +Warning: Variable or input pin "UNUSED55" is defined but never used +Warning: Variable or input pin "UNUSED63" is defined but never used +Warning: Variable or input pin "UNUSED70" is defined but never used +Warning: Variable or input pin "UNUSED72" is defined but never used +Warning: Variable or input pin "UNUSED77" is defined but never used +Warning: Variable or input pin "UNUSED78" is defined but never used +Info: Inferred 3 megafunctions from design logic + Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "CT[0]~0" + Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: "CTV[0]~9" + Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: "CTH[0]~7" +Info: Inferred 1 megafunctions from design logic + Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "op_6" +Info: Elaborated megafunction instantiation "lpm_counter:CT_rtl_0" +Info: Instantiated megafunction "lpm_counter:CT_rtl_0" with the following parameter: + Info: Parameter "LPM_WIDTH" = "4" + Info: Parameter "LPM_DIRECTION" = "UP" + Info: Parameter "LPM_TYPE" = "LPM_COUNTER" +Info: Elaborated megafunction instantiation "lpm_counter:CTV_rtl_1" +Info: Instantiated megafunction "lpm_counter:CTV_rtl_1" with the following parameter: + Info: Parameter "LPM_WIDTH" = "9" + Info: Parameter "LPM_DIRECTION" = "UP" + Info: Parameter "LPM_TYPE" = "LPM_COUNTER" +Info: Elaborated megafunction instantiation "lpm_counter:CTH_rtl_2" +Info: Instantiated megafunction "lpm_counter:CTH_rtl_2" with the following parameter: + Info: Parameter "LPM_WIDTH" = "6" + Info: Parameter "LPM_DIRECTION" = "UP" + Info: Parameter "LPM_TYPE" = "LPM_COUNTER" +Info: Elaborated megafunction instantiation "lpm_add_sub:op_6" +Info: Instantiated megafunction "lpm_add_sub:op_6" with the following parameter: + Info: Parameter "LPM_WIDTH" = "5" + Info: Parameter "LPM_DIRECTION" = "ADD" + Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED" + Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES" +Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:op_6" +Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:op_6" +Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:op_6" +Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|addcore:adder[0]", which is child of megafunction instantiation "lpm_add_sub:op_6" +Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|addcore:adder[0]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:op_6" +Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|addcore:adder|addcore:adder[0]|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:op_6" +Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:op_6" +Info: Elaborated megafunction instantiation "lpm_add_sub:op_6|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:op_6" +Info: Ignored 6 buffer(s) + Info: Ignored 6 SOFT buffer(s) +Info: Registers with preset signals will power-up high +Warning: TRI or OPNDRN buffers permanently enabled + Warning: Node "$00005" + Warning: Node "$00006" +Warning: Output pins are stuck at VCC or GND + Warning (13410): Pin "BEEP" is stuck at GND + Warning (13410): Pin "DENS_X" is stuck at VCC + Warning (13410): Pin "HD_CS" is stuck at GND +Info: Promoted pin-driven signal(s) to global signal + Info: Promoted clock signal driven by pin "TG42_IN" to global clock signal + Info: Promoted clear signal driven by pin "EPM_RES" to global clear signal +Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below. + Info: Register "XCT[2]" lost all its fanouts during netlist optimizations. +Warning: Design contains 25 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "XA[0]" + Warning (15610): No output dependent on input pin "XA[1]" + Warning (15610): No output dependent on input pin "XA[2]" + Warning (15610): No output dependent on input pin "VGA_IN" + Warning (15610): No output dependent on input pin "SINC_IN" + Warning (15610): No output dependent on input pin "XHR_RDY" + Warning (15610): No output dependent on input pin "UNUSED65" + Warning (15610): No output dependent on input pin "UNUSED33" + Warning (15610): No output dependent on input pin "UNUSED1" + Warning (15610): No output dependent on input pin "UNUSED2" + Warning (15610): No output dependent on input pin "UNUSED5" + Warning (15610): No output dependent on input pin "UNUSED7" + Warning (15610): No output dependent on input pin "UNUSED22" + Warning (15610): No output dependent on input pin "UNUSED24" + Warning (15610): No output dependent on input pin "UNUSED27" + Warning (15610): No output dependent on input pin "UNUSED28" + Warning (15610): No output dependent on input pin "UNUSED49" + Warning (15610): No output dependent on input pin "UNUSED50" + Warning (15610): No output dependent on input pin "UNUSED53" + Warning (15610): No output dependent on input pin "UNUSED55" + Warning (15610): No output dependent on input pin "UNUSED63" + Warning (15610): No output dependent on input pin "UNUSED70" + Warning (15610): No output dependent on input pin "UNUSED72" + Warning (15610): No output dependent on input pin "UNUSED77" + Warning (15610): No output dependent on input pin "UNUSED78" +Info: Implemented 163 device resources after synthesis - the final resource count might be different + Info: Implemented 46 input pins + Info: Implemented 30 output pins + Info: Implemented 4 bidirectional pins + Info: Implemented 74 macrocells + Info: Implemented 9 shareable expanders +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 58 warnings + Info: Peak virtual memory: 229 megabytes + Info: Processing ended: Sun Aug 28 03:30:39 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/src/altera/quartus/max/sp2_max.map.summary b/src/altera/quartus/max/sp2_max.map.summary new file mode 100644 index 0000000..9e9026e --- /dev/null +++ b/src/altera/quartus/max/sp2_max.map.summary @@ -0,0 +1,7 @@ +Analysis & Synthesis Status : Successful - Sun Aug 28 03:30:39 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : sp2_max +Top-level Entity Name : SP2_MAX +Family : MAX7000S +Total macrocells : 74 +Total pins : 80 diff --git a/src/altera/quartus/max/sp2_max.pin b/src/altera/quartus/max/sp2_max.pin new file mode 100644 index 0000000..2d05aee --- /dev/null +++ b/src/altera/quartus/max/sp2_max.pin @@ -0,0 +1,167 @@ + -- Copyright (C) 1991-2009 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCC : Dedicated power pin, which MUST be connected to VCC. + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), + -- connect each pin marked GND* either individually through a 10k Ohm resistor + -- to GND or tie all pins together and connect through a single 10k Ohm resistor + -- to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + -- NON_MIGRATABLE: This pin cannot be migrated. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +CHIP "sp2_max" ASSIGNED TO AN: EPM7128STC100-10 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +UNUSED55 : 1 : input : TTL : : : N +UNUSED72 : 2 : input : TTL : : : N +VCCIO : 3 : power : : 5.0V : : +TDI : 4 : input : TTL : : : N +UNUSED70 : 5 : input : TTL : : : N +CMOS_AS : 6 : output : TTL : : : Y +UNUSED27 : 7 : input : TTL : : : N +WR_PDOS : 8 : output : TTL : : : Y +WD : 9 : input : TTL : : : Y +WSTB : 10 : input : TTL : : : Y +GND : 11 : gnd : : : : +TR43 : 12 : input : TTL : : : Y +CLK_WG : 13 : output : TTL : : : Y +FDAT : 14 : output : TTL : : : Y +TMS : 15 : input : TTL : : : N +QDAT : 16 : output : TTL : : : Y +XA[0] : 17 : input : TTL : : : Y +VCCIO : 18 : power : : 5.0V : : +SINC_2 : 19 : bidir : TTL : : : Y +SINC_1 : 20 : bidir : TTL : : : Y +XA[1] : 21 : input : TTL : : : Y +UNUSED22 : 22 : input : TTL : : : N +XA[2] : 23 : input : TTL : : : Y +UNUSED50 : 24 : input : TTL : : : N +RSTB : 25 : input : TTL : : : Y +GND : 26 : gnd : : : : +UNUSED2 : 27 : input : TTL : : : N +UNUSED28 : 28 : input : TTL : : : N +SR : 29 : input : TTL : : : Y +SL : 30 : input : TTL : : : Y +CLK14 : 31 : output : TTL : : : Y +CLKZZ : 32 : bidir : TTL : : : Y +UNUSED33 : 33 : input : TTL : : : Y +VCCIO : 34 : power : : 5.0V : : +AUD : 35 : output : TTL : : : Y +TG42_BUF : 36 : output : TTL : : : Y +XACS : 37 : input : TTL : : : Y +GND : 38 : gnd : : : : +VCCINT : 39 : power : : 5.0V : : +HDD_C[3] : 40 : input : TTL : : : Y +HDD_C[2] : 41 : input : TTL : : : Y +HDD_C[1] : 42 : input : TTL : : : Y +GND : 43 : gnd : : : : +FDD_C[0] : 44 : input : TTL : : : Y +FDD_C[1] : 45 : input : TTL : : : Y +FDD_C[2] : 46 : input : TTL : : : Y +HDD_C[0] : 47 : input : TTL : : : Y +HD_DIR : 48 : output : TTL : : : Y +UNUSED49 : 49 : input : TTL : : : N +UNUSED1 : 50 : input : TTL : : : N +VCCIO : 51 : power : : 5.0V : : +HD_CS : 52 : output : TTL : : : Y +UNUSED53 : 53 : input : TTL : : : Y +/CONF_X : 54 : bidir : TTL : : : Y +UNUSED63 : 55 : input : TTL : : : N +10K_CLK : 56 : output : TTL : : : Y +WR_CNF : 57 : input : TTL : : : Y +10K_D0 : 58 : output : TTL : : : Y +GND : 59 : gnd : : : : +D0 : 60 : input : TTL : : : Y +VGA_IN : 61 : input : TTL : : : Y +TCK : 62 : input : TTL : : : N +UNUSED77 : 63 : input : TTL : : : N +SINC_V : 64 : output : TTL : : : Y +UNUSED65 : 65 : input : TTL : : : Y +VCCIO : 66 : power : : 5.0V : : +SINC : 67 : output : TTL : : : Y +SINC_H : 68 : output : TTL : : : Y +SINC_IN : 69 : input : TTL : : : Y +UNUSED24 : 70 : input : TTL : : : N +XHD_RES : 71 : output : TTL : : : Y +UNUSED5 : 72 : input : TTL : : : N +TDO : 73 : output : TTL : : : N +GND : 74 : gnd : : : : +XHD_WR : 75 : output : TTL : : : Y +XHD_RD : 76 : output : TTL : : : Y +UNUSED7 : 77 : input : TTL : : : N +UNUSED78 : 78 : input : TTL : : : Y +XHD1_CS[1] : 79 : output : TTL : : : Y +XHD1_CS[2] : 80 : output : TTL : : : Y +XHD2_CS[1] : 81 : output : TTL : : : Y +VCCIO : 82 : power : : 5.0V : : +XHD2_CS[2] : 83 : output : TTL : : : Y +BEEP : 84 : output : TTL : : : Y +TG42_OUT : 85 : output : TTL : : : Y +GND : 86 : gnd : : : : +TG42_IN : 87 : input : TTL : : : Y +XHR_RDY : 88 : input : TTL : : : Y +EPM_RES : 89 : input : TTL : : : Y +PW_GOOD : 90 : input : TTL : : : Y +VCCINT : 91 : power : : 5.0V : : +RDAT : 92 : input : TTL : : : Y +/WG_WR : 93 : output : TTL : : : Y +STE : 94 : input : TTL : : : Y +GND : 95 : gnd : : : : +DENS_X : 96 : output : TTL : : : Y +/WG_RD : 97 : output : TTL : : : Y +WDAT : 98 : output : TTL : : : Y +CMOS_DRD : 99 : output : TTL : : : Y +CMOS_DWR : 100 : output : TTL : : : Y diff --git a/src/altera/quartus/max/sp2_max.pof b/src/altera/quartus/max/sp2_max.pof new file mode 100644 index 0000000..8740f1b Binary files /dev/null and b/src/altera/quartus/max/sp2_max.pof differ diff --git a/src/altera/quartus/max/sp2_max.qpf b/src/altera/quartus/max/sp2_max.qpf new file mode 100644 index 0000000..35df9f6 --- /dev/null +++ b/src/altera/quartus/max/sp2_max.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 03:22:36 August 28, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "03:22:36 August 28, 2022" + +# Revisions + +PROJECT_REVISION = "sp2_max" diff --git a/src/altera/quartus/max/sp2_max.qsf b/src/altera/quartus/max/sp2_max.qsf new file mode 100644 index 0000000..ae8b38b --- /dev/null +++ b/src/altera/quartus/max/sp2_max.qsf @@ -0,0 +1,226 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 03:22:36 August 28, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# sp2_max_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY MAX7000S +set_global_assignment -name DEVICE "EPM7128STC100-10" +set_global_assignment -name TOP_LEVEL_ENTITY sp2_max +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "03:22:36 AUGUST 28, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" +set_location_assignment PIN_6 -to CMOS_AS +set_location_assignment PIN_8 -to WR_PDOS +set_location_assignment PIN_9 -to WD +set_location_assignment PIN_10 -to WSTB +set_location_assignment PIN_12 -to TR43 +set_location_assignment PIN_12 -to TR[43] +set_location_assignment PIN_13 -to CLK_WG +set_location_assignment PIN_14 -to FDAT +set_location_assignment PIN_16 -to QDAT +set_location_assignment PIN_17 -to XA0 +set_location_assignment PIN_17 -to XA[0] +set_location_assignment PIN_19 -to SINC_2 +set_location_assignment PIN_19 -to SINC_[2] +set_location_assignment PIN_20 -to SINC_1 +set_location_assignment PIN_20 -to SINC_[1] +set_location_assignment PIN_21 -to XA1 +set_location_assignment PIN_21 -to XA[1] +set_location_assignment PIN_23 -to XA2 +set_location_assignment PIN_23 -to XA[2] +set_location_assignment PIN_25 -to RSTB +set_location_assignment PIN_29 -to SR +set_location_assignment PIN_30 -to SL +set_location_assignment PIN_31 -to CLK14 +set_location_assignment PIN_31 -to CLK[14] +set_location_assignment PIN_32 -to CLKZZ +set_location_assignment PIN_33 -to UNUSED33 +set_location_assignment PIN_33 -to UNUSED[33] +set_location_assignment PIN_35 -to AUD +set_location_assignment PIN_36 -to TG42_BUF +set_location_assignment PIN_37 -to XACS +set_location_assignment PIN_40 -to HDD_C3 +set_location_assignment PIN_40 -to HDD_C[3] +set_location_assignment PIN_41 -to HDD_C2 +set_location_assignment PIN_41 -to HDD_C[2] +set_location_assignment PIN_42 -to HDD_C1 +set_location_assignment PIN_42 -to HDD_C[1] +set_location_assignment PIN_44 -to FDD_C0 +set_location_assignment PIN_44 -to FDD_C[0] +set_location_assignment PIN_45 -to FDD_C1 +set_location_assignment PIN_45 -to FDD_C[1] +set_location_assignment PIN_46 -to FDD_C2 +set_location_assignment PIN_46 -to FDD_C[2] +set_location_assignment PIN_47 -to HDD_C0 +set_location_assignment PIN_47 -to HDD_C[0] +set_location_assignment PIN_48 -to HD_DIR +set_location_assignment PIN_52 -to HD_CS +set_location_assignment PIN_53 -to UNUSED53 +set_location_assignment PIN_53 -to UNUSED[53] +set_location_assignment PIN_54 -to /CONF_X +set_location_assignment PIN_56 -to 10K_CLK +set_location_assignment PIN_57 -to WR_CNF +set_location_assignment PIN_58 -to 10K_D0 +set_location_assignment PIN_58 -to 10K_D[0] +set_location_assignment PIN_60 -to D0 +set_location_assignment PIN_60 -to D[0] +set_location_assignment PIN_61 -to VGA_IN +set_location_assignment PIN_64 -to SINC_V +set_location_assignment PIN_65 -to UNUSED65 +set_location_assignment PIN_65 -to UNUSED[65] +set_location_assignment PIN_67 -to SINC +set_location_assignment PIN_68 -to SINC_H +set_location_assignment PIN_69 -to SINC_IN +set_location_assignment PIN_71 -to XHD_RES +set_location_assignment PIN_75 -to XHD_WR +set_location_assignment PIN_76 -to XHD_RD +set_location_assignment PIN_78 -to UNUSED78 +set_location_assignment PIN_78 -to UNUSED[78] +set_location_assignment PIN_79 -to XHD1_CS1 +set_location_assignment PIN_79 -to XHD1_CS[1] +set_location_assignment PIN_80 -to XHD1_CS2 +set_location_assignment PIN_80 -to XHD1_CS[2] +set_location_assignment PIN_81 -to XHD2_CS1 +set_location_assignment PIN_81 -to XHD2_CS[1] +set_location_assignment PIN_83 -to XHD2_CS2 +set_location_assignment PIN_83 -to XHD2_CS[2] +set_location_assignment PIN_84 -to BEEP +set_location_assignment PIN_85 -to TG42_OUT +set_location_assignment PIN_87 -to TG42_IN +set_location_assignment PIN_88 -to XHR_RDY +set_location_assignment PIN_89 -to EPM_RES +set_location_assignment PIN_90 -to PW_GOOD +set_location_assignment PIN_92 -to RDAT +set_location_assignment PIN_93 -to /WG_WR +set_location_assignment PIN_94 -to STE +set_location_assignment PIN_96 -to DENS_X +set_location_assignment PIN_97 -to /WG_RD +set_location_assignment PIN_98 -to WDAT +set_location_assignment PIN_99 -to CMOS_DRD +set_location_assignment PIN_100 -to CMOS_DWR +set_global_assignment -name FMAX_REQUIREMENT "100 MHz" +set_global_assignment -name CUT_OFF_CLEAR_AND_PRESET_PATHS ON +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK ON +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to LR_T1 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to LR_T[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to LR_T0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to LR_T[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to CLK_WG +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD_RD +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD_RES +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD_WR +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD1_CS1 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD1_CS[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD1_CS2 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD1_CS[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD2_CS1 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD2_CS[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD2_CS2 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to XHD2_CS[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to 10K_CLK +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to 10K_D0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT OFF -to 10K_D[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to REG_P0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to REG_P[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to REG_P1 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to REG_P[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to REG_P2 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to REG_P[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to TG42_BUF +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to TG42_OUT +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to STWG0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to STWG[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to STWG1 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to STWG[1] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to STWG2 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to STWG[2] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to XCT0 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to XCT[0] +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to XCT1 +set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to XCT[1] +set_global_assignment -name SECURITY_BIT ON +set_global_assignment -name ENABLE_VREFB_PIN OFF +set_global_assignment -name ENABLE_VREFA_PIN OFF +set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V +set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE OFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE OFF +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE ON +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT OFF +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT ON +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT OFF +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFF +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF +set_global_assignment -name ENABLE_DEVICE_WIDE_OE OFF +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET OFF +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES OFF +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name USER_START_UP_CLOCK OFF +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS OFF +set_global_assignment -name AUTO_GLOBAL_CLOCK OFF +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM OFF +set_global_assignment -name AUTO_OPEN_DRAIN_PINS ON +set_global_assignment -name STATE_MACHINE_PROCESSING AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS OFF +set_global_assignment -name AUTO_FAST_INPUT_REGISTERS OFF +set_global_assignment -name AUTO_FAST_OUTPUT_REGISTERS OFF +set_global_assignment -name AUTO_GLOBAL_OE ON +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE AREA +set_global_assignment -name SAVE_DISK_SPACE ON +set_global_assignment -name SMART_RECOMPILE OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES OFF -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis +set_global_assignment -name END_TIME "25 us" +set_global_assignment -name START_TIME "0 ns" +set_global_assignment -name GLITCH_INTERVAL "0 ns" +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF +set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10 +set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN "0 ns" +set_global_assignment -name MISC_FILE "C:/Sprinter/src/altera/quartus/max/sp2_max.dpf" \ No newline at end of file diff --git a/src/altera/quartus/max/sp2_max.qws b/src/altera/quartus/max/sp2_max.qws new file mode 100644 index 0000000..51464d5 --- /dev/null +++ b/src/altera/quartus/max/sp2_max.qws @@ -0,0 +1,18 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=sp2_max.tdf +DocumentCLSID={5d384c4f-893c-11d1-a087-0020affa43f2} +IsChildFrameDetached=False +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap] +AFC_IN_REPORT=False diff --git a/src/altera/quartus/max/sp2_max.tan.rpt b/src/altera/quartus/max/sp2_max.tan.rpt new file mode 100644 index 0000000..bb4e02c --- /dev/null +++ b/src/altera/quartus/max/sp2_max.tan.rpt @@ -0,0 +1,1328 @@ +Classic Timing Analyzer report for sp2_max +Sun Aug 28 03:30:43 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Parallel Compilation + 6. Clock Setup: 'TG42_IN' + 7. Clock Setup: 'STE' + 8. Clock Setup: 'RSTB' + 9. Clock Setup: 'WSTB' + 10. Clock Hold: 'TG42_IN' + 11. Clock Hold: 'STE' + 12. Clock Hold: 'RSTB' + 13. Clock Hold: 'WSTB' + 14. tsu + 15. tco + 16. tpd + 17. th + 18. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++------------------------------+------------+-----------------------------------+----------------------------------+----------+----------+------------+----------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++------------------------------+------------+-----------------------------------+----------------------------------+----------+----------+------------+----------+--------------+ +; Worst-case tsu ; N/A ; None ; 23.800 ns ; HDD_C[3] ; $00051 ; -- ; TG42_IN ; 0 ; +; Worst-case tco ; N/A ; None ; 50.000 ns ; STWG[2] ; CLK_WG ; TG42_IN ; -- ; 0 ; +; Worst-case tpd ; N/A ; None ; 10.000 ns ; TG42_IN ; TG42_BUF ; -- ; -- ; 0 ; +; Worst-case th ; N/A ; None ; 51.000 ns ; SL ; LR_T[1] ; -- ; TG42_IN ; 0 ; +; Clock Setup: 'TG42_IN' ; -47.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; 9.62 MHz ( period = 104.000 ns ) ; /RESET ; $00051 ; TG42_IN ; TG42_IN ; 57 ; +; Clock Setup: 'STE' ; -21.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[2] ; STE ; STE ; 6 ; +; Clock Setup: 'RSTB' ; -21.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[2] ; RSTB ; RSTB ; 6 ; +; Clock Setup: 'WSTB' ; -21.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[2] ; WSTB ; WSTB ; 6 ; +; Clock Hold: 'TG42_IN' ; -12.200 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A ; FDD_1440 ; $00021 ; TG42_IN ; TG42_IN ; 48 ; +; Clock Hold: 'STE' ; 5.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A ; REG_P[1] ; REG_P[2] ; STE ; STE ; 0 ; +; Clock Hold: 'RSTB' ; 5.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A ; REG_P[1] ; REG_P[2] ; RSTB ; RSTB ; 0 ; +; Clock Hold: 'WSTB' ; 5.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A ; REG_P[1] ; REG_P[2] ; WSTB ; WSTB ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 123 ; ++------------------------------+------------+-----------------------------------+----------------------------------+----------+----------+------------+----------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Device Name ; EPM7128STC100-10 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; Off ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; fmax Requirement ; 100 MHz ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Minimum tpd to report ; 0 ns ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; Off ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; TG42_IN ; ; User Pin ; 100.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; +; STE ; ; User Pin ; 100.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; +; RSTB ; ; User Pin ; 100.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; +; WSTB ; ; User Pin ; 100.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'TG42_IN' ; ++------------+---------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++------------+---------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; -47.000 ns ; 9.62 MHz ( period = 104.000 ns ) ; /RESET ; $00051 ; TG42_IN ; TG42_IN ; 5.000 ns ; -25.000 ns ; 22.000 ns ; +; -47.000 ns ; 9.62 MHz ( period = 104.000 ns ) ; /RESET ; $00050 ; TG42_IN ; TG42_IN ; 5.000 ns ; -25.000 ns ; 22.000 ns ; +; -47.000 ns ; 9.62 MHz ( period = 104.000 ns ) ; /RESET ; $00053 ; TG42_IN ; TG42_IN ; 5.000 ns ; -25.000 ns ; 22.000 ns ; +; -47.000 ns ; 9.62 MHz ( period = 104.000 ns ) ; /RESET ; $00052 ; TG42_IN ; TG42_IN ; 5.000 ns ; -25.000 ns ; 22.000 ns ; +; -27.000 ns ; 15.63 MHz ( period = 64.000 ns ) ; LR_T[0] ; REG_P[2] ; TG42_IN ; TG42_IN ; 5.000 ns ; -21.000 ns ; 6.000 ns ; +; -27.000 ns ; 15.63 MHz ( period = 64.000 ns ) ; LR_T[1] ; REG_P[2] ; TG42_IN ; TG42_IN ; 5.000 ns ; -21.000 ns ; 6.000 ns ; +; -27.000 ns ; 15.63 MHz ( period = 64.000 ns ) ; LR_T[0] ; REG_P[1] ; TG42_IN ; TG42_IN ; 5.000 ns ; -21.000 ns ; 6.000 ns ; +; -27.000 ns ; 15.63 MHz ( period = 64.000 ns ) ; LR_T[1] ; REG_P[1] ; TG42_IN ; TG42_IN ; 5.000 ns ; -21.000 ns ; 6.000 ns ; +; -27.000 ns ; 15.63 MHz ( period = 64.000 ns ) ; LR_T[0] ; REG_P[0] ; TG42_IN ; TG42_IN ; 5.000 ns ; -21.000 ns ; 6.000 ns ; +; -27.000 ns ; 15.63 MHz ( period = 64.000 ns ) ; LR_T[1] ; REG_P[0] ; TG42_IN ; TG42_IN ; 5.000 ns ; -21.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; $00047 ; /RESET ; TG42_IN ; TG42_IN ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -13.000 ns ; 43.48 MHz ( period = 23.000 ns ) ; $00009 ; $00009 ; TG42_IN ; TG42_IN ; 10.000 ns ; -7.000 ns ; 6.000 ns ; +; -13.000 ns ; 43.48 MHz ( period = 23.000 ns ) ; XCT[0] ; XCT[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; -7.000 ns ; 6.000 ns ; +; -13.000 ns ; 43.48 MHz ( period = 23.000 ns ) ; XCT[0] ; XCT[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; -7.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[4] ; WGR[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[0] ; WGR[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[1] ; WGR[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[3] ; WGR[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[2] ; WGR[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; $00021 ; WGR[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[0] ; WGR[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[1] ; WGR[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[3] ; WGR[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[2] ; WGR[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; $00021 ; WGR[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[0] ; WGR[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[1] ; WGR[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[3] ; WGR[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[2] ; WGR[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; $00021 ; WGR[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[0] ; WGR[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[1] ; WGR[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[3] ; WGR[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[2] ; WGR[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; $00021 ; WGR[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[0] ; WGR[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[1] ; WGR[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[3] ; WGR[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; WGR[2] ; WGR[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; $00021 ; WGR[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -10.000 ns ; 50.00 MHz ( period = 20.000 ns ) ; $00023 ; $00021 ; TG42_IN ; TG42_IN ; 10.000 ns ; -4.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; REG_P[1] ; REG_P[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; REG_P[0] ; REG_P[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; REG_P[1] ; REG_P[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; REG_P[0] ; REG_P[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; REG_P[1] ; REG_P[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; REG_P[0] ; REG_P[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; STWG[1] ; STWG[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; STWG[0] ; STWG[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; STWG[1] ; STWG[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; STWG[2] ; STWG[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; STWG[0] ; STWG[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; STWG[0] ; STWG[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -6.000 ns ; 62.50 MHz ( period = 16.000 ns ) ; CT_WG ; CT_WG ; TG42_IN ; TG42_IN ; 10.000 ns ; 0.000 ns ; 6.000 ns ; +; -5.800 ns ; 46.30 MHz ( period = 21.600 ns ) ; /RESET ; SINC_VT ; TG42_IN ; TG42_IN ; 5.000 ns ; 9.000 ns ; 14.800 ns ; +; -2.000 ns ; 83.33 MHz ( period = 12.000 ns ) ; lpm_counter:CT_rtl_0|dffs[0] ; $00021 ; TG42_IN ; TG42_IN ; 10.000 ns ; 12.000 ns ; 14.000 ns ; +; -2.000 ns ; 83.33 MHz ( period = 12.000 ns ) ; lpm_counter:CT_rtl_0|dffs[0] ; $00023 ; TG42_IN ; TG42_IN ; 10.000 ns ; 12.000 ns ; 14.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; FDD_1440 ; FDD_1440 ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[2] ; lpm_counter:CT_rtl_0|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[1] ; lpm_counter:CT_rtl_0|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[0] ; lpm_counter:CT_rtl_0|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[2] ; lpm_counter:CT_rtl_0|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[3] ; lpm_counter:CT_rtl_0|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[1] ; lpm_counter:CT_rtl_0|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[0] ; lpm_counter:CT_rtl_0|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[2] ; lpm_counter:CTH_rtl_2|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_HT ; lpm_counter:CTH_rtl_2|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[2] ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_HT ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[2] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[4] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_HT ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[2] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[4] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[5] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_HT ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[2] ; SINC_HT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[3] ; SINC_HT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[4] ; SINC_HT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTH_rtl_2|dffs[5] ; SINC_HT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[2] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[5] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[5] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[6] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[5] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[6] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[7] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[5] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[6] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[7] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[8] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[2] ; SINC_VT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[3] ; SINC_VT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[4] ; SINC_VT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[5] ; SINC_VT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[6] ; SINC_VT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[7] ; SINC_VT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CTV_rtl_1|dffs[8] ; SINC_VT ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[1] ; lpm_counter:CT_rtl_0|dffs[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[0] ; lpm_counter:CT_rtl_0|dffs[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:CT_rtl_0|dffs[0] ; lpm_counter:CT_rtl_0|dffs[0] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; XCT[1] ; XCT[1] ; TG42_IN ; TG42_IN ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 5.200 ns ; Restricted to 125.0 MHz ( period = 8.0 ns ) ; XCT[1] ; $00021 ; TG42_IN ; TG42_IN ; 10.000 ns ; 20.000 ns ; 14.800 ns ; +; 5.200 ns ; Restricted to 125.0 MHz ( period = 8.0 ns ) ; XCT[1] ; $00023 ; TG42_IN ; TG42_IN ; 10.000 ns ; 20.000 ns ; 14.800 ns ; +; 7.200 ns ; Restricted to 125.0 MHz ( period = 8.0 ns ) ; FDD_1440 ; $00021 ; TG42_IN ; TG42_IN ; 10.000 ns ; 22.000 ns ; 14.800 ns ; +; 7.200 ns ; Restricted to 125.0 MHz ( period = 8.0 ns ) ; FDD_1440 ; $00023 ; TG42_IN ; TG42_IN ; 10.000 ns ; 22.000 ns ; 14.800 ns ; ++------------+---------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'STE' ; ++------------+-----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++------------+-----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[2] ; STE ; STE ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[1] ; REG_P[2] ; STE ; STE ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[1] ; STE ; STE ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[1] ; REG_P[1] ; STE ; STE ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[0] ; STE ; STE ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[1] ; REG_P[0] ; STE ; STE ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[1] ; REG_P[2] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[0] ; REG_P[2] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[1] ; REG_P[1] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[0] ; REG_P[1] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[1] ; REG_P[0] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[0] ; REG_P[0] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[1] ; STWG[1] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[0] ; STWG[1] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[1] ; STWG[2] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[2] ; STWG[2] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[0] ; STWG[2] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[0] ; STWG[0] ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; CT_WG ; CT_WG ; STE ; STE ; 10.000 ns ; 6.000 ns ; 6.000 ns ; ++------------+-----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'RSTB' ; ++------------+-----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++------------+-----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[2] ; RSTB ; RSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[1] ; REG_P[2] ; RSTB ; RSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[1] ; RSTB ; RSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[1] ; REG_P[1] ; RSTB ; RSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[0] ; RSTB ; RSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[1] ; REG_P[0] ; RSTB ; RSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[1] ; REG_P[2] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[0] ; REG_P[2] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[1] ; REG_P[1] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[0] ; REG_P[1] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[1] ; REG_P[0] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[0] ; REG_P[0] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[1] ; STWG[1] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[0] ; STWG[1] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[1] ; STWG[2] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[2] ; STWG[2] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[0] ; STWG[2] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[0] ; STWG[0] ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; CT_WG ; CT_WG ; RSTB ; RSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; ++------------+-----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'WSTB' ; ++------------+-----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++------------+-----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[2] ; WSTB ; WSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[1] ; REG_P[2] ; WSTB ; WSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[1] ; WSTB ; WSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[1] ; REG_P[1] ; WSTB ; WSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[0] ; REG_P[0] ; WSTB ; WSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; -21.000 ns ; 19.23 MHz ( period = 52.000 ns ) ; LR_T[1] ; REG_P[0] ; WSTB ; WSTB ; 5.000 ns ; -15.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[1] ; REG_P[2] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[0] ; REG_P[2] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[1] ; REG_P[1] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[0] ; REG_P[1] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[1] ; REG_P[0] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; REG_P[0] ; REG_P[0] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[1] ; STWG[1] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[0] ; STWG[1] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[1] ; STWG[2] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[2] ; STWG[2] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[0] ; STWG[2] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; STWG[0] ; STWG[0] ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; +; 0.000 ns ; 100.00 MHz ( period = 10.000 ns ) ; CT_WG ; CT_WG ; WSTB ; WSTB ; 10.000 ns ; 6.000 ns ; 6.000 ns ; ++------------+-----------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'TG42_IN' ; ++---------------+-------------------------------+-------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+-------------------------------+-------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; -12.200 ns ; FDD_1440 ; $00021 ; TG42_IN ; TG42_IN ; 0.000 ns ; 27.000 ns ; 14.800 ns ; +; -12.200 ns ; FDD_1440 ; $00023 ; TG42_IN ; TG42_IN ; 0.000 ns ; 27.000 ns ; 14.800 ns ; +; -10.200 ns ; XCT[1] ; $00021 ; TG42_IN ; TG42_IN ; 0.000 ns ; 25.000 ns ; 14.800 ns ; +; -10.200 ns ; XCT[1] ; $00023 ; TG42_IN ; TG42_IN ; 0.000 ns ; 25.000 ns ; 14.800 ns ; +; -8.000 ns ; $00009 ; $00009 ; TG42_IN ; TG42_IN ; 0.000 ns ; 14.000 ns ; 6.000 ns ; +; -8.000 ns ; XCT[0] ; XCT[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 14.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[4] ; WGR[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[0] ; WGR[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[1] ; WGR[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[3] ; WGR[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[2] ; WGR[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; $00021 ; WGR[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[0] ; WGR[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[1] ; WGR[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[3] ; WGR[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[2] ; WGR[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; $00021 ; WGR[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[0] ; WGR[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[1] ; WGR[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[3] ; WGR[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[2] ; WGR[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; $00021 ; WGR[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[0] ; WGR[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[1] ; WGR[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[3] ; WGR[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[2] ; WGR[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; $00021 ; WGR[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[0] ; WGR[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[1] ; WGR[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[3] ; WGR[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; WGR[2] ; WGR[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; $00021 ; WGR[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -5.000 ns ; $00023 ; $00021 ; TG42_IN ; TG42_IN ; 0.000 ns ; 11.000 ns ; 6.000 ns ; +; -3.000 ns ; lpm_counter:CT_rtl_0|dffs[0] ; $00021 ; TG42_IN ; TG42_IN ; 0.000 ns ; 17.000 ns ; 14.000 ns ; +; -3.000 ns ; lpm_counter:CT_rtl_0|dffs[0] ; $00023 ; TG42_IN ; TG42_IN ; 0.000 ns ; 17.000 ns ; 14.000 ns ; +; -1.000 ns ; REG_P[1] ; REG_P[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; REG_P[0] ; REG_P[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; REG_P[1] ; REG_P[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; REG_P[0] ; REG_P[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; REG_P[1] ; REG_P[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; REG_P[0] ; REG_P[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; STWG[1] ; STWG[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; STWG[0] ; STWG[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; STWG[1] ; STWG[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; STWG[2] ; STWG[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; STWG[0] ; STWG[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; STWG[0] ; STWG[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; -1.000 ns ; CT_WG ; CT_WG ; TG42_IN ; TG42_IN ; 0.000 ns ; 7.000 ns ; 6.000 ns ; +; 5.000 ns ; FDD_1440 ; FDD_1440 ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[2] ; lpm_counter:CT_rtl_0|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[1] ; lpm_counter:CT_rtl_0|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[0] ; lpm_counter:CT_rtl_0|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[2] ; lpm_counter:CT_rtl_0|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[3] ; lpm_counter:CT_rtl_0|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[1] ; lpm_counter:CT_rtl_0|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[0] ; lpm_counter:CT_rtl_0|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[2] ; lpm_counter:CTH_rtl_2|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_HT ; lpm_counter:CTH_rtl_2|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[2] ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_HT ; lpm_counter:CTH_rtl_2|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[2] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[4] ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_HT ; lpm_counter:CTH_rtl_2|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[0] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[1] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[2] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[3] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[4] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[5] ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_HT ; lpm_counter:CTH_rtl_2|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[2] ; SINC_HT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[3] ; SINC_HT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[4] ; SINC_HT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTH_rtl_2|dffs[5] ; SINC_HT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[2] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[3] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[4] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[5] ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[5] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[5] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[6] ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[6] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[5] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[6] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[7] ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[7] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[0] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[1] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[2] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[3] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[4] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[5] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[6] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[7] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[8] ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; SINC_VT ; lpm_counter:CTV_rtl_1|dffs[8] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[2] ; SINC_VT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[3] ; SINC_VT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[4] ; SINC_VT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[5] ; SINC_VT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[6] ; SINC_VT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[7] ; SINC_VT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CTV_rtl_1|dffs[8] ; SINC_VT ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[1] ; lpm_counter:CT_rtl_0|dffs[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[0] ; lpm_counter:CT_rtl_0|dffs[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; lpm_counter:CT_rtl_0|dffs[0] ; lpm_counter:CT_rtl_0|dffs[0] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; XCT[0] ; XCT[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; XCT[1] ; XCT[1] ; TG42_IN ; TG42_IN ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 10.800 ns ; /RESET ; SINC_VT ; TG42_IN ; TG42_IN ; -5.000 ns ; 4.000 ns ; 14.800 ns ; +; 20.000 ns ; LR_T[0] ; REG_P[2] ; TG42_IN ; TG42_IN ; -5.000 ns ; -14.000 ns ; 6.000 ns ; +; 20.000 ns ; LR_T[1] ; REG_P[2] ; TG42_IN ; TG42_IN ; -5.000 ns ; -14.000 ns ; 6.000 ns ; +; 20.000 ns ; LR_T[0] ; REG_P[1] ; TG42_IN ; TG42_IN ; -5.000 ns ; -14.000 ns ; 6.000 ns ; +; 20.000 ns ; LR_T[1] ; REG_P[1] ; TG42_IN ; TG42_IN ; -5.000 ns ; -14.000 ns ; 6.000 ns ; +; 20.000 ns ; LR_T[0] ; REG_P[0] ; TG42_IN ; TG42_IN ; -5.000 ns ; -14.000 ns ; 6.000 ns ; +; 20.000 ns ; LR_T[1] ; REG_P[0] ; TG42_IN ; TG42_IN ; -5.000 ns ; -14.000 ns ; 6.000 ns ; +; 26.000 ns ; $00047 ; /RESET ; TG42_IN ; TG42_IN ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 44.000 ns ; /RESET ; $00053 ; TG42_IN ; TG42_IN ; -5.000 ns ; -30.000 ns ; 14.000 ns ; +; 44.000 ns ; /RESET ; $00052 ; TG42_IN ; TG42_IN ; -5.000 ns ; -30.000 ns ; 14.000 ns ; +; 52.000 ns ; /RESET ; $00051 ; TG42_IN ; TG42_IN ; -5.000 ns ; -30.000 ns ; 22.000 ns ; +; 52.000 ns ; /RESET ; $00050 ; TG42_IN ; TG42_IN ; -5.000 ns ; -30.000 ns ; 22.000 ns ; ++---------------+-------------------------------+-------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'STE' ; ++---------------+----------+----------+------------+----------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+----------+----------+------------+----------+----------------------------+----------------------------+--------------------------+ +; 5.000 ns ; REG_P[1] ; REG_P[2] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[0] ; REG_P[2] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[1] ; REG_P[1] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[0] ; REG_P[1] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[1] ; REG_P[0] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[0] ; REG_P[0] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[1] ; STWG[1] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[0] ; STWG[1] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[1] ; STWG[2] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[2] ; STWG[2] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[0] ; STWG[2] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[0] ; STWG[0] ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; CT_WG ; CT_WG ; STE ; STE ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[0] ; REG_P[2] ; STE ; STE ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[1] ; REG_P[2] ; STE ; STE ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[0] ; REG_P[1] ; STE ; STE ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[1] ; REG_P[1] ; STE ; STE ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[0] ; REG_P[0] ; STE ; STE ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[1] ; REG_P[0] ; STE ; STE ; -5.000 ns ; -20.000 ns ; 6.000 ns ; ++---------------+----------+----------+------------+----------+----------------------------+----------------------------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'RSTB' ; ++---------------+----------+----------+------------+----------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+----------+----------+------------+----------+----------------------------+----------------------------+--------------------------+ +; 5.000 ns ; REG_P[1] ; REG_P[2] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[0] ; REG_P[2] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[1] ; REG_P[1] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[0] ; REG_P[1] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[1] ; REG_P[0] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[0] ; REG_P[0] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[1] ; STWG[1] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[0] ; STWG[1] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[1] ; STWG[2] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[2] ; STWG[2] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[0] ; STWG[2] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[0] ; STWG[0] ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; CT_WG ; CT_WG ; RSTB ; RSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[0] ; REG_P[2] ; RSTB ; RSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[1] ; REG_P[2] ; RSTB ; RSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[0] ; REG_P[1] ; RSTB ; RSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[1] ; REG_P[1] ; RSTB ; RSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[0] ; REG_P[0] ; RSTB ; RSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[1] ; REG_P[0] ; RSTB ; RSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; ++---------------+----------+----------+------------+----------+----------------------------+----------------------------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'WSTB' ; ++---------------+----------+----------+------------+----------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+----------+----------+------------+----------+----------------------------+----------------------------+--------------------------+ +; 5.000 ns ; REG_P[1] ; REG_P[2] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[0] ; REG_P[2] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[1] ; REG_P[1] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[0] ; REG_P[1] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[1] ; REG_P[0] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; REG_P[0] ; REG_P[0] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[1] ; STWG[1] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[0] ; STWG[1] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[1] ; STWG[2] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[2] ; STWG[2] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[0] ; STWG[2] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; STWG[0] ; STWG[0] ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 5.000 ns ; CT_WG ; CT_WG ; WSTB ; WSTB ; 0.000 ns ; 1.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[0] ; REG_P[2] ; WSTB ; WSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[1] ; REG_P[2] ; WSTB ; WSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[0] ; REG_P[1] ; WSTB ; WSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[1] ; REG_P[1] ; WSTB ; WSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[0] ; REG_P[0] ; WSTB ; WSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; +; 26.000 ns ; LR_T[1] ; REG_P[0] ; WSTB ; WSTB ; -5.000 ns ; -20.000 ns ; 6.000 ns ; ++---------------+----------+----------+------------+----------+----------------------------+----------------------------+--------------------------+ + + ++--------------------------------------------------------------------+ +; tsu ; ++-------+--------------+------------+----------+----------+----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-------+--------------+------------+----------+----------+----------+ +; N/A ; None ; 23.800 ns ; FDD_C[2] ; $00052 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; FDD_C[2] ; $00053 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[0] ; $00052 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[0] ; $00053 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[2] ; $00052 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[2] ; $00053 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[2] ; $00050 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[2] ; $00051 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; FDD_C[1] ; $00052 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; FDD_C[1] ; $00053 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; FDD_C[1] ; $00050 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; FDD_C[1] ; $00051 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; FDD_C[0] ; $00052 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; FDD_C[0] ; $00053 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[1] ; $00052 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[1] ; $00053 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[3] ; $00052 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[3] ; $00053 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[3] ; $00050 ; TG42_IN ; +; N/A ; None ; 23.800 ns ; HDD_C[3] ; $00051 ; TG42_IN ; +; N/A ; None ; 23.000 ns ; FDD_C[2] ; $00050 ; TG42_IN ; +; N/A ; None ; 23.000 ns ; FDD_C[2] ; $00051 ; TG42_IN ; +; N/A ; None ; 23.000 ns ; HDD_C[0] ; $00050 ; TG42_IN ; +; N/A ; None ; 23.000 ns ; HDD_C[0] ; $00051 ; TG42_IN ; +; N/A ; None ; 23.000 ns ; FDD_C[0] ; $00050 ; TG42_IN ; +; N/A ; None ; 23.000 ns ; FDD_C[0] ; $00051 ; TG42_IN ; +; N/A ; None ; 23.000 ns ; HDD_C[1] ; $00050 ; TG42_IN ; +; N/A ; None ; 23.000 ns ; HDD_C[1] ; $00051 ; TG42_IN ; +; N/A ; None ; 7.000 ns ; WR_CNF ; HDD_CLK ; TG42_IN ; +; N/A ; None ; 7.000 ns ; FDD_C[2] ; HDD_CLK ; TG42_IN ; +; N/A ; None ; 7.000 ns ; HDD_C[0] ; HDD_CLK ; TG42_IN ; +; N/A ; None ; -1.000 ns ; D0 ; FDD_1440 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[0] ; $00041 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[0] ; $00042 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[0] ; $00043 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[0] ; $00044 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[0] ; $00045 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[0] ; $00046 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[2] ; $00041 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[2] ; $00042 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[2] ; $00043 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[2] ; $00044 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[2] ; $00045 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[2] ; $00046 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[2] ; $00048 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[2] ; $00049 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[1] ; $00041 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[1] ; $00042 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[1] ; $00043 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[1] ; $00044 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[1] ; $00045 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[1] ; $00046 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[1] ; $00048 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[1] ; $00049 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[0] ; $00041 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[0] ; $00042 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[0] ; $00043 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[0] ; $00044 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[0] ; $00045 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; FDD_C[0] ; $00046 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[1] ; $00041 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[1] ; $00042 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[1] ; $00043 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[1] ; $00044 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[1] ; $00045 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[1] ; $00046 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[1] ; $00048 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[1] ; $00049 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[3] ; $00041 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[3] ; $00042 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[3] ; $00043 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[3] ; $00044 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[3] ; $00045 ; TG42_IN ; +; N/A ; None ; -1.000 ns ; HDD_C[3] ; $00046 ; TG42_IN ; +; N/A ; None ; -9.000 ns ; RDAT ; $00023 ; TG42_IN ; +; N/A ; None ; -9.000 ns ; RDAT ; $00021 ; TG42_IN ; +; N/A ; None ; -18.200 ns ; FDD_C[2] ; SINC_VT ; TG42_IN ; +; N/A ; None ; -18.200 ns ; HDD_C[0] ; SINC_VT ; TG42_IN ; +; N/A ; None ; -18.200 ns ; HDD_C[2] ; SINC_VT ; TG42_IN ; +; N/A ; None ; -18.200 ns ; FDD_C[1] ; SINC_VT ; TG42_IN ; +; N/A ; None ; -18.200 ns ; FDD_C[0] ; SINC_VT ; TG42_IN ; +; N/A ; None ; -18.200 ns ; HDD_C[1] ; SINC_VT ; TG42_IN ; +; N/A ; None ; -18.200 ns ; HDD_C[3] ; SINC_VT ; TG42_IN ; +; N/A ; None ; -19.000 ns ; EPM_RES ; /RESET ; TG42_IN ; +; N/A ; None ; -35.000 ns ; SR ; LR_T[0] ; STE ; +; N/A ; None ; -35.000 ns ; SR ; LR_T[0] ; RSTB ; +; N/A ; None ; -35.000 ns ; SR ; LR_T[0] ; WSTB ; +; N/A ; None ; -35.000 ns ; TR43 ; LR_T[1] ; STE ; +; N/A ; None ; -35.000 ns ; TR43 ; LR_T[1] ; RSTB ; +; N/A ; None ; -35.000 ns ; TR43 ; LR_T[1] ; WSTB ; +; N/A ; None ; -35.000 ns ; TR43 ; LR_T[0] ; STE ; +; N/A ; None ; -35.000 ns ; TR43 ; LR_T[0] ; RSTB ; +; N/A ; None ; -35.000 ns ; TR43 ; LR_T[0] ; WSTB ; +; N/A ; None ; -35.000 ns ; WD ; LR_T[1] ; STE ; +; N/A ; None ; -35.000 ns ; WD ; LR_T[1] ; RSTB ; +; N/A ; None ; -35.000 ns ; WD ; LR_T[1] ; WSTB ; +; N/A ; None ; -35.000 ns ; WD ; LR_T[0] ; STE ; +; N/A ; None ; -35.000 ns ; WD ; LR_T[0] ; RSTB ; +; N/A ; None ; -35.000 ns ; WD ; LR_T[0] ; WSTB ; +; N/A ; None ; -35.000 ns ; SL ; LR_T[1] ; STE ; +; N/A ; None ; -35.000 ns ; SL ; LR_T[1] ; RSTB ; +; N/A ; None ; -35.000 ns ; SL ; LR_T[1] ; WSTB ; +; N/A ; None ; -35.000 ns ; PW_GOOD ; $00047 ; TG42_IN ; +; N/A ; None ; -40.000 ns ; SR ; LR_T[0] ; TG42_IN ; +; N/A ; None ; -40.000 ns ; TR43 ; LR_T[1] ; TG42_IN ; +; N/A ; None ; -40.000 ns ; TR43 ; LR_T[0] ; TG42_IN ; +; N/A ; None ; -40.000 ns ; WD ; LR_T[1] ; TG42_IN ; +; N/A ; None ; -40.000 ns ; WD ; LR_T[0] ; TG42_IN ; +; N/A ; None ; -40.000 ns ; SL ; LR_T[1] ; TG42_IN ; ++-------+--------------+------------+----------+----------+----------+ + + ++---------------------------------------------------------------------------------------------+ +; tco ; ++-------+--------------+------------+-------------------------------+------------+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++-------+--------------+------------+-------------------------------+------------+------------+ +; N/A ; None ; 50.000 ns ; STWG[2] ; CLK_WG ; TG42_IN ; +; N/A ; None ; 47.000 ns ; $00047 ; XHD_RES ; TG42_IN ; +; N/A ; None ; 47.000 ns ; SINC_VT ; SINC ; TG42_IN ; +; N/A ; None ; 42.000 ns ; REG_P[2] ; WDAT ; TG42_IN ; +; N/A ; None ; 39.000 ns ; lpm_counter:CTV_rtl_1|dffs[8] ; SINC_2 ; TG42_IN ; +; N/A ; None ; 39.000 ns ; WGR[4] ; QDAT ; TG42_IN ; +; N/A ; None ; 39.000 ns ; STWG[2] ; CLK_WG ; STE ; +; N/A ; None ; 39.000 ns ; STWG[2] ; CLK_WG ; RSTB ; +; N/A ; None ; 39.000 ns ; STWG[2] ; CLK_WG ; WSTB ; +; N/A ; None ; 39.000 ns ; $00021 ; FDAT ; TG42_IN ; +; N/A ; None ; 39.000 ns ; SINC_HT ; SINC ; TG42_IN ; +; N/A ; None ; 39.000 ns ; SINC_VT ; SINC_V ; TG42_IN ; +; N/A ; None ; 36.000 ns ; $00009 ; CLK14 ; TG42_IN ; +; N/A ; None ; 31.000 ns ; /RESET ; /CONF_X ; TG42_IN ; +; N/A ; None ; 31.000 ns ; lpm_counter:CTH_rtl_2|dffs[5] ; SINC_1 ; TG42_IN ; +; N/A ; None ; 31.000 ns ; REG_P[2] ; WDAT ; STE ; +; N/A ; None ; 31.000 ns ; REG_P[2] ; WDAT ; RSTB ; +; N/A ; None ; 31.000 ns ; REG_P[2] ; WDAT ; WSTB ; +; N/A ; None ; 31.000 ns ; SINC_HT ; SINC_H ; TG42_IN ; +; N/A ; None ; 23.000 ns ; lpm_counter:CT_rtl_0|dffs[3] ; AUD ; TG42_IN ; +; N/A ; None ; 21.000 ns ; $00049 ; HD_DIR ; TG42_IN ; +; N/A ; None ; 15.000 ns ; XCT[1] ; CLKZZ ; TG42_IN ; +; N/A ; None ; 13.000 ns ; $00049 ; XHD_RD ; TG42_IN ; +; N/A ; None ; 13.000 ns ; $00048 ; XHD_WR ; TG42_IN ; +; N/A ; None ; 13.000 ns ; FDD_1440 ; 10K_D0 ; TG42_IN ; +; N/A ; None ; 13.000 ns ; $00043 ; /WG_RD ; TG42_IN ; +; N/A ; None ; 13.000 ns ; $00042 ; /WG_WR ; TG42_IN ; +; N/A ; None ; 13.000 ns ; $00041 ; WR_PDOS ; TG42_IN ; +; N/A ; None ; 13.000 ns ; $00044 ; CMOS_DWR ; TG42_IN ; +; N/A ; None ; 13.000 ns ; $00045 ; CMOS_AS ; TG42_IN ; +; N/A ; None ; 13.000 ns ; $00046 ; CMOS_DRD ; TG42_IN ; +; N/A ; None ; 5.000 ns ; $00051 ; XHD1_CS[2] ; TG42_IN ; +; N/A ; None ; 5.000 ns ; $00050 ; XHD1_CS[1] ; TG42_IN ; +; N/A ; None ; 5.000 ns ; HDD_CLK ; 10K_CLK ; TG42_IN ; +; N/A ; None ; 5.000 ns ; $00053 ; XHD2_CS[2] ; TG42_IN ; +; N/A ; None ; 5.000 ns ; $00052 ; XHD2_CS[1] ; TG42_IN ; ++-------+--------------+------------+-------------------------------+------------+------------+ + + ++------------------------------------------------------------------+ +; tpd ; ++-------+-------------------+-----------------+---------+----------+ +; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; ++-------+-------------------+-----------------+---------+----------+ +; N/A ; None ; 10.000 ns ; TG42_IN ; TG42_OUT ; +; N/A ; None ; 10.000 ns ; TG42_IN ; TG42_BUF ; ++-------+-------------------+-----------------+---------+----------+ + + ++---------------------------------------------------------------------------+ +; th ; ++---------------+-------------+------------+----------+----------+----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++---------------+-------------+------------+----------+----------+----------+ +; N/A ; None ; 51.000 ns ; SR ; LR_T[0] ; TG42_IN ; +; N/A ; None ; 51.000 ns ; TR43 ; LR_T[1] ; TG42_IN ; +; N/A ; None ; 51.000 ns ; TR43 ; LR_T[0] ; TG42_IN ; +; N/A ; None ; 51.000 ns ; WD ; LR_T[1] ; TG42_IN ; +; N/A ; None ; 51.000 ns ; WD ; LR_T[0] ; TG42_IN ; +; N/A ; None ; 51.000 ns ; SL ; LR_T[1] ; TG42_IN ; +; N/A ; None ; 40.000 ns ; SR ; LR_T[0] ; STE ; +; N/A ; None ; 40.000 ns ; SR ; LR_T[0] ; RSTB ; +; N/A ; None ; 40.000 ns ; SR ; LR_T[0] ; WSTB ; +; N/A ; None ; 40.000 ns ; TR43 ; LR_T[1] ; STE ; +; N/A ; None ; 40.000 ns ; TR43 ; LR_T[1] ; RSTB ; +; N/A ; None ; 40.000 ns ; TR43 ; LR_T[1] ; WSTB ; +; N/A ; None ; 40.000 ns ; TR43 ; LR_T[0] ; STE ; +; N/A ; None ; 40.000 ns ; TR43 ; LR_T[0] ; RSTB ; +; N/A ; None ; 40.000 ns ; TR43 ; LR_T[0] ; WSTB ; +; N/A ; None ; 40.000 ns ; WD ; LR_T[1] ; STE ; +; N/A ; None ; 40.000 ns ; WD ; LR_T[1] ; RSTB ; +; N/A ; None ; 40.000 ns ; WD ; LR_T[1] ; WSTB ; +; N/A ; None ; 40.000 ns ; WD ; LR_T[0] ; STE ; +; N/A ; None ; 40.000 ns ; WD ; LR_T[0] ; RSTB ; +; N/A ; None ; 40.000 ns ; WD ; LR_T[0] ; WSTB ; +; N/A ; None ; 40.000 ns ; SL ; LR_T[1] ; STE ; +; N/A ; None ; 40.000 ns ; SL ; LR_T[1] ; RSTB ; +; N/A ; None ; 40.000 ns ; SL ; LR_T[1] ; WSTB ; +; N/A ; None ; 40.000 ns ; PW_GOOD ; $00047 ; TG42_IN ; +; N/A ; None ; 24.000 ns ; RDAT ; $00023 ; TG42_IN ; +; N/A ; None ; 24.000 ns ; RDAT ; $00021 ; TG42_IN ; +; N/A ; None ; 24.000 ns ; EPM_RES ; /RESET ; TG42_IN ; +; N/A ; None ; 23.200 ns ; FDD_C[2] ; SINC_VT ; TG42_IN ; +; N/A ; None ; 23.200 ns ; HDD_C[0] ; SINC_VT ; TG42_IN ; +; N/A ; None ; 23.200 ns ; HDD_C[2] ; SINC_VT ; TG42_IN ; +; N/A ; None ; 23.200 ns ; FDD_C[1] ; SINC_VT ; TG42_IN ; +; N/A ; None ; 23.200 ns ; FDD_C[0] ; SINC_VT ; TG42_IN ; +; N/A ; None ; 23.200 ns ; HDD_C[1] ; SINC_VT ; TG42_IN ; +; N/A ; None ; 23.200 ns ; HDD_C[3] ; SINC_VT ; TG42_IN ; +; N/A ; None ; 6.000 ns ; D0 ; FDD_1440 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[0] ; $00041 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[0] ; $00042 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[0] ; $00043 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[0] ; $00044 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[0] ; $00045 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[0] ; $00046 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[2] ; $00041 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[2] ; $00042 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[2] ; $00043 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[2] ; $00044 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[2] ; $00045 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[2] ; $00046 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[2] ; $00048 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[2] ; $00049 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[1] ; $00041 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[1] ; $00042 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[1] ; $00043 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[1] ; $00044 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[1] ; $00045 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[1] ; $00046 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[1] ; $00048 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[1] ; $00049 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[0] ; $00041 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[0] ; $00042 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[0] ; $00043 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[0] ; $00044 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[0] ; $00045 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; FDD_C[0] ; $00046 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[1] ; $00041 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[1] ; $00042 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[1] ; $00043 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[1] ; $00044 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[1] ; $00045 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[1] ; $00046 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[1] ; $00048 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[1] ; $00049 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[3] ; $00041 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[3] ; $00042 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[3] ; $00043 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[3] ; $00044 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[3] ; $00045 ; TG42_IN ; +; N/A ; None ; 6.000 ns ; HDD_C[3] ; $00046 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; WR_CNF ; HDD_CLK ; TG42_IN ; +; N/A ; None ; -2.000 ns ; FDD_C[2] ; HDD_CLK ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[0] ; HDD_CLK ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[2] ; $00052 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[2] ; $00053 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[2] ; $00050 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[2] ; $00051 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[1] ; $00052 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[1] ; $00053 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[1] ; $00050 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[1] ; $00051 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[3] ; $00052 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[3] ; $00053 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[3] ; $00050 ; TG42_IN ; +; N/A ; None ; -2.000 ns ; HDD_C[3] ; $00051 ; TG42_IN ; +; N/A ; None ; -7.000 ns ; FDD_C[2] ; $00052 ; TG42_IN ; +; N/A ; None ; -7.000 ns ; FDD_C[2] ; $00053 ; TG42_IN ; +; N/A ; None ; -7.000 ns ; HDD_C[0] ; $00052 ; TG42_IN ; +; N/A ; None ; -7.000 ns ; HDD_C[0] ; $00053 ; TG42_IN ; +; N/A ; None ; -7.000 ns ; FDD_C[1] ; $00052 ; TG42_IN ; +; N/A ; None ; -7.000 ns ; FDD_C[1] ; $00053 ; TG42_IN ; +; N/A ; None ; -7.000 ns ; FDD_C[0] ; $00052 ; TG42_IN ; +; N/A ; None ; -7.000 ns ; FDD_C[0] ; $00053 ; TG42_IN ; +; N/A ; None ; -18.000 ns ; FDD_C[2] ; $00050 ; TG42_IN ; +; N/A ; None ; -18.000 ns ; FDD_C[2] ; $00051 ; TG42_IN ; +; N/A ; None ; -18.000 ns ; HDD_C[0] ; $00050 ; TG42_IN ; +; N/A ; None ; -18.000 ns ; HDD_C[0] ; $00051 ; TG42_IN ; +; N/A ; None ; -18.000 ns ; FDD_C[0] ; $00050 ; TG42_IN ; +; N/A ; None ; -18.000 ns ; FDD_C[0] ; $00051 ; TG42_IN ; +; N/A ; None ; -18.800 ns ; FDD_C[1] ; $00050 ; TG42_IN ; +; N/A ; None ; -18.800 ns ; FDD_C[1] ; $00051 ; TG42_IN ; ++---------------+-------------+------------+----------+----------+----------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Sun Aug 28 03:30:43 2022 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sp2_max -c sp2_max +Info: Started post-fitting delay annotation +Info: Delay annotation completed successfully +Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family +Warning: Found combinational loop of 2 nodes + Warning: Node "RDAT_X~11" + Warning: Node "RDAT_X~6" +Warning: Found combinational loop of 1 nodes + Warning: Node "TURBING~5" +Warning: Found combinational loop of 3 nodes + Warning: Node "THDD~2" + Warning: Node "NTHDD~13" + Warning: Node "NTHDD~11" +Warning: Found combinational loop of 2 nodes + Warning: Node "NT320~12" + Warning: Node "NT320~2" +Warning: Found pins functioning as undefined clocks and/or memory enables + Info: Assuming node "TG42_IN" is an undefined clock + Info: Assuming node "STE" is an undefined clock + Info: Assuming node "RSTB" is an undefined clock + Info: Assuming node "WSTB" is an undefined clock +Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew + Info: Detected gated clock "CT_WG1~8bal" as buffer + Info: Detected ripple clock "STWG[2]" as buffer + Info: Detected gated clock "STWG[2]~6bal" as buffer + Info: Detected gated clock "CT_WG~6" as buffer + Info: Detected gated clock "CT_WG~5" as buffer + Info: Detected gated clock "CT_WG~4" as buffer + Info: Detected ripple clock "CT_WG" as buffer + Info: Detected gated clock "TURBING~5" as buffer + Info: Detected ripple clock "FDD_1440" as buffer + Info: Detected ripple clock "HDD_CLK" as buffer + Info: Detected ripple clock "lpm_counter:CT_rtl_0|dffs[3]" as buffer + Info: Detected ripple clock "SINC_HT" as buffer + Info: Detected ripple clock "SINC_VT" as buffer + Info: Detected ripple clock "lpm_counter:CT_rtl_0|dffs[0]" as buffer + Info: Detected gated clock "XCT[2]~4" as buffer + Info: Detected gated clock "XCT[2]~3" as buffer + Info: Detected gated clock "XCT[2]~12" as buffer + Info: Detected gated clock "XCT[2]~11" as buffer + Info: Detected ripple clock "XCT[0]" as buffer + Info: Detected ripple clock "XCT[1]" as buffer +Info: Slack time is -47.0 ns for clock "TG42_IN" between source register "/RESET" and destination register "$00051" + Info: Fmax is 9.62 MHz (period= 104.0 ns) + Info: + Largest register to register requirement is -25.000 ns + Info: + Setup relationship between source and destination is 5.000 ns + Info: + Latch edge is 10.000 ns + Info: Clock period of Destination clock "TG42_IN" is 10.000 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 5.000 ns + Info: Clock period of Source clock "TG42_IN" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -26.000 ns + Info: + Shortest clock path from clock "TG42_IN" to destination register is 1.500 ns + Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN' + Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC121; Fanout = 1; REG Node = '$00051' + Info: Total cell delay = 1.500 ns ( 100.00 % ) + Info: - Longest clock path from clock "TG42_IN" to source register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN' + Info: 2: + IC(0.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP49; Fanout = 1; COMB Node = 'XCT[2]~4' + Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 13.500 ns; Loc. = LC56; Fanout = 18; REG Node = 'XCT[1]' + Info: 4: + IC(1.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC53; Fanout = 10; REG Node = 'lpm_counter:CT_rtl_0|dffs[3]' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC85; Fanout = 19; REG Node = '/RESET' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Micro clock to output delay of source is 2.000 ns + Info: - Micro setup delay of destination is 2.000 ns + Info: - Longest register to register delay is 22.000 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC85; Fanout = 19; REG Node = '/RESET' + Info: 2: + IC(0.000 ns) + CELL(16.000 ns) = 16.000 ns; Loc. = LC114; Fanout = 14; COMB LOOP Node = 'THDD~2' + Info: Loc. = LC119; Node "NTHDD~11" + Info: Loc. = LC114; Node "THDD~2" + Info: Loc. = LC118; Node "NTHDD~13" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 22.000 ns; Loc. = LC121; Fanout = 1; REG Node = '$00051' + Info: Total cell delay = 21.000 ns ( 95.45 % ) + Info: Total interconnect delay = 1.000 ns ( 4.55 % ) +Warning: Can't achieve timing requirement Clock Setup: 'TG42_IN' along 57 path(s). See Report window for details. +Info: Slack time is -21.0 ns for clock "STE" between source register "LR_T[0]" and destination register "REG_P[2]" + Info: Fmax is 19.23 MHz (period= 52.0 ns) + Info: + Largest register to register requirement is -15.000 ns + Info: + Setup relationship between source and destination is 5.000 ns + Info: + Latch edge is 5.000 ns + Info: Clock period of Destination clock "STE" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "STE" is 10.000 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -16.000 ns + Info: + Shortest clock path from clock "STE" to destination register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Longest clock path from clock "STE" to source register is 43.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG[2]~6bal' + Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG[2]' + Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T[0]' + Info: Total cell delay = 39.500 ns ( 90.80 % ) + Info: Total interconnect delay = 4.000 ns ( 9.20 % ) + Info: - Micro clock to output delay of source is 2.000 ns + Info: - Micro setup delay of destination is 2.000 ns + Info: - Longest register to register delay is 6.000 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T[0]' + Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 5.000 ns ( 83.33 % ) + Info: Total interconnect delay = 1.000 ns ( 16.67 % ) +Warning: Can't achieve timing requirement Clock Setup: 'STE' along 6 path(s). See Report window for details. +Info: Slack time is -21.0 ns for clock "RSTB" between source register "LR_T[0]" and destination register "REG_P[2]" + Info: Fmax is 19.23 MHz (period= 52.0 ns) + Info: + Largest register to register requirement is -15.000 ns + Info: + Setup relationship between source and destination is 5.000 ns + Info: + Latch edge is 5.000 ns + Info: Clock period of Destination clock "RSTB" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "RSTB" is 10.000 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -16.000 ns + Info: + Shortest clock path from clock "RSTB" to destination register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Longest clock path from clock "RSTB" to source register is 43.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG[2]~6bal' + Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG[2]' + Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T[0]' + Info: Total cell delay = 39.500 ns ( 90.80 % ) + Info: Total interconnect delay = 4.000 ns ( 9.20 % ) + Info: - Micro clock to output delay of source is 2.000 ns + Info: - Micro setup delay of destination is 2.000 ns + Info: - Longest register to register delay is 6.000 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T[0]' + Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 5.000 ns ( 83.33 % ) + Info: Total interconnect delay = 1.000 ns ( 16.67 % ) +Warning: Can't achieve timing requirement Clock Setup: 'RSTB' along 6 path(s). See Report window for details. +Info: Slack time is -21.0 ns for clock "WSTB" between source register "LR_T[0]" and destination register "REG_P[2]" + Info: Fmax is 19.23 MHz (period= 52.0 ns) + Info: + Largest register to register requirement is -15.000 ns + Info: + Setup relationship between source and destination is 5.000 ns + Info: + Latch edge is 5.000 ns + Info: Clock period of Destination clock "WSTB" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "WSTB" is 10.000 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -16.000 ns + Info: + Shortest clock path from clock "WSTB" to destination register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Longest clock path from clock "WSTB" to source register is 43.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG[2]~6bal' + Info: 6: + IC(1.000 ns) + CELL(7.000 ns) = 37.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG[2]' + Info: 7: + IC(1.000 ns) + CELL(5.000 ns) = 43.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T[0]' + Info: Total cell delay = 39.500 ns ( 90.80 % ) + Info: Total interconnect delay = 4.000 ns ( 9.20 % ) + Info: - Micro clock to output delay of source is 2.000 ns + Info: - Micro setup delay of destination is 2.000 ns + Info: - Longest register to register delay is 6.000 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T[0]' + Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 5.000 ns ( 83.33 % ) + Info: Total interconnect delay = 1.000 ns ( 16.67 % ) +Warning: Can't achieve timing requirement Clock Setup: 'WSTB' along 6 path(s). See Report window for details. +Info: Minimum slack time is -12.2 ns for clock "TG42_IN" between source register "FDD_1440" and destination register "$00021" + Info: + Shortest register to register delay is 14.800 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440' + Info: 2: + IC(0.000 ns) + CELL(8.800 ns) = 8.800 ns; Loc. = LC21; Fanout = 6; COMB LOOP Node = 'RDAT_X~6' + Info: Loc. = LC21; Node "RDAT_X~6" + Info: Loc. = LC20; Node "RDAT_X~11" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.800 ns; Loc. = LC17; Fanout = 12; REG Node = '$00021' + Info: Total cell delay = 13.800 ns ( 93.24 % ) + Info: Total interconnect delay = 1.000 ns ( 6.76 % ) + Info: - Smallest register to register requirement is 27.000 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is 0.000 ns + Info: Clock period of Destination clock "TG42_IN" is 10.000 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "TG42_IN" is 10.000 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 26.000 ns + Info: + Longest clock path from clock "TG42_IN" to destination register is 35.500 ns + Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN' + Info: 2: + IC(0.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = SEXP49; Fanout = 1; COMB Node = 'XCT[2]~4' + Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 13.500 ns; Loc. = LC56; Fanout = 18; REG Node = 'XCT[1]' + Info: 4: + IC(1.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC122; Fanout = 9; REG Node = 'lpm_counter:CT_rtl_0|dffs[0]' + Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 29.500 ns; Loc. = LC28; Fanout = 7; COMB Node = 'CT_WG1~8bal' + Info: 6: + IC(1.000 ns) + CELL(5.000 ns) = 35.500 ns; Loc. = LC17; Fanout = 12; REG Node = '$00021' + Info: Total cell delay = 32.500 ns ( 91.55 % ) + Info: Total interconnect delay = 3.000 ns ( 8.45 % ) + Info: - Shortest clock path from clock "TG42_IN" to source register is 9.500 ns + Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN' + Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK' + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440' + Info: Total cell delay = 8.500 ns ( 89.47 % ) + Info: Total interconnect delay = 1.000 ns ( 10.53 % ) + Info: - Micro clock to output delay of source is 2.000 ns + Info: + Micro hold delay of destination is 3.000 ns +Warning: Can't achieve minimum setup and hold requirement TG42_IN along 48 path(s). See Report window for details. +Info: Minimum slack time is 5.0 ns for clock "STE" between source register "REG_P[1]" and destination register "REG_P[2]" + Info: + Shortest register to register delay is 6.000 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P[1]' + Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 5.000 ns ( 83.33 % ) + Info: Total interconnect delay = 1.000 ns ( 16.67 % ) + Info: - Smallest register to register requirement is 1.000 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is 5.000 ns + Info: Clock period of Destination clock "STE" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 5.000 ns + Info: Clock period of Source clock "STE" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "STE" to destination register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Shortest clock path from clock "STE" to source register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_94; Fanout = 4; CLK Node = 'STE' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P[1]' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Micro clock to output delay of source is 2.000 ns + Info: + Micro hold delay of destination is 3.000 ns +Info: Minimum slack time is 5.0 ns for clock "RSTB" between source register "REG_P[1]" and destination register "REG_P[2]" + Info: + Shortest register to register delay is 6.000 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P[1]' + Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 5.000 ns ( 83.33 % ) + Info: Total interconnect delay = 1.000 ns ( 16.67 % ) + Info: - Smallest register to register requirement is 1.000 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is 5.000 ns + Info: Clock period of Destination clock "RSTB" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 5.000 ns + Info: Clock period of Source clock "RSTB" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "RSTB" to destination register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Shortest clock path from clock "RSTB" to source register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 2; CLK Node = 'RSTB' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P[1]' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Micro clock to output delay of source is 2.000 ns + Info: + Micro hold delay of destination is 3.000 ns +Info: Minimum slack time is 5.0 ns for clock "WSTB" between source register "REG_P[1]" and destination register "REG_P[2]" + Info: + Shortest register to register delay is 6.000 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P[1]' + Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 5.000 ns ( 83.33 % ) + Info: Total interconnect delay = 1.000 ns ( 16.67 % ) + Info: - Smallest register to register requirement is 1.000 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is 5.000 ns + Info: Clock period of Destination clock "WSTB" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 5.000 ns + Info: Clock period of Source clock "WSTB" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "WSTB" to destination register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC8; Fanout = 1; REG Node = 'REG_P[2]' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Shortest clock path from clock "WSTB" to source register is 27.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_10; Fanout = 2; CLK Node = 'WSTB' + Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 4: + IC(0.000 ns) + CELL(7.000 ns) = 21.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 27.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'REG_P[1]' + Info: Total cell delay = 25.500 ns ( 92.73 % ) + Info: Total interconnect delay = 2.000 ns ( 7.27 % ) + Info: - Micro clock to output delay of source is 2.000 ns + Info: + Micro hold delay of destination is 3.000 ns +Info: tsu for register "$00052" (data pin = "FDD_C[2]", clock pin = "TG42_IN") is 23.800 ns + Info: + Longest pin to register delay is 23.300 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_46; Fanout = 20; PIN Node = 'FDD_C[2]' + Info: 2: + IC(0.000 ns) + CELL(16.800 ns) = 17.300 ns; Loc. = LC119; Fanout = 10; COMB LOOP Node = 'NTHDD~11' + Info: Loc. = LC119; Node "NTHDD~11" + Info: Loc. = LC114; Node "THDD~2" + Info: Loc. = LC118; Node "NTHDD~13" + Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 23.300 ns; Loc. = LC123; Fanout = 1; REG Node = '$00052' + Info: Total cell delay = 22.300 ns ( 95.71 % ) + Info: Total interconnect delay = 1.000 ns ( 4.29 % ) + Info: + Micro setup delay of destination is 2.000 ns + Info: - Shortest clock path from clock "TG42_IN" to destination register is 1.500 ns + Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN' + Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC123; Fanout = 1; REG Node = '$00052' + Info: Total cell delay = 1.500 ns ( 100.00 % ) +Info: tco from clock "TG42_IN" to destination pin "CLK_WG" through register "STWG[2]" is 50.000 ns + Info: + Longest clock path from clock "TG42_IN" to source register is 46.500 ns + Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN' + Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK' + Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 11.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440' + Info: 4: + IC(0.000 ns) + CELL(8.000 ns) = 19.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 25.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 32.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 7: + IC(1.000 ns) + CELL(7.000 ns) = 40.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG[2]~6bal' + Info: 8: + IC(1.000 ns) + CELL(5.000 ns) = 46.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG[2]' + Info: Total cell delay = 42.500 ns ( 91.40 % ) + Info: Total interconnect delay = 4.000 ns ( 8.60 % ) + Info: + Micro clock to output delay of source is 2.000 ns + Info: + Longest register to pin delay is 1.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG[2]' + Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'CLK_WG' + Info: Total cell delay = 1.500 ns ( 100.00 % ) +Info: Longest tpd from source pin "TG42_IN" to destination pin "TG42_OUT" is 10.000 ns + Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN' + Info: 2: + IC(0.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC128; Fanout = 1; COMB Node = '$00003~3' + Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 10.000 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'TG42_OUT' + Info: Total cell delay = 10.000 ns ( 100.00 % ) +Info: th for register "LR_T[0]" (data pin = "SR", clock pin = "TG42_IN") is 51.000 ns + Info: + Longest clock path from clock "TG42_IN" to destination register is 54.500 ns + Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 11; CLK Node = 'TG42_IN' + Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC88; Fanout = 10; REG Node = 'HDD_CLK' + Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 11.500 ns; Loc. = LC91; Fanout = 13; REG Node = 'FDD_1440' + Info: 4: + IC(0.000 ns) + CELL(8.000 ns) = 19.500 ns; Loc. = LC32; Fanout = 3; COMB LOOP Node = 'TURBING~5' + Info: Loc. = LC32; Node "TURBING~5" + Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 25.500 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'CT_WG~6' + Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 32.500 ns; Loc. = LC26; Fanout = 8; REG Node = 'CT_WG' + Info: 7: + IC(1.000 ns) + CELL(7.000 ns) = 40.500 ns; Loc. = LC16; Fanout = 3; COMB Node = 'STWG[2]~6bal' + Info: 8: + IC(1.000 ns) + CELL(7.000 ns) = 48.500 ns; Loc. = LC19; Fanout = 6; REG Node = 'STWG[2]' + Info: 9: + IC(1.000 ns) + CELL(5.000 ns) = 54.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T[0]' + Info: Total cell delay = 49.500 ns ( 90.83 % ) + Info: Total interconnect delay = 5.000 ns ( 9.17 % ) + Info: + Micro hold delay of destination is 3.000 ns + Info: - Shortest pin to register delay is 6.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'SR' + Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'LR_T[0]' + Info: Total cell delay = 5.500 ns ( 84.62 % ) + Info: Total interconnect delay = 1.000 ns ( 15.38 % ) +Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details. +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 21 warnings + Info: Peak virtual memory: 185 megabytes + Info: Processing ended: Sun Aug 28 03:30:43 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/src/altera/quartus/max/sp2_max.tan.summary b/src/altera/quartus/max/sp2_max.tan.summary new file mode 100644 index 0000000..9aa9881 --- /dev/null +++ b/src/altera/quartus/max/sp2_max.tan.summary @@ -0,0 +1,136 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : N/A +Required Time : None +Actual Time : 23.800 ns +From : HDD_C[3] +To : $00051 +From Clock : -- +To Clock : TG42_IN +Failed Paths : 0 + +Type : Worst-case tco +Slack : N/A +Required Time : None +Actual Time : 50.000 ns +From : STWG[2] +To : CLK_WG +From Clock : TG42_IN +To Clock : -- +Failed Paths : 0 + +Type : Worst-case tpd +Slack : N/A +Required Time : None +Actual Time : 10.000 ns +From : TG42_IN +To : TG42_BUF +From Clock : -- +To Clock : -- +Failed Paths : 0 + +Type : Worst-case th +Slack : N/A +Required Time : None +Actual Time : 51.000 ns +From : SL +To : LR_T[1] +From Clock : -- +To Clock : TG42_IN +Failed Paths : 0 + +Type : Clock Setup: 'TG42_IN' +Slack : -47.000 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : 9.62 MHz ( period = 104.000 ns ) +From : /RESET +To : $00051 +From Clock : TG42_IN +To Clock : TG42_IN +Failed Paths : 57 + +Type : Clock Setup: 'STE' +Slack : -21.000 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : 19.23 MHz ( period = 52.000 ns ) +From : LR_T[0] +To : REG_P[2] +From Clock : STE +To Clock : STE +Failed Paths : 6 + +Type : Clock Setup: 'RSTB' +Slack : -21.000 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : 19.23 MHz ( period = 52.000 ns ) +From : LR_T[0] +To : REG_P[2] +From Clock : RSTB +To Clock : RSTB +Failed Paths : 6 + +Type : Clock Setup: 'WSTB' +Slack : -21.000 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : 19.23 MHz ( period = 52.000 ns ) +From : LR_T[0] +To : REG_P[2] +From Clock : WSTB +To Clock : WSTB +Failed Paths : 6 + +Type : Clock Hold: 'TG42_IN' +Slack : -12.200 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : N/A +From : FDD_1440 +To : $00021 +From Clock : TG42_IN +To Clock : TG42_IN +Failed Paths : 48 + +Type : Clock Hold: 'STE' +Slack : 5.000 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : N/A +From : REG_P[1] +To : REG_P[2] +From Clock : STE +To Clock : STE +Failed Paths : 0 + +Type : Clock Hold: 'RSTB' +Slack : 5.000 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : N/A +From : REG_P[1] +To : REG_P[2] +From Clock : RSTB +To Clock : RSTB +Failed Paths : 0 + +Type : Clock Hold: 'WSTB' +Slack : 5.000 ns +Required Time : 100.00 MHz ( period = 10.000 ns ) +Actual Time : N/A +From : REG_P[1] +To : REG_P[2] +From Clock : WSTB +To Clock : WSTB +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 123 + +-------------------------------------------------------------------------------------- + diff --git a/src/altera/quartus/max/sp2_max.tdf b/src/altera/quartus/max/sp2_max.tdf new file mode 100644 index 0000000..b24582c --- /dev/null +++ b/src/altera/quartus/max/sp2_max.tdf @@ -0,0 +1,499 @@ + +TITLE "SINC_controller"; + +PARAMETERS + ( + G_MODE = 1, -- 1 on LCELL, 0 - on EXP + + NUM = "NO", + NUMBER1 = B"00100000X", -- 0 - sinc + NUMBER2 = B"00110111X", -- 7 + NUMBER3 = B"01001101X", -- D + NUMBER4 = B"01010010X", -- 2 + NUMBER5 = B"00100000X", -- + NUMBER6 = B"00100000X", -- + NUMBER7 = B"00100000X" -- + ); + +SUBDESIGN SP2_MAX + ( + + TG42_IN : INPUT; + TG42_OUT : OUTPUT; + TG42_BUF : OUTPUT; + CLKZZ : BIDIR; + CLK14 : OUTPUT; + + AUD : OUTPUT; -- clk for timers + BEEP : OUTPUT; + + CMOS_DRD : OUTPUT; + CMOS_AS : OUTPUT; + CMOS_DWR : OUTPUT; + + WR_PDOS : OUTPUT; + WD : INPUT; + WSTB : INPUT; + SR,SL : INPUT; + RSTB : INPUT; + TR43 : INPUT; + CLK_WG : OUTPUT; + FDAT : OUTPUT; + QDAT : OUTPUT; + RDAT : INPUT; + /WG_WR : OUTPUT; + /WG_RD : OUTPUT; + STE : INPUT; + DENS_X : OUTPUT; + WDAT : OUTPUT; + + +-- XA[2..0] : BIDIR; + XA[2..0] : INPUT; + XACS : INPUT; +-- SINC_1 : OUTPUT; + SINC_1 : BIDIR; + SINC_2 : BIDIR; + + HDD_C[3..0] : INPUT; + FDD_C[2..0] : INPUT; + + HD_DIR : OUTPUT; + HD_CS : OUTPUT; + + /CONF_X : BIDIR; + 10K_CLK : OUTPUT; + WR_CNF : INPUT; + 10K_D0 : OUTPUT; + D0 : INPUT; + + VGA_IN : INPUT; +-- WR_COL : INPUT; + SINC_V : OUTPUT; + SINC_H : OUTPUT; + SINC : OUTPUT; + SINC_IN : INPUT; + + XHD_RES : OUTPUT; + XHD_WR : OUTPUT; + XHD_RD : OUTPUT; + + XHD1_CS[2..1] : OUTPUT; + XHD2_CS[2..1] : OUTPUT; + XHR_RDY : INPUT; + + EPM_RES : INPUT; + PW_GOOD : INPUT; + + UNUSED65 : INPUT; -- was GND65, hack for 3000 family + UNUSED33 : INPUT; -- was GND33, hack for 3000 family + UNUSED1 : INPUT; + UNUSED2 : INPUT; + UNUSED5 : INPUT; + UNUSED7 : INPUT; + UNUSED22 : INPUT; + UNUSED24 : INPUT; + UNUSED27 : INPUT; + UNUSED28 : INPUT; + UNUSED49 : INPUT; + UNUSED50 : INPUT; + UNUSED53 : INPUT; + UNUSED55 : INPUT; + UNUSED63 : INPUT; + UNUSED70 : INPUT; + UNUSED72 : INPUT; + UNUSED77 : INPUT; + UNUSED78 : INPUT; + + + + ) +VARIABLE + + XCT[2..0] : DFF; + CNF_ON : NODE; + CNF_OFF : NODE; + + CLK42 : NODE; + + CT[3..0] : DFF; + CTH[5..0] : DFF; + CTV[8..0] : DFFE; + + SINC_HT : DFF; + SINC_VT : DFFE; + + TURBING : NODE; + FDD_1440 : NODE; + NFDD_1440 : NODE; + + CT_WG : NODE; + CT_WG1 : NODE; + + STWG[2..0] : DFF; + CLK_PRC : NODE; + WGR[4..0] : DFF; + RDAT_X : NODE; + + REG_P[2..0] : DFF; + + /RESET : NODE; + + + S144,S720 : NODE; + + SHDD1,SHDD2 : NODE; + THDD : NODE; + NTHDD : NODE; + + NO_HDD : NODE; + + S320,S312 : NODE; + T320 : NODE; + NT320 : NODE; + + SOFT_RESET : NODE; + SOFT_RESET2 : NODE; + + HDD_CLK : NODE; + + LR_T[1..0] : DFF; + + EXP_X : NODE; + EXP_Y : NODE; + + CTV8M : DFF; + + CTV8C : NODE; + + FN_NUM : NODE; + +BEGIN + + /RESET = DFF((EPM_RES & XHD_RES),!CT3,SOFT_RESET,); + +-- /RESET = (EXP(!EPM_RES & EXP(EXP(EXP(EPM_RES)))) & SOFT_RESET); + + EXP_X = EXP(TG42_IN); + EXP_Y = EXP(TG42_IN); + + IF (G_MODE == 0) GENERATE + TG42_OUT = LCELL(EXP_X); + ELSE GENERATE + TG42_OUT = LCELL(TG42_BUF); + END GENERATE; + + TG42_BUF = LCELL(!TG42_IN); + + CLK42 = TG42_IN; + +-- CT[].clk = CLK14; + CT[].clk = XCT1; + CT[] = CT[] + 1; + +-- === horizontal sinc ===== + + CTH[].clk = !CT3; + SINC_HT.clk = !CT3; + + IF !((CTH[] == B"XXXX11") & SINC_HT) THEN + CTH[] = CTH[] + 1; + ELSE + CTH[] = GND; + END IF; + +-- SINC_1 = CTH5; + SINC_1 = TRI(CTH5,VCC); + SINC_2 = TRI(CTV8,VCC); + + SINC_HT.d = (CTH[] == B"1101XX"); + + SINC_H = SINC_HT; + +-- === vertical sinc ======= + +-- CTV[].clk = !CT3; +-- SINC_VT.clk = !CT3; + + CTV[].clk = SINC_HT; + SINC_VT.clk = SINC_HT; + + CTV8M.clk = SINC_HT; + +-- CTV[].ena = (CTH[] == B"110111"); +-- SINC_VT.ena = (CTH[] == B"110111"); + CTV[].ena = VCC; + SINC_VT.ena = VCC; + +-- IF (CTV[] == B"100111111") THEN + + IF (NUM == "YES") GENERATE + + FN_NUM =( + (CTV[8..0] == NUMBER1) or + (CTV[8..0] == NUMBER2) or + (CTV[8..0] == NUMBER3) or + (CTV[8..0] == NUMBER4) or + (CTV[8..0] == NUMBER5) or + (CTV[8..0] == NUMBER6) or + (CTV[8..0] == NUMBER7) + ) & !NO_HDD; + + ELSE GENERATE + + FN_NUM = GND; + + END GENERATE; + + + IF EXP((CTV[] == B"XXXXXXX11") & SINC_VT) THEN + + (CTV[8..0]) = ((CTV[8..0]) + 1) xor (CTV8M,B"00000000"); + CTV8M = FN_NUM; + + ELSE + CTV[7..0] = GND; + CTV8M = GND; + CTV8 = GND; + END IF; + + SINC_VT.d = ((CTV[8..0] == B"1001111XX") or ((CTV[8..0] == B"1001101XX")) & NT320); + + SINC_V = SINC_VT; + + SINC = SINC_V xor SINC_H; + +-- ============================= + +-- ========================================= +-- divide by 6 + + XCT[].clk = (TG42_IN xor !XCT1); + XCT[].d = XCT[] + 1; + +-- CLKZZ = 14 MHz + + CLKZZ = TRI(XCT1,CNF_OFF); + CLK14 = DFF(!CLK14,XCT0,,); + +-- test exists + +-- CNF_OFF = EXP(CNF_ON & /RESET); +-- CNF_ON = EXP(CNF_OFF & XACS); + + CNF_OFF = DFF(GND,GND,XACS,/RESET); + CNF_ON = !CNF_OFF; + +-- ========================================= + +-- ======== FDD controller ================== + + TURBING = EXP(EXP(TURBING & !WSTB & !RSTB) & !STE & NFDD_1440); +-- TURBING = GND; + + CT_WG = TFF(VCC,(XCT1 xor (CT_WG & TURBING)),,); + + STWG[].clk = (CT_WG xor STWG2); + STWG[].d = STWG[] + 1; + + CLK_WG = STWG2; + +-- CLK_PRC = STWG0; + CLK_PRC = CT_WG; + + CT_WG1 = EXP(EXP(XCT1 & FDD_1440) & EXP(CT0 & NFDD_1440)); + + WGR[].clk = CT_WG1; + + IF !FDAT THEN + TABLE WGR[3..0] => WGR[3..0].d; + 0 => 4; 1 => 5; 2 => 4; 3 => 5; + 4 => 6; 5 => 7; 6 => 8; 7 => 8; + 8 => 9; 9 => 9; 10 => 10; 11 => 11; + 12 => 12; 13 => 13; 14 => 14; 15 => 15; + END TABLE; + WGR4.d = WGR4; + ELSE + IF WGR[3..0] == 0 THEN + WGR[3..0].d = 3; + WGR4.d = WGR4; + ELSE + WGR[].d = WGR[] + 1; + END IF; + END IF; + + QDAT = WGR4; + RDAT_X = EXP(EXP(RDAT_X & EXP(!RDAT & !CT_WG1)) & EXP(RDAT & !CT_WG1)); +-- FDAT = DFF((RDAT_X or !DFF(RDAT_X,CT_WG1,,)),CT_WG1,,); + FDAT = DFF((RDAT_X or EXP(DFF(RDAT_X,CT_WG1,,))),CT_WG1,,); +-- ========================================================== +-- now not complete! + + AUD = CT3; + BEEP = GND; + +-- /CONF_X = TRI(GND,!/RESET); + + /CONF_X = OPNDRN(/RESET); + +-- 10K_CLK = WR_CNF; -- now not protect! + + 10K_CLK = DFF((WR_CNF & CNF_OFF) or ((HDD_C0 or FDD_C2) & CNF_ON),CLK42,,); + + 10K_D0 = DFFE(D0,10K_CLK,S720,(S144 & /RESET),CNF_OFF); + + DENS_X = VCC; + +-- === now NOT PRECOMP! ===== + +-- WDAT = WD; + + WDAT = REG_P2; + + REG_P[].clk = !CLK_PRC; + +-- CASE WD IS +-- WHEN 1 => REG_P[].d = (GND,SL,!(SL or SR),SR); +-- WHEN 0 => REG_P[].d = (EXP(EXP(REG_P2)),REG_P[1..0],GND); +-- END CASE; + +-- CASE (DFF(WD,CLK_WG,,),DFF((SL & TR43),CLK_WG,,),DFF((SR & TR43),CLK_WG,,)) IS + + LR_T[].clk = STWG2; +-- LR_T[].clk = CLK_WG; + + LR_T[].d = ((WD & !(SL & TR43)),(WD & !(SR & TR43))); + + CASE LR_T[] IS + WHEN 0 => REG_P[1..0] = (REG_P[1..0] - 1) & EXP(REG_P[1..0] == 0); + REG_P[2] = EXP(EXP(REG_P[1..0] == 1)); +-- REG_P[2] = (REG_P[1..0] == 1); + WHEN 1 => REG_P[1..0] = 1; REG_P[2] = GND; + WHEN 2 => REG_P[1..0] = 3; REG_P[2] = GND; + WHEN 3 => REG_P[1..0] = 2; REG_P[2] = GND; + END CASE; +% + CASE (WD,DFF((SL & TR43),CLK_WG,,),DFF((SR & TR43),CLK_WG,,)) IS + WHEN B"0XX" => REG_P[1..0] = (REG_P[1..0] - 1) & EXP(REG_P[1..0] == 0); + WHEN B"100" => REG_P[1..0] = 2; + WHEN B"110" => REG_P[1..0] = 1; + WHEN B"101" => REG_P[1..0] = 3; + WHEN B"111" => REG_P[1..0] = 2; + END CASE; +% + +% + CASE WD IS + WHEN 0 => REG_P[3] = EXP(EXP(REG_P[1..0] == 1)); + WHEN 1 => REG_P[3] = GND; + END CASE; +% + +-- === Port Controls ==================================== +% + FDD_C0 - 0 - WG93 / 1 - kmps/ p_dos + FDD_C1 - 0 - write / 1 - read + FDD_C2 - 0 - no / 1 - CS_WG/ strobe + + HDD_C0 - strobe + HDD_C[2..1] = 00 - SYS_FN, 01 - SYS_FN, 10 - HDD1/2, 11 - CMOS + HDD_C3 - 0 - HD_CS1, 1 HD_CS3 / 0 CMOS_DAT, 1 - CMOS_ADR + + HDD_C[3..0] = 0001, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set 1.44/720 + HDD_C[3..0] = 1001, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set 320/312 lines + HDD_C[3..0] = 0011, FDD_C[2..1] = 00; -> FDD_C0 = 1/0 -> set HDD1/HDD2 + HDD_C[3..0] = 1011, FDD_C[2..1] = 00; -> FDD_C0 = 0 -> soft_reset! + HDD_C[3..0] = X101, FDD_C[2..1] = XX; -> HDD1/2 rd/wr + +% + + SOFT_RESET = !((HDD_C[] == B"1011") & (FDD_C[] == B"000")); + SOFT_RESET2 = !((HDD_C[] == B"1011") & (FDD_C[] == B"001")); + +-- FDD switch + +-- NFDD_1440 = EXP(FDD_1440 & S720 & /RESET); +-- FDD_1440 = EXP(NFDD_1440 & S144); + FDD_1440 = 10K_D0; + NFDD_1440 = !10K_D0; + + S144 = EXP((HDD_C[] == B"0001") & (FDD_C[] == B"001")); + S720 = EXP((HDD_C[] == B"0001") & (FDD_C[] == B"000")); + +-- Screen Switch + + T320 = EXP(NT320 & S320 & /RESET); + NT320 = EXP(T320 & S312); + + S312 = EXP((HDD_C[] == B"1001") & (FDD_C[] == B"001")); + S320 = EXP((HDD_C[] == B"1001") & (FDD_C[] == B"000")); + +-- HDD Switch + +-- THDD = EXP(NTHDD & SHDD2 & /RESET); +-- NTHDD = EXP(THDD & SHDD1); + + THDD = EXP(NTHDD & NO_HDD & SHDD2 & /RESET & SOFT_RESET2); + NTHDD = EXP(THDD & NO_HDD & SHDD1 & /RESET & SOFT_RESET2); + NO_HDD = EXP(NTHDD & THDD & SHDD1 & SHDD2); + + SHDD2 = EXP((HDD_C[] == B"0011") & (FDD_C[] == B"001")); + SHDD1 = EXP((HDD_C[] == B"0011") & (FDD_C[] == B"000")); + +-- Control signals + + WR_PDOS = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2); + /WG_WR = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X00")),HDD_CLK,,FDD_C2); + /WG_RD = DFF(!((HDD_C[] == 0) & (FDD_C[] == B"X10")),HDD_CLK,,FDD_C2); + + CMOS_DWR = DFF(!((HDD_C[] == B"1110") & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2); + CMOS_AS =!DFF(!((HDD_C[] == B"0110") & (FDD_C[] == B"X01")),HDD_CLK,,FDD_C2); + CMOS_DRD = DFF(!((HDD_C[] == B"1110") & (FDD_C[] == B"X10")),HDD_CLK,,FDD_C2); + +-- HD_DIR = !HDD_C1; -- ???????????? + HD_DIR = XHD_RD; + +-- HD_CS = GND; +-- HD_CS = CTV8M; + HD_CS = (CTV8M and /RESET); + + +-- HD_CS = !/RESET; + +-- XHD_RES = VCC; + +-- XHD_RES = DFF(PW_GOOD,SINC_V,,); + XHD_RES = DFF(PW_GOOD,SINC_V,EPM_RES,); + +-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),CLK42,,); +-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),CLK42,,); + +-- HDD_CLK = EXP(EXP(HDD_C0)); + HDD_CLK = 10K_CLK; + +-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1 or !HDD_CLK),CLK42,,HDD_C0); +-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1 or !HDD_CLK),CLK42,,HDD_C0); +-- XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,HDD_C0); +-- XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,HDD_C0); + XHD_WR = DFF((!(HDD_C[] == B"X101") or FDD_C1),HDD_CLK,,(HDD_C0 and /RESET)); + XHD_RD = DFF((!(HDD_C[] == B"X101") or !FDD_C1),HDD_CLK,,(HDD_C0 and /RESET)); + +-- XHD1_CS1 = DFF(!((HDD_C[] == B"010X") & NTHDD),CLK42,,); +-- XHD1_CS2 = DFF(!((HDD_C[] == B"110X") & NTHDD),CLK42,,); + +-- XHD2_CS1 = DFF(!((HDD_C[] == B"010X") & THDD),CLK42,,); +-- XHD2_CS2 = DFF(!((HDD_C[] == B"110X") & THDD),CLK42,,); + +-- XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,); +-- XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,); + XHD1_CS1 = DFF((!(HDD_C[] == B"010X") or THDD),CLK42,,/RESET); + XHD1_CS2 = DFF((!(HDD_C[] == B"110X") or THDD),CLK42,,/RESET); + +-- XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,); +-- XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,); + XHD2_CS1 = DFF((!(HDD_C[] == B"010X") or NTHDD),CLK42,,/RESET); + XHD2_CS2 = DFF((!(HDD_C[] == B"110X") or NTHDD),CLK42,,/RESET); + + +END; + diff --git a/src/bin/sjasmplus.exe b/src/bin/sjasmplus.exe deleted file mode 100644 index a48537b..0000000 Binary files a/src/bin/sjasmplus.exe and /dev/null differ diff --git a/src/bios/BIOS.asm b/src/bios/BIOS.asm index 6f9bcfc..f2b268f 100644 --- a/src/bios/BIOS.asm +++ b/src/bios/BIOS.asm @@ -19,6 +19,19 @@ INCLUDE 'src/bios/shared/includes.inc' ; Includes ;--------------------------------------- + + LUA PASS1 + local date, month, year = Get_date_RU(sj.get_define("__DATE__")) + BuildDate = "'" .. date .. "." .. month .. "." .. year .. "'" + BuildYear = "'" .. year .. "'" + sj.insert_define("BUILD_DATE", BuildDate) + sj.insert_define("BUILD_YEAR", BuildYear) + ENDLUA + LUA ALLPASS + sj.insert_define("BUILD_DATE", BuildDate) + sj.insert_define("BUILD_YEAR", BuildYear) + ENDLUA + IF PACKED_MAIN ;------------[MAIN prebuild]------------; LUA PASS1 @@ -67,6 +80,7 @@ ;-----------------[EXP]----------------- MMU 0 e, 8 ; страница 8 в банку 0 и проверка на границы ORG COMPILE_ADDR.EXP + DEFINE+ IsInBIOS 1 OUTPUT 'Build/Bin/EXP.BIN' ShowInfo 'EXP block Start', 0 ; !!!!! test INCLUDE 'src/bios/EXP/EXP.asm' @@ -80,11 +94,13 @@ ;-----------------[ROM]----------------- MMU 0 e, 0 ; страница 0 в банку 0 и проверка на границы. ORG ROM_MAP.ROM + DEFINE+ IsInBIOS 0 OUTPUT 'Build/Bin/ROM.BIN' ShowInfo 'ROM block Start', 0 ; !!!!! test INCLUDE 'src/bios/ROM/ROM.asm' ShowInfo 'ROM block End', 0 ; !!!!! test OUTEND + UNDEFINE IsInBIOS ;--------------------------------------- ; @@ -123,18 +139,29 @@ OUTEND ;--------------------------------------- ; - EXPORT ID_Version - EXPORT ID_SPRINTER.bitstream_ver - EXPORT bitstream_ver_hex - EXPORT Disk_subsystem_ver_hex - EXPORT EXP_ID.VER - EXPORT EXP_ID.MOD - EXPORT ROM_ID.VER - EXPORT ROM_ID.MOD + ;EXPORT ROM_NUMBER ; !FIXIT part1, part2 для Flasher + EXPORT BOARD_INFO.number + EXPORT BOARD_INFO.type EXPORT BoardID.start EXPORT BoardID.end - EXPORT ROM_NUMBER ; !FIXIT part1, part2 для Flasher - + EXPORT FN_CRIPT.cnf + EXPORT ID_SPRINTER.bitstream_ver + EXPORT bitstream_ver_hex + ;EXPORT ID_Version + ;EXPORT ID_SPRINTER.BIOS_ver + ;EXPORT BIOS_ver_hex + ;EXPORT Disk_subsystem_ver_hex + EXPORT EXP_ID.VER ; Версия биоса + EXPORT EXP_ID.MOD + ;EXPORT ROM_ID.VER ; Версия дисковой подсистемы + ;EXPORT ROM_ID.MOD + EXPORT CNF_ID.VER ; Версия конфы + EXPORT CNF_ID.MOD + EXPORT msgStrings.str_ACEX_MODEL + EXPORT msgRusStrings.str_ACEX_MODEL + EXPORT BETA_BUILD + EXPORT BETA_RC + EXPORT RELEASEhotFIX ; LUA ALLPASS ; print ("DEPACKER", sj.get_label("DEPACKER.PackedMAIN")) ; print ("UnPacker", sj.get_label("UnPacker.PackedMAIN")) diff --git a/src/bios/BUILD.a80 b/src/bios/BUILD.a80 index 448e2ca..14c423a 100644 --- a/src/bios/BUILD.a80 +++ b/src/bios/BUILD.a80 @@ -32,7 +32,9 @@ ENDM ;[--------------------------------------------------------------------------] - + DEFINE SP_128_BIN INCBIN 'src/ZX_ROMS/NEW/SP_128.BIN' + DEFINE SP__48_BIN INCBIN 'src/ZX_ROMS/NEW/SP__48.BIN' + DEFINE SP_TRDOS_BIN INCBIN 'src/ZX_ROMS/NEW/SP_TRDOS.BIN' ;[--------------------------------------------------------------------------] MACRO ROM_BUILD bitstream @@ -41,44 +43,26 @@ Set_Block 'ROM free space: ', #4000 ; ;PAGE 1 -; INCBIN 'Build/Bin/LOGO_PAL.BIN' -; INCBIN 'Build/Bin/LOGO_DAT.BIN' INCBIN 'Build/Bin/LOGO.BIN' Set_Block 'LOGO free space: ', #8000 ; ; ;PAGE 2 ZX Page - #42 - INCBIN 'src/ZX_ROMS/SP_128.BIN' + SP_128_BIN Set_Block 'SP_128 free space: ', #C000 ; ;PAGE 3 ZX Page - #43 - INCBIN 'src/ZX_ROMS/SP__48.BIN' + SP__48_BIN Set_Block 'SP_48 free space: ', #10000 ; ;PAGE 4 ZX Page - #44 - INCBIN 'src/ZX_ROMS/SP_TRD.BIN' + SP_TRDOS_BIN Set_Block 'SP_TRD free space: ', #14000 ; -;PAGE 5 ZX Page - #45 - INCBIN 'src/ZX_ROMS/SP_EXP.BIN' - Set_Block 'SP_EXP free space: ', #18000 - - IF SetFullZXromLoader -; -;PAGE 6 ZX Page - #46 - INCBIN 'src/ZX_ROMS/SP_EXP.BIN' - Set_Block 'SP_EXP (duble) free space: ', #1C000 -; -;PAGE 7 ZX Page - #47 - INCBIN 'src/ZX_ROMS/SP_EXP2.BIN' - Set_Block 'SP_EXP2 free space: ', #20000 - ELSE - INCBIN IMG_RECOVERY,0,#8000 - DISPLAY "ROM Disk recovery part1, pages 6..7: #20000..#28000" - ;Set_Block 'Empty space: ', #1C000 ; 6 - ;Set_Block 'Empty space: ', #20000 ; 7 - ENDIF +;PAGE 5 Recovery image part 1 + INCBIN IMG_RECOVERY,0,#C000 + DISPLAY "ROM Disk recovery part1, pages 5..7: 1x4000..2x0000" ; @@ -87,12 +71,10 @@ INCBIN 'Build/Bin/EXP.BIN' Set_Block 'EXP free space: ', #24000 ; -;PAGE 9-11 (#09, #0A, #0B) - INCBIN IMG_RECOVERY,#8000,#C000 - DISPLAY "ROM Disk recovery part2, pages 9..11: #24000..#30000" - ; Set_Block 'Empty space: ', #28000 - ; Set_Block 'Empty space: ', #2C000 - ; Set_Block 'Empty space: ', #30000 +;PAGE 9-11 (#09, #0A, #0B) Recovery image part 2 + INCBIN IMG_RECOVERY,#C000,#C000 + DISPLAY "ROM Disk recovery part2, pages 9..11: 2x4000..3x0000" + Set_Block 'Empty space: ', #30000 ; ;PAGE 12-15 (#0C, #0D, #0E, #0F) INCBIN bitstream diff --git a/src/bios/Test/IDE_BIOS.as b/src/bios/Test/IDE_BIOS.as deleted file mode 100644 index c972595..0000000 --- a/src/bios/Test/IDE_BIOS.as +++ /dev/null @@ -1,346 +0,0 @@ - -;======================================================== -;55H READH LOAD SECTORS -;56H WRITEH SAVE SECTORS -;57H VERIFYH VERIFY SECTORS - -Y_PORT EQU 089H -;Write -HDW_COM EQU 4153H ;1F7H Command -HDW_DRV EQU 4152H ;1F6H Drive Control - -HDW_CLH EQU 0155H ;1F5H Cylinder High -HDW_CLL EQU 0154H ;1F4H Cylinder Low -HDW_SEC EQU 0153H ;1F3H Sector -HDW_CNT EQU 0152H ;1F2H Counter -HDW_ERR EQU 0151H ;1F1H Error -HDW_DAT EQU 0150H ;1F0H Data -;Read -HDR_CTL EQU 4053H ;1F7H Status (Control) -HDR_DRV EQU 4052H ;1F6H Drive Control - -HDR_CLH EQU 0055H ;1F5H Cylinder High -HDR_CLL EQU 0054H ;1F4H Cylinder Low -HDR_SEC EQU 0053H ;1F3H Sector -HDR_CNT EQU 0052H ;1F2H Counter -HDR_ERR EQU 0051H ;1F1H Error -HDR_DAT EQU 0050H ;1F0H Data - -BSY EQU 7 -RDY EQU 6 -DRQ EQU 3 -ERR EQU 0 - -;EQU FOR IY+ -DRVHD_H EQU 0 -SC_PT_H EQU 1 -HEADS_H EQU 2 -CYL_L_H EQU 3 -CYL_H_H EQU 4 -SPCLL_H EQU 5 -SPCLH_H EQU 6 - -IDE0 EQU 0C1C0H -IDE1 EQU 0C1C8H - -;IDE0 DEFB #FF ;DRIVE/HEAD REGISTER ;00 -; DEFB #FF ;SECTORS PER TRACK ;01 -; DEFB #FF ;HEADS ;02 -; DEFB #FF ;CYLINDERS LOW ;03 -; DEFB #FF ;CYLINDERS HIGH ;04 -; DEFB #FF ;SECTOR PER CYLINDER LOW ;05 -; DEFB #FF ;SECTOR PER CYLINDER HIGH ;06 -; DEFB #FF ;RESERVED ;07 - -;IDE1 DEFB #FF ;DRIVE/HEAD REGISTER ;00 -; DEFB #FF ;SECTORS PER TRACK ;01 -; DEFB #FF ;HEADS ;02 -; DEFB #FF ;CYLINDERS LOW ;03 -; DEFB #FF ;CYLINDERS HIGH ;04 -; DEFB #FF ;SECTOR PER CYLINDER LOW ;05 -; DEFB #FF ;SECTOR PER CYLINDER HIGH ;06 -; DEFB #FF ;RESERVED ;07 - -;HL:IX - SECTOR -; DE - ADDRESS -; B - SECTORS - -;READ SECTOR(S) -READH: PUSH IY - EXX - LD C,Y_PORT - IN B,(C) - PUSH BC - LD E,0C0H - OUT (C),E - EXX - CALL RDS000 - EXX - POP BC - OUT (C),B - EXX - POP IY - RET NC - LD A,4 ;NOT READY - RET - -;READ SECTOR(S) -RDS000: AND 1 - LD IY,IDE0 - JR Z,RDS001 - LD IY,IDE1 -RDS001: EXX - LD DE,0C040H - LD BC,HDR_CTL - CALL WAITPRT - EXX - RET C - PUSH DE - CALL PRESET - POP HL - LD BC,HDW_COM - LD A,020H ;READ WITH RETRY - OUT (C),A -;SAVE HL! -RDS002: EXX - LD DE,08908H ;WAIT BUSY=0 & DRQ=1 & ERR=0 - LD BC,HDR_CTL - CALL WAITPRT - EXX - RET C - LD BC,HDR_DAT - INIR - INIR -; - LD A,H - OR L - JR NZ,W44 - LD HL,0C000H -W44 -; - LD BC,HDR_CTL - IN A,(C) - BIT DRQ,A - JR NZ,RDS002 - XOR A - RET - -;HL:IX - SECTOR -; DE - ADDRESS -; B - SECTORS - -;WRITE SECTOR(S) -WRITEH: PUSH IY - EXX - LD C,Y_PORT - IN B,(C) - PUSH BC - LD E,0C0H - OUT (C),E - EXX - CALL WRS000 - EXX - POP BC - OUT (C),B - EXX - POP IY - RET NC - LD A,4 ;NOT READY - RET - -;WRITE SECTOR(S) -WRS000: AND 1 - LD IY,IDE0 - JR Z,WRS001 - LD IY,IDE1 -WRS001: EXX - LD DE,0C040H - LD BC,HDR_CTL - CALL WAITPRT - EXX - RET C - PUSH DE - CALL PRESET - POP HL - LD BC,HDW_COM - LD A,030H ;WRITE WITH RETRY - OUT (C),A -;SAVE HL! -WRS002: EXX - LD DE,08908H ;WAIT BUSY=0 & DRQ=1 & ERR=0 - LD BC,HDR_CTL - CALL WAITPRT - EXX - RET C - LD BC,HDW_DAT - OTIR - OTIR -; - LD A,H - OR L - JR NZ,W33 - LD HL,0C000H -W33: -; - LD BC,HDR_CTL - IN A,(C) - BIT DRQ,A - JR NZ,WRS002 - XOR A - RET - -;HL:IX - SECTOR -; B - SECTORS - -;VERIFY SECTOR(S) -VERIFYH: - PUSH IY - EXX - LD C,Y_PORT - IN B,(C) - PUSH BC - LD E,0C0H - OUT (C),E - EXX - CALL VRS000 - EXX - POP BC - OUT (C),B - EXX - POP IY - RET NC - LD A,4 ;NOT READY - RET - -;VERIFY SECTOR(S) -VRS000: AND 1 - LD IY,IDE0 - JR Z,VRS001 - LD IY,IDE1 -VRS001: EXX - LD DE,0C040H - LD BC,HDR_CTL - CALL WAITPRT - EXX - RET C - PUSH DE - CALL PRESET - POP HL - LD BC,HDW_COM - LD A,040H ;VERIFY WITH RETRY - OUT (C),A -VRS002: LD BC,HDR_CTL - IN A,(C) - BIT ERR,A - JR Z,VRS003 - SCF - RET -VRS003: LD DE,08100H ;WAIT BUSY=0 & ERR=0 - LD BC,HDR_CTL - CALL WAITPRT - RET C - XOR A - RET - -; HL:IX - LBA SECTOR -; B - SECTOR COUNTER - -PRESET: LD A,B - LD BC,HDW_CNT - OUT (C),A - IN A,(0E2H) - EX AF,AF' - LD A,0FEH - OUT (0E2H),A - LD A,(IY+DRVHD_H) - LD BC,HDW_DRV - OUT (C),A - BIT 6,A - LD E,LX - LD D,HX - CALL Z,LBA_CHS - LD BC,HDW_SEC - OUT (C),E ;LBA 0..7 - LD BC,HDW_CLL - OUT (C),D ;LBA 8..15 - LD BC,HDW_CLH - OUT (C),L ;LBA 16..23 - LD BC,HDW_DRV - DEC B - IN A,(C) - AND 0F0H - OR H ;LBA 24..27 - INC B - OUT (C),A - EX AF,AF' - OUT (0E2H),A - AND A - RET - -; HL:DE - SECTOR OFFSET - -LBA_CHS: - LD C,(IY+SPCLL_H) - LD B,(IY+SPCLH_H) -; HL:DE / BC => DE:IX HL-OSTATOK -DIV32X: LD HX,D - LD LX,E - EX DE,HL - LD HL,0 - LD A,020H -DIV011: ADD IX,IX - EX DE,HL - ADC HL,HL - EX DE,HL - ADC HL,HL - SBC HL,BC - JR NC,DIV012 - ADD HL,BC - DEC A - JR NZ,DIV011 - JR DIV014 -DIV012: INC IX - DEC A - JR NZ,DIV011 -DIV014: LD E,(IY+SC_PT_H) - LD D,0 - XOR A -CHS005: INC A - SBC HL,DE - JR NC,CHS005 - ADD HL,DE - DEC A - LD H,A - LD E,L - INC E - LD D,LX - LD A,HX - LD L,A - RET - -; D - MASK -; E - PATTERN -; BC - PORT - -WAITPRT: - LD HL,0000H -WAITP0: IN A,(C) - CP 0FFH - JR Z,WAITP1 - AND D - CP E - JR NZ,WAITP2 - AND A - RET - -WAITP2: DEC HL - LD A,L - OR H - JP NZ,WAITP0 -WAITP1: SCF - RET - -;======================================================= - - - diff --git a/src/bios/backup/EXP.as b/src/bios/backup/EXP.as deleted file mode 100644 index 8e990b8..0000000 --- a/src/bios/backup/EXP.as +++ /dev/null @@ -1,2252 +0,0 @@ - -; -;************************************************************* -; -; EXPANSION VER 3.00 (C) Peters Plus Ltd. -; -;************************************************************* - -;*************************************** -; DEVICE ZXSPECTRUM4096 ; модель с 4 метрами памяти -; MMU 0 e, 0 ; нулевая страница в банку 0 и проверка на границы -; OUTPUT './Build/EXP.BIN' - -;*************************************** - -; ORG 0 -; DISP 0 - -;SPRIN2 EQU 2 ; 1 - включение Sprinter-1 первой прошивкой -; 2 - включение Sprinter-2 первой прошивкой - -; INCLUDE '../shared/SPRINT00.asm' ; константы, макросы.. -; INCLUDE 'EXP_VERSION.inc' - -;KEMPSTON.JOY_DOS EQU 0FFh - -;*************************************** -;*********** BEGIN EXPANSION *********** -;*************************************** -;A_0000: ; Вход по RESET -EXP_START: - JP GLOBAL_RESET -; DB 0,0 - -;--------------------------------------- -ROM_NUMBER: -.part1: DW MotherBoardID ; MotherBoardID -.part2: DB 0 -;--------------------------------------- - -;--------------------------------------- -; BoardID: -; .start: WORD BoardID_start ; BoardID_start -; .end: WORD BoardID_end ; BoardID_end -;--------------------------------------- - -;======================================= - BLOCK 8-$,0 ; first on/off EXPANSION -;программа для вызова BIOS через RST8 из RAM0 -; -EXP_FNS_2_RET: - PUSH AF - LD A,ROM.EXT - OUT (SYS_PORT.OFF),A - POP AF - JR RST_18_1 -;======================================= - -;======================================= - BLOCK #10-$,0 ; DSS ??? -RST_10: -; JR RST10 -;======================================= - -;======================================= - BLOCK #18-$,0 -; RST18h - MAIN BIOS functions -; - JP EXP_FNS_RST18 ; !TEST new_api -RST_18_1: - CALL EXP_FNS_RST18 ; !TEST new_api - JR EXP_FNS_2_RET - -;======================================= - -;======================================= - BLOCK #20-$,0 -RST_20: -;======================================= - -;======================================= - BLOCK #28-$,0 -RST_28: -;======================================= - -;======================================= - BLOCK #30-$,0 -RST_30: -;======================================= - -;======================================= - BLOCK #38-$,0 -; INTERUPT Point -; -RST38: - EI - RETI - -;RST10: -; CALL_48 10h -; RET -;======================================= - -;======================================= - _mInfoBLOCK #66-$,0 - -NMI_Point: - RETN ; резерв 3 байта для команды JP - NOP - -;======================================= - -;SET_BIOS_TO_RAM: ; программа работает на адресе 0C000h -; -; LD SP,0C0C0H -; LD A,0E0H -; LD C,PAGE3 -; IN B,(C) -; CALL SET_ROM_PAGES+0C000H -; JP NO_SUMX_EQ - -;********************************** - -;BEEP: -; PUSH HL -; PUSH DE -; PUSH BC -; PUSH AF -; PUSH IX -; -; LD HL,BEEP_RET -; PUSH HL -; LD HL,SW_ROM -; PUSH HL -; LD HL,03B5h -; PUSH HL -; LD HL,200 -; LD D,H -; LD E,5 -; JP SW_ROM -;BEEP_RET: -; -; POP IX -; POP AF -; POP BC -; POP DE -; POP HL -; RET - -;======================================= - _mInfoALIGN #10,0 -;TABLE_X EQU #A0 ; any adress < #C0 with mask %xxxx0000 -; BLOCK TABLE_X-$ -TABLE_X: ; таблица для Sprinter POST-Tester-a -.v0: DB 00101000b ; "0" -.v1: DB 10111101b ; "1" -.v2: DB 00110010b ; "2" -.v3: DB 00110100b ; "3" -.v4: DB 10100101b ; "4" -.v5: DB 01100100b ; "5" -.v6: DB 01100000b ; "6" -.v7: DB 00111101b ; "7" -.v8: DB 00100000b ; "8" -.v9: DB 00100100b ; "9" -.vA: DB 00100001b ; "A" -.vB: DB 11100000b ; "B" -.vC: DB 01101010b ; "C" -.vD: DB 10110000b ; "D" -.vE: DB 01100010b ; "E" -.vF: DB 01100011b ; "F" -;======================================= - -;======================================= -; BLOCK MEM_MAP.ID_Version-$,0 ;#C0-$,0 -ID_Version: - dw bitstream_ver_hex ; Version of bitstream hex - -ID_SPRINTER_length: - DB ID_SPRINTER.LENGTH - -ID_SPRINTER: - DB 'Hardware v' -.bitstream_ver: - DB bitstream_ver_string,0 - DB 'Sprinter',0 - DB 0 -.LENGTH EQU $-ID_SPRINTER - -; Check for max length of string - ASSERT ID_SPRINTER.LENGTH < #20, 'ERROR! ID String is to long!' -;======================================= - - -; BLOCK #FC-$,0 -BoardID: -.start: WORD BoardID_start ; BoardID_start -.end: WORD BoardID_end ; BoardID_end - -; ;======================================= -; BLOCK #100-$,0 - -RESTARTS EQU #FFE0 ; !FIXIT вынести в SP2000.inc - -GLOBAL_RESET: - DI - IM 1 - LD HL,RESTARTS - LD DE,RESTARTS_PROG - LD B,RESTARTS_PROG.length -.compare: - LD A,(DE) - CP (HL) - JR NZ,NO_RESTART - INC HL - INC DE - DJNZ .compare - JP RESTARTS - -;********************************** -; программа, которая будучи размещенной в #40 странице, -; с адреса RESTARTS, перехватывает RESET -; ; Сделать заготовку с DISP-ENT на будущее !!!!! -RESTARTS_PROG: ; !TODO LDConf перехват ресета на любой конфе после hardreset - LD HL,RESTARTS ; 3 - LD B,16 ; 2 -.loop: - LD (HL),0 ; 2 - INC HL ; 1 - DJNZ .loop ; 2 - NOP ; 1 - NOP ; 1 - ; LD A,1 ; 2 - ; OUT (SLOT3),A ; 2 -; ; = 16 bytes -.length EQU $-RESTARTS_PROG -;********************************** - -;------------[Setup Starter]------------ - MODULE Setup_Starter -; программа, размещаемая по адресу 0C000h -; для запуска Setup -Start: - DISP COMPILE_ADDR.SETUP_STARTER -Exec: - LD A,CNF_0 + ROM.EXPANSION - OUT (SYS_PORT.ON),A - - LD HL,ROM_MAP.SETUP - LD DE,MEM_MAP.SETUP - LD BC,BLOCK_Setup.Length - LDIR - - LD A,CNF_0+ROM.EXT - OUT (SYS_PORT.ON),A - -;-----------[Check SPACE] - LD A,#FE ; !HARDCODE - LD BC,Port_All_Mode ; keyboard int & acc off - OUT (C),A - LD A,high ZXKeys.Line_7 - IN A,(ZXKeys) - CPL - AND 1 -; в регистре A передаётся нажата ли клавиша SPACE. -; потом проверяется в main.asm [space_check] -; и если нажата, то происходит игнор параметра -; "Быстрый старт ПЗУ" во время перезагрузки - EX AF,AF' - - LD A,#FF ; !HARDCODE - OUT (C),A ; keyboard int & acc on, zx_screen & original waits off (for conf >= 3.05) - - EX AF,AF' -;----------------------[] - DI - POP HL ; адрес возврата в EXP из SETUP - LD SP,#8000 ;!HARDCODE - PUSH HL - PUSH AF - JP SETUP_MAIN - ENT -Length EQU $-Setup_Starter.Start - ENDMODULE -;--------------------------------------- - - -;SYSTEM_ID_TXT: -; DB "NEW_BIOS" - - -;-----[перехват RESET не состоялся]----- -; -NO_RESTART: -; стек ещё не используем!!! - LD SP,IX ; сохранить значение переданное загрузчиком конфы (если старт после ресета) - -;*************************************** -; инициализация внутренних -; портов Z84C15 для POST-Tester-а -; - LD A,5 ; COM port for Printer OUT - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,#62 - OUT (Z84.SIO.Ch_A.Ctrl),A - - LD A,#CF ; BITS I/O - OUT (Z84.PIO.Port_A.Command),A - XOR A - OUT (Z84.PIO.Port_A.Command),A - OUT (Z84.PIO.Port_A.Data),A ; PRINTER - PORT - all zeros - -;*************************************** -;-инициализация системных портов Z84C15- -; - LD BC,#FF*256 + Z84.SYS.Control - XOR A - OUT (C),A ; 0 register - waits - INC C - OUT (C),A ; set 0 Waits - - DEC C - - LD A,3 ; 3-rd register - Misc.Control Register - OUT (C),A - INC C - XOR A ; !FIXIT читать доку на Z84, выбрать занчение для A - LD A,1 ; !FIXIT читать доку на Z84, выбрать занчение для A - OUT (C),A ; enable CS0, disable CS1 -; no boundary set! -;********************************** -; - -; - xor a - out (BorderColor),a -; - -; -;********************************** -; ==== POST PROCs ================= - MODULE POST_TEST - -; ********************************* -; ===== Point 0 ======= -; ********************************* - - LD A,(TABLE_X.v0) ; высветить "0" ;rdlow-ok - OUT (Z84.PIO.Port_A.Data),A - -; ==== TEST RAM BUS ======== - -POST_1_RAM_BUS: - LD BC,0 - LD HL,#C000 - LD DE,#0055 - -.loop: - LD (HL),E - INC L - LD (HL),D - DEC L - LD A,(HL) - XOR E - OR C - LD C,A - INC L - LD A,(HL) - XOR D - OR B - LD B,A - DEC L - - DEC E - INC D - JR NZ,.loop - LD A,E - CPL - LD E,A - INC L - INC L - BIT 4,L - JR Z,.loop - - LD A,B - OR C - JR Z,POST_1_OK ; no errors - -; ERROR RAM BUS CODE 'X'X'X'X... - -.error: - LD HL,TABLE_X -.ERB_2: - BIT 0,C - JR Z,.ERB_1 - -; высветить номер ошибочного бита - LD A,(HL) - AND %11011111 ; с запятыми - OUT (Z84.PIO.Port_A.Data),A - -; пауза - LD DE,0 -.pause: - DEC DE - LD A,D - OR E - JR NZ,.pause - -; RRC BC -.ERB_1: - LD A,C - RRA - RR B - RR C - -; бесконечный цикл - INC L - LD A,L - AND #AF - LD L,A - JR .ERB_2 - -; ************************************************ -; ===== Point 1 ============== -; ************************************************ -POST_1_OK: - - LD A,(TABLE_X.v1) ; высветить "1" ;rdlow-ok - OUT (Z84.PIO.Port_A.Data),A - -; ===== TEST ADRESS BUS ====== -POST_2_ADRESS_BUS: - LD HL,#C000 - LD DE,#0000 -.fill_mem: ; заполнить память адресами - LD (HL),E - INC L - LD (HL),D - INC HL - INC DE - INC DE - BIT 7,H - JR NZ,.fill_mem - - DEC HL - DEC DE - DEC DE -.check_mem: ; проверить совпадение - LD A,(HL) - CP D - JR NZ,.error - DEC HL - LD A,(HL) - CP E - JR NZ,.error - DEC HL - DEC DE - DEC DE - LD A,H - CP 0BFh - JR NZ,.check_mem - JR POST_2_OK - -; ошибка адреса CODE: 'XXXX -.error: -.TSAB_4: - LD C,D - LD B,11011111b - LD IX,.TSAB_3 - JR OUT_C_BYTE ; вывести старший байт с запятой -.TSAB_3: - LD C,E - LD B,0FFh - LD IX,.TSAB_4 - JR OUT_C_BYTE ; вывести младший без запятой - -; ===== OUT BYTE PROGRAM ======= - -OUT_C_BYTE: - LD A,C - - RRCA - RRCA - RRCA - RRCA - - AND #0F - OR TABLE_X - LD L,A - LD H,0 - LD A,(HL) - AND B - OUT (Z84.PIO.Port_A.Data),A - - EXX - LD DE,0 -.LOOP_WTT2: - DEC DE - LD A,D - OR E - JR NZ,.LOOP_WTT2 - LD A,#FF - OUT (Z84.PIO.Port_A.Data),A -.LOOP_WTT21: - DEC DE - LD A,D - OR E - JR NZ,.LOOP_WTT21 - EXX - - LD A,C - AND #0F - OR TABLE_X - LD L,A - LD A,(HL) - OUT (Z84.PIO.Port_A.Data),A - - EXX - LD DE,0 -.LOOP_WTT3: - DEC DE - LD A,D - OR E - JR NZ,.LOOP_WTT3 - LD A,#FF - OUT (Z84.PIO.Port_A.Data),A -.LOOP_WTT31: - DEC DE - LD A,D - OR E - JR NZ,.LOOP_WTT31 - EXX - - JP (IX) - -; ************************************************ -; ===== Point 2 ========= -; ************************************************ - -POST_2_OK: - - LD A,(TABLE_X.v2) ;rdlow-ok - OUT (Z84.PIO.Port_A.Data),A ; вывести "2" - -; ===== INIT DCP ======== -POST_3_INIT_DCP: - LD HL,POST_3_OK ; INIT PORTS - JP DCP_INIT ; процедура инициализации с возвратом в (HL) -; ошибок нет - -; *********************************** -; ===== Point 3 ========= -; *********************************** - -POST_3_OK: - LD A,(TABLE_X.v3) ; вывести "3" ;rdlow-ok - OUT (Z84.PIO.Port_A.Data),A - -; ===== TEST RAM PAGES == - - IN A,(SLOT3) - EX AF,AF' ; запомнить - -POST_4_PAGES: - LD B,0 -.loop: - LD A,#FF - LD I,A - LD A,B - OUT (SLOT3),A - LD A,0 - LD I,A - IN A,(SLOT3) - CP B - JR NZ,.error ; если ошибка переключения Port-а - DJNZ .loop - - EX AF,AF' - OUT (SLOT3),A ; восстановить - JR POST_4_OK - -; *********************************** -; ERROR Port CODE 'XX -.error: - LD C,B - LD IX,.error_out_ret -.error_out_ret: - LD B,11011111b - JP OUT_C_BYTE - -; *********************************** -; ===== Point 4 ========= -; *********************************** - -POST_4_OK: - LD A,(TABLE_X.v4) ;rdlow-ok - OUT (Z84.PIO.Port_A.Data),A ; высветить "4" - -;= проверка чистоты шины данных Z84C15 = -POST_5_DATA_BUS: - LD B,0 -.loop: - IN A,(0) - CP #FF -; JR NZ,.error ;!!!!! посмотреть - DJNZ .loop - JR POST_5_OK - -; ERROR CODE '_'XX -.error: - LD C,A -.erb1: - LD IX,.erbr1 - LD B,%11011111 - JP OUT_C_BYTE -.erbr1: - LD A,%11011111 - OUT (Z84.PIO.Port_A.Data),A - - LD DE,0 -.LOOP_WTT4: - DEC DE - LD A,D - OR E - JR NZ,.LOOP_WTT4 - JR .erb1 - -; ********************************** -; ===== Point 5 ========= -; ********************************** - -POST_5_OK: - LD A,(TABLE_X.v5) ;rdlow-ok - OUT (Z84.PIO.Port_A.Data),A ; вывести "5" - -; ********************************** -; POST завершен -; ********************************** - ENDMODULE - - MODULE SET_CONFIG_ID - - IN A,(SLOT3) - EX AF,AF' ; SAVE PAGE3 - -;NO_SUMX_EQ: - - LD A,SYS_PAGE - OUT (SLOT3),A - -;-------------[Save IX:IY]-------------- -; Don't use IY before this point if it`s normal booting!!! - -;NO_NEW_BIOS: - - LD IX,0 - AND A - ADD IX,SP ; восстановить значение переданное загрузчиком конфы (если старт после ресета) -; -; В этом месте у нас IX:IY из Loader.asm -; - -/* -; Дотащили до сюда метку от лоадера -; пока никак не используется - - LD A,IYL - LD L,A - LD A,IYH - LD H,A - - LD BC,#0107 ; !!!!! сравнить с 0107h вынести референсом тут и в loader.asm - AND A ; если равно - прошла перезагрузка - SBC HL,BC - JR Z,set_config -*/ -;--------------------------------------- - LD HL,#FFFD ; !!!!! Sprinter-2 вынести референсом тут и в loader.asm - -set_config: - LD (SYS_PAGE.CONFIG_BYTE),HL ; сохранить номер прошивки -; LD HL,(SYS_PAGE.CONFIG_BYTE) ; взять номер прошивки в HL - - EX AF,AF' - OUT (SLOT3),A ; Restore SLOT3 - - ENDMODULE -;********************************* -; первая инициализация страниц: -; SLOT3=0, SLOT2=2, SLOT1=5, SLOT0=0 - - XOR A - OUT (RGADR),A - OUT (RGMOD),A - OUT (SLOT3),A - OUT (SLOT0),A - LD A,5 - OUT (SLOT1),A - LD A,2 - OUT (SLOT2),A - -;********************************* -; Don't use stack (SP) before this point if it`s normal booting!!! - LD SP,#BFFE ; Начало использования стека!!! - PUSH HL ; сохранить номер прошивки - - CALL PORTS_INIT ; инициализировать порты - CALL EMM.CheckColdInit ; инициализация памяти - - POP HL ; конфигурация - JR Reset_Handler.start -; ************************************* -; Считаем, что вход в SETUP всегда !!! -; ************************************* - -; LD A,H -; CP 0FFH -; JR NZ,NO_SETUP_1 -; LD A,L - -;-----[IF]----- - ; IF SPRIN2 = 2 -; CP 0FDH ; Конфигурация Sprinter-2 -PG_SP1 equ #EC -PG_SP2 equ #EE -PG_AY equ #EA - -; ELSE - -; ; CP #FE ; Конфигурация Sprinter-1 -; PG_SP1 equ #EE -; PG_SP2 equ #EC -; PG_AY equ #EA - -; ENDIF -;-------------- -; JR NZ,NO_SETUP_2 - - MODULE Reset_Handler -start: - IN A,(SLOT3) - push af -;----[перехват soft reset #EE port]----- -Check_EE_Port: - - LD A,Conf_port.RET_PORT - LD B,0 - LD C,BIOS.SET_PORTS - CALL @ToBIOS_3D13 ; переустановить внутр. порт #EE - LD A,B - AND A - jr z,Check_Spec_Page - - DI - OUT (SLOT3),A ; Set restart page - -.After_Hard_Rst: - - LD HL,(#FFF4) ; prog address - ld a,(#FFF0) ; PAGE0 - OUT (SLOT0),A - LD A,(#FFF1) ; PAGE1 - OUT (SLOT1),A - LD A,(#FFF2) ; PAGE2 - OUT (SLOT2),A - LD A,(#FFF3) ; PAGE3 - OUT (SLOT3),A - - jp (HL) -; -;--[перехват soft/hard reset #41 page]-- -Check_Spec_Page: - - LD A,Spec_Page - OUT (SLOT3),A - LD A,(#FFFE) - CP 'Z' - JR NZ,No_Reset_handlers - LD A,(#FFFF) - CP 'X' - JR NZ,No_Reset_handlers - - LD A,(#FFF7) - CP 'R' - JR NZ,Spec_Page_handler_OK - LD A,(#FFF8) - CP 'S' - JR NZ,Spec_Page_handler_OK - LD A,(#FFF9) - CP 'T' - JR NZ,Spec_Page_handler_OK - - XOR A - LD (#FFF7),A - - JR Check_EE_Port.After_Hard_Rst -;--------------------------------------- -No_Reset_handlers: -init_rom_address EQU #8200 ;!HARDCODE - - ld hl,init_zx_roms - ld de,init_rom_address - ld bc,init_zx_roms.length - ldir - - call init_rom_address - - LD HL,#C000 - LD DE,#C001 - LD BC,#3FFF - LD (HL),C - LDIR ; забить FF-ами - - LD HL,PROG_NO_ROM - LD DE,#C000 + #38 - LD BC,PROG_NO_ROM.size - LDIR - - LD HL,RAM_BIOS_PROG - LD DE,#C000 + #08 - LD BC,RAM_BIOS_PROG.Length - LDIR - -Spec_Page_handler_OK: - pop af - OUT (SLOT3),A - - ENDMODULE -;************************************** -; COPY BIOS ТО RAM ???? -;************************************** -; -;************************************** -; - MODULE Prepare_For_Setup - -Set_ALL_Mode: - LD A,#FF - LD BC,Port_All_Mode - OUT (C),A - -Set_Default_Screen: - CALL INT_DEF ; set default int - ld a,128+4 ; !HARDCODE - ld c,#F2 ; !HARDCODE FN_SYNC - RST #18 ; set default vsync - -Setup_to_RAM: - LD HL,Setup_Starter.Start - LD DE,COMPILE_ADDR.SETUP_STARTER - LD BC,Setup_Starter.Length - LDIR - -; на стек кладётся адрес возврата и дальше тащится всякими костылями, чтоб вернуться назад - CALL Setup_Starter.Exec ; #C000 - - JP ZX_SPECTRUM_MODE ; выход в режим zx spectrum - - ENDMODULE -;*********************************** -; Инициализация портов - -PORTS_INIT: - -; включить TURBO - - LD A,D_TBON+CNF_0 - OUT (SYS_PORT.ON),A - -; RESET to ISA - - LD BC,ISA_PORT - LD A,#FF - OUT (C),A -.isa_reset: - DEC A - JR NZ,.isa_reset - OUT (C),A - -; Инициализация последовательного порта клавиатуры - - LD A,0 - OUT (Z84.SIO.Ch_A.Ctrl),A - - LD A,1 - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,0 ; 18H включение прерываний - OUT (Z84.SIO.Ch_A.Ctrl),A - - LD A,3 - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,#C1 - OUT (Z84.SIO.Ch_A.Ctrl),A - - LD A,4 - OUT (Z84.SIO.Ch_A.Ctrl),A -;------------------------------ ;!!!!! посмотреть -; ld a,5 - LD A,7 ; ????? 5/7 паритет? -;------------------------------ ;!!!!! посмотреть - OUT (Z84.SIO.Ch_A.Ctrl),A - - LD A,5 - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,#62 - OUT (Z84.SIO.Ch_A.Ctrl),A - -;--------[Clean keyboard buffer]-------- -.clean_kbd_buf: - IN A,(Z84.SIO.Ch_A.Ctrl) - BIT 0,A - jr z,.mouse - IN A,(Z84.SIO.Ch_A.Data) - jr .clean_kbd_buf -;--------------------------------------- -.mouse: -; Инициализация мыши - - LD A,0 ; for MOUSE - OUT (Z84.SIO.Ch_B.Ctrl),A - - LD A,1 - OUT (Z84.SIO.Ch_B.Ctrl),A - LD A,0 - OUT (Z84.SIO.Ch_B.Ctrl),A - - LD A,3 - OUT (Z84.SIO.Ch_B.Ctrl),A - LD A,#41 - OUT (Z84.SIO.Ch_B.Ctrl),A - - LD A,4 - OUT (Z84.SIO.Ch_B.Ctrl),A - LD A,#44 - OUT (Z84.SIO.Ch_B.Ctrl),A - - LD A,5 - OUT (Z84.SIO.Ch_B.Ctrl),A - LD A,#E0 - OUT (Z84.SIO.Ch_B.Ctrl),A - -; Инициализация таймера мыши - - LD A,85 ; for MOUSE - OUT (Z84.CTC.Ch_0),A - LD A,45 - OUT (Z84.CTC.Ch_0),A - -; Инициализация параллельного порта 1 (принтер) - -; для POST-Tester-а - -; LD A,0CFH ; BITS I/O -; OUT (Z84.PIO.Port_A.Command),A -; XOR A -; OUT (Z84.PIO.Port_A.Command),A ; ALL - out -; OUT (Z84.PIO.Port_A.Data),A ; DATA - all zeros - -; для printer-a - - LD A,#0F ; OUT - OUT (Z84.PIO.Port_A.Command),A - OUT (Z84.PIO.Port_A.Command),A - -; Инициализация параллельного порта 2 (INT/DMA ISA) - - LD BC,Z84.PIO.Port_B.Command - - LD A,#CF ; BITS I/O - OUT (C),A - LD A,#3F - OUT (C),A - LD A,#C0 - OUT (Z84.PIO.Port_B.Data),A - -; "Заглушение" ковокса - - XOR A - OUT (CBL.SYS_PORT),A - LD BC,CBL.OUT - LD A,#80 -.CBL_MUTE: - OUT (C),A - DJNZ .CBL_MUTE - -; Сброс контроллера дисковода - -; Включить доступ к контроллеру диска - - LD A,CNF_3 - OUT (SYS_PORT.ON),A - - OUT (FDC_93.DrvCTRL),A ; !!!!! глянуть - push hl - pop hl - LD A,#3C ; !!!!! глянуть - OUT (FDC_93.DrvCTRL),A ; !!!!! глянуть - push hl - pop hl - XOR A - OUT (FDC_93.Command),A - -; Выключить доступ к контроллеру диска - - LD A,CNF_0 - OUT (SYS_PORT.ON),A - -; set HDD1/not-HDD2 - - LD A,#21 ;!HARDCODE сделать через метку - OUT (#BC),A ;!HARDCODE - -; CALL DOS_OFF - - - LD BC,#7FFD - LD A,#10 - OUT (C),A ; BASIC_48 mode - LD B,#1F - LD A,01 - OUT (C),A ; RAM-0 mode !!! - - RET - -;************************************** - -; -;------------------------[copy zx-roms to zx-pages]---------------------; -; SLOT0 - ROM 8, sys_port - on. -; RAM SLOT0 - page 0 -; для режима zx spectrum -; ВЫПОЛНЯЕТСЯ ИЗ ОЗУ -init_zx_roms: - DISP Reset_Handler.init_rom_address - - in a,(SLOT3) - push af - - DI - LD A,1 - OUT (SYS_PORT.ON),A - ld a,2 - - IF SetFullZXromLoader - ld b,6 ; zx-rom number of pages - ELSE - ld b,4 - ENDIF - -.loop: - push bc - - out (ROM.SLOT0),a - or %01000000 - out (SLOT3),a - and %10111111 - - LD HL,0 - LD DE,#C000 - LD BC,#4000 - LDIR - - inc a - pop bc - DJNZ .loop - - xor a - out (ROM.SLOT0),a - OUT (SYS_PORT.ON),A - POP AF - out (SLOT3),a - - - LD A,#E2 ; ROM-ID - BASIC 128 - LD B,#42 ; page - CALL .SET_ROM - - LD A,#E3 ; ROM-ID - BASIC 48 - LD B,#43 ; page - CALL .SET_ROM - - LD A,#E1 ; ROM-ID - TR-DOS - LD B,#44 ; page - CALL .SET_ROM - - LD A,#E0 ; ROM-ID - EXPANSION - LD B,#45 ; page - CALL .SET_ROM - - - LD A,#EB ; ROM-ID - BIOS-1 - IF SetFullZXromLoader - LD B,#46 ; page - ELSE - LD B,#45 ; page - ENDIF - CALL .SET_ROM - - - IF SetFullZXromLoader - LD A,#EF ; ROM-ID - BIOS-2 - LD B,#47 ; page - CALL .SET_ROM - ENDIF - RET - -.SET_ROM: - LD C,BIOS.SET_PORTS - JP ToBIOS_3D13 - - ENT -.length EQU $-init_zx_roms -;-----------------------------------------------------------------------; -; - - -;************************************** -;************************************** - -GOTO_SPEC: ; ????? процедура биоса для захода в режим спеткрума - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,B - LD (SYS_PAGE.CONFIG_DE+1),A - EX AF,AF' - OUT (SLOT3),A - -;NO_SETUP_2: -; CP #FC -; JR Z,SPECTRUM_0 ; Конфигурация AY - -;NO_SETUP_1: -ZX_SPECTRUM_MODE: -; LD A,(#A8) -; OUT (Z84.PIO.Port_A.Data),A - - LD A,#FE ; !HARDCODE сделать через метку ACC-off Spectrum-MODE - LD BC,Port_All_Mode - OUT (C),A - -;SND_TEST_RET: - LD SP,#BFFF - - CALL INT_PENT - CALL SET_PAL_ZX - - LD HL,#4104 - LD E,0 - LD B,4 - CALL LP_OPEN_S - - LD HL,#5104 - LD E,0 - LD B,4 - CALL LP_OPEN_S - -;************************************* -/* - LD D,#35 - CALL CMOS_RD - BIT 0,A ; !!!!! -*/ -; PUSH AF -; CALL Z,SPRINTER_1 -; POP AF -; PUSH AF -; CALL NZ,AY8910 -; POP AF - -;************************************* - -SPECTRUM_0: - XOR A ; задача 0, режим 256 килобайт -SPECTRUM_TASK: - LD IX,BASIC_128 - JP INIT_PAGES ; инициализация номеров страниц режима спектрума - -BASIC_128: -;start_basic: - LD SP,#BFFF - LD HL,RES128_PROG - LD DE,#5B00 ; запуск программы на BASIC-е. - LD BC,LEN_RES128 - LDIR - DI - JP #5B00 - -;******************************** -; Программа, размещаемая на 5B00h для запуска Spectrum-а - -RES128_PROG: - LD A,ROM.EXT - OUT (SYS_PORT.OFF),A ; Возврат в 128k ROM - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (SLOT3),A - LD DE,(SYS_PAGE.CONFIG_DE) - XOR A - LD (SYS_PAGE.CONFIG_DE+1),A - OUT (C),B - - LD BC,#1FFD - OUT (C),A ; Scorp порт - LD B,#7F - OUT (C),A ; 128 порт - - LD A,E ; установка конфигурации и режима TURBO - OUT (SYS_PORT.OFF),A ; CONFIG_SET - - INC D - DEC D - JP Z,0 ; 0 ВХОД В BASIC-128 - LD A,#10 - OUT (C),A - DEC D - JP Z,0 ; 1 ВХОД В BASIC-48 - - LD HL,0 - PUSH HL - DEC D - JP Z,#3D29 ; 2 ВХОД В TR-DOS - - XOR A - OUT (C),A - LD A,#02 - LD B,#1F - OUT (C),A - DEC D - JP Z,0 ; 3 ВХОД В EXPANSION ??? - - LD A,0 - OUT (C),A - LD A,#30 - LD B,#7F - OUT (C),A - DEC D - JP Z,#3D29 ; 4 ВХОД В TR-DOS с закрытыми 128-ми портами - JP 0 ; 5 ВХОД В BASIC-48 с закрытыми 128-ми портами -LEN_RES128 EQU $-RES128_PROG - -;***************************************************** - -TURBO_OFF: - LD A,D_TBOFF - OUT (SYS_PORT.ON),A - RET - -TURBO_ON: - LD A,D_TBON - OUT (SYS_PORT.ON),A - RET - -JP_HL: JP (HL) - -;*************************************** - -RAM_BIOS_PROG: ; for CALL BIOS in 41h page - PUSH AF - LD A,ROM.EXT - OUT (SYS_PORT.ON),A - POP AF - RET - NOP -.Length EQU $-RAM_BIOS_PROG -; JR RST_18_1 - - -; -; -PROG_NO_ROM: - DISP #38 - - DI - - LD A,#FF - OUT (SLOT3),A - OUT (SLOT2),A - OUT (SLOT1),A - - LD SP,#BF00 - - LD C,BIOS.LP_OPEN_S - LD B,3 - LD E,0 - RST ToBIOS - - LD C,BIOS.LP_CLS_WIN - LD DE,0 - LD HL,#2050 - RST ToBIOS - - LD A,1 - OUT (RGMOD),A ; set scr-2 - - LD HL,MESSAGE_NR - LD DE,#A000 - LD BC,MESSAGE_NR.size - LD A,C - LDIR - - LD HL,#A000 - LD D,0 ; delimiter - LD E,COLORS.FLASH + COLORS.PAPER.RED + COLORS.INC.CYAN - LD B,A - LD C,BIOS.LP_PRINT_LN3 - RST ToBIOS - -1: DI : HALT - JR 1B - -MESSAGE_NR: DZ " Spectrum ROM not installed. Use spectrum.exe Press Ctrl+Alt+Del or RESET" -.size EQU $-MESSAGE_NR - - ENT -PROG_NO_ROM.size EQU $-PROG_NO_ROM -;-------------[new code end]------------ - - -;***************************************************** - - -;CH_2: -; LD A,2 -;C_1601: ; OPEN CHANEL -; CALL_48 1601h -; RET - - -;PRINT_LINE: -; LD A,(HL) -; INC HL -; CP 0FFh -; RET Z -; RST 10H -; JR PRINT_LINE - - -; JP RESET_128 - -;******************************** -; *** UTILITES *** -;******************************** - -;C_0030: ; получить раб обл -; CALL_48X 0030h -; RET -;C_19E8: ; очистить раб обл -; CALL_48X 19E8h -; RET -;C_1655: ; получить пространство -; CALL_48X 1655h -; RET - -;**************************************** -; ******* SERVICE ******* -;**************************************** - -;******************************************************* -; ДЕШИФРАЦИЯ КОМАНДНОЙ СТРОКИ,ПЕРЕДАННОЙ ДЛЯ "EXPANSION" -;******************************************************* - -;COMAND_LINE: -; LD HL,(CH_ADR) -;COMAND_LOOP: -; LD A,(HL) -; INC HL -; CP ":" -; JR Z,COMAND_L1 -; CP 0Dh -; JR NZ,COMAND_LOOP -; RET - -;COMAND_L1: -; LD A,(HL) -; CP 0EAh ; REM !!! -; RET NZ -; INC HL -;COMAND_OK: ; ОБНАРУЖЕНА КОМАНДА ДЛЯ 'expansion' -; LD A,(HL) -; INC HL -; CP ':' -; JP Z,MENU_S1 -; CP 0Dh -; JP Z,MENU_S1 -; CP 'I' -; JR Z,COMAND_ISD -; CP 'i' -; JR Z,COMAND_ISD -; CP 'T' -; JR Z,TASK_SWITCH -; CP 't' -; JR Z,TASK_SWITCH -; DEC HL -; POP BC -; JP BASIC_MENU -;MENU_S1: -; POP BC -; CALL SERVICE -; JP SW_ROM_1 -; -;COMAND_ISD: -; LD A,(HL) -; INC HL -; CP 'S' -; JP Z,COMAND_ISD2 -; CP 's' -; JP Z,COMAND_ISD2 -; RET - -;COMAND_ISD2: -; POP BC -; CALL ISDOS -; JP SW_ROM_1 - - -;TASK_SWITCH: -; -;; *** Сохранить задачу *** -; PUSH IY -; PUSH IX -; PUSH AF -; PUSH BC -; PUSH DE -; PUSH HL - -; EXX -; EX AF,AF' - -; PUSH AF -; PUSH BC -; PUSH DE -; PUSH HL -; -; LD A,R -; PUSH AF -; LD A,I -; PUSH AF -; -; LD A,(HL) -; RLCA -; RLCA -; RLCA -; RLCA -; AND 30H ; новая задача 0..3 -; LD C,A - -; IN A,(SLOT3) -; LD B,A ; 3-я страница текущей задачи -; LD A,SYS_PAGE -; OUT (SLOT3),A -; -; LD IX,TASK_DATA ; данные задач -; LD E,(IX) ; старая задача -; LD D,0 -; ADD IX,DE ; данные текущей задачи -; LD E,16 -; ADD IX,DE ; смещение данных в таблице задач -; -; LD (IX+1),B ; сохранить страницу 3 -; LD HL,0 -; ADD HL,SP -; LD (IX+2),L ; сохранить стек задачи -; LD (IX+3),H -; SET 0,(IX) ; установить флаг сохраненности текущей задачи -; RES 1,(IX) ; установить флаг, что задача покинута - -; LD IX,TASK_DATA -; LD E,C -; LD D,0 -; ADD IX,DE ; новая задача -; LD E,16 -; ADD IX,DE ; смещение данных в таблице задач - -; BIT 1,(IX) -;; JR NZ,TASK_IN_WORK ; задача в работе ??? неверное завершение -; ; сбрасывать или просто возвращаться -; -; BIT 0,(IX) ; была сохранена/нет -; JR NZ,TASK_SET ; задача существует -; -;; задачи не было! -; LD IX,TASK_DATA -; LD A,C ; задача -; LD (IX),A ; установить новую задачу текущей -; -; JP SPECTRUM_TASK ; запустить новую задачу! -; и пока пофиг распределение памяти! - -;TASK_SET: -; -; LD IX,TASK_RESTORE -; LD A,C -; EXX -; JP INIT_PAGES ; переключить все страницы! - -;TASK_RESTORE: -; EXX -; LD A,SYS_PAGE -; OUT (SLOT3),A -; LD A,C -; LD IX,TASK_DATA -; LD (IX),A ; установить новую задачу текущей - -; LD E,A -; LD D,0 -; ADD IX,DE ; новая задача -; LD E,16 -; ADD IX,DE - -; LD L,(IX+2) ; вспомнить стек -; LD H,(IX+3) -; LD SP,HL -; LD A,(IX+1) ; вспомнить третью страницу -; OUT (SLOT3),A - - -; POP AF ; восстановить -; LD I,A -; POP AF -; LD R,A -; POP HL -; POP DE -; POP BC -; POP AF -; EX AF,AF' -; EXX -; POP HL -; POP DE -; POP BC -; POP AF -; POP IX -; POP IY -; ; вернуться в задачу -; -;NO_TASK: -; POP BC -; JP SW_ROM_1 -; -;; 259F - ADRESS BASIC128 - MAIN_MENU - -;********************************************** -; paths from project DIR - INCLUDE 'EXP_HDD.asm' - INCLUDE 'SERVICE.asm' -; INCLUDE 'TEST.ASZ' - INCLUDE 'FLEX.asm' - IFN SET_NEWdcp - INCLUDE './src/bios/old_files/EXP_DCP_UNPACKER.asm' - ENDIF -; INCLUDE 'EXP_SCR.ASZ' - INCLUDE 'EXP_PIC2.asm' - - IFN SET_NEWdcp - INCLUDE 'EXP_FN2.asm' - ELSE - INCLUDE 'EXP_FN.ASM' - INCLUDE 'EXP_FN2.asm' - ENDIF -;********************************************** -; BLOCK DCP_DATA-$,#FF -; -; #-5kb-############################## -; #::::::::::::::::::::::::::::::::::#\ -; #::::: Место данных для DCP :::::::#\ -; #::::::::::::::::::::::::::::::::::#\ -; ####################################\ -; \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ -DCP_DATA: - - IFN SET_NEWdcp - INCBIN './src/bios/old_files/EXP_DCP.LZ' - ELSE - INCLUDE 'EXP_DCP_2.ASM' - ENDIF -;********************************************** - -;********************************************** - ;BLOCK #2800-$,#FF -; -; #-2kb-############################## -; #::::::::::::::::::::::::::::::::::#\ -; #:::: Здесь место для IBM-ZG ::::::#\ -; #::::::::::::::::::::::::::::::::::#\ -; ####################################\ -; \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ -ZG_ADRESS: - INCBIN 'EXP_FONT.FNT' -;********************************************** -; BLOCK #3000-$,#FF - IFN SET_NEWdcp - INCLUDE 'EXP_FN.asm' - ENDIF - INCLUDE 'EXP_LP2.asm' -;********************************************** -FN_SEND_BYTE: - LD E,A ; сохранить байт - CALL SEND_HALF_BYTE ; передать полубайт из Е - RET C ; возврат по ошибке - LD A,E ; сдвинуть байт на 4 бита - RRCA - RRCA - RRCA - RRCA - LD E,A - -SEND_HALF_BYTE: ; передать половину байта _E_!! - LD A,E - OR #F0 ; установить старшие биты LPT дата - OUT (Z84.PIO.Port_A.Data),A - LD BC,0 ; счетчик тайм-аута - -WAIT_SENT_1: - IN A,(KEMPSTON.JOY_DOS) ; проверить бит 4 на 1 при готовности PC - BIT 4,A - JR NZ,CONTINUE_SENT - DEC BC - LD A,B - OR C - JR NZ,WAIT_SENT_1 - XOR A - SCF ; тайм-аут - RET - -CONTINUE_SENT: ; PC - готов - LD A,E - AND #0F ; сбросить старшие биты LPT - - OUT (Z84.PIO.Port_A.Data),A - - LD BC,0 ; счетчик тайм-аута - -WAIT_SENT_2: - IN A,(KEMPSTON.JOY_DOS) ; проверить бит 4 на 0 - сообщение от PC - BIT 4,A - JR Z,CONTINUE_SENT2 - DEC BC - LD A,B - OR C - JR NZ,WAIT_SENT_2 - LD A,E - OR #F0 ; установить старшие биты LPT дата - OUT (Z84.PIO.Port_A.Data),A - XOR A - SCF ; тайм-аут - RET - -CONTINUE_SENT2: ; полубайт передан - LD A,E - OR #F0 ; установить старшие биты LPT дата - OUT (Z84.PIO.Port_A.Data),A - XOR A - RET - -;********************************************** - -FN_RESEIVE_B: ; принять байт в A - - CALL RESEIVE_POLU_BYTE ; принять полубайт - RET C ; возврат по ошибке - RLCA - RLCA - RLCA - RLCA - AND #F0 - LD E,A - CALL RESEIVE_POLU_BYTE ; второй - RET C - AND 0Fh - OR E - RET ; байт принят - -RESEIVE_POLU_BYTE: ; принять половину байта в Е - - LD A,#F0 ; установить старшие биты LPT дата - OUT (Z84.PIO.Port_A.Data),A - LD BC,0 ; счетчик тайм-аута - -WAIT_RES_1: - IN A,(KEMPSTON.JOY_DOS) ; проверить бит 4 на 1 при готовности PC - BIT 4,A - JR NZ,CONTINUE_RES - DEC BC - LD A,B - OR C - JR NZ,WAIT_RES_1 - XOR A - SCF ; тайм-аут - RET - -CONTINUE_RES: ; PC - готов, ждать 0 - XOR A ; сбросить старшие биты LPT - ждем полубайт - OUT (Z84.PIO.Port_A.Data),A - - LD BC,0 ; счетчик тайм-аута - -WAIT_RES_2: - IN A,(KEMPSTON.JOY_DOS) ; проверить бит 4 на 0 - сообщение от PC - BIT 4,A - JR Z,CONTINUE_RES2 - DEC BC - LD A,B - OR C - JR NZ,WAIT_RES_2 - LD A,#F0 ; установить старшие биты LPT дата - OUT (Z84.PIO.Port_A.Data),A - SCF - RET ; ошибка - -CONTINUE_RES2: ; полубайт выставлен -LOOP_EQ: ; прочитать еще раз, что бы совпало - AND #0F - LD B,A - IN A,(KEMPSTON.JOY_DOS) - AND #0F - CP B - JR NZ,LOOP_EQ - - OR #F0 ; установить старшие биты LPT дата в 1 - принято - OUT (Z84.PIO.Port_A.Data),A - RET - -;*************************************** -;!!!!! посмотреть -; BLOCK #3CC0-$,255 - ; no-magics! -;MAGIC_1: ; ЗАГЛУШКА ДЛЯ MAGIC -; PUSH AF -; LD A,ROM.EXT -; OUT (SYS_PORT.OFF),A -; POP AF -; JP MAGIC_1 -;MAGIC_3: -; PUSH AF -; LD A,ROM.EXT -; OUT (SYS_PORT.OFF),A -; POP AF -; RETN -;MAGIC_2: -;; CALL MG_BEGIN -; JR MAGIC_3 - -;************************* -; BLOCK #3CE0-$,0 -;SW_ROM_1: -; LD HL,259Fh -; PUSH HL -; LD HL,5B00h -; LD A,(HL) -; CP #F5 -; JR Z,JP_HL_48 ; ВОЗВРАТ К МЕНЮ BASIC128 -; POP HL -; JR SW_ROM ; ПРОСТОЙ ВОЗВРАТ -;************************* - -; BLOCK #3CF0-$,0 -;JMP_48: -; LD HL,00h -; JR JP_HL_48 -; -; NOP -; NOP -; NOP - -;*************************************** -; BLOCK #3CF8-$,0 - ; no basic-48! -;JP_HL_48: -; PUSH HL -;SW_ROM: -; PUSH AF -; LD A,ROM.EXT -; OUT (SYS_PORT.OFF),A -; POP AF -; RET -;*************************************** - _mInfoBLOCK #3D00-$,#FF -DOS_ON: NOP - RET -;*************************************** - -;*************************************** -; BLOCK #3D02-$,FF -; !TODO можно оприходовать тут 17 байтов -; -;*************************************** - -;*************************************** - _mInfoBLOCK #3D13-$,#FF - - NOP - JP #18 -;*************************************** - -;*************************************** -; BLOCK #3D17-$,FF -; !TODO можно оприходовать тут 233 байта -; -;*************************************** - -;*************************************** - _mInfoBLOCK #3E00-$,#FF -DOS_OFF: - DI - PUSH AF - PUSH BC - LD BC,(#5BFF) ; !HARDCODE - LD A,#C9 - LD (#5BFF),A ; !HARDCODE - CALL #5BFF ; !HARDCODE - LD (#5BFF),BC ; !HARDCODE - POP BC - POP AF - RET -;*************************************** - -;*************************************** -;START_HDD: -; -; LD C,2 -; CALL EXP_HDD -; RET C -; -; LD A,0 -; OUT (0FEH),A -; -; LD HL,4000H -; LD DE,4001H -; LD BC,1AFFH -; LD (HL),0 -; LDIR -; -; LD HL,0 -; LD IX,LP_SCR_80 -; CALL WIN_OPEN_WIN -; -; LD HL,#2050 -; LD DE,0 -; LD B,07H -; CALL LP_CLS_WIN -; -; LD DE,0 -; CALL LP_SET_PLACE -; -; LD HL,ID_SPRINTER -; LD E,47H -; LD B,L_ID -; CALL LP_PRINT_LINE -; -; LD C,0 -; CALL EXP_HDD -; RET C -; -; LD DE,1 -; LD IX,0 -; LD B,16 -; LD HL,8000H -; LD C,5 -; CALL EXP_HDD -; RET C -; LD HL,8000H -; LD DE,HDD_MSG -; LD B,HDD_MSG_LEN -;START_HDD_L: -; LD A,(DE) -; CP (HL) -; JR NZ,NO_BOOT -; INC HL -; INC DE -; DJNZ START_HDD_L -; JP (HL) -;NO_BOOT: -; RET -; - -;HDD_MSG: DB "Starting...",0 -; -;HDD_MSG_LEN EQU $-HDD_MSG -; -;HDD_MSG_NO: DB "Boot record not found" -;HDD_NO_LEN EQU $-HDD_MSG_NO - -;SAVE_AUTOSTART: -; LD HL,8000H -; LD DE,HDD_MSG -; LD B,HDD_MSG_LEN -;SAVE_AUTO_L1: -; LD A,(DE) -; CP (HL) -; RET NZ -; INC HL -; INC DE -; DJNZ SAVE_AUTO_L1 -; -; LD C,0 -; CALL EXP_HDD -; RET C -; -; LD HL,8000H -; LD A,0 -; LD DE,1 -; LD IX,0 -; LD B,16 -; LD C,6 -; CALL EXP_HDD -; RET -;*************************************** - -;*************************************** -; BLOCK #3E16-$,FF -; !TODO можно оприходовать тут 10 байтов -; -;*************************************** - -;*************************************** -;------[ ; !TODO что- то связанное с переменными LIB_TABLE ; ]------ -; _mInfoBLOCK #3E20-$,#FF - -FN_LIB: - SCF - RET -/* - - IN A,(SLOT3) - LD B,A - LD A,SYS_PAGE - OUT (SLOT3),A - PUSH HL - LD L,C - дешефратор API изменился и теперь в C не то, что тут ожидается. Ожидается #A0..AF - LD H,#C1 - LD A,(HL) - POP HL - AND A - SCF - JR Z,FN_LIB_RET - - OUT (SLOT3),A - LD (#C0FE),SP - LD SP,#C0F0 - PUSH BC - CALL #C100 ; !HARDCODE - POP BC - LD SP,(#C0FE) - ; LD A,B - ; OUT (SLOT3),A - ; RET - -FN_LIB_RET: - LD A,B - OUT (SLOT3),A -; SCF - RET -*/ -;---------------------------------------------------------------[]------ - -FN_KBD_OUT: ; вход A - byte -; B - speed_parameter - - AND A - LD E,A - LD D,#FF - JP PE,kbd_parity ; установка паритета PE/PO ??? - LD D,#FE -kbd_parity: - AND A ; первый бит - start-bit - 0 - RL E - RL D ; в DE - 11 бит для передачи - LD C,11 - -kbd_loop: - LD A,5 - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,#60 - BIT 0,E - JR NZ,no_inv - XOR 2 ; данные -no_inv: - LD L,A - OUT (Z84.SIO.Ch_A.Ctrl),A ; выставить данные - - LD A,5 - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,L - OR #80 ; синхроимпульс - OUT (Z84.SIO.Ch_A.Ctrl),A ; импульс синхро - LD A,B ; speed_par -kbd_loop1: - PUSH HL - POP HL - DEC A - JR NZ,kbd_loop1 - LD A,5 - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,L - OUT (Z84.SIO.Ch_A.Ctrl),A ; снять импульс синхро - - LD A,B ; speed_par -kbd_loop2: - PUSH HL - POP HL - DEC A - JR NZ,kbd_loop2 - RR D - RR E - DEC C - JR NZ,kbd_loop - - LD A,5 - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,#60 - OUT (Z84.SIO.Ch_A.Ctrl),A ; закончить передачу - AND A - RET -;**************************************** - - -; Чтение с ROM-Disk -; HL - адрес, куда читать -; DE - номер сектора (считать по 256b сектор) -; B - число секторов -; A' - размер сектора (1 - 256b, 2 - 512 b) -ROM_DISK: - LD C,0 ; счетчик - EX AF,AF' - DEC A - JR Z,.loop - DEC A - SCF - RET NZ - - EX DE,HL - ADD HL,HL - EX DE,HL - LD A,B - ADD A,A - LD B,A - RET C - - CALL .loop - RET C - AND A - RR D - RR E - XOR A - RET - -/* -; ????? какой-то глюк недоделанный -READ_ROM_PAGE_X: - LD DE,0 - LD BC,#100 ; один сектор - PUSH DE - PUSH BC - LD HL,ROM_DISK_PGS - LD DE,#FF00 ; !HARDCODE - LD A,#1F ; last page ROM - JR LOOP_NEXT -*/ - -.loop: - PUSH DE ; номер сектора - PUSH BC - - LD A,E - AND 63 ; ADRESS in ROM-Page - PUSH AF ; сохранить адрес - - EX DE,HL ; DE - адрес буфера - ADD HL,HL - ADD HL,HL ; H - номер банки - - LD A,(ROM_DISK.Pages.Number) - INC H - CP H - LD L,H - LD H, high ROM_DISK.Pages.Number ; ROM-Disk pages! - LD A,(HL) ; PAGE-ROM - - POP HL ; восстановить адрес в ROM-Page - LD L,0 ; если далеко захотели - выход с ошибкой - JR C,.errorExit ; ROM-Disk-end - -; DE - буфер -; HL - адрес в ROM -; B - число секторов -; A - ROM-Page -.loopRead: - DI - PUSH HL ; откуда - PUSH DE ; куда - - LD HL,-.stackDepth - .readProcedure.size ; memory stack use! - ADD HL,SP ; stack - - PUSH HL ; адрес программы .readProcedure - - LD DE,.readProcedure ; перенести программу на стек - EX DE,HL - LD BC,.readProcedure.size - LDIR ; программа на стеке - LD BC,#100 ; длина сектора - RET ; исполнить программу .readProcedure, на стеке адреса буфера и ROM - - -; DE - next address -; HL - ROM address -.readNext: - POP BC ; число секторое - - INC C ; счетчик считанных секторов - DEC B ; сектора кончились? - - JR Z,.normExit - BIT 6,H ; чтение не закончено - - PUSH BC ; сохранить счетчики - JR Z,.loopRead ; читать дальше - POP BC - - POP HL ; номер сектора - - LD A,B - LD B,0 - ADD HL,BC - LD B,A ; вычислить след.сектор - - EX DE,HL ; теперь HL - адрес, DE сектор, B - сколько еще читать - - JP .loop ; начать все снова! - -; чтение закончено -.normExit: - POP HL ; сектор, откуда велось чтение - ADD HL,BC ; по возврату: HL - след.адрес - EX DE,HL ; DE - след.сектор - AND A - RET -; ошибка -.errorExit: ; !TODO сделать, чтоб на выходе показывалось количество прочитанных секторов - POP BC - POP DE - SCF - RET - -; процедура, переносимая на стек для чтения из ROM-Disk -; осторожнее с PUSH, если надо много, то увеличивай .stackDepth -.readProcedure: - POP DE ; куда - POP HL ; откуда - OUT (ROM.SLOT0),A ; ROM_PAGE - LDIR ; здесь читается из ROM-Disk - LD B,A - XOR A - OUT (ROM.SLOT0),A - OUT (SYS_PORT.ON),A - LD A,B - JP .readNext -.stackDepth EQU 8 ; расстояние от конца процедуры до вершины стека. -.readProcedure.size EQU $-.readProcedure -;-----------------------------------------------------------------------; -; - -;-----------------------------------------------------------------------; -; ROM-Disk pages ; [ ] активировать ROM-DISK - _mInfoALIGN 256,#FF -; BLOCK #3F00-$,#FF -ROM_DISK.Pages.Number: - DB ROM_DISK.Pages.Size ; число страниц -; у страниц выставлен bit4 для корректной подстановки -;(подробнее в sp2000.inc - Порт управления страницами ПЗУ) -ROM_DISK.Pages: ; страницы ROM-Disk -; ABYTE #10 #01,#02,#03,#04,#05,#06,#07,#09,#0A,#0B ; 163840 bytes - without ZX-ROMS - IFN SetFullZXromLoader - ABYTE #10 #06,#07,#09,#0A,#0B ; 81920 bytes - - ELSE - ABYTE #10 #09,#0A,#0B ; 49152 bytes - - ENDIF - -.Size EQU $-ROM_DISK.Pages -; конец - FF -; DB #FF -;-----------------------------------------------------------------------; - -; - _mInfoBLOCK ToBIOS_FromEXT-$,#FF -;------------[Return to ROM]------------ -; #3FD0 -; Для вызова функций биоса из страницы 0 ПЗУ (ROM Extension) -FN1_RET: - PUSH AF - LD A,ROM.EXPANSION - OUT (SYS_PORT.ON),A - POP AF - RST #18 - JR FN1_RET - -; !TODO Free 7 bytes -;--------------------------------------- -; - - -; - _mInfoBLOCK #3FE0-$,#FF -;---------------[ Free ]---------------- -; !TODO Free 8 bytes and entry point -;SOUND_TEST: -; LD A,ROM.EXPANSION -; OUT (SYS_PORT.ON),A -; JP SND_TEST_RET -;--------------------------------------- -; - -;!TEST не нужно если new_api_table -;------------[HDD_5x portal]------------ -; точка входа/выхода для функций 5х из EXP - _mInfoBLOCK #3FE8-$,#FF -EXP_HDD: ;HDD_EXE: - PUSH AF - LD A,ROM.EXPANSION - OUT (SYS_PORT.ON),A - POP AF - RET -;--------------------------------------- -; - - -; - _mInfoBLOCK #3FF0-$,#FF -;---------------[ Free ]---------------- -; !TODO Free 8 bytes and entry point -;--------------------------------------- -; - - -; - _mInfoBLOCK #3FF8-$,#FF -;-----[ From TR-DOS to API #80..#FF]----- -; Точка входа/выхода для TR-DOS -EXP_FNS_RET: - PUSH AF - LD A,ROM.EXT - OUT (SYS_PORT.OFF),A ; Точка входа/выхода из/в TR-DOS при вызове функций BIOS #80..#FF - JP EXP_FNS ; !TEST new_api -;--------------------------------------- -; - -; - _mInfoBLOCK #4000-$,#FF -;======================================================================= diff --git a/src/bios/backup/EXP_FN.as b/src/bios/backup/EXP_FN.as deleted file mode 100644 index 1ba734b..0000000 --- a/src/bios/backup/EXP_FN.as +++ /dev/null @@ -1,841 +0,0 @@ -; - _mInfoALIGN 256,0 -TAB_FNS: ; !FIXIT поправить в доке названия функций, часть не совпадает -; 8x -/* 80 */ DW LP_OPEN_S ; открытие окна -/* 81 */ DW LP_PRINT_ALL ; печать символа в окно -/* 82 */ DW LP_PRINT_SYM ; печать символа без атр -/* 83 */ DW LP_PRINT_ATR ; печать только атрибута -/* 84 */ DW LP_SET_PLACE ; установка позиции печати -/* 85 */ DW LP_PRINT_LINE ; печать строки длиной B -/* 86 */ DW LP_PRINT_LINE2 ; печать строки -//- без атрибутов -/* 87 */ DW LP_PRINT_LINE3 ; печать строки длиной B до D -/* 88 */ DW LP_PRINT_LINE4 ; печать строки -//- без атрибутов -/* 89 */ DW LP_CLS_WIN -/* 8A */ DW LP_SCROLL_UD -/* 8B */ DW LP_PRINT_LINE5 -/* 8C */ DW LP_PRINT_LINE6 -/* 8D */ DW LP_CLS_WIN2 -/* 8E */ DW LP_GET_PLACE -/* 8F */ DW FN_TURBO -; 9x -/* 90 */ DW EMM.GetMemSize ; неразрушающее определение объема ОЗУ. -/* 91 */ DW EMM.InitMem ; инициализация распределения памяти -/* 92 */ DW EMM.GetMemRMD ; получить блок памяти для рамдиска -/* 93 */ DW EMM.FreeMemRMD ; освободить блок памяти рамдиска -/* 94 */ DW EMM.GetMemPageRMD ; получить номерa страниц RAM-Disk -/* 95 */ DW EMM.GetMemPageNext ; получить следующую страницу -/* 96 */ DW EMM.GetBanksPorts ; получить адреса портов -/* 97 */ DW EMM.CheckColdInit ; проверка на холодный старт и инициализации если он ;????? нужна ли как API? -/* 98 */ DW RAMD_CALC_PAGE ; Fn 98h ;????? -/* 99 */ DW SET_DISK_TYPE ; ;????? -/* 9A */ DW DISK_REDIR ; ;????? -/* 9B */ DW FN_NO ;GET_RAMD_NUM ; получить номер ram disk по его block id -/* 9C */ DW FN_NO ; -/* 9D */ DW EMM.DivMemBlocks ; разделения блока на два. -/* 9E */ DW EMM.MergeMemBlocks ; слияние двух блоков -/* 9F */ DW EMM.FullInit ; инициализация всей памяти, системных переменных -; Ax -/* A0 */ DW PIC_FN0 ; ОТКРЫТИЕ ОКНА - Fn 0A0h -/* A1 */ DW PIC_FN1 ; ВЫВЕСТИ ТОЧКУ -/* A2 */ DW PIC_FN2 ; ВЫВОД ЛИНИИ COPY -/* A3 */ DW PIC_FN3 ; ВЫВОД ЛИНИИ FILL -/* A4 */ DW PIC_FN4 ; ВЫВОД ПАЛИТРЫ -/* A5 */ DW PIC_FN5 ; УСТАНОВКА RGMOD -/* A6 */ DW PIC_FN6 ; A - page_pal, E - номер палитры, B - тип палитры -/* A7 */ DW PIC_FN7 ; Рисование линии одного цвета -/* A8 */ DW PIC_FN8 ; Рисование разноцветной линии -/* A9 */ DW PIC_FN9 ; нет -/* AA */ DW PIC_FN10 ; нет -/* AB */ DW PIC_FN11 ; нет -/* AC */ DW PIC_FN12 ; нет -/* AD */ DW PIC_FN14 ; нет -/* AE */ DW PIC_FN14 ; нет -/* AF */ DW PIC_FN15 ; нет -; Bx -/* B0 */ DW WIN_OPEN ; открытие окна по описателю -/* B1 */ DW WIN_CLOSE ; закрытие окна -/* B2 */ DW WIN_COPY ; сохранение текстового окна в памяти -/* B3 */ DW WIN_RESTORE ; восстановление текстового окна из памяти -/* B4 */ DW WIN_GET_SYM ; взять символ -/* B5 */ DW WIN_PUT_SYM ; положить символ -/* B6 */ DW WIN_SET_ZG ; загрузка знакогенератора -/* B7 */ DW WIN_MOVE ; переместить окно -/* B8 */ DW WIN_GET_ZG ; получить знакогенератор -/* B9 */ DW FN_NO -/* BA */ DW FN_NO -/* BB */ DW FN_NO -/* BC */ DW FN_NO -/* BD */ DW FN_NO -/* BE */ DW FN_NO -/* BF */ DW FN_NO -; Cx -/* C0 */ DW EMM.GetMemSize ; получить данные об объеме памяти и кол-во своб. стр. -/* C1 */ DW EMM.InitMem ; инициализация распределения памяти -/* C2 */ DW EMM.GetMem ; получить блок памяти -/* C3 */ DW EMM.FreeMem ; освободить блок памяти -/* C4 */ DW EMM.GetMemPage ; получить номер страницы в блоке памяти -/* C5 */ DW EMM.GetMemBlkPages ; получить список страниц блока памяти -/* C6 */ DW EMM.GetBanksPorts ; получить адреса портов окон -/* C7 */ DW EMM.GetMemPageNext ; получить следующую страницу блока -/* C8 */ DW BLK_RD_WR ; функция чтения/записи в блок памяти -/* C9 */ DW BLK_TO_RAMD ; назначить блок RAM-Disk-у -/* CA */ DW RAMD_CLEAR ; освободить RAM-Disk -/* CB */ DW RAMD_TO_DRV ; назначить RAM-Disk на дисковод -/* CC */ DW FDD_TO_DRV ; назначить REAL_DRIVE на дисковод -/* CD */ DW HDD_TO_DRV ; назначить HDD на дисковод -/* CE */ DW GET_RAMD_ST ; получить тип назначения на RAM-Disk -/* CF */ DW GET_DRV_ST ; получить тип назначения на дисковод -; Dx -/* D0 */ DW FN_LIB -/* D1 */ DW FN_LIB -/* D2 */ DW FN_LIB -/* D3 */ DW FN_LIB -/* D4 */ DW FN_LIB -/* D5 */ DW FN_LIB -/* D6 */ DW FN_LIB -/* D7 */ DW FN_LIB -/* D8 */ DW FN_LIB -/* D9 */ DW FN_LIB -/* DA */ DW FN_LIB -/* DB */ DW FN_LIB -/* DC */ DW FN_LIB -/* DD */ DW FN_LIB -/* DE */ DW FN_LIB -/* DF */ DW FN_LIB -; Ex -/* E0 */ DW LP_PRINT_LINE_DIR -/* E1 */ DW FN_NO -/* E2 */ DW FN_NO -/* E3 */ DW FN_NO -/* E4 */ DW FN_NO -/* E5 */ DW FN_NO -/* E6 */ DW FN_NO -/* E7 */ DW FN_NO -/* E8 */ DW FN_SEND_BYTE ; послать байт через PC_link -/* E9 */ DW FN_RESEIVE_B ; принять байт через PC_link -/* EA */ DW FN_KBD_OUT ; послать байт в клавиатуру -/* EB */ DW FN_NO -/* EC */ DW FN_NO -/* ED */ DW FN_CRIPT -/* EE */ DW AY8910 -/* EF */ DW FN_VERSION -; Fx -/* F0 */ DW SPRINTER_1 -/* F1 */ DW SPRINTER_2 -/* F2 */ DW FN_SINC -/* F3 */ DW SPRINTER_ALL -/* F4 */ DW DCP_FN0 -/* F5 */ DW CMOS_TEST -/* F6 */ DW CMOS_RD -/* F7 */ DW CMOS_WR -/* F8 */ DW SET_ROM_PAGES -/* F9 */ DW READ_PORTS ; !TODO -/* FA */ DW WRITE_PORTS ; !TODO -/* FB */ DW GOTO_SPEC ; Goto Spectrum! -/* FC */ DW FN_NO -/* FD */ DW FN_RESET -/* FE */ DW FN_NO ; SAVE_AUTOSTART -/* FF */ DW FN_VERSION - -EXP_FNS: ; Вход в функцию из DOS - POP AF - CALL APIfrom80toFF ; !TEST new_api - CALL DOS_ON - JP EXP_FNS_RET - -;************************************ -; Вход в функцию по RST18 и RST8 -EXP_FNS_RST18: - BIT 7,C - JR NZ,APIfrom80toFF ; !TEST new_api - ;.APIfrom40to5F: - BIT 6,C - RES 6,C - JP NZ,EXP_HDD_NEW - SCF - RET -;********************************** - -;----------------------------------------------------------------------- -FN_CRIPT: - DEC B - SCF - RET NZ - LD HL,(ROM_NUMBER.part1) ;rdlow-ok - LD A,(ROM_NUMBER.part2) ;rdlow-ok - LD BC,(BoardID.start) ;rdlow-ok - LD DE,(BoardID.end) ;rdlow-ok - AND A - RET -; BoardID_start old address #312A -; BoardID_end old address #312D -;----------------------------------------------------------------------- - -;********************************** -;!!!!! глянуть -; START_DI: -; PUSH AF -; LD A,R -; JP PE,XX_DI -; LD A,R -; XX_DI: LD A,#80 -; JP PE,XX_DI2 -; XOR A -; XX_DI2: LD R,A -; DI -; POP AF -; RET - -; END_DI: PUSH AF -; LD A,R -; BIT 7,A -; JR Z,XX_DI3 -; EI -; POP AF ; PE -; RET - -; XX_DI3: DI -; POP AF ; PO -; RET -;********************************** - - -APIfrom80toFF: - PUSH HL - LD L,C - SLA L - LD H,high TAB_FNS - LD C,(HL) // LD A,(HL) - INC L - LD H,(HL) - LD L,C // LD L,A - EX (SP),HL - RET - -;! ! ! ! ! ! ! ! -; !TODO сделать -READ_PORTS: -WRITE_PORTS: -FN_NO: SCF - RET -;! ! ! ! ! ! ! ! - -; ????? может переделать вход? -; CALL from 3D13h! -; in A - page, B - new ROM-page -; out B - old ROM-page -SET_ROM_PAGES: - EX AF,AF' - LD A,CNF_0 - OUT (SYS_PORT.ON),A - - LD C,SLOT2 ; получить страницу - IN D,(C) - - LD A,DCP_PAGE ; установить новую - OUT (C),A - - LD A,(#8000) ; сохранить то что было - LD L,A - LD A,(#8200) - LD H,A - EX AF,AF' ; страница - - LD (#8000),A ; установить порт ROM TR-DOS - LD (#8200),A - - EX AF,AF' - LD A,B - LD BC,0 - EX AF,AF' - - IN A,(C) - - EX AF,AF' - OUT (C),A ; установить новый TR-DOS - EX AF,AF' - - LD B,A - LD A,L - LD (#8000),A ; вернуть порт - LD A,H - LD (#8200),A ; вернуть порт - - LD C,SLOT2 - LD A,SYS_PAGE - OUT (C),A - LD A,(SYS_PAGE.CONFIG_DE-#4000) - OUT (C),D ; вернуть страницу - OUT (SYS_PORT.ON),A - - AND A - RET -;TAB_SIZE EQU $-TAB_FNS - -;***************************************** - -;***************************************** -; Функция дешифратора портов. -; HL - адрес -; DE - маска - 0 изменяемые биты, 1 неизменяемые -; B - порт -; -; ALL STACKS, DI -;***************************************** -DCP_FN0: ; !FIXIT запоминать тут состояние прерываний и вырубать - AND A - JP Z,PORTS_INIT - - PUSH IX - LD IX,.RET_DCP_FN0 - - IN A,(SLOT3) - EX AF,AF' - LD A,DCP_PAGE - OUT (SLOT3),A - - JR DCP_FN0M - -.RET_DCP_FN0: - EX AF,AF' - OUT (SLOT3),A - AND A - POP IX -; !FIXIT восстанавливать прерывания - RET - -;-----------------------------------------------------------------------; -; Функция дешифратора портов. -; HL - адрес -; DE - маска - 0 изменяемые биты, 1 неизменяемые -; B - порт -DCP_FN0M: - LD A,L - AND E - LD L,A - - LD A,H - AND D -; AND #3F - OR #C0 - LD H,A - - LD A,D - OR #C0 - LD D,A - -.loop: LD (HL),B - - LD A,L ; замаскировать неизменяемые биты 1-ми - OR E ; для прохождения переноса - INC A ; увеличить адрес - JR Z,.carry ; возник перенос - - OR E - XOR E ; обнулить неизменяемые биты - LD C,A ; изменяемая часть - - LD A,L - AND E ; выделить неизменяемую - OR C - LD L,A ; добавить изменяемую часть - - JR .loop ; цикл - -.carry: ; A = 0 -; OR E -; XOR E -; LD C,A - LD A,L ; забить изменяемые биты нулями - AND E -; OR C - LD L,A - - LD A,H ; замаскировать неизменяемые биты 1-ми - OR D ; для прохождения переноса - INC A ; увеличить адрес - JR Z,.exit - - OR D - XOR D - LD C,A ; изменяемая часть - - LD A,H - AND D ; выделить неизменяемую - OR C - LD H,A ; добавить изменяемую часть - JR .loop - -.exit: JP (IX) -;-----------------------------------------------------------------------; - - -; RAM-Disk A, BLK - B -BLK_TO_RAMD: - CP SYS_PAGE.RAMD_KEYS.NUM - CCF - RET C - - PUSH HL - LD L,A - - IN A,(SLOT2) - LD C,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD A,L - LD HL,SYS_PAGE.RAMD_KEYS-#4000 - ADD A,L - LD L,A - LD A,(HL) ; ключ блока - AND A - JR NZ,BLK_BUSY ; RAM-Disk занят - ошибка - LD (HL),B - - LD A,C - OUT (SLOT2),A - - LD A,B - AND A - POP HL - RET - -BLK_BUSY: - LD A,C - OUT (SLOT2),A - - SCF - POP HL - RET - -; RAM-Disk A -RAMD_CLEAR: - CP SYS_PAGE.RAMD_KEYS.NUM - CCF - RET C - - PUSH HL - LD L,A - - IN A,(SLOT2) - LD C,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD A,L - LD HL,SYS_PAGE.RAMD_KEYS-#4000 ; RAM-Disk свободен - ADD A,L - LD L,A - LD B,A ; запомнить удаляемый рамдиск - LD A,(HL) - AND A - JR Z,BLK_BUSY ; возврат с ошибкой - LD (HL),0 - LD A,C - OUT (SLOT2),A - - AND A - POP HL - RET - -; RAM-Disk A, DRV - B -RAMD_TO_DRV: - CP SYS_PAGE.RAMD_KEYS.NUM - CCF - RET C - LD C,A - LD A,B - CP 4 - CCF - RET C - - LD HL,SYS_PAGE.DISK_TYPE-#4000 - LD L,B - - IN A,(SLOT2) - LD B,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD A,C - ADD A,4 - LD (HL),A - LD A,B - OUT (SLOT2),A - AND A - RET - -; Disk A, DRV - B -FDD_TO_DRV: - CP 4 - CCF - RET C - LD C,A - - LD A,B - CP 4 - CCF - RET C - - LD HL,SYS_PAGE.DISK_TYPE-#4000 - LD L,B - - IN A,(SLOT2) - LD B,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD (HL),C - LD A,B - OUT (SLOT2),A - - AND A - RET - -; HDD A, DRV - B -HDD_TO_DRV: - AND 0FH - LD C,A - LD A,B - CP 4 - CCF - RET C - - LD HL,SYS_PAGE.DISK_TYPE-#4000 - LD L,B - - IN A,(SLOT2) - LD B,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD A,C - ADD A,40H - LD (HL),A - LD A,B - OUT (SLOT2),A - - AND A - RET - -; Вход: -; A - RAM Disk ID -; Выход: -; A - Number (0..15) -; GET_RAMD_NUM: -; EX AF,AF' -; IN A,(SLOT2) -; EX AF,AF' -; LD BC,SYS_PAGE * 256 + SLOT2 -; OUT (C),B - -; LD HL,SYS_PAGE.RAMD_KEYS-#4000 -; LD BC,SYS_PAGE.RAMD_KEYS.NUM -; CPIR - -; EX AF,AF' -; OUT (SLOT2),A -; EX AF,AF' - -; SCF -; RET PE - -; DEC L -; LD A,L -; SUB low SYS_PAGE.RAMD_KEYS -; RET - -; на выходе при А = 0 должен быть установлен флаг Z -GET_RAMD_ST: ; DSS надеется, что эта функция не грохает DE - CP SYS_PAGE.RAMD_KEYS.NUM - CCF - RET C - - PUSH BC - - LD HL,SYS_PAGE.RAMD_KEYS-#4000 - ADD A,L - LD L,A - - IN A,(SLOT2) - LD B,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD C,(HL) - LD A,B - OUT (SLOT2),A - LD A,C - POP BC - AND A - RET - -GET_DRV_ST: - CP 4 - CCF - RET C - - PUSH BC - - LD HL,SYS_PAGE.DISK_TYPE-#4000 - ADD A,L - LD L,A - - IN A,(SLOT2) - LD B,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD C,(HL) - LD A,B - OUT (SLOT2),A - - LD A,C - - POP BC - - AND A - RET - -;*********************************************** -; ????? чё за херня про бейсик? тут не то ниже -; -; CMOS - 35h,36h - установки бейсика -; -;*********************************************** -CMOS_EMU_WR: - PUSH DE - - LD C,SLOT3 - IN B,(C) - LD E,SYS_PAGE - OUT (C),E - LD E,D - LD D,#FF - LD (DE),A - OUT (C),B - - POP DE - RET - -; запись в CMOS -CMOS_WR: - CALL CMOS_TEST - JR C,CMOS_EMU_WR -XWR_CMOS: - LD BC,CMOS.Port.Address.Write - OUT (C),D - LD BC,CMOS.Port.Data.Write - OUT (C),A - RET - -CMOS_EMU_RD: - PUSH DE - - LD C,SLOT3 - IN B,(C) - LD E,SYS_PAGE - OUT (C),E - LD E,D - LD D,#FF - LD A,(DE) - OUT (C),B - - POP DE - RET - -; чтение из CMOS -CMOS_RD: - CALL CMOS_TEST - JR C,CMOS_EMU_RD -XRD_CMOS: - LD BC,CMOS.Port.Address.Write - OUT (C),D - LD BC,CMOS.Port.Data.Read - IN A,(C) - RET - -CMOS_TEST: - - PUSH DE - PUSH BC - PUSH AF - - LD D,3FH ; !HARDCODE - CALL XRD_CMOS - LD E,A - CPL - CALL XWR_CMOS - CALL XRD_CMOS - CPL - CP E - JR NZ,CMOS_ERR - LD A,E - CALL XWR_CMOS - - POP AF - POP BC - POP DE - AND A - RET - -CMOS_ERR: - LD A,E - CALL XWR_CMOS - POP AF - POP BC - POP DE - SCF - RET - -; -;DE - куда - страница открыта! -;BC - сколько -;HL - буфер -; -; PUSH BC -; LD H,D -; LD L,E -; ADD HL,BC -; JR C,CUT -; LD HL,BUFER -; LDIR -; POP BC -; RET -;CUT: -; PUSH HL -; LD A,L -; LD L,C -; LD C,A -; LD A,H -; LD H,B -; LD B,A -; -; AND A -; SBC HL,BC -; LD B,H -; LD C,L -; LD HL,BUFER -; LDIR -; CALL NEXT_BANK -; POP BC -; LD A,B -; OR C -; JR Z,LAB -; LDIR -;LAB: POP BC -; RET -; - -FN_TURBO: - CP 2 - JR Z,.FN_TB_ONOFF - CP 3 - JR Z,.FN_TB_ONOFF - CP #12 - JR Z,.SET_FDD_720 - CP #13 - JR Z,.SET_FDD_1440 - SCF - RET - -;!FIXIT меняем плотность - меняем в системной странице инфу об этом -.SET_FDD_720: - LD A,1 - OUT (#BD),A ; !HARDCODE - AND A - RET -;!FIXIT меняем плотность - меняем в системной странице инфу об этом -.SET_FDD_1440: - LD A,#21 - OUT (#BD),A ; !HARDCODE - AND A - RET - -.FN_TB_ONOFF: - LD C,A - IN A,(SLOT3) - LD B,A - LD A,SYS_PAGE - OUT (SLOT3),A - LD DE,(SYS_PAGE.CONFIG_DE) - LD A,E - AND #FC - OR C - LD E,A - OUT (SYS_PORT.ON),A - LD (SYS_PAGE.CONFIG_DE),DE - LD A,B - OUT (SLOT3),A - AND A - RET - - -; разделить блок памяти на два блока -; A - блок, B - длина первого блока после разделения -; выход: A - блок 1, B - блок 2 -EMM.DivMemBlocks: - INC B - DEC B - SCF - RET Z - DEC B - LD E,A - CALL EMM.GetMemPage ; получить номер страницы блока - RET C - LD D,A - - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A - - LD H,high (SYS_PAGE.RAMD_FAT - #4000) - LD L,D - LD A,(HL) - LD (HL),0FFH - LD B,A - - EX AF,AF' - OUT (SLOT2),A - - LD A,E - AND A - RET - -; слить два блока памяти в один -; А - блок 1, B - блок 2 -; выход: А - блок -EMM.MergeMemBlocks: - LD E,A - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A - LD H,high (SYS_PAGE.RAMD_FAT - #4000) - LD L,E - LD C,B - LD B,0 -EMM_ADD_L: - LD A,(HL) - AND A - JR Z,EMM_ADD_ERR - CP 0FFH - JR Z,EMM_ADD_NEXT - LD L,A - DJNZ EMM_ADD_L -EMM_ADD_ERR: - EX AF,AF' - OUT (SLOT2),A - SCF - RET - -EMM_ADD_NEXT: - LD A,C - AND A - JR Z,EMM_ADD_ERR - LD (HL),A - EX AF,AF' - OUT (SLOT2),A - AND A - LD A,E - RET -; - - - diff --git a/src/bios/backup/EXP_HDD.as b/src/bios/backup/EXP_HDD.as deleted file mode 100644 index 7e2c1a3..0000000 --- a/src/bios/backup/EXP_HDD.as +++ /dev/null @@ -1,824 +0,0 @@ - -; -; DISPLAY "HDD utility" -/* -P_HD_CS HDW_DRV #4152 -P_CMD HDW_COM #4153 -P_HDST HDR_CTL #4053 -P_S_CNT HDW_CNT #0152 -*/ -;HDD_TYPE EQU 1 ; ????? чё это??? - - MACRO WAIT_HDD -.loop: - LD BC,IDE.Read.Status - IN A,(C) - BIT IDE.ControlBit.Busy,A - JR NZ,.loop - ENDM - -;************************************** -;!TEST не нужно если new_api_table -EXP_HDD_NEW: - PUSH AF - LD A,C - CP #10 - ;JR C,EXP_4X.HDD_CMD - JR C,HDD_CMD.4x - POP AF - JP EXP_HDD ; !FIXIT дальше в ROM будут опять проверки старших битов рег. C, уйти как-то от этого - -; MODULE EXP_4X -; !TODO оптимизировать HD_CMD_X -; C - COMAND ( 5 - RD, 6 - WR ) -; 0 - INIT, 1 - DIAG -;HDD_CMD: -;!TEST не нужно если new_api_table -HDD_CMD.4x: - LD A,C ; !!!!! можно убрать, в A и так то, что в C - - AND A - JP Z,FN_HDD_INIT ; #40 Инициализация винчестера - DEC A - JP Z,FN_HDD_RECAL ; #41 Рекалибровка винчестера - DEC A - JP Z,FN_HDD_TEST_IDE ; #42 Тест наличия интерфейса IDE - DEC A - JP Z,FN_HDD_PREPARE ; #43 Подготовка винчестера к операции чтения/записи - DEC A - JP Z,FN_HDD_READ_BPB ; #44 Читать BPB первого раздела - DEC A - JP Z,FN_HDD_READ ; #45 Читать сектора с винчестера - DEC A - JP Z,FN_HDD_WRITE ; #46 Писать сектора на винчестер - DEC A - JP Z,FN_HDD_PART ; #47 set IDE number (Настройка партиций и master/slave)??? - DEC A - JP Z,FN_HDD_READ_NEXT ; #48 Читать следующий сектор (ONLY FOR LBA!) - - POP AF ;!TEST не нужно если new_api_table - SCF - RET -;======================================= - -;-----------------------------------[OK] -HD_BPB_PREP: - LD D,A - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(SYS_PAGE.HD_IDF_ADR.sectors) - LD E,A - EX AF,AF' - OUT (SLOT3),A - LD A,D - LD D,#00 - LD IX,#0000 - LD B,#01 -;--------------------------------------- - -;-----------------------------------[OK] -HD_PREPARE: - PUSH AF - PUSH HL - CALL HD_CALC_SECS - JR NC,HD_PREP_L1 - POP HL - POP AF - SCF - RET -;--------------------------------------- - -;-----------------------------------[OK] -HD_PREP_L1: - LD A,B - LD BC,IDE.Write.Counter ; Установить число секторов для записи - OUT (C),A - - IF IDE_Optimization - INC C ; IDE.Write.Sector - OUT (C),L ; СЕКТОР - INC C ; IDE.Write.CylinderLow - OUT (C),E ; дорожка low - INC C ; IDE.Write.CylinderHigh - OUT (C),D - ELSE - LD BC,IDE.Write.Sector - OUT (C),L ; СЕКТОР - LD BC,IDE.Write.CylinderLow - OUT (C),E ; дорожка low - LD BC,IDE.Write.CylinderHigh - OUT (C),D ; дорожка high - ENDIF - - LD BC,IDE.Read.Control -; DEC B - IN A,(C) - AND #F0 ; !!!!! посмотреть - OR H - INC B ; IDE.Write.DriveCtrl - - OUT (C),A - - POP HL ; BUFER & PAGE - POP AF - AND A - RET -;--------------------------------------- - - -NEXT_ADD_SEC: - PUSH AF - - LD A,B - LD BC,IDE.Write.Counter ; Установить число секторов для записи - OUT (C),A - - IF IDE_Optimization - DEC B - INC C - IN A,(C) ; IDE.Read.Sector - ADC A,E - INC B - OUT (C),A ; IDE.Write.Sector - - DEC B - INC C - IN A,(C) ; IDE.Read.CylinderLow - ADC A,D - INC B - OUT (C),A ; IDE.Write.CylinderLow - - DEC B - INC C - IN A,(C) ; IDE.Read.CylinderHigh - ADC A,0 - INC B - OUT (C),A ; IDE.Write.CylinderHigh - - LD BC,IDE.Read.Control - IN A,(C) - ELSE - LD BC,IDE.Read.Sector - IN A,(C) - ADC A,E - INC B - OUT (C),A ; IDE.Write.Sector - - LD BC,IDE.Read.CylinderLow - IN A,(C) - ADC A,D - INC B - OUT (C),A ; IDE.Write.CylinderLow - - LD BC,IDE.Read.CylinderHigh - IN A,(C) - ADC A,0 - INC B - OUT (C),A ; IDE.Write.CylinderHigh - - LD BC,IDE.Read.Control - IN A,(C) - ENDIF - - LD D,A - ADC A,0 - AND #0F - LD E,A - LD A,D - AND #F0 - OR E - INC B - OUT (C),A ; ????? HEADS?! IDE.Write.DriveCtrl - - POP AF - RET - - -;-----------------------------------[OK] -FN_HDD_PREPARE: ; ПОДГОТОВКА К ВНЕШНИМ ОПЕРАЦИЯМ R/W - POP AF - AND A - INC B - DEC B - RET Z - - CALL HD_WAIT - RET C - - CALL HD_PREPARE - RET C - - EXX - LD C,SLOT3 - IN B,(C) - EXX - OUT (SLOT3),A - EX AF,AF' - - SAFE_PORTY - - LD BC,IDE.Write.Command ; ????? - LD A,#20 ; ????? -; OUT (C),A - AND A ; ????? - - RET -;--------------------------------------- - -;-----------------------------------[OK] -FN_HDD_READ_BPB: - POP AF - CALL HD_WAIT - RET C - CALL HD_BPB_PREP - RET C - - JR HD_RD_L1 -;--------------------------------------- - - -; FOR LBA ONLY - NEXT_READ -FN_HDD_READ_NEXT: -; HL - bufer, A - page -; B - numer of sectors -; DE - add_par (next+DE) (d.b. 1 for NEXT) - POP AF - AND A - INC B - DEC B - RET Z ; ret if 0 sectors - CALL HD_WAIT - RET C - CALL NEXT_ADD_SEC - JR HD_RD_L1 - - -;-----------------------------------[OK] -FN_HDD_READ: - POP AF ; HL - BUFER, A - PAGE !!! - -HD_RD_CMD: - AND A - INC B - DEC B - RET Z - CALL HD_WAIT - RET C - - CALL HD_PREPARE - RET C - -HD_RD_L1: - EXX - LD C,SLOT3 - IN B,(C) - EXX - OUT (SLOT3),A - EX AF,AF' - - SAFE_PORTY - - LD BC,IDE.Write.Command - LD A,#20 - OUT (C),A - -HD_RD_L2: - - WAIT_HDD - - BIT IDE.ControlBit.DataRequest,A - JR NZ,HD_READ_CONT - - ZERO_PORTY - -HD_RET: - EXX - OUT (C),B - EXX - LD BC,IDE.Read.Error - IN A,(C) - AND A - SCF - RET NZ - - EX AF,AF' - AND A - RET -;--------------------------------------- - -;-----------------------------------[OK] -HD_READ_CONT: - LD BC,IDE.Read.Data - -.loop_read1: - DUP 16 - INI ; всего 16 раз INI - оптимально. - EDUP - JP NZ,.loop_read1 -.loop_read2: - DUP 16 - INI ; всего 16 раз INI - оптимально. - EDUP - JP NZ,.loop_read2 - - LD A,H - OR L - JR NZ,HD_RD_L2 - - LD A,SYS_PAGE - OUT (SLOT3),A - EX AF,AF' - LD HL,SYS_PAGE.RAMD_FAT - LD L,A - LD A,(HL) - OUT (SLOT3),A - EX AF,AF' - LD HL,#C000 ; !!!!! - JR HD_RD_L2 -;--------------------------------------- - -;-----------------------------------[OK] -FN_HDD_WRITE: - POP AF ; HL - BUFER, A - PAGE !!! - -HD_WR_CMD: - AND A - INC B - DEC B - RET Z - - CALL HD_WAIT - RET C - CALL HD_PREPARE - RET C - - EXX - LD C,SLOT3 - IN B,(C) - EXX - OUT (SLOT3),A - EX AF,AF' - - LD BC,IDE.Write.Command - LD A,#30 - OUT (C),A - -HD_WR_L2: - WAIT_HDD - - BIT IDE.ControlBit.DataRequest,A - JP Z,HD_RET - -; IF HDD_TYPE = 1 - LD BC,IDE.Write.Data - LD D,32 -HD_WR_LOOP: - DUP 16 - OUTI ; всего 16 раз OUTI - оптимально. - EDUP - - DEC D - JP NZ,HD_WR_LOOP -/* - ELSE - LD BC,P_DATS+#100 - LD D,64 -HD_WR_LOOP: - DUP 4 - INC HL - OUTI - DEC HL - DEC HL - OUTI - INC HL - EDUP - - DEC D - JR NZ,HD_WR_LOOP - ENDIF -*/ - LD A,H - OR L - JR NZ,HD_WR_L2 - - LD A,SYS_PAGE - OUT (SLOT3),A - EX AF,AF' - LD HL,SYS_PAGE.RAMD_FAT - LD L,A - LD A,(HL) - OUT (SLOT3),A - EX AF,AF' - LD HL,#C000 ;!!!!! - JR HD_WR_L2 -;--------------------------------------- - -;-----------------------------------[OK] -FN_HDD_RECAL: - POP AF -HD_CMD1_EX: - LD A,#A0 - LD BC,IDE.Write.DriveCtrl - OUT (C),A - LD A,#90 ; DIAGNOSTICS - CALL HD_CMD_EXE - AND A - BIT IDE.ControlBit.Error,A - RET Z - LD BC,IDE.Read.Error - IN A,(C) - CP 1 ; !!!!! глянуть - RET Z - SCF - RET -;--------------------------------------- - -;-----------------------------------[OK] -FN_HDD_TEST_IDE: - POP AF - LD E,#00 - LD BC,IDE.Write.DriveCtrl - LD A,#A0 ; !!!!! глянуть - OUT (C),A - - CALL TEST_HDD_DRV - - JR NZ,NO_HDD1 - SET 0,E -NO_HDD1: - LD BC,IDE.Write.DriveCtrl - LD A,#B0 ; !!!!! глянуть - OUT (C),A - - CALL TEST_HDD_DRV - - JR NZ,NO_HDD2 - SET 1,E -NO_HDD2: - LD A,E - AND A - SCF - RET Z ; HDD absent ! - AND A - RET -;--------------------------------------- - - -;-----------------------------------[DIFFERENT] -; Не должна портить регистр E!!! -TEST_HDD_DRV: -; EXP_HDD.ASM variant - LD HL,#01FE ; ????? - LD BC,IDE.Write.Counter - OUT (C),L - IF IDE_Optimization - INC C - OUT (C),H ; IDE.Write.Sector - - DEC C - INC B - IN A,(C) ; ????? IDE.Write.Counter+#100 - CP L - RET NZ - INC C - - ELSE - LD BC,IDE.Write.Sector - OUT (C),H - LD BC,IDE.Write.Counter+#100 - IN A,(C) - CP L - RET NZ - LD BC,IDE.Write.Sector+#100 - ENDIF - - IN A,(C) ; ????? IDE.Write.Sector+#100 - CP H - RET -/* -TEST_HDD_DRV: -; EXTENDED.ASM variant - LD HL,#00FF ;???!!!! - LD BC,IDE.Write.CylinderLow - OUT (C),L - IF IDE_Optimization - INC C - OUT (C),H ; IDE.Write.CylinderHigh - - INC B - DEC C - IN A,(C) ; ????? Тут регистр BC = #0254 - что за порт такой и что оттуда прочитается? - CP L - RET NZ - INC C - - ELSE - LD BC,IDE.Write.CylinderHigh - OUT (C),H - LD BC,#0254 ;???!!!! - IN A,(C) - CP L - RET NZ - LD BC,#0255 ;???!!!! - ENDIF - - IN A,(C) ; ????? Тут регистр BC = #0255 - что за порт такой и что оттуда прочитается? - CP H - RET -*/ -;--------------------------------------- - - -;-----------------------------------[OK] -FN_HDD_INIT: - POP AF - LD BC,IDE.Write.DriveCtrl - LD A,#A0 - OUT (C),A - CALL TEST_HDD_DRV - JR NZ,HD_ABSENT -HD_C0_L3: - WAIT_HDD - - LD BC,IDE.Write.Command - LD A,#EC ; !HARDCODE - OUT (C),A - - WAIT_HDD - - BIT IDE.ControlBit.DataRequest,A - JR NZ,HD_C0_L2 - SCF - RET -;--------------------------------------- - -;-----------------------------------[OK] -HD_ABSENT: - LD BC,IDE.Write.DriveCtrl - LD A,#B0 ; !HARDCODE - OUT (C),A - CALL TEST_HDD_DRV - JR Z,HD_C0_L3 - SCF - RET -;--------------------------------------- - -;-----------------------------------[OK] -HD_C0_L2: - LD BC,IDE.Read.Data - LD HL,SYS_PAGE.HD_IDF_ADR - IN A,(SLOT3) - LD D,A - LD A,SYS_PAGE - OUT (SLOT3),A - INIR - INIR - LD A,(SYS_PAGE.HD_IDF_ADR.sectors) ; число секторов - LD C,A - LD HL,0 - LD B,H - LD A,(SYS_PAGE.HD_IDF_ADR.heads) ; число головок -.loop: - ADD HL,BC - DEC A - JR NZ,.loop - LD (SYS_PAGE.HD_IDF_ADR.sec_cyl),HL - - WAIT_HDD - - LD BC,IDE.Read.Control -; DEC B - IN A,(C) - AND #10 - LD B,A - LD A,(SYS_PAGE.HD_IDF_ADR.heads) ; число головок - - DEC A - AND #0F - OR #A0 - OR B - - LD H,A - LD A,(SYS_PAGE.HD_IDF_ADR+99) ; ????? LBA? - BIT 1,A - JR Z,HD_C0_NO_LBA - SET 6,H - -HD_C0_NO_LBA: - LD BC,IDE.Write.DriveCtrl - OUT (C),H - - LD A,(SYS_PAGE.HD_IDF_ADR.sectors) ; число секторов - - LD BC,IDE.Write.Counter - OUT (C),A - LD A,D - OUT (SLOT3),A - - LD A,#91 ; SET HDD PARAMETERS - CALL HD_CMD_EXE - RET - -; RET C -; LD A,1FH ; RECALIBRATE -; CALL HD_CMD_EXE -; RET -;--------------------------------------- - -;-----------------------------------[OK] -HD_CMD_EXE: - CALL HD_WAIT - RET C - LD BC,IDE.Write.Command - OUT (C),A -HD_WAIT: - PUSH DE - PUSH BC - PUSH AF - LD DE,0 -HD_WAIT1: - LD BC,IDE.Read.Status - IN A,(C) - BIT IDE.ControlBit.Busy,A - JR Z,HD_W_EXIT - DEC DE - LD A,D - OR E - JR NZ,HD_WAIT1 - POP AF - POP BC - POP DE - SCF - RET -;--------------------------------------- - -;-----------------------------------[OK] -HD_W_EXIT: - POP AF - POP BC - POP DE - AND A - RET -;--------------------------------------- - - -;-----------------------------------[DIFFERENT] -/* -;EXTENDED.ASM Version - -HDD_LBA: ;???!!!! - POP BC - LD L,E - LD E,D - LD D,XL - XOR A - LD H,A - RET - -HD_CALC_SECS: - LD A,XH - AND A - SCF - RET NZ ; ошибка, слишком большой HDD - - PUSH BC - LD BC,IDE.Write.DriveCtrl - DEC B - IN A,(C) - BIT 6,A - JR NZ,HDD_LBA -; POP BC ;!!!!! посмотреть -*/ - -;EXP_HDD.ASM Version -HDD_LBA: - POP BC - LD L,E - LD E,D - LD D,XL - LD A,XH - AND #0F ; XOR A ????? разобраться - LD H,A - RET - -HD_CALC_SECS: - PUSH BC - LD BC,IDE.Read.Control -; DEC B - IN A,(C) - BIT 6,A - JR NZ,HDD_LBA - POP BC ; снимаем значение для корректного ret - - LD A,XH - AND A - SCF - RET NZ ; ошибка, слишком большой HDD -;--------------------------------------- - - -;-----------------------------------[OK] -; IX,DE - абсолютный номер сектора - PUSH IX - POP HL - - IN A,(SLOT3) - LD C,A - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,C - LD (SYS_PAGE.COPY_SLOT3),A - -; HL,DE - номер сектора -; BC - число секторов на цилиндре - LD BC,(SYS_PAGE.HD_IDF_ADR.sec_cyl) ; число секторов на цилиндре - LD A,16 ; HL,DE разделить на BC - SCF -DIV_LOOP: - EX DE,HL - ADD HL,HL - EX DE,HL - ADC HL,HL - - SBC HL,BC ; сравнить HL и BC - JR NC,NO_ADD ; переноса не было - +1! - ADD HL,BC - DEC A - JR NZ,DIV_LOOP - JR DIV_END -NO_ADD: - INC DE - DEC A - JR NZ,DIV_LOOP -DIV_END: -; DE - результат, HL - остаток -; DE - цилиндр - LD A,(SYS_PAGE.HD_IDF_ADR+12) ; !HARDCODE .sectors -; A - число секторов на дорожке -; HL - номер сектора в цилиндре - LD B,0 - LD C,A -; LD BC,(MS_BPB+S_P_T) ; ЧИСЛО СЕКТОРОВ НА ДОРОЖКЕ - XOR A -HD_CALC_LOOP2: - SBC HL,BC - INC A - JR NC,HD_CALC_LOOP2 - - DEC A ; A - головка - ADD HL,BC ; L - сектор - INC L - LD H,A ; HL - HEAD,SEC - - LD A,(SYS_PAGE.COPY_SLOT3) - OUT (SLOT3),A - - AND A - RET -;--------------------------------------- - - -FN_HDD_PART: - POP AF - BIT 0,A - LD A,#21 ; !HARDCODE - JR Z,IDE_1 - LD A,#01 ; !HARDCODE -IDE_1: - OUT (#BC),A ;!!!!! посмотреть - RET - -; ENDMODULE -;************************************************ - -; ????? -; DB 'HDD_DRV_END' -; Вход: -; C - команда -; 0 - INIT - входных пар нет => A - число поддерживаемых дисков. -; 1 - RESET - выбор диска A - номер диска от 0 => -; 2 - (STATUS) !!!!! TEST? -; 3 - MEDIA CHECK - A - номер диска => A = 0 - old. #FF - new (всегда #FF) !!!!! PREPARE??? -; 4 - READ BPB - A - диск HL - адрес в текущей странице. -; 5 - READ - A - диск, IX:DE сектор, HL - адрес, B - число секторов -; 6 - WRITE - '' - -; 7 - PART -; 8 - READ_NEXT -; -; ошибки - CF - A - ошибка -; -; 0 - нет ошибки -; 1 - неверная команда -; 2 - неверный номер диска -; 3 - неверный формат (не MS-DOS) -; 4 - нет готовности -; 5 - ошибка позиционирования -; 6 - сектор не найден -; 7 - ошибка CRC -; 8 - защита записи -; 9 - ошибка чтения -; 10 - ошибка записи -; 11 - ГЛЮК -; \ No newline at end of file diff --git a/src/bios/backup/EXTENDED.as b/src/bios/backup/EXTENDED.as deleted file mode 100644 index 96791b7..0000000 --- a/src/bios/backup/EXTENDED.as +++ /dev/null @@ -1,474 +0,0 @@ - -; -; It's disk drive BIOS extender for functions 5xh. -;--------------------------------------------------------------- -;Version! Description -;--------------------------------------------------------------- -; 2.32 ! Removed `DI' Disabled Interupt instruction in HDRIVER6 -; ! function load sectors. -; ! Fixed bug waiting slave device in AUTOIDE. - -;SPRINTER EQU 97 -;SPRINTER EQU 2000 -; DEVICE ZXSPECTRUM4096 - -/* -;HDD_TYPE EQU 1 - MACRO WAIT_HDD -.LL1: - LD BC,P_HDST - IN A,(C) - BIT 7,A - JR NZ,.LL1 - ENDM -*/ - -; ORG #0000 - -; INCLUDE '../VERSION.INC' -; INCLUDE '../BIOS.INC' - -;VER EQU 2 ;Version disk subsystem -;MOD EQU 40 - -;PAGE1 EQU #A2 -;PAGE2 EQU #C2 -;INT_ADRESS EQU #C124 -;INT_PAGE EQU #C126 -;INT_ID EQU #C127 -;BIOS EQU #3FD0 -; DS #3FD0,#FF - -;------------[Begin of ROM]------------- -ROM_START: - DI - HALT -;--------------------------------------- - -;--------------[checksum]--------------- - BLOCK 4-$,#FF -Check_Sum: - DB #FF,#FF,#FF,#FF ; место для контрольной суммы -;--------------------------------------- - BLOCK #10-$,#FF - RET -;--------------------------------------- - -;----------------[int]------------------ - BLOCK #38-$,#FF - -INT: - PUSH HL - PUSH BC - PUSH AF - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (C),A - - LD A,(SYS_PAGE.INT_ID) - CP #AA - JR Z,YESINT - OUT (C),B - JR NOINT -YESINT: - LD HL,(SYS_PAGE.INT_ADRESS) - LD A,H - OR L - LD A,(SYS_PAGE.INT_PAGE) - OUT (C),B - CALL NZ,EXTINT -NOINT: - POP AF - POP BC - POP HL - EI - RETI -;--------------------------------------- - -;----------------[NMI]------------------ - _mInfoBLOCK #66-$,#FF -NMI: - RETN -;--------------------------------------- - -;----------------[int]------------------ -EXTINT: - OR A - RET Z - LD C,SLOT1 - BIT 7,H - JR Z,L1 - LD C,SLOT2 - BIT 6,H - JR Z,L1 - LD C,SLOT3 -L1: - IN B,(C) - PUSH BC - OUT (C),A - CALL JPHL - POP BC - OUT (C),B - RET -JPHL: - JP (HL) -;--------------------------------------- - -; -;!TEST не нужно если new_api_table -HDD_FN_5x: - POP AF - CALL HDD_CMD.FN5X - JP RET_TO_EXP - - ;HD_CMD_X - ;!TEST не нужно если new_api_table -HDD_CMD_4X: - SET 6,C - CALL ToBIOS_FromEXT - RET - - - -; !TODO ; !FIXIT -; ; SCF -; ; BIT 7,C -; !FIXIT -;!TEST не нужно если new_api_table -HDD_CMD: - push af ; RET NZ - ld a,%00011111 ; BIT 6,C - sub c ; RET NZ - jp c,.exit ; BIT 5,C - pop af ; RET NZ - BIT 4,C - JP Z,HDD_CMD_4X ; 4xh functions ;C < #10 ; !TEST new_api -; 5xh functions #C0 - CD ROM, #80 - HARD DISK, #60 - RAM DISK, #00 - FLOPPY DISK -.FN5X: - RES 4,C ;C >= #10 - INC C - DEC C - JP Z,.RESERVED ;#50 - DEC C - JP Z,DRV_RESET ;#51 - Reset drive - DEC C - JP Z,DRV_READ_LONG ;#52 - Long read - DEC C - JP Z,DRV_WRITE_LONG ;#53 - Long write - DEC C - JP Z,DRV_VERIFY ;#54 - Verify sectors - DEC C - JP Z,DRV_READ ;#55 - Read sectors - DEC C - JP Z,DRV_WRITE ;#56 - Write sectors - DEC C - JP Z,DRV_DETECT ;#57 - Detect - DEC C - JP Z,DRV_GET_PAR ;#58 - Get Media parameters - DEC C - JP Z,DRV_SET_PAR ;#59 - Set Media parameters - DEC C - JP Z,DRV_VERSION ;#5A - Version number - DEC C - JP Z,.RESERVED ;#5B - DEC C - JP Z,.RESERVED ;#5C - DEC C - JP Z,.RESERVED ;#5D - DEC C - JP Z,.RESERVED ;#5E - DEC C - JP Z,DRV_CONFIG ;#5F - Configuration -.RESERVED: - LD A,1 ;!HARDCODE error code - SCF - RET -.exit: POP AF - SCF - RET - -DRV_VERSION: - LD HL,0 - LD BC,0 - LD DE,Disk_subsystem_ver_hex - AND A - RET - -DRV_CONFIG: ; ????? что за функция и куда указывает IX - IN A,(SLOT3) - PUSH AF - PUSH IY - LD A,SYS_PAGE - OUT (SLOT3),A - LD (IX+0),#04 - LD (IX+1),#00 ;FDD COUNT - LD (IX+2),#00 ;HDD COUNT - LD (IX+3),#00 ;CDD COUNT - LD (IX+4),#00 ;END CODE -;Calculating FDD devices - LD HL,FDD_INI_TABLE.FDD_0 - INC (IX+1) - LD B,8 - LD A,#FF -TFD0: - CP (HL) - INC HL - JR NZ,YYYFD0 - DJNZ TFD0 - DEC (IX+1) -YYYFD0: - LD HL,FDD_INI_TABLE.FDD_1 - INC (IX+1) - LD B,8 - LD A,#FF -TFD1: - CP (HL) - INC HL - JR NZ,YYYFD1 - DJNZ TFD1 - DEC (IX+1) -YYYFD1: -;Calculating IDE devices - LD IY,IDE.INIT_TBL_IDE0 - LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM - CP #FF - JR Z,ABSIDE0 - CP IDE.Device.HDD - JR NZ,NOT_HD0 - INC (IX+2) -NOT_HD0: - CP IDE.Device.CDROM - JR NZ,NOT_CD0 - INC (IX+3) -NOT_CD0: -ABSIDE0: - LD IY,IDE.INIT_TBL_IDE1 - LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM - CP #FF - JR Z,ABSIDE1 - CP IDE.Device.HDD - JR NZ,NOT_HD1 - INC (IX+2) - -NOT_HD1: - CP IDE.Device.CDROM - JR NZ,NOT_CD1 - INC (IX+3) -NOT_CD1: -ABSIDE1: - LD IY,IDE.INIT_TBL_IDE2 - LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM - CP #FF - JR Z,ABSIDE2 - CP IDE.Device.HDD - JR NZ,NOT_HD2 - INC (IX+2) -NOT_HD2: - CP IDE.Device.CDROM - JR NZ,NOT_CD2 - INC (IX+3) -NOT_CD2: -ABSIDE2: - LD IY,IDE.INIT_TBL_IDE3 - LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM - CP #FF - JR Z,check_exit - CP IDE.Device.HDD - JR NZ,NOT_HD3 - INC (IX+2) -NOT_HD3: - CP IDE.Device.CDROM - JR NZ,check_exit - INC (IX+3) -check_exit: - POP IY - POP AF - OUT (SLOT3),A - XOR A - RET - -DRV_RESET: - CP #10 - JP C,FDD_5x.RESET -; CP #60 -; JP C,.error -; CP #70 -; JP C,RESETR - CP #80 - JP C,.error - CP #90 - JP C,HDD_5x.RESET - CP #C0 - JP C,.error - CP #D0 - JP C,CD_5x.RESET -.error: - LD A,#AA - SCF - RET - -DRV_READ_LONG: - CP #10 - JP C,FDD_5x.LONG_READ - CP #60 - JP C,.error - CP #70 - JP C,RMD_5x.LONG_READ - CP #80 - JP C,.error - CP #90 - JP C,HDD_5x.LONG_READ - CP #C0 - JP C,.error - CP #D0 - JP C,CD_5x.LONG_READ -.error: - LD A,#AA - SCF - RET - -DRV_WRITE_LONG: - CP #10 - JP C,FDD_5x.LONG_WRITE - CP #60 - JP C,.error - CP #70 - JP C,RMD_5x.LONG_WRITE - CP #80 - JP C,.error - CP #90 - JP C,HDD_5x.LONG_WRITE -; CP #C0 -; JP C,.error -; CP #D0 -; JP C,LWRITEC -.error: - LD A,#AA - SCF - RET - -DRV_READ: - CP #10 ; !HARDCODE поназывать бы все ID - JP C,FDD_5x.READ - CP #60 - JP C,.error - CP #70 - JP C,RMD_5x.READ - CP #80 - JP C,.error - CP #90 - JP C,HDD_5x.READ - CP #C0 - JP C,.error - CP #D0 - JP C,CD_5x.READ -.error: - LD A,#AA - SCF - RET - -DRV_WRITE: - CP #10 - JP C,FDD_5x.WRITE - CP #60 - JP C,.error - CP #70 - JP C,RMD_5x.WRITE - CP #80 - JP C,.error - CP #90 - JP C,HDD_5x.WRITE -; CP #C0 -; JP C,.error -; CP #D0 -; JP C,WRITEC -.error: - LD A,#AA - SCF - RET - -DRV_VERIFY: -; CP #10 -; JP C,VERIFYD -; CP #60 -; JP C,.error -; CP #70 -; JP C,VERIFYR - CP #80 - JP C,.error - CP #90 - JP C,HDD_5x.VERIFY -; CP #C0 -; JP C,.error -; CP #D0 -; JP C,VERIFYC -.error: - LD A,#AA - SCF - RET - -DRV_DETECT: - CP #10 - JP C,FDD_5x.DETECT -; CP #60 -; JP C,.error -; CP #70 -; JP C,DETECTR -; CP #80 -; JP C,.error -; CP #90 -; JP C,DETECTH - CP #C0 - JP C,.error - CP #D0 - JP C,CD_5x.DETECT -.error: - LD A,#AA - SCF - RET - -DRV_GET_PAR: - CP #10 - JP C,FDD_5x.GETMED - CP #60 - JP C,.error - CP #70 - JP C,RMD_5x.GETMED - CP #80 - JP C,.error - CP #90 - JP C,HDD_5x.GETMED -.error: - LD A,#AA - SCF - RET - -DRV_SET_PAR: - CP #10 - JP C,FDD_5x.SETMED - CP #60 - JP C,.error - CP #70 - JP C,RMD_5x.SETMED - CP #80 - JP C,.error - CP #90 - JP C,HDD_5x.SETMED -.error: - LD A,#AA - SCF - RET -; - - INCLUDE 'src/bios/ROM/EXTENDED/FDD_DRIVER_2.asm' - INCLUDE 'src/bios/ROM/EXTENDED/RAM_DISK_DRIVER_1.asm' - INCLUDE 'src/bios/ROM/EXTENDED/HDD_DRIVER_6.asm' - INCLUDE 'src/bios/ROM/EXTENDED/CD_DRIVER_0.asm' - -;01000h SETUP - -; ORG #9000 -; INCBIN "BSETUP.BIN" -; INCLUDE "ENDROM.ASM" -; \ No newline at end of file diff --git a/src/bios/backup/ROM.as b/src/bios/backup/ROM.as deleted file mode 100644 index ffd6f9c..0000000 --- a/src/bios/backup/ROM.as +++ /dev/null @@ -1,135 +0,0 @@ -;-----------[#0000 Extended]------------ - INCLUDE 'src/bios/rom/EXTENDED/EXTENDED.asm' -;--------------------------------------- - DISPLAY " EXTENDED end addr: ", /A, $ - -;-------------[#1000 SETUP]------------- - ShowInfo 'Setup block of ROM start', 0 ; !!!!! test - -BLOCK_Setup EQU $ - - IF PACKED_MAIN - BLOCK ROM_MAP.SETUP-$,#FF - - DISP COMPILE_ADDR.SETUP - -; Depacker version -SETUP_MAIN: - LD HL,DEPACKER.UnpackedEXECaddr; точка входа в распакованном коде - PUSH HL - LD DE,DEPACKER.WorkAddr ; адрес процедуры депакера - PUSH DE - - LD HL,DEPACKER.Addr - LD BC,DEPACKER.Length - LDIR - - LD HL,DEPACKER.PackedMAIN ; где архив - LD DE,DEPACKER.UnpackAddr ; куда распаковывать - RET - -.Depacker EQU $ - ENT - -;-----------------[v] -DEPACK_DATA: - DISP DEPACKER.WorkAddr - MODULE UnPacker - INCLUDE 'src/bios/ROM/SETUP/DEHRUST.asm' ; !TODO сделать на LUA автовыбор декомпрессора и компрессора -PackedMAIN: INCBIN 'Build/Bin/temp/MAIN.PAK' - ENDMODULE - ENT -DEPACK_DATA.length EQU $-DEPACK_DATA -;-----------------[^] - - - ELSE - DISP COMPILE_ADDR.SETUP - ShowInfo 'Setup block DISP start', 1 ; !!!!! test -SETUP_MAIN: INCLUDE 'src/bios/ROM/SETUP/Main.asm' - ShowInfo 'Setup block DISP end', 1 ; !!!!! test - ENT - ENDIF - - - ShowInfo 'Setup block of ROM end', 0 ; !!!!! test -BLOCK_Setup.Length EQU $-BLOCK_Setup -;--------------------------------------- - - -;*************************************** -; -; !TODO можно оприходовать тут сколько-то байтов -; DISPLAY 'Address in ROM with ', /D, ToBIOS_FromEXT-$, ' free bytes: ',/H,$ -;*************************************** -; -;---------------[SET EXP]--------------- - _mInfoBLOCK ToBIOS_FromEXT-$,#FF ; #3FD0 -; call exp bios from setup -;RST18h: - PUSH AF - LD A,ROM.EXT ; set exp-rom to slot0 - OUT (SYS_PORT.ON),A - POP AF - RET -;--------------------------------------- - - - -;--------[ From TR-DOS to HDD part2]-------- - _mInfoBLOCK #3FD8-$,#FF -TRDOS_HD_CMD: -// JP L0107 - POP AF - CALL HDD_CMD ; !TEST new_api - JP RET_TO_TRDOS -;--------------------------------------- - - - -;-------------[SND_TEST_RET]------------- - _mInfoBLOCK #3FE0-$,#FF -SND_TEST_RET: - LD A,ROM.EXT - OUT (SYS_PORT.OFF),A -; JP SOUND_TEST - JP #0000 -;--------------------------------------- - - -;!TEST не нужно если new_api_table -;------------[HDD_5x portal]------------ -; точка входа/выхода для функций 5х из EXP - _mInfoBLOCK #3FE8-$,#FF -RET_TO_EXP: - PUSH AF - LD A,ROM.EXT - OUT (SYS_PORT.ON),A - JP HDD_FN_5x -;--------------------------------------- - - -;!FIXIT эта точка входа очень странная из страницы в страницу прыгает -;---------[ From TR-DOS to HDD ]-------- - _mInfoBLOCK #3FF0-$,255 -RET_TO_TRDOS: - PUSH AF - DI - LD A,ROM.EXT - OUT (SYS_PORT.OFF),A - JR TRDOS_HD_CMD ; тут не хватило места в 1 байт, чтоб сразу сделать JP -;--------------------------------------- - - - -;-----[???????????????????????????]----- - _mInfoBLOCK #3FF8-$,255 -A3FF8: PUSH AF - LD A,ROM.EXT - OUT (SYS_PORT.OFF),A -; !FIXIT может убрать заглушку и сделать, чтоб переключалось на EXP и дальше как в EXP_FNS_RET ? -; или своего чего-нибудь добавить. - JP #0000 -;--------------------------------------- -; $ = #4000 -;======================================= diff --git a/src/bios/exp/BIOS_FUNC.asm b/src/bios/exp/BIOS_FUNC.asm index 8848fba..dfcd642 100644 --- a/src/bios/exp/BIOS_FUNC.asm +++ b/src/bios/exp/BIOS_FUNC.asm @@ -2,45 +2,45 @@ MACRO _mNoDrive_5xTable numberOFdrives, byteOFword IF byteOFword DUP numberOFdrives - DB high FN_RESERVED_5x ;#50 - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_RESERVED_5x ;#50 - Дубль. На эту функцию прыгает из основного обработчика - DB high FN_5x_Parser_1 ;#51 - DB high FN_5x_Parser_2 ;#52 - DB high FN_5x_Parser_3 ;#53 - DB high FN_5x_Parser_4 ;#54 - DB high FN_5x_Parser_5 ;#55 - DB high FN_5x_Parser_6 ;#56 - DB high FN_5x_Parser_7 ;#57 - DB high FN_5x_Parser_8 ;#58 - DB high FN_5x_Parser_9 ;#59 + DB high FN_ABSENT_5x ;#51 + DB high FN_ABSENT_5x ;#52 + DB high FN_ABSENT_5x ;#53 + DB high FN_ABSENT_5x ;#54 + DB high FN_ABSENT_5x ;#55 + DB high FN_ABSENT_5x ;#56 + DB high FN_ABSENT_5x ;#57 + DB high FN_ABSENT_5x ;#58 + DB high FN_ABSENT_5x ;#59 - DB high DRV_VERSION ;#5A - Дубль. На эту функцию прыгает из основного обработчика - DB high FN_RESERVED_5x ;#5B - Дубль. На эту функцию прыгает из основного обработчика - DB high FN_RESERVED_5x ;#5C - Дубль. На эту функцию прыгает из основного обработчика - DB high FN_RESERVED_5x ;#5D - Дубль. На эту функцию прыгает из основного обработчика - DB high FN_RESERVED_5x ;#5E - Дубль. На эту функцию прыгает из основного обработчика - DB high DRV_CONFIG ;#5F - Дубль. На эту функцию прыгает из основного обработчика + DB high DRV_VERSION ;#5A - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_RESERVED_5x ;#5B - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_RESERVED_5x ;#5C - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_RESERVED_5x ;#5D - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_ABSENT_5x ;#5E + DB high DRV_LIST ;#5F - Дубль. На эту функцию прыгает из основного обработчика EDUP ELSE DUP numberOFdrives - DB low FN_RESERVED_5x ;#50 - Дубль. На эту функцию прыгает из основного обработчика + DB low FN_RESERVED_5x ;#50 - Дубль. На эту функцию прыгает из основного обработчика - DB low FN_5x_Parser_1 ;#51 - DB low FN_5x_Parser_2 ;#52 - DB low FN_5x_Parser_3 ;#53 - DB low FN_5x_Parser_4 ;#54 - DB low FN_5x_Parser_5 ;#55 - DB low FN_5x_Parser_6 ;#56 - DB low FN_5x_Parser_7 ;#57 - DB low FN_5x_Parser_8 ;#58 - DB low FN_5x_Parser_9 ;#59 + DB low FN_ABSENT_5x ;#51 + DB low FN_ABSENT_5x ;#52 + DB low FN_ABSENT_5x ;#53 + DB low FN_ABSENT_5x ;#54 + DB low FN_ABSENT_5x ;#55 + DB low FN_ABSENT_5x ;#56 + DB low FN_ABSENT_5x ;#57 + DB low FN_ABSENT_5x ;#58 + DB low FN_ABSENT_5x ;#59 - DB low DRV_VERSION ;#5A - Дубль. На эту функцию прыгает из основного обработчика - DB low FN_RESERVED_5x ;#5B - Дубль. На эту функцию прыгает из основного обработчика - DB low FN_RESERVED_5x ;#5C - Дубль. На эту функцию прыгает из основного обработчика - DB low FN_RESERVED_5x ;#5D - Дубль. На эту функцию прыгает из основного обработчика - DB low FN_RESERVED_5x ;#5E - Дубль. На эту функцию прыгает из основного обработчика - DB low DRV_CONFIG ;#5F - Дубль. На эту функцию прыгает из основного обработчика + DB low DRV_VERSION ;#5A - Дубль. На эту функцию прыгает из основного обработчика + DB low FN_RESERVED_5x ;#5B - Дубль. На эту функцию прыгает из основного обработчика + DB low FN_RESERVED_5x ;#5C - Дубль. На эту функцию прыгает из основного обработчика + DB low FN_RESERVED_5x ;#5D - Дубль. На эту функцию прыгает из основного обработчика + DB low FN_RESERVED_5x ;#5E - Дубль. На эту функцию прыгает из основного обработчика + DB low DRV_LIST ;#5F - Дубль. На эту функцию прыгает из основного обработчика EDUP ENDIF ENDM @@ -92,12 +92,12 @@ TAB_FNS: DB low FN_5x_Parser_8 ;#58 - Get Media parameters DB low FN_5x_Parser_9 ;#59 - Set Media parameters - DB low DRV_VERSION ;#5A - Version number - DB low FN_RESERVED_5x ;#5B - DB low FN_RESERVED_5x ;#5C - DB low FN_RESERVED_5x ;#5D - DB low FN_RESERVED_5x ;#5E - DB low DRV_CONFIG ;#5F - Configuration + DB low DRV_VERSION ;#5A - Version number + DB low FN_RESERVED_5x ;#5B + DB low FN_RESERVED_5x ;#5C + DB low FN_RESERVED_5x ;#5D + DB low FN_5x_Parser_E ;#5E + DB low DRV_LIST ;#5F ;-------------- ; 60 - #7F @@ -132,22 +132,22 @@ TAB_FNS: DB low EMM.GetMemPageNext ; #95 получить следующую страницу DB low EMM.GetBanksPorts ; #96 получить адреса портов DB low EMM.CheckColdInit ; #97 проверка на холодный старт и инициализации если он ;????? нужна ли как API? - DB low RAMD_CALC_PAGE ; #98 Fn 98h ;????? - DB low SET_DISK_TYPE ; #99 ;????? - DB low DISK_REDIR ; #9A ;????? + DB low RAMD_CALC_PAGE ; #98 Вычисление страницы и адреса в RAM-Disk по абсолютному номеру сектора + DB low SET_DISK_REDIR ; #99 Установить на текущий драйв переназначение (старая функция для TR-DOS!) ;????? + DB low GET_DISK_REDIR ; #9A Получить тип назначения на текущий драйв (старая функция для TR-DOS!) DB low GET_RAMD_NUM ; #9B получить номер ram disk по его block id - DB low FN_RESERVED ; #9C + DB low SWAP_RAM_DRIVES ; #9C сменить набор рамдисков ZX <-> Sp2000 DB low EMM.DivMemBlocks ; #9D разделения блока на два. DB low EMM.MergeMemBlocks ; #9E слияние двух блоков DB low EMM.FullInit ; #9F инициализация всей памяти, системных переменных ; Ax - DB low PIC_FN0 ; #A0 ОТКРЫТИЕ ОКНА - Fn 0A0h + DB low PIC_FN0_OpenWin ; #A0 ОТКРЫТИЕ ОКНА DB low PIC_FN1 ; #A1 ВЫВЕСТИ ТОЧКУ DB low PIC_FN2 ; #A2 ВЫВОД ЛИНИИ COPY DB low PIC_FN3 ; #A3 ВЫВОД ЛИНИИ FILL DB low PIC_SET_PAL ; #A4 ВЫВОД ПАЛИТРЫ DB low PIC_FN5 ; #A5 УСТАНОВКА RGMOD - DB low PIC_FN6 ; #A6 A - page_pal, E - номер палитры, B - тип палитры + DB low SET_PAL_INIT ; #A6 A - page_pal, E - номер палитры, B - тип палитры DB low PIC_FN7 ; #A7 Рисование линии одного цвета DB low PIC_FN8 ; #A8 Рисование разноцветной линии DB low PIC_FN9 ; #A9 нет @@ -209,7 +209,7 @@ TAB_FNS: DB low FN_LIB ; #DE DB low FN_LIB ; #DF ; Ex - DB low LP_PRINT_LINE_DIR ; #E0 + DB low LP_PR_LINE_DIR.START ; #E0 DB low FN_RESERVED ; #E1 DB low FN_RESERVED ; #E2 DB low FN_RESERVED ; #E3 @@ -228,19 +228,19 @@ TAB_FNS: ; Fx DB low RST_CONF.SP97_1 ; #F0 для совместимости с софтом Sp97 DB low RST_CONF.SP97_2 ; #F1 для совместимости с софтом Sp97 - DB low FN_SYNC ; #F2 - DB low RST_CONF.CUSTOM ; #F3 для совместимости с софтом Sp97 ;!TODO сделать её и для перезаливки конфы Sp2000 - DB low DCP_CONFIG ; #F4 + DB low FN_SYNC ; #F2 установка синхронизации + DB low RST_CONF.CUSTOM ; #F3 для совместимости с софтом Sp97 + DB low DCP_CONFIG ; #F4 функция распределения портов ; [x] DB low CMOS_TEST ; #F5 DB low CMOS_RD ; #F6 DB low CMOS_WR ; #F7 DB low SET_PORTS ; #F8 - DB low READ_PORTS ; #F9 !TODO - DB low WRITE_PORTS ; #FA !TODO - DB low GOTO_SPEC ; #FB Goto Spectrum! - DB low FN_RESERVED ; #FC + DB low READ_PORTS ; #F9 [x] 26/01/2024 + DB low FN_RESERVED ; #FA [x] 26/01/2024 не работала и не нужна, дублирует SET_PORTS + DB low GOTO_SPEC ; #FB Goto Spectrum! + DB low ZX_MEMORY_MANAGER ; #FC API для динамического выделения страниц Спектрума DB low REINIT ; #FD - DB low FN_RESERVED ; #FE SAVE_AUTOSTART ;!!!!! + DB low FN_RESERVED ; #FE SAVE_AUTOSTART. Есть в ZX_EXP.ASM DB low FN_VERSION ; #FF ;****************----------------------------************************----------------- @@ -288,15 +288,16 @@ TAB_FNS: DB high FN_RESERVED_5x DB high FN_RESERVED_5x DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high DRV_CONFIG -;-------------- + DB high FN_5x_Parser_E + DB high DRV_LIST +;-------------- ; 60 - #7F DUP #20 - DB high FN_RESERVED + DB high FN_RESERVED EDUP + ; 8x DB high LP_OPEN_S DB high LP_PRINT_ALL @@ -320,25 +321,25 @@ TAB_FNS: DB high EMM.GetMemRMD DB high EMM.FreeMemRMD DB high EMM.GetMemPageRMD - DB high EMM.GetMemPageNext + DB high EMM.GetMemPageNext DB high EMM.GetBanksPorts DB high EMM.CheckColdInit DB high RAMD_CALC_PAGE - DB high SET_DISK_TYPE - DB high DISK_REDIR - DB high FN_RESERVED - DB high FN_RESERVED + DB high SET_DISK_REDIR + DB high GET_DISK_REDIR + DB high GET_RAMD_NUM + DB high SWAP_RAM_DRIVES DB high EMM.DivMemBlocks DB high EMM.MergeMemBlocks DB high EMM.FullInit ; Ax - DB high PIC_FN0 + DB high PIC_FN0_OpenWin DB high PIC_FN1 DB high PIC_FN2 DB high PIC_FN3 DB high PIC_SET_PAL DB high PIC_FN5 - DB high PIC_FN6 + DB high SET_PAL_INIT DB high PIC_FN7 DB high PIC_FN8 DB high PIC_FN9 @@ -400,7 +401,7 @@ TAB_FNS: DB high FN_LIB DB high FN_LIB ; Ex - DB high LP_PRINT_LINE_DIR + DB high LP_PR_LINE_DIR.START DB high FN_RESERVED DB high FN_RESERVED DB high FN_RESERVED @@ -427,18 +428,37 @@ TAB_FNS: DB high CMOS_WR DB high SET_PORTS DB high READ_PORTS - DB high WRITE_PORTS - DB high GOTO_SPEC DB high FN_RESERVED + DB high GOTO_SPEC + DB high ZX_MEMORY_MANAGER DB high REINIT DB high FN_RESERVED DB high FN_VERSION +//////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////// +; +; ,----, ,----,. +; ,/ .`| ,' ,' | +; ,` .' : ,--, ,' .' | +; ; ; / ,---, ,--.'| ,----.' .' +; .'___,/ ,' ,---.'| | | : | | .' +; | : | | | : : : ' : : |--, ,--, ,--, +; ; |.'; ; ,--.--. : : : | ' | ,---. : | ;.' \|'. \/ .`| +; `----' | | / \ : |,-.' | | / \ | | |' \/ / ; +; ' : ;.--. .-. || : ' || | : / / | `----'.'\ ; \ \.' / +; | | ' \__\/: . .| | / :' : |__ . ' / | __ \ . | \ ; ; +; ' : | ," .--.; |' : |: || | '.'|' ; /| / /\/ / : / \ \ \ +; ; |.' / / ,. || | '/ :; : ;' | / | / ,,/ ',- ./__; ; \ +; '---' ; : .' \ : || , / | : | \ ''\ ;| :/\ \ ; +; | , .-./ \ / ---`-' \ \ / \ \ .' `---' `--` +; `--`---' `-'----' `----' `--`-,-' +//////////////////////////////////////////////////////////////////////////////////////// _mInfoALIGN 256,0 ;===========================================================[ 5x TABLE ] -TAB_5xFNS: - ; Drives Numbers: ; 0 FDD ; 1..5 reserved @@ -448,276 +468,306 @@ TAB_5xFNS: ; 9..B reserved ; C CDROM ; D..F reserved - -; Столбец - тип драйва -; строка - номер функции - +TAB_5xFNS: ; --< LOW PART >-- ;-------------------------------------------------------------[ FDD #0 ] ; - DB low FN_RESERVED_5x ;#50 - Дубль. На эту функцию прыгает из основного обработчика - DB low FDD_5x.RESET ;#51 - DB low FDD_5x.LONG_READ ;#52 - DB low FDD_5x.LONG_WRITE ;#53 - DB low FN_ABSENT_5x ;#54 - DB low FDD_5x.READ ;#55 - DB low FDD_5x.WRITE ;#56 - DB low FDD_5x.DETECT ;#57 - DB low FDD_5x.GETMED ;#58 - DB low FDD_5x.SETMED ;#59 + DB low FN_RESERVED_5x ;#50 - Дубль. На эту функцию прыгает из основного обработчика + DB low FDD_5x_RESET ;#51 + DB low FDD_5x_LONG_READ ;#52 + DB low FDD_5x_LONG_WRITE ;#53 + DB low FN_ABSENT_5x ;#54 + DB low FDD_5x_READ ;#55 + DB low FDD_5x_WRITE ;#56 + DB low FDD_5x_DETECT ;#57 + DB low FDD_5x_GET_PAR ;#58 + DB low FDD_5x_SET_PAR ;#59 - DB low DRV_VERSION ;#5A - Дубль. На эту функцию прыгает из основного обработчика - DB low FN_RESERVED_5x ;#5B - Дубль. На эту функцию прыгает из основного обработчика - DB low FN_RESERVED_5x ;#5C - Дубль. На эту функцию прыгает из основного обработчика - DB low FN_RESERVED_5x ;#5D - Дубль. На эту функцию прыгает из основного обработчика - DB low FN_RESERVED_5x ;#5E - Дубль. На эту функцию прыгает из основного обработчика - DB low DRV_CONFIG ;#5F - Дубль. На эту функцию прыгает из основного обработчика + DB low DRV_VERSION ;#5A - Дубль. На эту функцию прыгает из основного обработчика + DB low FN_RESERVED_5x ;#5B - Дубль. На эту функцию прыгает из основного обработчика + DB low FN_RESERVED_5x ;#5C - Дубль. На эту функцию прыгает из основного обработчика + DB low FN_RESERVED_5x ;#5D - Дубль. На эту функцию прыгает из основного обработчика + DB low FN_ABSENT_5x ;#5E - Дубль. На эту функцию прыгает из основного обработчика + DB low DRV_LIST ;#5F - Дубль. На эту функцию прыгает из основного обработчика ; ;---------------------------------------------------------------------[] - _mNoDrive_5xTable 5, 0 +;-----------------------------[ #1..#5 ] + _mNoDrive_5xTable 5, 0 +;-------------------------------------[] ;-------------------------------------------------------[ RAM DRIVE #6 ] ; - DB low FN_RESERVED_5x - DB low FN_ABSENT_5x - DB low RMD_5x.LONG_READ - DB low RMD_5x.LONG_WRITE - DB low FN_ABSENT_5x - DB low RMD_5x.READ - DB low RMD_5x.WRITE - DB low FN_ABSENT_5x - DB low RMD_5x.GETMED - DB low RMD_5x.SETMED + DB low FN_RESERVED_5x + DB low FN_ABSENT_5x + DB low RMD_5x_LONG_READ + DB low RMD_5x_LONG_WRITE + DB low FN_ABSENT_5x + DB low RMD_5x_READ + DB low RMD_5x_WRITE + DB low FN_ABSENT_5x + DB low RMD_5x_GET_PAR + DB low RMD_5x_SET_PAR - DB low DRV_VERSION - DB low FN_RESERVED_5x - DB low FN_RESERVED_5x - DB low FN_RESERVED_5x - DB low FN_RESERVED_5x - DB low DRV_CONFIG -; + DB low DRV_VERSION + DB low FN_RESERVED_5x + DB low FN_RESERVED_5x + DB low FN_RESERVED_5x + DB low FN_ABSENT_5x + DB low DRV_LIST ;---------------------------------------------------------------------[] - _mNoDrive_5xTable 1, 0 +;---------------------------------[ #7 ] + _mNoDrive_5xTable 1, 0 +;-------------------------------------[] -;-------------------------------------------------------------[ HDD #8 ] +;-------------------------------------------------------------[ ATA #8 ] ; - DB low FN_RESERVED_5x - DB low HDD_5x.RESET - DB low HDD_5x.LONG_READ - DB low HDD_5x.LONG_WRITE - DB low HDD_5x.VERIFY - DB low HDD_5x.READ - DB low HDD_5x.WRITE - DB low FN_ABSENT_5x - DB low HDD_5x.GETMED - DB low HDD_5x.SETMED + DB low FN_RESERVED_5x + DB low ATA_5x_RESET + DB low ATA_5x_LONG_READ + DB low ATA_5x_LONG_WRITE + DB low ATA_5x_VERIFY + DB low ATA_5x_READ + DB low ATA_5x_WRITE + DB low ATA_5x_DETECT + DB low ATA_5x_GET_PAR + DB low ATA_5x_SET_PAR - DB low DRV_VERSION - DB low FN_RESERVED_5x - DB low FN_RESERVED_5x - DB low FN_RESERVED_5x - DB low FN_RESERVED_5x - DB low DRV_CONFIG -; + DB low DRV_VERSION + DB low FN_RESERVED_5x + DB low FN_RESERVED_5x + DB low FN_RESERVED_5x + DB low FN_ABSENT_5x + DB low DRV_LIST ;---------------------------------------------------------------------[] - _mNoDrive_5xTable 3, 0 +;-----------------------------[ #9..#B ] + _mNoDrive_5xTable 3, 0 +;-------------------------------------[] -;----------------------------------------------------------[ CDROM #C0 ] +;-----------------------------------------------------------[ ATAPI #C ] ; - DB low FN_RESERVED_5x - DB low CD_5x.RESET - DB low CD_5x.LONG_READ - DB low FN_ABSENT_5x - DB low FN_ABSENT_5x - DB low CD_5x.READ - DB low FN_ABSENT_5x - DB low CD_5x.DETECT - DB low FN_ABSENT_5x - DB low FN_ABSENT_5x + DB low FN_RESERVED_5x + DB low ATAPI_5x_RESET + DB low ATAPI_5x_LONG_READ + DB low ATAPI_5x_LONG_WRITE ; [ ] new + DB low FN_ABSENT_5x ; VERIFY + DB low ATAPI_5x_READ + DB low ATAPI_5x_WRITE ; [ ] new + DB low ATAPI_5x_DETECT + DB low ATAPI_5x_GET_PAR ; [ ] new + DB low ATAPI_5x_SET_PAR ; SETMED - DB low DRV_VERSION - DB low FN_RESERVED_5x - DB low FN_RESERVED_5x - DB low FN_RESERVED_5x - DB low FN_RESERVED_5x - DB low DRV_CONFIG -; + DB low DRV_VERSION + DB low FN_RESERVED_5x + DB low FN_RESERVED_5x + DB low FN_RESERVED_5x + DB low ATAPI_5x_Extended ;[ ] media changed? ;!TODO + DB low DRV_LIST ;---------------------------------------------------------------------[] - _mNoDrive_5xTable 3, 0 -; +;-----------------------------[ #D..#F ] + _mNoDrive_5xTable 3, 0 +;-------------------------------------[] +; ; --< HIGH PART >-- ;-------------------------------------------------------------[ FDD #0 ] ; - DB high FN_RESERVED_5x ;#50 - Дубль. На эту функцию прыгает из основного обработчика - DB high FDD_5x.RESET ;#51 - DB high FDD_5x.LONG_READ ;#52 - DB high FDD_5x.LONG_WRITE ;#53 - DB high FN_ABSENT_5x ;#54 - DB high FDD_5x.READ ;#55 - DB high FDD_5x.WRITE ;#56 - DB high FDD_5x.DETECT ;#57 - DB high FDD_5x.GETMED ;#58 - DB high FDD_5x.SETMED ;#59 - - DB high DRV_VERSION ;#5A - Дубль. На эту функцию прыгает из основного обработчика - DB high FN_RESERVED_5x ;#5B - Дубль. На эту функцию прыгает из основного обработчика - DB high FN_RESERVED_5x ;#5C - Дубль. На эту функцию прыгает из основного обработчика - DB high FN_RESERVED_5x ;#5D - Дубль. На эту функцию прыгает из основного обработчика - DB high FN_RESERVED_5x ;#5E - Дубль. На эту функцию прыгает из основного обработчика - DB high DRV_CONFIG ;#5F - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_RESERVED_5x ;#50 - Дубль. На эту функцию прыгает из основного обработчика + DB high FDD_5x_RESET ;#51 + DB high FDD_5x_LONG_READ ;#52 + DB high FDD_5x_LONG_WRITE ;#53 + DB high FN_ABSENT_5x ;#54 + DB high FDD_5x_READ ;#55 + DB high FDD_5x_WRITE ;#56 + DB high FDD_5x_DETECT ;#57 + DB high FDD_5x_GET_PAR ;#58 + DB high FDD_5x_SET_PAR ;#59 + + DB high DRV_VERSION ;#5A - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_RESERVED_5x ;#5B - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_RESERVED_5x ;#5C - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_RESERVED_5x ;#5D - Дубль. На эту функцию прыгает из основного обработчика + DB high FN_ABSENT_5x ;#5E - Extended functions + DB high DRV_LIST ;#5F - Дубль. На эту функцию прыгает из основного обработчика ; ;---------------------------------------------------------------------[] - _mNoDrive_5xTable 5, 1 +;-----------------------------[ #1..#5 ] + _mNoDrive_5xTable 5, 1 +;-------------------------------------[] ;-------------------------------------------------------[ RAM DRIVE #6 ] ; - DB high FN_RESERVED_5x - DB high FN_ABSENT_5x - DB high RMD_5x.LONG_READ - DB high RMD_5x.LONG_WRITE - DB high FN_ABSENT_5x - DB high RMD_5x.READ - DB high RMD_5x.WRITE - DB high FN_ABSENT_5x - DB high RMD_5x.GETMED - DB high RMD_5x.SETMED + DB high FN_RESERVED_5x + DB high FN_ABSENT_5x + DB high RMD_5x_LONG_READ + DB high RMD_5x_LONG_WRITE + DB high FN_ABSENT_5x + DB high RMD_5x_READ + DB high RMD_5x_WRITE + DB high FN_ABSENT_5x + DB high RMD_5x_GET_PAR + DB high RMD_5x_SET_PAR - DB high DRV_VERSION - DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high DRV_CONFIG -; + DB high DRV_VERSION + DB high FN_RESERVED_5x + DB high FN_RESERVED_5x + DB high FN_RESERVED_5x + DB high FN_ABSENT_5x + DB high DRV_LIST ;---------------------------------------------------------------------[] - _mNoDrive_5xTable 1, 1 +;---------------------------------[ #7 ] + _mNoDrive_5xTable 1, 1 +;-------------------------------------[] -;-------------------------------------------------------------[ HDD #8 ] +;-------------------------------------------------------------[ ATA #8 ] ; - DB high FN_RESERVED_5x - DB high HDD_5x.RESET - DB high HDD_5x.LONG_READ - DB high HDD_5x.LONG_WRITE - DB high HDD_5x.VERIFY - DB high HDD_5x.READ - DB high HDD_5x.WRITE - DB high FN_ABSENT_5x - DB high HDD_5x.GETMED - DB high HDD_5x.SETMED + DB high FN_RESERVED_5x + DB high ATA_5x_RESET + DB high ATA_5x_LONG_READ + DB high ATA_5x_LONG_WRITE + DB high ATA_5x_VERIFY + DB high ATA_5x_READ + DB high ATA_5x_WRITE + DB high ATA_5x_DETECT + DB high ATA_5x_GET_PAR + DB high ATA_5x_SET_PAR - DB high DRV_VERSION - DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high DRV_CONFIG -; + DB high DRV_VERSION + DB high FN_RESERVED_5x + DB high FN_RESERVED_5x + DB high FN_RESERVED_5x + DB high FN_ABSENT_5x + DB high DRV_LIST ;---------------------------------------------------------------------[] - _mNoDrive_5xTable 3, 1 +;-----------------------------[ #9..#B ] + _mNoDrive_5xTable 3, 1 +;-------------------------------------[] -;----------------------------------------------------------[ CDROM #C0 ] +;-----------------------------------------------------------[ ATAPI #C ] ; - DB high FN_RESERVED_5x - DB high CD_5x.RESET - DB high CD_5x.LONG_READ - DB high FN_ABSENT_5x - DB high FN_ABSENT_5x - DB high CD_5x.READ - DB high FN_ABSENT_5x - DB high CD_5x.DETECT - DB high FN_ABSENT_5x - DB high FN_ABSENT_5x + DB high FN_RESERVED_5x + DB high ATAPI_5x_RESET + DB high ATAPI_5x_LONG_READ + DB high ATAPI_5x_LONG_WRITE ; LONG_WRITE ; [ ] new + DB high FN_ABSENT_5x + DB high ATAPI_5x_READ + DB high ATAPI_5x_WRITE ; WRITE ; [ ] new + DB high ATAPI_5x_DETECT + DB high ATAPI_5x_GET_PAR + DB high ATAPI_5x_SET_PAR ; SETMED - DB high DRV_VERSION - DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high FN_RESERVED_5x - DB high DRV_CONFIG -; + DB high DRV_VERSION + DB high FN_RESERVED_5x + DB high FN_RESERVED_5x + DB high FN_RESERVED_5x + DB high ATAPI_5x_Extended + DB high DRV_LIST ;---------------------------------------------------------------------[] - _mNoDrive_5xTable 3, 1 - -;=======================================================================; +;-----------------------------[ #D..#F ] + _mNoDrive_5xTable 3, 1 +;-------------------------------------[] +;======================================================================; ;************************************ ; Вход в функцию по RST18 и RST8 -EXP_FNS_RST18: - PUSH HL - LD L,C - LD H,high TAB_FNS - LD C,(HL) - INC H - LD H,(HL) - LD L,C - EX (SP),HL - RET +EXP_FNS_RST18: PUSH HL + LD L,C + LD H,high TAB_FNS + LD C,(HL) + INC H + LD H,(HL) + LD L,C + EX (SP),HL + RET -FN_5x_Parser_1: - LD C,1 - JP FN_5x_Parser -FN_5x_Parser_2: - LD C,2 - JP FN_5x_Parser -FN_5x_Parser_3: - LD C,3 - JP FN_5x_Parser -FN_5x_Parser_4: - LD C,4 - JP FN_5x_Parser -FN_5x_Parser_5: - LD C,5 - JP FN_5x_Parser -FN_5x_Parser_6: - LD C,6 - JP FN_5x_Parser -FN_5x_Parser_7: - LD C,7 - JP FN_5x_Parser -FN_5x_Parser_8: - LD C,8 - JP FN_5x_Parser -FN_5x_Parser_9: - LD C,9 -FN_5x_Parser: - PUSH HL - LD H,A - AND #F0 - OR C - ; тут в A номер УСТРОЙСТВА + НОМЕР ФУНКЦИИ - LD L,A - LD A,H - LD H,high TAB_5xFNS - LD C,(HL) - INC H - LD H,(HL) - LD L,C - EX (SP),HL - RET + ; ATA_5x_RESET + ; ATA_5x_LONG_READ + ; ATA_5x_LONG_WRITE + ; ATA_5x_VERIFY + ; ATA_5x_READ + ; ATA_5x_WRITE + ; ATA_5x_DETECT + ; ATA_5x_GET_PAR + ; ATA_5x_SET_PAR + ; DRV_VERSION + ; FN_RESERVED_5x + ; FN_RESERVED_5x + ; FN_RESERVED_5x + ; FN_RESERVED_5x + ; DRV_LIST -EXP_FNS: ; Вход в функцию из TR-DOS - POP AF +FN_5x_Parser_1: LD C,#01 ; ATA_5x_RESET + JR FN_5x_Parser +FN_5x_Parser_2: LD C,#02 ; ATA_5x_LONG_READ + JR FN_5x_Parser +FN_5x_Parser_3: LD C,#03 ; ATA_5x_LONG_WRITE + JR FN_5x_Parser +FN_5x_Parser_4: LD C,#04 ; ATA_5x_VERIFY + JR FN_5x_Parser +FN_5x_Parser_6: LD C,#06 ; ATA_5x_WRITE + JR FN_5x_Parser +FN_5x_Parser_7: LD C,#07 ; ATA_5x_DETECT + JR FN_5x_Parser +FN_5x_Parser_8: LD C,#08 ; ATA_5x_GET_PAR + JR FN_5x_Parser +FN_5x_Parser_9: LD C,#09 ; ATA_5x_SET_PAR + JR FN_5x_Parser +FN_5x_Parser_E: LD C,#0E ; DRV_EXTENDED + JR FN_5x_Parser +FN_5x_Parser_5: LD C,5 ; ATA_5x_READ +FN_5x_Parser: PUSH HL + LD H,A + AND #F0 + OR C + ; тут в A номер УСТРОЙСТВА + НОМЕР ФУНКЦИИ + LD L,A + LD A,H + LD H,high TAB_5xFNS + LD C,(HL) + INC H + LD H,(HL) + LD L,C + EX (SP),HL + RET + +; Вход в функции БИОС из TR-DOS +EXP_FNS:; отключаем запись в экран спектрума + ;EX (SP),HL + ;IN A,(RGADR) + ;LD L,A + ;LD A,#C0 + ;OUT (PORT_Y),A + ;LD A,H + ;EX (SP),HL ; (SP) = port_y + POP AF + ; CALL EXP_FNS_RST18 CALL DOS_ON + ; возвращаем запись в экран спектрума + ;EX (SP),HL + ;PUSH AF + ;LD A,L + ;OUT (RGADR),A + ;POP AF + ;POP HL + ; возврат JP EXP_FNS_RET ;! ! ! ! ! ! ! ! FN_RESERVED_5x: - LD A,1 ;!HARDCODE error code + LD A,BIOS.Error.InvalidSubFunction FN_RESERVED: SCF RET FN_ABSENT_5x: - LD A,#AA ;!HARDCODE error code + LD A,BIOS.Error.NotSupported SCF RET ;! ! ! ! ! ! ! ! diff --git a/src/bios/exp/DCP.ASM b/src/bios/exp/DCP.ASM index 9786e82..319cfd2 100644 --- a/src/bios/exp/DCP.ASM +++ b/src/bios/exp/DCP.ASM @@ -1,5 +1,5 @@ ;-----------------------------------------------------------------------; -; DATA FOR DCP +; DATA FOR DCPCollision between port #1F and CBL port fix ; вбиваем в таблицу DCP.XLSX нужный внешний порт, ; смотрим смещение для OUT (С),x - это адрес ; @@ -12,490 +12,498 @@ ; CCED/AAAAAAAAA ; NN1OW116517210 ; FF2SR54 3 -;DCP_DATA: 108 -; ....0..11.1110 -; WORD %00000001101110 ; - адрес -; WORD %00001001101111 ; - маска - 0 изменяемые биты, 1 неизменяемые -; BYTE Conf_port.Border_FE ; - порт +; 108 +;DCP_DATA: ....0..11.1110 +; WORD %00000001101110 ; - b13..12 cnf, b11 pent512, b10 dos, b9 r/w, b8..0 адрес +; WORD %00001001101111 ; - маска - 0 изменяемые биты, 1 неизменяемые +; BYTE ACEX.Border_FE ; - порт -; DCP END MARKER -; DW 0,0,0 ;-----------------------------------------------------------------------; ; - -; +.RECORD.Size EQU 5 ;-----------------------------------------------------------------------; -; VG93 Ports - DW %00000000000111 - DW %00010001101111 - DB Conf_port.VG93_1F - DW %11010000000111 - DW %11010001101111 - DB Conf_port.VG93_1F -;ok - DW %00000000100111 - DW %00010001101111 - DB Conf_port.VG93_3F - DW %11010000100111 - DW %11010001101111 - DB Conf_port.VG93_3F -;ok - DW %00000001000111 - DW %00010001101111 - DB Conf_port.VG93_5F - DW %11010001000111 - DW %11010001101111 - DB Conf_port.VG93_5F -;ok - DW %00000001100111 - DW %00010001101111 - DB Conf_port.VG93_7F - DW %11010001100111 - DW %11010001101111 - DB Conf_port.VG93_7F -;ok - DW %00000001101111 - DW %00011001101111 - DB Conf_port.VG93_State - DW %11010001101111 - DW %11011001101111 - DB Conf_port.VG93_State + DW %00'000'0'0000'0111 + DW %00'010'0'0110'1111 + DB ACEX.VG93_1F + DW %11'010'0'0000'0111 + DW %11'010'0'0110'1111 + DB ACEX.VG93_1F + + DW %00'000'0'0010'0111 + DW %00'010'0'0110'1111 + DB ACEX.VG93_3F + DW %11'010'0'0010'0111 + DW %11'010'0'0110'1111 + DB ACEX.VG93_3F + + DW %00'000'0'0100'0111 + DW %00'010'0'0110'1111 + DB ACEX.VG93_5F + DW %11'010'0'0100'0111 + DW %11'010'0'0110'1111 + DB ACEX.VG93_5F + + DW %00'000'0'0110'0111 + DW %00'010'0'0110'1111 + DB ACEX.VG93_7F + DW %11'010'0'0110'0111 + DW %11'010'0'0110'1111 + DB ACEX.VG93_7F + + DW %00'000'0'0110'1111 + DW %00'011'0'0110'1111 + DB ACEX.VG93_State + DW %11'010'0'0110'1111 + DW %11'011'0'0110'1111 + DB ACEX.VG93_State ; For joystick - DW %00011000000111 - DW %10011001101111 - DB Conf_port.JOY_VG93 - DW %10011000000111 - DW %11011001101111 - DB Conf_port.JOY_VG93 + DW %00'011'0'0000'0111 + DW %10'011'0'0110'1111 + DB ACEX.JOY_VG93 + DW %10'011'0'0000'0111 + DW %11'011'0'0110'1111 + DB ACEX.JOY_VG93 ; For VG93 with dos on - DW %00001001101111 - DW %00011001101111 - DB Conf_port.JOY_VG93 + DW %00'001'0'0110'1111 + DW %00'011'0'0110'1111 + DB ACEX.JOY_VG93 ; For VG93 with dos off - DW %11011001101111 - DW %11011001101111 - DB Conf_port.JOY_VG93 -;ok - DW %00000000101101 - DW %11011111111111 - DB Conf_port.FDD720 - DW %11000000101101 - DW %11001111111111 - DB Conf_port.FDD720 -;ok - DW %00000000111101 - DW %11011111111111 - DB Conf_port.FDD144 - DW %11000000111101 - DW %11001111111111 - DB Conf_port.FDD144 + DW %11'011'0'0110'1111 + DW %11'011'0'0110'1111 + DB ACEX.JOY_VG93 -;!FIXIT UNKNOWN PORTS--------------------------------------------------; dos on, только через BC, чтение/запись -;ok - DW %10000100101101 - DW %11010111111111 - DB #18 -;ok - DW %10000100111101 - DW %11010111111111 - DB #19 -;ok - DW %10000110101101 - DW %11010111111111 - DB #1A + DW %00'000'0'0010'1101 + DW %11'011'1'1111'1111 + DB ACEX.FDD720 + DW %11'000'0'0010'1101 + DW %11'001'1'1111'1111 + DB ACEX.FDD720 + + DW %00'000'0'0011'1101 + DW %11'011'1'1111'1111 + DB ACEX.FDD144 + DW %11'000'0'0011'1101 + DW %11'001'1'1111'1111 + DB ACEX.FDD144 + +;!FIXIT UNKNOWN PORTS ( Z84? ) ----------------------------------------; dos on, только через BC, чтение/запись + DW %10'000'1'0010'1101 + DW %11'010'1'1111'1111 + DB #18 + + DW %10'000'1'0011'1101 + DW %11'010'1'1111'1111 + DB #19 + + DW %10'000'1'1010'1101 + DW %11'010'1'1111'1111 + DB #1A ;----------------------------------------------------------------------; -;ok - DW %00000100101101 - DW %11001111111111 - DB #1B - DW %10000110111101 - DW %11010111111111 - DB #1B - DW %11000100101101 - DW %11001111111111 - DB #1B -;ok - DW %00001100111101 - DW %11001101111111 - DB #1C - DW %11001100111101 - DW %11001101111111 - DB #1C -;ok - DW %00000110101101 - DW %11001111111111 - DB #1D - DW %11000110101101 - DW %11001111111111 - DB #1D -;ok - DW %00000100111101 - DW %11001101111111 - DB #1E - DW %11000100111101 - DW %11001101111111 - DB #1E -;ok - DW %00000001000000 - DW %11000001101111 - DB #20 - DW %01000001000000 - DW %11010001101111 - DB #20 -;ok - DW %10000001000000 - DW %11010001101111 - DB #20 - DW %11000001000000 - DW %11000001101111 - DB #20 + DW %00'000'1'0010'1101 + DW %11'001'1'1111'1111 + DB ACEX.ISA_CTRL + DW %10'000'1'1011'1101 + DW %11'010'1'1111'1111 + DB ACEX.ISA_CTRL + DW %11'000'1'0010'1101 + DW %11'001'1'1111'1111 + DB ACEX.ISA_CTRL -;ok - DW %00000001000001 - DW %00010111101111 - DB #21 - DW %00010001000001 - DW %11010111101111 - DB #21 - DW %11010001000001 - DW %11010111101111 - DB #21 -;ok - DW %00000001000010 - DW %00010111101111 - DB #22 - DW %00010001000010 - DW %11010111101111 - DB #22 - DW %11010001000010 - DW %11010111101111 - DB #22 -;ok - DW %00000001000011 - DW %00010111101111 - DB #23 - DW %00010001000011 - DW %11010111101111 - DB #23 - DW %11010001000011 - DW %11010111101111 - DB #23 -;ok - DW %00000001000100 - DW %00010111101111 - DB #24 - DW %00010001000100 - DW %11010111101111 - DB #24 - DW %11010001000100 - DW %11010111101111 - DB #24 + DW %00'001'1'0011'1101 + DW %11'001'1'0111'1111 + DB ACEX.CMOS_DATA.READ + DW %11'001'1'0011'1101 + DW %11'001'1'0111'1111 + DB ACEX.CMOS_DATA.READ -;ok - DW %00000001000101 - DW %00010111101111 - DB #25 - DW %00010001000101 - DW %11010111101111 - DB #25 - DW %11010001000101 - DW %11010111101111 - DB #25 + DW %00'000'1'1010'1101 + DW %11'001'1'1111'1111 + DB ACEX.CMOS_ADDR.WRITE + DW %11'000'1'1010'1101 + DW %11'001'1'1111'1111 + DB ACEX.CMOS_ADDR.WRITE -;ok - DW %00000011000010 - DW %00010111101111 - DB #26 - DW %00010011000010 - DW %11010111101111 - DB #26 - DW %11010011000010 - DW %11010111101111 - DB #26 -;ok - DW %00000011000011 - DW %00010111101111 - DB #27 - DW %00010011000011 - DW %11010111101111 - DB #27 - DW %11010011000011 - DW %11010111101111 - DB #27 -;ok - DW %00000011000100 - DW %00010111101111 - DB Conf_port.IDE_CONTROL_3F6 - DW %00010011000100 - DW %11010111101111 - DB Conf_port.IDE_CONTROL_3F6 - DW %11010011000100 - DW %11010111101111 - DB Conf_port.IDE_CONTROL_3F6 -;ok - DW %00000011000101 - DW %00010111101111 - DB Conf_port.IDE_STATUS_3F7 - DW %00010011000101 - DW %11010111101111 - DB Conf_port.IDE_STATUS_3F7 - DW %11010011000101 - DW %11010111101111 - DB Conf_port.IDE_STATUS_3F7 -;ok - DW %00000000101100 - DW %11001111111111 - DB Conf_port.IDE_CHANEL_1 - DW %11000000101100 - DW %11001111111111 - DB Conf_port.IDE_CHANEL_1 -;ok - DW %00000000111100 - DW %11001111111111 - DB Conf_port.IDE_CHANEL_2 - DW %11000000111100 - DW %11001111111111 - DB Conf_port.IDE_CHANEL_2 -;ok - DW %00000010101101 - DW %11001111111111 - DB Conf_port.VSYNC320 - DW %11000010101101 - DW %11001111111111 - DB Conf_port.VSYNC320 -;ok - DW %00000010111101 - DW %11001111111111 - DB Conf_port.VSYNC312 - DW %11000010111101 - DW %11001111111111 - DB Conf_port.VSYNC312 -;ok - DW %00000010101100 - DW %11001111111111 - DB Conf_port.RESET - DW %11000010101100 - DW %11001111111111 - DB Conf_port.RESET -;ok - DW %00000010111100 - DW %11001111111111 - DB Conf_port.UNKNOWN ;!FIXIT можно пока убрать - DW %11000010111100 - DW %11001111111111 - DB Conf_port.UNKNOWN ;!FIXIT можно пока убрать -;ok - DW %00010000101011 - DW %11010001101011 - DB Conf_port.ISA_Control -;ok - DW %00011001101110 - DW %10011001101111 - DB Conf_port.ZX_Keyboard - DW %10011001101110 - DW %11011001101111 - DB Conf_port.ZX_Keyboard -;ok - DW %00001111111101 - DW %00001111111111 - DB Conf_port.AY_FFFD_READ -;ok - DW %00001111011111 - DW %11001111111111 - DB Conf_port.Kempston_Mouse - DW %11001111011111 - DW %11001111111111 - DB Conf_port.Kempston_Mouse -;ok - DW %00011001100011 - DW %11011001101111 - DB Conf_port.CBL_OUT - DW %01010001100011 - DW %11010001101111 - DB Conf_port.CBL_OUT - DW %10010001100011 - DW %11010001101111 - DB Conf_port.CBL_OUT - DW %00010000000111 - DW %11011000001111 - DB Conf_port.CBL_OUT - DW %00011000001000 - DW %11011001101111 - DB Conf_port.CBL_OUT - DW %00010001101011 - DW %10010001101111 - DB Conf_port.CBL_OUT - DW %10010001101011 - DW %11010001101111 - DB Conf_port.CBL_OUT -;ok - DW %00000001000110 - DW %11001111111111 - DB Conf_port.CBL_SYS_PORT - DW %11000001000110 - DW %11001111111111 - DB Conf_port.CBL_SYS_PORT -;ok - DW %00000111111101 - DW %00001111111111 - DB Conf_port.AY_FFFD_WRITE -;ok - DW %00000101111101 - DW %00001111111111 - DB Conf_port.AY_BFFD -;ok - DW %00000001101101 - DW %10000111111111 - DB Conf_port.Scorp_1FFD - DW %11000001101101 - DW %11000111111111 - DB Conf_port.Scorp_1FFD -;ok - DW %00000011101101 - DW %00100111101111 - DB Conf_port.Pent_7FFD - DW %00100011101101 - DW %11110111101111 - DB Conf_port.Pent_7FFD - DW %11100011101101 - DW %11100111101111 - DB Conf_port.Pent_7FFD - DW %10000001101101 - DW %11100111101111 - DB Conf_port.Pent_7FFD -;ok - DW %00000001101110 - DW %00001001101111 - DB Conf_port.Border_FE -;ok - DW %00000001010110 - DW %11001111111111 - DB Conf_port.ALL_MODE - DW %11000001010110 - DW %11001111111111 - DB Conf_port.ALL_MODE -;ok - DW %00000000001001 - DW %00010001101111 - DB Conf_port.PORT_Y - DW %00010000001001 - DW %11010001101111 - DB Conf_port.PORT_Y - DW %11010000001001 - DW %11010001101111 - DB Conf_port.PORT_Y -;ok - DW %00000001001001 - DW %00010001101111 - DB Conf_port.RGMOD - DW %00010001001001 - DW %11010001101111 - DB Conf_port.RGMOD - DW %11010001001001 - DW %11010001101111 - DB Conf_port.RGMOD -;ok - DW %00000000100100 - DW %00000000101111 - DB Conf_port.CNF_PORT + DW %00'000'1'0011'1101 + DW %11'001'1'0111'1111 + DB ACEX.CMOS_DATA.WRITE + DW %11'000'1'0011'1101 + DW %11'001'1'0111'1111 + DB ACEX.CMOS_DATA.WRITE +; +;---------HDD[v] + DW %00'000'0'0100'0000 + DW %11'000'0'0110'1111 + DB ACEX.IDE_DATA_1F0 + DW %01'000'0'0100'0000 + DW %11'010'0'0110'1111 + DB ACEX.IDE_DATA_1F0 + DW %10'000'0'0100'0000 + DW %11'010'0'0110'1111 + DB ACEX.IDE_DATA_1F0 + DW %11'000'0'0100'0000 + DW %11'000'0'0110'1111 + DB ACEX.IDE_DATA_1F0 -;!FIXIT можно убрать - DW %00000001101100 - DW %11001001101111 - DB Conf_port.SCALE - DW %11000001101100 - DW %11001001101111 - DB Conf_port.SCALE -;------------------------------ + DW %00'000'0'0100'0001 + DW %00'010'1'1110'1111 + DB ACEX.IDE_ERROR_1F1 + DW %00'010'0'0100'0001 + DW %11'010'1'1110'1111 + DB ACEX.IDE_ERROR_1F1 + DW %11'010'0'0100'0001 + DW %11'010'1'1110'1111 + DB ACEX.IDE_ERROR_1F1 -;ok - DW %00000000001010 - DW %00010001101111 - DB #E8 - DW %00010000001010 - DW %11010001101111 - DB #E8 - DW %11010000001010 - DW %11010001101111 - DB #E8 -;ok - DW %00000000101010 - DW %00010001101111 - DB #E9 - DW %00010000101010 - DW %11010001101111 - DB #E9 - DW %11010000101010 - DW %11010001101111 - DB #E9 + DW %00'000'0'0100'0010 + DW %00'010'1'1110'1111 + DB ACEX.IDE_COUNTER_1F2 + DW %00'010'0'0100'0010 + DW %11'010'1'1110'1111 + DB ACEX.IDE_COUNTER_1F2 + DW %11'010'0'0100'0010 + DW %11'010'1'1110'1111 + DB ACEX.IDE_COUNTER_1F2 -;ok - DW %00000001001010 - DW %00010001101111 - DB #EA - DW %00010001001010 - DW %11010001101111 - DB #EA - DW %11010001001010 - DW %11010001101111 - DB #EA -;ok - DW %00000001101010 - DW %00010001101111 - DB #F0 - DW %00010001101010 - DW %11010001101111 - DB #F0 - DW %11010001101010 - DW %11010001101111 - DB #F0 -; DCP END MARKER - DW 0,0,0 + DW %00'000'0'0100'0011 + DW %00'010'1'1110'1111 + DB ACEX.IDE_SECTOR_1F3 + DW %00'010'0'0100'0011 + DW %11'010'1'1110'1111 + DB ACEX.IDE_SECTOR_1F3 + DW %11'010'0'0100'0011 + DW %11'010'1'1110'1111 + DB ACEX.IDE_SECTOR_1F3 + + DW %00'000'0'0100'0100 + DW %00'010'1'1110'1111 + DB ACEX.IDE_CYLINDER_L_1F4 + DW %00'010'0'0100'0100 + DW %11'010'1'1110'1111 + DB ACEX.IDE_CYLINDER_L_1F4 + DW %11'010'0'0100'0100 + DW %11'010'1'1110'1111 + DB ACEX.IDE_CYLINDER_L_1F4 + + DW %00'000'0'0100'0101 + DW %00'010'1'1110'1111 + DB ACEX.IDE_CYLINDER_H_1F5 + DW %00'010'0'0100'0101 + DW %11'010'1'1110'1111 + DB ACEX.IDE_CYLINDER_H_1F5 + DW %11'010'0'0100'0101 + DW %11'010'1'1110'1111 + DB ACEX.IDE_CYLINDER_H_1F5 + + DW %00'000'0'1100'0010 + DW %00'010'1'1110'1111 + DB ACEX.IDE_DEVICE_HEAD_1F6 + DW %00'010'0'1100'0010 + DW %11'010'1'1110'1111 + DB ACEX.IDE_DEVICE_HEAD_1F6 + DW %11'010'0'1100'0010 + DW %11'010'1'1110'1111 + DB ACEX.IDE_DEVICE_HEAD_1F6 + + DW %00'000'0'1100'0011 + DW %00'010'1'1110'1111 + DB ACEX.IDE_STATUS_CMD_1F7 + DW %00'010'0'1100'0011 + DW %11'010'1'1110'1111 + DB ACEX.IDE_STATUS_CMD_1F7 + DW %11'010'0'1100'0011 + DW %11'010'1'1110'1111 + DB ACEX.IDE_STATUS_CMD_1F7 +;---------HDD[^] +; + DW %00'000'0'1100'0100 + DW %00'010'1'1110'1111 + DB ACEX.IDE_CONTROL_3F6 + DW %00'010'0'1100'0100 + DW %11'010'1'1110'1111 + DB ACEX.IDE_CONTROL_3F6 + DW %11'010'0'1100'0100 + DW %11'010'1'1110'1111 + DB ACEX.IDE_CONTROL_3F6 + + DW %00'000'0'1100'0101 + DW %00'010'1'1110'1111 + DB ACEX.IDE_STATUS_3F7 + DW %00'010'0'1100'0101 + DW %11'010'1'1110'1111 + DB ACEX.IDE_STATUS_3F7 + DW %11'010'0'1100'0101 + DW %11'010'1'1110'1111 + DB ACEX.IDE_STATUS_3F7 + + DW %00'000'0'0010'1100 + DW %11'001'1'1111'1111 + DB ACEX.IDE_CHANEL_1 + DW %11'000'0'0010'1100 + DW %11'001'1'1111'1111 + DB ACEX.IDE_CHANEL_1 + + DW %00'000'0'0011'1100 + DW %11'001'1'1111'1111 + DB ACEX.IDE_CHANEL_2 + DW %11'000'0'0011'1100 + DW %11'001'1'1111'1111 + DB ACEX.IDE_CHANEL_2 + + DW %00'000'0'1010'1101 + DW %11'001'1'1111'1111 + DB ACEX.VSYNC320 + DW %11'000'0'1010'1101 + DW %11'001'1'1111'1111 + DB ACEX.VSYNC320 + + DW %00'000'0'1011'1101 + DW %11'001'1'1111'1111 + DB ACEX.VSYNC312 + DW %11'000'0'1011'1101 + DW %11'001'1'1111'1111 + DB ACEX.VSYNC312 + + DW %00'000'0'1010'1100 + DW %11'001'1'1111'1111 + DB ACEX.RESET + DW %11'000'0'1010'1100 + DW %11'001'1'1111'1111 + DB ACEX.RESET + + DW %00'000'0'1011'1100 + DW %11'001'1'1111'1111 + DB ACEX.UNKNOWN ;!FIXIT можно пока убрать + DW %11'000'0'1011'1100 + DW %11'001'1'1111'1111 + DB ACEX.UNKNOWN ;!FIXIT можно пока убрать + + DW %00'010'0'0010'1011 + DW %11'010'0'0110'1011 + DB ACEX.ISA_Control + + DW %00'011'0'0110'1110 + DW %10'011'0'0110'1111 + DB ACEX.ZX_Keyboard + DW %10'011'0'0110'1110 + DW %11'011'0'0110'1111 + DB ACEX.ZX_Keyboard + + DW %00'001'1'1111'1101 + DW %00'001'1'1111'1111 + DB ACEX.AY_FFFD_READ + + DW %00'001'1'1101'1111 + DW %11'001'1'1111'1111 + DB ACEX.Kempston_Mouse + DW %11'001'1'1101'1111 + DW %11'001'1'1111'1111 + DB ACEX.Kempston_Mouse + + + ;-1F 0001 1111 x00x 0111 + ; 3F 0011 1111 x01x 0111 + ; 4F 0100 1111 x10x 0111 + ; 5F 0101 1111 x10x 0111 + ;+DF 1101 1111 x10x 1111 drum + ; DD 1101 1101 x10x 1101 scorp + ; FB 1111 1011 x11x 1011 + DW %00'011'0'0110'0011 + DW %11'011'0'0110'1111 + DB ACEX.CBL_OUT + DW %01'010'0'0110'0011 + DW %11'010'0'0110'1111 + DB ACEX.CBL_OUT + DW %10'010'0'0110'0011 + DW %11'010'0'0110'1111 + DB ACEX.CBL_OUT + DW %10'010'0'0110'1011 + DW %11'010'0'0110'1111 + DB ACEX.CBL_OUT + ; [x] Collision between ports #1F and CBL fix + ; DW %00'010'0'0000'0111 + ; DW %11'011'0'0000'1111 + ; DB ACEX.CBL_OUT + DW %00'010'0'0010'0111 + DW %11'011'0'0010'1111 + DB ACEX.CBL_OUT + DW %00'010'0'0100'0111 + DW %11'011'0'0100'1111 + DB ACEX.CBL_OUT + ; + DW %00'011'0'0000'1000 + DW %11'011'0'0110'1111 + DB ACEX.CBL_OUT + DW %00'010'0'0110'1011 + DW %10'010'0'0110'1111 + DB ACEX.CBL_OUT + + + DW %00'000'0'0100'0110 + DW %11'001'1'1111'1111 + DB ACEX.CBL_SYS_PORT + DW %11'000'0'0100'0110 + DW %11'001'1'1111'1111 + DB ACEX.CBL_SYS_PORT + + DW %00'000'1'1111'1101 + DW %00'001'1'1111'1111 + DB ACEX.AY_FFFD_WRITE + + DW %00'000'1'0111'1101 + DW %00'001'1'1111'1111 + DB ACEX.AY_BFFD + + DW %00'000'0'0110'1101 + DW %10'000'1'1111'1111 + DB ACEX.Scorp_1FFD + DW %11'000'0'0110'1101 + DW %11'000'1'1111'1111 + DB ACEX.Scorp_1FFD + + DW %00'000'0'1110'1101 + DW %00'100'1'1110'1111 + DB ACEX.Pent_7FFD + DW %00'100'0'1110'1101 + DW %11'110'1'1110'1111 + DB ACEX.Pent_7FFD + DW %11'100'0'1110'1101 + DW %11'100'1'1110'1111 + DB ACEX.Pent_7FFD + DW %10'000'0'0110'1101 + DW %11'100'1'1110'1111 + DB ACEX.Pent_7FFD + + DW %00'000'0'0110'1110 + DW %00'001'0'0110'1111 + DB ACEX.Border_FE + + DW %00'000'0'0101'0110 + DW %11'001'1'1111'1111 + DB ACEX.ALL_MODE + DW %11'000'0'0101'0110 + DW %11'001'1'1111'1111 + DB ACEX.ALL_MODE + + DW %00'000'0'0000'1001 + DW %00'010'0'0110'1111 + DB ACEX.PORT_Y + DW %00'010'0'0000'1001 + DW %11'010'0'0110'1111 + DB ACEX.PORT_Y + DW %11'010'0'0000'1001 + DW %11'010'0'0110'1111 + DB ACEX.PORT_Y + + DW %00'000'0'0100'1001 + DW %00'010'0'0110'1111 + DB ACEX.RGMOD + DW %00'010'0'0100'1001 + DW %11'010'0'0110'1111 + DB ACEX.RGMOD + DW %11'010'0'0100'1001 + DW %11'010'0'0110'1111 + DB ACEX.RGMOD + + DW %00'000'0'0010'0100 + DW %00'000'0'0010'1111 + DB ACEX.CNF_PORT + + DW %00'000'0'0110'1100 + DW %11'001'0'0110'1111 + DB ACEX.SCALE + DW %11'000'0'0110'1100 + DW %11'001'0'0110'1111 + DB ACEX.SCALE + + DW %00'000'0'0000'1010 + DW %00'010'0'0110'1111 + DB ACEX.SLOT0 + DW %00'010'0'0000'1010 + DW %11'010'0'0110'1111 + DB ACEX.SLOT0 + DW %11'010'0'0000'1010 + DW %11'010'0'0110'1111 + DB ACEX.SLOT0 + + DW %00'000'0'0010'1010 + DW %00'010'0'0110'1111 + DB ACEX.SLOT1 + DW %00'010'0'0010'1010 + DW %11'010'0'0110'1111 + DB ACEX.SLOT1 + DW %11'010'0'0010'1010 + DW %11'010'0'0110'1111 + DB ACEX.SLOT1 + + DW %00'000'0'0100'1010 + DW %00'010'0'0110'1111 + DB ACEX.SLOT2 + DW %00'010'0'0100'1010 + DW %11'010'0'0110'1111 + DB ACEX.SLOT2 + DW %11'010'0'0100'1010 + DW %11'010'0'0110'1111 + DB ACEX.SLOT2 + + DW %00'000'0'0110'1010 + DW %00'010'0'0110'1111 + DB ACEX.SLOT3 + DW %00'010'0'0110'1010 + DW %11'010'0'0110'1111 + DB ACEX.SLOT3 + DW %11'010'0'0110'1010 + DW %11'010'0'0110'1111 + DB ACEX.SLOT3 + ; DCP END MARKER + DW 0,0,0 ;-----------------------------------------------------------------------; ; ; ;----------------------------------------------------------------------; -DCP_INIT: - LD C,XL - LD B,XH - LD E,YL - LD D,YH - EXX - - LD HL,#C000 - LD DE,#C001 - LD BC,#3FFF - LD (HL),L - LDIR - - LD IY,DCP_DATA - LD IX,.ret - -.loop: LD L,(IY) - LD H,(IY+1) - LD E,(IY+2) - LD D,(IY+3) - LD B,(IY+4) - JP DCP_CONFIG.PARSE_TABLE - -.ret: LD BC,5 - ADD IY,BC - LD A,(IY+2) - OR (IY+3) - JR NZ,.loop - - EXX - LD XL,C - LD XH,B - LD YL,E - LD YH,D +; вызывается из POST_TEST.POST_3_INIT_DCP +DCP_INIT: LD E,YL + LD D,YH + EX DE,HL + LD E,XL + LD D,XH + ; + LD BC,DCP_DATA.RECORD.Size + EXX + LD HL,#C000 + LD DE,#C001 + LD BC,#3FFF + LD (HL),L + LDIR + ; + LD IY,DCP_DATA + LD IX,.ret + ; +.loop: LD L,(IY) + LD H,(IY+1) + LD E,(IY+2) + LD D,(IY+3) + LD B,(IY+4) + JP DCP_CONFIG.PARSE_TABLE + ; +.ret: EXX + ADD IY,BC + EXX + LD A,(IY+2) + OR (IY+3) + JR NZ,.loop + EXX + LD XL,E + LD XH,D + EX DE,HL + LD YL,E + LD YH,D ; First IN command - OPEN DCP - IN A,(SLOT3) - JP (HL) + IN A,(SLOT3) + JP POST_TEST.POST_3_OK ;-----------------------------------------------------------------------; ; @@ -510,8 +518,8 @@ DCP_CONFIG: AND A JP Z,PORTS_INIT - LD A,R - DI + LD A,R + DI PUSH AF PUSH IX @@ -532,7 +540,6 @@ DCP_CONFIG: RET PO EI RET - .PARSE_TABLE: LD A,L AND E @@ -588,56 +595,94 @@ DCP_CONFIG: ;-----------------------------------------------------------------------; ; +;----------------------------------------------------------------------; +;[x] 26/01/2024 +READ_PORTS: + CALL SET_PORTS.Prepare + LD BC,0 + IN B,(C) + JR SET_PORTS.End + +;[x] 26/01/2024 +; WRITE_PORTS: +; SCF +; RET +;----------------------------------------------------------------------; + ; ;-----------------------------------------------------------------------; -; CALL from 3D13h! Осторожнее с прерываниями, лучше гасить, чтоб не сбить сигнал DOS_ON +;[x] Теперь это не нужно: CALL from 3D13h! Осторожнее с прерываниями, лучше гасить, чтоб не сбить сигнал DOS_ON ; in: A - внутренний порт, B - значение для записи во внутренний порт -; out: B - старое значение внутреннего порта; Перед выходом восстанавливается конфа прописанная в CONFIG_DE +; out: B - старое значение внутреннего порта; Перед выходом восстанавливается конфа прописанная в CONFIG_DE. SET_PORTS: - EX AF,AF' - LD A,CNF_PORT.CNF_0 + ROM.BIOS - OUT (SYS_PORT.ROM),A - - LD C,SLOT2 ; получить страницу - IN D,(C) - - LD A,DCP_PAGE ; установить новую - OUT (C),A - - LD A,(#8000) ; сохранить то что было - LD L,A - LD A,(#8200) - LD H,A - EX AF,AF' ; страница - - LD (#8000),A ; установить внутренний порт - LD (#8200),A - - EX AF,AF' - LD A,B - LD BC,0 - EX AF,AF' - - IN A,(C) - - EX AF,AF' - OUT (C),A ; установить новое значение порта - EX AF,AF' - - LD B,A - LD A,L - LD (#8000),A ; вернуть порт - LD A,H - LD (#8200),A ; вернуть порт - - LD C,SLOT2 - LD A,SYS_PAGE - OUT (C),A - LD A,(SYS_PAGE.CONFIG_DE-#4000) - OUT (C),D ; вернуть страницу - OUT (SYS_PORT.ROM),A - - AND A - RET + CALL .Prepare + ; + EX AF,AF' + LD A,B + LD BC,0 + EX AF,AF' + ; + ; Чтение порта + IN A,(C) + ; Запись порта + EX AF,AF' + OUT (C),A ; установить новое значение порта + EX AF,AF' + ; + LD B,A ; прошлое состояние порта + ; +.End: LD A,DCP_PAGE ; установить DCP + LD C,SLOT2 + OUT (C),A + LD A,L + LD (#8000),A ; вернуть порт + LD A,H + LD (#8200),A ; вернуть порт + ; + LD A,SYS_PAGE + OUT (C),A + LD A,(SYS_PAGE.CONFIG_DE-#4000) + OUT (C),D ; вернуть страницу + OUT (SYS_PORT.ROM),A + ; + CALL DOS_OFF + ; + ;[x] SET_PORTS: no need to call from #3D13 and DI. 31/12/23 + BIT 2,E + RET Z + EI + RET + ;AND A + ;RET + ; +.Prepare: + EX AF,AF' + ;[x] SET_PORTS: no need to call from #3D13 and DI. 31/12/23 + AND A + LD A,R + PUSH AF + POP DE + DI + CALL DOS_ON + ; + LD A,CNF_PORT.CNF_0 + ROM.BIOS + OUT (SYS_PORT.ROM),A + ; + LD C,SLOT2 ; получить страницу + IN D,(C) + ; + LD A,DCP_PAGE ; установить новую + OUT (C),A + ; + LD A,(#8000) ; сохранить то что было + LD L,A + LD A,(#8200) + LD H,A + EX AF,AF' ; страница + ; + LD (#8000),A ; установить внутренний порт + LD (#8200),A + OUT (C),D ; вернуть страницу + RET ;-----------------------------------------------------------------------; ; \ No newline at end of file diff --git a/src/bios/exp/EXP.asm b/src/bios/exp/EXP.asm index 9c721ae..9d28266 100644 --- a/src/bios/exp/EXP.asm +++ b/src/bios/exp/EXP.asm @@ -2,10 +2,13 @@ ; ;************************************************************* ; -; EXPANSION VER 3.00 (C) Peters Plus Ltd. +; EXPANSION VER 3.00 (C) Peters Plus Ltd. +; EXPANSION VER 3.1 (C) Sprinter Team ; ;************************************************************* + DISPLAY "\r\n/=====================[EXP part]=====================\\" + ;*************************************** ;*********** BEGIN EXPANSION *********** ;*************************************** @@ -14,9 +17,12 @@ EXP_START: JP GLOBAL_RESET ;--------------------------------------- -ROM_NUMBER: -.part1: DW MotherBoardID ; MotherBoardID -.part2: DB 0 +;ROM_NUMBER: +;.part1: DW MotherBoardID +;.part2: DB 0 +BOARD_INFO: +.number: DW MotherBoardID +.type: DB MotherBoardType ;--------------------------------------- ;--------------------------------------- @@ -48,7 +54,7 @@ RST_10: JP EXP_FNS_RST18 RST_18_1: CALL EXP_FNS_RST18 - JR EXP_FNS_2_RET +.exit: JR EXP_FNS_2_RET ;======================================= @@ -70,10 +76,44 @@ RST_30: ;======================================= BLOCK #38-$,0 ; INTERUPT Point -RST38: - EI - RETI +RST38: IF TEST_INT + ;INT: + PUSH BC + PUSH AF + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + + LD A,(SYS_PAGE.INT_ID) + CP #AA + JR Z,YESINT + OUT (C),B + JP NOINT +YESINT: PUSH HL + LD HL,(SYS_PAGE.INT_ADRESS) + LD A,H + OR L + LD A,(SYS_PAGE.INT_PAGE) + OUT (C),B + PUSH DE + CALL NZ,EXTINT + POP DE + POP HL +NOINT: POP AF + POP BC + EI + RETI + ELSE + +; PUSH AF +; 1: DEC A +; JR NZ,1B +; POP AF + EI + RETI + ENDIF ;RST10: ; CALL_48 10h ; RET @@ -81,28 +121,35 @@ RST38: ;======================================= + IFN TEST_INT _mInfoALIGN #10,0 -;TABLE_X EQU #A0 ; any adress < #C0 with mask %xxxx0000 -; BLOCK TABLE_X-$ -TABLE_X: ; таблица для Sprinter POST-Tester-a -.v0: DB 00101000b ; "0" -.v1: DB 10111101b ; "1" -.v2: DB 00110010b ; "2" -.v3: DB 00110100b ; "3" -.v4: DB 10100101b ; "4" -.v5: DB 01100100b ; "5" -.v6: DB 01100000b ; "6" -.v7: DB 00111101b ; "7" -.v8: DB 00100000b ; "8" -.v9: DB 00100100b ; "9" -.vA: DB 00100001b ; "A" -.vB: DB 11100000b ; "B" -.vC: DB 01101010b ; "C" -.vD: DB 10110000b ; "D" -.vE: DB 01100010b ; "E" -.vF: DB 01100011b ; "F" +; any adress < #C0 with mask %xxxx0000 +; таблица для Sprinter POST-Tester-a +TABLE_X: +.v0: DB %00101000 ; "0" a +.v1: DB %10111101 ; "1" ___ +.v2: DB %00110010 ; "2" f | g | b +.v3: DB %00110100 ; "3" |___| +.v4: DB %10100101 ; "4" e | | c +.v5: DB %01100100 ; "5" |___|. +.v6: DB %01100000 ; "6" d +.v7: DB %00111101 ; "7" +.v8: DB %00100000 ; "8" a - 7 +.v9: DB %00100100 ; "9" b - 6 +.vA: DB %00100001 ; "A" . - 5 +.vB: DB %11100000 ; "B" f - 4 +.vC: DB %01101010 ; "C" g - 3 +.vD: DB %10110000 ; "D" e - 2 +.vE: DB %01100010 ; "E" c - 1 +.vF: DB %01100011 ; "F" d - 0 + ENDIF ;======================================= -RESTARTS EQU #FFE0 ; !FIXIT вынести в SP2000.inc +; + +; +;======================================= + IFN TEST_INT +RESTARTS EQU #FFE0 GLOBAL_RESET: DI IM 1 @@ -117,16 +164,15 @@ GLOBAL_RESET: INC DE DJNZ .compare JP RESTARTS + ENDIF ;======================================= _mInfoBLOCK #66-$,0 - NMI_Point: ; резерв 3 байта для команды JP ;NOP ;NOP ;NOP RETN - ;======================================= ;SET_BIOS_TO_RAM: ; программа работает на адресе 0C000h @@ -165,25 +211,32 @@ NMI_Point: ; POP DE ; POP HL ; RET - ;======================================= ; BLOCK MEM_MAP.ID_Version-$,0 ;#C0-$,0 -ID_Version: - dw bitstream_ver_hex ; Version of bitstream hex -ID_SPRINTER_length: - DB ID_SPRINTER.LENGTH - -ID_SPRINTER: - DB 'Hardware v' -.bitstream_ver: - DB bitstream_ver_string,0 - DB 'Sprinter',0 - DB 0 -.LENGTH EQU $-ID_SPRINTER +ID_Version: DW BIOS_ver_hex +ID_SPRINTER: DB 'Firmware v' +.BIOS_ver: DB BIOS_ver_string + IF BETA_BUILD > 0 + DB " ", BETA_str_ver + ELSE + IF RELEASEhotFIX > 0 + DB ReleaseHotFix + ENDIF + ENDIF + DB 0 +.Record1_Size EQU $-ID_SPRINTER + ; запись 2 + DB 'Sprinter',0 + ; запись 3 ; [x] 24/02/2024 +.bitstream_ver: DB bitstream_ver_string,0 + DB 0 + ; +.Size EQU $-ID_SPRINTER +.Records_Num EQU 3 ; Check for max length of string - ASSERT ID_SPRINTER.LENGTH < #20, 'ERROR! ID String is to long!' + ASSERT ID_SPRINTER.Record1_Size < SYS_PAGE.ID_FLAG.Size, 'ERROR! ID String is to long!' ;======================================= @@ -191,83 +244,204 @@ ID_SPRINTER: BoardID: .start: WORD BoardID_start ; BoardID_start .end: WORD BoardID_end ; BoardID_end - -; ;======================================= -; BLOCK #100-$,0 +;#######################################################################; -; RESTARTS EQU #FFE0 ; !FIXIT вынести в SP2000.inc -; GLOBAL_RESET: -; DI -; IM 1 -; LD HL,RESTARTS -; LD DE,RESTARTS_PROG -; LD B,RESTARTS_PROG.Size -; .compare: -; LD A,(DE) -; CP (HL) -; JR NZ,NO_RESTART -; INC HL -; INC DE -; DJNZ .compare -; JP RESTARTS +;#######################################################################; +;-----------------------------------------------------------------------; +; ROM-Disk pages ; [x] активирован ROM-DISK +ROM_DISK.Pages.Number: + BYTE ROM_DISK.Pages.Size ; число страниц +; у страниц выставлен bit4 для корректной подстановки +;(подробнее в sp2000.inc - Порт управления страницами ПЗУ) +ROM_DISK.Pages: ; страницы ROM-Disk + ABYTE #10 #05,#06,#07,#09,#0A,#0B ; 98304 bytes +.Size EQU $-ROM_DISK.Pages +;-----------------------------------------------------------------------; +;#######################################################################; -;-----[перехват RESET не состоялся]----- + + +;======================================= + IF TEST_INT + _mInfoALIGN #10,0 +; any adress < #C0 with mask %xxxx0000 +; таблица для Sprinter POST-Tester-a +TABLE_X: +.v0: DB %00101000 ; "0" a +.v1: DB %10111101 ; "1" ___ +.v2: DB %00110010 ; "2" f | g | b +.v3: DB %00110100 ; "3" |___| +.v4: DB %10100101 ; "4" e | | c +.v5: DB %01100100 ; "5" |___|. +.v6: DB %01100000 ; "6" d +.v7: DB %00111101 ; "7" +.v8: DB %00100000 ; "8" a - 7 +.v9: DB %00100100 ; "9" b - 6 +.vA: DB %00100001 ; "A" . - 5 +.vB: DB %11100000 ; "B" f - 4 +.vC: DB %01101010 ; "C" g - 3 +.vD: DB %10110000 ; "D" e - 2 +.vE: DB %01100010 ; "E" c - 1 +.vF: DB %01100011 ; "F" d - 0 + ENDIF +;======================================= ; + +; +;======================================= + IF TEST_INT +RESTARTS EQU #FFE0 +; полный перехват ресета сразу после проливки конфы и CAD. +; закидывается в карту портов, поэтому использовать надо хитро. +GLOBAL_RESET: + DI + IM 1 + LD HL,RESTARTS + LD DE,RESTARTS_PROG + LD B,RESTARTS_PROG.Size +.compare: + LD A,(DE) + CP (HL) + JR NZ,NO_RESTART + INC HL + INC DE + DJNZ .compare + JP RESTARTS + ENDIF +;======================================= +; + +; +;-----[перехват RESET не состоялся]----- NO_RESTART: ; стек ещё не используем!!! LD SP,IX ; сохранить значение переданное загрузчиком конфы (если старт после ресета) - ; инициализация внутренних портов Z84C15 для POST-Tester-а LD A,5 ; COM port for Printer OUT OUT (Z84.SIO.Ch_A.Ctrl),A LD A,#62 OUT (Z84.SIO.Ch_A.Ctrl),A - + ; LD A,#CF ; BITS I/O OUT (Z84.PIO.Port_A.Command),A XOR A OUT (Z84.PIO.Port_A.Command),A OUT (Z84.PIO.Port_A.Data),A ; PRINTER - PORT - all zeros + ; -инициализация системных портов Z84C15- + LD BC,#FF*256 + Z84.SYS.Control + XOR A ; Z84.REG.WaitState_Ctrl + OUT (C),A ; Z84.SYS.Control + INC C ; Z84.REG.WaitState_MemBound + OUT (C),A ; Z84.SYS.Data ; set 0 Waits + ; + DEC C + LD A,3 ; Z84.REG.Misc_Ctrl + OUT (C),A ; Z84.SYS.Control + INC C + ; no boundary set! + ;XOR A ; disable CS0, disable CS1 + LD A,1 ; enable CS0, disable CS1 + OUT (C),A ; Z84.SYS.Data + JP POST_TEST.START +;--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--== + IF TEST_INT +;----------------[int]------------------ +EXTINT: OR A + RET Z - ; -инициализация системных портов Z84C15- - LD BC,#FF*256 + Z84.SYS.Control - XOR A - OUT (C),A ; 0 register - waits - INC C - OUT (C),A ; set 0 Waits + BIT 7,H + JR Z,.L2 + LD C,SLOT2 + BIT 6,H + JR Z,.L1 + LD C,SLOT3 - DEC C +.L1: IN B,(C) + PUSH BC + OUT (C),A + CALL .JPHL + POP BC + OUT (C),B + RET + ; проверка на нулевой слот +.L2: BIT 6,H + LD C,SLOT1 + JR NZ,.L1 ; продолжаем если ненулевой слот - LD A,3 ; 3-rd register - Misc.Control Register - OUT (C),A - INC C - XOR A ; !FIXIT читать доку на Z84, выбрать занчение для A - LD A,1 ; !FIXIT читать доку на Z84, выбрать занчение для A - OUT (C),A ; enable CS0, disable CS1 - JP POST_TEST.START -; no boundary set! -; + PUSH HL + LD HL,-.stackDepth - .switchProcedure.size + .patch-2 + ADD HL,SP + PUSH HL + LD HL,-.stackDepth - .switchProcedure.size ; memory stack use! + ADD HL,SP ; stack + PUSH HL ; адрес программы .readProcedure -; -;----------------------------[ FOR ZX-MODE ]----------------------------; - IF BIOS_ZXMODE -;!HARDCODE на этот адрес #С0 прыгает в vROM Basic-48 по адресу #3CF0 -; можно попробовать переделать этот адрес там - _mInfoBLOCK #C0-$,0 -;BEGIN: -; Вход через USR 15600 -RET_FROM_BIOS_TO_BASIC48: - CALL CH_2 - CALL COMAND_LINE ; ВЫПОЛНЕНИЕ КОМАНДЫ, ЕСЛИ ЕСТЬ - ; Вход без команды - JP SW_ROM_1 ; ВОЗВРАТ В << MAIN MENU >> + LD DE,.switchProcedure ; перенести программу на стек + EX DE,HL + LD BC,.switchProcedure.size + LDIR + RET + +; процедура, переносимая на стек для вызова прерывания пользователя из SLOT0 +; осторожнее с PUSH, если надо много, то увеличивай .stackDepth +.switchProcedure: + DEC DE + POP HL + LD (HL),E + INC HL + LD (HL),D + + LD C,SLOT0 + IN B,(C) + POP HL + PUSH BC + OUT (C),A + + XOR A + OUT (SYS_PORT.RAM),A + +.patch EQU $+1-.switchProcedure + CALL .JPHL + + DI + + XOR A + OUT (SYS_PORT.ROM),A + + POP BC + OUT (C),B + + RET +.JPHL: JP (HL) +.stackDepth EQU 64 ; расстояние от конца процедуры до вершины стека. +.switchProcedure.size EQU $-.switchProcedure ENDIF -;-----------------------------------------------------------------------; +;--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--==--== + ; ==== POST PROCs ================= +; LPT 0 - start +; post 1. TEST RAM BUS +; IF ERROR -> ERROR RAM BUS - CODE 'X'X'X'X... - высветить номер ошибочного бита +; LPT 1 - post 1 OK +; post 2 TEST ADRESS BUS +; IF ERROR -> ошибка адреса CODE 'XXXX - вывести старший байт с запятой, пауза, вывести младший без запятой +; LPT 2 - post 2 OK +; post 3 init DCP +; no errors +; LPT 3 - post 3 OK +; post 4 TEST RAM PAGES запись в порт страницы, чтение записанного +; IF ERROR -> ошибка переключения Port-а CODE 'XX - вывод байта записанного в порт +; LPT 4 - post 4 OK +; post 5 проверка чистоты шины данных Z84C15 +; IF ERROR -> ERROR CODE '_'XX - в биосе на ошибке не зависает, хз почему, может на случай конфы с грязной шиной спектрума +; LPT 5 - post 5 OK +; LPT 4 - post 5 error - старый биос +; LPT F - post 5 error - биос 05/04/2025))) +; MODULE POST_TEST START: ; ********************************* @@ -283,9 +457,7 @@ POST_1_RAM_BUS: LD BC,0 LD HL,#C000 LD DE,#0055 - -.loop: - LD (HL),E +.loop: LD (HL),E INC L LD (HL),D DEC L @@ -324,7 +496,7 @@ POST_1_RAM_BUS: ; высветить номер ошибочного бита LD A,(HL) - AND %11011111 ; с запятыми + AND %1101'1111 ; с запятыми OUT (Z84.PIO.Port_A.Data),A ; пауза @@ -345,7 +517,7 @@ POST_1_RAM_BUS: ; бесконечный цикл INC L LD A,L - AND #AF + AND +(TABLE_X or #0F) ;%1010'1111 LD L,A JR .ERB_2 @@ -354,14 +526,14 @@ POST_1_RAM_BUS: ; ************************************************ POST_1_OK: - LD A,(TABLE_X.v1) ; высветить "1" ;rdlow-ok + LD A,(TABLE_X.v1) ; высветить "1" ;rdlow-ok OUT (Z84.PIO.Port_A.Data),A ; ===== TEST ADRESS BUS ====== POST_2_ADRESS_BUS: LD HL,#C000 LD DE,#0000 -.fill_mem: ; заполнить память адресами +.fill_mem: ; заполнить память адресами LD (HL),E INC L LD (HL),D @@ -374,7 +546,7 @@ POST_2_ADRESS_BUS: DEC HL DEC DE DEC DE -.check_mem: ; проверить совпадение +.check_mem: ; проверить совпадение LD A,(HL) CP D JR NZ,.error @@ -394,14 +566,14 @@ POST_2_ADRESS_BUS: .error: .TSAB_4: LD C,D - LD B,11011111b + LD B,%1101'1111 LD IX,.TSAB_3 - JR OUT_C_BYTE ; вывести старший байт с запятой + JR OUT_C_BYTE ; вывести старший байт с запятой .TSAB_3: LD C,E - LD B,0FFh + LD B,%1111'1111 LD IX,.TSAB_4 - JR OUT_C_BYTE ; вывести младший без запятой + JR OUT_C_BYTE ; вывести младший без запятой ; ===== OUT BYTE PROGRAM ======= @@ -467,13 +639,13 @@ OUT_C_BYTE: ; ************************************************ POST_2_OK: - LD A,(TABLE_X.v2) ;rdlow-ok - OUT (Z84.PIO.Port_A.Data),A ; вывести "2" + LD A,(TABLE_X.v2) ;rdlow-ok + OUT (Z84.PIO.Port_A.Data),A ; вывести "2" ; ===== INIT DCP ======== POST_3_INIT_DCP: - LD HL,POST_3_OK ; INIT PORTS - JP DCP_INIT ; процедура инициализации с возвратом в (HL) + ;LD HL,POST_3_OK ; INIT PORTS + JP DCP_INIT ; процедура инициализации с возвратом на POST_3_OK ; ошибок нет ; *********************************** @@ -481,27 +653,27 @@ POST_3_INIT_DCP: ; *********************************** POST_3_OK: - LD A,(TABLE_X.v3) ; вывести "3" ;rdlow-ok + LD A,(TABLE_X.v3) ; вывести "3" ;rdlow-ok OUT (Z84.PIO.Port_A.Data),A ; ===== TEST RAM PAGES == IN A,(SLOT3) - EX AF,AF' ; запомнить + EX AF,AF' ; запомнить POST_4_PAGES: LD B,0 .loop: LD A,#FF LD I,A LD A,B OUT (SLOT3),A - LD A,0 + XOR A LD I,A IN A,(SLOT3) CP B - JR NZ,.error ; если ошибка переключения Port-а + JR NZ,.error ; если ошибка переключения Port-а DJNZ .loop EX AF,AF' - OUT (SLOT3),A ; восстановить + OUT (SLOT3),A ; восстановить JR POST_4_OK ; *********************************** @@ -509,7 +681,7 @@ POST_4_PAGES: .error: LD C,B LD IX,.error_out_ret .error_out_ret: - LD B,11011111b + LD B,%1101'1111 JP OUT_C_BYTE ; *********************************** @@ -517,27 +689,34 @@ POST_4_PAGES: ; *********************************** POST_4_OK: - LD A,(TABLE_X.v4) ;rdlow-ok - OUT (Z84.PIO.Port_A.Data),A ; высветить "4" + LD A,(TABLE_X.v4) ;rdlow-ok + OUT (Z84.PIO.Port_A.Data),A ; высветить "4" ;= проверка чистоты шины данных Z84C15 = POST_5_DATA_BUS: LD B,0 .loop: IN A,(0) CP #FF -; JR NZ,.error ;!!!!! посмотреть + IF ERROR_POST_5 + JR NZ,.error ;!!!!! посмотреть + ELSE + JR NZ,POST_5_ERROR + ENDIF DJNZ .loop + LD A,(TABLE_X.v5) ;rdlow-ok JR POST_5_OK - + ; + ; + IF ERROR_POST_5 ; ERROR CODE '_'XX .error: LD C,A .erb1: LD IX,.erbr1 - LD B,%11011111 + LD B,%1101'1111 JP OUT_C_BYTE .erbr1: - LD A,%11011111 + LD A,%1101'1111 OUT (Z84.PIO.Port_A.Data),A LD DE,0 @@ -547,393 +726,397 @@ POST_5_DATA_BUS: OR E JR NZ,.LOOP_WTT4 JR .erb1 + ENDIF ; ********************************** ; ===== Point 5 ========= ; ********************************** + IFN ERROR_POST_5 +POST_5_ERROR: + LD A,(TABLE_X.vF) ;rdlow-ok + ENDIF POST_5_OK: - LD A,(TABLE_X.v5) ;rdlow-ok - OUT (Z84.PIO.Port_A.Data),A ; вывести "5" - + OUT (Z84.PIO.Port_A.Data),A ; вывести "5" ; ********************************** ; POST завершен -; ********************************** ENDMODULE +; ********************************** +;-----------------------------------------------------------------------; +; первая инициализация страниц: + XOR A + OUT (RGADR),A + OUT (RGMOD),A + OUT (SLOT0),A + ;free zx pages! + ;LD A,ZX_PAGE.SLOT1 + ;OUT (SLOT1),A + ;LD A,ZX_PAGE.SLOT2 + ;OUT (SLOT2),A + OUT (SLOT2),A ; ZERO_PAGE + DEC A ; SHARED_PAGE + OUT (SLOT1),A + ; + LD A,SYS_PAGE + OUT (SLOT3),A +;-----------------------------------------------------------------------; MODULE SET_CONFIG_ID - - IN A,(SLOT3) - EX AF,AF' ; SAVE PAGE3 - -;NO_SUMX_EQ: - - LD A,SYS_PAGE - OUT (SLOT3),A - ;-------------[Save IX:IY]-------------- ; Don't use IY before this point if it`s normal booting!!! - LD IX,0 - AND A - ADD IX,SP ; восстановить значение переданное загрузчиком конфы (если старт после ресета) -; + LD IX,0 + XOR A + ADD IX,SP ; восстановить значение переданное загрузчиком конфы (если старт после ресета) ; В этом месте у нас IX:IY из Loader.asm -; -; Дотащили до сюда метку от лоадера, пока не используется -; !TODO number from loader - ; LD A,YL - ; LD L,A - ; LD A,YH - ; LD H,A - ; LD BC,#0107 ; !!!!! сравнить с 0107h вынести референсом тут и в loader.asm - ; AND A ; если равно - прошла перезагрузка - ; SBC HL,BC - ;JR Z,set_config ;!TODO активация метки IX:IY из лоадера - - ;!TEST - ;LD IX,#FFFD ; LD IX,#FFFD ; !!!!! Sprinter-2 вынести референсом тут и в loader.asm - LD HL,#FEFF ; LD IX,#FEFF ; !!!!! Sprinter-2 вынести референсом тут и в loader.asm - ; -set_config: - LD (SYS_PAGE.CONFIG_BYTE),HL ; сохранить номер прошивки - ;LD (SYS_PAGE.CONFIG_BYTE),IX ; сохранить номер прошивки - ;LD HL,(SYS_PAGE.CONFIG_BYTE) ; взять номер прошивки в HL - ; - LD A,CNF_PORT.CNF_0 + CNF_PORT.TURBO.ON - LD (SYS_PAGE.CONFIG_DE),A - - EX AF,AF' - OUT (SLOT3),A ; Restore SLOT3 - +; Дотащили до сюда метку от лоадера + ;[x] 31/12/2023 подстраховка от недоутечки памяти + ; IY - number from loader + LD D,YH + LD E,YL + EX DE,HL + LD DE,SP2000_Loader_Flag + SBC HL,DE + JR NZ,.no_conf_reload + ; IX - number from loader + LD D,XH + LD E,XL + EX DE,HL + LD DE,ACEX.Config_ID.Sp2000 + SBC HL,DE + ; A = 0 + JR NZ,.no_conf_reload + LD A,#80 +.no_conf_reload: + LD R,A ; reg R bit7 - признак запуска с отработкой лоадера конфы + ; + ; на всякий случай + LD HL,ACEX.Config_ID.Sp2000 + LD (SYS_PAGE.CONFIG_BYTE),HL ; сохранить номер прошивки + ; + LD A,CNF_PORT.CNF_0 + CNF_PORT.TURBO.ON + LD (SYS_PAGE.CONFIG_DE),A + ; ENDMODULE -;********************************* -; первая инициализация страниц: -; SLOT3=0, SLOT2=2, SLOT1=5, SLOT0=0 - - XOR A - OUT (RGADR),A - OUT (RGMOD),A - OUT (SLOT3),A - OUT (SLOT0),A - LD A,5 - OUT (SLOT1),A - LD A,2 - OUT (SLOT2),A - -;********************************* +;-----------------------------------------------------------------------; ; Don't use stack (SP) before this point if it`s normal booting!!! - LD SP,#BFFE ; Начало использования стека!!! - PUSH HL ; сохранить номер прошивки + LD SP,ROM_MAP.EXP.STACK ; Начало использования стека!!! + PUSH HL ; сохранить номер прошивки - CALL PORTS_INIT ; инициализировать порты + CALL PORTS_INIT ; инициализировать порты XOR A OUT (BorderColor),A - CALL EMM.CheckColdInit ; инициализация памяти - - POP HL ; конфигурация - JR Reset_Handler.start -; ************************************* -; Считаем, что вход в SETUP всегда !!! -; ************************************* - -; LD A,H -; CP #FF -; JR NZ,NO_SETUP_1 -; LD A,L - - -; JR NZ,NO_SETUP_2 - - MODULE Reset_Handler -start: - IN A,(SLOT3) - push af + CALL EMM.CheckColdInit ; инициализация памяти + POP HL ; конфигурация +; JR Reset_Handler.start +;-----------------------------------------------------------------------; + MODULE Reset_Handler +start: DI ;----[перехват soft reset #EE port]----- -Check_EE_Port: - - LD A,Conf_port.RET_PORT - LD B,0 - LD C,BIOS.SET_PORTS - CALL @ToBIOS_3D13 ; переустановить внутр. порт #EE - LD A,B - AND A - jr z,Check_Spec_Page - - DI - OUT (SLOT3),A ; Set restart page - +Check_EE_Port: LD A,ACEX.RET_PORT + LD B,0 + ;[x] SET_PORTS: no need to call from #3D13 and DI. 31/12/23 + ;LD C,BIOS.SET_PORTS + ;CALL @ToBIOS_3D13 ; переустановить внутр. порт #EE + CALL SET_PORTS + ; + ; [x] 20/10/2024 игнор перехватчика по клавише 0 + LD A,high ZXKeys.Line_4 + IN A,(ZXKeys) + RRCA + JR NC,No_Reset_handlers + ; + LD A,B + AND A + JR Z,Check_Spec_Page + ; + OUT (SLOT3),A ; Set restart page .After_Hard_Rst: - - LD HL,(#FFF4) ; prog address - ld a,(#FFF0) ; PAGE0 - OUT (SLOT0),A - LD A,(#FFF1) ; PAGE1 - OUT (SLOT1),A - LD A,(#FFF2) ; PAGE2 - OUT (SLOT2),A - LD A,(#FFF3) ; PAGE3 - OUT (SLOT3),A - - jp (HL) + LD HL,(Spec_Page.RET_addr) ; prog address + LD A,(Spec_Page.page_0) ; PAGE0 + OUT (SLOT0),A + LD A,(Spec_Page.page_1) ; PAGE1 + OUT (SLOT1),A + LD A,(Spec_Page.page_2) ; PAGE2 + OUT (SLOT2),A + LD A,(Spec_Page.Reload_Version) + CP #FF + JR Z,.JPHL ; olg logic + ; new logic +.ver_2: LD SP,(Spec_Page.Stack_Point) + AND A + LD A,#FF + LD (Spec_Page.Reload_Version),A + LD A,(Spec_Page.page_3) ; PAGE3 + OUT (SLOT3),A + JR Z,.JPHL + PUSH HL + JP EXP_FNS_2_RET +.JPHL: JP (HL) ; ;--[перехват soft/hard reset #41 page]-- Check_Spec_Page: - LD A,Spec_Page - OUT (SLOT3),A - LD A,(#FFFE) - CP 'Z' - JR NZ,No_Reset_handlers - LD A,(#FFFF) - CP 'X' - JR NZ,No_Reset_handlers - - LD A,(#FFF7) - CP 'R' - JR NZ,Spec_Page_handler_OK - LD A,(#FFF8) - CP 'S' - JR NZ,Spec_Page_handler_OK - LD A,(#FFF9) - CP 'T' - JR NZ,Spec_Page_handler_OK - - XOR A - LD (#FFF7),A - - JR Check_EE_Port.After_Hard_Rst + LD A,Spec_Page + OUT (SLOT3),A + ; Check for hardreset flag + LD A,(Spec_Page.flag_R) + CP 'R' + JR NZ,No_Reset_handlers + LD A,(Spec_Page.flag_S) + CP 'S' + JR NZ,No_Reset_handlers + LD A,(Spec_Page.flag_T) + CP 'T' + JR NZ,No_Reset_handlers + ; + XOR A + LD (Spec_Page.flag_R),A + JR Check_EE_Port.After_Hard_Rst + ; ;--------------------------------------- No_Reset_handlers: -init_rom_address EQU #8200 ;!HARDCODE - - ld hl,init_zx_roms - ld de,init_rom_address - ld bc,init_zx_roms.length - ldir - - call init_rom_address - - LD HL,#C000 - LD DE,#C001 - LD BC,#3FFF - LD (HL),C - LDIR ; забить FF-ами - - ; ставим метку если прогрузили ПЗУ спектрума - LD A,'X' - LD (DE),A - DEC DE - LD A,'Z' - LD (DE),A - -;!FIXIT сделать выбор грузить да/нет ПЗУ спектрума при старте, [-------] -; если нет - то воткнуть этот код: - ; LD HL,PROG_NO_ROM - ; LD DE,#C000 + #38 - ; LD BC,PROG_NO_ROM.size - ; LDIR - - ; LD HL,RAM_BIOS_PROG - ; LD DE,#C000 + #08 - ; LD BC,RAM_BIOS_PROG.Length - ; LDIR -;[---------------------------------------------------------------------] - -Spec_Page_handler_OK: - pop af - OUT (SLOT3),A - + XOR A ;!HARDCODE zx page number + OUT (SLOT3),A ENDMODULE -; -;************************************** -; - MODULE Prepare_For_Setup +;-----------------------------------------------------------------------; -Set_ALL_Mode: - LD A,#FF - LD BC,Port_All_Mode - OUT (C),A + MODULE Prepare_For_Setup +Set_ALL_Mode: LD A,Port_All_Mode.DEFAULT + LD BC,Port_All_Mode + OUT (C),A Set_Default_Screen: - CALL FN_SYNC.INT_DEF ; set default int - ld a,128+4 ; !HARDCODE - ;ld c,BIOS.FN_SYNC - ;RST ToBIOS_18 ; set default vsync - CALL FN_SYNC ; set default vsync -Setup_to_RAM: - LD HL,Setup_Starter.Start - LD DE,COMPILE_ADDR.SETUP_STARTER - LD BC,Setup_Starter.Length - LDIR - -; на стек кладётся адрес возврата и дальше тащится всякими костылями, чтоб вернуться назад - CALL Setup_Starter.Exec ; #C000 - - JP ZX_SPECTRUM_MODE ; выход в режим zx spectrum - + CALL FN_SYNC.INT_DEF ; set default int + LD A,128+4 ; !HARDCODE + CALL FN_SYNC ; set default vsync +Setup_to_RAM: LD HL,Setup_Starter.Start + LD DE,COMPILE_ADDR.SETUP_STARTER + LD BC,Setup_Starter.Size + LDIR + ; на стек кладётся адрес возврата и дальше тащится всякими костылями, чтоб вернуться назад + CALL Setup_Starter.Exec ; #C000 + ;JP PrepareToZX ENDMODULE + +;PrepareToZX: ; Setup HDD drives for ZX Spectrum mode +; DI +; LD D,CMOS_CELL.TRDOSmount +; CALL CMOS_RD +; AND %1010'1010 ; маска для 4-х HDD +; JR Z,.start_zx +; ; find first good partition +; ; + +; ; чистка переменных ZX HDD +; IN A,(SLOT3) +; EX AF,AF +; LD A,SYS_PAGE +; OUT (SLOT3),A +; ; +; XOR A +; LD H,A +; LD L,A +; LD (SYS_PAGE.CURRENT_DIR_SEC_L),HL +; LD (SYS_PAGE.CURRENT_DIR_SEC_H),HL +; DEC A +; LD (SYS_PAGE.CURRENT_HDD),A +; LD (SYS_PAGE.CURRENT_DIR_DRIVE),A +; LD (SYS_PAGE.CURRENT_DIR_DRIVE_COPY),A +; ; +; EX AF,AF +; OUT (SLOT3),A +; EX AF,AF +; ; +; XOR A +; .loop: PUSH AF +; CALL FN_HDD_PART +; POP BC +; JR NC,.start_zx +; LD A,B +; INC A +; CP #10 +; JR C,.loop + ; выход в режим zx spectrum +.start_zx: + ; IF FREE_ZX_PAGES + ; не должно сюда попасть + LD B,high BIOS.REINIT.HARD_RESET + JP REINIT + ; ELSE ; [x] free zx pages! + ; XOR A + ; OUT (SLOT2),A ; ZERO_PAGE + ; DEC A + ; OUT (SLOT1),A ; SHARED_PAGE + ; ;LD A,5 + ; ;OUT (SLOT1),A + ; ;LD A,2 + ; ;OUT (SLOT2),A + ; ; + ; JP GOTO_SPEC.ZX_MODE + ; ENDIF ;*********************************** ; Инициализация портов PORTS_INIT: -; включить TURBO - LD A,CNF_PORT.TURBO.ON + CNF_PORT.CNF_0 - OUT (SYS_PORT.ROM),A - -; RESET to ISA - LD BC,ISA_PORT - LD A,#FF - OUT (C),A -.isa_reset: - DEC A - JR NZ,.isa_reset - OUT (C),A - -; Инициализация последовательного порта клавиатуры - XOR A ;LD A,0 - OUT (Z84.SIO.Ch_A.Ctrl),A - - INC A ;LD A,1 - OUT (Z84.SIO.Ch_A.Ctrl),A - DEC A ;LD A,0 ; #18 включение прерываний - OUT (Z84.SIO.Ch_A.Ctrl),A - - LD A,3 - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,#C1 - OUT (Z84.SIO.Ch_A.Ctrl),A - - LD A,4 - OUT (Z84.SIO.Ch_A.Ctrl),A - -; ????? 5/7 паритет? -; LD A,5 - LD A,7 - OUT (Z84.SIO.Ch_A.Ctrl),A - - LD A,5 - OUT (Z84.SIO.Ch_A.Ctrl),A - LD A,#62 ;60, 61 - OUT (Z84.SIO.Ch_A.Ctrl),A - -;--------[Clean keyboard buffer]-------- -.clean_kbd_buf: - IN A,(Z84.SIO.Ch_A.Ctrl) - BIT 0,A - jr z,.mouse - IN A,(Z84.SIO.Ch_A.Data) - jr .clean_kbd_buf + ; включить TURBO + LD A,CNF_PORT.CNF_0 + CNF_PORT.TURBO.ON + OUT (SYS_PORT.ROM),A + ; ; RESET to ISA + ; LD BC,PORT_ISA + ; LD A,#FF + ; OUT (C),A + ; .isa_reset: + ; DEC A ;!FIXIT может убрать цикл ожидания и запулить 0 в ису после инита клавы? + ; JR NZ,.isa_reset + ; OUT (C),A + ; + ; Инициализация последовательного порта клавиатуры + ; reg 0 + XOR A ;LD A,0 + OUT (Z84.SIO.Ch_A.Ctrl),A + ; reg 4 + LD A,4 + OUT (Z84.SIO.Ch_A.Ctrl),A + ;INC A ;LD A,5 + OUT (Z84.SIO.Ch_A.Ctrl),A + ; reg 3 + LD A,3 + OUT (Z84.SIO.Ch_A.Ctrl),A + LD A,#C1 + OUT (Z84.SIO.Ch_A.Ctrl),A + ; reg 5 + LD A,5 + OUT (Z84.SIO.Ch_A.Ctrl),A + LD A,#62 ;60, 61 + OUT (Z84.SIO.Ch_A.Ctrl),A + ; reg 1 + LD A,1 + OUT (Z84.SIO.Ch_A.Ctrl),A + DEC A ;LD A,0 ; #18 включение прерываний + OUT (Z84.SIO.Ch_A.Ctrl),A +.mouse: ; Инициализация мыши + ; Инициализация таймера мыши + LD A,#55 + OUT (Z84.CTC.Ch_0),A + LD A,#2D ; скорость порта - второй множитель + OUT (Z84.CTC.Ch_0),A + ; reg 0 + XOR A ;LD A,0 + OUT (Z84.SIO.Ch_B.Ctrl),A + ; reg 4 + LD A,4 + OUT (Z84.SIO.Ch_B.Ctrl),A + ;!TODO вспомнить + ;LD A,#45 + ;LD A,#44 + ; + LD A,#40 ; скорость порта - первый множитель = 16 + OUT (Z84.SIO.Ch_B.Ctrl),A + ; reg 3 + LD A,3 + OUT (Z84.SIO.Ch_B.Ctrl),A + LD A,#41 + OUT (Z84.SIO.Ch_B.Ctrl),A + ; reg 5 + LD A,5 + OUT (Z84.SIO.Ch_B.Ctrl),A + LD A,#E0 + OUT (Z84.SIO.Ch_B.Ctrl),A + ; reg 1 + LD A,1 + OUT (Z84.SIO.Ch_B.Ctrl),A + DEC A ;LD A,0 + OUT (Z84.SIO.Ch_B.Ctrl),A + ; Инициализация параллельного порта 1 (принтер) + ; для POST-Tester-а + LD A,#CF ; BITS I/O + OUT (Z84.PIO.Port_A.Command),A + XOR A + OUT (Z84.PIO.Port_A.Command),A ; ALL - out + OUT (Z84.PIO.Port_A.Data),A ; DATA - all zeros + ; для принтера + LD A,#0F ; OUT + OUT (Z84.PIO.Port_A.Command),A + OUT (Z84.PIO.Port_A.Command),A + ; Инициализация параллельного порта 2 (INT/DMA ISA) + LD BC,Z84.PIO.Port_B.Command ;только через регистр BC, иначе Альтера перехватит + LD A,#CF ; BITS I/O + OUT (C),A + LD A,#3F + OUT (C),A + LD A,#C0 + OUT (Z84.PIO.Port_B.Data),A + ; "Заглушение" ковокса и ресет ISA + ; ресет ISA часть 1 + LD BC,PORT_ISA + LD A,#FF + OUT (C),A + ; глушим ковокс + XOR A + OUT (SP_SND.CBL.SYS_PORT),A + LD BC,SP_SND.CBL.OUT + LD A,#80 +.CBL_MUTE: OUT (C),A + DJNZ .CBL_MUTE + ; ресет ISA часть 2 после небольшой паузы + LD BC,PORT_ISA + XOR A + OUT (C),A + ; Сброс контроллера дисковода + ; Включить доступ к контроллеру диска (третья конфа) + LD A,CNF_PORT.CNF_3+ROM.BIOS + OUT (SYS_PORT.ROM),A + OUT (FDC_93.DrvCTRL),A : ASSERT CNF_PORT.CNF_3+ROM.BIOS = #1C, "ERROR: A != #1C" + PUSH HL ; для задержки + POP HL ; для задержки + LD A,#3C ;!HARDCODE + OUT (FDC_93.DrvCTRL),A + PUSH HL ; для задержки + POP HL ; для задержки + XOR A ;!HARDCODE CMD КР1818ВГ93 + OUT (FDC_93.Command),A + ; Выключить доступ к контроллеру диска + LD A,CNF_PORT.CNF_0+ROM.BIOS + OUT (SYS_PORT.ROM),A + ; set HDD1/not-HDD2 + LD A,IDE.Chanel.Primary + OUT (IDE.Chanel.Set),A + LD BC,#7FFD + LD A,#10 + OUT (C),A ; BASIC_48 mode + LD B,#1F + LD A,1 + OUT (C),A ; RAM-0 mode !!! + ; очистка буферов клавиатуры и мыши в SIO + CALL .clean_kbd_buf + JR .clean_mouse_buf +.clean_kbd_buf: ; Clearing the keyboard buffer + IN A,(Z84.SIO.Ch_A.Ctrl) + RRCA + RET NC + IN A,(Z84.SIO.Ch_A.Data) + JR .clean_kbd_buf +.clean_mouse_buf:; Clearing the mouse buffer + IN A,(Z84.SIO.Ch_B.Ctrl) + RRCA + RET NC + IN A,(Z84.SIO.Ch_B.Data) + JR .clean_mouse_buf ;--------------------------------------- -; Инициализация мыши -.mouse: XOR A ;LD A,0 - OUT (Z84.SIO.Ch_B.Ctrl),A - - INC A ;LD A,1 - OUT (Z84.SIO.Ch_B.Ctrl),A - DEC A ;LD A,0 - OUT (Z84.SIO.Ch_B.Ctrl),A - - LD A,3 - OUT (Z84.SIO.Ch_B.Ctrl),A - LD A,#41 - OUT (Z84.SIO.Ch_B.Ctrl),A - - LD A,4 - OUT (Z84.SIO.Ch_B.Ctrl),A - LD A,#44 - OUT (Z84.SIO.Ch_B.Ctrl),A - - LD A,5 - OUT (Z84.SIO.Ch_B.Ctrl),A - LD A,#E0 - OUT (Z84.SIO.Ch_B.Ctrl),A - -; Инициализация таймера мыши - LD A,85 - OUT (Z84.CTC.Ch_0),A - LD A,45 - OUT (Z84.CTC.Ch_0),A - -; Инициализация параллельного порта 1 (принтер) - -; для POST-Tester-а -; LD A,0CFH ; BITS I/O -; OUT (Z84.PIO.Port_A.Command),A -; XOR A -; OUT (Z84.PIO.Port_A.Command),A ; ALL - out -; OUT (Z84.PIO.Port_A.Data),A ; DATA - all zeros - -; для printer-a - LD A,#0F ; OUT - OUT (Z84.PIO.Port_A.Command),A - OUT (Z84.PIO.Port_A.Command),A - -; Инициализация параллельного порта 2 (INT/DMA ISA) - LD BC,Z84.PIO.Port_B.Command - LD A,#CF ; BITS I/O - OUT (C),A - LD A,#3F - OUT (C),A - LD A,#C0 - OUT (Z84.PIO.Port_B.Data),A - -; "Заглушение" ковокса - XOR A - OUT (CBL.SYS_PORT),A - LD BC,CBL.OUT - LD A,#80 -.CBL_MUTE: - OUT (C),A - DJNZ .CBL_MUTE - -; Сброс контроллера дисковода - ; Включить доступ к контроллеру диска (третья конфа) - LD A,CNF_PORT.CNF_3 + ROM.BIOS - OUT (SYS_PORT.ROM),A - - OUT (FDC_93.DrvCTRL),A - push hl - pop hl - LD A,#3C ;!HARDCODE команда для ВГ93 - OUT (FDC_93.DrvCTRL),A - push hl - pop hl - XOR A - OUT (FDC_93.Command),A - -; Выключить доступ к контроллеру диска - LD A,CNF_PORT.CNF_0 + ROM.BIOS - OUT (SYS_PORT.ROM),A - -; set HDD1/not-HDD2 - LD A,#21 ;!HARDCODE сделать через метку - OUT (IDE.Chanel.Choose),A - - LD BC,#7FFD - LD A,#10 - OUT (C),A ; BASIC_48 mode - LD B,#1F - LD A,01 - OUT (C),A ; RAM-0 mode !!! - - RET - ;-----------------------------------------------------------------------; ;-----------------------------------------------------------------------; ; paths from project DIR + INCLUDE 'BIOS_FUNC.ASM' INCLUDE 'FUNC_4x.ASM' INCLUDE 'FUNC_CMOS.ASM' - INCLUDE 'BIOS_FUNC.ASM' INCLUDE 'FUNC_SERVICE.asm' - - INCLUDE 'FLEX.asm' -; INCLUDE 'EXP_SCR.ASZ' - INCLUDE 'FUNC_PIC.ASM' + ; INCLUDE 'EXP_SCR.ASZ' LP_SCR_MNU + INCLUDE 'FUNC_SCREEN.ASM' INCLUDE 'FUNC_RAM_ROM_DRV.ASM' INCLUDE 'FUNC_SYS.ASM' - INCLUDE 'FUNK_FOR_TRDOS.ASM' + INCLUDE 'FUNC_FOR_TRDOS.ASM' INCLUDE 'FUNC_5x.asm' INCLUDE 'FUNC_LOW_PRINT.ASM' ;-----------------------------------------------------------------------; @@ -946,7 +1129,7 @@ PORTS_INIT: ; #::::::::::::::::::::::::::::::::::#\ ; ####################################\ ; \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ -DCP_DATA: INCLUDE 'DCP.ASM' +DCP_DATA: INCLUDE 'DCP.ASM' ;-----------------------------------------------------------------------; ;-----------------------------------------------------------------------; @@ -957,607 +1140,14 @@ DCP_DATA: INCLUDE 'DCP.ASM' ; #::::::::::::::::::::::::::::::::::#\ ; ####################################\ ; \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ -ZG_ADRESS: INCLUDE 'FONT.ASM' +ZG_ADDRESS: INCLUDE 'FONT.ASM' +ZG_SIZE EQU $-ZG_ADDRESS + ASSERT (ZG_SIZE <= #800), "The font size is too big!" ;-----------------------------------------------------------------------; ; -; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ [___FOR ZX-MODE___] _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ; - -; -;------------------------[copy zx-roms to zx-pages]---------------------; -; SLOT0 - ROM 8, sys_port - on. -; RAM SLOT0 - page 0 -; для режима zx spectrum -; ВЫПОЛНЯЕТСЯ ИЗ ОЗУ -init_zx_roms: - DISP Reset_Handler.init_rom_address - - IN A,(SLOT3) - PUSH AF - - ;!HARDCODE - DI - LD A,1 - OUT (SYS_PORT.ROM),A - LD A,2 - - IF SetFullZXromLoader - LD B,6 ; zx-rom number of pages - ELSE - LD B,4 - ENDIF - -.loop: - push bc - - out (ROM.SLOT0),a - or %01000000 - out (SLOT3),a - and %10111111 - - LD HL,0 - LD DE,#C000 - LD BC,#4000 - LDIR - - inc a - pop bc - DJNZ .loop - - xor a - out (ROM.SLOT0),a - OUT (SYS_PORT.ROM),A - POP AF - out (SLOT3),a - - - LD A,#E2 ;!HARDCODE ROM-ID - BASIC 128 - LD B,#42 ; page - CALL .SET_ROM - - LD A,#E3 ;!HARDCODE ROM-ID - BASIC 48 - LD B,#43 ; page - CALL .SET_ROM - - LD A,#E1 ;!HARDCODE ROM-ID - TR-DOS - LD B,#44 ; page - CALL .SET_ROM - - LD A,#E0 ;!HARDCODE ROM-ID - EXPANSION - LD B,#45 ; page - CALL .SET_ROM - - - LD A,#EB ;!HARDCODE ROM-ID - BIOS-1 - IF SetFullZXromLoader - LD B,#46 ; page - ELSE - LD B,#45 ; page - ENDIF - CALL .SET_ROM - - - IF SetFullZXromLoader - LD A,#EF ;!HARDCODE ROM-ID - BIOS-2 - LD B,#47 ; page - CALL .SET_ROM - ENDIF - RET - -.SET_ROM: - LD C,BIOS.SET_PORTS - JP ToBIOS_3D13 - - ENT -.length EQU $-init_zx_roms -;-----------------------------------------------------------------------; -; - - -;-----------------------------------------------------------------------; -GOTO_SPEC: ; ????? процедура биоса для захода в режим спектрума - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,B - LD (SYS_PAGE.CONFIG_DE+1),A - EX AF,AF' - OUT (SLOT3),A - -;NO_SETUP_2: -; CP #FC -; JR Z,SPECTRUM_0 ; Конфигурация AY - -;NO_SETUP_1: -ZX_SPECTRUM_MODE: - LD A,#FE ; !HARDCODE сделать через метку ACC-off Spectrum-MODE - LD BC,Port_All_Mode - OUT (C),A - -;SND_TEST_RET: - LD SP,#BFFF - - CALL FN_SYNC.INT_PENT - CALL SET_PAL_ZX - - LD HL,#4104 - LD E,0 - LD B,4 - CALL LP_OPEN_S - - LD HL,#5104 - LD E,0 - LD B,4 - CALL LP_OPEN_S - - - ; LD D,#35 - ; CALL CMOS_RD - ; BIT 0,A ; !!!!! - -; PUSH AF -; CALL Z,SPRINTER_1 -; POP AF -; PUSH AF -; CALL NZ,AY8910 -; POP AF - -SPECTRUM_0: - XOR A ; задача 0, режим 256 килобайт -SPECTRUM_TASK: - LD IX,BASIC_128 - JP INIT_PAGES ; инициализация номеров страниц режима спектрума - -;start_basic: -BASIC_128: - LD SP,#BFFF - LD HL,RES128_PROG - LD DE,#5B00 ; запуск программы на BASIC-е. - LD BC,LEN_RES128 - LDIR - DI - JP #5B00 ;!HARDCODE - -;-----------------------------------------------------------------------; - -;***************************************************** - -; TURBO_OFF: -; LD A,D_TBOFF -; OUT (SYS_PORT.ON),A -; RET - -; TURBO_ON: -; LD A,D_TBON -; OUT (SYS_PORT.ON),A -; RET - -; JP_HL: JP (HL) - - -;PRINT_LINE: -; LD A,(HL) -; INC HL -; CP 0FFh -; RET Z -; RST 10H -; JR PRINT_LINE - - -; JP RESET_128 - - - IF BIOS_ZXMODE -;-----------------------------------------------------------------------; -; ******* SERVICE ******* -;-----------------------------------------------------------------------; - -;------[ ДЕШИФРАЦИЯ КОМАНДНОЙ СТРОКИ,ПЕРЕДАННОЙ ДЛЯ "EXPANSION" ]-------; -COMAND_LINE: - LD HL,(#5C5D) ;!HARDCODE CH_ADR -COMAND_LOOP: - LD A,(HL) - INC HL - CP ":" - JR Z,COMAND_L1 - CP 0Dh - JR NZ,COMAND_LOOP - RET - -COMAND_L1: - LD A,(HL) - CP 0EAh ; REM !!! - RET NZ - INC HL -COMAND_OK: ; ОБНАРУЖЕНА КОМАНДА ДЛЯ 'expansion' - LD A,(HL) - INC HL - CP ':' - JP Z,MENU_S1 - CP 0Dh - JP Z,MENU_S1 - CP 'I' - JR Z,COMAND_ISD - CP 'i' - JR Z,COMAND_ISD - CP 'T' - JR Z,TASK_SWITCH - CP 't' - JR Z,TASK_SWITCH - DEC HL - POP BC - JP BASIC_MENU -MENU_S1: - POP BC - CALL SERVICE - JP SW_ROM_1 - -COMAND_ISD: - LD A,(HL) - INC HL - CP 'S' - JP Z,COMAND_ISD2 - CP 's' - JP Z,COMAND_ISD2 - RET - -COMAND_ISD2: - POP BC - CALL ISDOS - JP SW_ROM_1 - - -TASK_SWITCH: - -; *** Сохранить задачу *** - PUSH IY - PUSH IX - PUSH AF - PUSH BC - PUSH DE - PUSH HL - - EXX - EX AF,AF' - - PUSH AF - PUSH BC - PUSH DE - PUSH HL - - LD A,R - PUSH AF - LD A,I - PUSH AF - - LD A,(HL) - RLCA - RLCA - RLCA - RLCA - AND 30H ; новая задача 0..3 - LD C,A - - IN A,(SLOT3) - LD B,A ; 3-я страница текущей задачи - LD A,SYS_PAGE - OUT (SLOT3),A - - LD IX,SYS_PAGE.TASK_DATA ; данные задач - LD E,(IX) ; старая задача - LD D,0 - ADD IX,DE ; данные текущей задачи - LD E,16 - ADD IX,DE ; смещение данных в таблице задач - - LD (IX+1),B ; сохранить страницу 3 - LD HL,0 - ADD HL,SP - LD (IX+2),L ; сохранить стек задачи - LD (IX+3),H - SET 0,(IX) ; установить флаг сохраненности текущей задачи - RES 1,(IX) ; установить флаг, что задача покинута - - LD IX,SYS_PAGE.TASK_DATA - LD E,C - LD D,0 - ADD IX,DE ; новая задача - LD E,16 - ADD IX,DE ; смещение данных в таблице задач - - BIT 1,(IX) -; JR NZ,TASK_IN_WORK ; задача в работе ??? неверное завершение - ; сбрасывать или просто возвращаться - - BIT 0,(IX) ; была сохранена/нет - JR NZ,TASK_SET ; задача существует - -; задачи не было! - LD IX,SYS_PAGE.TASK_DATA - LD A,C ; задача - LD (IX),A ; установить новую задачу текущей - - JP SPECTRUM_TASK ; запустить новую задачу! -; и пока пофиг распределение памяти! - -TASK_SET: - LD IX,TASK_RESTORE - LD A,C - EXX - JP INIT_PAGES ; переключить все страницы! - -TASK_RESTORE: - EXX - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,C - LD IX,SYS_PAGE.TASK_DATA - LD (IX),A ; установить новую задачу текущей - - LD E,A - LD D,0 - ADD IX,DE ; новая задача - LD E,16 - ADD IX,DE - - LD L,(IX+2) ; вспомнить стек - LD H,(IX+3) - LD SP,HL - LD A,(IX+1) ; вспомнить третью страницу - OUT (SLOT3),A - - - POP AF ; восстановить - LD I,A - POP AF - LD R,A - POP HL - POP DE - POP BC - POP AF - EX AF,AF' - EXX - POP HL - POP DE - POP BC - POP AF - POP IX - POP IY - ; вернуться в задачу - -NO_TASK: - POP BC - JP SW_ROM_1 - -; 259F - ADRESS BASIC128 - MAIN_MENU -;-----------------------------------------------------------------------; - - - -;-----------------------------------------------------------------------; -; *** UTILITES *** -;-----------------------------------------------------------------------; - -; C_0030: ; получить раб обл -; CALL_48X 0030h -; RET -C_19E8: ; очистить раб обл - CALL_48X 19E8h - RET -C_1655: ; получить пространство - CALL_48X 1655h - RET -CLS: -C_0D6B: CALL_48 #0D6B - RET -CH_2: LD A,2 -C_1601: ; OPEN CHANEL - CALL_48 #1601 - RET - - INCLUDE 'ZX_MENU.ASM' - INCLUDE 'ZX_MODE.ASM' - ENDIF -;-----------------------------------------------------------------------; -; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ; -; - - - - -; -;>$< >$< >$< >$< >$< >$< [ ПЕРЕМЕЩАЕМЫЕ В ОЗУ ] >$< >$< >$< >$< >$< >$< ; - - -;--------[ Программа, размещаемая с #5B00 для запуска Spectrum ]--------; -;!TODO нужна ли тут? -RES128_PROG: - DISP #5B00 ;!HARDCODE SWAP_ROM - LD A,ROM.BIOS - OUT (SYS_PORT.RAM),A ; Возврат в 128k ROM - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (SLOT3),A - LD DE,(SYS_PAGE.CONFIG_DE) - XOR A - LD (SYS_PAGE.CONFIG_DE+1),A - OUT (C),B - - LD BC,#1FFD - OUT (C),A ; Scorp порт - LD B,#7F - OUT (C),A ; 128 порт - - LD A,E ; установка конфигурации и режима TURBO - OUT (SYS_PORT.OFF),A ; CONFIG_SET - - INC D - DEC D - JP Z,0 ; 0 ВХОД В BASIC-128 - LD A,#10 - OUT (C),A - DEC D - JP Z,0 ; 1 ВХОД В BASIC-48 - - LD HL,0 - PUSH HL - DEC D - JP Z,#3D29 ; 2 ВХОД В TR-DOS - - ;!TODO пока не работает - XOR A - OUT (C),A - LD A,#02 - LD B,#1F - OUT (C),A - DEC D - JP Z,0 ; 3 ВХОД В EXPANSION ??? - ; - - XOR A - OUT (C),A - LD A,#30 - LD B,#7F - OUT (C),A - DEC D - JP Z,#3D29 ; 4 ВХОД В TR-DOS с закрытыми 128-ми портами - JP 0 ; 5 ВХОД В BASIC-48 с закрытыми 128-ми портами - ENT -LEN_RES128 EQU $-RES128_PROG -;-----------------------------------------------------------------------; - -;-------------------------------[ #FFE0 ]-------------------------------; -; программа, которая будучи размещенной в #40 странице, -; с адреса RESTARTS, перехватывает RESET -RESTARTS_PROG: ; !TODO LDConf перехват ресета на любой конфе после hardreset - LD HL,RESTARTS - LD B,16 -.loop: - LD (HL),0 - INC HL - DJNZ .loop - NOP - NOP -.Size EQU $-RESTARTS_PROG - ; LD A,1 - ; OUT (SLOT3),A -;-----------------------------------------------------------------------; - -;----------------------------[Setup Starter]----------------------------; - MODULE Setup_Starter -; программа, размещаемая по адресу 0C000h -; для запуска Setup -Start: - DISP COMPILE_ADDR.SETUP_STARTER -Exec: - LD A,CNF_PORT.CNF_0 + ROM.EXPANSION - OUT (SYS_PORT.ROM),A - - LD HL,ROM_MAP.SETUP - LD DE,MEM_MAP.SETUP - LD BC,BLOCK_Setup.Length - LDIR - - LD A,CNF_PORT.CNF_0 + ROM.BIOS - OUT (SYS_PORT.ROM),A - -;-----------[Check SPACE] - LD A,#FE ; !HARDCODE - LD BC,Port_All_Mode ; keyboard int & acc off - OUT (C),A - LD A,high ZXKeys.Line_7 - IN A,(ZXKeys) - CPL - AND 1 -; в регистре A передаётся нажата ли клавиша SPACE. -; потом проверяется в main.asm [space_check] -; и если нажата, то происходит игнор параметра -; "Быстрый старт ПЗУ" во время перезагрузки - EX AF,AF' - - LD A,#FF ; !HARDCODE - OUT (C),A ; keyboard int & acc on, zx_screen & original waits off (for conf >= 3.05) - - EX AF,AF' -;----------------------[] - DI - POP HL ; адрес возврата в EXP из SETUP - LD SP,#8000 ;!HARDCODE - PUSH HL - PUSH AF - JP SETUP_MAIN - ENT -Length EQU $-Setup_Starter.Start - ENDMODULE -;-----------------------------------------------------------------------; - -;---------------------[ ЗАГЛУШКИ ДЛЯ #41 СТРАНИЦЫ]----------------------; -;-------------[RST 08] -RAM_BIOS_PROG: ; for CALL BIOS in 41h page - DISP #08 - PUSH AF - LD A,ROM.BIOS - OUT (SYS_PORT.ROM),A - POP AF - RET - ENT -.Length EQU $-RAM_BIOS_PROG -;-------------------[] - -;-------------[RST 38] -PROG_NO_ROM: - DISP #38 - DI - - LD A,#FF - OUT (SLOT3),A - OUT (SLOT2),A - OUT (SLOT1),A - - LD SP,#BF00 - - LD C,BIOS.LP_OPEN_S - LD B,3 - LD E,0 - RST ToBIOS - - LD C,BIOS.LP_CLS_WIN - LD DE,0 - LD HL,#2050 - RST ToBIOS - - LD A,1 - OUT (RGMOD),A ; set scr-2 - - LD HL,MESSAGE_NR - LD DE,#A000 - LD BC,MESSAGE_NR.size - LD A,C - LDIR - - LD HL,#A000 - LD D,0 ; delimiter - LD E,COLORS.FLASH + COLORS.PAPER.RED + COLORS.INC.CYAN - LD B,A - LD C,BIOS.LP_PRINT_LINE3 - RST ToBIOS - -.loop: DI - HALT - JR .loop - -MESSAGE_NR: DZ " Spectrum ROM not installed. Use spectrum.exe Press Ctrl+Alt+Del or RESET" -.size EQU $-MESSAGE_NR - ENT -PROG_NO_ROM.size EQU $-PROG_NO_ROM -;-------------------[] -;-----------------------------------------------------------------------; -;>$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$<; - - +; !FIXIT сделать эти фиксированные адреса отдельным файлом и с IF/ELSE и подключать их потом куда надо. ; ;????? посмотреть ;----------------------------------------------------------------------; @@ -1582,9 +1172,9 @@ PROG_NO_ROM.size EQU $-PROG_NO_ROM ;************************* _mInfoBLOCK #3CE0-$,0 SW_ROM_1: - LD HL,#259F ;!HARDCODE Show Main Menu in BASIC-128 + LD HL,#259F ;!HARDCODE BASIC_FN.x128.show_main_menu PUSH HL - LD HL,#5B00 ;!HARDCODE + LD HL,#5B00 ;!HARDCODE BASIC_FN.x128.ROM_SWAP LD A,(HL) CP #F5 ; #F5 - опкод 'PUSH AF'. Проверяется то ли в #5B00 JR Z,JP_HL_48 ; ВОЗВРАТ К МЕНЮ BASIC128 @@ -1604,11 +1194,11 @@ SW_ROM_1: ;*************************************** _mInfoBLOCK #3CF8-$,0 ; no basic-48! -JP_HL_48: +JP_HL_48: ;!FIXIT assert with ROM PUSH HL -SW_ROM: +SW_ROM: ;!FIXIT assert with ROM PUSH AF - LD A,ROM.BIOS + LD A,ROM.BIOS ;!FIXIT неправильное название константы OUT (SYS_PORT.RAM),A POP AF RET @@ -1629,42 +1219,209 @@ SW_ROM: ; ;----------------------------------------------------------------------; _mInfoBLOCK #3D00-$,#FF -DOS_ON: NOP +DOS_ON: NOP ;!TODO работает при #7FFD[4] = 1. Как-то узнавать значение 7FFD и менять? RET ;*************************************** ;*************************************** ; BLOCK #3D02-$,FF ; !TODO можно оприходовать тут 17 байтов -; ;*************************************** ;*************************************** _mInfoBLOCK #3D13-$,#FF NOP - JP #18 + JP ToBIOS_18 ;*************************************** ;*************************************** ; BLOCK #3D17-$,FF -; !TODO можно оприходовать тут 233 байта -; ;*************************************** +; + + + + + ; IF FREE_ZX_PAGES +;-----------------------------------------------------------------------; +GOTO_SPEC: PUSH HL + LD HL,RET_TO_BIOS + EX (SP),HL + PUSH HL + PUSH AF + CALL FN_TURBO.SET_FDD_720 + POP AF + LD HL,GOTO_SPECTRUM + EX (SP),HL + JP EXTENSION_FNs + +ZX_MEMORY_MANAGER: + PUSH HL + LD HL,RET_TO_BIOS + EX (SP),HL + PUSH HL + LD HL,MANAGE_ZX_PAGES.FN_ENTRANCE + EX (SP),HL + JP EXTENSION_FNs +;-----------------------------------------------------------------------; + + +;>$< >$< >$< >$< >$< >$< [ ПЕРЕМЕЩАЕМЫЕ В ОЗУ ] >$< >$< >$< >$< >$< >$< ; +; +;---------------------[ ЗАГЛУШКИ ДЛЯ #41 СТРАНИЦЫ]----------------------; +;-------------[RST 08] +RAM_BIOS_PROG: ; for CALL BIOS in #41 page + DISP Spec_Page.to_bios + PUSH AF + LD A,ROM.BIOS + OUT (SYS_PORT.ROM),A + POP AF + RET + ENT +.Length EQU $-RAM_BIOS_PROG +;-------------------[] +; +;-------------[RST 38] +PROG_NO_ROM: + DISP Spec_Page.no_zx_rom + DI + ; + LD A,CNF_PORT.CNF_0 + OUT (SYS_PORT.RAM),A + ; + LD A,SHARED_PAGE + OUT (SLOT3),A + OUT (SLOT2),A + OUT (SLOT1),A + LD SP,#BF00 + ; + LD BC,BIOS.SET_PAL_INIT.CGA + RST ToBIOS + ; + LD E,0 + LD BC,BIOS.LP_OPEN_S.TXT_80x32_Default + RST ToBIOS + ; + LD DE,0 + LD B,E + LD HL,#2050 + LD C,BIOS.LP_CLS_WIN + RST ToBIOS + ; + LD HL,MESSAGE_NR + LD DE,#A000 + PUSH DE + LD BC,MESSAGE_NR.size + LDIR + ; BC=0 + POP HL + SCF + EX AF,AF' + SCF + LD A,COLORS.CGA.FLASH + COLORS.CGA.INK.RED + PUSH BC + POP IY + LD DE,#0F00 + ; B=0 delimiter + LD C,BIOS.LP_PR_LINE_DIR + RST ToBIOS + ; + ; set scr-2 + LD A,1 + OUT (SCREEN_SWITCH),A +.loop: DI + HALT + JR .loop + ;Spectrum ROM configuration error + ; 10 20 30 40 50 60 70 80 + ; "123456789|123456789|123456789|123456789|123456789|123456789|123456789|123456789|" +MESSAGE_NR: DZ "\t\t\tSpectrum ROM configuration error\r\n\t\t\t Press Ctrl+Alt+Del or RESET." +.size EQU $-MESSAGE_NR + ENT +PROG_NO_ROM.size EQU $-PROG_NO_ROM +;-------------------[] +;-----------------------------------------------------------------------; +;>$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$<; + +;-------------------------------[ #FFE0 ]-------------------------------; +; программа, которая будучи размещенной в #40 странице, +; с адреса RESTARTS, перехватывает RESET +RESTARTS_PROG: ; !TODO LDConf перехват ресета на любой конфе после hardreset + LD HL,RESTARTS + LD B,16 +.loop: LD (HL),0 + INC HL + DJNZ .loop + NOP + NOP +.Size EQU $-RESTARTS_PROG + ; LD A,1 + ; OUT (SLOT3),A +;-----------------------------------------------------------------------; + +;----------------------------[Setup Starter]----------------------------; + MODULE Setup_Starter +; программа, размещаемая по адресу #C000 для запуска Setup +Start: DISP COMPILE_ADDR.SETUP_STARTER +Exec: LD A,CNF_PORT.CNF_0 + ROM.EXTENSION + OUT (SYS_PORT.ROM),A + ; + LD HL,ROM_MAP.SETUP + LD DE,MEM_MAP.SETUP + LD BC,BLOCK_Setup.Length + LDIR + ; + LD A,CNF_PORT.CNF_0 + ROM.BIOS + OUT (SYS_PORT.ROM),A +;-----------[Check SPACE] + ; в CF передаётся нажата ли клавиша SPACE. CF=0: клавиша нажата + ; потом проверяется в main.asm [space_check] и если нажата, + ; то происходит игнор параметра "Быстрый старт ПЗУ" + ; во время перезагрузки в [Check Quick Start ROM] + LD BC,Port_All_Mode + IN H,(C) ; или LD H,#FF + LD A,Port_All_Mode.DEFAULT - Port_All_Mode.SPECTRUM_MODE_OFF + OUT (C),A ; keyboard int & acc off + LD A,high ZXKeys.Line_7 + IN A,(ZXKeys) + RRA ; CF=0 клавиша нажата +;----------------------[] + OUT (C),H + DI + POP HL ; адрес возврата в EXP из SETUP + JP SETUP_MAIN + ENT +Size EQU $-Setup_Starter.Start + ENDMODULE +;-----------------------------------------------------------------------; +;-----------------------------------------------------------------------; +;>$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$<; +; + + + + ;*************************************** _mInfoBLOCK #3E00-$,#FF -;!TODO а чё не в стек прыгать? DOS_OFF: + PUSH AF + LD A,R DI - PUSH AF - PUSH BC - LD BC,(#5BFF) ; !HARDCODE - LD A,#C9 - LD (#5BFF),A ; !HARDCODE - CALL #5BFF ; !HARDCODE - LD (#5BFF),BC ; !HARDCODE - POP BC - POP AF + PUSH AF + PUSH BC + ; + LD BC,(#5BFF) ; !HARDCODE + LD A,#C9 ; Opcode RET + LD (#5BFF),A ; !HARDCODE + CALL #5BFF ; !HARDCODE + LD (#5BFF),BC ; !HARDCODE + ; + POP BC + POP AF + JP PO,.no_EI + EI +.no_EI: POP AF RET ;*************************************** @@ -1679,7 +1436,7 @@ DOS_OFF: //////////////////////////////////////////////////////////////////////// ;------[ ; !TODO что- то связанное с переменными LIB_TABLE ; ]------ ; _mInfoBLOCK #3E20-$,#FF -; [ ] +; [x] FN_LIB: SCF RET @@ -1719,7 +1476,7 @@ FN_LIB: -;!TODO скомпоновать +;!TODO скомпоновать и допаять ;----------------------------------------------------------------------; ; вход A - byte ; B - speed_parameter @@ -1780,51 +1537,60 @@ kbd_loop2: AND A RET ;----------------------------------------------------------------------; -; +;----------------------------------------------------------------------; +; DE - частота +; HL - продолжительность +BEEP: LD A,#10 + CALL .beep_loop + ; + ;XOR A + CALL .beep_loop + ; + DEC HL + LD A,H + OR L + JR NZ,BEEP + RET + ; +.beep_loop: OUT (SP_SND.Beeper),A + LD B,D + LD C,E + ; +.loop: DEC BC + LD A,B + OR C + JR NZ,.loop + RET +;----------------------------------------------------------------------; ;#######################################################################; -;#######################################################################; -;-----------------------------------------------------------------------; -; ROM-Disk pages ; [x] активирован ROM-DISK - _mInfoALIGN 256,#FF -; BLOCK #3F00-$,#FF -ROM_DISK.Pages.Number: - BYTE ROM_DISK.Pages.Size ; число страниц -; у страниц выставлен bit4 для корректной подстановки -;(подробнее в sp2000.inc - Порт управления страницами ПЗУ) -ROM_DISK.Pages: ; страницы ROM-Disk - IFN SetFullZXromLoader - ABYTE #10 #06,#07,#09,#0A,#0B ; 81920 bytes - ELSE - ABYTE #10 #09,#0A,#0B ; 49152 bytes - ENDIF -.Size EQU $-ROM_DISK.Pages -;-----------------------------------------------------------------------; -; - _mInfoBLOCK ToBIOS_FromEXT-$,#FF -;------------[Return to ROM]------------ + + + +;---------[Return to EXTENSION]--------- + _mInfoBLOCK #3FD0-$,#FF ; ToBIOS_FromEXT ; #3FD0 -; Для вызова функций биоса из страницы 0 ПЗУ (ROM Extension) -FN1_RET: +; Для вызова функций биоса из страницы 0 ПЗУ (Extension) +RET_TO_EXTENSION: PUSH AF - LD A,ROM.EXPANSION + LD A,ROM.EXTENSION OUT (SYS_PORT.ROM),A POP AF - RST #18 - JR FN1_RET + RST ToBIOS_18 + JP RET_TO_EXTENSION -; !TODO Free 7 bytes +; !TODO Free 6 bytes ;--------------------------------------- ; +;---------------[ Free ]---------------- ; _mInfoBLOCK #3FE0-$,#FF -;---------------[ Free ]---------------- ; !TODO Free 8 bytes and entry point ;SOUND_TEST: ; LD A,ROM.EXPANSION @@ -1833,13 +1599,13 @@ FN1_RET: ;--------------------------------------- ; -;!TEST new_api -;------------[HDD_5x portal]------------ -; точка входа/выхода для функций 5х из EXP +; [x] new portal +;------------[Portal to EXT]------------ +; точка входа/выхода для функций в ROM.EXTENSION _mInfoBLOCK #3FE8-$,#FF -EXP_HDD: ;HDD_EXE: +EXTENSION_FNs: ;EXP_HDD: PUSH AF - LD A,ROM.EXPANSION + LD A,ROM.EXTENSION OUT (SYS_PORT.ROM),A POP AF RET @@ -1848,16 +1614,16 @@ EXP_HDD: ;HDD_EXE ; - _mInfoBLOCK #3FF0-$,#FF ;---------------[ Free ]---------------- + _mInfoBLOCK #3FF0-$,#FF ; !TODO Free 8 bytes and entry point ;--------------------------------------- ; ; +;----[ From TR-DOS to API #80..#FF ]----- _mInfoBLOCK #3FF8-$,#FF -;-----[ From TR-DOS to API #80..#FF]----- ; Точка входа/выхода для TR-DOS EXP_FNS_RET: PUSH AF diff --git a/src/bios/exp/EXP_DCP2.txt b/src/bios/exp/EXP_DCP2.txt deleted file mode 100644 index 9f69774..0000000 --- a/src/bios/exp/EXP_DCP2.txt +++ /dev/null @@ -1,130 +0,0 @@ -6E 0000.00 0110 1110 -7E 0000.00 0111 1110 -EE 0000.00 1110 1110 -FE 0000.00 1111 1110 -16E 0000.01 0110 1110 -17E 0000.01 0111 1110 -1EE 0000.01 1110 1110 -1FE 0000.01 1111 1110 - -and 0000.00 0110 1110 -or 0000.01 1111 1110 -notAnd 0011.11 1001 0001 -xor^ 0011.10 0110 1111 - - -; DATA FOR DCP -; вбиваем в таблицу DCP.XLSX нужный внешний порт, -; смотрим смещение для OUT (С),x - это адрес -; -; CCED/AAAAAAAAA -; NN1OW116517210 -; FF2SR54 3 -; CC EDWA AAAA AAAA -; NN 1O/1 1651 7210 -; FF 2SR5 4 3 -; 10 8 - -and 00 0000 0000 0111 - a1 -or 11 1011 1001 0111 - o1 -not a1 11 1111 1111 1000 - n1 -n1 xor o1 00 0110 0110 1111 - -#10 ALTERA #1F external -; CS_WG93_1F ...0...00.0111 - DW %00 0000 0000 0111 ; - адрес - DW %00 0100 0110 1111 ; - маска - 0 изменяемые биты, 1 неизменяемые - DB #10 ; - порт - - - -Altera #16 - 2D 00 0000 0010 1101 - 82D 00 1000 0010 1101 -302D 11 0000 0010 1101 -342D 11 0100 0010 1101 -382D 11 1000 0010 1101 -3C2D 11 1100 0010 1101 - -and 00 0000 0010 1101 - a1 adress -or 11 1100 0010 1101 - o1 -not a1 11 1111 1101 0010 - n1 -n1 xor o1 00 0011 1111 1111 mask - -Altera #17 - 3D 00 0000 0011 1101 - 83D 00 1000 0011 1101 -303D 11 0000 0011 1101 -343D 11 0100 0011 1101 -383D 11 1000 0011 1101 -3C3D 11 1100 0011 1101 - -and 00 0000 0011 1101 - a1 adress -or 11 1100 0011 1101 - o1 -not a1 11 1111 1100 0010 - n1 -n1 xor o1 00 0011 1111 1111 mask - -and 00 0000 0011 1101 - a1 adress -or 00 1000 0011 1101 - o1 -not a1 11 1111 1100 0010 - n1 -n1 xor o1 11 0111 1111 1111 mask - - - -and 00 0000 0000 0000 - a1 adress -not a1 00 0000 0000 0000 - n1 -or 00 0000 0000 0000 - o1 -n1 xor o1 00 0000 0000 0000 mask - -Found 48 occurrences of '29'. - - 4C5 00 0100 1100 0101 - 4D5 00 0100 1101 0101 - 6C5 00 0110 1100 0101 - 6D5 00 0110 1101 0101 - CC5 00 1100 1100 0101 - CD5 00 1100 1101 0101 - EC5 00 1110 1100 0101 - ED5 00 1110 1101 0101 - -34C5 11 0100 1100 0101 -34D5 11 0100 1101 0101 -36C5 11 0110 1100 0101 -36D5 11 0110 1101 0101 -3CC5 11 1100 1100 0101 -3CD5 11 1100 1101 0101 -3EC5 11 1110 1100 0101 -3ED5 11 1110 1101 0101 - -and 11 0100 1100 0101 - a1 adress -not a1 00 1011 0011 1010 - n1 -or 11 1110 1101 0101 - o1 -n1 xor o1 11 0101 1110 1111 mask - - -Found 12 occurrences of '1b'. - 12D 00 0001 0010 1101 - 52D 00 0101 0010 1101 - 92D 00 1001 0010 1101 - D2D 00 1101 0010 1101 - -312D 11 0001 0010 1101 -352D 11 0101 0010 1101 -392D 11 1001 0010 1101 -3D2D 11 1101 0010 1101 - -and 11 0001 0010 1101 - a1 adress -not a1 00 1110 1101 0010 - n1 -or 11 1101 0010 1101 - o1 -n1 xor o1 11 0011 1111 1111 mask - - -21BD 10 0001 1011 1101 -23BD 10 0011 1011 1101 -29BD 10 1001 1011 1101 -2BBD 10 1011 1011 1101 - -and 10 0001 1011 1101 - a1 adress -not a1 01 1110 0100 0010 - n1 -or 10 1011 1011 1101 - o1 -n1 xor o1 11 0101 1111 1111 mask \ No newline at end of file diff --git a/src/bios/exp/EXTENDED/CD_DRIVER_0.asm b/src/bios/exp/EXTENDED/CD_DRIVER_0.asm deleted file mode 100644 index db42a32..0000000 --- a/src/bios/exp/EXTENDED/CD_DRIVER_0.asm +++ /dev/null @@ -1,389 +0,0 @@ -;CD ROM DRIVE DRIVER ;!FIXIT ALL! -;--------------------------------------------------------------- -;Rev Date Name Description -;--------------------------------------------------------------- -; 02-08-2001 DNS Initial this module -;--------------------------------------------------------------- -;======================================================== -;!FIXIT -R170 EQU #0050 ;Data -R171 EQU #0051 ;Error -R172 EQU #0052 ;Direct -R173 EQU #0053 ;Reserve -R174 EQU #0054 ;Lenght block low -R175 EQU #0055 ;Lenght block high -R176 EQU #4052 ;Drive device -R177 EQU #4053 ;Status - -W170 EQU #0150 ;Data -W171 EQU #0151 ;???? -W172 EQU #0152 ;???? -W173 EQU #0153 ;Reserve -W174 EQU #0154 ;Lenght block low -W175 EQU #0155 ;Lenght block high -W176 EQU #4152 ;Drive device -W177 EQU #4153 ;Command - -RAM_ATAPI_PK EQU #FEE0 -RAM_ATAPI_READ EQU #FEF0 - -;BSY EQU 7 -;DRQ EQU 3 -;ERR EQU 0 - - -;[]===========================================================[] -CD_5x.RESET: - LD B,50 -.loop: - PUSH BC - LD A,1 - CALL CD_TEST - POP BC - RET NC - EI - HALT - DJNZ .loop - RET -;[]===========================================================[] - - -;[]===========================================================[] -CD_5x.LONG_READ: ; !FIXIT не надо сохранять страницу SLOT3 как в других драйвах? -;[]===========================================================[] -;[]===========================================================[] -CD_5x.READ: - LD A,1 - JP CD_READ -;[]===========================================================[] - - -;[]===========================================================[] -CD.OPEN: - LD A,1 - JP CD_OPEN -;[]===========================================================[] - - -;[]===========================================================[] -CD.CLOSE: - LD A,1 - JP CD_CLOSE -;[]===========================================================[] - - - -SIZESEC EQU #0800 -PKTSIZE EQU 12 - -CD_TEST LD HL,CMDNOPP - LD DE,0 - CALL AP_COM - RET - -; -;[]===========================================================[] -CD_5x.DETECT: ; !FIXIT - SCF - RET -;[]===========================================================[] -CD_OPEN: - LD HL,CMDOPEN - LD DE,0 - CALL AP_COM - RET -; - -CD_CLOSE: - LD HL,CMDCLOS - LD DE,0 - CALL AP_COM - RET - -; HL:IX - SECTOR -; DE - ADDRESS -; B - SECTOR COUNT -; A - DRIVE - -CD_READ: - LD C,A - EXX - LD C,SLOT3 - IN A,(C) - PUSH AF - LD A,SYS_PAGE - OUT (C),A - LD HL,CMDREAD - LD DE,RAM_ATAPI_READ - LD BC,PKTSIZE - LDIR - EXX - LD A,H - LD (RAM_ATAPI_READ+SECREAD+0),A ;R01 - LD A,L - LD (RAM_ATAPI_READ+SECREAD+1),A ;R01 - LD A,XH - LD (RAM_ATAPI_READ+SECREAD+2),A ;R01 - LD A,XL - LD (RAM_ATAPI_READ+SECREAD+3),A ;R01 - LD A,B - LD (RAM_ATAPI_READ+COUNT+1),A ;R01 - POP AF - OUT (SLOT3),A -;R01 LD HL,CMDREAD - LD HL,RAM_ATAPI_READ - LD A,C - CALL AP_COM - RET - -; INPUT: HL - AP paket (12bytes) -; RETURN: CF - ERROR -; 01h - RECOVERED ERROR -; 02h - NOT READY -; 03h - MEDIUM ERROR -; 04h - HARDWARE ERROR -; 05h - ILLEGAL REQUEST -; 06h - UNIT ATTETION -; 07h - DATA PROTECT -; 0Bh - ABORTED COMMAND -; 80h - TIME OUT - -AP_COM AND #01 - LD A,#A0 - JR Z,.APCOM1 - LD A,#B0 -.APCOM1 LD BC,W176 - OUT (C),A ;SELECT DRIVE - EXX - LD DE,#8000 - LD BC,R177 - CALL CWAITPRT - EXX - JR NC,.CDREADY - LD BC,W177 - LD A,#08 - OUT (C),A - LD B,#00 - DJNZ $ - EXX - LD DE,#8000 - LD BC,R177 - CALL CWAITPRT - EXX - RET C -.CDREADY: - LD C,SLOT3 - IN B,(C) - - PUSH DE - PUSH BC - - LD A,SYS_PAGE - OUT (C),A - LD A,B - LD DE,RAM_ATAPI_PK - LD BC,PKTSIZE - LDIR - - POP BC - POP DE - OUT (C),B - - XOR A - EXX - OUT (C),A - XOR A - LD BC,W171 - OUT (C),A - LD DE,SIZESEC ;SIZE BLOCK - LD BC,W174 - OUT (C),E - LD BC,W175 - OUT (C),D - LD BC,W177 - LD A,#A0 - OUT (C),A - LD DE,#8000 - LD BC,R177 - CALL CWAITPRT - EXX - RET C - EXX - LD DE,#0908 - LD BC,R177 - CALL CWAITPRT - EXX - BIT IDE.ControlBit.Error,A - JR NZ,.CDERROR - JR NC,.YEP_DRQ - LD A,#80 - RET -.YEP_DRQ: - LD C,SLOT3 - IN B,(C) - PUSH BC - LD A,SYS_PAGE - OUT (SLOT3),A - LD HL,RAM_ATAPI_PK - LD BC,W170 - LD A,PKTSIZE - SRL A -.OUTPKT: - OUTI - OUTI - DEC A - JR NZ,.OUTPKT - POP BC - OUT (C),B - LD B,#80 - DJNZ $ -.AP_LOOP: - EXX - LD DE,#8000 - LD BC,R177 - CALL CWAITPRT - EXX - RET C - LD BC,R177 - IN A,(C) - BIT IDE.ControlBit.Error,A - JR Z,.NO_ERR -.CDERROR: - LD BC,R171 ;ERROR - IN A,(C) - RRCA - RRCA - RRCA - RRCA - AND #0F - SCF - RET -.NO_ERR: - BIT IDE.ControlBit.DataRequest,A - LD A,0 - RET Z ;NO DATA REQUEST - EX DE,HL - LD BC,R174 - IN E,(C) - LD BC,R175 - IN D,(C) ;TRANSFER BLOCK SIZE - LD A,D - OR E - RET Z ;BLOCK = 0 - LD BC,R172 - IN A,(C) - AND #02 - CP #02 - JP Z,.FROM_CD -;.TO_CD: - LD BC,R170 -.WR_T_CD: - OUTI - OUTI - DEC DE - DEC DE - LD A,D - OR E - JR NZ,.WR_T_CD - EX DE,HL - JR .AP_LOOP -.FROM_CD: - LD A,H - OR L - JR Z,.NULL - LD BC,R170 -.RD_F_CD: - INI - INI - DEC DE - DEC DE - LD A,D - OR E - JR NZ,.RD_F_CD - EX DE,HL - JR .AP_LOOP -.NULL: LD BC,R170 -.RD_N_CD: - IN A,(C) - DEC B - IN A,(C) - DEC B - DEC DE - DEC DE - LD A,D - OR E - JR NZ,.RD_N_CD -; DE = 0 !!! - JR .AP_LOOP - - - -; E - Second * 10 -; PAUSE LD HL,#0000 -; PAUSE1 DEC L -; JR NZ,PAUSE1 -; DEC H -; JR NZ,PAUSE1 -; DEC E -; JR NZ,PAUSE1 -; RET - - -; D - MASK -; E - PATTERN -; BC - PORT -CWAITPRT: - LD A,100 - LD HL,#0000 -.CWAITPX: - EX AF,AF' -.CWAITP0: - IN A,(C) - CP #FF - JR Z,.CWAITP1 - AND D - CP E - JR NZ,.CWAITP2 - AND A - RET -.CWAITP2: - DEC L - JR NZ,.CWAITP0 - DEC H - JR NZ,.CWAITP0 - EX AF,AF' - DEC A - JR NZ,.CWAITPX - EX AF,AF' -.CWAITP1: - SCF - RET - -CMDNOPP DEFB #00 - DEFB 00,00,00 - DEFB #00 - DEFB 00,00,00 - DEFB 00,00,00 - DEFB #00 - -CMDOPEN DEFB #1B - DEFB #00,#00,#00 - DEFB #02 - DEFB #00,#00,#00,#00,#00,#00,#00 - -CMDCLOS DEFB #1B - DEFB #00,#00,#00 - DEFB #03 - DEFB #00,#00,#00,#00,#00,#00,#00 - -CMDREAD DEFB #28,#00 -SECREAD EQU $-CMDREAD - DEFB #00,#00,#00,#00 - DEFB #00 -COUNT EQU $-CMDREAD - DEFB #00,#01 - DEFB #00,#00,#00 - -;======================================================== - - diff --git a/src/bios/exp/EXTENDED/FDD_DRIVER_2.asm b/src/bios/exp/EXTENDED/FDD_DRIVER_2.asm index 38c0387..e1599c2 100644 --- a/src/bios/exp/EXTENDED/FDD_DRIVER_2.asm +++ b/src/bios/exp/EXTENDED/FDD_DRIVER_2.asm @@ -3,6 +3,10 @@ ;[]===========================================================[] +;!TODO +; объеденить процедуры FDD_5x_LONG_READ и FDD_5x_LONG_WRITE +; объеденить процедуры READ_SECTOR и WR_SEC + ; FDD.CHANGE: ; LD A,#01 @@ -21,23 +25,25 @@ ; IX - Capacity sector in bytes ; B - Flags ; D7 - "1" - High Density, "0" - Double Density +; D0 - FDD drv number +; A - D0 - "1" - Removable media ;[]===========================================================[] ;!FIXIT всегда идет работа с данными для диска А -FDD_5x.GETMED: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD HL,(FDD_INI_TABLE.FDD_0.SECTORS) - LD DE,(FDD_INI_TABLE.FDD_0.CYLINDL) - LD IX,(FDD_INI_TABLE.FDD_0.B_P_S) - LD A,(FDD_INI_TABLE.FDD_0.F144) - LD B,A - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' - AND A - RET +FDD_5x_GET_PAR: IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD HL,(SYS_PAGE.FDD_TABLE.SECTORS) + LD DE,(SYS_PAGE.FDD_TABLE.CYLINDL) + LD IX,(SYS_PAGE.FDD_TABLE.BytesPerSector) + LD A,(SYS_PAGE.FDD_TABLE.DISK) + LD B,A + EX AF,AF' + OUT (SLOT3),A + XOR A + INC A ; removable media. CF=0, LD A,1 + RET ;[]===========================================================[] ;Function: Set Current Media Parameters @@ -50,56 +56,88 @@ FDD_5x.GETMED: ; D7 - "1" - High Density, "0" - Double Density ;Return: None ;[]===========================================================[] -FDD_5x.SETMED: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,B - LD (FDD_INI_TABLE.FDD_0.SECTORS),HL - LD (FDD_INI_TABLE.FDD_0.CYLINDL),DE - LD (FDD_INI_TABLE.FDD_0.B_P_S),IX - LD (FDD_INI_TABLE.FDD_0.F144),A - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' - AND A - RET +FDD_5x_SET_PAR: ;!TEST FDD 720/1440 + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD A,B + LD (SYS_PAGE.FDD_TABLE.SECTORS),HL + LD (SYS_PAGE.FDD_TABLE.CYLINDL),DE + LD (SYS_PAGE.FDD_TABLE.BytesPerSector),IX + LD (SYS_PAGE.FDD_TABLE.DISK),A + ; + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + AND A + RET ;[]===========================================================[] ;Function: Detect Disk Density ; A - Disk ;Return: ; A - Flag D7 - "1" - High Density, "0" - Double Density +; B - bit0=1 removable ;[]===========================================================[] -FDD_5x.DETECT: - CALL SET_DOS_ON - CALL DISK_ID - PUSH AF - CALL SET_DOS_OFF - POP AF - RET +FDD_5x_DETECT: CALL SAVE_INTERRUPTS.switch_off + CALL SET_DOS_ON + CALL DISK_ID + PUSH AF + CALL SET_DOS_OFF + POP AF + LD B,%0000'0001 ;bit0=1 removable, bit1=1 drive changed, bit7..2 reserved ; [ ] + JP SAVE_INTERRUPTS.restore + ;RET ;[]===========================================================[] ;Function: Reset Disk ; A - Disk ;Return: None ;[]===========================================================[] -FDD_5x.RESET: - CALL SET_DOS_ON - CALL S_FDD - CALL DISK_ID - LD A,4 ;NOT READY /NO DISK/ - JP C,MOTOR_OFF - CALL RESWG - XOR A - OUT (FDC_93.Track),A - IN A,(FDC_93.Command) - LD C,A - CALL SET_DOS_OFF - LD A,C - AND A - RET +FDD_5x_RESET: CALL SAVE_INTERRUPTS.switch_off + CALL SET_DOS_ON + CALL S_FDD + CALL DISK_ID + JR C,.int + ; [ ] размера сектора + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD H,B + LD L,0 + LD (SYS_PAGE.FDD_TABLE.BytesPerSector),HL + EX AF,AF' + OUT (SLOT3),A + ; +.int: CALL SAVE_INTERRUPTS.restore + JR C,.MOTOR_OFF + ; + CALL RESWG + XOR A ;!HARDCODE CMD КР1818ВГ93 + OUT (FDC_93.Track),A + IN A,(FDC_93.Command) + ;LD C,A + CALL SET_DOS_OFF + ;LD A,C + AND A + JP SAVE_INTERRUPTS.restore + ;RET +.MOTOR_OFF: ;PUSH AF + LD A,#D0 ;!HARDCODE CMD КР1818ВГ93 + OUT (FDC_93.Command),A ;STOP OPERATION + LD A,#00 + OUT (FDC_93.DrvCTRL),A + LD A,#3C + OUT (FDC_93.DrvCTRL),A + CALL SET_DOS_OFF + ; CF=1 + LD A,BIOS.Error.NotReady + ;POP AF + ;JP SAVE_INTERRUPTS.restore + RET ;[]===========================================================[] ;Function: Read Sectors ; A - Disk @@ -110,142 +148,142 @@ FDD_5x.RESET: ; HL:IX - Sector + Sector counter ; DE - Address + (Sector counter * Size sector) ;[]===========================================================[] -FDD_5x.READ: - EX AF,AF' - IN A,(SLOT3) - EX AF,AF' +FDD_5x_READ: EX AF,AF' + IN A,(SLOT3) + EX AF,AF' ;[]===========================================================[] ;Function: Long Read Sectors ; A - Disk ; HL:IX - Sector ; DE - Address ; B - Sector counter -; A'- Memory ID Block +; A'- Memory Page Number ;Return: ; HL:IX - Sector + Sector counter ; DE - Address + (Sector counter * Size sector) ;[]===========================================================[] -FDD_5x.LONG_READ: - PUSH IY - PUSH BC - PUSH HL - PUSH IX - EX AF,AF' - LD C,A - EX AF,AF' - PUSH BC - CALL SET_DOS_ON - CALL S_FDD - CALL SPEED - CALL NTRACK - POP BC - EX DE,HL -; LD A,B -; OR A -; JP Z,RETDOS - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD IY,(FDD_INI_TABLE.FDD_0.B_P_S) - LD XH,C - LD A,(FDD_INI_TABLE.FDD_0.SECTORS) - LD C,A - EX AF,AF' - OUT (SLOT3),A -.DSK_LP: - LD A,D - EXX - CALL SEEK - EXX - PUSH DE - PUSH BC - PUSH HL - CALL RD_SEC - JP C,ERRDOS - LD D,YH - LD E,YL - POP HL - POP BC - ADD HL,DE - JR NC,.THISRD - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD D,#C2 - LD E,XH - LD A,(DE) - LD XH,A - EX AF,AF' - OUT (SLOT3),A - SET 7,H - SET 6,H -.THISRD: - POP DE - LD A,C - INC E - CP E - JP NZ,.NINC_T - LD E,0 - INC D -.NINC_T: - DJNZ .DSK_LP -.RETDOS: - CALL SET_DOS_OFF - LD A,XH - EX AF,AF' - EX DE,HL - POP IX - POP HL - POP BC - POP IY - LD A,B - LD C,B - INC B - DEC B - LD B,0 - JR NZ,.ADD8BIT - INC B -.ADD8BIT: - ADD IX,BC - LD BC,0 - ADC HL,BC - LD B,A - XOR A - RET - -ERRDOS: - POP HL - POP BC - POP DE - CALL SET_DOS_OFF - EX DE,HL - EX AF,AF' - EXX - LD C,XH - EXX - LD A,B - POP IX - POP HL - POP BC - POP IY - PUSH AF - LD C,A - LD A,B - SUB C - LD C,A - LD B,0 - ADD IX,BC - LD C,B - ADC HL,BC - POP BC - EXX - LD A,C - EXX - EX AF,AF' - SCF - RET +FDD_5x_LONG_READ: + EXX + LD B,#80 ; COMMAND READ ;!HARDCODE CMD КР1818ВГ93 + EXX + ; +.RW_Shared: CALL SAVE_INTERRUPTS.switch_off + CALL .Start + JP SAVE_INTERRUPTS.restore + ; +.Start: PUSH IY + PUSH BC + PUSH HL + PUSH IX + ; + EX AF,AF' + LD C,A ; Memory Page Number + EX AF,AF' + PUSH BC + CALL SET_DOS_ON + CALL S_FDD + CALL SET_SPEED + CALL NTRACK + POP BC + EX DE,HL + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD IY,(SYS_PAGE.FDD_TABLE.BytesPerSector) + LD XH,C ; Memory Page Number + LD A,(SYS_PAGE.FDD_TABLE.SECTORS) + LD C,A + EX AF,AF' + OUT (SLOT3),A +.DSK_LP: LD A,D + EXX + PUSH BC + CALL SEEK + POP BC + EXX + PUSH DE + PUSH BC + PUSH HL + CALL FDD_RW_SECTOR + JR C,ERRDOS + ; размер сектора + LD D,YH + LD E,YL + ; + POP HL + POP BC + ADD HL,DE + ; + CALL C,CHANGE_MEM_BLK + ; +.THISRD: POP DE + LD A,C + INC E + CP E + JR NZ,.NINC_T + LD E,0 + INC D +.NINC_T: DJNZ .DSK_LP +.RETDOS: CALL SET_DOS_OFF + LD A,XH ; Memory Page Number + EX AF,AF' + EX DE,HL + POP IX + POP HL + POP BC + POP IY + LD A,B + LD C,B + INC B + DEC B + LD B,0 + JR NZ,.ADD8BIT + INC B +.ADD8BIT: ADD IX,BC + ;!TEST + ;LD BC,0 + ;ADC HL,BC + ;LD B,A + ;XOR A + ;RET + ; + LD B,A + RET NC + INC HL + XOR A + RET + ; +ERRDOS: POP HL + POP BC + POP DE + CALL SET_DOS_OFF + EX DE,HL + EX AF,AF' + EXX + LD C,XH ; Memory Page Number + EXX + LD A,B + POP IX + POP HL + POP BC + POP IY + PUSH AF + LD C,A + LD A,B + SUB C + LD C,A + LD B,0 + ADD IX,BC + LD C,B + ADC HL,BC + POP BC + EXX + LD A,C + EXX + EX AF,AF' + SCF + RET ;[]===========================================================[] ;Function: Write Sectors @@ -257,487 +295,362 @@ ERRDOS: ; HL:IX - Sector + Sector counter ; DE - Address + (Sector counter * Size sector) ;[]===========================================================[] -FDD_5x.WRITE: - EX AF,AF' - IN A,(SLOT3) - EX AF,AF' +FDD_5x_WRITE: EX AF,AF' + IN A,(SLOT3) + EX AF,AF' ;[]===========================================================[] ;Function: Long Write Sectors ; A - Disk ; HL:IX - Sector ; DE - Address ; B - Sector counter -; A'- Memory ID Block +; A'- Memory Page Number ;Return: ; HL:IX - Sector + Sector counter ; DE - Address + (Sector counter * Size sector) +;?? B - Sector counter ;[]===========================================================[] -FDD_5x.LONG_WRITE: - PUSH IY - PUSH BC - PUSH HL - PUSH IX - EX AF,AF' - LD C,A - EX AF,AF' - PUSH BC - CALL SET_DOS_ON - CALL S_FDD - CALL SPEED - CALL NTRACK - POP BC - EX DE,HL -; LD A,B -; OR A -; JP Z,RETDOS - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD IY,(FDD_INI_TABLE.FDD_0.B_P_S) - LD XH,C - LD A,(FDD_INI_TABLE.FDD_0.SECTORS) - LD C,A - EX AF,AF' - OUT (SLOT3),A -.DSK_LP2: - LD A,D - EXX - CALL SEEK - EXX - PUSH DE - PUSH BC - PUSH HL - CALL WR_SEC - JP C,ERRDOS - LD D,YH - LD E,YL - POP HL - POP BC - ADD HL,DE - JR NC,.THISWR - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD D,#C2 - LD E,XH - LD A,(DE) - LD XH,A - EX AF,AF' - OUT (SLOT3),A - SET 7,H - SET 6,H -.THISWR: - POP DE - LD A,C - INC E - CP E - JP NZ,.NINC_T2 - LD E,0 - INC D -.NINC_T2: - DJNZ .DSK_LP2 - CALL SET_DOS_OFF - LD A,XH - EX AF,AF' - EX DE,HL - POP IX - POP HL - POP BC - POP IY - LD A,B - LD C,B - INC B - DEC B - LD B,0 - JR NZ,.ADW8BIT - INC B -.ADW8BIT: - ADD IX,BC - LD BC,0 - ADC HL,BC - LD B,A - XOR A - RET - -; -;------------------------------- -;READ SECTOR -;------------------------------- -RD_SEC: LD D,5 ;RETRY COUNT -.RRETRY: - DI - PUSH DE - LD A,E - INC A - OUT (FDC_93.Sector),A -.FDREAD: - IN A,(SLOT3) - EX AF,AF' - LD A,XH - OUT (SLOT3),A - LD B,4 - LD C,FDC_93.Data - LD A,#80 ;COMMAND READ - OUT (FDC_93.Command),A -.FDR001: - IN A,(FDC_93.DrvCTRL) ;WAIT INTRQ or DRQ - AND #C0 - JR NZ,.FDR004 - INC DE - LD A,E - OR D - JR NZ,.FDR001 - DJNZ .FDR001 - SCF - JR .FDR005 -.FDR004: - INI ;READ BYTE -.FDR002: - IN A,(FDC_93.DrvCTRL) - AND #C0 - JR Z,.FDR002 - JP P,.FDR004 -.FDR005: - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' -;------------------------------- - POP DE - EI - IN A,(FDC_93.Command) - LD C,A -;R01 - JP C,.ERR_XRD -; JP C,ERRRD ;READ ERROR - AND #7F - RET Z - BIT 2,C - JR NZ,.ERDATA - LD A,5 ;SEEK ERROR - DEC D - JP Z,.RSTOP - PUSH DE - CALL RESWG ; RESET_WG - LD A,XL - CALL SEEK ; !!!!! посмотреть -.ERR_XRD: - POP DE - JR .RRETRY -.ERDATA: - DEC D ; POTERIA DANNYH - JR NZ,.RRETRY -.ERRRD: LD A,9 ;READ ERROR -.RSTOP: EX AF,AF' - LD A,#D0 - OUT (FDC_93.Command),A ;STOP OPERATION - EX AF,AF' - BIT 0,C - SCF - RET Z - LD A,6 ;SECTOR NOT FOUND /NO DISK/ - RET -; - +FDD_5x_LONG_WRITE: + EXX + LD B,#A0 ;COMMAND WRITE ;!HARDCODE CMD КР1818ВГ93 + EXX + JP FDD_5x_LONG_READ.RW_Shared ; ;------------------------------- ;WRITE SECTOR ;------------------------------- -WR_SEC: LD D,5 ;RETRY COUNT -.WRETRY: - DI - PUSH DE - LD A,E - INC A - OUT (FDC_93.Sector),A -.FDWRITE: - IN A,(SLOT3) - EX AF,AF' - LD A,XH - OUT (SLOT3),A - LD B,4 - LD C,FDC_93.Data - LD A,#A0 ;COMMAND WRITE - OUT (FDC_93.Command),A -.FDW001: - IN A,(FDC_93.DrvCTRL) ;WAIT INTRQ or DRQ - AND #C0 - JR NZ,.FDW004 - INC DE - LD A,E - OR D - JR NZ,.FDW001 - DJNZ .FDW001 - SCF - JR .FDW005 -.FDW004: - OUTI ;WRITE BYTE -.FDW002: - IN A,(FDC_93.DrvCTRL) - AND #C0 - JR Z,.FDW002 - JP P,.FDW004 -.FDW005: - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' -;------------------------------- - POP DE - EI - IN A,(FDC_93.Command) - LD C,A -;R01 - JP C,.ERR_XWR -; JP C,ERRWR ;WRITE ERROR - AND #7F - RET Z - BIT 6,C - LD A,8 ;WRITE PROTECT - JR NZ,.WSTOP - BIT 2,C - JR NZ,.EWDATA - LD A,5 ;SEEK ERROR - DEC D - JP Z,.WSTOP -.ERR_XWR: - PUSH DE - CALL RESWG ; RESET_WG - LD A,XL - CALL SEEK ; !!!!! посмотреть - POP DE - JR .WRETRY -.EWDATA: - DEC D ; POTERIA DANNYH - JR NZ,.WRETRY -.ERRWR: LD A,10 ;WRITE ERROR -.WSTOP: EX AF,AF' - LD A,#D0 - OUT (FDC_93.Command),A ;STOP OPERATION - EX AF,AF' - BIT 0,C - SCF - RET Z - LD A,6 ;SECTOR NOT FOUND /NO DISK/ - RET - +FDD_RW_SECTOR: LD D,5 ;RETRY COUNT +.RETRY: ;DI + PUSH HL + PUSH DE + LD A,E + INC A + OUT (FDC_93.Sector),A + IN A,(SLOT3) + EX AF,AF' + LD A,XH + OUT (SLOT3),A + ; + LD B,4 + LD C,FDC_93.Data + EXX + LD A,B ; COMMAND read or write + EXX + OUT (FDC_93.Command),A + ; +.wait_loop: IN A,(FDC_93.DrvCTRL) ;WAIT INTRQ or DRQ + AND %1100'0000 ;b6: DRQ (запрос данных = 1). b7: INTRQ (выполняется команда = 0). + JR NZ,.RW_PROC + INC DE + LD A,E + OR D + JR NZ,.wait_loop + DJNZ .wait_loop + SCF + JR .after_rw ; error + ; +.RW_PROC: EXX + BIT 5,B + EXX + ; [ ] 15/04/25 размер сектора больше, чем установлено в SYS_PAGE.FDD_TABLE.BytesPerSector вызовет ошибку + LD D,YH + LD E,YL + INC DE + ; + JR NZ,.write_loop + ;READ BYTE +.read_loop: DEC DE + LD A,D + OR E + JR Z,.SectorSizeError + ; + INI +.wait_data_r: IN A,(FDC_93.DrvCTRL) + AND %1100'0000 ;b6: DRQ (запрос данных = 1). b7: INTRQ (выполняется команда = 0). + JR Z,.wait_data_r + JP P,.read_loop ; JUMP if "выполняется команда = 0" +.rw_return: ; +.after_rw: EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + ; + POP DE + POP HL + ;EI + LD A,BIOS.Error.NotReady + JR C,.CMD_ERROR + ; + IN A,(FDC_93.Command) + LD C,A + AND #7F + ; NORMAL EXIT + RET Z + ; + BIT 6,C + LD A,BIOS.Error.WriteProtect + JR NZ,.error_exit + ; + BIT 2,C + JR NZ,.data_lost + ; + LD A,BIOS.Error.Seek +.CMD_ERROR: DEC D + JR Z,.error_exit + ; + PUSH DE + PUSH HL + CALL RESWG ; RESET_WG + LD A,XL + CALL SEEK ; !!!!! посмотреть + POP HL + POP DE + JR .RETRY + ; +.data_lost: DEC D ; потеря данных + JR NZ,.RETRY + ; + EXX + BIT 5,B + EXX + LD A,BIOS.Error.Read ; Error Read + JR Z,.error_exit + ; + LD A,BIOS.Error.Write ; Error Write + ; +.error_exit: EX AF,AF' + LD A,#D0 ;!HARDCODE CMD КР1818ВГ93 + OUT (FDC_93.Command),A ;STOP OPERATION + EX AF,AF' + BIT 0,C + SCF + RET Z + LD A,BIOS.Error.SectorNotFound + RET + ; + ;WRITE BYTE +.write_loop: DEC DE + LD A,D + OR E + JR Z,.SectorSizeError + ; + OUTI +.wwait_data: IN A,(FDC_93.DrvCTRL) + AND %1100'0000 ;b6: DRQ (запрос данных = 1). b7: INTRQ (выполняется команда = 0). + JR Z,.wwait_data + JP P,.write_loop + JP .rw_return + ; +.SectorSizeError: + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + POP DE + POP HL + ;EI + ; A = 0 + LD C,A + LD A,BIOS.Error.UnknownDevice + JR .error_exit ; ; Врубает третью карту портов -SET_DOS_ON: - EX AF,AF' - LD A,CNF_PORT.CNF_3 + ROM.BIOS - OUT (SYS_PORT.ROM),A ; - OPEN - EX AF,AF' - RET +SET_DOS_ON: EX AF,AF' + LD A,CNF_PORT.CNF_3 + ROM.BIOS + OUT (SYS_PORT.ROM),A ; - OPEN + EX AF,AF' + RET ; Врубает нулевую карту портов -SET_DOS_OFF: - EX AF,AF' - LD A,CNF_PORT.CNF_0 + ROM.BIOS - OUT (SYS_PORT.ROM),A ; - CLOSE - EX AF,AF' - RET +SET_DOS_OFF: EX AF,AF' + LD A,CNF_PORT.CNF_0 + ROM.BIOS + OUT (SYS_PORT.ROM),A ; - CLOSE + EX AF,AF' + RET + +; +S_FDD: PUSH BC + AND 1 + LD B,A + OR #3C + OUT (FDC_93.DrvCTRL),A + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(SYS_PAGE.FDD_TABLE.DISK) + AND #FE + OR B + LD (SYS_PAGE.FDD_TABLE.DISK),A + EX AF,AF' + OUT (SLOT3),A + POP BC + RET ; ; -FDD.SET720: - LD A,#01 ;!HARDCODE - OUT (#BD),A ;!HARDCODE - RET +CHANGE_SPEED: IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(SYS_PAGE.FDD_TABLE.DISK) + XOR #80 + LD (SYS_PAGE.FDD_TABLE.DISK),A + ;AND #80 + RLA + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + ;JR Z,FDD.SET720 + JR NC,FDD.SET720 + ;JP FDD.SET1440 ;CF=1 +FDD.SET1440: LD A,FDD_Density.SET_1440 + OUT (FDD_Density),A + RET ; +; +SET_SPEED: IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(SYS_PAGE.FDD_TABLE.DISK) + ;AND #80 + RLA + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + ;JR NZ,FDD.SET1440 + JR C,FDD.SET1440 + ;JR FDD.SET720 ;CF=0 +FDD.SET720: LD A,FDD_Density.SET_720 + OUT (FDD_Density),A + RET + + +; прерывания должны быть отключены +; выход: A - FDD_INIT_TABLE.DISK, B - sector size high byte +DISK_ID: EXX + CALL SET_SPEED + IN A,(FDC_93.Track) + OUT (FDC_93.Data),A + LD A,#18 ;!TODO выписать комманды ВГ ;SEARCH ;!HARDCODE CMD КР1818ВГ93 + CALL EXECOM + LD C,4 ; счётчик +.loop_reg_C: LD A,#C0 ;!HARDCODE CMD КР1818ВГ93 + OUT (FDC_93.Command),A + LD HL,#F000 ; счётчик +.loop_reg_HL: IN A,(FDC_93.DrvCTRL) + AND #C0 + JR NZ,.Read_Index + ; +.ID_LP4: DEC HL + LD A,H + OR L + JR NZ,.loop_reg_HL + CALL CHANGE_SPEED + DEC C + JR NZ,.loop_reg_C + EXX + SCF + RET + ; +.Read_Index: ; + ; Данные FDC_93.Data: + ; номер цилиндра BYTE + ; номер головки BYTE + ; номер сектора BYTE + ; длина сектора BYTE + ; контрольная сумма WORD + LD H,4 ; !HARDCODE счётчик до байта размера сектора +.ID_LP2: IN A,(FDC_93.Data) + DEC H + JR NZ,.ID_LP3 + LD L,A ; [ ] размера сектора (старший байт) +.ID_LP3: IN A,(FDC_93.DrvCTRL) + AND %1100'0000 + JR Z,.ID_LP3 + JP P,.ID_LP2 + LD A,L + EXX + LD B,A ; [ ] размера сектора (старший байт) + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(SYS_PAGE.FDD_TABLE.DISK) + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + AND #80 + RET ; -FDD.SET1440: - LD A,#21 ;!HARDCODE - OUT (#BD),A ;!HARDCODE - RET -; - -; -S_FDD: PUSH BC - AND 1 - LD B,A - OR #3C - OUT (FDC_93.DrvCTRL),A - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(FDD_INI_TABLE.FDD_0.DISK) - AND #FE - OR B - LD (FDD_INI_TABLE.FDD_0.DISK),A - EX AF,AF' - OUT (SLOT3),A - POP BC - RET -; - -; -MOTOR_OFF: - PUSH AF - LD A,#D0 - OUT (FDC_93.Command),A ;STOP OPERATION - LD A,#00 - OUT (FDC_93.DrvCTRL),A - LD A,#3C - OUT (FDC_93.DrvCTRL),A - CALL SET_DOS_OFF - POP AF - RET -; - -; -TURNSPD: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(FDD_INI_TABLE.FDD_0.F144) - XOR #80 - LD (FDD_INI_TABLE.FDD_0.F144),A - AND #80 - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' - JP Z,FDD.SET720 - JP FDD.SET1440 ;NZ -; - -; -SPEED: IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(FDD_INI_TABLE.FDD_0.F144) - AND #80 - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' - JP Z,FDD.SET720 - JP FDD.SET1440 ;NZ -; - -; -DISK_ID: - DI - EXX - CALL SPEED - IN A,(FDC_93.Track) - OUT (FDC_93.Data),A - LD A,#18 ;!TODO выписать комманды ВГ ;SEARCH ; !HARDCODE - CALL EXECOM - LD C,4 -.ID_LP0: - LD A,#C0 - OUT (FDC_93.Command),A - LD HL,#F000 -.ID_LP1: - IN A,(FDC_93.DrvCTRL) - AND #C0 - JR Z,.ID_LP4 -.ID_LP2: - IN A,(FDC_93.Data) -.ID_LP3: - IN A,(FDC_93.DrvCTRL) - AND #C0 - JR Z,.ID_LP3 - JP P,.ID_LP2 - EXX - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(FDD_INI_TABLE.FDD_0.F144) - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' - AND #80 - EI - RET -.ID_LP4: - DEC HL - LD A,H - OR L - JP NZ,.ID_LP1 - CALL TURNSPD - DEC C - JP NZ,.ID_LP0 - EXX - SCF - EI - RET -; - -; -SEEK: LD XL,A - LD C,A - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(FDD_INI_TABLE.FDD_0.DISK) - AND 1 - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' - SRL C - JR C,.GT001 - OR #3C -.GT001: OR #2C - OUT (FDC_93.DrvCTRL),A - IN A,(FDC_93.Track) - CP C - PUSH BC - CALL NZ,P50ms - POP BC - LD A,C - OUT (FDC_93.Data),A - IN A,(FDC_93.Track) - CP C - EX AF,AF' ;R.TRACK==PHISICAL TRACK - LD A,#18 - CALL EXECOM - RET C - EX AF,AF' - LD A,C - OUT (FDC_93.Track),A - RET Z -.STOL: PUSH BC - CALL P50ms - POP BC - RET +SEEK: LD XL,A + LD C,A + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(SYS_PAGE.FDD_TABLE.DISK) + AND 1 + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + SRL C + JR C,.GT001 + ; + OR #3C +.GT001: OR #2C + OUT (FDC_93.DrvCTRL),A + IN A,(FDC_93.Track) + CP C + CALL NZ,P50ms + LD A,C + OUT (FDC_93.Data),A + IN A,(FDC_93.Track) + CP C + EX AF,AF' ;R.TRACK==PHISICAL TRACK + LD A,#18 ;!HARDCODE CMD КР1818ВГ93 + CALL EXECOM + RET C + EX AF,AF' + LD A,C + OUT (FDC_93.Track),A + RET Z +.STOL: CALL P50ms + RET ; ;P750ms LD B,3 ;PMS2 LD A,255 ; CALL P1ms ; DJNZ PMS2 ; RET -P50ms: LD A,12 -.P1ms: LD C,255 -.PMS: DEC C - JR NZ,.PMS - DEC A - JR NZ,.P1ms - RET +P50ms: PUSH BC + LD A,12 +.P1ms: LD C,255 +.PMS: DEC C + JR NZ,.PMS + DEC A + JR NZ,.P1ms + POP BC + RET ; ; -RESWG: LD A,8 -EXECOM: OUT (FDC_93.Command),A - LD HL,#0000 -.WREST: DEC HL - LD A,H - OR L - SCF - RET Z - IN A,(FDC_93.DrvCTRL) - AND #80 - JR Z,.WREST - AND A - RET +RESWG: LD A,8 ;!HARDCODE CMD КР1818ВГ93 + ; +EXECOM: OUT (FDC_93.Command),A + LD HL,#0000 ; счётчик +.WREST: DEC HL + LD A,H + OR L + SCF + RET Z + ; + IN A,(FDC_93.DrvCTRL) + AND #80 + JR Z,.WREST + RET ; ; @@ -745,36 +658,55 @@ EXECOM: OUT (FDC_93.Command),A ; HL:IX - SECTOR ; H - TRACK, L - SECTOR ;HL:IX/SECTOR_PER_TRACK -NTRACK: - PUSH HL - EX (SP),IX - POP HL - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(FDD_INI_TABLE.FDD_0.SECTORS) - LD C,A - LD B,0 - EX AF,AF' - OUT (SLOT3),A - XOR A -.NTRK: INC A - SBC HL,BC - JR NC,.NTRK - EX AF,AF' - LD A,XL - OR XH - JR Z,.NTRK3 - EX AF,AF' - DEC IX - JR .NTRK -.NTRK3: EX AF,AF' - ADD HL,BC - DEC A - LD H,A - RET +NTRACK: PUSH HL + EX (SP),IX + POP HL + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(SYS_PAGE.FDD_TABLE.SECTORS) + LD C,A + LD B,0 + EX AF,AF' + OUT (SLOT3),A + XOR A +.NTRK: INC A + SBC HL,BC + JR NC,.NTRK + EX AF,AF' + LD A,XL + OR XH + JR Z,.NTRK3 + EX AF,AF' + DEC IX + JR .NTRK +.NTRK3: EX AF,AF' + ADD HL,BC + DEC A + LD H,A + RET ; - - +SAVE_INTERRUPTS: +.switch_off: PUSH AF + LD A,R + LD A,#80 + JP PE,.set_R + XOR A +.set_R: LD R,A + DI + POP AF + RET + ; ; +.restore: PUSH AF + LD A,R + BIT 7,A + JR Z,.set_di + EI + POP AF ; PE + RET + ; +.set_di: DI + POP AF ; PO + RET ;[]===========================================================[] \ No newline at end of file diff --git a/src/bios/exp/EXTENDED/HDD_DRIVER_6.asm b/src/bios/exp/EXTENDED/HDD_DRIVER_6.asm deleted file mode 100644 index ac3a106..0000000 --- a/src/bios/exp/EXTENDED/HDD_DRIVER_6.asm +++ /dev/null @@ -1,671 +0,0 @@ - -;======================================================== -;R03 !25.07.2001! BUG FIX WITH RETURN ERROR CODE -;R02 !24.07.2001! ADD SECONDARY CHANEL -;R01 !16.08.2000! REMOVED "DI" - -/* -;Write -IDE.Write.Command EQU #4153 ; #1F7 Command -IDE.Write.DriveCtrl EQU #4152 ; #1F6 Drive Control - -HDW_CLH EQU #0155 ; #1F5 Cylinder High -HDW_CLL EQU #0154 ; #1F4 Cylinder Low -HDW_SEC EQU #0153 ; #1F3 Sector -HDW_CNT EQU #0152 ; #1F2 Counter -HDW_ERR EQU #0151 ; #1F1 Error -HDW_DAT EQU #0150 ; #1F0 Data - -;Read -IDE.Read.Status EQU #4053 ; #1F7 Status (Control) -HDR_DRV EQU #4052 ; #1F6 Drive Control - -HDR_CLH EQU #0055 ; #1F5 Cylinder High -HDR_CLL EQU #0054 ; #1F4 Cylinder Low -HDR_SEC EQU #0053 ; #1F3 Sector -HDR_CNT EQU #0052 ; #1F2 Counter -HDR_ERR EQU #0051 ; #1F1 Error -HDR_DAT EQU #0050 ; #1F0 Data - -;Bits for IDE.Read.Status -;---[] -BSY EQU 7 -RDY EQU 6 -DRQ EQU 3 -ERR EQU 0 -;---[] - -HDD EQU 1 -CDROM EQU 2 - - -;EQU FOR IY+ -IDE.HDD_INIT_TABLE.Chanel EQU 0 -IDE.HDD_INIT_TABLE.SectorsPerTrack EQU 1 -IDE.HDD_INIT_TABLE.HeadsNumber EQU 2 -IDE.HDD_INIT_TABLE.CylinderNumberLow EQU 3 -IDE.HDD_INIT_TABLE.CylinderNumberHigh EQU 4 -IDE.HDD_INIT_TABLE.SectorsPerCylinderLow EQU 5 -IDE.HDD_INIT_TABLE.SectorsPerCylinderHigh EQU 6 -DTYPE_H EQU 7 - -IDE0 EQU #C1C0 -IDE1 EQU #C1C8 -IDE2 EQU #C1D0 -IDE3 EQU #C1D8 -*/ - -;IDE0 DB #FF ;DRIVE/HEAD REGISTER ;00 -; DB #FF ;SECTORS PER TRACK ;01 -; DB #FF ;HEADS ;02 -; DB #FF ;CYLINDERS LOW ;03 -; DB #FF ;CYLINDERS HIGH ;04 -; DB #FF ;SECTOR PER CYLINDER LOW ;05 -; DB #FF ;SECTOR PER CYLINDER HIGH ;06 -; DB #FF ;RESERVED ;07 - -;IDE1 DB #FF ;DRIVE/HEAD REGISTER ;00 -; DB #FF ;SECTORS PER TRACK ;01 -; DB #FF ;HEADS ;02 -; DB #FF ;CYLINDERS LOW ;03 -; DB #FF ;CYLINDERS HIGH ;04 -; DB #FF ;SECTOR PER CYLINDER LOW ;05 -; DB #FF ;SECTOR PER CYLINDER HIGH ;06 -; DB #FF ;RESERVED ;07 - -HDD_5x.RESET: ; !FIXIT не ресетится? -;For non-ATAPI drives, the only method a driver has of resetting a drive -; after a major error is to do a "software reset" on the bus. -; Set bit 2 (SRST, value = 4) in the proper Control Register for the -; bus. This will reset both ATA devices on the bus. Then, you have to -; clear that bit again, yourself. The master drive on the bus is -; automatically selected. - XOR A - RET - -SELECTH: - AND #0F - LD IY,IDE.INIT_TBL_IDE0 - JR Z,SELHH - DEC A - LD IY,IDE.INIT_TBL_IDE1 - - JR Z,SELHH - DEC A ;R02 - LD IY,IDE.INIT_TBL_IDE2 ;R02 - JR Z,SELHH ;R02 - DEC A ;R02 - LD IY,IDE.INIT_TBL_IDE3 ;R02 - - JR NZ,NODRIVE -SELHH: - EXX - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (C),A - - LD A,(IY+IDE.HDD_INIT_TABLE.Chanel) - AND #01 - LD A,#01 ;SECONDARY - JR NZ,SELCHAN - LD A,#21 ;PRIMARY -SELCHAN: - OUT (#BC),A ;R02 ; !HARDCODE ; !HARDCODE - - LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) - CP IDE.Device.HDD - LD A,(IY+IDE.HDD_INIT_TABLE.Chanel) - OUT (C),B - LD BC,IDE.Write.DriveCtrl - RES 0,A - OUT (C),A - EXX - RET Z -NODRIVE: - LD A,2 - SCF - RET - -;[]===========================================================[] -;Function: Get Current Media Parameters -; A - Disk -;Return: -; H - Heads -; L - Sectors per cylinder -; DE - Cylinders -; IX - Capacity sector in bytes -; B - Flags: ide chanel -;[]===========================================================[] -HDD_5x.GETMED: - CALL SELECTH - RET C - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD L,(IY+IDE.HDD_INIT_TABLE.SectorsPerTrack) - LD H,(IY+IDE.HDD_INIT_TABLE.HeadsNumber) - LD E,(IY+IDE.HDD_INIT_TABLE.CylinderNumberLow) - LD D,(IY+IDE.HDD_INIT_TABLE.CylinderNumberHigh) - LD B,(IY+IDE.HDD_INIT_TABLE.Chanel) - LD IX,512 - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' - AND A - RET - -;[]===========================================================[] -;Function: Set Current Media Parameters -; A - Disk -; H - Heads -; L - Sectors -; DE - Cylinders -; IX - Capacity sector in bytes -; B - Flags -;Return: None -;[]===========================================================[] -HDD_5x.SETMED: - CALL SELECTH - RET C - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD (IY+IDE.HDD_INIT_TABLE.SectorsPerTrack),L - LD (IY+IDE.HDD_INIT_TABLE.HeadsNumber),H - LD (IY+IDE.HDD_INIT_TABLE.CylinderNumberLow),E - LD (IY+IDE.HDD_INIT_TABLE.CylinderNumberHigh),D - LD (IY+IDE.HDD_INIT_TABLE.Chanel),B - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' - AND A - RET - -;[]===========================================================[] -;Function: Read Sectors -; A - Disk -; HL:IX - Sector -; DE - Address -; B - Sector counter -;Return: -; HL:IX - Sector + Sector counter -; DE - Address + (Sector counter * Size sector) -;[]===========================================================[] -;READ SECTOR(S) -HDD_5x.READ: - EX AF,AF' - IN A,(SLOT3) - EX AF,AF' -;[]===========================================================[] -;Function: Long Read Sectors -; A - Disk -; HL:IX - Sector -; DE - Address -; B - Sector counter -; A'- Memory ID Block -;Return: -; HL:IX - Sector + Sector counter -; DE - Address + (Sector counter * Size sector) -;[]===========================================================[] -;LONG READ SECTOR(S) -HDD_5x.LONG_READ: - PUSH IY - - SAFE_PORTY_2 - - PUSH BC - PUSH IX - PUSH HL - CALL RDS000 - EX DE,HL - JP C,HERRRD0 - LD A,XH - EX AF,AF' - POP HL - POP IX - POP BC - XOR A - CP B - LD C,B - LD B,A - JR NZ,RNOT256 - INC B - ADD IX,BC - LD B,C - ADC HL,BC - EX AF,AF' - JR RST8RDR - -RNOT256 ADD IX,BC - LD C,B - ADC HL,BC - EX AF,AF' - JR RST8RDR - -HERRRD0 LD B,A - LD C,XL - LD A,XH - EX AF,AF' - POP HL - POP IX - PUSH BC - LD B,0 - ADD IX,BC - LD C,B - ADC HL,BC - POP BC - POP AF - SUB C - LD C,A - LD A,B - LD B,C - SCF ;R03 - EX AF,AF' ;R03 -RST8RDR: - - RESTORE_PORTY - - POP IY - EX AF,AF' - RET - -;READ SECTOR(S) -RDS000: - CALL SELECTH - RET C - EXX - LD DE,#C140 ;WAIT BUSY=0 & READY=1 & ERR=0 - LD BC,IDE.Read.Status - CALL WAITPRT - EXX - RET C - EX AF,AF' - PUSH AF - PUSH DE - CALL PRESET - POP HL - POP AF - LD XL,0 - LD XH,A - LD BC,IDE.Write.Command - LD A,#020 ;READ WITH RETRY - OUT (C),A -;SAVE HL! -RDS002: EXX - LD DE,#8908 ;WAIT BUSY=0 & DRQ=1 & ERR=0 - LD BC,IDE.Read.Status - CALL WAITPRT - EXX - RET C - NOP ;R01 REMOVED "DI" ; !FIXIT - IN A,(SLOT3) - EX AF,AF' - LD A,XH - OUT (SLOT3),A - LD BC,IDE.Read.Data - LD D,#20 -RDS003: - DUP 16 - INI - EDUP - DEC D - JR NZ,RDS003 - EX AF,AF' - OUT (SLOT3),A - EI -; - LD A,H - OR L - JR NZ,.W44 - LD HL,#C000 - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD D,#C2 - LD E,XH - LD A,(DE) - LD XH,A - EX AF,AF' - OUT (SLOT3),A -.W44: INC XL ;INC LOADED SECTORS - EXX - LD DE,#C140 ;WAIT BUSY=0 & ERR=0 & READY=1 - LD BC,IDE.Read.Status - CALL WAITPRT - EXX - RET C - LD BC,IDE.Read.Status - IN A,(C) - BIT IDE.ControlBit.DataRequest,A - JR NZ,RDS002 - XOR A - RET - -;[]===========================================================[] -;Function: Write Sectors -; A - Disk -; HL:IX - Sector -; DE - Address -; B - Sector counter -;Return: -; HL:IX - Sector + Sector counter -; DE - Address + (Sector counter * Size sector) -;[]===========================================================[] -;WRITE SECTOR(S) -HDD_5x.WRITE: - EX AF,AF' - IN A,(SLOT3) - EX AF,AF' -;[]===========================================================[] -;Function: Long Write Sectors -; A - Disk -; HL:IX - Sector -; DE - Address -; B - Sector counter -; A'- Memory ID Block -;Return: -; HL:IX - Sector + Sector counter -; DE - Address + (Sector counter * Size sector) -;[]===========================================================[] -;WRITE SECTOR(S) -HDD_5x.LONG_WRITE: - PUSH IY - - SAFE_PORTY_2 - - PUSH IX - PUSH HL - PUSH BC - CALL WRS000 - EX DE,HL - JP C,HERRWR0 - LD A,XH - EX AF,AF' - POP HL - POP IX - POP BC - XOR A - CP B - LD C,B - LD B,A - JR NZ,WNOT256 - INC B - ADD IX,BC - LD B,C - ADC HL,BC - EX AF,AF' - JR RST8WRR - -WNOT256 ADD IX,BC - LD C,B - ADC HL,BC - EX AF,AF' - JR RST8WRR - -HERRWR0 LD B,A - LD C,XL - LD A,XH - EX AF,AF' - POP HL - POP IX - PUSH BC - LD B,0 - ADD IX,BC - LD C,B - ADC HL,BC - POP BC - POP AF - SUB C - LD C,A - LD A,B - LD B,C - SCF ;R03 - EX AF,AF' ;R03 -RST8WRR EXX - POP BC - OUT (C),B - EXX - POP IY - EX AF,AF' - RET - -;WRITE SECTOR(S) -WRS000: - CALL SELECTH - RET C - EXX - LD DE,#C140 ;WAIT BUSY=0 & READY=1 & ERR=0 - LD BC,IDE.Read.Status - CALL WAITPRT - EXX - RET C - EX AF,AF' - PUSH AF - PUSH DE - PUSH BC - LD D,#1D ;!!!!! CMOS глянуть - ;LD C,BIOS.CMOS_RD - ;RST ToBIOS_18 - CALL CMOS_RD - POP BC - AND 1 - JR Z,NOWP - POP HL - POP AF - EX AF,AF' - LD XL,0 - LD A,8 ;WRITE PROTECT - SCF - RET -NOWP CALL PRESET - POP HL - POP AF - LD XL,0 - LD XH,A - LD BC,IDE.Write.Command - LD A,#30 ;WRITE WITH RETRY - OUT (C),A -;SAVE HL! -WRS002: EXX - LD DE,#8908 ;WAIT BUSY=0 & DRQ=1 & ERR=0 - LD BC,IDE.Read.Status - CALL WAITPRT - EXX - RET C - DI - IN A,(SLOT3) - EX AF,AF' - LD A,XH - OUT (SLOT3),A - LD BC,IDE.Write.Data - LD D,#20 -WRS003: - DUP 16 - OUTI - EDUP - DEC D - JR NZ,WRS003 - EX AF,AF' - OUT (SLOT3),A - EI -; - LD A,H - OR L - JR NZ,.W33 - LD HL,#C000 - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD D,#C2 - LD E,XH - LD A,(DE) - LD XH,A - EX AF,AF' - OUT (SLOT3),A -.W33: INC XL ;INC SAVED SECTORS - EXX - LD DE,#C140 ;WAIT BUSY=0 & ERR=0 & READY=1 - LD BC,IDE.Read.Status - CALL WAITPRT - EXX - RET C - LD BC,IDE.Read.Status - IN A,(C) - BIT IDE.ControlBit.DataRequest,A - JR NZ,WRS002 - XOR A - RET - -;[]===========================================================[] -;Function: Verify Sectors -; A - Disk -; HL:IX - Sector -; B - Sector counter -;Return: None -;[]===========================================================[] -;VERIFY SECTOR(S) -HDD_5x.VERIFY: - PUSH IY - - SAFE_PORTY_2 - - PUSH IX - PUSH HL - CALL VRS000 - POP HL - POP IX - EXX - POP BC - OUT (C),B - EXX - POP IY - RET - -;VERIFY SECTOR(S) -VRS000: CALL SELECTH - RET C - EXX - LD DE,#C140 ;WAIT BUSY=0 & READY=1 & ERR=0 - LD BC,IDE.Read.Status - CALL WAITPRT - EXX - RET C - PUSH DE - CALL PRESET - POP HL - LD BC,IDE.Write.Command - LD A,#40 ; !HARDCODE VERIFY WITH RETRY - OUT (C),A -VRS002: LD BC,IDE.Read.Status - IN A,(C) - BIT IDE.ControlBit.Error,A - JR Z,VRS003 - SCF - RET -VRS003: LD DE,#C140 ;WAIT BUSY=0 & ERR=0 & READY=1 - LD BC,IDE.Read.Status - CALL WAITPRT - RET C - XOR A - RET - -; HL:IX - LBA SECTOR -; B - SECTOR COUNTER - -PRESET: LD A,B - LD BC,IDE.Write.Counter - OUT (C),A - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(IY+IDE.HDD_INIT_TABLE.Chanel) - LD BC,IDE.Write.DriveCtrl - OUT (C),A - BIT 6,A ;бит CHS/LBA ;!FIXIT сделать метками номера бит - LD E,XL - LD D,XH - CALL Z,LBA_CHS - LD BC,IDE.Write.Sector - OUT (C),E ;LBA 0..7 - LD BC,IDE.Write.CylinderLow - OUT (C),D ;LBA 8..15 - LD BC,IDE.Write.CylinderHigh - OUT (C),L ;LBA 16..23 - LD BC,IDE.Write.DriveCtrl - DEC B - IN A,(C) - AND #F0 - OR H ;LBA 24..27 - INC B - OUT (C),A - EX AF,AF' - OUT (SLOT3),A - AND A - RET - -; HL:DE - SECTOR OFFSET - -LBA_CHS: - LD C,(IY+IDE.HDD_INIT_TABLE.SectorsPerCylinderLow) - LD B,(IY+IDE.HDD_INIT_TABLE.SectorsPerCylinderHigh) -; HL:DE / BC => DE:IX HL-OSTATOK -DIV32X: LD XH,D - LD XL,E - EX DE,HL - LD HL,0 - LD A,#20 -DIV011: ADD IX,IX - EX DE,HL - ADC HL,HL - EX DE,HL - ADC HL,HL - SBC HL,BC - JR NC,DIV012 - ADD HL,BC - DEC A - JR NZ,DIV011 - JR DIV014 -DIV012: INC IX - DEC A - JR NZ,DIV011 -DIV014: LD E,(IY+IDE.HDD_INIT_TABLE.SectorsPerTrack) - LD D,0 - XOR A -CHS005: INC A - SBC HL,DE - JR NC,CHS005 - ADD HL,DE - DEC A - LD H,A - LD E,L - INC E - LD D,XL - LD A,XH - LD L,A - RET - -; D - MASK -; E - PATTERN -; BC - PORT -WAITPRT: - LD HL,#0000 -.P0: IN A,(C) - AND D - CP E - JR NZ,.P2 - AND A - RET -.P2: DEC HL - LD A,L - OR H - JP NZ,.P0 -.error: LD A,4 ;!HARDCODE error number - SCF - RET -;======================================================= \ No newline at end of file diff --git a/src/bios/exp/EXTENDED/IDE/ATAPI_DRV.ASM b/src/bios/exp/EXTENDED/IDE/ATAPI_DRV.ASM new file mode 100644 index 0000000..53a606c --- /dev/null +++ b/src/bios/exp/EXTENDED/IDE/ATAPI_DRV.ASM @@ -0,0 +1,1221 @@ +;[x] 18/12/2023. добавление/допиливание API CD-ROM (ATAPI) +;██████████████████████████████████████████████████████████████████████████ +;CD ROM DRIVE DRIVER +;--------------------------------------------------------------- +;Rev Date Name Description +;--------------------------------------------------------------- +; 02-08-2001 DNS Initial this module +;--------------------------------------------------------------- +;======================================================== + +;!TODO ;!TODO ;!TODO ;!TODO ;!TODO ;!TODO ;!TODO ;!TODO ;!TODO ;!TODO ;!TODO ;!TODO +; +; [ ] установка параметра максимального размера для чтения через DRV_SET_PAR +; +;---------------------------------------------------------------------------------- +MAX_ATAPI_SEC_SIZE EQU 4096/2 +PACKET_SIZE EQU 12 ; !FIXIT брать из IDENTIFY PACKET DEVICE +RAM_ATAPI_PK EQU SYS_PAGE.SHARED_BUFFER_32b +RAM_ATAPI_RW_CMD EQU SYS_PAGE.SHARED_BUFFER_32b+16 +MAX_DATA_PACKET_FOR_REQUEST_SENSE EQU 254 + + +_ZIP_WAITS_ EQU 128 + + ASSERT ((PACKET_SIZE % 4) = 0), "PACKET_SIZE must be an even number" + +;[]================================================================[#51] +;!FIXIT сделать настоящий ресет +ATAPI_5x_RESET: LD C,IDE.Device.ATAPI + CALL SELECT_DRIVE + RET C + LD B,50 +.loop: PUSH BC + CALL EXEC_TEST_CMD + ;!FIXIT ;[ ] sector size. сделать реинит HDD_INIT_TABLE + POP BC + RET NC + LD C,A + ; + ;CALL ATAPI_CHECK_MEDIA_CHANGED.noWait + ;RET C + CP BIOS.Error.ATAPI.UnitAttention + SCF + RET Z + ; + CP BIOS.Error.ATAPI.MediumError + SCF + RET Z + ; не трогать прерывания + ; EI + ; HALT + EXX + XOR A +.pause_loop: LD B,A + DJNZ $ + DEC A + JR NZ,.pause_loop + EXX + DJNZ .loop + LD A,C + AND A + SCF + RET NZ + RET +/* +HL = 1e00 + B = 1 +ATAPI_WAITPRT.LOOP +DE = 00FF +*/ +;[]================================================================[#51] + + +;[]================================================================[#58] +;Function: Get Current Media Parameters +; A - Disk +;Return: +; H - Heads ; [ ] For ATAPI HL:DE - media size in sectors +; L - Sectors per cylinder ; +; DE - Cylinders ; +; IX - Capacity sector in bytes +; B - Flags: MASTER/SLAVE, LBA/CHS +; [ ] A - HDD_INIT_TABLE.MediaParameters +; IF media changed +; [ ] CF' = 1, A' = error number UnitAttention +ATAPI_5x_GET_PAR: + LD C,IDE.Device.ATAPI + CALL SELECT_DRIVE + RET C + ; +.DriveSelected: IN A,(SLOT3) + AND A + PUSH AF + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + ; + ; [ ] sector size. media changed + RES 1,(IY + IDE.HDD_INIT_TABLE.MediaParameters) ; [ ] removable media + CALL ATAPI_CHECK_MEDIA_CHANGED + EX AF,AF' + POP AF + EX AF,AF' + JR NC,.get_data + ; + CP BIOS.Error.ATAPI.UnitAttention + JR Z,.UnitAttention + ; + CP BIOS.Error.ATAPI.MediumError + JR NZ,.unknown_error + ;!FIXIT костыль + LD A,BIOS.Error.ATAPI.UnitAttention ;!FIXIT костыль + RES 1,(IY + IDE.HDD_INIT_TABLE.MediaParameters) ; [ ] removable media + ; +.unknown_error: LD HL,#FFFF + LD D,H + LD E,L + PUSH HL + POP IX + SCF + EX AF,AF' ; тут маскируем ошибку, изначально CF=1 только если устройство отсутствует + OUT (SLOT3),A + RET + ; +.UnitAttention: RES 1,(IY + IDE.HDD_INIT_TABLE.MediaParameters) ; [ ] removable media + EX AF,AF' + SCF + EX AF,AF' +.get_data: LD A,(IY+IDE.HDD_INIT_TABLE.MediaParameters) + AND %000'0100 + CALL NZ,.RereadCapacity + ; + LD A,(IY+IDE.HDD_INIT_TABLE.MediaParameters) + LD B,(IY+IDE.HDD_INIT_TABLE.DRV_Flags) + ; [ ] sector size + LD E,(IY+IDE.HDD_INIT_TABLE.SectorSize) + LD D,(IY+IDE.HDD_INIT_TABLE.SectorSize + 1) + LD XL,E + LD XH,D + ; [ ] media size + LD L,(IY+IDE.HDD_INIT_TABLE.MediaSizeHigh) + LD H,(IY+IDE.HDD_INIT_TABLE.MediaSizeHigh+1) + LD E,(IY+IDE.HDD_INIT_TABLE.MediaSizeLow) + LD D,(IY+IDE.HDD_INIT_TABLE.MediaSizeLow+1) + ; + EX AF,AF' + OUT (SLOT3),A + LD A,BIOS.Error.ATAPI.UnitAttention ; если CF, то номер ошибки + EX AF,AF + RET +.RereadCapacity: + EX AF,AF' + PUSH AF + CALL GET_ATAPI_CAPACITY + POP AF + EX AF,AF' + RET +;[]================================================================[#58] + + +;[]================================================================[#59] +; [ ] media changed +ATAPI_5x_SET_PAR: + LD L,B + LD C,IDE.Device.ATAPI + CALL SELECT_DRIVE + RET C + ; + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD (IY+IDE.HDD_INIT_TABLE.MediaParameters),B + EX AF,AF + OUT (SLOT3),A + RET +;[]================================================================[#59] + + + +;!TODO +; atapi.pdf стр. 24 запись/чтение могут быть максимальными блоками в несколько заходов +;[]================================================================[#55] +;Function: Read Sectors +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter +;Return: +; HL:IX - Sector + Sector counter +; DE - Address + (Sector counter * Size sector) +;READ SECTOR(S) +ATAPI_5x_READ: ;PUSH IY ; !FIXIT зачем? + LD C,0 ; признак short + EX AF,AF' + IN A,(SLOT3) + EX AF,AF' + JR ATAPI_5x_LONG_READ.main +;[]================================================================[#52] +;Function: Long Read Sectors +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter +; A'- Memory Page Number +;Return: +; HL:IX - Sector + Sector counter +; DE - Address + (Sector counter * Size sector) +;LONG READ SECTOR(S) +ATAPI_5x_LONG_READ: + ;AND A + ; + ;PUSH IY ; !FIXIT зачем? + LD C,1 ; признак long +.main: EX AF,AF' + AND A ;read + EX AF,AF' + JR ATAPI_BEGIN_RW + ; + ; SAFE_PORTY_2 + ; PUSH BC + ; PUSH IX + ; PUSH HL + ; ; + ; CALL RW_ATAPI_SECTORs + ; ; [ ] sector size. media changed + ; JP ATA_5x_LONG_READ.shared + ; JP NC,ATA_5x_LONG_READ.shared + ; CP BIOS.Error.UnitAttention + ; JR Z,ATAPI_MEDIA_ERROR + ; SCF +;[]================================================================[#52] +; INPUT: +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter +; A'- Memory Page Number +; CF'=1 - write, CF'=0 - read +; +; OUTPUT: +; +RW_ATAPI_SECTORs: + PUSH BC + LD C,IDE.Device.ATAPI + CALL SELECT_DRIVE + POP BC + RET C + ; + EXX + LD C,SLOT3 + IN B,(C) + PUSH BC + LD A,SYS_PAGE + OUT (C),A + ; [ ] media change + LD A,(IY + IDE.HDD_INIT_TABLE.MediaParameters) + AND %0000'0010 + JR NZ,.error_media + ; + LD HL,ATAPI_CMD_PACKET.READ + EX AF,AF' + JR NC,.read_cmd + LD HL,ATAPI_CMD_PACKET.WRITE +.read_cmd: EX AF,AF' + LD DE,RAM_ATAPI_RW_CMD + LD BC,PACKET_SIZE + LDIR + EXX + ; + LD A,H + LD H,L + LD L,A + LD (RAM_ATAPI_RW_CMD + ATAPI_PACKET.SECTOR+0),HL + LD A,XH + LD (RAM_ATAPI_RW_CMD + ATAPI_PACKET.SECTOR+2),A ;R01 + LD A,XL + LD (RAM_ATAPI_RW_CMD + ATAPI_PACKET.SECTOR+3),A ;R01 + LD A,B + LD (RAM_ATAPI_RW_CMD + ATAPI_PACKET.COUNTER+1),A ;R01 + ; + LD YL,C ; признак short/long из C в YL + LD HL,RAM_ATAPI_RW_CMD + CALL EXEC_PACKET_COMMAND.start + ; +.exit: POP BC + OUT (C),B + RET + ; +.error_media: EXX + LD A,BIOS.Error.ATAPI.UnitAttention + SCF + JR .exit + +;[]===========================================================[#52, #55] + +ATAPI_BEGIN_RW: SAFE_PORTY_2 + PUSH BC + PUSH IX + PUSH HL + ; + CALL RW_ATAPI_SECTORs + ; + JP ATA_5x_LONG_READ.shared + +;[]================================================================[#56] +;Function: Write Sectors +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter +;Return: +; HL:IX - Sector + Sector counter +; DE - Address + (Sector counter * Size sector) +;WRITE SECTOR(S) +ATAPI_5x_WRITE: ;PUSH IY ; !FIXIT зачем? + ; проба бага + LD C,0 ; признак short + ;LD C,1 ; признак long + ; + EX AF,AF' + IN A,(SLOT3) + EX AF,AF' + JR ATAPI_5x_LONG_WRITE.main +;[]================================================================[#53] +;Function: Long Write Sectors +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter +; A'- Memory Page Number +;Return: +; HL:IX - Sector + Sector counter +; DE - Address + (Sector counter * Size sector) +;WRITE SECTOR(S) +ATAPI_5x_LONG_WRITE: + ;AND A + ; + ;PUSH IY ; !FIXIT зачем? + LD C,1 ; признак long +.main: EX AF,AF' + SCF ;write + EX AF,AF' + JR ATAPI_BEGIN_RW + ; + ; SAFE_PORTY_2 + ; PUSH BC + ; PUSH IX + ; PUSH HL + ; ; + ; CALL RW_ATAPI_SECTORs + ; ; + ; JP ATA_5x_LONG_READ.shared + +;[]================================================================[#57] +;Function: Detect Disk +; A - Disk +;Return: CF=0 - A=Drive type +; B=MediaParameters byte ; [ ] media change +; CF=1 - drive not present, A=#02 +; ATAPI_5x_DETECT: LD C,IDE.Device.ATAPI +; AND %1011'1111 +; .shared: LD D,A +; LD E,C +; PUSH DE +; CALL DRV_DETECT +; POP DE +; RET C +; ; +; PUSH AF +; LD C,SLOT3 +; IN B,(C) +; LD A,SYS_PAGE +; OUT (C),A +; INC HL ;!HARDCODE HDD_INIT_TABLE +; INC HL +; INC HL +; LD A,(HL) +; OUT (C),B +; LD B,A +; AND %0000'0011 ;[ ] media change переделать логику тут и в ДСС? ; !FIXIT +; JR NZ,.error +; ; +; .exit: POP AF +; RET +; ; +; .error: AND %0000'0010 +; JR NZ,.UnitAttention +; ; +; LD A,D +; LD C,E +; CALL SELECT_DRIVE +; CALL ATAPI_CHECK_MEDIA_CHANGED +; JR NC,.exit +; POP BC +; RET +; ; +; .UnitAttention: POP AF +; LD A,BIOS.Error.ATAPI.UnitAttention +; SCF +; RET +;[]================================================================[#57] +;[]================================================================[#57] +;Function: Detect Disk +; A - Disk +;Return: CF=0 - A=Drive type +; B=MediaParameters byte ; [ ] media change +; CF=1 - drive not present, A=#02 +ATAPI_5x_DETECT: + LD C,IDE.Device.ATAPI + JP ATA_5x_DETECT.shared +;[]================================================================[#57] + +;[]================================================================[#5E] +; [ ] +;Function: Extended +; A - Disk +; B - SubFunction +;Return: +; [ ] расписать в доке +ATAPI_5x_Extended: + LD C,IDE.Device.ATAPI + CALL SELECT_DRIVE + RET C + ; + LD A,B + CP 2 + JR C,TRAY_FN ; B = 0 или 1 + ; + JR Z,ATAPI_REQUEST_SENSE ; B = 2 + ; + CP 3 + JR Z,ATAPI_CUSTOM_CMD + ; ... + LD A,BIOS.Error.InvalidSubFunction + SCF + RET +;[]================================================================[#5E] + +;----------------------------------------------------------------------;!TODO сделать доступной через расширенную функцию API +; вход: DE - адрес для данных +ATAPI_REQUEST_SENSE: + IN A,(SLOT3) + EX AF,AF' +.FN: LD HL,ATAPI_CMD_PACKET.REQUEST_SENSE + JR EXEC_PACKET_COMMAND.start +;----------------------------------------------------------------------; + +;[ ] media changed +;----------------------------------------------------------------------; +ATAPI_CHECK_MEDIA_CHANGED: + CALL EXEC_TEST_CMD ;!FIXIT а может и не надо + RET C + ; +.next_check: EXX + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + ; + LD A,(IY + IDE.HDD_INIT_TABLE.MediaParameters) + OUT (C),B + EXX + RRA + RRA + LD A,BIOS.Error.ATAPI.UnitAttention + RET +;----------------------------------------------------------------------; + + +;----------------------------------------------------------------------; +; ATAPI_CHECK_ERROR: +; CALL ATAPI_GET_ERROR_REG +; ;CP BIOS.Error.ATAPI.NoSence +; ;JP Z,ATAPI_MEDIA_ERROR +; CP BIOS.Error.ATAPI.NotReady +; JP Z,ATAPI_MEDIA_ERROR +; CP BIOS.Error.ATAPI.UnitAttention +; JP Z,ATAPI_MEDIA_ERROR +; ; +; SCF +; RET +;----------------------------------------------------------------------; + + +;----------------------------------------------------------------------; +; HL - указатель на пакетную команду (первый или второй слот) +; DE - указатель на буффер для команды +ATAPI_CUSTOM_CMD: + IN A,(SLOT3) + EX AF,AF' + LD A,1 ; признак, что ошибка смены носителя НЕ обрабатываться в EXEC_PACKET_COMMAND + JP EXEC_PACKET_COMMAND.start_custom +;----------------------------------------------------------------------; + + +;----------------------------------------------------------------------; +TRAY_FN: LD HL,ATAPI_CMD_PACKET.CLOSE + LD DE,0 ; маркер того, что не нужно читать с устройства в ОЗУ + DEC A + JR Z,EXEC_PACKET_COMMAND.start + LD HL,ATAPI_CMD_PACKET.OPEN + ;JR EXEC_PACKET_COMMAND + +; INPUT: HL - AP packet (12bytes) +; DE - address for/with data if needed +; A' - начальная страница для R/W Long +; +; RETURN: CF - ERROR +; ;!FIXIT номера неправильные +; !TODO CD ERRORS to INCLUDES +; #01 - RECOVERED ERROR +; #02 - NOT READY +; #03 - MEDIUM ERROR +; #04 - HARDWARE ERROR +; #05 - ILLEGAL REQUEST +; #06 - UNIT ATTETION +; #07 - DATA PROTECT +; #0B - ABORTED COMMAND +; #80 - TIME OUT +EXEC_PACKET_COMMAND: +; .error_APLOOP: LD A,BIOS.Error.ATAPI.UnitAttention +; RET + ;CALL ATAPI_GET_ERROR_REG + +.error_ex: EX DE,HL +.error: CP #FF +.error_fail: SCF + RET NZ + LD A,BIOS.Error.Failure + RET + ; +.error_TimeOut: CP #FF + EX DE,HL + JR Z,.error_fail + LD A,BIOS.Error.ATAPI.TimeOut + SCF + RET + ; + ; +; +.start: XOR A ; признак того, что ошибка смены носителя должна обрабатываться в EXEC_PACKET_COMMAND +.start_custom: EXX + LD C,A ; признак того, что ошибка смены носителя должна обрабатываться в EXEC_PACKET_COMMAND + CALL ATAPI_WAITPRT + EXX + JR NC,.READY + ; +.reset: LD BC,IDE.Write.Command + LD A,IDE.CMD.ATAPI.Reset + OUT (C),A + ; + LD B,#80 +.pause: DJNZ .pause + ; + EXX + CALL ATAPI_WAITPRT + EXX + JR C,.error_ex + ; +.READY: LD C,SLOT3 + IN B,(C) + PUSH DE + PUSH BC + ; + LD A,SYS_PAGE + OUT (C),A + LD DE,RAM_ATAPI_PK ;!FIXIT может на стеке выделять место? + LD BC,PACKET_SIZE + LDIR + ; + POP BC + POP DE + OUT (C),B + ; + XOR A + EXX + LD H,C ; признак того, что ошибка смены носителя должна обрабатываться в EXEC_PACKET_COMMAND + LD BC,IDE.Write.Features + OUT (C),A + LD DE,MAX_ATAPI_SEC_SIZE ;SIZE BLOCK ;!HARDCODE доставать из переменной какой-нибудь + LD BC,IDE.Write.ByteCountLow + OUT (C),E + LD BC,IDE.Write.ByteCountHigh + OUT (C),D + LD BC,IDE.Write.Command + LD A,IDE.CMD.ATAPI.Packet + OUT (C),A + LD C,H ; признак того, что ошибка смены носителя должна обрабатываться в EXEC_PACKET_COMMAND + CALL ATAPI_WAITPRT + EXX + JR C,.error_ex + ; + EXX + LD DE,256*(IDE.CtrlByte.DataRequest+IDE.CtrlByte.Error)+IDE.CtrlByte.DataRequest + CALL ATAPI_WAITPRT.Custom + EXX + JR C,.error_TimeOut + ; + ; EXEC ATAPI PACKET COMMAND +.YEP_DRQ: LD C,SLOT3 + IN B,(C) + PUSH BC + LD A,SYS_PAGE + OUT (SLOT3),A + LD HL,RAM_ATAPI_PK + LD BC,IDE.Write.Data + LD A,PACKET_SIZE/4 ; !FIXIT брать из IDENTIFY PACKET DEVICE +.OUTPKT: OUTI + OUTI + OUTI + OUTI + DEC A + JR NZ,.OUTPKT + ; + POP BC + OUT (C),B + ; pause + ; LD B,0 + ; DJNZ $ + ; DJNZ $ + ; + EX AF,AF' + LD XH,A ; страница для R/W_LONG + EX AF,AF' + ;A=0 + LD XL,A + EX DE,HL + ; +.AP_LOOP: ;CALL ATAPI_WAITPRT.wait_NZ + LD B,_ZIP_WAITS_ + DJNZ $ + CALL ATAPI_CHECK_DRV + JP C,.error;_APLOOP + RET Z + ;====== IF DATA REQUEST ===============================================; + IN A,(SLOT3) + EX AF,AF' ;>-----------> \ + ; + LD A,XH + OUT (SLOT3),A + CALL ATAPI_PREPARE_RW + RET NC + JR Z,.WRITE_DATA + ;READ +.read_loop: INI + INI + DEC DE + LD A,D + OR E + JR NZ,.read_loop + ; +.return_rw: EX AF,AF' ;<-----------< / + INC XL ;INC LOADED SECTORS + OUT (SLOT3),A + ; + LD A,H + OR L + JR NZ,.AP_LOOP + ; short/long + ; A = 0 + SUB YL + JR NC,.END_BUFFER + ; next page in mem block + CALL CHANGE_MEM_BLK + JR .AP_LOOP + ;WRITE +.WRITE_DATA: INC B ; LD BC,IDE.Write.Data +.write_loop: OUTI + OUTI + DEC DE + LD A,D + OR E + JR NZ,.write_loop + JR .return_rw + ; ; +.END_BUFFER: ;CALL ATAPI_WAITPRT.wait_NZ + LD B,_ZIP_WAITS_ + DJNZ $ + CALL ATAPI_CHECK_DRV + JP C,.error + JR NZ,ATAPI_IdlePasses.Enter + RET + ; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +ATAPI_IdlePasses: + ;CALL ATAPI_WAITPRT.wait_NZ + LD B,_ZIP_WAITS_ + DJNZ $ + CALL ATAPI_CHECK_DRV + JP C,EXEC_PACKET_COMMAND.error + JP Z,EXEC_PACKET_COMMAND.error_fail + ; +.Enter: CALL ATAPI_PREPARE_RW + RET NC + JR Z,.write_data + ; +.read_loop: IN F,(C) ; читаем по 1 разу с чётного адреса, читается WORD + DEC DE + LD A,D + OR E + JR NZ,.read_loop + JR ATAPI_IdlePasses + ; +.write_data: ; A = 0 + OUT (C),A ; кидаем 0 в регистр защёлку IDE + INC B +.write_loop: XOR A + OUT (C),A ; пишем по 1 разу в нечётный адрес, пишется WORD + DEC DE + LD A,D + OR E + JR NZ,.write_loop + JR ATAPI_IdlePasses + ; +; выход: +; CF,ZF ATAPI_WAITPRT Error или Check Condition со внешней обработкой +; ZF No errors, no data request +; NZ,NC DATA REQUEST +; CF Error +ATAPI_CHECK_DRV: + ;EX DE,HL + EXX + ;CALL .zeroWait + CALL ATAPI_WAITPRT + EXX + ; ZF=1 + RET C + ; + ; [ ] media change. а надо ли тут? ;!FIXIT лучше блокировать носитель + LD A,high IDE.Read.Status + IN A,(low IDE.Read.Status) + ; + AND IDE.CtrlByte.DataRequest + IDE.CtrlByte.Error + RET Z ;NO DATA REQUEST. A = 0: BIOS.Error.NoErrors + RRA ; Checking IDE.CtrlByte.CheckCondition + RET NC ; DataRequest CF=0, ZF=0 + ; + CALL ATAPI_GET_ERROR_REG + EXX + DEC C ; признак того, что ошибка смены носителя должна обрабатываться в EXEC_PACKET_COMMAND + EXX + SCF + RET Z ; выход, если ошибка обрабатывается не в EXEC_PACKET_COMMAND + ; + ; CP BIOS.Error.ATAPI.NoSence + ; JP Z,ATAPI_MEDIA_ERROR + CP BIOS.Error.ATAPI.NotReady + JP Z,ATAPI_MEDIA_ERROR + CP BIOS.Error.ATAPI.UnitAttention + JP Z,ATAPI_MEDIA_ERROR + ; + ;CP BIOS.Error.ATAPI.IllegalRequest + ;RET Z + ; + SCF + RET + ; +; .zeroWait: ;LD B,2 +; LD HL,#800 +; .loop: LD A,high IDE.Read.Status +; IN A,(low IDE.Read.Status) +; AND A +; RET NZ +; DEC HL +; LD A,H +; OR L +; JR NZ,.loop +; ;DJNZ .loop +; RET + +ATAPI_PREPARE_RW: + LD BC,IDE.Read.ByteCountLow + IN E,(C) + INC C ;LD BC,IDE.Read.ByteCountHigh + IN D,(C) ;TRANSFER BLOCK SIZE + ; + LD A,D + OR E + RET Z ;BLOCK = 0 + ; + ; уменьшаем счётчик загружаемых байтов в 2 раза. Читаем по 2 байта + SRL D + RR E + ; + LD BC,IDE.Read.InterruptReason + IN A,(C) + AND IDE.InterruptReasonByte.IO + LD BC,IDE.Read.Data + SCF + RET + + +; .AddrOverflow: EX DE,HL +; AND A +; SBC HL,DE +; EX DE,HL +; RET + +; +; !TODO холостое чтение +; .error_buffer: AND A +; SBC HL,DE +;.NULL: +;.RD_N_CD: IN A,(C) +; DEC B +; IN A,(C) +; DEC B +; DEC DE +; DEC DE +; LD A,D +; OR E +; JR NZ,.RD_N_CD +; ; DE = 0 +; JR .AP_LOOP +;----------------------------------------------------------------------; + + +;----------------------------------------------------------------------; +; портим только регистр AF +ATAPI_GET_ERROR_REG: + XOR A ;LD BC,IDE.Read.Error + IN A,(IDE.Read.Error) ;IN A,(C) + RRCA + RRCA + RRCA + RRCA + AND #0F + OR BIOS.Error.ATAPI + RET +;----------------------------------------------------------------------; + + + +;----------------------------------------------------------------------; +; D - MASK, E - PATTERN +; !!! некоторые функции надеются, что на выходе всегда ZF +; не должна трогать рег. C +ATAPI_WAITPRT: LD DE,256*IDE.CtrlByte.Busy + 0 +.Custom: LD B,9 ; 3 = общая задержка около секунды + LD HL,#0000 + ; 4 128 768 +.LOOP: LD A,high IDE.Read.Status + IN A,(low IDE.Read.Status) + CP #FF + SCF + RET Z + ; + AND D + CP E + RET Z + ; + DEC HL + LD A,H + OR L + JR NZ,.LOOP + ; + ; LD A,high IDE.Read.Status + ; IN A,(low IDE.Read.Status) + ; CP #FF + ; SCF + ; RET Z + ; + ; 1 392 512 256 + DJNZ .LOOP + ; + ; LD A,high IDE.Read.Status + ; IN A,(low IDE.Read.Status) + ; INC A ;CP #FF + ; SCF + ; RET Z + ; + LD A,BIOS.Error.Busy + SCF + RET + ; +; .wait_NZ: LD B,2 ; 50 - задержка определённая тестами на IOMEGA ZIP Drive +; .NZ_loop: LD A,high IDE.Read.Status +; IN A,(low IDE.Read.Status) +; LD C,A +; AND A +; CALL NZ,PutHexNumb +; ;INC A +; ;RET NZ +; ;AND IDE.CtrlByte.Busy + IDE.CtrlByte.DataRequest + IDE.CtrlByte.CheckCondition +; ;INC A +; ;AND A +; ;RET NZ +; DJNZ .NZ_loop +; RET +;----------------------------------------------------------------------; + + +;----------------------------------------------------------------------; +;Процедура преобразования 8битовых чисел в шестнадц. текст +;На вход: +; HL - адрес буфера +; А - байт +;На выход: +; DE - два байта шестнадцатеричного текста +; PutHexNumb: PUSH IX +; PUSH IY +; PUSH AF +; EX AF,AF' +; PUSH AF +; EX AF,AF' +; PUSH DE +; PUSH HL +; PUSH BC +; LD A,C +; EXX +; PUSH DE +; PUSH HL +; PUSH BC +; ; +; PUSH AF +; RRCA +; RRCA +; RRCA +; RRCA +; AND #0F +; ADD A,#90 +; DAA +; ADC A,#40 +; DAA +; LD E,A +; POP AF +; AND #0F +; ADD A,#90 +; DAA +; ADC A,#40 +; DAA +; LD D,A +; ; +; LD HL," " +; PUSH HL +; PUSH DE +; LD L,0 +; ADD HL,SP +; ; +; SCF +; LD B,COLORS.CGA.INK.LGRAY + COLORS.CGA.PAPER.BLACK +; EX AF,AF' +; AND A +; LD A,B +; CALL LP_PR_LINE_DIR.START +; POP HL +; POP HL +; ; +; POP BC +; POP HL +; POP DE +; EXX +; POP BC +; POP HL +; POP DE +; POP AF +; EX AF,AF' +; POP AF +; POP IY +; POP IX +; RET + ; +;----------------------------------------------------------------------; + + +;----------------------------------------------------------------------; +; D - MASK, E - PATTERN +; !!! некоторые функции надеются, что на выходе всегда ZF +; не должна трогать рег. C +; ATAPI_WAITPRT: LD DE,256*IDE.CtrlByte.Busy + 0 +; .Custom: +; .LOOP: LD A,high IDE.Read.Status +; IN A,(low IDE.Read.Status) +; CP #FF +; JR Z,.error +; ; +; AND D +; CP E +; RET Z +; JR .LOOP +; ; +; ; LD A,high IDE.Read.Status +; ; IN A,(low IDE.Read.Status) +; ; INC A ;CP #FF +; ; SCF +; ; RET Z +; ; ; +; ; LD A,BIOS.Error.Busy +; ; RET +; ; +; .error: SCF +; RET +;----------------------------------------------------------------------; + +;----------------------------------------------------------------------; +; DE - buffer +ATAPI_READ_CAPACITY_DATA: + LD BC,28 ;счётчик + ; +.loop: PUSH BC + PUSH DE + LD A,SYS_PAGE + EX AF,AF' + LD A,1 + LD HL,ATAPI_CMD_PACKET.READ_CAPACITY_DATA + CALL EXEC_PACKET_COMMAND.start_custom + POP DE + POP BC + RET NC + ; + CALL ATAPI_GET_ERROR_REG + CP BIOS.Error.ATAPI.NotReady + SCF + RET NZ + ; + PUSH BC + CALL ATAPI_MEDIA_ERROR + CP BIOS.Error.ATAPI.NotReady + SCF + POP BC + RET NZ + ; + CPI + RET PO ;счётчик + ; + LD HL,0 +.pause: DEC HL + LD A,H + OR L + JR NZ,.pause + ; + JP .loop + ;RET +;----------------------------------------------------------------------; + + +;----------------------------------------------------------------------; +; ATAPI_TEST: LD HL,ATAPI_CMD_PACKET.TEST_UNIT_READY +; LD DE,0 ; маркер того, что не нужно читать с устройства в ОЗУ +; JP EXEC_PACKET_COMMAND +;----------------------------------------------------------------------; + + +;----------------------------------------------------------------------; +ATAPI_MEDIA_ERROR: + PUSH IX + PUSH HL + ; + IN A,(SLOT3) + PUSH AF + LD A,SYS_PAGE + OUT (SLOT3),A + EX AF,AF' ; set page with buffer to SYS_PAGE + LD DE,SYS_PAGE.SHARED_BUFFER_256b + CALL ATAPI_REQUEST_SENSE.FN + ; + LD A,(SYS_PAGE.SHARED_BUFFER_256b + 2) ; SenceKey + CP 2 ; NOT READY + JR Z,.Not_Ready + CP 6 ; UNIT ATTENTION + JR NZ,.unkn_error + ; + LD A,(SYS_PAGE.SHARED_BUFFER_256b + 12) ; AdditionalSenceKey + CP #28 ; NOT READY TO READY TRANSITION + JR Z,.MedCh3 + CP #29 ; POWER ON, RESET OR BUS DEVICE RESET OCCURRED + JR Z,.MedChanged + JR .unkn_error + ; +.MedCh3: LD A,(SYS_PAGE.SHARED_BUFFER_256b + 13) ; AdditionalSenseCodeQualifier. 0 + AND A + JR NZ,.unkn_error + ; +.MedChanged: LD A,(IY + IDE.HDD_INIT_TABLE.MediaParameters) + OR %0000'0011 + LD (IY + IDE.HDD_INIT_TABLE.MediaParameters),A + ; + CALL GET_ATAPI_CAPACITY +; LD DE,SYS_PAGE.TMP_BUFFER +; CALL ATAPI_READ_CAPACITY_DATA +; ; +; LD HL,#FFFF +; LD C,BIOS.Error.ATAPI.MediumError +; JR C,.No_Media +; ; +; LD HL,(SYS_PAGE.TMP_BUFFER) ; media size high +; LD (IY+IDE.HDD_INIT_TABLE.MediaSizeHigh),H +; LD (IY+IDE.HDD_INIT_TABLE.MediaSizeHigh+1),L +; LD HL,(SYS_PAGE.TMP_BUFFER + 2) ; media size low +; LD (IY+IDE.HDD_INIT_TABLE.MediaSizeLow),H +; LD (IY+IDE.HDD_INIT_TABLE.MediaSizeLow+1),L +; LD HL,(SYS_PAGE.TMP_BUFFER + 6) ; sector size +; ; +; LD C,BIOS.Error.ATAPI.UnitAttention +; .No_Media: LD (IY+IDE.HDD_INIT_TABLE.SectorSize),H ;[ ] sector size +; LD (IY+IDE.HDD_INIT_TABLE.SectorSize + 1),L +; JR NC,.exit +; SET 2,(IY + IDE.HDD_INIT_TABLE.MediaParameters) + ; +.exit: POP AF + POP HL + POP IX + OUT (SLOT3),A + LD A,C + SCF + RET + ; +.Not_Ready: LD A,(SYS_PAGE.SHARED_BUFFER_256b + 12) ; AdditionalSenceKey + LD C,BIOS.Error.ATAPI.MediumError ; нет носителя + ;!TODO + ; 06,00 - NO REFERENCE POSITION FOUND (media may be upside down) + ; 3A - MEDIUM NOT PRESENT + ; + CP 4 + JR NZ,.exit + ; [ ] !(test for ZIP) + LD A,(SYS_PAGE.SHARED_BUFFER_256b + 13) ; AdditionalSenseCodeQualifier + CP 1 ; LOGICAL DRIVE NOT READY - IN PROGRESS OF BECOMING READY + JR NZ,.exit + ; + ; идёт инициализация + LD C,BIOS.Error.ATAPI.NotReady + JR .exit + ; +.unkn_error: LD C,BIOS.Error.ATAPI.MediumError + JR .exit + + +;----------------------------------------------------------------------; +GET_ATAPI_CAPACITY: + ; + LD DE,SYS_PAGE.TMP_BUFFER + CALL ATAPI_READ_CAPACITY_DATA + ; + LD HL,#FFFF + LD C,BIOS.Error.ATAPI.MediumError + JR C,.No_Media + ; + LD HL,(SYS_PAGE.TMP_BUFFER) ; media size high + LD (IY+IDE.HDD_INIT_TABLE.MediaSizeHigh),H + LD (IY+IDE.HDD_INIT_TABLE.MediaSizeHigh+1),L + LD HL,(SYS_PAGE.TMP_BUFFER + 2) ; media size low + LD (IY+IDE.HDD_INIT_TABLE.MediaSizeLow),H + LD (IY+IDE.HDD_INIT_TABLE.MediaSizeLow+1),L + LD HL,(SYS_PAGE.TMP_BUFFER + 6) ; sector size + ; + LD C,BIOS.Error.ATAPI.UnitAttention +.No_Media: LD (IY+IDE.HDD_INIT_TABLE.SectorSize),H ;[ ] sector size + LD (IY+IDE.HDD_INIT_TABLE.SectorSize + 1),L + RET NC + SET 2,(IY + IDE.HDD_INIT_TABLE.MediaParameters) + RET +;----------------------------------------------------------------------; + +;----------------------------------------------------------------------; + +; !!! SELECT_DRIVE должен отработать заранее +EXEC_TEST_CMD: LD HL,ATAPI_CMD_PACKET.TEST_UNIT_READY + LD DE,0 ; маркер того, что не нужно читать с устройства в ОЗУ + JP EXEC_PACKET_COMMAND.start + +//////////////////////////////////////////////////////////////////////// +ATAPI_CMD_PACKET: +.TEST_UNIT_READY: DUP 12 + DB #00 + EDUP +; +.OPEN: DB #1B + DB #00,#00,#00 + DB #02 + DB #00,#00,#00,#00,#00,#00,#00 +; +.CLOSE: DB #1B + DB #00,#00,#00 + DB #03 + DB #00,#00,#00,#00,#00,#00,#00 +; +.READ: DB #28,#00 + DB #00,#00,#00,#00 ; sector dword + DB #00 + DB #00,#01,#00,#00 ; counter dword + DB #00 +; +.WRITE: DB #2E,#00 ; write and verify + ;DB #2A,#00 ; write + DB #00,#00,#00,#00 ; sector dword + DB #00 + DB #00,#01,#00,#00 ; counter dword + DB #00 +; +.READ_CAPACITY_DATA: DB #25 + BLOCK 11,0 +; +.REQUEST_SENSE: DB #03 + DB #00,#00,#00 + DB MAX_DATA_PACKET_FOR_REQUEST_SENSE + DB #00,#00,#00,#00,#00,#00,#00 +; + +ATAPI_PACKET: +.SECTOR EQU 2 +.COUNTER EQU 7 +//////////////////////////////////////////////////////////////////////// +; +; E - Second * 10 +; PAUSE LD HL,#0000 +; PAUSE1 DEC L +; JR NZ,PAUSE1 +; DEC H +; JR NZ,PAUSE1 +; DEC E +; JR NZ,PAUSE1 +; RET +; +/* +Если ловится ошибка media changed, то биос должен выставлять в HDD_INIT_TABLE.MediaParameters = 3 +и затирать FF SectorSize. +Дос после получения такой ошибки должен вызывать BIOS.DRV_DETECT и если всё ОК, то ReScanDRV +*/ \ No newline at end of file diff --git a/src/bios/exp/EXTENDED/IDE/ATA_DRV.ASM b/src/bios/exp/EXTENDED/IDE/ATA_DRV.ASM new file mode 100644 index 0000000..b1e6dd5 --- /dev/null +++ b/src/bios/exp/EXTENDED/IDE/ATA_DRV.ASM @@ -0,0 +1,735 @@ + +;======================================================== +;R03 !25.07.2001! BUG FIX WITH RETURN ERROR CODE +;R02 !24.07.2001! ADD SECONDARY CHANEL +;R01 !16.08.2000! REMOVED "DI" + +/* +;Write +IDE.Write.Command EQU #4153 ; #1F7 Command +IDE.Write.DeviceHead EQU #4152 ; #1F6 Drive Control + +HDW_CLH EQU #0155 ; #1F5 Cylinder High +HDW_CLL EQU #0154 ; #1F4 Cylinder Low +HDW_SEC EQU #0153 ; #1F3 Sector +HDW_CNT EQU #0152 ; #1F2 Counter +HDW_ERR EQU #0151 ; #1F1 Error +HDW_DAT EQU #0150 ; #1F0 Data + +;Read +IDE.Read.Status EQU #4053 ; #1F7 Status (Control) +HDR_DRV EQU #4052 ; #1F6 Drive Control + +HDR_CLH EQU #0055 ; #1F5 Cylinder High +HDR_CLL EQU #0054 ; #1F4 Cylinder Low +HDR_SEC EQU #0053 ; #1F3 Sector +HDR_CNT EQU #0052 ; #1F2 Counter +HDR_ERR EQU #0051 ; #1F1 Error +HDR_DAT EQU #0050 ; #1F0 Data + +;Bits for IDE.Read.Status +;---[] +BSY EQU 7 +RDY EQU 6 +DRQ EQU 3 +ERR EQU 0 +;---[] + +HDD EQU 1 +CDROM EQU 2 + + +;EQU FOR IY+ +IDE.HDD_INIT_TABLE.DRV_Flags EQU 0 +IDE.HDD_INIT_TABLE.SectorsPerTrack EQU 1 +IDE.HDD_INIT_TABLE.HeadsNumber EQU 2 +IDE.HDD_INIT_TABLE.CylinderNumberLow EQU 3 +IDE.HDD_INIT_TABLE.CylinderNumberHigh EQU 4 +IDE.HDD_INIT_TABLE.SectorsPerCylinderLow EQU 5 +IDE.HDD_INIT_TABLE.SectorsPerCylinderHigh EQU 6 +DTYPE_H EQU 7 + +IDE0 EQU #C1C0 +IDE1 EQU #C1C8 +IDE2 EQU #C1D0 +IDE3 EQU #C1D8 +*/ + +;IDE0 DB #FF ;DRIVE/HEAD REGISTER ;00 +; DB #FF ;SECTORS PER TRACK ;01 +; DB #FF ;HEADS ;02 +; DB #FF ;CYLINDERS LOW ;03 +; DB #FF ;CYLINDERS HIGH ;04 +; DB #FF ;SECTOR PER CYLINDER LOW ;05 +; DB #FF ;SECTOR PER CYLINDER HIGH ;06 +; DB #FF ;RESERVED ;07 + +;IDE1 DB #FF ;DRIVE/HEAD REGISTER ;00 +; DB #FF ;SECTORS PER TRACK ;01 +; DB #FF ;HEADS ;02 +; DB #FF ;CYLINDERS LOW ;03 +; DB #FF ;CYLINDERS HIGH ;04 +; DB #FF ;SECTOR PER CYLINDER LOW ;05 +; DB #FF ;SECTOR PER CYLINDER HIGH ;06 +; DB #FF ;RESERVED ;07 + + +WRITE_OUTI_DUPs EQU 32 ; bytes + +;[]================================================================[#51] +;Function: Reset drive +ATA_5x_RESET: ; !FIXIT не ресетится? +;For non-ATAPI drives, the only method a driver has of resetting a drive +; after a major error is to do a "software reset" on the bus. +; Set bit 2 (SRST, value = 4) in the proper Control Register for the +; bus. This will reset both ATA devices on the bus. Then, you have to +; clear that bit again, yourself. The master drive on the bus is +; automatically selected. + XOR A + RET +;[]================================================================[#51] + + +;[]================================================================[#58] +;Function: Get Current Media Parameters +; A - Disk +;Return: +; H - Heads +; L - Sectors per cylinder +; DE - Cylinders +; IX - Capacity sector in bytes +; B - Flags: MASTER/SLAVE, LBA/CHS +ATA_5x_GET_PAR: + LD C,IDE.Device.HDD + CALL SELECT_DRIVE + RET C + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(IY+IDE.HDD_INIT_TABLE.MediaParameters) + LD L,(IY+IDE.HDD_INIT_TABLE.SectorsPerTrack) + LD H,(IY+IDE.HDD_INIT_TABLE.HeadsNumber) + LD E,(IY+IDE.HDD_INIT_TABLE.CylinderNumberLow) + LD D,(IY+IDE.HDD_INIT_TABLE.CylinderNumberHigh) + LD B,(IY+IDE.HDD_INIT_TABLE.DRV_Flags) + LD IX,512 ;!HARDCODE ; [ ] sector size + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + AND A + RET +;[]================================================================[#58] + +;[]================================================================[#59] +;Function: Set Current Media Parameters +; A - Disk +; H - Heads +; L - Sectors +; DE - Cylinders +; IX - Capacity sector in bytes +; B - Flags +;Return: None +ATA_5x_SET_PAR: + LD C,IDE.Device.HDD + CALL SELECT_DRIVE + RET C + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD (IY+IDE.HDD_INIT_TABLE.SectorsPerTrack),L + LD (IY+IDE.HDD_INIT_TABLE.HeadsNumber),H + LD (IY+IDE.HDD_INIT_TABLE.CylinderNumberLow),E + LD (IY+IDE.HDD_INIT_TABLE.CylinderNumberHigh),D + LD (IY+IDE.HDD_INIT_TABLE.DRV_Flags),B + ;!TODO ; [ ] sector size + ;!TODO ; [ ] UnitAttention + EX AF,AF' + OUT (SLOT3),A + ;EX AF,AF' + ;AND A + RET +;[]================================================================[#59] + +;[]================================================================[#55] +;Function: Read Sectors +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter +;Return: +; HL:IX - Sector + Sector counter +; DE - Address + (Sector counter * Size sector) +;READ SECTOR(S) +ATA_5x_READ: ;PUSH IY ; !FIXIT зачем? + LD C,0 ; признак short + EX AF,AF' + IN A,(SLOT3) + EX AF,AF' + JP ATA_5x_LONG_READ.main +;[]================================================================[#52] +;Function: Long Read Sectors +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter, 0 = 256 +; A'- Memory Page Number +;Return: +; HL:IX - Sector + Sector counter +; DE - Address + (Sector counter * Size sector) +; A' - Last mem page in RAM Block used for readed data +;LONG READ SECTOR(S) +ATA_5x_LONG_READ: + ;PUSH IY ; !FIXIT зачем? + LD C,1 ; признак long +.main: SAFE_PORTY_2 + PUSH BC + PUSH IX + PUSH HL + ; + EX AF,AF' + AND A ;read + EX AF,AF' + CALL RW_ATA_SECTORs + ; +.shared: EX DE,HL + JR C,.error + LD A,XH ; current page in mem block for SLOT3 + EX AF,AF' + ; + POP HL + POP IX + POP BC + ; HL:IX + B. если B=0, то B=256 + XOR A + CP B + LD C,B + CCF + RLA + LD B,A + ADD IX,BC + JR NC,.exit + INC HL + CCF + ; +.exit: RESTORE_PORTY + ;POP IY + RET + ; +.error: LD B,A ; A - номер ошибки + LD C,XL + LD A,XH ; current page in mem block for SLOT3 + EX AF,AF' + POP HL + POP IX + PUSH BC + LD B,0 + ADD IX,BC + ; + ;LD C,B + ;ADC HL,BC + JR NC,.no_inc_hl + INC HL +.no_inc_hl: ; + POP BC + POP AF + SUB C + LD C,A + LD A,B + LD B,C + SCF ;R03 + JR .exit +;[]===========================================================[#52, #55] + + +;[]================================================================[#56] +;Function: Write Sectors +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter +;Return: +; HL:IX - Sector + Sector counter +; DE - Address + (Sector counter * Size sector) +;WRITE SECTOR(S) +ATA_5x_WRITE: ;PUSH IY ; !FIXIT зачем? + LD C,0 ; признак short + EX AF,AF' + IN A,(SLOT3) + EX AF,AF' + JP ATA_5x_LONG_WRITE.main +;[]================================================================[#53] +;Function: Long Write Sectors +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter +; A'- Memory Page Number +;Return: +; HL:IX - Sector + Sector counter +; DE - Address + (Sector counter * Size sector) +;WRITE SECTOR(S) +ATA_5x_LONG_WRITE: + ;PUSH IY ; !FIXIT зачем? + LD C,1 ; признак long +.main: SAFE_PORTY_2 + PUSH BC + PUSH IX + PUSH HL + ; + EX AF,AF' + SCF ;write + EX AF,AF' + CALL RW_ATA_SECTORs + ; + JP ATA_5x_LONG_READ.shared + +;███████████████████████████████████████████████████████████████████████████████████████████████████████; +; !TODO поддержка 8-bit data transfer mode для древних винтов +; A - Disk +; HL:IX - Sector +; DE - Address +; B - Sector counter +; C - short/long +; A'- Memory Page Number +; CF'=1 - write, CF'=0 - read +RW_ATA_SECTORs: PUSH BC ; признак short/long в C + LD C,IDE.Device.HDD + CALL SELECT_DRIVE + POP BC ; признак short/long в C + RET C + ; + EXX + LD DE,256*(IDE.CtrlByte.Busy+IDE.CtrlByte.Ready) + IDE.CtrlByte.Ready + CALL WAITPRT.custom + EXX + RET C + ; + EX AF,AF' + PUSH AF ; memory page number + PUSH BC ; признак short/long в C + PUSH DE ; Address + CALL PRESET + ; IY из SELECT_DRIVE больше не нужен + ; + POP HL ; Address + POP IY ; признак short/long в YL + POP AF ; memory page number + LD XL,0 + LD XH,A ; memory page number + LD BC,IDE.Write.Command + LD A,IDE.CMD.ATA.WriteSectorsWithRetry + JR C,.set_command ; CF = r/w + ; + LD A,IDE.CMD.ATA.ReadSectorsWithRetry +.set_command: OUT (C),A + EX AF,AF' + EXX + LD DE,256*(IDE.CtrlByte.Busy+IDE.CtrlByte.DataRequest+IDE.CtrlByte.Error)+IDE.CtrlByte.DataRequest + CALL WAITPRT.custom + EXX + RET C + ;DI ;R01 REMOVED "DI" +.big_loop: IN A,(SLOT3) + EX AF,AF' ;>-----------> \ + LD A,XH + OUT (SLOT3),A + LD BC,IDE.Read.Data + JR C,.write_sector + ; + ; READ SECTOR 512 bytes ;!HARDCODE sector size +.loop_256_1: DUP 16 + INI + EDUP + JP NZ,.loop_256_1 +.loop_256_2: DUP 16 + INI + EDUP + JP NZ,.loop_256_2 + AND A + ;EX AF,AF' + ; ; ; ; ; + ; CF=0 +.return_rw: EX AF,AF' ;<-----------< / + INC XL ;INC LOADED SECTORS + OUT (SLOT3),A + ; + LD A,H + OR L + JR NZ,.end_pass + ; short/long + ; A = 0 + SUB YL + JR NC,.END_BUFFER + ; next page in mem block + CALL CHANGE_MEM_BLK + ; LD HL,#C000 + ; IN A,(SLOT3) + ; EX AF,AF' ;>-----------> \ + ; LD A,SYS_PAGE + ; OUT (SLOT3),A + ; LD D,high SYS_PAGE.RAM_TABLE + ; LD E,XH + ; LD A,(DE) + ; LD XH,A + ; EX AF,AF' ;<-----------< / + ; OUT (SLOT3),A + ; +.end_pass: ;INC XL ;INC LOADED SECTORS + EXX + CALL WAITPRT + EXX + RET C + ; + ;INC XL ;INC LOADED SECTORS + LD BC,IDE.Read.Status + IN A,(C) + BIT IDE.CtrlBit.DataRequest,A + RET Z + ; + JP .big_loop + ; +.write_sector: ; WRITE SECTOR 512 bytes ;!HARDCODE sector size + INC B ; LD BC,IDE.Write.Data + LD D,512/WRITE_OUTI_DUPs ;!HARDCODE sector size +.loop: DUP WRITE_OUTI_DUPs + OUTI + EDUP + DEC D + JR NZ,.loop + SCF + JP .return_rw + ; ; +.END_BUFFER: CALL ATA_IdlePasses.CHECK_DRV + JR NZ,ATA_IdlePasses.Enter + RET +;;;;;;;;;;;;;;;;; +ATA_IdlePasses: CALL .CHECK_DRV + JR NZ,.Enter + ; + RET C + LD A,BIOS.Error.Failure + SCF + RET + ; +.Enter: XOR A ; счётчик для READ_ZEROS, данные для .WrZeros + EX AF,AF' + LD BC,IDE.Read.Data + JR C,.WrZeros + ; READ > /dev/null + EX AF,AF' +.RdLoop: IN F,(C) ; читаем по 1 разу с чётного адреса, читается WORD + DEC A + JR NZ,.RdLoop + JR ATA_IdlePasses + ; WRITE ZEROS +.WrZeros: EX AF,AF' + ; +.WrLoop: OUT (C),A + DJNZ .WrLoop + ; +.WrLoop2: OUT (C),A + DJNZ .WrLoop2 + JR ATA_IdlePasses + ; +.CHECK_DRV: EXX + CALL WAITPRT + EXX + RET C + ; + LD BC,IDE.Read.Status + IN A,(C) + BIT IDE.CtrlBit.DataRequest,A + RET +;!TODO доделать эту же хурму для других устройств +;███████████████████████████████████████████████████████████████████████████████████████████████████████; +/* + IFN OPTIMIZE_RW_PROCEDURE +WRITE_ATA_SECTORs: + LD C,IDE.Device.HDD + CALL SELECT_DRIVE + RET C + EXX + ;LD DE,#C140 ;WAIT BUSY=0 & READY=1 & ERR=0 + CALL WAITPRT + EXX + RET C + EX AF,AF' + PUSH AF + PUSH DE + CALL PRESET + POP HL + POP AF + LD XL,0 + LD XH,A + LD BC,IDE.Write.Command + LD A,IDE.CMD.ATA.WriteSectorsWithRetry + OUT (C),A + ; SAVE HL?! + EXX + LD DE,#8908 ;WAIT BUSY=0 & DRQ=1 & ERR=0 + CALL WAITPRT.custom + EXX + RET C + ; +.big_loop: IN A,(SLOT3) + EX AF,AF' + LD A,XH + OUT (SLOT3),A + ; WRITE SECTOR 512 bytes ;!HARDCODE sector size + LD BC,IDE.Write.Data + LD D,512/WRITE_OUTI_DUPs ;!HARDCODE sector size +.loop: DUP WRITE_OUTI_DUPs + OUTI + EDUP + DEC D + JR NZ,.loop + ; ; ; ; ; + EX AF,AF' + OUT (SLOT3),A + ;EI + ; + LD A,H + OR L + JR NZ,.W33 + ; next page in mem block + LD HL,#C000 + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD D,high SYS_PAGE.RAM_TABLE + LD E,XH + LD A,(DE) + LD XH,A + EX AF,AF' + OUT (SLOT3),A + ; +.W33: INC XL ;INC SAVED SECTORS + EXX + ;LD DE,#C140 ;WAIT BUSY=0 & ERR=0 & READY=1 + CALL WAITPRT + EXX + RET C + LD BC,IDE.Read.Status + IN A,(C) + BIT IDE.CtrlBit.DataRequest,A + ; + RET Z + JP .big_loop + ;JP NZ,.big_loop + ;XOR A + ;RET + ; + ENDIF +*/ +;[]===========================================================[#53, #56] + + +;[]================================================================[#54] +;Function: Verify Sectors +; A - Disk +; HL:IX - Sector +; B - Sector counter +;Return: CF - error +;VERIFY SECTOR(S) +ATA_5x_VERIFY: ;PUSH IY ; !FIXIT зачем? + SAFE_PORTY_2 + PUSH IX + PUSH HL + CALL .VERIFY + POP HL + POP IX + RESTORE_PORTY + ;POP IY + RET +;VERIFY SECTOR(S) +.VERIFY: LD C,IDE.Device.HDD + CALL SELECT_DRIVE + RET C + EXX + LD DE,256*(IDE.CtrlByte.Busy+IDE.CtrlByte.Ready) + IDE.CtrlByte.Ready + CALL WAITPRT.custom + EXX + RET C + ;PUSH DE + ; IN A,(SLOT3) + ; PUSH AF + CALL PRESET + ; POP AF + ; OUT (SLOT3),A + ;POP HL + LD BC,IDE.Write.Command + LD A,IDE.CMD.ATA.ReadVerifySectorsWithRetry + OUT (C),A + LD BC,IDE.Read.Status + IN A,(C) + RRA ;BIT IDE.CtrlBit.Error,A : SCF : RET NZ + RET C + ; + JP WAITPRT + ;RET C + ;XOR A + ;RET +;[]================================================================[#54] + + +; HL:IX - LBA SECTOR +; B - SECTOR COUNTER +; выход: SLOT3 = SYS_PAGE +PRESET: LD A,B + LD BC,IDE.Write.Counter + OUT (C),A + ; + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(IY+IDE.HDD_INIT_TABLE.DRV_Flags) + LD BC,IDE.Write.DeviceHead + OUT (C),A + ;бит CHS/LBA ;!FIXIT сделать метками номера бит + AND %0100'0000 + LD E,XL + LD D,XH + CALL Z,LBA_CHS + LD BC,IDE.Write.Sector + OUT (C),E ;LBA 0..7 + ; + INC C ; LD BC,IDE.Write.CylinderLow + OUT (C),D ;LBA 8..15 + INC C ; LD BC,IDE.Write.CylinderHigh + OUT (C),L ;LBA 16..23 + LD BC,IDE.Read.Control + IN A,(C) + AND #F0 ;!HARDCODE DRIVE/HEAD REGISTER PHISICAL DISK bitmask + OR H ;LBA 24..27 + INC B ; LD BC,IDE.Write.DeviceHead + ; + OUT (C),A + EX AF,AF' + OUT (SLOT3),A + ;AND A + RET +;PRESET ; + + +; HL:DE - SECTOR OFFSET +LBA_CHS: LD C,(IY+IDE.HDD_INIT_TABLE.SectorsPerCylinderLow) + LD B,(IY+IDE.HDD_INIT_TABLE.SectorsPerCylinderHigh) + ; +DIV32X: ;HL:DE / BC => DE:IX HL-OSTATOK + LD XH,D + LD XL,E + EX DE,HL + LD HL,0 + LD A,#20 + ; +.loop: ADD IX,IX + EX DE,HL + ADC HL,HL + EX DE,HL + ADC HL,HL + SBC HL,BC + JR NC,.DIV012 + ; + ADD HL,BC + DEC A + JR NZ,.loop + ; + JR .DIV014 + ; +.DIV012: INC IX + DEC A + JR NZ,.loop + ; +.DIV014: LD E,(IY+IDE.HDD_INIT_TABLE.SectorsPerTrack) + LD D,0 + XOR A + ; +.loop2: INC A + SBC HL,DE + JR NC,.loop2 + ; + ADD HL,DE + DEC A + LD H,A + LD E,L + INC E + LD D,XL + LD A,XH + LD L,A + RET + +;----------------------------------------------------------------------; +; D - MASK +; E - PATTERN +; !!! некоторые функции надеются, что на выходе всегда ZF +WAITPRT: LD DE,256*(IDE.CtrlByte.Busy+IDE.CtrlByte.Ready+IDE.CtrlByte.Error) + IDE.CtrlByte.Ready +.custom: LD BC,IDE.Read.Status + LD HL,#0000 ; задержка ;!HARDCODE + ; +.loop: PUSH HL +; +.loop2: IN A,(C) + AND D + CP E + JR Z,.ok + DEC HL + LD A,L + OR H + JP NZ,.loop2 + ; + POP HL + DEC L + JR NZ,.loop + ; +.error: LD A,BIOS.Error.NotReady + SCF + RET + ; +.ok: POP HL + RET +;----------------------------------------------------------------------; + + +;[]================================================================[#57] +;[x] 18/12/2023. добавление/допиливание API CD-ROM (ATAPI) +; [ ] media change +;Function: Detect Disk +; A - Disk +;Return: CF=0 - A=Drive type +; CF=1 - error +ATA_5x_DETECT: LD C,IDE.Device.HDD +.shared: CALL SELECT_DRIVE + RET C + ; + LD B,A + AND %0000'0011 ;[ ] media change переделать логику тут и в ДСС? ; !FIXIT + JR NZ,.notZero + LD A,C + RET + ; +.notZero: AND %0000'0010 + JR NZ,.UnitAttention + ; C = DriveType + LD A,C + CP IDE.Device.ATAPI + JR Z,.AtapiCheckMedia + ;!FIXIT AtaCheckMedia - не сделано ; [ ] media change + AND A + RET + ; +.AtapiCheckMedia: + PUSH BC ; B - MediaParameters, C - DriveType + CALL ATAPI_CHECK_MEDIA_CHANGED + POP BC ; B - MediaParameters, C - DriveType + RET C + LD A,C + RET + ; +.UnitAttention: LD A,BIOS.Error.ATAPI.UnitAttention + SCF + RET +;[]================================================================[#57] \ No newline at end of file diff --git a/src/bios/exp/EXTENDED/IDE/shared.asm b/src/bios/exp/EXTENDED/IDE/shared.asm new file mode 100644 index 0000000..160ec71 --- /dev/null +++ b/src/bios/exp/EXTENDED/IDE/shared.asm @@ -0,0 +1,123 @@ +;[x] 18/12/2023. добавление/допиливание API CD-ROM (ATAPI) +;======================================================================= +; Вход: A - номер устройства, C - DriveType +; Выход: A - MediaParameters, C - DriveType +; не портит L +SELECT_DRIVE: AND #0F + LD IY,IDE.INIT_TBL_IDE0 + JR Z,.channel + DEC A + LD IY,IDE.INIT_TBL_IDE1 + ;R02 + JR Z,.channel + DEC A + LD IY,IDE.INIT_TBL_IDE2 + JR Z,.channel + DEC A + LD IY,IDE.INIT_TBL_IDE3 + ; + JR NZ,.error + ; +.channel: EXX + IN A,(SLOT3) + PUSH AF + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD H,(IY + IDE.HDD_INIT_TABLE.MediaParameters) + LD C,(IY + IDE.HDD_INIT_TABLE.DriveType) + LD B,(IY + IDE.HDD_INIT_TABLE.DRV_Flags) + POP AF + OUT (SLOT3),A ;возврат страницы + ; + LD A,C + EXX + ; + CP C + ; + EXX + SCF + LD A,BIOS.Error.BadNumber + RET NZ + ; + LD A,B + RRA + LD A,IDE.Chanel.Secondary + JR C,.device + LD A,IDE.Chanel.Primary +.device: OUT (IDE.Chanel.Set),A ;R02 + LD A,B + AND #F0 + LD BC,IDE.Write.DeviceHead + OUT (C),A + ; +.del_me: LD A,high IDE.Read.Status + IN A,(low IDE.Read.Status) + AND IDE.CtrlByte.Busy + ; тестирование задержек + ;JR NZ,.del_me + JR Z,.notBusy + LD B,32 + DJNZ $ + ; +.notBusy: LD A,H + EXX + RET + ; +.error: LD A,BIOS.Error.BadNumber + SCF + RET +;======================================================================= + + +;======================================================================= +; next page in mem block +CHANGE_MEM_BLK: LD HL,#C000 + IN A,(SLOT3) + EX AF,AF' ;>-----------> \ + LD A,SYS_PAGE + OUT (SLOT3),A + LD D,high SYS_PAGE.RAM_TABLE + LD E,XH + LD A,(DE) + LD XH,A + EX AF,AF' ;<-----------< / + OUT (SLOT3),A + RET +;======================================================================= + + +;======================================================================= +;Function: Detect Disk +; A - Disk +; С - Type +;Return: CF=0 - A=Drive type, H=MediaParameters +; CF=1 - drive not present, A=#02 +;DRV_DETECT: CP #84 ;!HARDCODE max IDE drives (#80,#81,#82,#83) +; CCF +; JR C,.error +; ; +; LD IX,IDE.INIT_TBL_IDE0 +; AND 3 +; JR Z,.get_param +; LD IX,IDE.INIT_TBL_IDE1 +; DEC A +; JR Z,.get_param +; LD IX,IDE.INIT_TBL_IDE2 +; DEC A +; JR Z,.get_param +; LD IX,IDE.INIT_TBL_IDE3 +; .get_param: IN A,(SLOT3) +; LD B,A +; LD A,SYS_PAGE +; OUT (SLOT3),A +; ; +; LD H,(IX + IDE.HDD_INIT_TABLE.MediaParameters) +; LD A,(IX + IDE.HDD_INIT_TABLE.DriveType) +; CP C ; compare Type +; LD C,SLOT3 +; OUT (C),B +; RET Z +; SCF +; .error: LD A,BIOS.Error.BadNumber +; RET \ No newline at end of file diff --git a/src/bios/exp/EXTENDED/RAM_DISK_DRIVER_1.asm b/src/bios/exp/EXTENDED/RAM_DISK_DRIVER_1.asm index c61d1e7..9b91bbf 100644 --- a/src/bios/exp/EXTENDED/RAM_DISK_DRIVER_1.asm +++ b/src/bios/exp/EXTENDED/RAM_DISK_DRIVER_1.asm @@ -12,7 +12,7 @@ ;Return: None ;[]===========================================================[] ;!FIXIT -RMD_5x.SETMED: +RMD_5x_SET_PAR: and a ret ; A - Disk @@ -35,51 +35,52 @@ RMD_5x.SETMED: ; IX - Capacity sector in bytes ; B - Flags: ramblock ID ;[]===========================================================[] -RMD_5x.GETMED: -.SectorSize EQU 512 ;!HARDCODE - AND #0F - CALL GET_RAMD_ST ; получение идентификатора блока - RET C - SCF - RET Z - - - LD C,A - LD B,#FF -.loop: INC B - PUSH BC - LD A,C - CALL EMM.GetMemPage ; получить физический номер страницы из блока - POP BC - JR NC,.loop - CP #FF - RET NZ - LD E,B - LD B,C - -; тут в E количество страниц в рамдиске, B - ID рамдиска - LD HL,1*256 + #4000/.SectorSize - LD D,0 - LD IX,.SectorSize - - RET +RMD_5x_GET_PAR: AND #0F + CALL GET_RAMD_ST ; получение идентификатора блока + RET C + SCF + RET Z + ; + LD C,A + LD B,#FF +.loop: INC B + PUSH BC + LD A,C + CALL EMM.GetMemPage ; получить физический номер страницы из блока + POP BC + JR NC,.loop + ; CF==1, A==0 - ошибка, A==#FF - ok + INC A + RET NZ ; если выходит, то с флагами CF==1, ZF==1 + ; + LD E,B + LD B,C + ; тут в E количество страниц в рамдиске, B - ID рамдиска + LD HL,1*256 + #4000/.SectorSize + LD D,0 + LD IX,.SectorSize + XOR A + INC A ; removable media. CF=0, LD A,1 + RET + ; +.SectorSize EQU 512 ;!HARDCODE //////////////////////////////////////////////////////////////////////////////////// -RMD_5x.LONG_WRITE: +RMD_5x_LONG_WRITE: LD C,#FF JP RAM_DRV_READ_WRITE -RMD_5x.LONG_READ: +RMD_5x_LONG_READ: LD C,0 JP RAM_DRV_READ_WRITE -RMD_5x.WRITE: +RMD_5x_WRITE: LD C,#FF JP RAM_DRV_NO_LONG -RMD_5x.READ: +RMD_5x_READ: LD C,0 ;JP RAM_DRV_NO_LONG RAM_DRV_NO_LONG: EX AF,AF' - IN A,(SLOT3) + IN A,(SLOT3) EX AF,AF' ; НА входе рег С = 0 если чтение, либо #FF, если запись RAM_DRV_READ_WRITE: @@ -115,7 +116,7 @@ RAM_DRV_READ_WRITE: AND #0F ;номер рамдиска ;LD C,BIOS.GET_RAMD_ST - ;RST ToBIOS_18 + ;RST_to_BIOS CALL GET_RAMD_ST ; A = Memory Block ID @@ -136,7 +137,7 @@ RAM_DRV_READ_WRITE: PUSH DE //PUSH BC ;LD C,BIOS.BLK_RD_WR - ;RST ToBIOS_18 + ;RST_to_BIOS CALL BLK_RD_WR JR C,.error_stack3 ; hl = address + Sector_low * 256 * Sector_counter diff --git a/src/bios/exp/FLEX.asm b/src/bios/exp/FLEX.asm deleted file mode 100644 index 4950cc8..0000000 --- a/src/bios/exp/FLEX.asm +++ /dev/null @@ -1,822 +0,0 @@ - -SYCLES EQU 0 -;START EQU 1 -ST1 EQU 2 -DPAL1 EQU 3 -ST2 EQU 4 -DPAL2 EQU 5 - - MACRO NEXT_LIN_H - EX AF,AF' - INC A - OUT (RGADR),A - EX AF,AF' - ENDM - - MACRO NEXT_LIN_HP - EX AF,AF' - INC A - OUT (RGADR),A - JR NZ,.MD_NO_INC_H - inc l -.MD_NO_INC_H: - EX AF,AF' - ENDM - - -;***************************************** -; -; Инициализация страниц для -; спектрумовского режима и -; восстановление спектрумовского -; экрана -; -; Возврат по IX -; -; !!! NO USE STACK !!! -; -;***************************************** -; инициализация страниц zx spectrum -INIT_PAGES: - AND A - LD E,A - EX AF,AF' - LD A,E - -; BIT 7,A -; JR Z,SCORPION_256_MODE -; BIT 6,A -; JR Z,PENTAGON_128_MODE -; -;PENTAGON_48_MODE: -; AND 03CH -; OUT (SLOT0),A -; INC A -; OUT (SLOT1),A -; INC A -; OUT (SLOT2),A -; INC A -; LD D,A -; LD BC,1FFDH -; XOR A -; OUT (C),A -; LD B,7FH -; OUT (C),A -; LD A,D -; OUT (SLOT3),A -; JR INIT_VIDEO_REG -; -; -; PENTAGON_128_MODE: -; LD D,8 -; AND #38 -; JR ALL_MODE - -SCORPION_256_MODE: - LD D,16 - AND #30 ; до 4-х спектрумов - -ALL_MODE: - OUT (SLOT0),A - XOR 5 - OUT (SLOT1),A - XOR 7 - OUT (SLOT2),A - OR #0F - LD E,A - -.loop: DEC D - - LD A,D - RLCA - AND #10 - LD BC,#1FFD - OUT (C),A - - LD A,D - AND 7 - OR #40 - LD B,#7F - OUT (C),A - - LD A,E - OUT (SLOT3),A - DEC E - - DEC D - INC D - JR NZ,.loop - -INIT_VIDEO_REG: - XOR A - OUT (RGADR),A ; регистр видео адреса -; OUT (RGSCR),A ; регистр экрана - OUT (RGMOD),A ; регистр моды - - ;!TEST - ; Restore old Spectrum Screen - ;; LD HL,#4000 - ;; LD DE,#4000 - ;; LD BC,#1B00 - ;; LDIR - - ; EX AF,AF' - ; BIT 6,A - ; JR NZ,NO_SCREEN_ALT - - ; EX AF,AF' - - ; LD A,7 ; седьмая экранная страница - ; LD BC,#7FFD - ; OUT (C),A - - ; Restore old Spectrum Screen 2 - ;; LD HL,#C000 - ;; LD DE,#C000 - ;; LD BC,#1B00 - ;; LDIR - - ; XOR A - ; LD BC,#7FFD - ; OUT (C),A - ; - - EX AF,AF' -NO_SCREEN_ALT: - AND A - JP (IX) - -;**************************************** -; Загрузка режима экрана. -;**************************************** - -; CALL SINC_DEF -; CALL SET_PAL_ZX -; RET - -;**************************************** - -;!TODO тут функция -CL0 EQU 200 -CL1 EQU 240 - -SET_PAL_IBM: - LD DE,#8000 - JR SET_PAL_ -SET_PAL_ZX: - LD DE,0 -SET_PAL_: - PUSH IX - IN A,(RGADR) - PUSH AF - IN A,(SLOT3) - EX AF,AF' - LD A,#50 - OUT (SLOT3),A - - LD IX,#C3F0 ; !HARDCODE адрес палитры? -SET_PAL_ZX1: - CALL GENERATE_PAL1 - LD A,E - OUT (RGADR),A - LD (IX),L - LD (IX+1),B - LD (IX+2),C - LD (IX+3),H - INC E - JR NZ,SET_PAL_ZX1 - LD BC,4 - ADD IX,BC - INC D - LD A,D - AND 3 - JR NZ,SET_PAL_ZX1 - - EX AF,AF' - OUT (SLOT3),A - POP AF - OUT (RGADR),A - POP IX - RET - -; генерация спектрумовской палитры. -; E - атрибут, D - номер PAL -; ВЫХОД - C - BLUE, L - RED, B - GREEN, H - INTENSITY -GENERATE_PAL1: - XOR A - LD C,A - LD B,A - LD L,A - - BIT 7,D - JR NZ,GENERATE_IBM - - BIT 1,D - JR NZ,GEM_PAL_FLH ;!FIXIT походу никогда не вызывается -GEM_PAL_NOF: - BIT 0,D - JR Z,GEN_PAL_PAP - -GEN_PAL_INK: - LD A,CL0 - BIT 6,E - JR Z,GEN_PAL_NOI1 - LD A,CL1 -GEN_PAL_NOI1: - BIT 0,E ; BLUE - JR Z,GEN_PP_NO1 - LD C,A -GEN_PP_NO1: - BIT 1,E ; RED - JR Z,GEN_PP_NO2 - LD L,A -GEN_PP_NO2: - BIT 2,E ; GREEN - JR Z,GEN_PP_NO3 - LD B,A -GEN_PP_NO3: - JR GEN_PP_NO6 -; -; -GEM_PAL_FLH: - BIT 7,E - JR Z,GEM_PAL_NOF - BIT 0,D - JR Z,GEN_PAL_INK - -GEN_PAL_PAP: - LD A,CL0 - BIT 6,E - JR Z,GEN_PAL_NOI2 - LD A,CL1 -GEN_PAL_NOI2: - BIT 3,E ; BLUE - JR Z,GEN_PP_NO4 - LD C,A -GEN_PP_NO4: - BIT 4,E ; RED - JR Z,GEN_PP_NO5 - LD L,A -GEN_PP_NO5: - BIT 5,E ; GREEN - JR Z,GEN_PP_NO6 - LD B,A -GEN_PP_NO6: - - LD A,C - AND A - RRA - ADD A,L - RRA - ADD A,B - RRA - LD H,A ; B/W mode - - RET - -;**************************************** - -GENERATE_IBM: - BIT 7,E - JR Z,GEN_IBM_NO_FLH - BIT 1,D - JR Z,GEN_IBM_PAPER - -GEN_IBM_NO_FLH: - BIT 0,D - JR Z,GEN_IBM_PAPER - -GEN_IBM_INK: - -GEN_NO_INTENS: - LD A,0A8h -GEN_INTENS: - BIT 0,E ; BLUE - JR Z,GEN_PPI_NO4 - LD C,A -GEN_PPI_NO4: - BIT 2,E ; RED - JR Z,GEN_PPI_NO5 - LD L,A -GEN_PPI_NO5: - BIT 1,E ; GREEN - JR Z,GEN_PPI_NO6 - LD B,A -GEN_PPI_NO6: - - LD A,E - AND 0Fh - CP 6 - JR NZ,no_correct - LD B,54h -no_correct: - BIT 3,E - JR Z,GEN_PP_NO6 - - LD A,54h - ADD A,C - LD C,A - LD A,54h - ADD A,B - LD B,A - LD A,54h - ADD A,L - LD L,A - - JR GEN_PP_NO6 - -GEN_IBM_PAPER: - LD A,0A8h - BIT 4,E ; BLUE - JR Z,GEN_PPI_NO4X - LD C,A -GEN_PPI_NO4X: - BIT 6,E ; RED - JR Z,GEN_PPI_NO5X - LD L,A -GEN_PPI_NO5X: - BIT 5,E ; GREEN - JR Z,GEN_PPI_NO6X - LD B,A -GEN_PPI_NO6X: - - LD A,E - AND 070h - CP 60h - JR NZ,no_correct2 - LD B,54h -no_correct2: - JR GEN_PP_NO6 - -;**************************************** -;**************************************** -;**************************************** - -; D - номер графической палитры -SET_PAL_GRAF: - PUSH IX - IN A,(RGADR) - PUSH AF - - IN A,(SLOT3) - EX AF,AF' - LD A,#50 - OUT (SLOT3),A - - - LD IX,0C3E0H - LD A,D - AND 3 - ADD A,A - ADD A,A - LD E,A - LD D,0 - ADD IX,DE - - LD E,0 - - XOR A - LD B,A - LD C,A - LD L,A - LD H,A - -SET_PAL_GR1: - LD A,E - OUT (RGADR),A - - LD (IX),L - LD (IX+1),B - LD (IX+2),C - LD (IX+3),H - - CALL GENERATE_PAL3 - - INC E - LD A,E - CP 40 - JR NZ,SET_PAL_GR1 - - XOR A - LD B,A - LD C,A - LD L,A - LD H,A - -SET_PAL_GR2: - LD A,E - OUT (RGADR),A - - LD (IX),L - LD (IX+1),B - LD (IX+2),C - LD (IX+3),H - - CALL GENERATE_PAL2 - - INC E - JR NZ,SET_PAL_GR2 - - EX AF,AF' - OUT (SLOT3),A - POP AF - OUT (RGADR),A - POP IX - RET -; -;;********************************* -; - -GENERATE_PAL3: ; gray-scale - LD A,B - ADD A,6 - LD B,A - LD C,A - LD L,A - - LD A,C - AND A - RRA - ADD A,L - RRA - ADD A,B - RRA - LD H,A - - RET - -GENERATE_PAL2: ; C - BLUE; L - RED; B - GREEN; H - INTENSITY - LD A,C - ADD A,50 - LD C,A - JR NC,GEN_PAL2_L1 - LD C,0 - LD A,L - ADD A,50 - LD L,A - JR NC,GEN_PAL2_L1 - LD L,0 - LD A,B - ADD A,50 - LD B,A - JR NC,GEN_PAL2_L1 - LD B,0 - -GEN_PAL2_L1: - LD A,C - AND A - RR A - ADD A,L - RR A - ADD A,B - RR A - LD H,A - - RET -; -;;***************************************** - -FN_SYNC: - BIT 7,a - JR Z,.old_mode - - ld h,a - and #60 ; check reserved bits - jr nz,.error - - bit 2,h ; Set V-Sinc? - jr nz,.set_v_sinc - - bit 4,h ; Set Waits? - jr z,.error ; Error - no parameters - -.set_waits: - ld a,h - and 8 ; check waits. Z - no waits, NZ - waits - ld h,#FF - jr z,1F - ld h,#FB -1: - ld bc,(Port_All_Mode) - in a,(C) - and h - out (C),a - RET - -.set_v_sinc: - ld a,h - and 3 - jr z,.SetDefLines - dec a - jr z,.SetCmosLines - dec a - jr z,.Set320Lines -; jr Set312Lines - -.set312lines: - ld a,Port_VSYNC.SET_312L - out (Port_VSYNC),a - - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (C),A - ld a,(SYS_PAGE.VSyncAndWaits) - and 2 - ld (SYS_PAGE.VSyncAndWaits),a - OUT (C),B - -.end_set_v_sinc: - bit 4,h - ret z - jr .set_waits - - -.Set320Lines: - ld a,Port_VSYNC.SET_320L - out (Port_VSYNC),a - - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (C),A - ld a,(SYS_PAGE.VSyncAndWaits) - or 1 - ld (SYS_PAGE.VSyncAndWaits),a - OUT (C),B - - jr .end_set_v_sinc - -.SetCmosLines: - LD D,CMOS.Cell.ScreenSET - CALL CMOS_RD - - AND CMOS.Cell.ScreenSET.Mask.Sinc ; в регистре A значение ScreenSET - jr z,.SetDefLines - - bit 6,a - jr z,.set312lines - - jr .Set320Lines - -.old_mode: - AND A - JR Z,.INT_DEF - DEC A - JR Z,.INT_SCORP - DEC A - JR Z,.INT_PENT - DEC A - JR Z,.INT_ORIG - DEC A - JR Z,.INT_CMOS_SINC -.error: SCF - RET - -.SetDefLines: - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (C),A - ld a,(SYS_PAGE.VSyncAndWaits) - OUT (C),B - and 1 - jr z,.set312lines - jr .Set320Lines - -.INT_DEF: - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (C),A - LD DE,(SYS_PAGE.CONFIG_ALL) - OUT (C),B - - CALL Test_CONFIG_ALL - jr nz,.INT_CMOS_SINC - jp (IX) - -.INT_CMOS_SINC: - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (C),A - LD DE,(SYS_PAGE.CONFIG_ALL) - OUT (C),B - - LD D,CMOS.Cell.ScreenSET - CALL CMOS_RD - - AND CMOS.Cell.ScreenSET.Mask.Int ; в регистре A значение ScreenSET - jr nz,.skiptest - - CALL Test_CONFIG_ALL - jp (IX) ; default int (non CMOS) - -.skiptest: - cp #10 - jr z,.INT_SCORP ; scorpion int - - cp #20 - jr z,.INT_PENT ; pentagon int - -; jr ORIG_SINC ; original int - -.INT_ORIG: - LD IX,SCREEN_TABLES.ORIGINAL - JR .PROG_SCR -.INT_SCORP: - LD IX,SCREEN_TABLES.SCORPION - JR .PROG_SCR -.INT_PENT: - LD IX,SCREEN_TABLES.PENTAGON -; JR PROG_SCR - -.PROG_SCR: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - EX AF,AF' - LD (SYS_PAGE.COPY_SLOT3),A - IN A,(RGADR) - LD (SYS_PAGE.COPY_RGADR),A - - LD (SYS_PAGE.CONFIG_ALL),IX - LD A,0 - -;----[START]-----------------------[? 1] -.loop_1: - OUT (RGADR),A - EX AF,AF' - - LD A,#50 - OUT (SLOT3),A - - LD HL,#C300 - -;----[START]------------------[v 2]----- -.loop_2: - LD C,(IX) -;----[START]-------------[v 3]---------- -.loop_3: -; взять адрес данных для записи в служебную область экрана - LD E,(IX+1) ; take adress of line X - LD D,(IX+2) -;----[START]--------[v 4]--------------- -.loop_4: - LD A,(DE) ; take counter in table 1, line X, column Y - INC DE - AND A - JR Z,.loop_4_exit ; exit if zero-counter - LD B,A - LD A,(DE) - INC DE -;----[START]---[v 5]-------------------- -.loop_5: - LD (HL),A - INC L - LD (HL),0 - INC L - LD (HL),0 - - EX AF,AF' - INC A - OUT (RGADR),A - EX AF,AF' - - LD (HL),0 - DEC L - LD (HL),0 - DEC L - LD (HL),A - - EX AF,AF' - INC A - OUT (RGADR),A - EX AF,AF' - - DJNZ .loop_5 -;--------------[^ 5]-------------------- - JR .loop_4 -;-------------------[^ 4]--------------- -.loop_4_exit: - INC HL ; next line - INC HL - INC HL - INC HL - IN A,(RGADR) - AND #80 - OUT (RGADR),A - DEC C - JR NZ,.loop_3 -;------------------------[^ 3]---------- - INC IX ; next counter - INC IX - INC IX - LD A,(IX) - AND A - JR NZ,.loop_2 -;-----------------------------[^ 2]----- - LD A,SYS_PAGE - OUT (SLOT3),A - LD IX,(SYS_PAGE.CONFIG_ALL) - - EX AF,AF' - ADD A,#80 - JR NC,.loop_1 -;----------------------------------[^ 1] - - ; Exit - LD A,(SYS_PAGE.COPY_RGADR) - OUT (RGADR),A - LD A,(SYS_PAGE.COPY_SLOT3) - OUT (SLOT3),A -.exit: OR A - RET - -;DE - содержимое CONFIG_ALL -Test_CONFIG_ALL: - LD HL,SCREEN_TABLES.SCORPION - AND A - SBC HL,DE - ld IX,FN_SYNC.INT_SCORP - RET Z - - LD HL,SCREEN_TABLES.ORIGINAL - AND A - SBC HL,DE - ld IX,FN_SYNC.INT_ORIG - RET Z - - LD HL,SCREEN_TABLES.PENTAGON - AND A - SBC HL,DE - ld IX,FN_SYNC.INT_PENT - RET Z - and a - RET - - -;--- Screen data table 1: counter1, data1 .. counterX, dataX -SCREEN_TABLES: -; -; | число | значения | -; | строк | в | -; | /2 | строках | -.SCR: DB 41 , #F8 - DB 3 , #FC - DB 4 , #FC - DB 7 , #FC - DB 9 , #F8 - DB 0 - -;.SCR: DB 41,#F8, 3,#FC, 4,#FC, 7,#FC, 9,#F8, 0 -.INT: DB 40,#FC, 2,#FD, 6,#FC, 7,#FC, 9,#FC, 0 -.INT_SC: DB 41,#F8, 1,#FD, 6,#FC, 7,#FC, 9,#F8, 0 -.BLN: DB 41,#FC, 3,#FC, 4,#FC, 7,#FC, 9,#FC, 0 -.SNC: DB 41,#FC, 3,#FC, 4,#FC, 7,#FC, 9,#FC, 0 -.RES: DB 41,#F8, 3,#FE, 4,#FE, 7,#FE, 9,#F8, 0 -;--------------------------------------- - -;--- Screen data tables 2: counter1, data address1 .. counterX, data addressX -; -; | число | значения | -; |столбцов| в | -; | | столбцах | -.PENTAGON: DB 33 : DW .SCR - DB 1 : DW .INT ; DW .BLN - DB 3 : DW .SNC - DB 1 : DW .BLN - DB 1 : DW .SCR - DB 1 : DW .RES - DB 0 ; end -.SCORPION: DB 31 : DW .SCR - DB 1 : DW .INT_SC - DB 1 : DW .SCR - DB 1 : DW .SNC - DB 3 : DW .SNC - DB 1 : DW .BLN - DB 2 : DW .RES - DB 0 ; end -.ORIGINAL: DB 33 : DW .SCR - DB 1 : DW .SNC - DB 1 : DW .INT - DB 2 : DW .SNC - DB 1 : DW .BLN - DB 1 : DW .SCR - DB 1 : DW .RES - DB 0 ; end - -; ;!TEST -;.L_ORIGINAL: DB 32 : DW L_SCR -; DB 4 : DW L_SNC -; DB 1 : DW L_INT -; DB 1 : DW L_SNC -; DB 1 : DW L_BLN -; DB 1 : DW L_SCR -; DB 2 : DW L_RES -; DB 0 ; end - -;--------------------------------------- -FLEX_END: diff --git a/src/bios/exp/FONT.ASM b/src/bios/exp/FONT.ASM index 2ef9370..3ea3f24 100644 --- a/src/bios/exp/FONT.ASM +++ b/src/bios/exp/FONT.ASM @@ -167,4 +167,8 @@ end end ENDLUA -; \ No newline at end of file +; +/* +Линия 256 байтов в ОЗУ становится столбиком в видеопамяти. +Слева направо переходит сверху вниз. Первая линия - первый столбик. +*/ \ No newline at end of file diff --git a/src/bios/exp/FUNC_4x.ASM b/src/bios/exp/FUNC_4x.ASM index 5d4c999..052f141 100644 --- a/src/bios/exp/FUNC_4x.ASM +++ b/src/bios/exp/FUNC_4x.ASM @@ -1,69 +1,125 @@ ; - MACRO WAIT_HDD -.loop: LD BC,IDE.Read.Status - IN A,(C) - BIT IDE.ControlBit.Busy,A - JR NZ,.loop - ENDM +; MACRO WAIT_HDD +; LD BC,IDE.Read.Status +; .loop: IN A,(C) +; BIT IDE.CtrlBit.Busy,A +; JR NZ,.loop +; ENDM ;______________________________________________________________________: ; +F4x_WAIT_HDD: LD BC,IDE.Read.Status +.loop: IN A,(C) + BIT IDE.CtrlBit.Busy,A + RET Z + JR .loop + +; GET_BPB_OFFSET: +; ;LD A,SYS_PAGE +; ;LD HL,MS_BPB +; PUSH AF +; PUSH HL +; LD B,1 +; LD IX,#0000 +; LD DE,#0000 +; CALL FN_HDD_READ +; POP IX +; POP AF +; PUSH AF +; PUSH IX +; LD DE,#01BE ;!HARDCODE смещение от начала сектора для таблицы разделов +; ADD IX,DE +; ; +; EX AF,AF' +; IN A,(SLOT3) +; EX AF,AF' +; OUT (SLOT3),A +; ; +; LD E,(IX+8) ; первый сектор (LBA) начала раздела (DWORD) +; LD D,(IX+9) +; LD L,(IX+10) +; LD H,(IX+11) +; ; +; EX AF,AF' +; OUT (SLOT3),A +; EX AF,AF' +; ; +; PUSH HL +; POP IX +; POP HL +; POP AF +; RET HD_BPB_PREP: - LD D,A - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(SYS_PAGE.HD_IDF_ADR.sectors) - LD E,A - EX AF,AF' - OUT (SLOT3),A - LD A,D - LD D,#00 - LD IX,#0000 - LD B,#01 + ; [x] 27/01/2024 теперь режим спектрума работает с любым разделом HDD + ;LD D,A + ;IN A,(SLOT3) + ;EX AF,AF' + ; LD A,SYS_PAGE + ; OUT (SLOT3),A + ; LD A,(SYS_PAGE.HD_IDF_ADR.sectors) + ; LD E,A + ;EX AF,AF' + ;OUT (SLOT3),A + ;LD A,D + ;LD D,#00 + ;LD IX,#0000 + ;LD B,#01 + + LD B,A + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(SYS_PAGE.CURRENT_HDD) + INC A + JR NZ,.configured + ; + LD A,(SYS_PAGE.HD_IDF_ADR.sectors) + LD E,A + LD D,#00 + LD IX,#0000 + JR .done + ; +.configured: + LD IX,(SYS_PAGE.HDD_PARTITION_OFFSET+2) + LD DE,(SYS_PAGE.HDD_PARTITION_OFFSET) +.done: EX AF,AF' + OUT (SLOT3),A + LD A,B + LD B,#01 + ; HD_PREPARE: PUSH AF PUSH HL CALL HD_CALC_SECS - JR NC,.L1 - POP HL - POP AF - SCF - RET - -.L1: LD A,B + JR C,.error + ; + LD A,B LD BC,IDE.Write.Counter ; Установить число секторов для записи OUT (C),A - - IF IDE_Optimization + ; INC C - OUT (C),L - INC C - OUT (C),E - INC C - OUT (C),D - ELSE - LD BC,IDE.Write.Sector OUT (C),L ; СЕКТОР - LD BC,IDE.Write.CylinderLow + INC C OUT (C),E ; дорожка low - LD BC,IDE.Write.CylinderHigh + INC C OUT (C),D ; дорожка high - ENDIF - + ; LD BC,IDE.Read.Control IN A,(C) AND #F0 ; !!!!! посмотреть OR H - INC B ; IDE.Write.DriveCtrl - + INC B ; IDE.Write.DeviceHead OUT (C),A - POP HL ; BUFER & PAGE POP AF AND A RET + ; +.error: POP HL + POP AF + SCF + RET NEXT_ADD_SEC: @@ -73,7 +129,6 @@ NEXT_ADD_SEC: LD BC,IDE.Write.Counter ; Установить число секторов для записи OUT (C),A - IF IDE_Optimization DEC B INC C IN A,(C) ; IDE.Read.Sector @@ -97,29 +152,7 @@ NEXT_ADD_SEC: LD BC,IDE.Read.Control IN A,(C) - ELSE - LD BC,IDE.Read.Sector - IN A,(C) - ADC A,E - INC B - OUT (C),A ; IDE.Write.Sector - - LD BC,IDE.Read.CylinderLow - IN A,(C) - ADC A,D - INC B - OUT (C),A ; IDE.Write.CylinderLow - - LD BC,IDE.Read.CylinderHigh - IN A,(C) - ADC A,0 - INC B - OUT (C),A ; IDE.Write.CylinderHigh - - LD BC,IDE.Read.Control - IN A,(C) - ENDIF - + ; LD D,A ADC A,0 AND #0F @@ -128,7 +161,7 @@ NEXT_ADD_SEC: AND #F0 OR E INC B - OUT (C),A ; ????? HEADS?! IDE.Write.DriveCtrl + OUT (C),A ; IDE.Write.DeviceHead POP AF RET @@ -151,7 +184,7 @@ FN_HDD_PREPARE: ; CALL HD_PREPARE RET C -;!TEST + ; [x] EX AF,AF' LD A,#BF ; check buffer address in SLOT3 SUB H @@ -169,18 +202,19 @@ FN_HDD_PREPARE: ; .SetCommand: LD BC,IDE.Write.Command - LD A,#20 -; OUT (C),A + LD A,IDE.CMD.ATA.ReadSectorsWithRetry + ; OUT (C),A AND A RET + + FN_HDD_READ_BPB: CALL HD_WAIT RET C CALL HD_BPB_PREP - RET C - - JR HD_RD_L1 + JR NC,FN_HDD_READ.L1 + RET ; FOR LBA ONLY - NEXT_READ @@ -195,9 +229,8 @@ FN_HDD_READ_NEXT: CALL HD_WAIT RET C CALL NEXT_ADD_SEC - JR HD_RD_L1 - - + JR FN_HDD_READ.L1 + ; ; HL - BUFER, A - PAGE FN_HDD_READ: AND A @@ -205,33 +238,57 @@ FN_HDD_READ: DEC B RET Z CALL HD_WAIT + CALL NC,HD_PREPARE RET C - - CALL HD_PREPARE - RET C -HD_RD_L1: - EXX +.L1: EXX LD C,SLOT3 IN B,(C) EXX OUT (SLOT3),A EX AF,AF' - + ; SAFE_PORTY - + ; LD BC,IDE.Write.Command - LD A,#20 + LD A,IDE.CMD.ATA.ReadSectorsWithRetry OUT (C),A -HD_RD_L2: - - WAIT_HDD - - BIT IDE.ControlBit.DataRequest,A - JR NZ,HD_READ_CONT - +.L2: CALL F4x_WAIT_HDD + ;BIT IDE.CtrlBit.DataRequest,A + AND IDE.CtrlByte.DataRequest + JR Z,.RET_PortY + ; + ;HD_READ_CONT + LD BC,IDE.Read.Data +.loop_read1: + DUP 16 + INI ; всего 16 раз INI - оптимально. + EDUP + JR NZ,.loop_read1 +.loop_read2: + DUP 16 + INI ; всего 16 раз INI - оптимально. + EDUP + JR NZ,.loop_read2 + ; + LD A,H + OR L + JR NZ,.L2 + ; + LD A,SYS_PAGE + OUT (SLOT3),A + EX AF,AF' + LD H,high SYS_PAGE.RAM_TABLE + LD L,A + LD A,(HL) + OUT (SLOT3),A + EX AF,AF' + LD HL,#C000 + JR .L2 + ; +.RET_PortY: ZERO_PORTY -HD_RET: - EXX + ; +HD_RET: EXX OUT (C),B EXX LD BC,IDE.Read.Error @@ -239,39 +296,11 @@ HD_RET: AND A SCF RET NZ - + ; EX AF,AF' AND A RET -HD_READ_CONT: - LD BC,IDE.Read.Data - -.loop_read1: - DUP 16 - INI ; всего 16 раз INI - оптимально. - EDUP - JP NZ,.loop_read1 -.loop_read2: - DUP 16 - INI ; всего 16 раз INI - оптимально. - EDUP - JP NZ,.loop_read2 - - LD A,H - OR L - JR NZ,HD_RD_L2 - - LD A,SYS_PAGE - OUT (SLOT3),A - EX AF,AF' - LD HL,SYS_PAGE.RAMD_FAT - LD L,A - LD A,(HL) - OUT (SLOT3),A - EX AF,AF' - LD HL,#C000 ; !!!!! - JR HD_RD_L2 ; HL - BUFER, A - PAGE FN_HDD_WRITE: @@ -293,24 +322,24 @@ FN_HDD_WRITE: EX AF,AF' LD BC,IDE.Write.Command - LD A,#30 + LD A,IDE.CMD.ATA.WriteSectorsWithRetry OUT (C),A HD_WR_L2: - WAIT_HDD + CALL F4x_WAIT_HDD - BIT IDE.ControlBit.DataRequest,A - JP Z,HD_RET + BIT IDE.CtrlBit.DataRequest,A + JR Z,HD_RET LD BC,IDE.Write.Data - LD D,32 + LD D,32 ;!HARDCODE зависит от счётчика DUP в HD_WR_LOOP HD_WR_LOOP: DUP 16 - OUTI ; всего 16 раз OUTI - оптимально. + OUTI ; всего 16 раз OUTI - оптимально. EDUP DEC D - JP NZ,HD_WR_LOOP + JR NZ,HD_WR_LOOP LD A,H OR L @@ -319,31 +348,55 @@ HD_WR_LOOP: LD A,SYS_PAGE OUT (SLOT3),A EX AF,AF' - LD HL,SYS_PAGE.RAMD_FAT + LD H,high SYS_PAGE.RAM_TABLE LD L,A LD A,(HL) OUT (SLOT3),A EX AF,AF' - LD HL,#C000 ;!!!!! + LD HL,#C000 ; !HARDCODE JR HD_WR_L2 +;-----------------------------------------------------------------------; FN_HDD_RECAL: - LD A,#A0 - LD BC,IDE.Write.DriveCtrl + ; !TEST ;[ ] работа с предварительно выбранным HDD + LD BC,IDE.Read.Control + IN A,(C) + PUSH AF + ; + LD A,IDE.Drive.Master + LD BC,IDE.Write.DeviceHead OUT (C),A - LD A,#90 ; DIAGNOSTICS + LD A,IDE.CMD.ATA.ExecuteDeviceDiagnostic CALL HD_CMD_EXE - AND A - BIT IDE.ControlBit.Error,A - RET Z + ; !TEST работа с предварительно выбранным HDD + POP DE + ; + RET C LD BC,IDE.Read.Error IN A,(C) - CP 1 ; !!!!! глянуть + ; !TEST работа с предварительно выбранным HDD + LD BC,IDE.Write.DeviceHead + OUT (C),D + ; + AND #7F + DEC A RET Z SCF - RET + RET + +; Diagnostic Codes +; +; Code Description +; #01 Device 0 passed, Device 1 passed or not present +; #00 Device 0 failed, Device 1 passed or not present +; #81 Device 1 failed, Device 0 passed +; #80 Device 1 failed, Device 0 failed +; +; The meaning of values other than #01 and #81 are vendor specific and +; should be considered a diagnostic failed condition. +;-----------------------------------------------------------------------; + - ;????? глянуть ; RET C ; LD A,#1F ; RECALIBRATE @@ -351,125 +404,223 @@ FN_HDD_RECAL: ; RET + +; [x] 28/01/2024 работает со всеми каналами FN_HDD_TEST_IDE: LD E,#00 - LD BC,IDE.Write.DriveCtrl - LD A,#A0 ; !!!!! глянуть - OUT (C),A - - CALL TEST_HDD_DRV - - JR NZ,NO_HDD1 - SET 0,E -NO_HDD1: - LD BC,IDE.Write.DriveCtrl - LD A,#B0 ; !!!!! глянуть - OUT (C),A - - CALL TEST_HDD_DRV - - JR NZ,NO_HDD2 - SET 1,E -NO_HDD2: - LD A,E + ; TEST Secondary Chanel + LD A,IDE.Chanel.Secondary + OUT (IDE.Chanel.Set),A + CALL .TEST_CHANEL + SLA E + SLA E + ; TEST Primary Chanel + LD A,IDE.Chanel.Primary + OUT (IDE.Chanel.Set),A + CALL .TEST_CHANEL +; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; LD BC,IDE.Write.DeviceHead +; LD A,IDE.Drive.Master +; OUT (C),A +; ; +; CALL TEST_HDD_DRV +; ; +; JR NZ,.NO_HDD1 +; SET 0,E +; .NO_HDD1: +; LD BC,IDE.Write.DeviceHead +; LD A,IDE.Drive.Slave +; OUT (C),A +; ; +; CALL TEST_HDD_DRV +; ; +; JR NZ,.NO_HDD2 +; SET 1,E +; .NO_HDD2: +; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD A,(SYS_PAGE.CURRENT_HDD) + OUT (C),B + CP #FF + JR Z,.exit + AND 1 + JR Z,.exit + LD A,IDE.Chanel.Secondary + OUT (IDE.Chanel.Set),A +; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +.exit: LD A,E AND A SCF RET Z ; HDD absent ! AND A RET +.TEST_CHANEL: + LD BC,IDE.Write.DeviceHead + LD A,IDE.Drive.Master + OUT (C),A + ; + CALL TEST_HDD_DRV + ; + JR NZ,.NO_HDD1 + SET 0,E +.NO_HDD1: + LD BC,IDE.Write.DeviceHead + LD A,IDE.Drive.Slave + OUT (C),A + ; + CALL TEST_HDD_DRV + ; + RET NZ + SET 1,E + RET + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;-----------------------------------[DIFFERENT] ; Не должна портить регистр E!!! TEST_HDD_DRV: -; EXP_HDD.ASM variant - LD HL,#01FE ; ????? + LD HL,#01FE LD BC,IDE.Write.Counter OUT (C),L - IF IDE_Optimization INC C OUT (C),H ; IDE.Write.Sector - + ; DEC C - INC B - IN A,(C) ; ????? IDE.Write.Counter+#100 + DEC B + IN A,(C) ; IDE.Read.Counter CP L RET NZ INC C - ELSE - LD BC,IDE.Write.Sector - OUT (C),H - LD BC,IDE.Write.Counter+#100 - IN A,(C) - CP L - RET NZ - LD BC,IDE.Write.Sector+#100 - ENDIF - IN A,(C) ; ????? IDE.Write.Sector+#100 + IN A,(C) ; IDE.Read.Sector CP H RET -/* -TEST_HDD_DRV: -; EXTENDED.ASM variant - LD HL,#00FF ;????? - LD BC,IDE.Write.CylinderLow - OUT (C),L - IF IDE_Optimization - INC C - OUT (C),H ; IDE.Write.CylinderHigh + +; TEST_HDD_DRV: +; ; EXTENDED.ASM variant +; LD HL,#00FF +; LD BC,IDE.Write.CylinderLow +; OUT (C),L +; INC C +; OUT (C),H ; IDE.Write.CylinderHigh - INC B - DEC C - IN A,(C) ; ????? Тут регистр BC = #0254 - что за порт такой и что оттуда прочитается? - CP L - RET NZ - INC C +; INC B +; DEC C +; IN A,(C) ; Тут регистр BC = #0254 - .CylinderLow +; CP L +; RET NZ +; INC C - ELSE - LD BC,IDE.Write.CylinderHigh - OUT (C),H - LD BC,#0254 ;???!!!! - IN A,(C) - CP L - RET NZ - LD BC,#0255 ;???!!!! - ENDIF - - IN A,(C) ; ????? Тут регистр BC = #0255 - что за порт такой и что оттуда прочитается? - CP H - RET -*/ +; IN A,(C) ; Тут регистр BC = #0255 - .CylinderHigh +; CP H +; RET -FN_HDD_INIT: - LD BC,IDE.Write.DriveCtrl - LD A,#A0 - OUT (C),A - CALL TEST_HDD_DRV - JR NZ,HD_ABSENT -HD_C0_L3: - WAIT_HDD - - LD BC,IDE.Write.Command - LD A,#EC ; !HARDCODE - OUT (C),A - - WAIT_HDD - - BIT IDE.ControlBit.DataRequest,A - JR NZ,HD_C0_L2 - SCF - RET -HD_ABSENT: - LD BC,IDE.Write.DriveCtrl - LD A,#B0 ; !HARDCODE +; [x] 07/01/2024 bit0 - master/slave, bit1: Primary/Secondary, bit2..3: использующийся раздел в MBR +; !TODO сделать работу с переменными биоса SYS_PAGE.IDE_0..3 +FN_HDD_PART: + DI + PUSH BC + PUSH HL + ; + EX AF,AF' + IN A,(SLOT3) + EX AF,AF' + ; + LD C,A + AND 2 + LD A,IDE.Chanel.Primary + JR Z,.SET_CH + LD A,IDE.Chanel.Secondary +.SET_CH: + OUT (IDE.Chanel.Set),A + ; + LD A,C + PUSH AF + AND 1 + ; + LD A,IDE.Drive.Slave + JR NZ,.SET_Master_Slave + ; + LD A,IDE.Drive.Master +.SET_Master_Slave: + LD BC,IDE.Write.DeviceHead OUT (C),A CALL TEST_HDD_DRV - JR Z,HD_C0_L3 - SCF - RET + JR NZ,.Error + ; + CALL FN_HDD_INIT.L3 + JR C,.Error + ; + POP BC + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD A,B + LD (SYS_PAGE.CURRENT_HDD),A + ; + EX AF,AF' + OUT (SLOT3),A + ; + CALL SET_BPB_OFFSET +.exit: POP HL + POP BC + EI + RET + ; +.Error: POP AF + SCF + JR .exit -HD_C0_L2: +; [x] 27/01/2024 адаптирована для корректной работы с FN_HDD_PART +FN_HDD_INIT: + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD A,(SYS_PAGE.CURRENT_HDD) + OUT (C),B + INC A + JR Z,FN_HDD_PART + + ; !FIXIT сделать тут выбор первого попавшегося из SYS.IDE_0-3 + CALL TEST_HDD_DRV + SCF + RET NZ + ; LD BC,IDE.Write.DeviceHead + ; LD A,IDE.Drive.Master + ; OUT (C),A + ; CALL TEST_HDD_DRV + ; JR NZ,.ABSENT + ; +.L3: CALL F4x_WAIT_HDD + LD BC,IDE.Write.Command + LD A,IDE.CMD.ATA.IdentifyDevice ;!FIXIT переделать + OUT (C),A + CALL F4x_WAIT_HDD + AND IDE.CtrlByte.DataRequest + ;JR NZ,.L2 + SCF + RET Z + ;JR NZ,.L2 + ;SCF + ;RET +; .ABSENT: +; LD BC,IDE.Write.DeviceHead +; LD A,IDE.Drive.Slave +; OUT (C),A +; CALL TEST_HDD_DRV +; JR Z,.L3 +; SCF +; RET + ; +;.L2: LD BC,IDE.Read.Data LD HL,SYS_PAGE.HD_IDF_ADR IN A,(SLOT3) @@ -478,51 +629,47 @@ HD_C0_L2: OUT (SLOT3),A INIR INIR + ; B = 0 + LD H,B + LD L,B LD A,(SYS_PAGE.HD_IDF_ADR.sectors) ; число секторов LD C,A - LD HL,0 - LD B,H + ;LD HL,0 + ;LD B,H LD A,(SYS_PAGE.HD_IDF_ADR.heads) ; число головок -.loop: - ADD HL,BC +.loop: ADD HL,BC DEC A JR NZ,.loop LD (SYS_PAGE.HD_IDF_ADR.sec_cyl),HL - - WAIT_HDD - + CALL F4x_WAIT_HDD LD BC,IDE.Read.Control IN A,(C) AND #10 LD B,A LD A,(SYS_PAGE.HD_IDF_ADR.heads) ; число головок - DEC A AND #0F - OR #A0 + OR IDE.Drive.Master OR B LD H,A - LD A,(SYS_PAGE.HD_IDF_ADR+99) ; ????? LBA? - BIT 1,A - JR Z,HD_C0_NO_LBA + LD A,(SYS_PAGE.HD_IDF_ADR.LBA_CHS) + ;BIT 1,A + AND %0000'0010 + JR Z,.NO_LBA SET 6,H - -HD_C0_NO_LBA: - LD BC,IDE.Write.DriveCtrl +.NO_LBA: + LD BC,IDE.Write.DeviceHead OUT (C),H - LD A,(SYS_PAGE.HD_IDF_ADR.sectors) ; число секторов - +.HDD_CONFIGURED: LD BC,IDE.Write.Counter OUT (C),A LD A,D OUT (SLOT3),A - - LD A,#91 ; SET HDD PARAMETERS - CALL HD_CMD_EXE - RET - + LD A,IDE.CMD.ATA.InitializeDeviceParameters ; SET HDD PARAMETERS + ;CALL HD_CMD_EXE + ;RET HD_CMD_EXE: CALL HD_WAIT RET C @@ -533,144 +680,172 @@ HD_WAIT: PUSH BC PUSH AF LD DE,0 -HD_WAIT1: LD BC,IDE.Read.Status - IN A,(C) - BIT IDE.ControlBit.Busy,A - JR Z,HD_W_EXIT +.loop: IN A,(C) + AND IDE.CtrlByte.Busy + JR Z,.EXIT DEC DE LD A,D OR E - JR NZ,HD_WAIT1 + JR NZ,.loop POP AF POP BC POP DE SCF RET -HD_W_EXIT: - POP AF + ; +.EXIT: POP AF POP BC POP DE AND A RET -/* -;EXTENDED.ASM Version -HDD_LBA: ;???!!!! - POP BC - LD L,E - LD E,D - LD D,XL - XOR A - LD H,A - RET +; ;EXTENDED.ASM Version +; HDD_LBA: ;???!!!! +; POP BC +; LD L,E +; LD E,D +; LD D,XL +; XOR A +; LD H,A +; RET +; HD_CALC_SECS: +; LD A,XH +; AND A +; SCF +; RET NZ ; ошибка, слишком большой HDD -HD_CALC_SECS: - LD A,XH - AND A - SCF - RET NZ ; ошибка, слишком большой HDD +; PUSH BC +; LD BC,IDE.Write.DeviceHead +; DEC B +; IN A,(C) +; BIT 6,A +; JR NZ,HDD_LBA +; ; POP BC - PUSH BC - LD BC,IDE.Write.DriveCtrl - DEC B - IN A,(C) - BIT 6,A - JR NZ,HDD_LBA -; POP BC ;!!!!! посмотреть -*/ ;EXP_HDD.ASM Version -HDD_LBA: - POP BC - LD L,E - LD E,D - LD D,XL - LD A,XH - AND #0F - LD H,A - RET - HD_CALC_SECS: PUSH BC LD BC,IDE.Read.Control IN A,(C) - BIT 6,A - JR NZ,HDD_LBA - POP BC ; снимаем значение для корректного ret - - LD A,XH + AND %0100'0000 + POP BC + JR Z,.CHS + ; LBA + LD L,E + LD E,D + LD D,XL + LD A,XH + AND #0F ; LBA 28 + LD H,A + RET + ; CHS +.CHS: LD A,XH AND A SCF RET NZ ; ошибка, слишком большой HDD - -; IX,DE - абсолютный номер сектора + ; IX,DE - абсолютный номер сектора PUSH IX POP HL - + ; IN A,(SLOT3) LD C,A LD A,SYS_PAGE OUT (SLOT3),A LD A,C LD (SYS_PAGE.COPY_SLOT3),A - -; HL,DE - номер сектора -; BC - число секторов на цилиндре + ; HL,DE - номер сектора + ; BC - число секторов на цилиндре LD BC,(SYS_PAGE.HD_IDF_ADR.sec_cyl) ; число секторов на цилиндре LD A,16 ; HL,DE разделить на BC SCF -DIV_LOOP: +.DIV_LOOP: EX DE,HL ADD HL,HL EX DE,HL ADC HL,HL - + ; SBC HL,BC ; сравнить HL и BC - JR NC,NO_ADD ; переноса не было - +1! + JR NC,.NO_ADD ; переноса не было - +1! ADD HL,BC DEC A - JR NZ,DIV_LOOP - JR DIV_END -NO_ADD: + JR NZ,.DIV_LOOP + JR .DIV_END +.NO_ADD: INC DE DEC A - JR NZ,DIV_LOOP -DIV_END: -; DE - результат, HL - остаток -; DE - цилиндр - LD A,(SYS_PAGE.HD_IDF_ADR+12) ; !HARDCODE .sectors -; A - число секторов на дорожке -; HL - номер сектора в цилиндре - LD B,0 + JR NZ,.DIV_LOOP +.DIV_END: + ; DE - результат, HL - остаток + ; DE - цилиндр + LD A,(SYS_PAGE.HD_IDF_ADR.sectors) + ; A - число секторов на дорожке + ; HL - номер сектора в цилиндре LD C,A -; LD BC,(MS_BPB+S_P_T) ; ЧИСЛО СЕКТОРОВ НА ДОРОЖКЕ + ;LD BC,(MS_BPB+S_P_T) ; ЧИСЛО СЕКТОРОВ НА ДОРОЖКЕ XOR A -HD_CALC_LOOP2: - SBC HL,BC + LD B,A +.LOOP: SBC HL,BC INC A - JR NC,HD_CALC_LOOP2 - + JR NC,.LOOP + ; DEC A ; A - головка ADD HL,BC ; L - сектор INC L LD H,A ; HL - HEAD,SEC - + ; LD A,(SYS_PAGE.COPY_SLOT3) OUT (SLOT3),A - AND A RET - -FN_HDD_PART: - BIT 0,A - LD A,#21 ; !HARDCODE - JR Z,.SET_CH - LD A,#01 ; !HARDCODE -.SET_CH: - OUT (IDE.Chanel.Choose),A +; [x] 27/01/2024 теперь режим спектрума работает с любым разделом HDD +SET_BPB_OFFSET: + LD A,SYS_PAGE + LD HL,SYS_PAGE.MS_BPB + LD IX,#0000 + LD DE,#0000 + LD B,1 + CALL FN_HDD_READ + ; + EX AF,AF' + IN A,(SLOT3) + EX AF,AF' + OUT (SLOT3),A + ; + LD A,(SYS_PAGE.CURRENT_HDD) + RRCA + RRCA + AND 3 + INC A + LD B,A + ; + ; ; смещение от начала сектора для таблицы разделов c первым сектором LBA для первого раздела + LD HL,SYS_PAGE.MS_BPB - _sMBR_PARTITION_RECORD + _sBOOT_SECTOR.PARTITION_TABLE + LD DE,_sMBR_PARTITION_RECORD +.loop: ADD HL,DE + DJNZ .loop + ; + LD A,_sMBR_PARTITION_RECORD.Start_LBA + ADD L + LD L,A + LD DE,SYS_PAGE.HDD_PARTITION_OFFSET + LD C,_sMBR_PARTITION_RECORD.Size_LBA - _sMBR_PARTITION_RECORD.Start_LBA + LDIR + ; [x] 07/07/2024 fix bug with select empty partition record + EX DE,HL + XOR A + LD B,_sMBR_PARTITION_RECORD.Size_LBA - _sMBR_PARTITION_RECORD.Start_LBA +.loop2: DEC HL + OR (HL) + DJNZ .loop2 + SUB 1 + ; + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' RET ; ENDMODULE diff --git a/src/bios/exp/FUNC_5x.asm b/src/bios/exp/FUNC_5x.asm index 317606b..c43c2e5 100644 --- a/src/bios/exp/FUNC_5x.asm +++ b/src/bios/exp/FUNC_5x.asm @@ -22,103 +22,75 @@ DRV_VERSION: LD DE,Disk_subsystem_ver_hex AND A RET + ; -DRV_CONFIG: ; ????? что за функция и куда указывает IX +; +DRV_LIST: IN A,(SLOT3) PUSH AF PUSH IY LD A,SYS_PAGE - OUT (SLOT3),A - LD (IX+0),#04 - LD (IX+1),#00 ;FDD COUNT - LD (IX+2),#00 ;HDD COUNT - LD (IX+3),#00 ;CDD COUNT - LD (IX+4),#00 ;END CODE + OUT (SLOT3),A ; !TODO сделать структурой + XOR A + LD (IX+0),#04 ; DB 0 ;LEN ;!HARDCODE + ;LD (IX+1),A ; DB 0 ;FDD COUNT + LD (IX+1),#02 ; DB 0 ;FDD COUNT + LD (IX+2),A ; DB 0 ;HDD COUNT + LD (IX+3),A ; DB 0 ;CDROM COUNT + ; ; BLOCK 13,0 ;RESERVED ;!TODO сделать RAMDRIVE тут? + LD (IX+4),A ; END FLAG + DEC A + ;Calculating FDD devices - LD HL,FDD_INI_TABLE.FDD_0 - INC (IX+1) - LD B,8 - LD A,#FF -.TFD0: - CP (HL) - INC HL - JR NZ,.YYYFD0 - DJNZ .TFD0 - DEC (IX+1) -.YYYFD0: - LD HL,FDD_INI_TABLE.FDD_1 - INC (IX+1) - LD B,8 - LD A,#FF -.TFD1: - CP (HL) - INC HL - JR NZ,.YYYFD1 - DJNZ .TFD1 - DEC (IX+1) -.YYYFD1: -;Calculating IDE devices + ; A=#FF + ; LD HL,SYS_PAGE.FDD_TABLE + ; CALL .CHECK_FDD + ; LD HL,SYS_PAGE.FDD_1_TABLE + ; CALL .CHECK_FDD + ; A=#FF +;Calculating IDE devices IDE TYPE 1-HDD, 2-CD-ROM LD IY,IDE.INIT_TBL_IDE0 + LD DE,IDE.HDD_INIT_TABLE + LD B,4 ; !HARDCODE кол-во IDE устройств +.CHECK_IDE: LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM CP #FF - JR Z,.ABSIDE0 + JR Z,.NEXT_IDE CP IDE.Device.HDD - JR NZ,.NOT_HD0 + JR NZ,.NOT_HDD INC (IX+2) -.NOT_HD0: - CP IDE.Device.CDROM - JR NZ,.NOT_CD0 - INC (IX+3) -.NOT_CD0: -.ABSIDE0: - LD IY,IDE.INIT_TBL_IDE1 - LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM - CP #FF - JR Z,.ABSIDE1 - CP IDE.Device.HDD - JR NZ,.NOT_HD1 - INC (IX+2) -.NOT_HD1: - CP IDE.Device.CDROM - JR NZ,.NOT_CD1 - INC (IX+3) -.NOT_CD1: -.ABSIDE1: - LD IY,IDE.INIT_TBL_IDE2 - LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM - CP #FF - JR Z,.ABSIDE2 - CP IDE.Device.HDD - JR NZ,.NOT_HD2 - INC (IX+2) -.NOT_HD2: - CP IDE.Device.CDROM - JR NZ,.NOT_CD2 - INC (IX+3) -.NOT_CD2: -.ABSIDE2: - LD IY,IDE.INIT_TBL_IDE3 - LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) ;IDE TYPE 1-HDD, 2-CD-ROM - CP #FF - JR Z,.check_exit - CP IDE.Device.HDD - JR NZ,.NOT_HD3 - INC (IX+2) -.NOT_HD3: - CP IDE.Device.CDROM - JR NZ,.check_exit +.NOT_HDD: + CP IDE.Device.ATAPI + JR NZ,.NEXT_IDE INC (IX+3) +.NEXT_IDE: + ADD IY,DE + DJNZ .CHECK_IDE + ; .check_exit: POP IY POP AF OUT (SLOT3),A XOR A RET + ; +; A=#FF +; .CHECK_FDD: +; INC (IX+1) +; LD B,8 +; .TFD0: CP (HL) +; INC HL +; RET NZ +; DJNZ .TFD0 +; DEC (IX+1) +; RET +; ; INCLUDE 'EXTENDED/FDD_DRIVER_2.asm' INCLUDE 'EXTENDED/RAM_DISK_DRIVER_1.asm' - INCLUDE 'EXTENDED/HDD_DRIVER_6.asm' - INCLUDE 'EXTENDED/CD_DRIVER_0.asm' + INCLUDE 'EXTENDED/IDE/ATA_DRV.asm' + INCLUDE 'EXTENDED/IDE/ATAPI_DRV.asm' + INCLUDE 'EXTENDED/IDE/SHARED.asm' ;DISPLAY " EXTENDED end addr: ", /A, $ diff --git a/src/bios/exp/FUNC_CMOS.ASM b/src/bios/exp/FUNC_CMOS.ASM index a783501..0e7fd31 100644 --- a/src/bios/exp/FUNC_CMOS.ASM +++ b/src/bios/exp/FUNC_CMOS.ASM @@ -1,7 +1,13 @@ -;*********************************************** -; ????? чё за херня про бейсик? тут не то ниже -; CMOS - 35h,36h - установки бейсика -;*********************************************** +; + MACRO _mCMOS_MAX_TEST + ASSERT CMOS.MAX_ADDRESS = #7F, "WARNING!!! Logick broken with BIT 7 check" + BIT 7,D + SCF + RET NZ + ENDM +; + +; не менять CF CMOS_EMU_WR: PUSH DE @@ -16,72 +22,86 @@ CMOS_EMU_WR: POP DE RET +; ; запись в CMOS -CMOS_WR: - CALL CMOS_TEST - JR C,CMOS_EMU_WR -XWR_CMOS: - LD BC,CMOS.Port.Address.Write - OUT (C),D - LD BC,CMOS.Port.Data.Write - OUT (C),A - RET +CMOS_WR: ; [x] + _mCMOS_MAX_TEST + ; + CALL CMOS_TEST + JR C,CMOS_EMU_WR +.WR: LD BC,CMOS.Port.Address.Write + OUT (C),D + LD BC,CMOS.Port.Data.Write + OUT (C),A + RET +; -CMOS_EMU_RD: - PUSH DE - - LD C,SLOT3 - IN B,(C) - LD E,SYS_PAGE - OUT (C),E - LD E,D - LD D,#FF - LD A,(DE) - OUT (C),B - - POP DE - RET +; не менять CF +CMOS_EMU_RD: PUSH DE + LD C,SLOT3 + IN B,(C) + LD E,SYS_PAGE + OUT (C),E + LD E,D + LD D, high SYS_PAGE.CMOS_EMULATOR + LD A,(DE) + OUT (C),B + POP DE + RET +; ; чтение из CMOS -CMOS_RD: - CALL CMOS_TEST - JR C,CMOS_EMU_RD -XRD_CMOS: - LD BC,CMOS.Port.Address.Write - OUT (C),D - LD BC,CMOS.Port.Data.Read - IN A,(C) - RET +CMOS_RD: ; [x] + _mCMOS_MAX_TEST + ; + CALL CMOS_TEST + JR C,CMOS_EMU_RD +.RD: LD BC,CMOS.Port.Address.Write + OUT (C),D + LD BC,CMOS.Port.Data.Read + IN A,(C) + RET +; +;Проверка наличия CMOS CMOS_TEST: + PUSH AF PUSH DE PUSH BC - PUSH AF - LD D,#3F ; !HARDCODE CHECKSUM SETTING - CALL XRD_CMOS + LD D,CMOS.TEST_CELL ; [x] раньше писало в ячейку чек-суммы + CALL CMOS_RD.RD LD E,A CPL - CALL XWR_CMOS - CALL XRD_CMOS + CALL CMOS_WR.WR + CALL CMOS_RD.RD CPL CP E - JR NZ,CMOS_ERR LD A,E - CALL XWR_CMOS + JR NZ,.CMOS_ERR + CALL CMOS_WR.WR - POP AF POP BC POP DE + POP AF AND A RET - -CMOS_ERR: - LD A,E - CALL XWR_CMOS - POP AF + ; +.CMOS_ERR: + CALL CMOS_WR.WR POP BC POP DE + POP AF SCF - RET \ No newline at end of file + RET + +; Не портит HL +; GET_CMOS_VALUE: LD A,L +; CALL CMOS_RD +; AND H +; .loop: RRCA +; RRC H +; JR NC,.loop +; RLCA +; RET \ No newline at end of file diff --git a/src/bios/exp/FUNK_FOR_TRDOS.ASM b/src/bios/exp/FUNC_FOR_TRDOS.ASM similarity index 54% rename from src/bios/exp/FUNK_FOR_TRDOS.ASM rename to src/bios/exp/FUNC_FOR_TRDOS.ASM index ac9b096..10fc2fa 100644 --- a/src/bios/exp/FUNK_FOR_TRDOS.ASM +++ b/src/bios/exp/FUNC_FOR_TRDOS.ASM @@ -1,5 +1,6 @@ -; -DISK_REDIR: +;!TODO исправить SLOT2 на SLOT3 и затестить +;!TODO добавить описание +GET_DISK_REDIR: PUSH HL LD HL,SYS_PAGE.DISK_TYPE-#4000 IN A,(SLOT2) @@ -18,27 +19,32 @@ DISK_REDIR: RET ; -; -SET_DISK_TYPE: - PUSH HL - LD HL,SYS_PAGE.DISK_TYPE-#4000 - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A - LD A,(ZX_VARS.OPER_DISK) - AND 3 - ADD A,L - LD L,A - LD (HL),E - LD L,(HL) - EX AF,AF' - OUT (SLOT2),A - LD A,L - POP HL +;!TODO исправить SLOT2 на SLOT3 и затестить, но не пользоваться стеком тогда +;!TODO добавить описание +SET_DISK_REDIR: + PUSH HL + LD HL,SYS_PAGE.DISK_TYPE-#4000 + IN A,(SLOT2) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT2),A + LD A,(ZX_VARS.OPER_DISK) + AND 3 + ADD A,L + LD L,A + LD (HL),E + ; + ;LD L,(HL) + LD L,E + ; + EX AF,AF' + OUT (SLOT2),A + LD A,L + POP HL RET ; +;!TODO исправить SLOT2 на SLOT3 и затестить ; Disk A, DRV - B FDD_TO_DRV: CP 4 @@ -66,7 +72,7 @@ FDD_TO_DRV: RET ; -; +;!TODO исправить SLOT2 на SLOT3 и затестить ; RAM-Disk A, DRV - B RAMD_TO_DRV: CP SYS_PAGE.RAMD_KEYS.NUM @@ -77,10 +83,10 @@ RAMD_TO_DRV: CP 4 CCF RET C - + ; LD HL,SYS_PAGE.DISK_TYPE-#4000 LD L,B - + ; IN A,(SLOT2) LD B,A LD A,SYS_PAGE @@ -94,34 +100,35 @@ RAMD_TO_DRV: RET ; -; +;!TODO исправить SLOT2 на SLOT3 и затестить ; HDD A, DRV - B HDD_TO_DRV: - AND 0FH - LD C,A - LD A,B - CP 4 + AND #0F + OR #40 + + LD C,A + LD A,B + CP 4 CCF - RET C - - LD HL,SYS_PAGE.DISK_TYPE-#4000 - LD L,B - - IN A,(SLOT2) - LD B,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD A,C - ADD A,40H - LD (HL),A - LD A,B - OUT (SLOT2),A - - AND A + RET C + ; + LD H,high (SYS_PAGE.DISK_TYPE-#4000) + LD L,B + ; + IN A,(SLOT2) + LD B,A + LD A,SYS_PAGE + OUT (SLOT2),A + LD A,C + LD (HL),A + LD A,B + OUT (SLOT2),A + ; + AND A RET ; -; +; не убивает DE и BC GET_DRV_ST: CP 4 CCF diff --git a/src/bios/exp/FUNC_LOW_PRINT.ASM b/src/bios/exp/FUNC_LOW_PRINT.ASM index d44b697..c0c0467 100644 --- a/src/bios/exp/FUNC_LOW_PRINT.ASM +++ b/src/bios/exp/FUNC_LOW_PRINT.ASM @@ -62,669 +62,549 @@ ; B - атрибут очистки ; H - высота, L - ширина ;============================================================= - MACRO TEST_40 -; LOCAL LLL -; EX AF,AF' -; JR C,LLL -; INC D ; режим 40 -;LLL: -; EX AF,AF' - ENDM - MACRO DJ_NEXT_HL - DJNZ .LLL - CALL LP_NEXT_HL -.LLL: + MACRO CORRECT_SCR_40_FORWARD ;[x] включил 31/10/23, чисто на Хэллоууууииин + EX AF,AF' + JR C,.LLL + INC D ; режим 40 +.LLL: EX AF,AF' + ENDM ; + + + MACRO CORRECT_SCR_40_BACKWARD + EX AF,AF' + JR C,.LLL + DEC D ; режим 40 +.LLL: EX AF,AF' + ENDM ; + + + MACRO DJNZ_NEXT_HL + DJNZ .LLL + CALL LP_NEXT_HL +.LLL: ; ENDM - - MACRO LP_OPEN_PG - IN A,(SLOT3) - LD C,A - LD A,SYS_PAGE - OUT (SLOT3),A - - LD A,C - LD (SYS_PAGE.COPY_SLOT3),A - IN A,(RGADR) - LD (SYS_PAGE.COPY_RGADR),A - ENDM - - MACRO LP_CLOSE_PG - LD A,(SYS_PAGE.COPY_RGADR) - OUT (RGADR),A - LD A,(SYS_PAGE.COPY_SLOT3) - OUT (SLOT3),A - ENDM - - - MACRO LP_BEG_PM - EX AF,AF' - EXX - IN A,(SLOT3) - LD C,A - IN A,(RGADR) - LD B,A - - LD A,SYS_PAGE - OUT (SLOT3),A - LD (SYS_SP),SP - LD SP,SYS_SP - PUSH BC - - LD HL,(SYS_PAGE.WIN_MAP_IX+WIN_HL) - LD DE,(SYS_PAGE.WIN_MAP_IX+WIN_DE) - LD BC,(SYS_PAGE.WIN_MAP_IX+WIN_BC) - - LD A,E - AND A - RRA - OUT (RGADR),A - EXX - EX AF,AF' - ENDM - - MACRO LP_END_PM - EX AF,AF' - EXX - RLA - LD E,A - LD (SYS_PAGE.WIN_MAP_IX+WIN_HL),HL ; место печати - LD (SYS_PAGE.WIN_MAP_IX+WIN_DE),DE - LD (SYS_PAGE.WIN_MAP_IX+WIN_BC),BC - - POP BC - LD A,B - OUT (RGADR),A - LD A,C - OUT (SLOT3),A - - LD SP,SYS_SP - EXX - EX AF,AF' - RET - ENDM - -LP_PRINT_ALL: - CALL LP_BEG_P - EXX - LD C,A - LD A,#50 - OUT (SLOT3),A - EXX - -LP_PRINT_AL1: - - EXX - LD A,D - OUT (RGADR),A - INC D - LD (HL),C - EXX - LD A,E - EXX - INC L - LD (HL),A - DEC L - -; TEST_40 - - DJ_NEXT_HL - -; DEC B -; CALL Z,LP_NEXT_HL - EXX - - DJNZ LP_PRINT_AL1 - - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - -LP_PRINT_SYM: - - CALL LP_BEG_P - EXX - LD C,A - LD A,#50 - OUT (SLOT3),A - EXX -LP_PRINT_SY1: - EXX - LD A,D - OUT (RGADR),A - LD (HL),C - INC D - - TEST_40 - - DJ_NEXT_HL -; DEC B -; CALL Z,LP_NEXT_HL - EXX - DJNZ LP_PRINT_SY1 - - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - -LP_PRINT_ATR: - CALL LP_BEG_P - LD A,E - EXX - LD C,A - LD A,#50 - OUT (SLOT3),A - EXX - -LP_PRINT_AT1: - EXX - LD A,D - OUT (RGADR),A - INC D - - INC L - LD (HL),C - DEC L - - - TEST_40 - - DJ_NEXT_HL -; DEC B -; CALL Z,LP_NEXT_HL - EXX - DJNZ LP_PRINT_AT1 - - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - - -LP_PRINT_LINE: - CALL LP_BEG_P - EXX -; LD C,A - LD A,#50 - OUT (SLOT3),A - LD C,RGADR - EXX - -LP_PRINT_LN1: - EXX - OUT (C),D - INC D - EXX - LD A,(HL) - INC HL - EXX - LD (HL),A - EXX - LD A,E - EXX - INC L - LD (HL),A - DEC L - - TEST_40 - - DJ_NEXT_HL - -; DEC B -; CALL Z,LP_NEXT_HL - EXX - - DJNZ LP_PRINT_LN1 - - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - - -LP_PRINT_LINE2: - CALL LP_BEG_P - - LD A,#50 - OUT (SLOT3),A - EXX - LD C,RGADR - EXX - -LP_PRINT_LN2: - LD A,(HL) - INC HL - EXX - OUT (C),D - INC D - LD (HL),A - TEST_40 - - DJ_NEXT_HL - -; DEC B -; CALL Z,LP_NEXT_HL - EXX - DJNZ LP_PRINT_LN2 - - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - -LP_PRINT_LINE3: - CALL LP_BEG_P - EXX -; LD C,A - LD A,#50 - OUT (SLOT3),A - EXX - -LP_PRINT_LN3: - EXX - LD A,D - OUT (RGADR),A - INC D - - EXX - LD A,(HL) - INC HL - CP D - JR NZ,LP_PR_L31 - DEC HL - LD A,' ' -LP_PR_L31: - EXX - - LD (HL),A - EXX - LD A,E - EXX - INC L - LD (HL),A - DEC L - - TEST_40 - - DJ_NEXT_HL - -; DEC B -; CALL Z,LP_NEXT_HL - EXX - - DJNZ LP_PRINT_LN3 - - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - - -LP_PRINT_LINE4: - CALL LP_BEG_P - EXX -; LD C,A - LD A,#50 - OUT (SLOT3),A - EXX - -LP_PRINT_LN4: - EXX - LD A,D - OUT (RGADR),A - - EXX - LD A,(HL) - INC HL - CP D - JR NZ,LP_PR_L41 - DEC HL - LD A,' ' -LP_PR_L41: - EXX - - LD (HL),A - - INC D - - TEST_40 - - DJ_NEXT_HL - -; DEC B -; CALL Z,LP_NEXT_HL - EXX - - DJNZ LP_PRINT_LN4 - - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - - -LP_PRINT_LINE5: - CALL LP_BEG_P - EXX -; LD C,A - LD A,#50 - OUT (SLOT3),A - EXX - -LP_PRINT_LN5: - EXX - LD A,D - OUT (RGADR),A - - EXX - LD A,(HL) - INC HL - CP D - JR Z,LP_PR_L51 - EXX - - LD (HL),A - EXX - LD A,E - EXX - INC L - LD (HL),A - DEC L - - INC D - - TEST_40 - - DJ_NEXT_HL - -; DEC B -; CALL Z,LP_NEXT_HL - EXX - - DJNZ LP_PRINT_LN5 - -LP_PR_L51: - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - -LP_PRINT_LINE6: - CALL LP_BEG_P - EXX -; LD C,A - LD A,#50 - OUT (SLOT3),A - EXX - -LP_PRINT_LN6: - EXX - LD A,D - OUT (RGADR),A - - EXX - LD A,(HL) - INC HL - CP D - JR Z,LP_PR_L61 - EXX - - LD (HL),A - - INC D - - TEST_40 - - DJ_NEXT_HL - -; DEC B -; CALL Z,LP_NEXT_HL - EXX - - DJNZ LP_PRINT_LN6 -LP_PR_L61: - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - -LP_PRINT_LINE_DIR: - - CALL LP_BEG_P - EXX -; LD C,A - LD A,#50 - OUT (SLOT3),A - EXX - -LP_PRINT_LN_D: - EXX - LD A,D - OUT (RGADR),A - - EXX - LD A,(HL) - INC HL - CP B - JR Z,LP_LN_DD1 - EXX - - CP 14 - JR NC,LP_PRINT_LN_DD - CP 7 - JR C,LP_PRINT_LN_DD - SUB 7 - JR Z,LP_BEEP - DEC A - JR Z,LP_BACK - DEC A - JR Z,LP_TAB - DEC A - JR Z,LP_LF - DEC A - JR Z,LP_XX - DEC A - JR Z,LP_CLS - DEC A - JR Z,LP_CR - -LP_XX: ; выводить! - -LP_PRINT_LN_DD: - LD (HL),A - INC D - -LP_PRINT_LN_D1: - - DJ_NEXT_HL - EXX - JR LP_PRINT_LN_D - -LP_LN_DD1: - LD A,SYS_PAGE - OUT (SLOT3),A - CALL LP_END_P - RET - -LP_PRINT_LN_D11: - LD A,#50 - OUT (SLOT3),A - JR LP_PRINT_LN_D1 - -LP_BEEP: - JR LP_PRINT_LN_D1 - -LP_BACK: - LD A,SYS_PAGE - OUT (SLOT3),A - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_H_BEG) - CP D - JR Z,LP_PRINT_LN_D11 - INC B - DEC D - JR LP_PRINT_LN_D11 - -LP_TAB: - LD A,SYS_PAGE - OUT (SLOT3),A - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_H_BEG) - SUB D - NEG - AND 07H - NEG - ADD A,8 - - LD C,A - LD A,#50 - OUT (SLOT3),A - -LP_TAB_L: - LD (HL),20H - INC D - DEC B - JR Z,LP_TAB_L1 - DEC C - JR NZ,LP_TAB_L - JR LP_PRINT_LN_D1 - -LP_TAB_L1: - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_H_BEG) - LD D,A - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_SIZE_REL) - LD B,A - -LP_LF: - LD A,SYS_PAGE - OUT (SLOT3),A - - INC L - INC L - INC L - INC L - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_V_END) - CP L - JR NC,LP_PRINT_LN_D11 - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_V_BEG) - LD L,A ; вернуться наверх без скролла!!! - -; scrolling ???? - - JR LP_PRINT_LN_D11 - -LP_CLS: - - JR LP_PRINT_LN_D1 - -LP_CR: - LD A,SYS_PAGE - OUT (SLOT3),A - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_H_BEG) - LD D,A - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_SIZE_REL) - LD B,A - - JR LP_PRINT_LN_D11 - -;***************************************** - -LP_SET_PLACE: ; !!!!! ожидается, что портятся только альтернативные регистры и те, что как параметры на входе - CALL LP_BEG_P - CALL LP_AT_D - CALL LP_TAB_E - CALL LP_END_P - RET - -LP_GET_PLACE: - CALL LP_BEG_P - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_H_BEG) - NEG - EXX - ADD A,D - EXX - LD E,A - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_V_BEG) - NEG - EXX - ADD A,L - DEC A - EXX - RRCA - RRCA - AND #3F - LD D,A - - CALL LP_END_P - RET - -;********************************************* - - -;********************************************* - -LP_CLS_WIN: - LD C,20h - JR LP_CLS_WIN_3 -LP_CLS_WIN2: - LD C,A -LP_CLS_WIN_3: - CALL LP_BEG_P - LD (SYS_PAGE.SYS_WORK1),BC ; сохранить цвет - push de -LP_CLS_L2: - CALL LP_AT_D - CALL LP_TAB_E - PUSH DE - - EXX - LD BC,(SYS_PAGE.SYS_WORK1) - EXX - LD B,L - - LD A,#50 - OUT (SLOT3),A - -LP_CLS_L1: - - EXX - LD A,D - OUT (RGADR),A - - LD (HL),C - INC L - LD (HL),B - DEC L - - INC D - EXX - - DJNZ LP_CLS_L1 - - LD A,SYS_PAGE - OUT (SLOT3),A - - POP DE - INC D - DEC H - JR NZ,LP_CLS_L2 - pop de - - CALL LP_AT_D - CALL LP_TAB_E - CALL LP_END_P - RET +;********************************* +;* LOW LEVEL PRINTER * +;* DE' - ZG * +;* HL' - PLACE ON SCR * +;* C' - ATTRIBUTES * +;* B' - COUNT SYMBS * +;* ZF - inverse * +;* AF' - страница и mode * +;********************************* +; MACRO LP_BEG_PM +; EX AF,AF' +; EXX +; IN A,(SLOT3) +; LD C,A +; IN A,(PORT_Y) +; LD B,A +; LD A,SYS_PAGE +; OUT (SLOT3),A +; LD (SYS_SP),SP +; LD SP,SYS_SP +; PUSH BC +; ; +; LD HL,(WIN_ID_0.HL) +; LD DE,(WIN_ID_0.DE) +; LD BC,(WIN_ID_0.BC) +; LD A,E +; AND A +; RRA +; OUT (PORT_Y),A +; EXX +; EX AF,AF' +; ENDM ; + +; MACRO LP_END_PM +; EX AF,AF' +; EXX +; RLA +; LD E,A +; LD (WIN_ID_0.HL),HL ; место печати +; LD (WIN_ID_0.DE),DE +; LD (WIN_ID_0.BC),BC +; ; +; POP BC +; LD A,B +; OUT (PORT_Y),A +; LD A,C +; OUT (SLOT3),A +; LD SP,SYS_SP +; EXX +; EX AF,AF' +; RET +; ENDM ; + +; +;------------------------------------------------------------------[#81] +LP_PRINT_ALL: CALL LP_BEG_P + EXX + LD C,A + EXX + LD A,#50 + OUT (SLOT3),A + ; +.loop: EXX + LD A,D + OUT (PORT_Y),A + INC D +.cont: LD (HL),C + EXX + LD A,E + EXX + INC L + LD (HL),A + DEC L + CORRECT_SCR_40_FORWARD + DJNZ_NEXT_HL + EXX + DJNZ .loop + JP LP_END_P +;------------------------------------------------------------------[#81] +; + +; +;------------------------------------------------------------------[#82] +; +LP_PRINT_SYM: CALL LP_BEG_P + EXX + LD C,A + EXX + LD A,#50 + OUT (SLOT3),A + ; +.loop: EXX + LD A,D + OUT (PORT_Y),A +.cont: LD (HL),C + INC D + CORRECT_SCR_40_FORWARD + DJNZ_NEXT_HL + EXX + DJNZ .loop + JP LP_END_P +;------------------------------------------------------------------[#82] +; + +; +;------------------------------------------------------------------[#83] +LP_PRINT_ATR: CALL LP_BEG_P + LD A,E + EXX + LD C,A + EXX + LD A,#50 + OUT (SLOT3),A + ; +.loop: EXX + LD A,D + OUT (PORT_Y),A + INC D + INC L + LD (HL),C + DEC L + CORRECT_SCR_40_FORWARD + DJNZ_NEXT_HL + EXX + DJNZ .loop + JP LP_END_P +;------------------------------------------------------------------[#83] +; + +; +;------------------------------------------------------------------[#85] +LP_PRINT_LINE: CALL LP_BEG_P + EXX + LD C,PORT_Y + EXX + LD A,#50 + OUT (SLOT3),A + ; +.loop: EXX + OUT (C),D + INC D + EXX + LD A,(HL) + INC HL + EXX + LD (HL),A + EXX + LD A,E + EXX + INC L + LD (HL),A + DEC L + CORRECT_SCR_40_FORWARD + DJNZ_NEXT_HL + EXX + DJNZ .loop + JP LP_END_P +;------------------------------------------------------------------[#85] +; + +; +;------------------------------------------------------------------[#86] +LP_PRINT_LINE2: CALL LP_BEG_P + EXX + LD C,PORT_Y + EXX + LD A,#50 + OUT (SLOT3),A + ; +.loop: LD A,(HL) + INC HL + EXX + OUT (C),D + INC D + LD (HL),A + CORRECT_SCR_40_FORWARD + DJNZ_NEXT_HL + EXX + DJNZ .loop + ;LD A,SYS_PAGE + ;OUT (SLOT3),A + JP LP_END_P +;------------------------------------------------------------------[#86] +; + +; +;------------------------------------------------------------------[#87] +LP_PRINT_LINE3: CALL LP_BEG_P + LD A,#50 + OUT (SLOT3),A + ; +.loop: EXX + LD A,D + OUT (PORT_Y),A + INC D + EXX + LD A,(HL) + INC HL + CP D + JR NZ,.NoEnd + ; + DEC HL + EXX + LD C,' ' + JP LP_PRINT_ALL.cont + ; +.NoEnd: EXX + LD (HL),A + EXX + LD A,E + EXX + INC L + LD (HL),A + DEC L + CORRECT_SCR_40_FORWARD + DJNZ_NEXT_HL + EXX + DJNZ .loop + JP LP_END_P +;------------------------------------------------------------------[#87] +; + +; +;------------------------------------------------------------------[#88] +LP_PRINT_LINE4: CALL LP_BEG_P + LD A,#50 + OUT (SLOT3),A + ; +.loop: EXX + LD A,D + OUT (PORT_Y),A + EXX + LD A,(HL) + INC HL + CP D + JR NZ,.NoEndSymbol + ; + DEC HL + EXX + LD C,' ' + JP LP_PRINT_SYM.cont + ; +.NoEndSymbol: EXX + LD (HL),A + INC D + CORRECT_SCR_40_FORWARD + DJNZ_NEXT_HL + EXX + DJNZ .loop + JP LP_END_P +;------------------------------------------------------------------[#88] +; + +; +;------------------------------------------------------------------[#8B] +LP_PRINT_LINE5: CALL LP_BEG_P + LD A,#50 + OUT (SLOT3),A + EXX + LD C,PORT_Y + EXX + ; +.loop: EXX + OUT (C),D + EXX + LD A,(HL) + INC HL + CP D + JR Z,LP_END_P + ; + EXX + LD (HL),A + EXX + LD A,E + EXX + INC L + LD (HL),A + DEC L + INC D + CORRECT_SCR_40_FORWARD + DJNZ_NEXT_HL + EXX + DJNZ .loop + ;JP LP_END_P +;----------------- ------------------------------------[#8B] +; ожидается, что портятся только альтернативные регистры и те, что как параметры на входе +LP_END_P: LD A,SYS_PAGE + OUT (SLOT3),A + ; +.SYS_PAGE: EX AF,AF' + EXX + RLA + LD E,A + LD (WIN_ID_0.LineAddr),HL ; место печати + LD (WIN_ID_0.ColumnRGADR_TXTMode),DE + LD (WIN_ID_0.reg_BC),BC + CALL LP_CLOSE_PG + EXX + EX AF,AF' + AND A + RET + ; +.short: EX AF,AF' + EXX + CALL LP_CLOSE_PG + EXX + EX AF,AF' + AND A + RET +;------------------------------------------------------------------[#8C] +LP_PRINT_LINE6: CALL LP_BEG_P + LD A,#50 + OUT (SLOT3),A + EXX + LD C,PORT_Y + EXX + ; +.loop: EXX + OUT (C),D + EXX + LD A,(HL) + INC HL + CP D + JR Z,LP_END_P + ; + EXX + LD (HL),A + INC D + CORRECT_SCR_40_FORWARD + DJNZ_NEXT_HL + EXX + DJNZ .loop + JP LP_END_P +;------------------------------------------------------------------[#8C] +; + + + + +; +;------------------------------------------------------------------[#84] +; портятся только альтернативные регистры и те, что как параметры на входе +LP_SET_PLACE: CALL LP_BEG_P + CALL LP_SET_CUR + JP LP_END_P.SYS_PAGE +;------------------------------------------------------------------[#84] +; + +; +;------------------------------------------------------------------[#8E] +LP_GET_PLACE: CALL LP_BEG_P + LD A,(WIN_ID_0.H_BEG) + NEG + EXX + ADD A,D + EXX + LD E,A + LD A,(WIN_ID_0.V_BEG) + NEG + EXX + ADD A,L + DEC A + EXX + RRCA + RRCA + AND %0011'1111 + LD D,A + ; режим txt 40 + EX AF,AF' + JR C,.no_txt40 + SRL E + AND A +.no_txt40: EX AF,AF' + JP LP_END_P.short +;------------------------------------------------------------------[#8E] +; + +; +;-------------------------------------------------------------[#89, #8D] +;--------------------------------------------------------[#8D] +LP_CLS_WIN2: LD C,A + JR LP_CLS_WIN.START +;--------------------------------------------------------[#8D] +;--------------------------------------------------------[#89] +LP_CLS_WIN: LD C,' ' +;---------------- -----------------------------[#89] +.START: CALL LP_BEG_P + CALL .CLS + JP LP_END_P.SYS_PAGE + ; +.CLS: LD (SYS_PAGE.SYS_WORK1),BC ; сохранить цвет ; !TODO использовать переменные окна + PUSH DE + ; !TODO проверка на превышение размера окна - но сейчас эти процедуры для полного экрана + ; EXX + ; LD A,B + ; EXX + ; CP L + ; JR NC,.loop1 + ; LD L,A + ; +.loop1: CALL LP_SET_CUR + PUSH DE + EXX + LD BC,(SYS_PAGE.SYS_WORK1) ; !TODO использовать переменные окна + EXX + LD B,L + LD A,#50 + OUT (SLOT3),A + ; +.loop2: EXX + LD A,D + OUT (PORT_Y),A + LD (HL),C + INC L + LD (HL),B + DEC L + INC D + CORRECT_SCR_40_FORWARD + EXX + DJNZ .loop2 + ; + LD A,SYS_PAGE + OUT (SLOT3),A + POP DE + INC D + DEC H + JR NZ,.loop1 + ; + POP DE + JP LP_SET_CUR +;-------------------------------------------------------------[#89, #8D] +; + +; +;------------------------------------------------------------------[#B8] +; DE - адрес куда переслать фонт +WIN_GET_ZG: LD HL,ZG_ADDRESS + LD BC,ZG_SIZE + LDIR + AND A + RET +;------------------------------------------------------------------[#B8] +; + +; +;------------------------------------------------------------------[#B6] +WIN_SET_ZG: EX AF,AF' ; LP_SET_ZG: + EXX + CALL LP_OPEN_PG + CALL .SET + CALL LP_CLOSE_PG + EXX + EX AF,AF' + AND A + RET + ; +.SET: IN A,(SLOT1) ;LP_SET_ZG1 + LD (SYS_PAGE.COPY_SLOT1),A + LD A,SHARED_PAGE + OUT (SLOT1),A + EXX + LD BC,Port_All_Mode + IN A,(C) + LD (SYS_PAGE.SYS_WORK1),A + AND #FE ; Spectrum Screen on, accelerator and keyboard interrupt off + OUT (C),A + EX AF,AF' + LD B,A + AND #0F + ADD A,A + OUT (PORT_Y),A + LD A,B ; %xx00'0000 + RRCA ; %0xx0'0000 + RRCA ; %00xx'0000 + RRCA ; %000x'x000 + AND %0001'1000 + OR %0100'0000 + LD H,A + LD L,0 + LD BC,ZG_SIZE + EX DE,HL + ;[ ] 11/02/2024 установка шрифта более гибкая без заплётов + LD A,H + SUB #C0 + JR NC,.change + ; + LDIR +.cont: EX DE,HL + LD A,H + RRCA + RRCA + RRCA + DEC A + AND 3 + ADD A,#58 + LD H,A + ; +.loop: LD (HL),L + INC L + JR NZ,.loop + ; + LD A,(SYS_PAGE.SYS_WORK1) + LD BC,Port_All_Mode + OUT (C),A + EXX + EX AF,AF' + LD A,(SYS_PAGE.COPY_SLOT1) + OUT (SLOT1),A + RET + ; + ;[ ] 11/02/2024 установка шрифта более гибкая без заплётов +.change: LD A,(SYS_PAGE.COPY_SLOT3) + OUT (SLOT3),A + LDIR + LD A,SYS_PAGE + OUT (SLOT3),A + JR .cont +;------------------------------------------------------------------[#B6] +; ;******************************************************* ; @@ -733,1295 +613,1784 @@ LP_CLS_L1: ; 1 - ver size ; 2 - hor place ; 3 - ver place +; определение size +LP_SIZE: CALL LP_OPEN_PG + LD DE,(WIN_ID_0.USER.SIZE_H) + LD A,(WIN_ID_0.USER.MODE) + AND %0010'0000 + CALL LP_CLOSE_PG + RET NZ + ; txt 40 + SLA E + RET +; -LP_SIZE: ; определение size - LP_OPEN_PG - LD DE,(SYS_PAGE.WIN_MAP_IX+WIN_SIZE_H) - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_MODE) - BIT 5,A - LP_CLOSE_PG - RET NZ - LD A,E - ADD A,A - LD E,A - RET - -; LD (SYS_PAGE.WIN_MODE_SC),DE ; место по горизонтали и страница моды -; LD (SYS_PAGE.WIN_MODE_SH),HL ; место по вертикали с адресом - -LP_AT_D: ; !!!!! ожидается, что портятся только альтернативные регистры и те, что как параметры на входе - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_SIZE_V) - EXX - LD L,A - EXX - LD A,D - EXX -LP_AT_DX: - SUB L - JR NC,LP_AT_DX -; JR Z,LP_AT_DX - ADD A,L - - ADD A,A - ADD A,A - LD L,A - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_V_BEG) - ADD A,L - LD L,A - INC L - LD H,#C3 - EXX - RET - -; !!!!! ожидается, что портятся только альтернативные регистры и те, что как параметры на входе -LP_TAB_E: - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_SIZE_REL) - EXX - LD D,A - EXX - LD A,E - EXX -LP_TAB_EX: - SUB D - JR NC,LP_TAB_EX - JR Z,LP_TAB_EX - NEG - LD B,A ; сохранить сколько осталось символов в строке - NEG - ADD A,D - LD D,A - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_MODE) - BIT 5,A - JR Z,LP_NO_ADD_A - - LD A,D - ADD A,A - LD D,A - -LP_NO_ADD_A: - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_H_BEG) - ADD A,D - LD D,A - EXX - RET - - +; ожидается, что портятся только альтернативные регистры и те, что как параметры на входе +; установить курсор: +; D - номер символа по вертикали +; E - номер символа по горизонтали +LP_SET_CUR: ; LP_AT_D: + LD A,(WIN_ID_0.USER.SIZE_V) + EXX + LD L,A + EXX + LD A,D + EXX +.loop_x: SUB L + JR NC,.loop_x + ; + ADD A,L + ADD A,A + ADD A,A + LD L,A + ; + LD A,(WIN_ID_0.V_BEG) + ADD A,L + LD L,A + INC L + LD H,#C3 ;!HARDCODE начало описателей в SLOT3 + EXX + ;RET + ; + ;LP_TAB_E: + LD A,(WIN_ID_0.SIZE_REL) + EXX + LD D,A + EXX + LD A,E + EXX +.loop_y: SUB D + JR NC,.loop_y + JR Z,.loop_y + ; + NEG + LD B,A ; сохранить сколько осталось символов в строке + NEG + ADD A,D + LD D,A + ; + EX AF,AF' + JR C,.LLL + SLA D ; режим txt 40. не должно ставить CF +.LLL: EX AF,AF' +.skip_Dx2: LD A,(WIN_ID_0.H_BEG) + ADD A,D + LD D,A + EXX + RET ;************************************************************* ; вычисление нового места -LP_NEXT_HL: - LD A,SYS_PAGE - OUT (SLOT3),A - - INC L - INC L - INC L - INC L - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_V_END) - CP L - JR NC,LP_NEXT_HL1 - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_V_BEG) - LD L,A - INC L - LD H,0C3H - -LP_NEXT_HL1: - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_H_BEG) - LD D,A - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_SIZE_REL) - LD B,A - - LD A,#50 - OUT (SLOT3),A - RET - -; program set registers -; for low printer -; !!!!! ожидается, что портятся только альтернативные регистры и те, что как параметры на входе -LP_BEG_P: - EX AF,AF' - EXX - LP_OPEN_PG - LD HL,(SYS_PAGE.WIN_MAP_IX+WIN_HL) - LD DE,(SYS_PAGE.WIN_MAP_IX+WIN_DE) - LD BC,(SYS_PAGE.WIN_MAP_IX+WIN_BC) - LD A,E - AND A - RRA - OUT (RGADR),A - EXX - EX AF,AF' - RET - - -; program init registers -; for low printer & save -WIN_GET_ZG: ; DE - адрес куда переслать фонт - LD HL,ZG_ADRESS - LD BC,#0800 - LDIR - AND A - RET - -WIN_SET_ZG: -LP_SET_ZG: - EX AF,AF' - EXX - LP_OPEN_PG - - CALL LP_SET_ZG1 - - LP_CLOSE_PG - EXX - EX AF,AF' - AND A - RET - - -LP_SET_ZG1: - IN A,(SLOT1) - LD (SYS_PAGE.COPY_SLOT1),A - LD A,#FF - OUT (SLOT1),A - EXX - - LD BC,Port_All_Mode - IN A,(C) - LD (SYS_PAGE.SYS_WORK1),A - AND #FE ; accelerator and keyboard interrupt off - OUT (C),A - - EX AF,AF' - - LD B,A - AND #0F - ADD A,A - OUT (RGADR),A - LD A,B - RRCA - RRCA - RRCA - AND #18 - OR #40 - LD H,A - LD L,0 - - LD BC,#0800 - EX DE,HL - LDIR - EX DE,HL - LD A,H - RRCA - RRCA - RRCA - DEC A - AND 3 - ADD A,#58 - LD H,A -; LD HL,05800H -LP_INI_L1: - LD (HL),L - INC L - JR NZ,LP_INI_L1 - - LD A,(SYS_PAGE.SYS_WORK1) - LD BC,Port_All_Mode - OUT (C),A - - EXX - - EX AF,AF' - LD A,(SYS_PAGE.COPY_SLOT1) - OUT (SLOT1),A - - RET - -LP_INI_P: - - EX AF,AF' - EXX - - LP_OPEN_PG - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_MODE) - CP #C0 - JR NC,LP_INI_NO_ZG ; открытие бордера... - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_MODE_S) - BIT 0,A - JR NZ,LP_INI_NO_ZG ; открытие Spectrum-Screen - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_MODE) - BIT 4,A - JR Z,LP_INI_NO_ZG ; открытие графического экрана - LD DE,(SYS_PAGE.WIN_ZG) ; знакогенератор - - EXX - EX AF,AF' - CALL LP_SET_ZG1 - EXX - EX AF,AF' - -LP_INI_NO_ZG: - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_H_BEG) - LD D,A - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_V_BEG) - LD L,A - INC L - LD H,#C3 - - AND A - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_MODE) - BIT 5,A - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_SIZE_H) - JR NZ,LP_INI_40 - ADD A,A - SCF -LP_INI_40: - LD B,A - LD (SYS_PAGE.WIN_MAP_IX+WIN_SIZE_REL),A - -; LD DE,(SYS_PAGE.WIN_MODE_SC) ; место по горизонтали и страница моды -; LD HL,(SYS_PAGE.WIN_MODE_SH) ; место по вертикали с адресом -; INC HL -; LD B,0 -; CALL LP_TAB_H2 - - EX AF,AF' - EXX -; JR LP_END_P -; program save registers -; for low printer -LP_END_P: ; !!!!! ожидается, что портятся только альтернативные регистры и те, что как параметры на входе - EX AF,AF' - EXX - RLA - LD E,A - LD (SYS_PAGE.WIN_MAP_IX+WIN_HL),HL ; место печати - LD (SYS_PAGE.WIN_MAP_IX+WIN_DE),DE - LD (SYS_PAGE.WIN_MAP_IX+WIN_BC),BC - - LP_CLOSE_PG - EXX - EX AF,AF' - AND A - RET - -LP_END_P2: - EX AF,AF' - EXX - LP_CLOSE_PG - EXX - EX AF,AF' - RET +LP_NEXT_HL: LD A,SYS_PAGE + OUT (SLOT3),A + LD A,4 ;!HARDCODE длина одного описателя квадратика + ADD L + LD L,A + LD A,(WIN_ID_0.V_END) + CP L + JR C,.end_line + ; +.no_end_line: LD A,(WIN_ID_0.H_BEG) + LD D,A + LD A,(WIN_ID_0.SIZE_REL) + LD B,A + LD A,#50 + OUT (SLOT3),A + RET + ; +.end_line: LD HL,(WIN_ID_0.V_BEG) + INC L + LD H,#C3 ;!HARDCODE начало описателей в SLOT3 + JP .no_end_line +; !ожидается, что портятся только альтернативные регистры и те, что как параметры на входе +LP_BEG_P: EX AF,AF' + EXX + CALL LP_OPEN_PG + LD HL,(WIN_ID_0.LineAddr) + LD DE,(WIN_ID_0.ColumnRGADR_TXTMode) + LD BC,(WIN_ID_0.reg_BC) + LD A,E + AND A + RRA + ;OUT (PORT_Y),A + EXX + EX AF,AF' + RET +; +LP_INI_P: EX AF,AF' + EXX + CALL LP_OPEN_PG + LD A,(WIN_ID_0.USER.MODE) + CP #C0 + JR NC,.NO_ZG ; открытие бордера... + LD A,(WIN_ID_0.USER.MODE_S) + AND %0000'0001 + JR NZ,.NO_ZG ; открытие Spectrum-Screen + ; + LD A,(WIN_ID_0.USER.MODE) + BIT 4,A + JR Z,.NO_ZG ; открытие графического экрана + ;LD DE,(SYS_PAGE.WIN_ZG) ; знакогенератор + LD DE,ZG_ADDRESS ; знакогенератор + EXX + EX AF,AF' + CALL WIN_SET_ZG.SET ;LP_SET_ZG1 ;!TODO стоит ли каждый раз закидывать шрифт? + EX AF,AF' + EXX +.NO_ZG: LD A,(WIN_ID_0.H_BEG) + LD D,A + LD A,(WIN_ID_0.V_BEG) + LD L,A + INC L + LD H,#C3 + AND A + LD A,(WIN_ID_0.USER.MODE) + BIT 5,A + LD A,(WIN_ID_0.USER.SIZE_H) + JR NZ,.TXT_40 + ; TXT_80 + ADD A,A + SCF +.TXT_40: LD B,A + LD (WIN_ID_0.SIZE_REL),A + EX AF,AF' + EXX + JP LP_END_P ;******************************************************** -LP_OPEN_S: - LD A,B - ADD A,A - CP LP_SC_TAB_SIZE - CCF - RET C - PUSH HL - LD HL,LP_SC_TAB +; +;------------------------------------------------------------------[#80] +LP_OPEN_S: LD A,B + ADD A,A + CP LP_SC_TAB.SIZE + CCF + RET C + PUSH HL + LD HL,LP_SC_TAB + ADD A,L + LD L,A + JR NC,.no_inc + INC H +.no_inc: LD A,(HL) + INC HL + LD H,(HL) + LD L,A + EX (SP),HL + RET + ; +LP_SC_TAB: DW LP_SET_32 ; 0 - спектрумовское окно 32x24 + DW LP_SET_64 ; 1 - текстовое окно 64x24 + DW LP_SET_40 ; 2 - текстовое окно 40x32 + DW LP_SET_80 ; 3 - текстовое окно 80x32 + DW LP_SET_32.X ; 4 - спектрумовское окно, HL - положение окна + DW LP_SET_64.X ; 5 - текстовое окно 64x24, HL - положение окна + DW LP_SET_40.X ; 6 - текстовое окно 40x32, HL - положение окна + DW LP_SET_80.X ; 7 - текстовое окно 80x32, HL - положение окна + DW PIC_SET_S1 ; 8 - графическое окно 0, HL - положение окна + DW PIC_SET_S2 ; 9 - графическое окно 1, HL - положение окна + ;DW LP_SET_MNU ; 10 - ;!TODO +.SIZE: EQU $-LP_SC_TAB - ADD A,L - LD L,A - LD A,H - ADC A,0 - LD H,A - LD A,(HL) - INC HL - LD H,(HL) - LD L,A - EX (SP),HL - RET +; !TODO +; LP_SET_MNU: +; LD IX,LP_SCR_MNU +; JP PIC_FN0_OpenWin -LP_SC_TAB: - DW LP_SET_32 - DW LP_SET_64 - DW LP_SET_40 - DW LP_SET_80 - DW LP_SET_32X - DW LP_SET_64X - DW LP_SET_40X - DW LP_SET_80X - DW PIC_SET_S1 - DW PIC_SET_S2 -; DW LP_SET_MNU +LP_SET_32: LD HL,#4104 +.X: LD IX,LP_SCR_32 + JP PIC_FN0_OpenWin -LP_SC_TAB_SIZE EQU $-LP_SC_TAB +LP_SET_64: LD HL,#4104 +.X: LD IX,LP_SCR_64 + JP PIC_FN0_OpenWin -;LP_SET_MNU: ; ????? -; SCF -; RET -; LD IX,LP_SCR_MNU -; JR LP_SET_MODE +LP_SET_40: LD HL,#4000 +.X: LD IX,LP_SCR_40 + JP PIC_FN0_OpenWin -LP_SET_32: - LD HL,4104H -LP_SET_32X: - LD IX,LP_SCR_32 - JR LP_SET_MODE +LP_SET_80: LD HL,#4000 +.X: LD IX,LP_SCR_80 + JP PIC_FN0_OpenWin -LP_SET_64: - LD HL,4104H -LP_SET_64X: - LD IX,LP_SCR_64 - JR LP_SET_MODE +PIC_SET_S1: LD IX,PIC_320X256_1 + JP PIC_FN0_OpenWin -LP_SET_40: - LD HL,4000H -LP_SET_40X: - LD IX,LP_SCR_40 - JR LP_SET_MODE +PIC_SET_S2: LD IX,PIC_320X256_2 + JP PIC_FN0_OpenWin +;------------------------------------------------------------------[#80] +; -LP_SET_80: - LD HL,4000H -LP_SET_80X: - LD IX,LP_SCR_80 - JR LP_SET_MODE +;------------------------------------------------------------------[#B1] +; !TODO +WIN_CLOSE: SCF + RET +;------------------------------------------------------------------[#B1] +; -PIC_SET_S1: - LD IX,PIC_320X256_1 - JR LP_SET_MODE - -PIC_SET_S2: - LD IX,PIC_320X256_2 - JR LP_SET_MODE - -;********************************************************** -; HL - место на экране по знакоместам (НЕ ИСПОЛЬЗУЕТСЯ) +; +;------------------------------------------------------------------[#B0] ; IX - описатель окна -WIN_OPEN: - LP_OPEN_PG - LD (SYS_PAGE.WIN_MAP_SC),IX ; карта окна -; PUSH HL - PUSH DE - LD HL,(SYS_PAGE.WIN_MAP_SC) - LD DE,SYS_PAGE.WIN_MAP_IX - LD BC,32 - LDIR - LD IX,SYS_PAGE.WIN_MAP_IX - POP DE -; POP HL +WIN_OPEN.SCR1: LD E,1 +; E - bit0 - номер экрана +WIN_OPEN: CALL .Prepare + LD L,(IX + Window_Variables.USER.PLACE_H) + LD H,(IX + Window_Variables.USER.PLACE_V) + JP WIN_OPEN_W1 + ; +.Prepare: CALL LP_OPEN_PG + PUSH HL + PUSH DE + ;LD (SYS_PAGE.WIN_MAP_SC),IX ; карта окна + ;LD HL,(SYS_PAGE.WIN_MAP_SC) + PUSH IX + POP HL + LD DE,WIN_ID_0 + LD BC,Window_UserVars + LDIR + LD IX,WIN_ID_0 + POP DE + POP HL + LD (IX + Window_Variables.MODE_E),E + RET +;------------------------------------------------------------------[#B0] +; - LD L,(IX+WIN_PLACE_H) - LD H,(IX+WIN_PLACE_V) - LD (IX+WIN_MODE_E),E - JR WIN_OPEN_W1 - - -; HL - PLACE -; IX - SIZE_HOR; IX+1 - SIZE_VER; IX+2,3; IX+4 - MODE; -; E - страница моды. -PIC_FN0: -LP_SET_MODE: - LD A,H - AND #10 ; переместить бит 4 в регистр E - XOR E - LD E,A - - LD A,L - AND #3F - ADD HL,HL - ADD HL,HL - LD L,A - RES 7,H - RES 6,H -; LD A,H -; AND 3FH -; LD H,A - -;LP_SET_MODE_M: - LP_OPEN_PG - LD (SYS_PAGE.WIN_MAP_SC),IX ; карта окна - PUSH HL - PUSH DE - LD HL,(SYS_PAGE.WIN_MAP_SC) - LD DE,SYS_PAGE.WIN_MAP_IX - LD BC,32 - LDIR - LD IX,SYS_PAGE.WIN_MAP_IX - POP DE - POP HL - - LD (IX+WIN_PLACE_H),L - LD (IX+WIN_PLACE_V),H - LD (IX+WIN_MODE_E),E - -WIN_OPEN_W1: - LD A,L - ADD A,A - INC A ; вычисление PORT_Y - BIT 4,E - JR NZ,LP_SET_NO_OR - OR #80 ; если вывод на второй экран -LP_SET_NO_OR: - LD (IX+WIN_H_BEG),A - LD D,A - LD A,(IX+WIN_SIZE_H) - ADD A,A - ADD A,D - LD (IX+WIN_H_END),A - - LD (SYS_PAGE.WIN_MODE_SC),DE ; место по горизонтали и страница моды - - LD A,H - AND #3F - ADD A,A - ADD A,A - LD L,A - LD H,#C3 - LD (SYS_PAGE.WIN_MODE_SH),HL ; место по вертикали с адресом - LD (IX+WIN_V_BEG),A - LD A,(IX+WIN_SIZE_V) - ADD A,A - ADD A,A - ADD A,L - LD (IX+WIN_V_END),A - - LD L,(IX+WIN_V_BEG) - LD H,#C3 - LD B,(IX+WIN_SIZE_V) ; размер по вертикали - - - LD (IX+WIN_WORK_1),0 - LD A,(IX+WIN_MODE) ; знакогенератор плюс режим - LD (IX+WIN_WORK_2),A - BIT 4,A - JR NZ,LP_SET_LOOP ; переход, если текстовый режим - - AND #F0 - LD C,A - LD A,(IX+WIN_GR_X) - RRCA - RRCA - RRCA - LD D,A - AND #0F - OR C - LD (IX+WIN_WORK_2),A - - LD A,D - AND #E0 - LD C,A - LD A,(IX+WIN_GR_Y) - AND #1F - OR C - RLCA - RLCA - RLCA - LD (IX+WIN_WORK_1),A - -LP_SET_LOOP: - LD D,(IX+WIN_H_BEG) ; D - начало строки (PORT_Y) - LD C,(IX+WIN_SIZE_H) ; размер по горизонтали - LD A,(IX+WIN_MODE) ; знакогенератор плюс режим - - PUSH BC - CALL LP_MODE_LINE - POP BC - INC L - INC L - INC L - INC L - DJNZ LP_SET_LOOP - - LD A,(IX+WIN_MODE_E) - AND 1 - OUT (RGMOD),A -; LD A,(IX+WIN_MODE) -; BIT 4,A - - LP_CLOSE_PG - -; RET Z - - CALL LP_INI_P - -; LD A,(SYS_PAGE.WIN_MODE_SC) -; OUT (RGMOD),A - - CALL LP_SIZE -; AND A - XOR A - RET - -WIN_CLOSE: - SCF - RET +; +;------------------------------------------------------------------[#A0] +; HL = X + Y*64 + #4000 + #1000*RGMOD. место на экране по знакоместам +; IX - описатель окна +; E - bit0: номер экрана +;LP_SET_MODE: +PIC_FN0_OpenWin: + ; финт для совместимости со старыми прогами, где передавались другие параметры + LD A,H + AND %00001'0000 ; переместить бит 4 в регистр E + XOR E + LD E,A + ; + LD A,L + AND #3F + ADD HL,HL + ADD HL,HL + LD L,A + ; + LD A,H + AND #3F + LD H,A + CALL WIN_OPEN.Prepare + LD (IX + Window_Variables.USER.PLACE_H),L + LD (IX + Window_Variables.USER.PLACE_V),H + ; +WIN_OPEN_W1: LD A,L + ADD A,A + INC A ; вычисление PORT_Y + BIT 4,E + JR NZ,.NO_OR + OR #80 ; если вывод на второй экран +.NO_OR: LD (IX+Window_Variables.H_BEG),A + LD D,A + LD A,(IX+Window_Variables.USER.SIZE_H) + ADD A,A + ADD A,D + LD (IX+Window_Variables.H_END),A + ;LD (SYS_PAGE.WIN_MODE_SC),DE ; место по горизонтали и страница моды + LD A,H + AND #3F + ADD A,A + ADD A,A + LD L,A + LD H,A + ;LD (SYS_PAGE.WIN_MODE_SH),HL ; место по вертикали с адресом + LD (IX+Window_Variables.V_BEG),A + LD A,(IX+Window_Variables.USER.SIZE_V) + ADD A,A + ADD A,A + ADD A,L + LD (IX+Window_Variables.V_END),A + ; + ;LD L,(IX+Window_Variables.V_BEG) + LD L,H + LD H,#C3 + LD B,(IX+Window_Variables.USER.SIZE_V) ; размер по вертикали + LD (IX+Window_Variables.WORK_1),0 + LD A,(IX+Window_Variables.USER.MODE) ; знакогенератор плюс режим + LD (IX+Window_Variables.WORK_2),A + BIT 4,A + JR NZ,.LOOP ; переход, если текстовый режим + ; + AND #F0 + LD C,A + LD A,(IX+Window_Variables.USER.GR_X) + RRCA + RRCA + RRCA + LD D,A + AND #0F + OR C + LD (IX+Window_Variables.WORK_2),A + ; + LD A,D + AND #E0 + LD C,A + LD A,(IX+Window_Variables.USER.GR_Y) + AND #1F + OR C + RLCA + RLCA + RLCA + LD (IX+Window_Variables.WORK_1),A +.LOOP: LD D,(IX+Window_Variables.H_BEG) ; D - начало строки (PORT_Y) + LD C,(IX+Window_Variables.USER.SIZE_H) ; размер по горизонтали + LD A,(IX+Window_Variables.USER.MODE) ; знакогенератор плюс режим + PUSH BC + CALL LP_MODE_LINE + POP BC + INC L + INC L + INC L + INC L + DJNZ .LOOP + ; + LD A,(IX+Window_Variables.MODE_E) + AND 1 + OUT (SCREEN_SWITCH),A + ;LD A,(IX+Window_Variables.MODE) + ;BIT 4,A + CALL LP_CLOSE_PG + ;RET Z + CALL LP_INI_P + ;LD A,(SYS_PAGE.WIN_MODE_SC) + ;OUT (RGMOD),A + ; нигде не было описано + CALL LP_SIZE + ; DE - размеры окна + ; + XOR A ;!TODO номер окна + RET +; ; Установка режима на линии -LP_MODE_LINE: - BIT 0,(IX+WIN_MODE_S) - JP NZ,LP_MODE_LINE2 ; идти на спектрум - BIT 4,A - JP Z,LP_MODE_LINE3 ; идти на графику! - DEC D - -; текстовый режим. - - EX AF,AF' - LD A,#50 - OUT (SLOT3),A - LD A,L ; вертикальное положение - CP 80H - JR NC,LP_EXIT_MODE - -LP_MODE_RECURSE: - LD A,D ; горизонтальное положение - AND 7FH - SUB 80 - JR C,LP_MODE_LL - SUB 48 - NEG - - LD E,A ; запомнить - ADD A,D - LD D,A ; новое положение - - LD A,E ; восстановить - RRA - AND 3FH - SUB C - JR NC,LP_EXIT_MODE - NEG - LD C,A ; новое значение C - JR LP_MODE_RECURSE - -LP_MODE_LL: - NEG - RRA - AND 3FH - CP C - JR NC,LP_MODE_LR - LD C,A -LP_MODE_LR: - EX AF,AF' - - INC D -LP_MD_LL1: - EX AF,AF' - LD A,D - OUT (RGADR),A - EX AF,AF' - LD (HL),A ; режим - INC D - EX AF,AF' - LD A,D - OUT (RGADR),A - EX AF,AF' - LD (HL),A ; режим - INC D - DEC C - JR NZ,LP_MD_LL1 - - EX AF,AF' -LP_EXIT_MODE: - LD A,SYS_PAGE - OUT (SLOT3),A - EX AF,AF' - - RET - -; Установка режима на линии -LP_MODE_LINE2: - -; Spectrum mode - - LD A,(IX+WIN_WORK_2) - LD B,(IX+WIN_WORK_1) - - DEC D - - EX AF,AF' - LD A,#50 - OUT (SLOT3),A - LD A,L ; вертикальное положение - CP 80H - JR NC,LP_EXIT_MODE2 - -LP_MODE_RECURSE2: - LD A,D ; горизонтальное положение - AND 7FH - SUB 80 - JR C,LP_MODE_LL2 - SUB 48 - NEG - - LD E,A ; запомнить - ADD A,D - LD D,A ; новое положение - - LD A,E ; восстановить - RRA - AND 3FH - SUB C - JR NC,LP_EXIT_MODE2 - NEG - LD C,A ; новое значение C - JR LP_MODE_RECURSE2 - -LP_MODE_LL2: - NEG - RRA - AND 3FH - CP C - JR NC,LP_MODE_LR2 - LD C,A -LP_MODE_LR2: - EX AF,AF' - - INC D -LP_MD_LL2: - EX AF,AF' - LD A,D - OUT (RGADR),A - EX AF,AF' - LD (HL),A ; режим - INC L - LD (HL),B - INC L - LD (HL),B - DEC L - DEC L - - INC D - BIT 4,A - JR NZ,lp_md_ll3x - INC B -lp_md_ll3x: - EX AF,AF' - LD A,D - OUT (RGADR),A - EX AF,AF' - LD (HL),A ; режим - INC L - LD (HL),B - INC L - LD (HL),B - DEC L - DEC L - - INC D - - INC B - JR NZ,LP_NO_ADD_40 - ADD A,40H -LP_NO_ADD_40: - - DEC C - JR NZ,LP_MD_LL2 - - EX AF,AF' -LP_EXIT_MODE2: - LD A,SYS_PAGE - OUT (SLOT3),A - EX AF,AF' - - LD (IX+WIN_WORK_1),B - LD (IX+WIN_WORK_2),A - - RET - - -LP_MODE_LINE3: ; Установка режима на линии - -; Grafic Mode - - LD A,(IX+WIN_WORK_1) - LD B,(IX+WIN_WORK_2) - - DEC D - - EX AF,AF' - LD A,#50 - OUT (SLOT3),A - LD A,L ; вертикальное положение - CP 80H - JR NC,LP_EXIT_MODE3 - -LP_MODE_RECURSE3: - LD A,D ; горизонтальное положение - AND 7FH - SUB 80 - JR C,LP_MODE_LL3 - SUB 48 - NEG - - LD E,A ; запомнить - ADD A,D - LD D,A ; новое положение - - LD A,E ; восстановить - RRA - AND 3FH - SUB C - JR NC,LP_EXIT_MODE3 - NEG - LD C,A ; новое значение C - JR LP_MODE_RECURSE3 - -LP_MODE_LL3: - NEG - RRA - AND 3FH - CP C - JR NC,LP_MODE_LR3 - LD C,A -LP_MODE_LR3: - EX AF,AF' - - INC D - - BIT 5,B - JR Z,LP_GR_640 - -LP_MD_LL3: - - EX AF,AF' - LD A,D - OUT (RGADR),A - EX AF,AF' - LD (HL),B ; режим - INC L - LD (HL),A ; режим 2 - INC L - LD (HL),0 ; режим 2 - DEC L - DEC L - - INC D - -; EX AF,AF' -; LD A,D -; OUT (RGADR),A -; EX AF,AF' -; LD (HL),B ; режим -; INC L -; LD (HL),A ; режим 2 -; DEC L - - INC D - - INC A - LD E,A - AND 7 - JR NZ,LP_NO_INC_B - LD A,E - SUB 8 - LD E,A - INC B -LP_NO_INC_B: - LD A,E - - DEC C - JR NZ,LP_MD_LL3 - -LP_640_RET: - EX AF,AF' -LP_EXIT_MODE3: - LD A,SYS_PAGE - OUT (SLOT3),A - EX AF,AF' - - LD A,(IX+WIN_WORK_1) - ADD A,8 - LD (IX+WIN_WORK_1),A - - RET - -LP_GR_640: - - EX AF,AF' - LD A,D - OUT (RGADR),A - EX AF,AF' - LD (HL),B ; режим 1 - INC L - LD (HL),A ; режим 2 - INC L - LD (HL),0 ; режим 3 - - INC D - - EX AF,AF' - LD A,D - OUT (RGADR),A - EX AF,AF' - LD (HL),0 ; режим 3 - DEC L - LD (HL),A ; режим 2 - DEC L - LD (HL),B ; режим 1 - - INC D - - INC A - LD E,A - AND 7 - JR NZ,LP_NO_INC_B6 - LD A,E - SUB 8 - LD E,A - INC B -LP_NO_INC_B6: - LD A,E - - DEC C - JR NZ,LP_GR_640 - JP LP_640_RET - - +LP_MODE_LINE: BIT 0,(IX+Window_Variables.USER.MODE_S) + JP NZ,.Spectrum ; идти на спектрум + BIT 4,A + JP Z,.Graphic ; идти на графику! + DEC D + ; текстовый режим. + EX AF,AF' + LD A,#50 + OUT (SLOT3),A + LD A,L ; вертикальное положение + CP #80 + JR NC,.Exit_txt + ; + CALL .RECURSE + JR NC,.Exit_txt + ; + CALL .CALC_C + ; +.loop_txt_scr: EX AF,AF' + LD A,D + OUT (PORT_Y),A + EX AF,AF' + LD (HL),A ; режим + INC D + EX AF,AF' + LD A,D + OUT (PORT_Y),A + EX AF,AF' + LD (HL),A ; режим + INC D + DEC C + JR NZ,.loop_txt_scr + ; + EX AF,AF' +.Exit_txt: LD A,SYS_PAGE + OUT (SLOT3),A + EX AF,AF' + RET + ; + ; Spectrum mode +.Spectrum: LD A,(IX+Window_Variables.WORK_2) + LD B,(IX+Window_Variables.WORK_1) + DEC D + EX AF,AF' + LD A,#50 + OUT (SLOT3),A + LD A,L ; вертикальное положение + CP #80 + JR NC,.Exit_zx_scr + ; + CALL .RECURSE + JR NC,.Exit_zx_scr + ; + CALL .CALC_C + ; +.loop_zx_scr: EX AF,AF' + LD A,D + OUT (PORT_Y),A + EX AF,AF' + LD (HL),A ; режим + ; + INC L + LD (HL),B + INC L + LD (HL),B + DEC L + DEC L + ; + INC D + BIT 4,A + JR NZ,.no_inc_B_zx + ; + INC B +.no_inc_B_zx: EX AF,AF' + LD A,D + OUT (PORT_Y),A + EX AF,AF' + ; + LD (HL),A ; режим + INC L + LD (HL),B + INC L + LD (HL),B + DEC L + DEC L + ; + INC D + INC B + JR NZ,.NO_ADD_40 + ; + ADD A,#40 +.NO_ADD_40: DEC C + JR NZ,.loop_zx_scr + EX AF,AF' + ; +.Exit_zx_scr: LD A,SYS_PAGE + OUT (SLOT3),A + EX AF,AF' + LD (IX+Window_Variables.WORK_1),B + LD (IX+Window_Variables.WORK_2),A + RET + ; + ; Graphic Mode +.Graphic: LD A,(IX+Window_Variables.WORK_1) + LD B,(IX+Window_Variables.WORK_2) + DEC D + EX AF,AF' + LD A,#50 + OUT (SLOT3),A + LD A,L ; вертикальное положение + CP #80 + JR NC,.Exit2_GFX_scr + ; + CALL .RECURSE + JR NC,.Exit2_GFX_scr + ; + CALL .CALC_C + ; + BIT 5,B + JR Z,.GFX_640_Loop + ; + ; GFX 320 +.loop_GFX_scr: EX AF,AF' + LD A,D + OUT (PORT_Y),A + EX AF,AF' + LD (HL),B ; mode 0 + INC L + LD (HL),A ; mode 1 + INC L + LD (HL),0 ; mode 2 + DEC L + DEC L + INC D + ; + ;EX AF,AF' + ;LD A,D + ;OUT (PORT_Y),A + ;EX AF,AF' + ;LD (HL),B ; режим + ;INC L + ;LD (HL),A ; режим 2 + ;DEC L + ; + INC D + INC A + LD E,A + AND 7 + JR NZ,.NO_INC_B_320 + ; + LD A,E + SUB 8 + LD E,A + INC B +.NO_INC_B_320: LD A,E + DEC C + JR NZ,.loop_GFX_scr + ; +.Exit_GFX_scr: EX AF,AF' +.Exit2_GFX_scr: LD A,SYS_PAGE + OUT (SLOT3),A + EX AF,AF' + LD A,(IX+Window_Variables.WORK_1) + ADD A,8 + LD (IX+Window_Variables.WORK_1),A + RET + ; + ; GFX 640 +.GFX_640_Loop: EX AF,AF' + LD A,D + OUT (PORT_Y),A + EX AF,AF' + LD (HL),B ; mode 0 + INC L + LD (HL),A ; mode 1 + INC L + LD (HL),0 ; mode 2 + ; + INC D + EX AF,AF' + LD A,D + OUT (PORT_Y),A + EX AF,AF' + LD (HL),0 ; mode 2 + DEC L + LD (HL),A ; mode 1 + DEC L + LD (HL),B ; mode 0 + ; + INC D + INC A + LD E,A + AND 7 + JR NZ,.NO_INC_B_640 + ; + LD A,E + SUB 8 + LD E,A + INC B +.NO_INC_B_640: LD A,E + DEC C + JR NZ,.GFX_640_Loop + JP .Exit_GFX_scr +; +.RECURSE: LD A,D ; горизонтальное положение + AND #7F + SUB 80 + RET C + SUB 48 + NEG + LD E,A ; запомнить + ADD A,D + LD D,A ; новое положение + LD A,E ; восстановить + RRA + AND #3F + SUB C + RET NC + NEG + LD C,A ; новое значение C + JR .RECURSE +; +.CALC_C: NEG + RRA + AND #3F + CP C + JR NC,.NoChangeC + LD C,A +.NoChangeC: EX AF,AF' + INC D + RET ;***************************************************************** -LP_SCROLL_UD: - DEC B - JR Z,LP_SCROLL_UP - DEC B - JR Z,LP_SCROLL_DN -; DEC B -; JR Z,LP_SCROLL_UP2 -; DEC B -; JR Z,LP_SCROLL_DN2 - SCF - RET +LP_SCROLL_UD: DEC B + JR Z,LP_SCROLL_UP + DEC B + JR Z,LP_SCROLL_DN + SCF + RET ; Вход: ; D - верхняя строка ( от 0 ) ; E - число скроллируемых строк -LP_SCROLL_UP: - DEC E - RET Z - - LP_OPEN_PG - LD B,E - LD E,0 - PUSH BC - CALL LP_AT_D - CALL LP_TAB_E ; вычислить переменные для строки - POP BC - -LP_SCROLL_L2: - EXX - PUSH HL - EXX - POP HL - - LD E,L - LD D,H - INC L - INC L - INC L - INC L - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_V_END) - CP L - JR C,LP_SCROLL_U_EXIT ; если конец, то выход - - PUSH BC - - LD A,L - EXX - LD L,A - EXX - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_SIZE_H) - - ADD A,A ; число байт в строке для переноса - ADD A,A - - LD C,A - LD B,0 - - LD A,#50 - OUT (SLOT3),A ; открыть страницу для переноса - EXX - LD A,D ; получить порт начала строки - EXX +LP_SCROLL_UP: DEC E + RET Z + CALL LP_OPEN_PG + ; + LD B,E + LD E,0 ; всю строку окна скроллим + CALL .RUN + JP LP_CLOSE_PG + ; + ; +.RUN: CALL LP_SET_CUR ; вычислить переменные для строки + PUSH IX + LD IX,(WIN_ID_0.USER.SIZE_H) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;!TODO + ; отличие от LP_SCROLL_DN + LD A,(WIN_ID_0.V_END) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + LD C,A + LD A,#50 + OUT (SLOT3),A ; открыть страницу для переноса + ; +.loop2: EXX + PUSH HL + EXX + POP HL + ; + LD E,L + LD D,H + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;!TODO + ; отличие от LP_SCROLL_DN + LD A,4 + ADD L + LD L,A + ; + LD A,C ; LD A,(WIN_ID_0.V_END) + CP L + JR C,.exit ; если конец, то выход + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + PUSH BC + LD A,L + EXX + LD L,A + EXX + ;XH + LD A,XL ; WIN_ID_0.USER.SIZE_H + ; LD A,SYS_PAGE + ; OUT (SLOT3),A + ; LD A,(WIN_ID_0.USER.SIZE_H) + ADD A,A ; число байт в строке для переноса + ADD A,A + LD C,A + LD B,0 + ; LD A,#50 + ; OUT (SLOT3),A ; открыть страницу для переноса + ; + EXX + LD A,D ; получить порт начала строки + EXX +.loop1: OUT (PORT_Y),A + INC A ; следующее значение порта + LDI + LDD + ; + OUT (PORT_Y),A + INC A ; следующее значение порта + LDI + LDD + JP PE,.loop1 + ; + POP BC + DJNZ .loop2 +.exit: POP IX + RET -LP_SCROLL_L1: - OUT (RGADR),A - INC A ; следующее значение порта - LDI - LDD - OUT (RGADR),A - INC A ; следующее значение порта - LDI - LDD - JP PE,LP_SCROLL_L1 - - LD A,SYS_PAGE - OUT (SLOT3),A - - POP BC - - DJNZ LP_SCROLL_L2 - -LP_SCROLL_U_EXIT: - - LP_CLOSE_PG - RET ; Вход : ; D - верхняя строка ( от 0 ) ; E - число скроллируемых строк -LP_SCROLL_DN: - DEC E - RET Z - - LP_OPEN_PG - LD B,E - LD E,0 - LD A,D - ADD A,B -; DEC A - LD D,A - PUSH BC - CALL LP_AT_D - CALL LP_TAB_E - POP BC - - -LP_SCROLL_D2: - - - EXX - PUSH HL - EXX - POP HL - - LD E,L - LD D,H - DEC L - DEC L - DEC L - DEC L - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_V_BEG) - CP L - JR Z,LP_SCROLL_U_CONT - JR NC,LP_SCROLL_U_EXIT ; если конец, то выход - -LP_SCROLL_U_CONT: - - PUSH BC - - LD A,L - EXX - LD L,A - EXX - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_SIZE_H) - ADD A,A - ADD A,A - LD C,A - LD B,0 - - LD A,#50 - OUT (SLOT3),A - EXX - LD A,D - EXX - - -LP_SCROLL_D1: - OUT (RGADR),A - INC A - LDI - LDD - OUT (RGADR),A - INC A - LDI - LDD - JP PE,LP_SCROLL_D1 - - LD A,SYS_PAGE - OUT (SLOT3),A - - POP BC - DJNZ LP_SCROLL_D2 - -LP_SCROLL_D_EXIT: - - LP_CLOSE_PG - RET +LP_SCROLL_DN: DEC E + RET Z + CALL LP_OPEN_PG + ; + LD B,E + LD E,0 + LD A,D + ADD A,B + LD D,A + CALL .RUN +.EXIT: JP LP_CLOSE_PG + ; + ; +.RUN: CALL LP_SET_CUR + PUSH IX + LD IX,(WIN_ID_0.USER.SIZE_H) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;!TODO + ; отличие от LP_SCROLL_UD + LD A,(WIN_ID_0.V_BEG) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + LD C,A + LD A,#50 + OUT (SLOT3),A ; открыть страницу для переноса + ; +.loop2: EXX + PUSH HL + EXX + POP HL + ; + LD E,L + LD D,H + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;!TODO + ; отличие от LP_SCROLL_UD + LD A,L + SUB 4 + LD L,A + ; + LD A,C + CP L ; .CONT: L >= A + JR Z,.CONT + JR NC,.exit ; если конец, то выход + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +.CONT: PUSH BC + LD A,L + EXX + LD L,A + EXX + ; + LD A,XL ; WIN_ID_0.USER.SIZE_H + ; LD A,SYS_PAGE + ; OUT (SLOT3),A + ; LD A,(WIN_ID_0.USER.SIZE_H) + ADD A,A ; число байт в строке для переноса + ADD A,A + LD C,A + LD B,0 + ; LD A,#50 + ; OUT (SLOT3),A ; открыть страницу для переноса + ; + EXX + LD A,D ; получить порт начала строки + EXX +.loop1: OUT (PORT_Y),A + INC A ; следующее значение порта + LDI + LDD + ; + OUT (PORT_Y),A + INC A ; следующее значение порта + LDI + LDD + JP PE,.loop1 + ; + POP BC + DJNZ .loop2 +.exit: POP IX + RET ; DE - место символа в окне ; А - номер окна ; выход: HL - символ/атрибут B - знакогенератор -WIN_GET_SYM: - AND A - SCF - RET NZ - - CALL LP_BEG_P - - CALL LP_AT_D - CALL LP_TAB_E - - LD A,#50 - OUT (SLOT3),A - - EXX - - LD A,D - OUT (RGADR),A - - LD A,(HL) - EXX - LD L,A - EXX - INC L - LD A,(HL) - EXX - LD H,A - EXX - DEC L - DEC L - LD A,(HL) - EXX - LD B,A - EXX - INC L - - EXX - - LD A,SYS_PAGE - OUT (SLOT3),A - - CALL LP_END_P - RET +WIN_GET_SYM: AND A + SCF + RET NZ + ; + CALL LP_BEG_P + CALL LP_SET_CUR + LD A,#50 + OUT (SLOT3),A + ; + EXX + LD A,D + OUT (PORT_Y),A + LD A,(HL) + EXX + LD L,A + EXX + INC L + LD A,(HL) + EXX + LD H,A + EXX + DEC L + DEC L + LD A,(HL) + INC L + EXX + LD B,A + JP LP_END_P + ;RET ; DE - место символа в окне ; А - номер окна -; HL - символ/атрибут B - знакогенератор -WIN_PUT_SYM: - AND A - SCF - RET NZ +; HL - символ/атрибут +; B - знакогенератор +WIN_PUT_SYM: AND A + SCF + RET NZ + ; + CALL LP_BEG_P + CALL LP_SET_CUR + LD A,#50 + OUT (SLOT3),A + ; + EXX + LD A,D + OUT (PORT_Y),A + EXX + ; [ ] 31/03/2025 если B=0, то кладём только символ + ; если B=1, то кладём символ с атрибутом + ; символ + ; LD A,L + ; EXX + ; LD (HL),A + ; INC L + ; EXX + ; ; атрибут + ; LD A,H + ; EXX + ; LD (HL),A + ; DEC L + ; DEC L + ; EXX + ; ; шрифт + ; LD A,B + ; EXX + ; LD (HL),A + ; INC L + ; EXX + ; JP LP_END_P + ; + ; шрифт + LD A,B + OR A + JR Z,.onlySymbol + DEC B + JR Z,.noChangeZG + ; + EXX + DEC L + LD (HL),A + INC L + EXX + ; атрибут +.noChangeZG: LD A,H + EXX + INC L + LD (HL),A + DEC L + EXX + ; символ +.onlySymbol: LD A,L + EXX + LD (HL),A + EXX + JP LP_END_P - CALL LP_BEG_P - CALL LP_AT_D - CALL LP_TAB_E - - LD A,#50 - OUT (SLOT3),A - - EXX - - LD A,D - OUT (RGADR),A - - EXX - LD A,L - EXX - - LD (HL),A - INC L - - EXX - LD A,H - EXX - - LD (HL),A - DEC L - DEC L - - EXX - LD A,B - EXX - - LD (HL),A - INC L - - EXX - - LD A,SYS_PAGE - OUT (SLOT3),A - - CALL LP_END_P - RET ; HL - размер окна ; DE - положение окна ; A - номер окна ; IX - новое положение окна -WIN_MOVE: - AND A - SCF - RET NZ - PUSH IX - PUSH HL - LD B,#FF - LD IX,#C000 - CALL WIN_COPY_WIN1 - POP HL - POP DE - LD B,0FFH - LD IX,0C000H - CALL WIN_REST_WIN1 - AND A - RET +WIN_MOVE: AND A + SCF + RET NZ + PUSH IX + PUSH HL + LD B,SHARED_PAGE + LD IX,SLOT3.MEM_ADDR + CALL WIN_COPY_WIN1 + POP HL + POP DE + LD B,SHARED_PAGE + LD IX,SLOT3.MEM_ADDR + CALL WIN_RESTORE.Start + AND A + RET ; HL - размер сохраняемого окна ; DE - место сохраняемого окна ; IX - адрес сохраняемого окна, в странице 4000h ; А - номер окна, B - страница -WIN_COPY: - AND A - SCF - RET NZ -WIN_COPY_WIN1: - CALL LP_BEG_P - - IN A,(SLOT1) - PUSH AF - - CALL LP_AT_D - CALL LP_TAB_E - - LD (SYS_PAGE.SYS_WORK1),SP - - LD A,B - OUT (SLOT3),A - LD A,#50 - OUT (SLOT1),A - - EXX - RES 7,H - LD C,D - EXX - -LP_COPY_L2: - LD A,L - EXX - LD B,A - - ADD A,A - ADD A,XL - LD XL,A - JR NC,LP_NO_INC_IX1 - INC XH -LP_NO_INC_IX1: - - LD SP,IX - - LD A,C - ADD A,B - -LP_COPY_L1: - DEC A - OUT (RGADR),A - LD E,(HL) - INC L - LD D,(HL) - DEC L - PUSH DE - DJNZ LP_COPY_L1 - - INC HL - INC HL - INC HL - INC HL - - EXX - - DEC H - JR NZ,LP_COPY_L2 - - LD A,SYS_PAGE - OUT (SLOT3),A - LD SP,(SYS_PAGE.SYS_WORK1) - - POP AF - OUT (SLOT1),A - - CALL LP_END_P2 - AND A - RET - +WIN_COPY: AND A + SCF + RET NZ +WIN_COPY_WIN1: CALL LP_BEG_P + IN A,(SLOT1) + PUSH AF + ; + CALL LP_SET_CUR + LD (SYS_PAGE.SYS_WORK1),SP + LD A,B + OUT (SLOT3),A + LD A,#50 + OUT (SLOT1),A + ; + EXX + RES 7,H + LD C,D + EXX + ; +.COPY_loop2: LD A,L + EXX + LD B,A + ADD A,A + ADD A,XL + LD XL,A + JR NC,.NO_INC_XH + ; + INC XH +.NO_INC_XH: LD SP,IX + LD A,C + ADD A,B +.COPY_loop: DEC A + OUT (PORT_Y),A + LD E,(HL) + INC L + LD D,(HL) + DEC L + PUSH DE + DJNZ .COPY_loop + ; + INC HL + INC HL + INC HL + INC HL + EXX + DEC H + JR NZ,.COPY_loop2 + ; + LD A,SYS_PAGE + OUT (SLOT3),A + LD SP,(SYS_PAGE.SYS_WORK1) + ; + POP AF + OUT (SLOT1),A + JP LP_END_P.short +; ; HL - размер сохраняемого окна ; DE - место сохраняемого окна ; IX - адрес данных восстанавливаемого окна -WIN_RESTORE: - AND A - SCF - RET NZ -WIN_REST_WIN1: - CALL LP_BEG_P +WIN_RESTORE: AND A + SCF + RET NZ +.Start: + CALL LP_BEG_P + ; + IN A,(SLOT1) + PUSH AF + ; + CALL LP_SET_CUR + ; + LD (SYS_PAGE.SYS_WORK1),SP + LD SP,IX + ; + LD A,B + OUT (SLOT3),A + LD A,#50 + OUT (SLOT1),A + ; + EXX + RES 7,H + LD C,D + EXX +.L2: LD A,L + EXX + LD B,A + LD A,C +.L1: OUT (PORT_Y),A + INC A + POP DE + LD (HL),E + INC L + LD (HL),D + DEC L + DJNZ .L1 + ; + INC HL + INC HL + INC HL + INC HL + EXX + DEC H + JR NZ,.L2 - IN A,(SLOT1) - PUSH AF + LD A,SYS_PAGE + OUT (SLOT3),A - CALL LP_AT_D - CALL LP_TAB_E + LD SP,(SYS_PAGE.SYS_WORK1) - LD (SYS_PAGE.SYS_WORK1),SP - LD SP,IX - - LD A,B - OUT (SLOT3),A - LD A,#50 - OUT (SLOT1),A - - EXX - RES 7,H - LD C,D - EXX - -LP_REST_L2: - - LD A,L - EXX - LD B,A - - LD A,C - -LP_REST_L1: - - OUT (RGADR),A - INC A - POP DE - LD (HL),E - INC L - LD (HL),D - DEC L - - DJNZ LP_REST_L1 - - INC HL - INC HL - INC HL - INC HL - - EXX - DEC H - - JR NZ,LP_REST_L2 - - LD A,SYS_PAGE - OUT (SLOT3),A - - LD SP,(SYS_PAGE.SYS_WORK1) - - POP AF - OUT (SLOT1),A - - CALL LP_END_P2 - AND A - RET + POP AF + OUT (SLOT1),A + JP LP_END_P.short +;======================================================================; + +; Печать с управляющими символами в консоль +;------------------------------------------------------------------[#E0] +LP_PR_LINE_DIR: + ;>------------------------------------------------[BELL] +.BELL: EXX + PUSH HL + PUSH BC + ; + LD DE,1200 + LD HL,4 + CALL BEEP + ; + POP BC + POP HL + EXX + JR .loop + ;-------------------------------------------------[BELL] + + ;>------------------------------------------------[Backspace] +.BACK: LD A,(WIN_ID_0.H_BEG) + CP D + JR Z,.loop + INC B + DEC D + CORRECT_SCR_40_BACKWARD + JP .loop + ;>------------------------------------------------[Backspace] + ; +.EXIT_SpecSymbol: + DEC HL + CALL LP_END_P + POP IX + SCF + RET +; +.EXIT: POP IX + JP LP_END_P +;;;;;;;;;;;;;;;;; +; A - атрибуты выводимого символа если CF' +; CF - XY-mode +; DE - место символа в окне, если CF=1 +; HL - адрес с выводимой строкой +; B - цвет консоли (используется при скролле и очистке окна) +; IY - два спец.символа для выхода с CF=1. Должны быть равны B, если не нужны +; CF' - выводить символ с атрибутами +;;;;;;;;;;;;;;;;; +.START: PUSH IX + LD XL,A ; атрибуты выводимого символа + ; + EX AF,AF' + PUSH AF ; attr-mode + EX AF,AF' + ; + IN A,(SLOT3) + LD C,A + CALL LP_BEG_P + CALL C,LP_SET_CUR ; mode for DE + POP AF ; attr-mode + LD A,B + ; далее рег B свободен, можно задействовать + LD (SYS_PAGE.SYS_WORK2),A ; цвет консоли + EXX + RL C ; C' - attr-mode. выводить атрибут +.loop: LD A,D + OUT (PORT_Y),A + EXX + LD A,C + OUT (SLOT3),A + ; + LD A,(HL) + LD XH,A + INC HL + AND A + JR Z,.EXIT + CP YH + JR Z,.EXIT_SpecSymbol + CP YL + JR Z,.EXIT_SpecSymbol + ; + EXX + ; печатаемые символы + CP 14 + JR NC,.print + CP 7 + JR C,.print + ; управляющие символы + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,XH + ; + SUB 7 + JR Z,.BELL ; A = 07 "BELL" + DEC A + JR Z,.BACK ; A = 08 "Backspace" + DEC A + JR Z,.TAB ; A = 09 "TAB" + DEC A + JR Z,.LineFeed ; А = 10 "Line Feed" + DEC A + JR Z,.VertTab ; А = 11 "Vertical Tabulation" + DEC A + JR Z,.CLS ; А = 12 "Form feed" - разрыв страницы, начало нового листа, может работать как VT + ;DEC A + ;JR Z,.CR ; А = 13 "Carriage Return" + ;>------------------------------------------------[CR] +.CR: LD A,(WIN_ID_0.H_BEG) + LD D,A + LD A,(WIN_ID_0.SIZE_REL) + LD B,A + JP .loop + ;-------------------------------------------------[CR] + + ;>------------------------------------------------[PRINT] +.print: LD A,#50 + OUT (SLOT3),A + LD A,XH + LD (HL),A + ; выводить атрибут + RR C ; C' - attr flag + JR NC,.NoPutAttr + ; + INC L + LD A,XL + LD (HL),A + DEC L +.NoPutAttr: RL C ; C' - attr flag + INC D +.next_full: CORRECT_SCR_40_FORWARD +.next: DJNZ .loop + CALL LP_NEXT_HL_DIR + JP .loop + ;-------------------------------------------------[PRINT] + + ;>------------------------------------------------[TAB] +.TAB: LD A,(WIN_ID_0.H_BEG) + SUB D + NEG + AND %0000'0111 + NEG + ADD A,8 + CP B + JR C,.keep_A + ; + LD A,B + DEC A +.keep_A: ;NEG + PUSH BC ; save C' - attr flag + LD C,A + EX AF,AF' + JR C,.LLL + ; + EX AF,AF' + ADD A,A ; режим 40 + EX AF,AF' +.LLL: EX AF,AF' + ; +.tabNxt: ADD A,D + LD D,A + LD A,B + SUB C ; set XL + POP BC ; restore C' - attr flag + LD B,A + JP .loop + ; + ;-------------------------------------------------[TAB] + + ;>------------------------------------------------[Line Feed] +.VertTab: ; +.LineFeed: LD A,4 ;!HARDCODE длина одного описателя квадратика + ADD L + LD L,A + ; + LD A,(WIN_ID_0.V_END) + CP L + CALL C,LP_NEXT_HL_DIR.end_line + JP .loop + ;-------------------------------------------------[Line Feed] + + ;>------------------------------------------------[Form feed] +.CLS: PUSH BC ; C' - attr flag + EXX + PUSH BC + PUSH HL + PUSH DE + ; + LD A,(SYS_PAGE.SYS_WORK2) ; цвет консоли + LD B,A + LD DE,0 + LD HL,(WIN_ID_0.USER.SIZE_H) ; get WIN XY + LD A,(WIN_ID_0.SIZE_REL) + LD L,A + LD C," " + CALL LP_CLS_WIN.CLS + ; + POP DE + POP HL + POP BC + EXX + LD A,B + POP BC ; C' - attr flag + LD B,A + JP .loop + ;-------------------------------------------------[Form feed] +;------------------------------------------------------------------[#E0] +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +LP_NEXT_HL_DIR: LD A,SYS_PAGE + OUT (SLOT3),A + LD A,4 ;!HARDCODE длина одного описателя квадратика + ADD L + LD L,A + LD A,(WIN_ID_0.V_END) + CP L + CALL C,.end_line + ; +.no_end_line: LD A,(WIN_ID_0.H_BEG) + LD D,A + LD A,(WIN_ID_0.SIZE_REL) + LD B,A + RET + ; +.end_line: LD A,L + SUB 4 ;!HARDCODE длина одного описателя квадратика + LD L,A + PUSH HL + DEC L + PUSH BC + PUSH DE + EXX + PUSH BC + PUSH HL + PUSH DE + LD A,(WIN_ID_0.V_BEG) + LD D,A + LD A,(WIN_ID_0.USER.SIZE_V) + LD B,A + LD E,0 ; всю строку окна скроллим + CALL LP_SCROLL_UP.RUN + ; + LD A,SYS_PAGE + OUT (SLOT3),A + LD C," " + LD A,(SYS_PAGE.SYS_WORK2) ; цвет консоли + LD B,A + LD A,(WIN_ID_0.USER.SIZE_V) + DEC A + LD D,A + LD E,0 + LD HL,(WIN_ID_0.SIZE_REL) + LD H,1 + LD C," " + CALL LP_CLS_WIN.CLS + ; + POP DE + POP HL + POP BC + EXX + POP DE + POP BC + POP HL + RET +; +; LD HL,(WIN_ID_0.V_END) +; DEC L +; DEC L +; DEC L +; LD H,#C3 +; ; +; LD A,(WIN_ID_0.H_BEG) +; LD D,A +; ; +; LD A,#50 +; OUT (SLOT3),A +; ; +; EXX +; LD A,(WIN_ID_0.SIZE_REL) +; LD B,A +; .loop_cl_line: EXX +; LD A,D +; OUT (PORT_Y),A +; LD (HL),C +; INC D +; CORRECT_SCR_40_FORWARD +; EXX +; DJNZ .loop_cl_line +; LD A,SYS_PAGE +; OUT (SLOT3),A +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + + +LP_OPEN_PG: IN A,(SLOT3) + LD C,A + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD A,C + LD (SYS_PAGE.COPY_SLOT3),A + IN A,(PORT_Y) + LD (SYS_PAGE.COPY_RGADR),A + RET +; + +; не должна влиять на флаги и трогать регистры кроме A +LP_CLOSE_PG: LD A,(SYS_PAGE.COPY_RGADR) + OUT (PORT_Y),A + LD A,(SYS_PAGE.COPY_SLOT3) + OUT (SLOT3),A + RET + +/* + +;!TODO старая LP_SET_MODE - расковырять старый LP_SCR_MNU + + MODULE EXPERIMENT + +; byte 1 +; 0..4 - VIDEO_PAGE +; 5 - mode 42/84 ; 0 - 42,1 - 84 +; 6 - next line +; 7 - end table +; byte 2 - number of places +; byte 3..4 - adress places/ +; 4000-5FFF - Spectrum modes/ C000-FFFF - Graf mode +; + MACRO LP_S PG,XX,ADR + DB PG,XX + DW ADR + ENDM + + MACRO LP_OPEN_PG + IN A,(SLOT3) + LD C,A + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD A,C + LD (SYS_PAGE.COPY_SLOT3),A + IN A,(PORT_Y) + LD (SYS_PAGE.COPY_RGADR),A + ENDM ; + + MACRO LP_CLOSE_PG + LD A,(SYS_PAGE.COPY_RGADR) + OUT (PORT_Y),A + LD A,(SYS_PAGE.COPY_SLOT3) + OUT (SLOT3),A + ENDM ; +;--------------------------------------- +GR_BIT_END: EQU 7 + +S_BIT_END: EQU 7 +S_BIT_LIN: EQU 6 +S_BIT_MOD: EQU 5 + +BIT_1440: EQU 1 +BIT_MASK_1440: EQU %00000010 + +MODE_PAGE: EQU #FC +;--------------------------------------- + ;DS (($/4)*4+4-$) + ALIGN 4 + + +LP_SCR_MNU: + LP_S #40,14,#40E7 + LP_S #40,14,#4807 + LP_S #40,14,#4827 + LP_S #40,14,#4847 + LP_S #40,14,#4867 + LP_S #40,14,#4887 + LP_S #40,14,#48A7 + LP_S #40,14,#48C7 + LP_S #40,14,#48E7 + DB #FF,0,0,0 + +; LP_SCR_80: +; DB 40,32,0,0,#1B,0,0,0 +; DB 0,0,0,0,0,0,0,0 + +; LP_S %0110'0010,40,#4000 +; LP_S %0110'0010,40,#4028 +; LP_S %0110'0010,40,#4050 +; LP_S %0110'0010,40,#4078 +; LP_S %0110'0010,40,#40A0 +; LP_S %0110'0010,40,#40C8 +; +; LP_S %0110'0010,40,#4800 +; LP_S %0110'0010,40,#4828 +; LP_S %0110'0010,40,#4850 +; LP_S %0110'0010,40,#4878 +; LP_S %0110'0010,40,#48A0 +; LP_S %0110'0010,40,#48C8 +; +; LP_S %0110'0010,40,#5000 +; LP_S %0110'0010,40,#5028 +; LP_S %0110'0010,40,#5050 +; LP_S %0110'0010,40,#5078 +; LP_S %0110'0010,40,#50A0 +; LP_S %0110'0010,40,#50C8 +; +; LP_S %0110'0100,40,#4000 +; LP_S %0110'0100,40,#4028 +; LP_S %0110'0100,40,#4050 +; LP_S %0110'0100,40,#4078 +; LP_S %0110'0100,40,#40A0 +; LP_S %0110'0100,40,#40C8 +; +; LP_S %0110'0100,40,#4800 +; LP_S %0110'0100,40,#4828 +; LP_S %0110'0100,40,#4850 +; LP_S %0110'0100,40,#4878 +; LP_S %0110'0100,40,#48A0 +; LP_S %0110'0100,40,#48C8 +; +; LP_S %0110'0100,40,#5000 +; LP_S %0110'0100,40,#5028 +; +; DEFB #FF,0,0,0 +; +; LP_SCR_40: +; DB 40,32,0,0,7BH,0,0,0 +; DB 0,0,0,0,0,0,0,0 +; +; LP_S 01000100B,40,5050H +; LP_S 01000100B,40,5078H +; LP_S 01000100B,40,50A0H +; LP_S 01000100B,40,50C8H +; +; LP_S 01000110B,40,4000H +; LP_S 01000110B,40,4028H +; LP_S 01000110B,40,4050H +; LP_S 01000110B,40,4078H +; LP_S 01000110B,40,40A0H +; LP_S 01000110B,40,40C8H +; +; LP_S 01000110B,40,4800H +; LP_S 01000110B,40,4828H +; LP_S 01000110B,40,4850H +; LP_S 01000110B,40,4878H +; LP_S 01000110B,40,48A0H +; LP_S 01000110B,40,48C8H +; +; LP_S 01000110B,40,5000H +; LP_S 01000110B,40,5028H +; LP_S 01000110B,40,5050H +; LP_S 01000110B,40,5078H +; LP_S 01000110B,40,50A0H +; LP_S 01000110B,40,50C8H +; +; LP_S 01001000B,40,4000H +; LP_S 01001000B,40,4028H +; LP_S 01001000B,40,4050H +; LP_S 01001000B,40,4078H +; LP_S 01001000B,40,40A0H +; LP_S 01001000B,40,40C8H +; +; LP_S 01001000B,40,4800H +; LP_S 01001000B,40,4828H +; LP_S 01001000B,40,4850H +; LP_S 01001000B,40,4878H +; +; DEFB 0FFh,0,0,0 +; +; LP_SCR_32: +; DB 32,24,4,4,30H,1,0,0 +; DB 0,0,0,0,0,0,0,0 +; +; LP_S 040h,32,04000H +; LP_S 040h,32,04020H +; LP_S 040h,32,04040H +; LP_S 040h,32,04060H +; LP_S 040h,32,04080H +; LP_S 040h,32,040A0H +; LP_S 040h,32,040C0H +; LP_S 040h,32,040E0H +; +; LP_S 040h,32,04800H +; LP_S 040h,32,04820H +; LP_S 040h,32,04840H +; LP_S 040h,32,04860H +; LP_S 040h,32,04880H +; LP_S 040h,32,048A0H +; LP_S 040h,32,048C0H +; LP_S 040h,32,048E0H +; +; LP_S 040h,32,05000H +; LP_S 040h,32,05020H +; LP_S 040h,32,05040H +; LP_S 040h,32,05060H +; LP_S 040h,32,05080H +; LP_S 040h,32,050A0H +; LP_S 040h,32,050C0H +; LP_S 040h,32,050E0H +; +; LP_S 0FFh,0,0 +; +; LP_SCR_64: +; DB 32,24,4,4,9BH,0,0,0 +; DB 0,0,0,0,0,0,0,0 +; +; LP_S 06Ah,32,04000H +; LP_S 06Ah,32,04020H +; LP_S 06Ah,32,04040H +; LP_S 06Ah,32,04060H +; LP_S 06Ah,32,04080H +; LP_S 06Ah,32,040A0H +; LP_S 06Ah,32,040C0H +; LP_S 06Ah,32,040E0H +; +; LP_S 06Ah,32,04800H +; LP_S 06Ah,32,04820H +; LP_S 06Ah,32,04840H +; LP_S 06Ah,32,04860H +; LP_S 06Ah,32,04880H +; LP_S 06Ah,32,048A0H +; LP_S 06Ah,32,048C0H +; LP_S 06Ah,32,048E0H +; +; LP_S 06Ah,32,05000H +; LP_S 06Ah,32,05020H +; LP_S 06Ah,32,05040H +; LP_S 06Ah,32,05060H +; LP_S 06Ah,32,05080H +; LP_S 06Ah,32,050A0H +; LP_S 06Ah,32,050C0H +; LP_S 06Ah,32,050E0H +; +; LP_S 0FFh,0,0 + + +@LP_SET_MNU: LD IX,LP_SCR_MNU + ;JR LP_SET_MODE +; HL - смещение от начала экрана +; = hor_sh + vert_sh * 64 + 4000H +; IX - экранная таблица +LP_SET_MODE: LP_OPEN_PG + LD (SYS_PAGE.WIN_MAP_SC),IX + LD (SYS_PAGE.WIN_MODE_SH),HL + LD (SYS_PAGE.WIN_MODE_SC),DE + LD HL,(SYS_PAGE.WIN_MAP_SC) + LD DE,SYS_PAGE.WIN_MAP_IX +.LP_SET_COPY: LD BC,4 + LDIR + BIT S_BIT_END,(HL) + JR Z,.LP_SET_COPY + LD BC,4 + LDIR + LD HL,SYS_PAGE.WIN_MAP_IX + LD (SYS_PAGE.WIN_MAP_SC),HL +.LP_SET_MODE_INT: + LD IX,(SYS_PAGE.WIN_MAP_SC) + LD HL,(SYS_PAGE.WIN_MODE_SH) + CALL LP_SET_MODE1 + LD DE,(SYS_PAGE.WIN_MODE_SC) + LP_CLOSE_PG + PUSH DE + CALL LP_INI_P + POP DE + LD A,E + OUT (RGMOD),A + CALL LP_SIZE + RET + +LP_SET_MODE1: AND A + BIT S_BIT_END,(IX) ; проверка конца данных + RET NZ + + PUSH HL + + IN A,(RGADR) + PUSH AF + + LD A,H + CP #48 + CCF + LD A,#16 + ADC A,0 + OUT (RGADR),A + +.LP_SET_LOOP: CALL LP_MODE_LINE + + INC IX + INC IX + INC IX + INC IX + BIT S_BIT_LIN,(IX) + JR Z,.LP_SET_LOOP + + POP AF + OUT (RGADR),A + + POP HL + + LD BC,#40 + ADD HL,BC + JR LP_SET_MODE1 + +;******************************************************** +; Вычисление значения MODE из экранной таблицы. +; IX - текущее положение в таблице. +LP_MODE_LINE: BIT 3,H + RET NZ + + IN A,(SLOT1) + LD (SYS_PAGE.SYS_WORK1),A + + IN A,(RGADR) + AND 1 + OR MODE_PAGE + OUT (SLOT1),A + + LD A,(IX) + LD B,A + RRCA + AND #0F + LD C,A + LD A,B + AND #20 + XOR #30 + OR C + LD C,A + LD A,(IX+3) + RLC A + RLC A + RLC A + AND #C0 + OR C + LD D,A ; Первый байт MODE + LD E,(IX+2) ; Второй байт.. + + LD B,(IX+1) ; число знакомест + + LD A,L + AND #3F + SUB 40 + JR NC,.LP_NO_SET_MD + NEG + CP B + JR NC,.LP_MD_NO_B + LD B,A +.LP_MD_NO_B: + +.LP_MD_LOOP: SET 4,H + LD (HL),E + RES 4,H + LD (HL),D + + INC E + INC L + DJNZ .LP_MD_LOOP + +.LP_MD_END: LD A,(SYS_PAGE.SYS_WORK1) + OUT (SLOT1),A + RET + +.LP_NO_SET_MD: LD A,C + +.LP_MD_LOOP2: INC E + INC L + BIT 5,H + JR Z,.LP_MD_LOOP + DJNZ .LP_MD_LOOP2 + JR .LP_MD_END + + +; вычисление нового места +LP_TAB_HL: LD HL,(SYS_PAGE.WIN_TAB_SC) ; загрузить текущее положение в таблице SCR + LD A,(HL) ; загрузить флаги таблицы + BIT S_BIT_END,A ; флаг конца + JR Z,LP_TAB_H1 ; если 0 - не конец +LP_TAB_H2: LD HL,(SYS_PAGE.WIN_MAP_SC) ; загрузить начальное положение в таблице SCR +LP_TAB_H3: LD A,(HL) ; и новые флаги +LP_TAB_H1: CALL .LP_PG1 ; переключить страницу + INC HL ; (HL) - новое число символов + BIT S_BIT_MOD,A ; бит 42/84 + LD A,(HL) ; загрузить число символов + JR Z,.LP_NO_MUL ; если 84, то не нужно умножение на 2 + ADD A,A ; A=A*2 +.LP_NO_MUL: LD B,A ; число символов в B + INC HL ; загрузка нового HL + LD A,(HL) + INC HL + INC HL + LD (SYS_PAGE.WIN_TAB_SC),HL ; с сохранением следующего положения в таблице SCR + DEC HL + LD H,(HL) ; положение на экране + LD L,A + + LD A,H + RRCA ; вычислить положение + RRCA ; аттрибута + RRCA + AND 3 + OR H + OR #18 + LD C,A + RET + +.LP_PG1: AND #1F ; переключать только страницы ОЗУ Spectrum mode + OUT (RGADR),A + LD E,(HL) ; значение битов и флагов + + BIT S_BIT_MOD,E ; бит 42/84 + JR Z,.LP_N_84 ; если 42 то не устанавливать CF + SCF ; 84 mode +.LP_N_84: EX AF,AF' ; спрятать флаги и значение для вывода в порт + LD A,E ; в A должен быть байт с флагами + RET + +; program init registers +; for low printer & save +LP_INI_P: EXX + LP_OPEN_PG + LD DE,(SYS_PAGE.WIN_ZG) + LD B,0 + CALL LP_TAB_H2 + EXX +; program save registers +; for low printer +LP_END_P: EX AF,AF' + EXX + RLA + LD E,A + LD (SYS_PAGE.WIN_SAV_HL),HL + LD (SYS_PAGE.WIN_SAV_DE),DE + LD (SYS_PAGE.WIN_SAV_BC),BC + LP_CLOSE_PG + EXX + EX AF,AF' + RET + + +; определение size +LP_SIZE: LP_OPEN_PG + EXX + XOR A + LD HL,(SYS_PAGE.WIN_MAP_SC) ; начало карты scr + CALL .LP_LN2 ; сканировать до + EXX ; конца + NEG ; получить число + LD D,A ; строк в D + LD E,0 + EXX + ;LD A,3 ; число символов + LD HL,(SYS_PAGE.WIN_MAP_SC) ; по 3-йе строке + ;CALL LP_LN2 ; настройка +.LOOP: CALL LP_TAB_H3 ; данные + LD A,B + EXX + ADD A,E + LD E,A + EXX + LD HL,(SYS_PAGE.WIN_TAB_SC) ; данные экрана + BIT S_BIT_LIN,(HL) + JR Z,.LOOP + ;BIT S_BIT_MOD,(HL) + EXX + ;XOR A + ;OUT (RGADR),A + LP_CLOSE_PG + RET + ; +.LP_LN0: DEC A + RET Z +.LP_LN1: INC HL + INC HL + INC HL + INC HL +.LP_LN2: BIT S_BIT_LIN,(HL) + JR Z,.LP_LN1 + BIT S_BIT_END,(HL) + JR Z,.LP_LN0 + RET + + ENDMODULE + +*/ \ No newline at end of file diff --git a/src/bios/exp/FUNC_PIC.ASM b/src/bios/exp/FUNC_PIC.ASM deleted file mode 100644 index bac6322..0000000 --- a/src/bios/exp/FUNC_PIC.ASM +++ /dev/null @@ -1,536 +0,0 @@ - -;****************************************************************** -; вход: DE - вертикаль, HL - горизонталь, -; B - цвет точки, A - экран -PIC_FN1: - AND A - SCF - RET NZ - - IN A,(RGADR) - PUSH AF - - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - - LD A,(SYS_PAGE.WIN_MAP_IX+WIN_GRAF_Y) - ADD A,E - OUT (RGADR),A - LD A,B - LD BC,(SYS_PAGE.WIN_MAP_IX+WIN_GRAF_X) - ADD HL,BC - LD B,A - LD A,#50 - OUT (SLOT3),A - LD (HL),A - EX AF,AF' - OUT (SLOT3),A - - POP AF - OUT (RGADR),A - RET - -; вход: DE - вертикаль, HL - горизонталь. -; IX - длина линии в точках не 0 !!! -; FILL - by A -; ????? -PIC_FN2: - LD D,A - IN A,(SLOT1) - EX AF,AF' - - LD A,B - ADD A,#50 - OUT (SLOT1),A - - BIT 0,B - LD BC,#40+#4000 - JR Z,PIC_FN2_NO_2ND - LD BC,#40+320+#4000 -PIC_FN2_NO_2ND: - ADD HL,BC - - LD A,E - OUT (RGADR),A - - LD A,XH - AND A - JR Z,PIC_FN2_NO256 -PIC_FN2_256L: - LD B,64 -PIC_FN2_256: - LD (HL),D - INC HL - LD (HL),D - INC HL - LD (HL),D - INC HL - LD (HL),D - INC HL - DJNZ PIC_FN2_256 - DEC A - JR NZ,PIC_FN2_256L - -PIC_FN2_NO256: - LD B,XL - AND A - RR B - JR NC,PIC_FN2_NO1 - LD (HL),D - INC HL - AND A -PIC_FN2_NO1: - RR B - JR NC,PIC_FN2_NO2 - LD (HL),D - INC HL - LD (HL),D - INC HL - AND A -PIC_FN2_NO2: - XOR A - CP B - JR Z,PIC_FN2_NO4 -PIC_FN2_4: - LD (HL),D - INC HL - LD (HL),D - INC HL - LD (HL),D - INC HL - LD (HL),D - INC HL - DJNZ PIC_FN2_4 -PIC_FN2_NO4: - - EX AF,AF' - OUT (SLOT1),A - XOR A - OUT (RGADR),A - RET - -;************************************************************************ -; вход: dE - вертикаль, HL - горизонталь. -; A',HL' - адрес данных во второй странице ! -; BC' - длина данных -; ВЫВОД ЛИНИИ ТОЧЕК -PIC_FN3: - IN A,(SLOT3) - LD C,A - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,C - LD (SYS_PAGE.COPY_SLOT3),A - IN A,(SLOT2) - LD (SYS_PAGE.COPY_SLOT2),A - IN A,(SLOT1) - LD (SYS_PAGE.COPY_SLOT1),A - - LD A,B - ADD A,#50 - OUT (SLOT1),A - - BIT 0,B - LD BC,40H+04000H - JR Z,PIC_FN3_NO_2ND - LD BC,40H+320+04000H -PIC_FN3_NO_2ND: - ADD HL,BC - - LD A,E - OUT (RGADR),A - - LD A,H - EXX - LD D,A - EXX - LD A,L - EXX - LD E,A - EXX - - EX AF,AF' - OUT (SLOT2),A - EX AF,AF' - LD HL,SYS_PAGE.RAMD_FAT - LD L,A - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(HL) - OUT (SLOT3),A - EXX - LDIR - BIT 6,H - JR Z,PIC_FN3_NO - RES 6,H - EX AF,AF' -PIC_FN3_NO: - EXX - - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(SYS_PAGE.COPY_SLOT1) - OUT (SLOT1),A - LD A,(SYS_PAGE.COPY_SLOT2) - OUT (SLOT2),A - LD A,(SYS_PAGE.COPY_SLOT3) - OUT (SLOT3),A - - XOR A - OUT (RGADR),A - RET - -;************************************************************************** -; вход: HL - данные палитры RGB, E - начальный цвет -; D - число цветов, B - PAL-mask, A - page PAL -;PIC_FN4: -PIC_SET_PAL: - PUSH IX - - EX AF,AF' - IN A,(RGADR) - PUSH AF ; сохранить положение RGADR - LD A,E - OUT (RGADR),A ; начальный цвет в порт - LD A,D ; сохранить число цветов - EX AF,AF' ; вернуть страницу PAL - - BIT 7,H ; проверить адрес данных - LD C,SLOT3 ; если ниже 8000h - LD D,0C3H ; то граф.экран на странице 3 - JR Z,PIC_FN4_NO_PAGE1 - LD D,043H ; иначе - LD C,SLOT1 ; на странице 1 -PIC_FN4_NO_PAGE1: - - ADD A,A - JR C,PIC_PAL_READ - - ADD A,A - AND 1CH - XOR 0E0H ; младший байт адреса PAL - LD E,A ; DE - адрес в видео-ОЗУ - PUSH DE - POP IX ; адрес палитры - - LD D,B ; маска PAL - EX AF,AF' ; вернуть число цветов - LD B,A ; число цветов - - IN E,(C) ; сохранить страницу 3 - LD A,#50 ; страница графического RAM - OUT (C),A - -PIC_FN4_L1: ; цикл установки цветов палитры - - LD A,(HL) ; B - AND D - LD (IX+2),A - INC HL - - LD A,(HL) ; G - AND D - LD (IX+1),A - INC HL - - LD A,(HL) ; R - AND D - LD (IX+0),A - INC HL - - LD A,(HL) ; Y - AND D - LD (IX+3),A - INC HL - - IN A,(RGADR) - INC A - OUT (RGADR),A - - DJNZ PIC_FN4_L1 ; выполнять, пока не 0 - - OUT (C),E ; восстановить страницу 3 - - POP AF - OUT (RGADR),A ; восстановить Y_PORT - POP IX - AND A - RET - -PIC_PAL_READ: - - ADD A,A - AND 1CH - XOR 0E0H ; младший байт адреса PAL - LD E,A ; DE - адрес в видео-ОЗУ - PUSH DE - POP IX ; адрес палитры - - LD D,B ; маска PAL - EX AF,AF' ; вернуть число цветов - LD B,A ; число цветов - - IN E,(C) ; сохранить страницу 3 - LD A,#50 ; страница графического RAM - OUT (C),A - -PIC_FN4_L2: ; цикл установки цветов палитры - - LD A,(IX+2) - LD (HL),A ; B - INC HL - - LD A,(IX+1) - LD (HL),A ; G - INC HL - - LD A,(IX+0) - LD (HL),A ; R - INC HL - - LD A,(IX+3) - LD (HL),A ; Y - INC HL - - IN A,(RGADR) - INC A - OUT (RGADR),A - - DJNZ PIC_FN4_L2 ; выполнять, пока не 0 - - OUT (C),E ; восстановить страницу 3 - - POP AF - OUT (RGADR),A ; восстановить Y_PORT - POP IX - AND A - RET - - -;******************************************************************** -PIC_FN5: ; УСТАНОВКА СТРАНИЦЫ MODE - LD A,E - AND 1 - OUT (RGMOD),A - RET -;******************************************************************* -; A - page_pal, E - номер палитры, B - тип палитры -PIC_FN6: - LD D,A - DEC B - JP Z,SET_PAL_GRAF - DEC B - JP Z,SET_PAL_ZX - DEC B - JP Z,SET_PAL_IBM - -; LD IX,PAL_DAT1 -; JR Z,PIC_FN6_L1 -; DEC B -; LD IX,PAL_DAT -; JR Z,PIC_FN6_L1 - - SCF - RET - -;PIC_FN6_L1: -; AND 3 -; ADD A,A -; ADD A,A -; ADD A,0E0H -; LD L,A -; LD H,43H -; IN A,(SLOT1) -; PUSH AF -; -; LD A,#50 -; OUT (SLOT1),A -; XOR A -; OUT (RGADR),A -; EX AF,AF' -; call PAL_LOOP_M -; -; POP AF -; OUT (SLOT1),A -; XOR A -; OUT (RGADR),A -; -; RET - -;****************************************************************** -; Рисование линии. -; dЕ - вертикаль, HL - горизонталь -; H' - высота, C'/DE',B' - add_parameters -; A - color -PIC_FN7: - LD D,A - IN A,(SLOT1) - PUSH AF - - LD A,B - ADD A,#50 - OUT (SLOT1),A - - BIT 0,B - LD BC,#40+#4000 - JR Z,.no_2nd - LD BC,#40+320+#4000 -.no_2nd: - ADD HL,BC - LD A,E - -.loop: OUT (RGADR),A ; страница видео-ОЗУ - LD (HL),D - - EXX - EX AF,AF' - - DEC H - JR Z,.exit - - LD A,C ; NEXT HORIZONTAL - ADD A,B - LD C,A - LD A,E - EXX - - ADC A,L - LD L,A - - EXX - LD A,D - EXX - - ADC A,H - LD H,A - INC E ; NEXT VERTICAL - EX AF,AF' - INC A - JR .loop - -.exit: EXX - POP AF - OUT (SLOT1),A - XOR A - OUT (RGADR),A - RET - -;****************************************************************** -; Рисование линии. -; dЕ - вертикаль, HL - горизонталь -; H' - высота, C'/DE',B' - add_parameters -; (IX) - colors -PIC_FN8: - IN A,(SLOT1) - PUSH AF - - LD A,B - ADD A,#50 - OUT (SLOT1),A - - BIT 0,B - LD BC,#40+#4000 - JR Z,.no_2nd - LD BC,#40+320+#4000 -.no_2nd: - ADD HL,BC - LD A,E - -.loop: OUT (RGADR),A ; страница видео-ОЗУ - LD D,(IX) - INC IX - LD (HL),D - - EXX - EX AF,AF' - - DEC H - JR Z,.exit - - LD A,C ; NEXT HORIZONTAL - ADD A,B - LD C,A - LD A,E - EXX - - ADC A,L - LD L,A - - EXX - LD A,D - EXX - - ADC A,H - LD H,A - - INC E ; NEXT VERTICAL - - EX AF,AF' - INC A - JR .loop - -.exit: EXX - POP AF - OUT (SLOT1),A - XOR A - OUT (RGADR),A - RET - -;************************************************** -; Вывод спрайта на экран -; HL - горизоталь, dE - вертикаль -; A',HL' - адрес данных -PIC_FN9: - -;********************************* -; HL,E - координаты D - color -; B - Magnify -PIC_FN10: -PIC_FN11: -PIC_FN12: -PIC_FN13: -PIC_FN14: -PIC_FN15: - SCF - RET - -;************************************ -; -; Экранные таблицы -; -;текстовое окно 80x32 -LP_SCR_80: - DB 40,32,0,0,27,0,0,0 - DB 0, 0,0,0, 0,0,0,0 - -;текстовое окно 40x32 -LP_SCR_40: - DB 40,32,0,0,123,0,0,0 - DB 0, 0,0,0, 0,0,0,0 - -;спектрумовское окно 32x24 -LP_SCR_32: - DB 32,24,4,4,48,1,0,0 - DB 0, 0,0,0, 0,0,0,0 - -;текстовое окно 64x24 -LP_SCR_64: - DB 32,24,4,4,155,0,0,0 - DB 0, 0,0,0, 0,0,0,0 - -;графическое окно 0 -PIC_320X256_1: - DB 40,32,0,0,32,0,8,0 - DB 0, 0,0,0, 0,0,0,0 - -;графическое окно 1 -PIC_320X256_2: - DB 40,32,0,0,96,0,48,0 - DB 0, 0,0,0, 0,0, 0,0 - -;************************************ -; - - diff --git a/src/bios/exp/FUNC_RAM_ROM_DRV.ASM b/src/bios/exp/FUNC_RAM_ROM_DRV.ASM index fbeaaf5..304df85 100644 --- a/src/bios/exp/FUNC_RAM_ROM_DRV.ASM +++ b/src/bios/exp/FUNC_RAM_ROM_DRV.ASM @@ -1,107 +1,128 @@ ;===================[ Функции распределения памяти ]===================; - +; Выход: BC - FREE MEM в блоках по 16k, HL - FULL MEM +;!TEST все SLOT2 на SLOT1 ; ;----------------------------------------------------------------------; -; Определение объема памяти. -; Выход: BC - FREE MEM в блоках по 16k, HL - FULL MEM -EMM.GetMemSize: - IN A,(SLOT2) - LD B,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD HL,SYS_PAGE.RAMD_FAT-#4000 - LD C,0 -.loop: LD A,(HL) - INC L - JR Z,.exit - AND A - JR NZ,.loop - INC C - JR .loop -.exit: LD HL,#100 - LD A,B - LD B,0 - OUT (SLOT2),A - RET +; Определение объема памяти. +; Выход: BC - FREE MEM в блоках по 16k, HL - FULL MEM +EMM.GetMemSize: IN A,(SLOT1) + LD B,A + LD A,SYS_PAGE + OUT (SLOT1),A + XOR A + LD C,A + LD HL,SYS_PAGE.RAM_TABLE-#4000-#4000 + ; +.loop: DEC L + JR Z,.exit + CP (HL) + JR NZ,.loop + INC C + JP .loop + ; +.exit: LD HL,#100 ;!HARDCODE max mem pages + LD A,B + ; L=0 + LD B,L + OUT (SLOT1),A + RET + + /* +.loop: LD A,(HL) + INC L + JR Z,.exit + AND A + JR NZ,.loop + INC C + JR .loop +.exit: LD HL,#100 ;!HARDCODE max mem pages + LD A,B + LD B,0 + OUT (SLOT1),A + RET + */ ;----------------------------------------------------------------------; ; - +;!!!!! Если используется SLOT3 со своими страницами, то не пользоваться +; стеком, там может быть SP в режиме спектрума ; ;----------------------------------------------------------------------; -; Инициализация распределения памяти. -EMM.InitMem: - PUSH BC - PUSH HL - PUSH DE +; Инициализация распределения памяти. +EMM.InitMem: PUSH BC + PUSH HL + PUSH DE - IN A,(SLOT2) - LD C,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD HL,SYS_PAGE.RAMD_FAT-#4000 ; Адрес FAT ОЗУ. -; обнуляем таблицу -.loopFree: - LD (HL),0 - INC L - JR NZ,.loopFree -; резервируем спец.страницы и страницы ZX - LD B,RESERVED_PAGES.Blocks - LD DE,RESERVED_PAGES ; таблица занятых системных страниц -.loop: LD A,(DE) - CP #FF - JR Z,.exitLoop -.loopBlk: - INC DE - LD L,A - LD A,(DE) - LD (HL),A - CP #FF - JR NZ,.loopBlk -.exitLoop: - INC DE - DJNZ .loop - LD L,A - LD (HL),A -; Инициализация ключей RAM-Disks - LD HL,SYS_PAGE.RAMD_KEYS-#4000 - LD B,SYS_PAGE.RAMD_KEYS.NUM -.loop2: LD (HL),0 - INC L - DJNZ .loop2 - LD A,C - OUT (SLOT2),A - - POP DE - POP HL - POP BC - RET + IN A,(SLOT3) + LD C,A + LD A,SYS_PAGE + OUT (SLOT3),A + LD HL,SYS_PAGE.RAM_TABLE ; Адрес RAM FAT в ОЗУ. + ; обнуляем таблицу + XOR A +.loopFree: LD (HL),A + INC L + JR NZ,.loopFree + ; резервируем спец.страницы и страницы ZX + ;LD B,RESERVED_PAGES.Blocks + LD DE,RESERVED_PAGES ; таблица занятых системных страниц +.loop: LD A,(DE) + CP #FF + JR Z,.exitLoop + ; +.loopBlk: INC DE + LD L,A + LD A,(DE) + LD (HL),A + CP #FF + JR NZ,.loopBlk + ; +.exitLoop: ;INC DE + ;DJNZ .loop + LD L,A + LD (HL),A + ; Инициализация ключей RAM-Disks + XOR A + LD HL,SYS_PAGE.RAMD_KEYS + LD B,SYS_PAGE.RAMD_KEYS.NUM +.loop2: LD (HL),A + INC L + DJNZ .loop2 + ; [x] 04/11/2023 + LD HL,SYS_PAGE.Sp_RAMD_KEYS + LD B,SYS_PAGE.Sp_RAMD_KEYS.NUM +.loop3: LD (HL),A + INC L + DJNZ .loop3 + ; + LD A,C + OUT (SLOT3),A + POP DE + POP HL + POP BC + RET ;---------------------------------------------------------------------[] -RESERVED_PAGES: - ;; Block #1 - можно освободить по ID 1 - DB 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 ; for Spectrum - DB #42,#43,#44,#45 ; For BASIC128/BASIC48/TRDOS/EXPANSION - ;!FIXIT выяснилось, что эмулятор ПЗУ умеет больше страниц. Всего 10. - IF SetFullZXromLoader - DB #46,#47 - ENDIF - DB #FF ; End of the block - - ;; Block #2 - нельзя освобождать - DB 0 ; for Spectrum - DB DCP_PAGE ; Ports map - DB Spec_Page ; Page for Spectrum mode - ; Screen pages - DB #50,#51,#52,#53,#54,#55,#56,#57 - DB #58,#59,#5A,#5B,#5C,#5D,#5E,#5F - ; - DB MODE_PAGE ; ????? - DB CBL.BUFFER_PAGE ; Page for CBL audio - DB SYS_PAGE ; Page for system (BIOS) variables - DB #FF ; End of the block - -.Blocks EQU 2 +RESERVED_PAGES: ;[x] free zx pages! + ; Block #1 - можно освободить по ID 1 + ;DB 1,3,4,6,7,8,9,10,11,12,13,14,15 ; for Spectrum + ; эмулятор ПЗУ + ;DB #42,#43,#44,#45,#46,#47;,#48,#49,#4A,#4B ; For (BASIC128, BASIC48, TRDOS, SCORP_ROM)*2, vBIOS, vEXTENSION + ;DB #FF ; End of the block + ; + ; Block #2 - нельзя освобождать + DB ZX_PAGE.SLOT0,ZX_PAGE.SLOT2,ZX_PAGE.SLOT1 ; for Spectrum and BIOS starting + DB DCP_PAGE ; Ports map + DB Spec_Page ; Page for Spectrum mode + ; Screen pages + DB #50,#51,#52,#53,#54,#55,#56,#57 + DB #58,#59,#5A,#5B,#5C,#5D,#5E,#5F + ; + ;DB MODE_PAGE ; ????? + DB SP_SND.CBL.BUFFER_PAGE ; Page for CBL audio + DB SYS_PAGE ; Page for system (BIOS) variables + DB #FF ; End of the block + ; ;----------------------------------------------------------------------; ; @@ -109,59 +130,95 @@ RESERVED_PAGES: ; ;----------------------------------------------------------------------; -; Получить блок памяти N bytes, -; Вход: B - число необходимых блоков -; Выход: L,A - КЛЮЧ RAM-Disk/код ошибки -; CF - признак ошибки +; Получить блок памяти N bytes, +; Вход: B - число необходимых блоков +; Выход: L,A - КЛЮЧ RAM-Disk/код ошибки +; CF - признак ошибки ;EMM_FN2M: -EMM.GetMem: - ;PUSH DE - PUSH BC - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A - LD C,B ; сохранить число нужных блоков - LD HL,SYS_PAGE.RAMD_FAT-#4000 -; Цикл проверки наличия нужных блоков. -.loop: DEC L - JR Z,.noRAM - LD A,(HL) - AND A - JR NZ,.loop - DJNZ .loop +EMM.GetMem: PUSH BC + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD HL,SYS_PAGE.RAM_TABLE + XOR A + LD C,#FF ; Метка конца рамблока + ; Заполнить RAM_TABLE +.loop2: DEC L + JR Z,.error_no_mem + CP (HL) + JR NZ,.loop2 + LD (HL),C + LD C,L + DJNZ .loop2 + ; L = указатель цепочки. + EX AF,AF' + OUT (SLOT3),A + LD A,L + AND A + POP BC + RET + ; +.error_no_mem: EX AF,AF' + OUT (SLOT3),A + LD A,C + CALL EMM.FreeMem + LD L,BIOS.Error.EMM.NoMemory + LD A,L + SCF + POP BC + RET - ; Место есть ! - LD B,C ; Восстановить нужный объем диска - LD C,#FF ; МЕТКА КОНЦА RAM-Disk - LD HL,SYS_PAGE.RAMD_FAT-#4000 -; Заполнить RAMD_FAT -.loop2: DEC L - LD A,(HL) - AND A - JR NZ,.loop2 - LD (HL),C - LD C,L - DJNZ .loop2 - ; L - указатель цепочки. - EX AF,AF' - OUT (SLOT2),A - LD A,L - AND A - POP BC - ;POP DE - RET - -.noRAM: LD L,1 ; НЕТ ПАМЯТИ - EX AF,AF' - OUT (SLOT2),A - LD A,L - SCF - POP BC - ;POP DE - RET + /* +EMM.GetMem: PUSH BC + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD C,B ; сохранить число нужных блоков + LD HL,SYS_PAGE.RAM_TABLE + ; Цикл проверки наличия нужных блоков. + XOR A +.loop: DEC L + JR Z,.noRAM + ; LD A,(HL) + ; AND A + CP (HL) + JR NZ,.loop + DJNZ .loop + ; Место есть ! + LD B,C ; Восстановить нужный объем диска + LD C,#FF ; МЕТКА КОНЦА RAM-Disk + LD L,A ;low SYS_PAGE.RAM_TABLE + ; Заполнить RAM_TABLE + ; A = 0 +.loop2: DEC L + ; LD A,(HL) + ; AND A + CP (HL) + JR NZ,.loop2 + LD (HL),C + LD C,L + DJNZ .loop2 + ; L = указатель цепочки. + EX AF,AF' + OUT (SLOT3),A + LD A,L + AND A + POP BC + RET + ; +.noRAM: LD L,BIOS.Error.EMM.NoMemory + EX AF,AF' + OUT (SLOT3),A + LD A,L + SCF + POP BC + RET + */ ;----------------------------------------------------------------------; ; @@ -169,142 +226,151 @@ EMM.GetMem: ; ;----------------------------------------------------------------------; -; Получить блок памяти N bytes, для RAM-Disk A -; Вход: B - число необходимых блоков, A - RAM-Disk -; Выход: L,A - КЛЮЧ RAM-Disk/код ошибки -; CF - признак ошибки +; Получить блок памяти N bytes, для RAM-Disk A +; Вход: B - число необходимых блоков, A - RAM-Disk +; Выход: L,A - КЛЮЧ RAM-Disk/код ошибки +; CF - признак ошибки ;EMM.GetMem: -EMM.GetMemRMD: - PUSH AF - CALL EMM.GetMem - JR C,.error1 - - LD B,A - POP AF - CALL BLK_TO_RAMD - RET NC -.error2: - LD L,2 ; RAM-Disk занят ;!TODO перечислить все варианты ошибок и их номера как для ДСС - RET -.error1: - POP AF ; нет памяти - LD L,1 - SCF - RET +EMM.GetMemRMD: PUSH AF + CALL EMM.GetMem + JR C,.error1 + ; + LD B,A + POP AF + CALL BLK_TO_RAMD + RET NC + ; +.error2: LD L,BIOS.Error.BadNumber ; RAM-Disk занят + LD A,L + RET + ; +.error1: POP HL ; чистим стек + LD L,A + RET ;----------------------------------------------------------------------; ; ;----------------------------------------------------------------------; -; Освободить блок памяти ключа K -; Вход: A - КЛЮЧ RAM-Disk -EMM.FreeMemRMD: - CALL GET_RAMD_ST - RET C - SCF - RET Z - LD C,A - IN A,(SLOT2) - LD B,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD (HL),0 - LD A,B - OUT (SLOT2),A - LD A,C +; Освободить блок памяти ключа K +; Вход: A - КЛЮЧ RAM-Disk +EMM.FreeMemRMD: CALL GET_RAMD_ST + RET C + SCF + RET Z + LD C,A + IN A,(SLOT3) + LD B,A + LD A,SYS_PAGE + OUT (SLOT3),A + LD H,high SYS_PAGE.RAMD_KEYS + LD (HL),0 + LD A,B + OUT (SLOT3),A + LD A,C ;JR EMM.FreeMem ;------[ -; Освободить блок памяти -; Вход: A - НАЧАЛО ЦЕПОЧКИ +; Освободить блок памяти +; Вход: A - НАЧАЛО ЦЕПОЧКИ +; НЕ ПОРТИТЬ DE!!! ;EMM_FN3M: -EMM.FreeMem: - AND A - SCF - RET Z +EMM.FreeMem: ; [x] теперь нельзя освободить страницу #FF + SCF + INC A + RET Z + DEC A + ; + RET Z + ; + LD C,A + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A - LD L,A - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A + LD H,high SYS_PAGE.RAM_TABLE + LD A,C +.loop: LD L,A + LD A,(HL) ; следующий блок + AND A + JR Z,.error + LD (HL),0 ; Освободить + CP #FF ; Если не конец + JR NZ,.loop ; продолжать - LD H,high (SYS_PAGE.RAMD_FAT - #4000) - LD A,L -EMM_F3M_L1: - LD L,A - LD A,(HL) ; следующий блок - AND A - JR Z,EMM_FN3M_ERR - LD (HL),0 ; Освободить - CP #FF ; Если не конец - JR NZ,EMM_F3M_L1 ; продолжать + ; [x] 23/08/2024 восстановление цепочки если освобождали не с начала + LD A,C + LD L,0 + LD BC,256 + CPIR + JR NZ,.exit + DEC HL + LD (HL),#FF + ; +.exit: EX AF,AF' + OUT (SLOT3),A + XOR A ; no error code + RET - EX AF,AF' - OUT (SLOT2),A - LD A,0 ;!FIXIT недокументировано - AND A - RET - -EMM_FN3M_ERR: - EX AF,AF' - OUT (SLOT2),A - LD A,2 ;!FIXIT недокументировано - SCF - RET +.error: EX AF,AF' + OUT (SLOT3),A + LD A,BIOS.Error.BadNumber + SCF + RET ;----------------------------------------------------------------------; ; -; +; WARNING!!! не трогать DE ;----------------------------------------------------------------------; -; Получить страницу N ключа K -; Вход: A - КЛЮЧ RAM-Disk, B - номер страницы -; Выход: A - страница +; Получить страницу N ключа K +; Вход: A - КЛЮЧ RAM-Disk, B - номер страницы +; Выход: A - страница EMM.GetMemPageRMD: - CALL GET_RAMD_ST - RET C - SCF - RET Z + CALL GET_RAMD_ST + RET C + SCF + RET Z ;JR EMM.GetMemPage -;------[ -; Получить страницу N блока K -; Вход: A - блок, B - номер страницы -; Выход: A - страница, IF CF - A=0 - нет блока, A=FF - END +;------[ +; Получить страницу N блока K +; Вход: A - блок, B - номер страницы +; Выход: A - страница, IF CF - A=0 - нет блока, A=FF - END ;EMM_FN4M: EMM.GetMemPage: - LD L,A - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A + LD L,A + IN A,(SLOT1) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT1),A - INC B - LD H,high (SYS_PAGE.RAMD_FAT - #4000) + INC B + LD H,high (SYS_PAGE.RAM_TABLE-#4000-#4000) EMM_F4M_L1: - LD A,(HL) - AND A - JR Z,EMM_F4M_ERR - DEC B - JR Z,EMM_F4M_END - LD L,A - CP 0FFH - JR NZ,EMM_F4M_L1 + LD A,(HL) + AND A + JR Z,EMM_F4M_ERR + DEC B + JR Z,EMM_F4M_END + LD L,A + CP #FF + JR NZ,EMM_F4M_L1 EMM_F4M_ERR: - LD L,A - EX AF,AF' - OUT (SLOT2),A - LD A,L - SCF - RET + LD L,A + EX AF,AF' + OUT (SLOT1),A + LD A,L + SCF + RET EMM_F4M_END: - EX AF,AF' - OUT (SLOT2),A - LD A,L - AND A - RET + EX AF,AF' + OUT (SLOT1),A + LD A,L + AND A + RET ;----------------------------------------------------------------------; ; @@ -312,29 +378,32 @@ EMM_F4M_END: ; ;----------------------------------------------------------------------; -; Получить следующую страницу по FAT -; Вход: A - страница ОЗУ -; Выход: A - следующая страница ОЗУ +; Получить следующую страницу по FAT +; Вход: A - страница ОЗУ +; Выход: A - следующая страница ОЗУ ;EMM_FN5: EMM.GetMemPageNext: - LD L,A - AND A - SCF - RET Z - IN A,(SLOT2) - LD H,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD A,H - LD H,high (SYS_PAGE.RAMD_FAT - #4000) - LD L,(HL) - OUT (SLOT2),A - LD A,L - AND A - SCF - RET Z - AND A - RET + LD L,A + AND A + SCF + RET Z + + IN A,(SLOT1) + LD H,A + LD A,SYS_PAGE + OUT (SLOT1),A + + LD A,H + LD H,high (SYS_PAGE.RAM_TABLE-#4000-#4000) + LD L,(HL) + OUT (SLOT1),A + LD A,L + AND A + SCF + RET Z + + AND A + RET ;----------------------------------------------------------------------; ; @@ -342,588 +411,74 @@ EMM.GetMemPageNext: ; ;----------------------------------------------------------------------; -; Получить список страниц блока в HL -; Вход: A - блок, HL - адрес буфера - 256 байт. -; Выход: HL - адрес блока, B - длина блока в страницах ОЗУ +; Получить список страниц блока в HL +; Вход: A - блок, HL - адрес буфера - 256 байт. +; Выход: HL - адрес блока, B - длина блока в страницах ОЗУ ;EMM_FN5M: EMM.GetMemBlkPages: - PUSH DE - PUSH HL - EX DE,HL - LD B,0 - LD L,A - -.loop: LD A,L - LD (DE),A - INC DE - AND A - JR Z,.error - CP #FF - JR Z,.end - - IN A,(SLOT2) - LD C,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD H,high (SYS_PAGE.RAMD_FAT - #4000) - LD L,(HL) - LD A,C - OUT (SLOT2),A - - INC B - JR NZ,.loop - -.error: SCF - POP HL - POP DE - RET - -.end: POP HL - POP DE - AND A - RET -;----------------------------------------------------------------------; -; - - - -; -;----------------------------------------------------------------------; -;RAMD_R_W: -; ╔════════════════════════════════════════════════╗ -; ║ RD/WR SECTOR ║\ -; ║ HL - BUFER ║\ -; ║ DE - ABS sector в 256b блоках ║\ -; ║ B - число данных в 256b блоках ║\ -; ║ A - block RAM ║\ -; ║ A' - команда чтение/запись/чтение ROM Disk ║\ -; ║ 0 - read, 255 - write, 70 - read ROM DISK ║\ -; ║ ** NOT USED TR-DOS VARS ** ║\ -; ╚════════════════════════════════════════════════╝\ -; \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ -BLK_RD_WR: - AND A - SCF - RET Z - - ; - ; сохраняем состояние прерываний - LD C,A - LD A,R - PUSH AF - LD A,C - DI - CALL .start - ; восстанавливаем состояние прерываний - EX AF,AF' - POP AF - JP PO,.noInterrupts - EI -.noInterrupts: - EX AF,AF' - RET - ; - -.start: EX AF,AF' - AND A ; 0 - read - JR Z,.reset_Z - CP #FF ; write - JR Z,.keep_Z - - CP 5 ; old read - JR Z,.reset_Z - CP 6 ; old write - JR Z,.keep_Z - - CP #46 - JP Z,ROM_DISK - - EX AF,AF' - SCF - RET - -.reset_Z: - INC A ; set Z for WRITE -.keep_Z: - EX AF,AF' - ; - - PUSH HL - PUSH BC - LD C,SLOT2 - IN B,(C) - ld h,a - LD A,SYS_PAGE - OUT (SLOT2),A - ld a,h - - LD H,high (SYS_PAGE.RAMD_FAT - #4000) - LD L,A - - INC D -RAMD_LOOP_D: - DEC D - JR Z,NOT_FOUR_BLK - LD L,(HL) - LD L,(HL) - LD L,(HL) - LD L,(HL) - JR RAMD_LOOP_D - -NOT_FOUR_BLK: - LD A,E -.loop: SUB #40 - JR C,NOT_ONE_BLK - LD L,(HL) - JR .loop - -NOT_ONE_BLK: - AND #3F - LD D,A ; DE - ADRESS in RAM-Disk - LD E,0 - - LD A,L ; L - текущий банк RAM-Disk - - OUT (C),B ; восстановить страницу - - POP BC ; длина данных - POP HL ; адрес буфера - - BIT 7,H - JR NZ,BLK_PAGE1 ; !!!!! JR NZ,BLK_PAGE1 ? - -BLK_PAGE3: ; !TODO переделать на SLOT ????? - LD C,SLOT3 - IN C,(C) - OUT (SLOT3),A - SET 7,D - SET 6,D - JR BLK_CONT1 - -BLK_PAGE1: - LD C,SLOT1 - IN C,(C) - OUT (SLOT1),A - RES 7,D - SET 6,D - -BLK_CONT1: ; DE - RamDisk, HL - data - EX AF,AF' - JR Z,NO_EX_RW1 ; WRITE - EX DE,HL ; for READ -NO_EX_RW1: - EX AF,AF' - - LD A,16 -BLK_LL1: - DUP 16 - LDI - EDUP - - DEC A - JR NZ,BLK_LL1 - - EX AF,AF' - JR Z,NO_EX_RW2 ; WRITE - EX DE,HL ; for READ -NO_EX_RW2: - EX AF,AF' ; DEC C прокрутился 256 раз и вернулся - INC B ; B уже уменьшился на 1, - DEC B - JP Z,BLK_EXIT_1 - - BIT 6,D - JP NZ,BLK_CONT1 - - BIT 7,D - JR Z,BLK_PAGE3_X - - IN A,(SLOT1) - LD E,A - LD D,#42 - LD A,SYS_PAGE - OUT (SLOT1),A - LD A,(DE) - OUT (SLOT1),A - LD DE,#4000 - JP BLK_CONT1 - -BLK_PAGE3_X: - IN A,(SLOT3) - LD E,A - LD D,#C2 - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(DE) - OUT (SLOT3),A - LD DE,#C000 - - BIT 7,H - JP Z,BLK_CONT1 - - LD E,A - LD A,C - OUT (SLOT3),A - IN A,(SLOT1) - LD C,A - LD A,E - OUT (SLOT1),A - LD DE,#4000 - JP BLK_CONT1 - -BLK_EXIT_1: - LD A,D - DEC A - RLCA - LD A,C - JR C,BLK_EXIT_2 - OUT (SLOT1),A - RET -BLK_EXIT_2: - OUT (SLOT3),A - AND A - RET -;----------------------------------------------------------------------; -; - - - -; -;----------------------------------------------------------------------; - ;**************************************** - ;!!!!! READ_ROM_PAGE_X чтение последних - ; 256 байтов ПЗУ в служебную страницу зачем-то - ; READ_ROM_PAGE_X: - ; LD DE,0 - ; LD BC,#100 ; один сектор - ; PUSH DE - ; PUSH BC - ; LD HL,#3F00 - ; LD DE,#FF00 - ; LD A,#1F ; last page ROM - ; JR ROM_DISK.loopRead - ;**************************************** - -; Чтение с ROM-Disk -; HL - адрес, куда читать -; DE - номер сектора (считать по 256b сектор) -; B - число секторов -; A' - размер сектора (1 - 256b, 2 - 512 b) -ROM_DISK: - ; сохраняем состояние прерываний - ;LD A,R - EX AF,AF' - LD C,0 ; счетчик - DEC A - JR Z,.loop - ;JR Z,.start - DEC A - SCF - RET NZ - - EX DE,HL - ADD HL,HL - EX DE,HL - LD A,B - ADD A,A - LD B,A - ;!!!!! - RET C - - DI - CALL .loop -; ; восстанавливаем состояние прерываний -; EX AF,AF' -; JP PO,.noInterrupts -; EI -; .noInterrupts: -; EX AF,AF' -; ; - RET C - AND A - RR D - RR E - XOR A - RET - -; .start: -; DI -; CALL .loop -; ; восстанавливаем состояние прерываний -; EX AF,AF' -; JP PO,.noInterrupts2 -; EI -; .noInterrupts2: -; EX AF,AF' -; ; -; RET - - -.loop: PUSH DE ; номер сектора - PUSH BC - - LD A,E - AND 63 ; ADRESS in ROM-Page - PUSH AF ; сохранить адрес - - EX DE,HL ; DE - адрес буфера - ADD HL,HL - ADD HL,HL ; H - номер банки - - LD A,(ROM_DISK.Pages.Number) - INC H - CP H - LD L,H - LD H, high ROM_DISK.Pages.Number ; ROM-Disk pages! - LD A,(HL) ; PAGE-ROM - - POP HL ; восстановить адрес в ROM-Page - LD L,0 ; если далеко захотели - выход с ошибкой - JR C,.errorExit ; ROM-Disk-end -; DE - буфер -; HL - адрес в ROM -; B - число секторов -; A - ROM-Page -.loopRead: - PUSH HL ; откуда - PUSH DE ; куда - - LD HL,-.stackDepth - .readProcedure.size ; memory stack use! - ADD HL,SP ; stack - - PUSH HL ; адрес программы .readProcedure - - LD DE,.readProcedure ; перенести программу на стек - EX DE,HL - LD BC,.readProcedure.size - LDIR ; программа на стеке - LD BC,#100 ; длина сектора - RET ; исполнить программу .readProcedure, на стеке адреса буфера и ROM -; DE - next address -; HL - ROM address -.readNext: - POP BC ; число секторов - - INC C ; счетчик считанных секторов - DEC B ; сектора кончились? - - JR Z,.normExit - BIT 6,H ; чтение не закончено - - PUSH BC ; сохранить счетчики - JR Z,.loopRead ; читать дальше - POP BC - - POP HL ; номер сектора - - LD A,B - LD B,0 - ADD HL,BC - LD B,A ; вычислить след.сектор - - EX DE,HL ; теперь HL - адрес, DE сектор, B - сколько еще читать - - JP .loop ; начать все снова! -; чтение закончено -.normExit: - POP HL ; сектор, откуда велось чтение - ADD HL,BC ; по возврату: HL - след.адрес - EX DE,HL ; DE - след.сектор - AND A - RET -; ошибка -.errorExit: ; !TODO сделать, чтоб на выходе показывалось количество прочитанных секторов - POP BC - POP DE - SCF - RET -; процедура, переносимая на стек для чтения из ROM-Disk -; осторожнее с PUSH, если надо много, то увеличивай .stackDepth -.readProcedure: - POP DE ; куда - POP HL ; откуда - OUT (ROM.SLOT0),A ; ROM_PAGE - LDIR ; здесь читается из ROM-Disk - LD B,A - XOR A - OUT (ROM.SLOT0),A - OUT (SYS_PORT.ROM),A - LD A,B - JP .readNext -.stackDepth EQU 8 ; расстояние от конца процедуры до вершины стека. -.readProcedure.size EQU $-.readProcedure -;----------------------------------------------------------------------; -; - - - -; -;----------------------------------------------------------------------; -; вход: DE - ram_disk trk_sec, A - RAM-Disk -; выход: HL - адрес, A - page -RAMD_CALC_PAGE: - CP 16 - CCF - RET C ; НЕТ ТАКОГО RAM-Disk - - PUSH AF - LD H,D - LD L,E - ADD HL,HL - ADD HL,HL - LD B,H - LD A,E - OR #C0 - LD C,A ; C - часть адреса, B - страница - POP AF - - CALL EMM.GetMemPageRMD ; ПОЛУЧИТЬ СТРАНИЦУ - LD L,0 - LD H,C - RET -;----------------------------------------------------------------------; -; - - - -; -;----------------------------------------------------------------------; -; Вход: -; A - RAM Disk ID -; Выход: -; A - Number (0..15) -GET_RAMD_NUM: - EX AF,AF' - IN A,(SLOT2) - EX AF,AF' - LD BC,SYS_PAGE * 256 + SLOT2 - OUT (C),B - - LD HL,SYS_PAGE.RAMD_KEYS-#4000 - LD BC,SYS_PAGE.RAMD_KEYS.NUM - CPIR - - EX AF,AF' - OUT (SLOT2),A - EX AF,AF' - - SCF - RET PE - - DEC L - LD A,L - SUB low SYS_PAGE.RAMD_KEYS - RET -;----------------------------------------------------------------------; -; - - - -; -;----------------------------------------------------------------------; -; на выходе при А = 0 должен быть установлен флаг Z -; DSS надеется, что эта функция не грохает DE -GET_RAMD_ST: - CP SYS_PAGE.RAMD_KEYS.NUM - CCF - RET C - - PUSH BC - - LD HL,SYS_PAGE.RAMD_KEYS-#4000 - ADD A,L - LD L,A - - IN A,(SLOT2) - LD B,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD C,(HL) - LD A,B - OUT (SLOT2),A - LD A,C - POP BC - AND A - RET -;----------------------------------------------------------------------; -; - - - -; -;----------------------------------------------------------------------; -; RAM-Disk A, BLK - B -BLK_TO_RAMD: - CP SYS_PAGE.RAMD_KEYS.NUM - CCF - RET C - - PUSH HL - LD L,A - - IN A,(SLOT2) - LD C,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD A,L - LD HL,SYS_PAGE.RAMD_KEYS-#4000 - ADD A,L - LD L,A - LD A,(HL) ; ключ блока - AND A - JR NZ,BLK_BUSY ; RAM-Disk занят - ошибка - LD (HL),B - - LD A,C - OUT (SLOT2),A - - LD A,B - AND A - POP HL - RET - -BLK_BUSY: - LD A,C - OUT (SLOT2),A - - SCF - POP HL - RET -;----------------------------------------------------------------------; -; - - - -; -;----------------------------------------------------------------------; -; RAM-Disk A -RAMD_CLEAR: - CP SYS_PAGE.RAMD_KEYS.NUM - CCF - RET C - - PUSH HL - LD L,A - - IN A,(SLOT2) - LD C,A - LD A,SYS_PAGE - OUT (SLOT2),A - LD A,L - LD HL,SYS_PAGE.RAMD_KEYS-#4000 ; RAM-Disk свободен - ADD A,L - LD L,A - LD B,A ; запомнить удаляемый рамдиск - LD A,(HL) - AND A - JR Z,BLK_BUSY ; возврат с ошибкой - LD (HL),0 - LD A,C - OUT (SLOT2),A - - AND A - POP HL - RET + PUSH DE + PUSH HL + EX DE,HL + LD B,0 + LD L,A + +.loop: LD A,L + LD (DE),A + INC DE + AND A + JR Z,.error + CP #FF + JR Z,.end + ; + IN A,(SLOT1) + LD C,A + LD A,SYS_PAGE + OUT (SLOT1),A + LD H,high (SYS_PAGE.RAM_TABLE-#4000-#4000) + LD L,(HL) + LD A,C + OUT (SLOT1),A + ; + INC B + JR NZ,.loop + +.error: SCF +.end: POP HL + POP DE + RET + +; RAMDRV.EXE вызывает эту функцию с адресом в SLOT1, поэтому лучше так не оптимизировать +; EMM.GetMemBlkPages: +; PUSH DE +; PUSH HL +; EX DE,HL +; LD B,0 +; LD L,A + +; IN A,(SLOT1) +; LD C,A +; LD A,SYS_PAGE +; OUT (SLOT1),A + +; .loop: LD A,L +; LD (DE),A +; INC DE +; AND A +; JR Z,.error +; CP #FF +; JR Z,.end +; ; +; LD H,high +(SYS_PAGE.RAM_TABLE - #4000 - #4000) +; LD L,(HL) +; INC B +; JR NZ,.loop + +; .error: SCF +; .end: LD A,C +; OUT (SLOT1),A +; POP HL +; POP DE +; RET ;----------------------------------------------------------------------; ; @@ -935,33 +490,33 @@ RAMD_CLEAR: ; A - блок, B - длина первого блока после разделения ; выход: A - блок 1, B - блок 2 EMM.DivMemBlocks: - INC B - DEC B - SCF - RET Z - DEC B - LD E,A - CALL EMM.GetMemPage ; получить номер страницы блока - RET C - LD D,A + INC B + DEC B + SCF + RET Z + DEC B + LD E,A + CALL EMM.GetMemPage ; получить номер страницы блока + RET C + LD D,A - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A - LD H,high (SYS_PAGE.RAMD_FAT - #4000) - LD L,D - LD A,(HL) - LD (HL),0FFH - LD B,A + LD H,high +(SYS_PAGE.RAM_TABLE); - #4000 - #4000) + LD L,D + LD A,(HL) + LD (HL),#FF + LD B,A - EX AF,AF' - OUT (SLOT2),A + EX AF,AF' + OUT (SLOT3),A - LD A,E - AND A - RET + LD A,E + AND A + RET ;----------------------------------------------------------------------; ; @@ -973,38 +528,605 @@ EMM.DivMemBlocks: ; А - блок 1, B - блок 2 ; выход: А - блок EMM.MergeMemBlocks: - LD E,A - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A - LD H,high (SYS_PAGE.RAMD_FAT - #4000) - LD L,E - LD C,B - LD B,0 -EMM_ADD_L: - LD A,(HL) - AND A - JR Z,EMM_ADD_ERR - CP 0FFH - JR Z,EMM_ADD_NEXT - LD L,A - DJNZ EMM_ADD_L -EMM_ADD_ERR: - EX AF,AF' - OUT (SLOT2),A - SCF - RET + LD E,A + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD H,high SYS_PAGE.RAM_TABLE + LD L,E + LD C,B + LD B,0 +.ADD_L: LD A,(HL) + AND A + JR Z,.ADD_ERR + CP #FF + JR Z,.ADD_NEXT + LD L,A + DJNZ .ADD_L -EMM_ADD_NEXT: - LD A,C - AND A - JR Z,EMM_ADD_ERR - LD (HL),A - EX AF,AF' - OUT (SLOT2),A - AND A - LD A,E - RET +.ADD_ERR: + EX AF,AF' + OUT (SLOT3),A + SCF + RET + +.ADD_NEXT: LD A,C + AND A + JR Z,.ADD_ERR + LD (HL),A + EX AF,AF' + OUT (SLOT3),A + AND A + LD A,E + RET +;----------------------------------------------------------------------; +; + + + +; +;----------------------------------------------------------------------; +; вход: DE - ram_disk trk_sec, A - RAM-Disk +; выход: HL - адрес, A - page +RAMD_CALC_PAGE: + CP 16 + CCF + RET C ; НЕТ ТАКОГО RAM-Disk + + PUSH AF + LD H,D + LD L,E + ADD HL,HL + ADD HL,HL + LD B,H + LD A,E + OR #C0 + LD C,A ; C - часть адреса, B - страница + POP AF + + CALL EMM.GetMemPageRMD ; ПОЛУЧИТЬ СТРАНИЦУ + LD L,0 + LD H,C + RET +;----------------------------------------------------------------------; +; + + + +; +;----------------------------------------------------------------------; +; Вход: +; A - RAM Disk ID +; Выход: +; A - Number (0..15) +GET_RAMD_NUM: + EX AF,AF' + IN A,(SLOT1) + EX AF,AF' + LD BC,SYS_PAGE*256+SLOT1 + OUT (C),B + + LD HL,SYS_PAGE.RAMD_KEYS-#4000-#4000 + LD BC,SYS_PAGE.RAMD_KEYS.NUM + CPIR + + EX AF,AF' + OUT (SLOT1),A + EX AF,AF' + + SCF + RET PE + + DEC L + LD A,L + SUB low SYS_PAGE.RAMD_KEYS + RET +;----------------------------------------------------------------------; +; + + + +; +;----------------------------------------------------------------------; +; [x] 04/11/2023 +; Вход: +; B = 0: swap to Sp +; B = #FF: swap to ZX +; B = #FE: no swap, only get info +; Выход: +; A - current RAM Drives set +SWAP_RAM_DRIVES: + IN A,(SLOT3) + EX AF,AF' + PUSH AF ;на всякий случай + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD A,(SYS_PAGE.CURRENT_RAM_DRV) + LD C,A + CP B + JR Z,.exit ; уже установлен запрашиваемый набор + ; + LD A,#FE + CP B + JR Z,.exit ; ничего не менять, выдать текущий набор + ; +.swap: LD HL,SYS_PAGE.RAMD_KEYS + LD DE,SYS_PAGE.Sp_RAMD_KEYS + LD B,SYS_PAGE.RAMD_KEYS.NUM +.loop: LD A,(DE) + LD C,A + LD A,(HL) + LD (DE),A + LD A,C + LD (HL),A + INC HL + INC DE + DJNZ .loop + ; + LD A,(SYS_PAGE.CURRENT_RAM_DRV) + XOR #FF + LD (SYS_PAGE.CURRENT_RAM_DRV),A + LD C,A + ; +.exit: EX AF,AF' + OUT (SLOT3),A + POP AF + EX AF,AF' + LD A,C + RET +;----------------------------------------------------------------------; +; + + +; +;----------------------------------------------------------------------; +; на выходе при А = 0 должен быть установлен флаг Z +; не убивает DE и BC +GET_RAMD_ST: + CP SYS_PAGE.RAMD_KEYS.NUM + CCF + RET C + + PUSH BC + + LD HL,SYS_PAGE.RAMD_KEYS-#4000-#4000 + ADD A,L + LD L,A + + IN A,(SLOT1) + LD B,A + LD A,SYS_PAGE + OUT (SLOT1),A + LD C,(HL) + LD A,B + OUT (SLOT1),A + LD A,C + POP BC + AND A + RET +;----------------------------------------------------------------------; +; + + + +; +;----------------------------------------------------------------------; +; RAM-Disk A, BLK - B +BLK_TO_RAMD: + CP SYS_PAGE.RAMD_KEYS.NUM + CCF + RET C + + PUSH HL + LD L,A + + IN A,(SLOT3) + LD C,A + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,L + LD HL,SYS_PAGE.RAMD_KEYS; - #4000 - #4000 + ADD A,L + LD L,A + LD A,(HL) ; ключ блока + AND A + JR NZ,BLK_BUSY ; RAM-Disk занят - ошибка + LD (HL),B + + LD A,C + OUT (SLOT3),A + + LD A,B + AND A + POP HL + RET + ; +BLK_BUSY: + LD A,C + OUT (SLOT3),A + SCF + POP HL + LD A,L + RET +;----------------------------------------------------------------------; +; + + + +; +;----------------------------------------------------------------------; +; RAM-Disk A +RAMD_CLEAR: + CP SYS_PAGE.RAMD_KEYS.NUM + CCF + RET C + + PUSH HL + LD L,A + + IN A,(SLOT3) + LD C,A + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,L + LD HL,SYS_PAGE.RAMD_KEYS; - #4000 - #4000 ; RAM-Disk свободен + ADD A,L + LD L,A + LD B,A ; запомнить удаляемый рамдиск + LD A,(HL) + AND A + JR Z,BLK_BUSY ; возврат с ошибкой + LD (HL),0 + LD A,C + OUT (SLOT3),A + + AND A + POP HL + RET +;----------------------------------------------------------------------; +; + + + +; +;----------------------------------------------------------------------; !FIXIT SAFE_RGADR +;RAMD_R_W: +; ╔════════════════════════════════════════════════╗ +; ║ RD/WR SECTOR ║\ +; ║ HL - BUFER ║\ +; ║ DE - ABS sector в 256b блоках ║\ +; ║ B - число данных в 256b блоках ║\ +; ║ A - block RAM ║\ +; ║ A' - команда чтение/запись/чтение ROM Disk ║\ +; ║ 0 - read, 255 - write, 70 - read ROM DISK║\ +; ║ ** NOT USED TR-DOS VARS ** ║\ +; ╚════════════════════════════════════════════════╝\ +; \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ +BLK_RD_WR: AND A + SCF + RET Z + ; + AND A + INC B + DEC B + RET Z + ; сохраняем состояние прерываний + LD C,A + LD A,R + PUSH AF + ; сохраняем PORT_Y + IN A,(PORT_Y) + PUSH AF + LD A,#C0 + OUT (PORT_Y),A + ; + LD A,C + DI + CALL .start + EX AF,AF' + ; восстанавливаем PORT_Y + POP AF + OUT (PORT_Y),A + ; восстанавливаем состояние прерываний + POP AF + JP PO,.noInterrupts + EI +.noInterrupts: EX AF,AF' + RET +; ; +.start: EX AF,AF' + AND A ; 0 - read + JR Z,.reset_Z + CP #FF ; write + JR Z,.keep_Z + ; + CP 5 ; old read + JR Z,.reset_Z + CP 6 ; old write + JR Z,.keep_Z + ; + CP #46 + JP Z,ROM_DISK + ; + EX AF,AF' + SCF + RET + ; +.reset_Z: INC A ; set Z for WRITE +.keep_Z: EX AF,AF' + ; + PUSH HL + PUSH BC + LD C,SLOT1 + IN B,(C) + LD H,A + LD A,SYS_PAGE + OUT (SLOT1),A + LD A,H + ; + LD H,high +(SYS_PAGE.RAM_TABLE-#4000-#4000) + LD L,A + INC D +.RAMD_LOOP_D: DEC D + JR Z,.NOT_FOUR_BLK + LD L,(HL) + LD L,(HL) + LD L,(HL) + LD L,(HL) + JP .RAMD_LOOP_D + ; +.NOT_FOUR_BLK: LD A,E +.loop: SUB #40 + JR C,.NOT_ONE_BLK + LD L,(HL) + JP .loop + ; +.NOT_ONE_BLK: AND #3F + LD D,A ; DE - ADRESS in RAM-Disk + LD E,0 + LD A,L ; L - текущий банк RAM-Disk + OUT (C),B ; восстановить страницу + POP BC ; длина данных + POP HL ; адрес буфера + BIT 7,H + JR NZ,.BLK_PAGE1 + ; + LD C,SLOT3 + IN C,(C) + OUT (SLOT3),A + SET 7,D + SET 6,D + JP .BLK_CONT1 + ; +.BLK_PAGE1: LD C,SLOT1 + IN C,(C) + OUT (SLOT1),A + RES 7,D + SET 6,D + ; DE - RamDisk, HL - data +.BLK_CONT1: EX AF,AF' + JR Z,.NO_EX_RW1 ; WRITE + EX DE,HL ; for READ +.NO_EX_RW1: EX AF,AF' + LD A,16 + ; +.BLK_LL1: DUP 16 + LDI + EDUP + DEC A + JR NZ,.BLK_LL1 + ; + EX AF,AF' + JR Z,.NO_EX_RW2 ; WRITE + EX DE,HL ; for READ +.NO_EX_RW2: EX AF,AF' ; DEC C прокрутился 256 раз и вернулся + ; A = 0 + CP B + JP Z,.BLK_EXIT_1 + ; + BIT 6,D + JP NZ,.BLK_CONT1 + ; + BIT 7,D + JR Z,.BLK_PAGE3_X + ; + IN A,(SLOT1) + LD E,A + LD D,high +(SYS_PAGE.RAM_TABLE-#4000-#4000) + LD A,SYS_PAGE + OUT (SLOT1),A + LD A,(DE) + OUT (SLOT1),A + LD DE,#4000 + JP .BLK_CONT1 + ; +.BLK_PAGE3_X: IN A,(SLOT3) + LD E,A + LD D,high SYS_PAGE.RAM_TABLE + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(DE) + OUT (SLOT3),A + LD DE,#C000 + ; + BIT 7,H + JP Z,.BLK_CONT1 + ; + LD E,A + LD A,C + OUT (SLOT3),A + IN A,(SLOT1) + LD C,A + LD A,E + OUT (SLOT1),A + LD DE,#4000 + JP .BLK_CONT1 + ; +.BLK_EXIT_1: LD A,D + DEC A + RLCA + LD A,C + JR C,.BLK_EXIT_2 + OUT (SLOT1),A + RET + ; +.BLK_EXIT_2: OUT (SLOT3),A + AND A + RET +;----------------------------------------------------------------------; +; + + + +; +;----------------------------------------------------------------------; + ;**************************************** + ;!!!!! READ_ROM_PAGE_X чтение последних + ; 256 байтов ПЗУ в служебную страницу зачем-то + ; READ_ROM_PAGE_X: + ; LD DE,0 + ; LD BC,#100 ; один сектор + ; PUSH DE + ; PUSH BC + ; LD HL,#3F00 + ; LD DE,#FF00 + ; LD A,#1F ; last page ROM + ; JR ROM_DISK.loopRead + ;**************************************** + +; Чтение с ROM-Disk +; HL - адрес, куда читать +; DE - номер сектора (считать по 256b сектор) +; B - число секторов +; A' - размер сектора (1 - 256b, 2 - 512 b) +ROM_DISK: EX AF,AF' + LD C,0 ; счетчик + DEC A + JR Z,.loop + ; + DEC A + SCF + RET NZ + ; + EX DE,HL + ADD HL,HL + EX DE,HL + LD A,B + ADD A,A + LD B,A + RET C + ; + DI + CALL .loop + RET C + ; + AND A + RR D + RR E + XOR A + RET + ; +.loop: PUSH DE ; номер сектора + PUSH BC + ; + LD A,E + AND #3F ; ADRESS in ROM-Page + PUSH AF ; сохранить адрес + ; + EX DE,HL ; DE - адрес буфера + ADD HL,HL + ADD HL,HL ; H - номер банки + ; [ ] без привязки ром-диска к align 256 + ;LD A,(ROM_DISK.Pages.Number) + ;INC H + ;CP H + ; + LD C,H + LD B,0 + LD HL,ROM_DISK.Pages + ADD HL,BC + ; + LD A,(ROM_DISK.Pages.Number) ; rdlow-ok + INC C + CP C + ; + ;LD L,H + ;LD H,high ROM_DISK.Pages.Number ; ROM-Disk pages! + ; + LD A,(HL) ; PAGE-ROM + POP HL ; восстановить адрес в ROM-Page + LD L,0 ; если далеко захотели - выход с ошибкой + JR C,.errorExit ; ROM-Disk-end + ; DE - буфер + ; HL - адрес в ROM + ; B - число секторов + ; A - ROM-Page +.loopRead: PUSH HL ; откуда + PUSH DE ; куда + + LD HL,-.stackDepth-.readProcedure.size ; memory stack use! + ADD HL,SP ; stack + + PUSH HL ; адрес программы .readProcedure + + LD DE,.readProcedure ; перенести программу на стек + EX DE,HL + LD BC,.readProcedure.size + LDIR ; программа на стеке + LD BC,#100 ; длина сектора + RET ; исполнить программу .readProcedure, на стеке адреса буфера и ROM + ; DE - next address + ; HL - ROM address +.readNext: POP BC ; число секторов + + INC C ; счетчик считанных секторов + DEC B ; сектора кончились? + + JR Z,.normExit + BIT 6,H ; чтение не закончено + + PUSH BC ; сохранить счетчики + JR Z,.loopRead ; читать дальше + POP BC + + POP HL ; номер сектора + + LD A,B + LD B,0 + ADD HL,BC + LD B,A ; вычислить след.сектор + + EX DE,HL ; теперь HL - адрес, DE сектор, B - сколько еще читать + + JP .loop ; начать все снова! +; чтение закончено +.normExit: POP HL ; сектор, откуда велось чтение + ADD HL,BC ; по возврату: HL - след.адрес + EX DE,HL ; DE - след.сектор + AND A + RET +; ошибка +.errorExit: ; !TODO сделать, чтоб на выходе показывалось количество прочитанных секторов + POP BC + POP DE + SCF + RET +; процедура, переносимая на стек для чтения из ROM-Disk +; осторожнее с PUSH, если надо много, то увеличить .stackDepth +.readProcedure: + POP DE ; куда + POP HL ; откуда + OUT (ROM.SLOT0),A ; ROM_PAGE + LDIR ; здесь читается из ROM-Disk + LD B,A + XOR A + OUT (ROM.SLOT0),A + OUT (SYS_PORT.ROM),A + LD A,B + JP .readNext +.stackDepth EQU 8 ; расстояние от конца процедуры до вершины стека. +.readProcedure.size EQU $-.readProcedure ;----------------------------------------------------------------------; ; \ No newline at end of file diff --git a/src/bios/exp/FUNC_SCREEN.ASM b/src/bios/exp/FUNC_SCREEN.ASM new file mode 100644 index 0000000..9da51e1 --- /dev/null +++ b/src/bios/exp/FUNC_SCREEN.ASM @@ -0,0 +1,1145 @@ + +;****************************************************************** +; вход: DE - вертикаль, HL - горизонталь, +; B - цвет точки, A - экран +PIC_FN1: + AND A + SCF + RET NZ + CCF + + IN A,(PORT_Y) + PUSH AF + + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + + LD A,(WIN_ID_0.GRAF_Y) + ADD A,E + OUT (PORT_Y),A + LD A,B + LD BC,(WIN_ID_0.GRAF_X) + ADD HL,BC + LD B,A + LD A,#50 + OUT (SLOT3),A + LD (HL),A + EX AF,AF' + OUT (SLOT3),A + + POP AF + OUT (PORT_Y),A + RET + +; вход: DE - вертикаль, HL - горизонталь. +; IX - длина линии в точках не 0 !!! +; FILL - by A +; ????? +PIC_FN2: + LD D,A + IN A,(SLOT1) + EX AF,AF' + + LD A,B + ADD A,#50 + OUT (SLOT1),A + + BIT 0,B + LD BC,#40+#4000 + JR Z,PIC_FN2_NO_2ND + LD BC,#40+320+#4000 +PIC_FN2_NO_2ND: + ADD HL,BC + + LD A,E + OUT (PORT_Y),A + + LD A,XH + AND A + JR Z,PIC_FN2_NO256 +PIC_FN2_256L: + LD B,64 +PIC_FN2_256: + LD (HL),D + INC HL + LD (HL),D + INC HL + LD (HL),D + INC HL + LD (HL),D + INC HL + DJNZ PIC_FN2_256 + DEC A + JR NZ,PIC_FN2_256L + +PIC_FN2_NO256: + LD B,XL + AND A + RR B + JR NC,PIC_FN2_NO1 + LD (HL),D + INC HL + AND A +PIC_FN2_NO1: + RR B + JR NC,PIC_FN2_NO2 + LD (HL),D + INC HL + LD (HL),D + INC HL + AND A +PIC_FN2_NO2: + XOR A + CP B + JR Z,PIC_FN2_NO4 +PIC_FN2_4: + LD (HL),D + INC HL + LD (HL),D + INC HL + LD (HL),D + INC HL + LD (HL),D + INC HL + DJNZ PIC_FN2_4 +PIC_FN2_NO4: + + EX AF,AF' + OUT (SLOT1),A + XOR A + OUT (PORT_Y),A + RET + +;************************************************************************ +; вход: dE - вертикаль, HL - горизонталь. +; A',HL' - адрес данных во второй странице ! +; BC' - длина данных +; ВЫВОД ЛИНИИ ТОЧЕК +PIC_FN3: + IN A,(SLOT3) + LD C,A + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,C + LD (SYS_PAGE.COPY_SLOT3),A + IN A,(SLOT2) + LD (SYS_PAGE.COPY_SLOT2),A + IN A,(SLOT1) + LD (SYS_PAGE.COPY_SLOT1),A + + LD A,B + ADD A,#50 + OUT (SLOT1),A + + BIT 0,B + LD BC,#40 + #4000 + JR Z,PIC_FN3_NO_2ND + LD BC,#40 + 320 + #4000 +PIC_FN3_NO_2ND: + ADD HL,BC + + LD A,E + OUT (PORT_Y),A + + LD A,H + EXX + LD D,A + EXX + LD A,L + EXX + LD E,A + EXX + + EX AF,AF' + OUT (SLOT2),A + EX AF,AF' + LD HL,SYS_PAGE.RAM_TABLE + LD L,A + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(HL) + OUT (SLOT3),A + EXX + LDIR + BIT 6,H + JR Z,PIC_FN3_NO + RES 6,H + EX AF,AF' +PIC_FN3_NO: + EXX + + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(SYS_PAGE.COPY_SLOT1) + OUT (SLOT1),A + LD A,(SYS_PAGE.COPY_SLOT2) + OUT (SLOT2),A + LD A,(SYS_PAGE.COPY_SLOT3) + OUT (SLOT3),A + + XOR A + OUT (PORT_Y),A + RET + +;************************************************************************** +;PIC_FN4: +; вход: HL - данные палитры RGB, E - начальный цвет +; D - число цветов, B - PAL-mask, A - page PAL +PIC_SET_PAL: + PUSH IX + + EX AF,AF' + IN A,(PORT_Y) + PUSH AF ; сохранить положение PORT_Y + LD A,E + OUT (PORT_Y),A ; начальный цвет в порт + LD A,D ; сохранить число цветов + EX AF,AF' ; вернуть страницу PAL + + BIT 7,H ; проверить адрес данных + LD C,SLOT3 ; если ниже 8000h + LD D,#C3 ; то граф.экран на странице 3 + JR Z,.NO_PAGE1 + LD D,#43 ; иначе + LD C,SLOT1 ; на странице 1 +.NO_PAGE1: + ADD A,A + PUSH AF + + ADD A,A + AND #1C + XOR #E0 ; младший байт адреса PAL + LD E,A ; DE - адрес в видео-ОЗУ + PUSH DE + POP IX ; адрес палитры + + LD D,B ; маска PAL + EX AF,AF' ; вернуть число цветов + LD B,A ; число цветов + + IN E,(C) ; сохранить страницу 3 + LD A,#50 ; страница графического RAM + OUT (C),A + + POP AF + JR C,PIC_GET_PAL + ; цикл установки цветов палитры +.loopPal: + LD A,(HL) ; B + AND D + LD (IX+2),A + INC HL + + LD A,(HL) ; G + AND D + LD (IX+1),A + INC HL + + LD A,(HL) ; R + AND D + LD (IX+0),A + INC HL + + LD A,(HL) ; Y + AND D + LD (IX+3),A + INC HL + + IN A,(PORT_Y) + INC A + OUT (PORT_Y),A + DJNZ .loopPal ; выполнять, пока не 0 + +.exit: OUT (C),E ; восстановить страницу 3 + POP AF + OUT (PORT_Y),A ; восстановить Y_PORT + POP IX + AND A + RET + +PIC_GET_PAL: + ; цикл чтения цветов палитры +.loopPal: + LD A,(IX+2) + LD (HL),A ; B + INC HL + + LD A,(IX+1) + LD (HL),A ; G + INC HL + + LD A,(IX+0) + LD (HL),A ; R + INC HL + + LD A,(IX+3) + LD (HL),A ; Y + INC HL + + IN A,(PORT_Y) + INC A + OUT (PORT_Y),A + DJNZ .loopPal ; выполнять, пока не 0 + + JR PIC_SET_PAL.exit + +;******************************************************************** +PIC_FN5: ; УСТАНОВКА СТРАНИЦЫ MODE + LD A,E + AND 1 + OUT (RGMOD),A + RET +;******************************************************************* +; Установка внутренней палитры +; A - page_pal, E - номер палитры, B - тип палитры +SET_PAL_INIT: + LD D,A + DEC B + JP Z,SET_GRAPH_PALETTE + DEC B + JP Z,SET_TXT_PALETTE.ZX + DEC B + JP Z,SET_TXT_PALETTE.IBM + +; LD IX,PAL_DAT1 +; JR Z,PIC_FN6_L1 +; DEC B +; LD IX,PAL_DAT +; JR Z,PIC_FN6_L1 + + SCF + RET + +;PIC_FN6_L1: +; AND 3 +; ADD A,A +; ADD A,A +; ADD A,#E0 +; LD L,A +; LD H,#43 +; IN A,(SLOT1) +; PUSH AF +; +; LD A,#50 +; OUT (SLOT1),A +; XOR A +; OUT (PORT_Y),A +; EX AF,AF' +; call PAL_LOOP_M +; +; POP AF +; OUT (SLOT1),A +; XOR A +; OUT (PORT_Y),A +; +; RET + +;****************************************************************** +; Рисование линии. +; dЕ - вертикаль, HL - горизонталь +; H' - высота, C'/DE',B' - add_parameters +; A - color ;!FIXIT заменить сразу на D? +PIC_FN7: + LD D,A + IN A,(SLOT1) + PUSH AF + + LD A,B + ADD A,#50 + OUT (SLOT1),A + + BIT 0,B + LD BC,#40+#4000 ;!HARDCODE screen + JR Z,.no_2nd + LD BC,#40+320+#4000 ;!HARDCODE screen +.no_2nd: + ADD HL,BC + LD A,E + +.loop: OUT (PORT_Y),A ; страница видео-ОЗУ + LD (HL),D + + EXX + EX AF,AF' + + DEC H + JR Z,.exit + + LD A,C ; NEXT HORIZONTAL + ADD A,B + LD C,A + LD A,E + EXX + + ADC A,L + LD L,A + + EXX + LD A,D + EXX + + ADC A,H + LD H,A + INC E ; NEXT VERTICAL + EX AF,AF' + INC A + JR .loop + +.exit: EXX + POP AF + OUT (SLOT1),A + XOR A + OUT (PORT_Y),A + RET + +;****************************************************************** +; Рисование линии. +; dЕ - вертикаль, HL - горизонталь +; H' - высота, C'/DE',B' - add_parameters +; (IX) - colors +PIC_FN8: + IN A,(SLOT1) + PUSH AF + + LD A,B + ADD A,#50 + OUT (SLOT1),A + + BIT 0,B + LD BC,#40+#4000 ;!HARDCODE screen + JR Z,.no_2nd + LD BC,#40+320+#4000 ;!HARDCODE screen +.no_2nd: + ADD HL,BC + LD A,E + +.loop: OUT (PORT_Y),A ; страница видео-ОЗУ + LD D,(IX) + INC IX + LD (HL),D + + EXX + EX AF,AF' + + DEC H + JR Z,.exit + + LD A,C ; NEXT HORIZONTAL + ADD A,B + LD C,A + LD A,E + EXX + + ADC A,L + LD L,A + + EXX + LD A,D + EXX + + ADC A,H + LD H,A + + INC E ; NEXT VERTICAL + + EX AF,AF' + INC A + JR .loop + +.exit: EXX + POP AF + OUT (SLOT1),A + XOR A + OUT (PORT_Y),A + RET + +;************************************************** +; Вывод спрайта на экран +; HL - горизоталь, dE - вертикаль +; A',HL' - адрес данных +PIC_FN9: + +;********************************* +; HL,E - координаты D - color +; B - Magnify +PIC_FN10: +PIC_FN11: +PIC_FN12: +PIC_FN13: +PIC_FN14: +PIC_FN15: + SCF + RET +;************************************ + + +;************************************ +; SYCLES EQU 0 +; ;START EQU 1 +; ST1 EQU 2 +; DPAL1 EQU 3 +; ST2 EQU 4 +; DPAL2 EQU 5 + +; MACRO NEXT_LIN_H +; EX AF,AF' +; INC A +; OUT (PORT_Y),A +; EX AF,AF' +; ENDM + +; MACRO NEXT_LIN_HP +; EX AF,AF' +; INC A +; OUT (PORT_Y),A +; JR NZ,.MD_NO_INC_H +; INC L +; .MD_NO_INC_H: +; EX AF,AF' +; ENDM + +;**************************************** +; Загрузка режима экрана. +;**************************************** + +; CALL SINC_DEF +; CALL SET_TXT_PALETTE.ZX +; RET + +;**************************************** + +;!TODO тут функция +CL0 EQU 200 +CL1 EQU 240 + + +SET_TXT_PALETTE: +.IBM: LD DE,#8000 + JR .TXT + ; +.ZX: LD DE,0 +.TXT: PUSH IX + IN A,(PORT_Y) + PUSH AF + IN A,(SLOT3) + EX AF,AF' + LD A,#50 + OUT (SLOT3),A + ; + LD IX,#C3F0 ; !HARDCODE адрес палитры? +.generate_loop: + CALL GENERATE_PAL1 + LD A,E + OUT (PORT_Y),A + LD (IX),L ; R + LD (IX+1),B ; G + LD (IX+2),C ; B + LD (IX+3),H ; i ? + INC E + JR NZ,.generate_loop + ; + LD BC,4 + ADD IX,BC + INC D + LD A,D + AND 3 + JR NZ,.generate_loop + ; + EX AF,AF' + OUT (SLOT3),A + POP AF + OUT (PORT_Y),A + POP IX + RET + +; генерация спектрумовской палитры. +; Вход: E - атрибут, D - номер палитры +; ВЫХОД: L - red, B - green, C - blue, H - intensity +GENERATE_PAL1: XOR A + LD C,A + LD B,A + LD L,A + BIT 7,D + JR NZ,GENERATE_IBM + BIT 1,D + JR NZ,.FLH +.NOF: BIT 0,D + JR Z,.PAPER +.INK: LD A,CL0 + BIT 6,E + JR Z,.NOI1 + LD A,CL1 +.NOI1: BIT 0,E ; BLUE + JR Z,.NO1 + LD C,A +.NO1: BIT 1,E ; RED + JR Z,.PP_NO2 + LD L,A +.PP_NO2: BIT 2,E ; GREEN + JR Z,.PP_NO6 + LD B,A +.PP_NO3: JR .PP_NO6 +; +.FLH: BIT 7,E + JR Z,.NOF + BIT 0,D + JR Z,.INK +.PAPER: LD A,CL0 + BIT 6,E + JR Z,.NOI2 + LD A,CL1 +.NOI2: BIT 3,E ; BLUE + JR Z,.PP_NO4 + LD C,A +.PP_NO4: BIT 4,E ; RED + JR Z,.PP_NO5 + LD L,A +.PP_NO5: BIT 5,E ; GREEN + JR Z,.PP_NO6 + LD B,A +.PP_NO6: LD A,C + AND A + RRA + ADD A,L + RRA + ADD A,B + RRA + LD H,A ; B/W mode + RET +;**************************************** + +GENERATE_IBM: + BIT 7,E + JR Z,.NO_FLH + BIT 1,D + JR Z,.PAPER +.NO_FLH: + BIT 0,D + JR Z,.PAPER +.INK: +.NO_INTENS: + LD A,#A8 +.INTENS: + BIT 0,E ; BLUE + JR Z,.PPI_NO4 + LD C,A +.PPI_NO4: + BIT 2,E ; RED + JR Z,.PPI_NO5 + LD L,A +.PPI_NO5: + BIT 1,E ; GREEN + JR Z,.PPI_NO6 + LD B,A +.PPI_NO6: + LD A,E + AND #0F + CP 6 + JR NZ,.no_correct + LD B,#54 +.no_correct: + BIT 3,E + JR Z,GENERATE_PAL1.PP_NO6 + + LD A,#54 + ADD A,C + LD C,A + LD A,#54 + ADD A,B + LD B,A + LD A,#54 + ADD A,L + LD L,A + JR GENERATE_PAL1.PP_NO6 +.PAPER: + LD A,#A8 + BIT 4,E ; BLUE + JR Z,.PPI_NO4X + LD C,A +.PPI_NO4X: + BIT 6,E ; RED + JR Z,.PPI_NO5X + LD L,A +.PPI_NO5X: + BIT 5,E ; GREEN + JR Z,.PPI_NO6X + LD B,A +.PPI_NO6X: + LD A,E + AND #70 + CP #60 + JR NZ,GENERATE_PAL1.PP_NO6 + LD B,#54 + JR GENERATE_PAL1.PP_NO6 +;**************************************** + +;**************************************** +;**************************************** + +; D - номер графической палитры +SET_GRAPH_PALETTE: + PUSH IX + IN A,(PORT_Y) + PUSH AF + + IN A,(SLOT3) + EX AF,AF' + LD A,#50 + OUT (SLOT3),A + + + LD IX,#C3E0 + LD A,D + AND 3 + ADD A,A + ADD A,A + LD E,A + LD D,0 + ADD IX,DE + + LD E,0 + + XOR A + LD B,A + LD C,A + LD L,A + LD H,A + +SET_PAL_GR1: + LD A,E + OUT (PORT_Y),A + + LD (IX),L + LD (IX+1),B + LD (IX+2),C + LD (IX+3),H + + CALL GENERATE_PAL3 + + INC E + LD A,E + CP 40 + JR NZ,SET_PAL_GR1 + + XOR A + LD B,A + LD C,A + LD L,A + LD H,A + +SET_PAL_GR2: + LD A,E + OUT (PORT_Y),A + + LD (IX),L + LD (IX+1),B + LD (IX+2),C + LD (IX+3),H + + CALL GENERATE_PAL2 + + INC E + JR NZ,SET_PAL_GR2 + + EX AF,AF' + OUT (SLOT3),A + POP AF + OUT (PORT_Y),A + POP IX + RET +; +;;********************************* +; + +GENERATE_PAL3: ; gray-scale + LD A,B + ADD A,6 + LD B,A + LD C,A + LD L,A + + LD A,C + AND A + RRA + ADD A,L + RRA + ADD A,B + RRA + LD H,A + + RET + +GENERATE_PAL2: ; C - BLUE; L - RED; B - GREEN; H - INTENSITY + LD A,C + ADD A,50 + LD C,A + JR NC,GEN_PAL2_L1 + LD C,0 + LD A,L + ADD A,50 + LD L,A + JR NC,GEN_PAL2_L1 + LD L,0 + LD A,B + ADD A,50 + LD B,A + JR NC,GEN_PAL2_L1 + LD B,0 + +GEN_PAL2_L1: + LD A,C + AND A + RR A + ADD A,L + RR A + ADD A,B + RR A + LD H,A + + RET +; +;************************************ + +FN_SYNC: BIT 7,A + JR Z,.old_mode + ; + LD H,A + AND #60 ; check reserved bits + JR NZ,.error + ; + BIT 2,H ; Set V-Sinc? + JR NZ,.set_v_sinc + ; + BIT 4,H ; Set Waits? + JR Z,.error ; Error - no parameters + ; +.set_waits: LD A,H + AND 8 ; check waits. Z - no waits, NZ - waits + LD H,Port_All_Mode.DEFAULT + JR Z,.no_change + LD H,Port_All_Mode.DEFAULT-Port_All_Mode.MEM_WAITS_OFF +.no_change: LD BC,(Port_All_Mode) + IN A,(C) + AND H + OUT (C),A + RET + ; +.set_v_sinc: LD A,H + AND 3 + JR Z,.SetDefLines + DEC A + JR Z,.SetCmosLines + DEC A + JR Z,.Set320Lines + ;JR .Set312Lines +.set312lines: LD A,Port_VSYNC.SET_312L + OUT (Port_VSYNC),A + ; + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + LD A,(SYS_PAGE.VSyncAndWaits) + AND 2 + LD (SYS_PAGE.VSyncAndWaits),A + OUT (C),B + ; +.end_set_v_sinc: + BIT 4,H + RET Z + JR .set_waits + ; +.Set320Lines: LD A,Port_VSYNC.SET_320L + OUT (Port_VSYNC),A + ; + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + LD A,(SYS_PAGE.VSyncAndWaits) + OR 1 + LD (SYS_PAGE.VSyncAndWaits),A + OUT (C),B + JR .end_set_v_sinc + ; +.SetCmosLines: LD D,CMOS_CELL.ScreenSET + CALL CMOS_RD + ; + AND high CMOS_CELL.ScreenSET.Mask.Sinc ; в регистре A значение ScreenSET + JR Z,.SetDefLines + ; + BIT 6,A + JR Z,.set312lines + JR .Set320Lines + ; +.old_mode: AND A + JR Z,.INT_DEF + DEC A + JR Z,.INT_SCORP + DEC A + JR Z,.INT_PENT + DEC A + JR Z,.INT_ORIG + DEC A + JR Z,.INT_CMOS_SINC + ; [x] кастомный экран по таблице пользователя + DEC A + JR Z,.PROG_SCR + ; +.error: SCF + RET + ; +.SetDefLines: LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + LD A,(SYS_PAGE.VSyncAndWaits) + OUT (C),B + AND 1 + JR Z,.set312lines + JR .Set320Lines + ; +.INT_DEF: LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + LD DE,(SYS_PAGE.SCREEN_TABLE) + OUT (C),B + ; + CALL Test_SCREEN_TABLE + JR NZ,.INT_CMOS_SINC + JP (IX) + ; +.INT_CMOS_SINC: LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + LD DE,(SYS_PAGE.SCREEN_TABLE) + OUT (C),B + ; + LD D,CMOS_CELL.ScreenSET + CALL CMOS_RD + ; + AND high CMOS_CELL.ScreenSET.Mask.Int ; в регистре A значение ScreenSET + JR NZ,.skiptest + ; + CALL Test_SCREEN_TABLE + JP (IX) ; default int (non CMOS) + ; +.skiptest: CP #10 + JR Z,.INT_SCORP ; scorpion int + ; + CP #20 + JR Z,.INT_PENT ; pentagon int + ; + ;JR .INT_ORIG ; original int +.INT_ORIG: LD IX,SCREEN_TABLES.ORIGINAL + JR .PROG_SCR + ; +.INT_SCORP: LD IX,SCREEN_TABLES.SCORPION + JR .PROG_SCR + ; +.INT_PENT: LD IX,SCREEN_TABLES.PENTAGON + ;JR .PROG_SCR +.PROG_SCR: IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + EX AF,AF' + LD (SYS_PAGE.COPY_SLOT3),A + IN A,(PORT_Y) + LD (SYS_PAGE.COPY_RGADR),A + ; + LD (SYS_PAGE.SCREEN_TABLE),IX + XOR A +;----[START]-----------------------[? 1] +.loop_1: OUT (PORT_Y),A + EX AF,AF' + LD A,#50 + OUT (SLOT3),A + LD HL,#C300 +;----[START]------------------[v 2]----- +.loop_2: LD C,(IX) +;----[START]-------------[v 3]---------- +.loop_3: ; взять адрес данных для записи в служебную область экрана + LD E,(IX+1) ; take adress of line X + LD D,(IX+2) +;----[START]--------[v 4]--------------- +.loop_4: LD A,(DE) ; take counter in table 1, line X, column Y + INC DE + AND A + JR Z,.loop_4_exit ; exit if zero-counter + LD B,A + LD A,(DE) + INC DE +;----[START]---[v 5]-------------------- +.loop_5: LD (HL),A + INC L + LD (HL),0 + INC L + LD (HL),0 + ; + EX AF,AF' + INC A + OUT (PORT_Y),A + EX AF,AF' + ; + LD (HL),0 + DEC L + LD (HL),0 + DEC L + LD (HL),A + ; + EX AF,AF' + INC A + OUT (PORT_Y),A + EX AF,AF' + ; + DJNZ .loop_5 +;--------------[^ 5]-------------------- + JR .loop_4 +;-------------------[^ 4]--------------- +.loop_4_exit: INC HL ; next line + INC HL + INC HL + INC HL + IN A,(PORT_Y) + AND #80 + OUT (PORT_Y),A + DEC C + JR NZ,.loop_3 +;------------------------[^ 3]---------- + INC IX ; next counter + INC IX + INC IX + LD A,(IX) + AND A + JR NZ,.loop_2 +;-----------------------------[^ 2]----- + LD A,SYS_PAGE + OUT (SLOT3),A + LD IX,(SYS_PAGE.SCREEN_TABLE) + ; + EX AF,AF' + ADD A,#80 + JR NC,.loop_1 +;----------------------------------[^ 1] + ; Exit + LD A,(SYS_PAGE.COPY_RGADR) + OUT (PORT_Y),A + LD A,(SYS_PAGE.COPY_SLOT3) + OUT (SLOT3),A +.exit: OR A + RET + ; + ;DE - содержимое SYS_PAGE.SCREEN_TABLE +Test_SCREEN_TABLE: + LD HL,SCREEN_TABLES.SCORPION + AND A + SBC HL,DE + LD IX,FN_SYNC.INT_SCORP + RET Z + ; + LD HL,SCREEN_TABLES.ORIGINAL + AND A + SBC HL,DE + LD IX,FN_SYNC.INT_ORIG + RET Z + ; + LD HL,SCREEN_TABLES.PENTAGON + AND A + SBC HL,DE + LD IX,FN_SYNC.INT_PENT + RET Z + AND A + RET +;--- Screen data table 1: counter1, data1 .. counterX, dataX +SCREEN_TABLES: +; | число | значения | +; | строк | в | +; | /2 | строках | +.SCR: DB 41 , #F8 + DB 3 , #FC + DB 4 , #FC + DB 7 , #FC + DB 9 , #F8 + DB 0 + +;.SCR: DB 41,#F8, 3,#FC, 4,#FC, 7,#FC, 9,#F8, 0 +.INT: DB 40,#FC, 2,#FD, 6,#FC, 7,#FC, 9,#FC, 0 +.INT_SC: DB 41,#F8, 1,#FD, 6,#FC, 7,#FC, 9,#F8, 0 +.BLN: DB 41,#FC, 3,#FC, 4,#FC, 7,#FC, 9,#FC, 0 +.SNC: DB 41,#FC, 3,#FC, 4,#FC, 7,#FC, 9,#FC, 0 +.RES: DB 41,#F8, 3,#FE, 4,#FE, 7,#FE, 9,#F8, 0 +;--------------------------------------- + +;--- Screen data tables 2: counter1, data address1 .. counterX, data addressX +; +; | кол-во | значения | +; | строк | в | +; | | строке | +.PENTAGON: DB 33 : DW .SCR + DB 1 : DW .INT ; DW .BLN + DB 3 : DW .SNC + DB 1 : DW .BLN + DB 1 : DW .SCR + DB 1 : DW .RES + DB 0 ; end +.SCORPION: DB 31 : DW .SCR + DB 1 : DW .INT_SC + DB 1 : DW .SCR + DB 1 : DW .SNC + DB 3 : DW .SNC + DB 1 : DW .BLN + DB 2 : DW .RES + DB 0 ; end +.ORIGINAL: DB 33 : DW .SCR + DB 1 : DW .SNC + DB 1 : DW .INT + DB 2 : DW .SNC + DB 1 : DW .BLN + DB 1 : DW .SCR + DB 1 : DW .RES + DB 0 ; end +;--------------------------------------- + +;************************************ +; +; Экранные таблицы +; +;текстовое окно 80x32 +LP_SCR_80: + DB 40,32,0,0,%0001'1011,0,0,0 + BLOCK 8,0 + +;текстовое окно 40x32 +LP_SCR_40: + DB 40,32,0,0,%0111'1011,0,0,0 + BLOCK 8,0 + +;спектрумовское окно 32x24 +LP_SCR_32: + DB 32,24,4,4,%0011'0000,1,0,0 + BLOCK 8,0 + +;текстовое окно 64x24 +LP_SCR_64: + DB 32,24,4,4,%1001'1011,0,0,0 + BLOCK 8,0 + +;графическое окно 0 +PIC_320X256_1: + DB 40,32,0,0,%0010'0000,0,8,0 + BLOCK 8,0 + +;графическое окно 1 +PIC_320X256_2: + DB 40,32,0,0,%0110'0000,0,48,0 + BLOCK 8,0 + +;************************************ +; + + diff --git a/src/bios/exp/FUNC_SERVICE.asm b/src/bios/exp/FUNC_SERVICE.asm index b7e8dbd..a766644 100644 --- a/src/bios/exp/FUNC_SERVICE.asm +++ b/src/bios/exp/FUNC_SERVICE.asm @@ -1,238 +1,637 @@ ; DISPLAY "Service" ; !FIXIT тут можно, походу, дохрена убрать -; страницы с конфой для Sp97, для совместимости с древними прогами -PG_SP1 equ #EC -PG_SP2 equ #EE -PG_AY equ #EA +; ; страницы с конфой для Sp97, для совместимости с древними прогами +; PG_SP1 equ #EC +; PG_SP2 equ #EE +; PG_AY equ #EA +; ; + +; ;!TODO замутить заливку конфы, рестарт, перехват ресета силами BIOS +; PG_Sp2000 EQU #FE +; PG_Sp2000_REINIT EQU #FD ; -;!TODO замутить заливку конфы, рестарт, перехват ресета силами BIOS -PG_Sp2000 EQU #FE -; RST_CONF: ;--[] ZX Spectrum -.AY8910: - LD D,#35 ;!HARDCODE выяснить за что раньше эта ячейка в кмос отвечала. похоже на хранение значения Port_All_Mode или CONFIG_DE+1 - CALL CMOS_RD - OR 1 - CALL CMOS_WR - - LD BC,Port_All_Mode - IN A,(C) - AND #FE ;!HARDCODE - OUT (C),A ; ACC_OFF - - LD A,PG_AY - - LD DE,#FFFC - JR .INT_PLD +.AY8910: CALL .ACC_OFF + LD DE,ACEX.Config_ID.Sp97_AY + JR .INT_PLD + ;LD A,CNF_PORT.CNF_1 + ;OUT (SYS_PORT.ON),A + ;RET ;--[] ;--[] Sprinter ZX -.SP97_1: - LD D,#35 ;!HARDCODE выяснить за что раньше эта ячейка в кмос отвечала. похоже на хранение значения Port_All_Mode или CONFIG_DE+1 - CALL CMOS_RD - AND #FE - CALL CMOS_WR - - LD BC,Port_All_Mode - IN A,(C) - AND #FE ;!HARDCODE - OUT (C),A ; ACC_OFF - - LD A,PG_SP1 - LD DE,#FFFE ;!HARDCODE - JR .INT_PLD +.SP97_1: CALL .ACC_OFF + LD DE,ACEX.Config_ID.Sp97_1 + JR .INT_PLD ;--[] ;--[] -.SP97_2: - LD BC,Port_All_Mode - IN A,(C) - OR 1 ; ACC_ON - OUT (C),A - LD A,PG_SP2 - LD DE,#FFFD ;!HARDCODE - JR .INT_PLD +.SP97_2: CALL .ACC_ON + LD DE,ACEX.Config_ID.Sp97_2 + JR .INT_PLD ;--[] + ;--[] -.CUSTOM: - CP #80 - JR NC,.CHOOSE_CNF - ; only for old FLEX10K soft compatible - LD C,SLOT3 - IN B,(C) - OUT (C),A ; PAGE с прошивкой - LD DE,(#C090) ; PLD-ID - OUT (C),B ; RET page -;--[] ;JR INT_PLD +;[x] +.SP2000: CALL .ACC_ON + LD DE,ACEX.Config_ID.Sp2000 + JR .INT_PLD +;--[] + + +;--[] +.CUSTOM: LD C,A + ; устанавливаем нулевую карту портов + LD A,CNF_PORT.CNF_0 + OUT (SYS_PORT.ON),A + LD A,C + ; + CP #80 ; тут теперь может любое число быть у старых прог + JR NC,.CHOOSE_CNF + ; only for old FLEX10K soft compatible +.crutch: LD C,SLOT3 + IN B,(C) + OUT (C),A ; PAGE с прошивкой + LD DE,(#C090) ; PLD-ID + OUT (C),B ; RET page +;--[] ;JR INT_PLD .INT_PLD: ; only for old FLEX10K soft compatible - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (C),A - LD (SYS_PAGE.CONFIG_BYTE),DE - OUT (C),B + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + LD (SYS_PAGE.CONFIG_BYTE),DE + OUT (C),B + ; + LD A,E ; config-byte + CP #FF + LD A,#80 + JR Z,.YES_CBL + XOR A +.YES_CBL: LD BC,SP_SND.CBL.SYS_PORT + OUT (C),A + ; + LD A,E ; config-byte + OR #FE ;!HARDCODE + LD BC,Port_All_Mode ; SYSTEM Spectrum/Sprinter + OUT (C),A + ; + LD A,#3C + OUT (FDC_93.DrvCTRL),A + ; восстанавливаем карту портов - походу, не нужно + ;LD C,SLOT3 + ;IN B,(C) + ; LD A,SYS_PAGE + ; OUT (C),A + ; LD A,(SYS_PAGE.CONFIG_DE.CNF_PORT) + ;OUT (C),B + ;OUT (SYS_PORT.ON),A + XOR A + RET + ; + ;[x] +.CHOOSE_CNF: ; [x] bug with "free zx pages" + LD A,high ZX_MEM_PORT.Scorpion + IN A,(ZX_MEM_PORT) + RRCA + LD A,C + JR C,.not_vRAM_page + ; + IN A,(SLOT3) + CP C + LD A,C + JR Z,.crutch + ; [x] +.not_vRAM_page: CP ACEX.Config_PG.Sp2000_SoftRestartNow + JP Z,.ReturnSoftReset + ; + CP ACEX.Config_PG.Sp2000_AcexSetUpNow + JR Z,.INIT_ACEX + ; + CP ACEX.Config_PG.Sp2000_SetUp + JR Z,.SP2000 + ; + CP ACEX.Config_PG.Sp2000_SoftRestartSet + JR Z,.SetUpSoftReset + ; + CP ACEX.Config_PG.Sp2000_AcexSetUpSet + JR Z,.SetUpHardReset + ; + ; only for old FLEX10K soft compatible + CP ACEX.Config_PG.Sp97_1 + LD DE,ACEX.Config_ID.Sp97_1 + JR Z,.INT_PLD + ; + CP ACEX.Config_PG.Sp97_2 + LD DE,ACEX.Config_ID.Sp97_2 + JR Z,.INT_PLD + ; + CP ACEX.Config_PG.Sp97_AY + LD DE,ACEX.Config_ID.Sp97_AY + JR Z,.INT_PLD + SCF + RET + ; +; B - ID рамблока с bitstream + ;[x] +.INIT_ACEX: LD C,B + LD B,high BIOS.REINIT.HARD_RESET + CALL .PrepareResetSetUp + LD B,C + CALL .PrepareHardReset + JR C,.INIT_ACEX.ERROR + LD B,high BIOS.REINIT.HARD_RESET + JR .set_ret_addr + +; DI +; IN A,(SLOT3) ; сохраняем номер воткнутой страницы +; PUSH AF +; LD A,Spec_Page +; OUT (SLOT3),A +; ; проверяем размер блока с конфой и получаем страницы конфы +; LD HL,Spec_Page.bitstream_pages +; LD A,B +; AND A +; JR Z,.INIT_ACEX.ReloadConfFromROM +; ; +; CALL EMM.GetMemBlkPages +; LD A,B +; JR C,.INIT_ACEX.ERROR +; CP BitStream_SizeInPages+1 ; количество страниц в кэш для бистрима плюс одна +; JR NC,.INIT_ACEX.ERROR +; LD A,(Spec_Page.bitstream_pages) +; INC A +; JR Z,.INIT_ACEX.ERROR +; ; +; .INIT_ACEX.ReloadConfFromROM: +; ; закидываем в Spec_Page прогу для заливки конфы +; LD HL,.INIT_ACEX.PROGRAM +; LD DE,Spec_Page.init_acex +; LD BC,.INIT_ACEX.PROGRAM.Size +; LDIR +; ; если ZF=0, то процедура сделает ресет с перезаливкой из BIOS, иначе из КЭШ +; CALL Spec_Page.init_acex +; LD B,high BIOS.REINIT.HARD_RESET +; POP HL +; ; +; ;вход: B - параметр функции BIOS REINIT +; ; H - Spec_Page.page_3 +; .INIT_ACEX.ifSoftreset: +; ; сохраняем воткнутые страницы в Spec_Page +; IN A,(SLOT0) +; LD E,A +; IN A,(SLOT1) +; LD D,A +; IN A,(SLOT2) +; ;POP HL ; восстанавливаем номер воткнутой страницы +; LD L,A +; LD (Spec_Page.page_0),DE +; LD (Spec_Page.page_2),HL +; ; +; ; достаём адрес возврата в вызывающую функцию и сохраняем в Spec_Page +; POP DE +; LD HL,RST_18_1.exit +; XOR A +; SBC HL,DE +; JR NZ,.set_ret ; NZ - если вызов был по RST #18 +; POP DE ; если вызов был в ОЗУ по RST 8 +; INC A +; .set_ret: LD (Spec_Page.RET_addr),DE +; ; A=0 - SYS_PORT.ON +; ; A=1 - SYS_PORT.OFF +; LD (Spec_Page.Reload_Version),A +; LD (Spec_Page.Stack_Point),SP +; ; +; LD A,high BIOS.REINIT.HARD_RESET +; CP B +; JR NZ,.reinit +; ; Устанавливаем ключи для HARD reset +; LD HL,Spec_Page.flag_R +; LD (HL),"R" +; INC HL +; LD (HL),"S" +; INC HL +; LD (HL),"T" +; ; +; ; .. ... ... .. +; ;LD BC,BIOS.REINIT.HARD_RESET +; .reinit: JP REINIT + ; +.SetUpHardReset: + LD C,B + LD B,high BIOS.REINIT.HARD_RESET + CALL .PrepareResetSetUp + LD (Spec_Page.RET_addr),DE + LD A,#FF + LD (Spec_Page.Reload_Version),A + LD B,C + CALL .PrepareHardReset + JR .INIT_ACEX.ERROR ; нормальный выход в данном случае + ; +.ReturnSoftReset: + CALL .PrepareSoftReset + CALL .PrepareResetSetUp + ; достаём адрес возврата в вызывающую функцию и сохраняем в Spec_Page +.set_ret_addr: POP DE + LD HL,RST_18_1.exit + XOR A + SBC HL,DE + JR NZ,.set_ret ; NZ - если вызов был по RST #18 + POP DE ; если вызов был в ОЗУ по RST 8 + INC A +.set_ret: LD (Spec_Page.RET_addr),DE + ; A=0 - SYS_PORT.ON + ; A=1 - SYS_PORT.OFF + LD (Spec_Page.Reload_Version),A + LD (Spec_Page.Stack_Point),SP + JP REINIT + ; +.SetUpSoftReset: + PUSH DE + CALL .PrepareSoftReset + CALL .PrepareResetSetUp + POP DE + LD (Spec_Page.RET_addr),DE + LD A,#FF + LD (Spec_Page.Reload_Version),A + LD A,(Spec_Page.page_3) + OUT (SLOT3),A + RET - LD A,E ; config-byte - CP #FF - LD A,128 - JR Z,.YES_CBL - XOR A -.YES_CBL: - LD BC,CBL.SYS_PORT - OUT (C),A + ; DI + ; LD A,ACEX.RET_PORT + ; LD B,Spec_Page + ; CALL SET_PORTS + ; ; + ; ; и так понятно что делает + ; IN A,(SLOT3) ; сохраняем номер воткнутой страницы + ; LD H,A + ; LD A,Spec_Page + ; OUT (SLOT3),A + ; ; + ; LD B,high BIOS.REINIT.SOFT_RESET + ; JR .INIT_ACEX.ifSoftreset + ; + ;;; +.INIT_ACEX.ERROR: + LD A,(Spec_Page.page_3) + OUT (SLOT3),A + ;SCF + RET +; +;--[] +.ACC_OFF: LD BC,Port_All_Mode + IN A,(C) + AND Port_All_Mode.DEFAULT - Port_All_Mode.SPECTRUM_MODE_OFF + OUT (C),A + RET + ; +.ACC_ON: LD BC,Port_All_Mode + IN A,(C) + OR 1 ; ACC_ON + OUT (C),A + RET +;--[] +; +.INIT_ACEX.PROGRAM: + DISP Spec_Page.init_acex + ; + SAFE_PORTY + IN A,(FastRAM.ON) + ; IN A,(SLOT1) + ; LD (.slot1_page),A + ; + LD A,#FE ; чтоб проверить, что вызывать после CALL NZ,.INIT_ACEX.PROGRAM.LOAD + ; тут ZF должен быть из вызывающей процедуры + CALL NZ,.INIT_ACEX.PROGRAM.LOAD ; если RAM_BLOCK ID не равен 0, то выполняется + INC A ; флаг ZF=0 грузим из ROM + ; +.INIT_ACEX.PROGRAM.SET_KEYS: + LD A,3 + OUT (FastRAM.SLOT0),A ; Страница КЭШ = 3 + ; + LD HL,.INIT_ACEX.Reload_String ; флаг перезагрузки из КЭШ-а + JR Z,.skip ; устанавливаем флаг перезагрузки из КЭШ-а + INC L ; затираем флаг перезагрузки из КЭШ-а +.skip: LD DE,ACEX.LOADER.String_Address-#C000 + LD BC,#10 + LDIR - LD A,E ; config-byte + LD HL,#FFFF ; залить конфу только при первой перезагрузке + ;LD HL,ACEX.LOADER.Reload_Flag ; заливать конфу при каждой перезагрузке + LD (ACEX.LOADER.Reload_Flag_Address-#C000),HL + ; +.INIT_ACEX.PROGRAM.END: + XOR A + OUT (FastRAM.SLOT0),A + IN A,(FastRAM.OFF) +; .slot1_page+1: LD A,0 + LD A,(Spec_Page.page_1) + OUT (SLOT1),A + RET + ; + ; +.INIT_ACEX.PROGRAM.LOAD: + XOR A ; страница КЭШ + LD HL,Spec_Page.bitstream_pages + OUT (FastRAM.SLOT0),A ; Страница КЭШ = 0 + INC A +.INIT_ACEX.PROGRAM.load_loop: + EX AF,AF' + LD A,(HL) + INC HL + CP #FF + RET Z + OUT (SLOT1),A ; страница с данными файла + EX AF,AF' + ; + ; перекидывание #3000 байтов в КЭШ(0) = #1000 + EXX + LD HL,#4000 + LD DE,#1000 + LD BC,#3000 + LDIR + ; докидывание #1000 байтов в КЭШ(1) = #0000 + ; HL = #7000 + OUT (FastRAM.SLOT0),A ; Страница КЭШ = 1 + INC A + ; + LD D,C ; LD DE,0 + LD B,#10 ; LD BC,#1000 + LDIR + EXX + JR .INIT_ACEX.PROGRAM.load_loop - OR #FE ;!HARDCODE - LD BC,Port_All_Mode ; SYSTEM Spectrum/Sprinter - OUT (C),A + +.INIT_ACEX.Reload_String: + DB ACEX.RELOAD_STRING + ; + ENT +.INIT_ACEX.PROGRAM.Size EQU $-.INIT_ACEX.PROGRAM +;--[] +.PrepareSoftReset: + LD A,ACEX.RET_PORT + LD B,Spec_Page + CALL SET_PORTS + LD B,high BIOS.REINIT.SOFT_RESET + RET - LD A,#3C - OUT (FDC_93.DrvCTRL),A - - XOR A - RET - -.CHOOSE_CNF: - ;!TEST - CP PG_Sp2000 - LD DE,SP2000_ConfID - JR Z,.INIT_ACEX - ; - - ; only for old FLEX10K soft compatible - CP PG_SP1 - LD DE,#FFFE ;!HARDCODE - JR Z,.INT_PLD - CP PG_SP2 - LD DE,#FFFD - JR Z,.INT_PLD - CP PG_AY - LD DE,#FFFC - JR Z,.INT_PLD - SCF - RET - -.INIT_ACEX: - ; .. ... ... .. - ;!TODO сделать функцию по заливке своей конфы, перехвату ресета. - ; .. ... ... .. - LD BC,256*BIOS.REINIT.HARD_RESET + BIOS.REINIT - JP ToBIOS_18 +.PrepareResetSetUp: + DI + ; сохраняем воткнутые страницы в Spec_Page + IN A,(SLOT3) + LD H,A + LD A,Spec_Page + OUT (SLOT3),A + ; + IN A,(SLOT2) + LD L,A + LD (Spec_Page.page_2),HL + IN A,(SLOT0) + LD (Spec_Page.page_0),A + IN A,(SLOT1) + LD (Spec_Page.page_1),A + ; + LD A,high BIOS.REINIT.HARD_RESET + CP B + LD HL,Spec_Page.flag_R + JR NZ,.kill_flag + ; Устанавливаем ключи для HARD reset + LD (HL),"R" + INC HL +.kill_flag: LD (HL),"S" + INC HL + LD (HL),"T" + RET + ; +; B - ramblock bitstream +.PrepareHardReset: + ; проверяем размер блока с конфой и получаем страницы конфы + LD HL,Spec_Page.bitstream_pages + LD A,B + AND A + JR Z,.INIT_ACEX.ReloadConfFromROM + ; + CALL EMM.GetMemBlkPages + RET C ; ERROR + LD A,BitStream_SizeInPages ; количество страниц в кэш для бистрима + CP B + RET C ; ERROR + LD A,(Spec_Page.bitstream_pages) + INC A + SCF + RET Z ; ERROR + ; +.INIT_ACEX.ReloadConfFromROM: + ; закидываем в Spec_Page прогу для заливки конфы + LD HL,.INIT_ACEX.PROGRAM + LD DE,Spec_Page.init_acex + LD BC,.INIT_ACEX.PROGRAM.Size + LDIR + ; если ZF=0, то процедура сделает ресет с перезаливкой из BIOS, иначе из КЭШ + JP Spec_Page.init_acex +;--[] ;*************************************** -;!TEST + +;[x] ;--------------------------[;!TODO потестить]--------------------------; ; B - параметр сброса ; B = 1 - RESTART. ; B = 2 - Soft reset ; B = 3 - Hard reset -; B = 4 - Reinit spectrum pages -REINIT: DEC B - JR Z,.Restart ;1 - DEC B - JR Z,.SoftReset ;2 - DEC B - JR Z,.HardReset ;3 - DEC B - SCF - RET NZ -.ReinitZXpages: ;4 - LD DE,RESERVED_PAGES ; таблица занятых системных страниц - LD HL,SYS_PAGE.RAMD_FAT ; Адрес FAT ОЗУ. +; B = 4 - Free memory except ZX pages +REINIT: DEC B + JR Z,.Restart ; 1 + DEC B + JR Z,.SoftReset ; 2 + DEC B + JR Z,.HardReset ; 3 + DEC B + SCF + RET NZ + ; ; 4 +.FreeNoZxMem: DI + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + LD (SYS_PAGE.SP_SAVE),SP + LD SP,SYS_PAGE.SYS_SP + PUSH BC + ; чистим буфер + LD HL,SYS_PAGE.SHARED_BUFFER_256b + LD DE,SYS_PAGE.SHARED_BUFFER_256b + 1 + LD BC,255 + LD (HL),0 + LDIR + ; + LD IX,SYS_PAGE.Block_IDs + LD H,high SYS_PAGE.RAM_TABLE + LD D,high SYS_PAGE.SHARED_BUFFER_256b + LD BC,2*256 + #FF ; 2 = vRAM и VROM ID's + CALL SAVE_CHAINS + ; + CALL EMM.InitMem + ; + LD HL,SYS_PAGE.SHARED_BUFFER_256b + LD DE,SYS_PAGE.RAM_TABLE + CALL RESTORE_CHAINS + ; CF=0 + POP BC + LD SP,(SYS_PAGE.SP_SAVE) + OUT (C),B + RET - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (SLOT3),A - - LD A,(DE) -.zxloop: - CP #FF - JR Z,.endzxloop - INC DE - LD L,A - - LD A,(HL) - AND A - JR NZ,.errorzxloop - - LD A,(DE) - LD (HL),A - JR .zxloop - -.errorzxloop: - DEC DE - LD HL,-RESERVED_PAGES-1 - ADD HL,DE - JR NC,.errorzxloop_noChanges - - DEC DE - LD H,high SYS_PAGE.RAMD_FAT - LD A,(DE) - LD L,A - LD A,#FF - LD (HL),A -.errorzxloop_noChanges: - SCF -.endzxloop: - OUT (C),B - RET +;[x] +.Restart: DI + XOR A + LD BC,#1FFD + OUT (C),A + LD B,#7F + OUT (C),A + OUT (RGADR),A + OUT (RGMOD),A + OUT (SLOT0),A + ; [ ] 16/09/24 free zx pages! + ;LD A,5 + ;OUT (SLOT1),A + ;LD A,2 + ;OUT (SLOT2),A + OUT (SLOT2),A + DEC A + OUT (SLOT1),A + ; + LD A,DCP_PAGE + OUT (SLOT3),A + JP 0 ;Restart ; -;!TEST +; +.SoftReset: DI + LD A,#10 + LD BC,#1FFD + OUT (C),A ; 8-я страница !! + ; + LD A,RESET_PAGE + OUT (SLOT3),A + LD A,CNF_PORT.TURBO.OFF + OUT (SYS_PORT.ROM),A +.loop2: LD (#C000),A ; Soft RESET !!! + JR .loop2 +; + +;[x] .HardReset: DI + LD A,SYS_PORT.CNF_0 + OUT (SYS_PORT.ROM),A + ; + LD A,Z84.REG.Misc_Ctrl + OUT (Z84.SYS.Control),A + LD A,%0000'0011 ; CS1/CS0 enabled + OUT (Z84.SYS.Data),A + ; LD A,DCP_PAGE OUT (SLOT1),A ; set DCP page - LD A,Conf_port.RESET + LD A,ACEX.RESET LD (#4400),A ; open for WR .loop: LD BC,#0100 ; цикл сброса OUT (C),C - LD BC,0 + LD B,C OUT (C),C JR .loop ; полностью зациклить! ; +;----------------------------------------------------------------------; +; Вход: H - RAM_TABLE +; D - Buffer for RAM_TABLE +; IX - указатель на последовательность из RAM BLOCK ID +; B - кол-во RAM BLOCK ID в последовательности +; C - #FF (чтоб LDI не ломало DJNZ счётчик) +SAVE_CHAINS: LD A,(IX) + INC IX + OR A + LD L,A + CALL NZ,COPY_CHAIN + DJNZ SAVE_CHAINS + RET +; Вход: H - RAM_TABLE +; L - RAM BLOCK ID +; D - Buffer for RAM_TABLE +COPY_CHAIN: LD E,L + LDI + DEC L + LD L,(HL) + INC L + RET Z + DEC L + JR COPY_CHAIN +;--------------; +; Вход: HL - копия RAM_TABLE откуда копировать +; DE - RAM_TABLE +RESTORE_CHAINS: XOR A +.loop: CP (HL) + JR Z,.NoCopy + LD E,L + LDI + DEC L +.NoCopy: INC L + JR NZ,.loop + RET +;----------------------------------------------------------------------; -;!TEST -.Restart: - DI - LD A,0 - LD BC,#1FFD - OUT (C),A - LD B,#7F - OUT (C),A - LD A,#40 - OUT (SLOT3),A - LD A,5 - OUT (SLOT1),A - LD A,2 - OUT (SLOT3),A - LD A,0 - OUT (SLOT0),A - OUT (RGADR),A - OUT (RGMOD),A - JP 0 ;Restart -; -; -.SoftReset: - DI - LD A,#10 - LD BC,#1FFD - OUT (C),A ; 8-я страница !! +;----------------------------------------------------------------------; +; старый вариант освобождения страниц спектрума через RAM BLK ID 1 +;----------------------------------------------------------------------; +; JR Z,.HardReset ;3 +; DEC B +; .ReinitZXpages: ;4 +; LD DE,RESERVED_PAGES ; таблица занятых системных страниц +; LD HL,SYS_PAGE.RAM_TABLE ; Адрес FAT ОЗУ. + +; LD C,SLOT3 +; IN B,(C) +; LD A,SYS_PAGE +; OUT (SLOT3),A + +; LD A,(DE) +; .zxloop: +; CP #FF +; JR Z,.endzxloop +; INC DE +; LD L,A + +; LD A,(HL) +; AND A +; JR NZ,.errorzxloop + +; LD A,(DE) +; LD (HL),A +; JR .zxloop + +; .errorzxloop: +; DEC DE +; LD HL,-RESERVED_PAGES-1 +; ADD HL,DE +; JR NC,.errorzxloop_noChanges + +; DEC DE +; LD H,high SYS_PAGE.RAM_TABLE +; LD A,(DE) +; LD L,A +; LD A,#FF +; LD (HL),A +; .errorzxloop_noChanges: +; SCF +; .endzxloop: +; OUT (C),B +; RET - LD A,RESET_PAGE - OUT (SLOT3),A - LD A,CNF_PORT.TURBO.OFF + ROM.BIOS - OUT (SYS_PORT.ROM),A -.loop2: LD (#C000),A ; Soft RESET !!! - JR .loop2 -; ;----------------------------------------------------------------------; ; \ No newline at end of file diff --git a/src/bios/exp/FUNC_SYS.ASM b/src/bios/exp/FUNC_SYS.ASM index 6953d9e..1a66800 100644 --- a/src/bios/exp/FUNC_SYS.ASM +++ b/src/bios/exp/FUNC_SYS.ASM @@ -23,27 +23,6 @@ EMM.GetBanksPorts: RET ;84t .error: SCF RET ;74t - -; old version - ; LD C,SLOT0 - ; IN B,(C) - ; AND A - ; RET Z ;34t - ; LD C,SLOT1 - ; IN B,(C) - ; DEC A - ; RET Z ;62t - ; LD C,SLOT2 - ; IN B,(C) - ; DEC A - ; RET Z ;90t - ; LD C,SLOT3 - ; IN B,(C) - ; DEC A - ; RET Z ;118t - ; SCF - ; RET ;150t - ;----------------------------------------------------------------------; ;----------------------------------------------------------------------; @@ -52,143 +31,257 @@ EMM.GetBanksPorts: FN_VERSION: PUSH HL EX DE,HL - LD HL,ID_SPRINTER_length - - ld c,(hl) - inc hl - ld b,0 + ; LD HL,ID_SPRINTER_FullSize + + ; LD B,0 + ; LD C,(HL) + ; INC HL + LD HL,ID_SPRINTER + LD BC,ID_SPRINTER.Size LDIR - + ; POP HL LD DE,(ID_Version) ;rdlow-ok - + ; IN A,(SLOT2) EX AF,AF' LD A,SYS_PAGE OUT (SLOT2),A - LD BC,(SYS_PAGE.CONFIG_BYTE-#4000) ; Version PLD ; !TODO через структуру для переменных биоса + LD BC,(SYS_PAGE.CONFIG_BYTE - #4000) ; Version PLD ; !TODO через структуру для переменных биоса EX AF,AF' OUT (SLOT2),A - LD A,2 ; Число полей + LD A,ID_SPRINTER.Records_Num ; Число полей AND A RET ;----------------------------------------------------------------------; ;----------------------------------------------------------------------; +; [x] 28/01/24 добавлена подфункция выдачи инфы про Acex FN_CRIPT: - DEC B - SCF - RET NZ - LD HL,(ROM_NUMBER.part1) ;rdlow-ok - LD A,(ROM_NUMBER.part2) ;rdlow-ok - LD BC,(BoardID.start) ;rdlow-ok - LD DE,(BoardID.end) ;rdlow-ok - AND A + DJNZ .Acex_ver + ; + ; BoardID_start old address #312A + ; BoardID_end old address #312D +.board_id: + LD HL,(BOARD_INFO.number) ;rdlow-ok + LD A,(BOARD_INFO.type) ;rdlow-ok + LD BC,(BoardID.start) ;rdlow-ok + LD DE,(BoardID.end) ;rdlow-ok + AND A RET -; BoardID_start old address #312A -; BoardID_end old address #312D + ; +.error: LD A,BIOS.Error.InvalidSubFunction + SCF + RET + ; +.Acex_ver: + DJNZ .error + PUSH HL + LD A,R + DI + PUSH AF + ; + LD HL,-.stackDepth - .readProcedure.size ; memory stack use! + ADD HL,SP + PUSH HL ; адрес программы .readProcedure + LD DE,.readProcedure ; перенести программу на стек + EX DE,HL + LD BC,.readProcedure.size + LDIR ; программа на стеке + LD A,+(12 xor %0000'1000) ; !HARDCODE bitstream page in rom + RET +.return:; + POP AF + JP PO,.no_EI + EI +.no_EI: CALL .choose_chip + POP DE + LD BC,.chip_ID_TXT.RecordSize + LDIR +.cnf+1: LD DE,bitstream_ver_hex + AND A + RET + ; +.choose_chip: + XOR A + LD HL, - ACEX.Chip_ID.K30 + ADC HL,DE + LD HL,.chip_ID_TXT.K30 + RET Z + OR A ; снять CF + INC A + LD HL, - ACEX.Chip_ID.K50 + ADC HL,DE + LD HL,.chip_ID_TXT.K50 + RET Z + POP HL ; баланс стека +.error_unknownChip: + SCF + POP HL + LD A,BIOS.Error.UnknownDevice + RET + ; +; процедура, переносимая на стек для чтения Acex ID +; осторожнее с PUSH, если надо много, то увеличивай .stackDepth +.readProcedure: + OUT (ROM.SLOT0),A ; ROM_PAGE + LD DE,(#100 + 3) ; !HARDCODE здесь читается Acex ID + XOR A + OUT (ROM.SLOT0),A + OUT (SYS_PORT.ROM),A + JP .return +.stackDepth EQU 2 ; расстояние от конца процедуры до вершины стека. +.readProcedure.size EQU $-.readProcedure + ; +.chip_ID_TXT: +.chip_ID_TXT.K30: DZ "K30" +.chip_ID_TXT.RecordSize EQU $-.chip_ID_TXT +.chip_ID_TXT.K50 DZ "K50" +;.chip_ID_TXT.K100 DZ "K100" +.chip_ID_TXT.Size EQU $-.chip_ID_TXT ;----------------------------------------------------------------------; ;----------------------------------------------------------------------; ;EMM_FN7 EMM.CheckColdInit: - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A + IN A,(SLOT2) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT2),A - LD HL,#8000 - LD DE,ID_SPRINTER_length - ld a,(de) - inc de - ld b,a -.loop: LD A,(DE) - CP (HL) - JR NZ,INIT_SYS_ALL - INC HL - INC DE - DJNZ .loop - EX AF,AF' - OUT (SLOT2),A + LD HL,SYS_PAGE.ID_FLAG - #4000 + ; LD DE,ID_SPRINTER_FullSize + ; LD A,(DE) + ; DEC A + ; INC DE + ; LD B,A + LD B,ID_SPRINTER.Record1_Size + LD DE,ID_SPRINTER +.loop: LD A,(DE) + CP (HL) + JR NZ,INIT_SYS_ALL + INC HL + INC DE + DJNZ .loop + ; Disable user IM address in SYS_PAGE + XOR A + LD (SYS_PAGE.INT_ID - #4000),A + ; + EX AF,AF' + OUT (SLOT2),A RET ;MSDOS_COLD_VARS: EMM.FullInit: DI - IN A,(SLOT2) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT2),A - + IN A,(SLOT2) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT2),A INIT_SYS_ALL: - LD HL,ID_SPRINTER_length - LD DE,SYS_PAGE.ID_FLAG - #4000 - LD C,(hl) - LD B,0 - INC hl + DI + ; LD HL,#8000 + ; LD DE,#8001 + ; LD (HL),#FF + ; LD BC,#3FFF + ; LDIR + ; + ; LD HL,ID_SPRINTER_FullSize + ; LD DE,SYS_PAGE.ID_FLAG - #4000 + ; LD C,(HL) + ; LD B,0 + ; INC HL + LD HL,ID_SPRINTER + LD DE,SYS_PAGE.ID_FLAG - #4000 + LD BC,ID_SPRINTER.Record1_Size LDIR - -;!TODO что за переменные? - LD HL,SYS_PAGE.DISK_TYPE-#4000 - LD (HL),0 ;!HARDCODE - INC HL - LD (HL),1 ;!HARDCODE - INC HL - LD (HL),#40 ;!HARDCODE HDD - INC HL - LD (HL),3 ;!HARDCODE - INC HL - LD (HL),0 ; SYS_PAGE.COPY_SLOT0 - INC HL - LD (HL),5 ; SYS_PAGE.COPY_SLOT1 - INC HL - LD (HL),2 ; SYS_PAGE.COPY_SLOT2 - INC HL - LD (HL),0 ; SYS_PAGE.COPY_SLOT3 + ; чистка переменных ZX HDD + XOR A + LD H,A + LD L,A + LD (SYS_PAGE.CURRENT_DIR_SEC_L - #4000),HL + LD (SYS_PAGE.CURRENT_DIR_SEC_H - #4000),HL + LD (SYS_PAGE.Block_IDs - #4000),HL + DEC A + LD (SYS_PAGE.CURRENT_HDD - #4000),A + LD (SYS_PAGE.CURRENT_DIR_DRIVE - #4000),A + LD (SYS_PAGE.CURRENT_DIR_DRIVE_COPY - #4000),A + ; Disable user IM address in SYS_PAGE + XOR A + LD (SYS_PAGE.INT_ID - #4000),A + ; + LD HL,SYS_PAGE.DISK_TYPE - #4000 + LD (HL),DRIVE_CODES.TRDOS.FDD ; FDD A + INC HL + LD (HL),DRIVE_CODES.TRDOS.FDD + 1 ; FDD B + INC HL + LD (HL),DRIVE_CODES.TRDOS.HDD + INC HL + LD (HL),DRIVE_CODES.TRDOS.HDD + INC HL + ; A = 0 + LD (HL),A + INC HL + LD (HL),ZX_PAGE.SLOT1 + INC HL + LD (HL),ZX_PAGE.SLOT2 + INC HL + LD (HL),A - LD A,9 - LD (SYS_PAGE.MSD_SECS-#4000),A - LD A,0 - LD (SYS_PAGE.DS_1440-#4000),A + LD A,9 + LD (SYS_PAGE.MSD_SECS - #4000),A + XOR A + LD (SYS_PAGE.DS_1440 - #4000),A - LD HL,SYS_PAGE.RAMD_KEYS-#4000 - LD DE,SYS_PAGE.RAMD_KEYS+1-#4000 - - LD BC,SYS_PAGE.RAMD_KEYS.NUM-1 - LD (HL),0 + LD HL,SYS_PAGE.RAMD_KEYS - #4000 + LD DE,SYS_PAGE.RAMD_KEYS+1 - #4000 + LD BC,SYS_PAGE.RAMD_KEYS.NUM-1 + LD (HL),0 LDIR - - LD DE,ZG_ADRESS ; адрес знакогенератора - LD (SYS_PAGE.WIN_ZG-#4000),DE + ; [x] 04/11/2023 + LD HL,SYS_PAGE.Sp_RAMD_KEYS - #4000 + LD DE,SYS_PAGE.Sp_RAMD_KEYS+1 - #4000 + LD BC,SYS_PAGE.Sp_RAMD_KEYS.NUM-1 + LD (HL),0 + LDIR + ; + ; [x] 17/08/2024 fixed bug with change current RAM drives type + XOR A + LD (SYS_PAGE.CURRENT_RAM_DRV - #4000),A + ; + ;;; init task's + ; + ;LD DE,ZG_ADDRESS ; адрес знакогенератора + ;LD (SYS_PAGE.WIN_ZG - #4000),DE ; -;-----------[new code start]------------ ; !!!!! посмотреть-причесать +;-----------[new code start]------------; !!!!! посмотреть-причесать INIT_VSyncAndWaits: - LD D,CMOS.Cell.ScreenSET + LD D,CMOS_CELL.ScreenSET CALL CMOS_RD ld d,a jr nc,.cmos_OK ; если нет CMOS, то стандартные настройки ld a,3 - ld (SYS_PAGE.VSyncAndWaits-#4000),A + ld (SYS_PAGE.VSyncAndWaits - #4000),A jr z,INIT_CONFIG_ALL.setDefaultINT .cmos_OK: - and CMOS.Cell.ScreenSET.Mask.Sinc - bit 6,a + and high CMOS_CELL.ScreenSET.Mask.Sinc + and #40 ld a,3 ; 320 lines & no waits jr z,.setVSyncAndWaits dec a ; 312 lines & no waits .setVSyncAndWaits: - ld (SYS_PAGE.VSyncAndWaits-#4000),A + ld (SYS_PAGE.VSyncAndWaits - #4000),A INIT_CONFIG_ALL: ld a,d - and CMOS.Cell.ScreenSET.Mask.Int + and high CMOS_CELL.ScreenSET.Mask.Int jr z,.setDefaultINT ; set default int - xor CMOS.Cell.ScreenSET.Mask.Int + xor high CMOS_CELL.ScreenSET.Mask.Int LD HL,SCREEN_TABLES.ORIGINAL ; set original int jr z,.setINT @@ -199,17 +292,22 @@ INIT_CONFIG_ALL: .setDefaultINT: LD HL,SCREEN_TABLES.PENTAGON ; set pentagon int .setINT: - LD (SYS_PAGE.CONFIG_ALL-#4000),HL + LD (SYS_PAGE.SCREEN_TABLE - #4000),HL ;------------[new code end]------------- ; - LD DE,CNF_PORT.CNF_0 + CNF_PORT.TURBO.ON + ROM.BIOS - LD (SYS_PAGE.CONFIG_DE-#4000),DE + LD DE,CNF_PORT.CNF_0 + ROM.BIOS + LD (SYS_PAGE.CONFIG_DE - #4000),DE - LD HL,SYS_PAGE.TASK_DATA-#4000 ; убить все задачи - LD DE,SYS_PAGE.TASK_DATA+1-#4000 - LD BC,#FF - LD (HL),0 - LDIR + + + ; LD HL,SYS_PAGE.ZX_TASK.CURRENT - #4000 ; убить все задачи + ; LD DE,SYS_PAGE.ZX_TASK.CURRENT+1 - #4000 + ; LD BC,_ZX_TASK - 1 + ; LD (HL),0 + ; LDIR + LD A,Spec_Page + OUT (SLOT2),A + LD (Spec_Page.flag_Z - #4000),A EX AF,AF' OUT (SLOT2),A @@ -230,6 +328,7 @@ INIT_CONFIG_ALL: RET ;----------------------------------------------------------------------; + ;----------------------------------------------------------------------; FN_TURBO: CP 2 @@ -245,14 +344,14 @@ FN_TURBO: ;!FIXIT меняем плотность - меняем в системной странице инфу об этом .SET_FDD_720: - LD A,1 - OUT (#BD),A ; !HARDCODE + LD A,FDD_Density.SET_720 + OUT (FDD_Density),A AND A RET ;!FIXIT меняем плотность - меняем в системной странице инфу об этом .SET_FDD_1440: - LD A,#21 - OUT (#BD),A ; !HARDCODE + LD A,FDD_Density.SET_1440 + OUT (FDD_Density),A AND A RET @@ -262,14 +361,14 @@ FN_TURBO: LD B,A LD A,SYS_PAGE OUT (SLOT3),A - ;!TEST + ; ;LD DE,(SYS_PAGE.CONFIG_DE) ;LD A,E LD A,(SYS_PAGE.CONFIG_DE) ; AND #FC ; !HARDCODE OR C - ;!TEST + ; ;LD E,A ;LD (SYS_PAGE.CONFIG_DE),DE LD (SYS_PAGE.CONFIG_DE),A @@ -282,18 +381,14 @@ FN_TURBO: RET ;----------------------------------------------------------------------; -;----------------------------------------------------------------------; -READ_PORTS: ; !TODO сделать -WRITE_PORTS: ; !TODO сделать - SCF - RET -;----------------------------------------------------------------------; +;----------------------------------------------------------------------; ;!TODO ;FN_GET_SYS_VAR: ; Вход: HL - номер системной переменной ; Выход: HL - значение системной переменной ; RET +;----------------------------------------------------------------------; ;!TODO скомпоновать @@ -418,28 +513,24 @@ LOOP_EQ: ; ;----------------------------------------------------------------------; ;********************************** -;!!!!! глянуть ; START_DI: ; PUSH AF ; LD A,R -; JP PE,XX_DI -; LD A,R -; XX_DI: LD A,#80 +; LD A,#80 ; JP PE,XX_DI2 ; XOR A ; XX_DI2: LD R,A ; DI ; POP AF ; RET - +; ; END_DI: PUSH AF ; LD A,R -; BIT 7,A +; AND #80 ; JR Z,XX_DI3 ; EI ; POP AF ; PE ; RET - ; XX_DI3: DI ; POP AF ; PO ; RET diff --git a/src/bios/exp/ZX_MEM.TXT b/src/bios/exp/ZX_MEM.TXT new file mode 100644 index 0000000..cf20fbf --- /dev/null +++ b/src/bios/exp/ZX_MEM.TXT @@ -0,0 +1,13 @@ +Отдельные рамблоки для: + vROM + vRAM +Отдельные процедуры выделения страниц для: + #1FFD - обрабатывать первым если нужен. Не подходят #A0, #D0..#DF + #7FFD - 128/512, не выделять память для #1FFD в режиме pent 512 + vROM +Страницу 0 использовать как раньше для маппа в #7FFD и для #1FFD=1 +Подкрутить в меню спектрума переключалку режимов и освобождение памяти под новую модель памяти +При освобождении памяти vROM мапить на эти порты обратно Spec_Page +Проверить на хардкод биос и zxroms, чтоб не втыкались стандартные (зарезервированные) страницы +; +Сделать переключалку в биосе старый/новый режим работы памяти? \ No newline at end of file diff --git a/src/bios/exp/ZX_MENU.ASM b/src/bios/exp/ZX_MENU.ASM deleted file mode 100644 index a8930e0..0000000 --- a/src/bios/exp/ZX_MENU.ASM +++ /dev/null @@ -1,339 +0,0 @@ -; "MENU PROGRAMS." -;********************************* -; FOR INCLUDE !!! -;********************************* -; Обслуживание МЕНЮ -; HL - адрес таблицы программ -; A - номер в таблице -; если A=-1, то возврат, -; иначе выполнение -;***************************** - - -EXEC_PNT: - INC A - RET Z -EXEC_PNT_LOOP: - DEC A - JR Z,EXEC_HL - INC HL - INC HL - JR EXEC_PNT_LOOP -EXEC_HL: - LD E,(HL) - INC HL - LD D,(HL) - INC HL - EX DE,HL - JP (HL) -RET_FROM_M: - POP HL - RET - -;**************************************** -; РАБОТА С MENU_128 -;**************************************** -; ВХОД: - DE - адрес меню -; BC - длина меню -; ВЫХОД: A - выбранный пункт -;**************************************** -RUN_MENU: - PUSH IX - PUSH DE ; DE - MENU - PUSH BC ; BC - len_menu - - LD A,(DE) - DEC A ; число CMD - CP 9 - JR C,RUN_M_1 -RUN_MN_ERR: - POP BC - POP DE - LD A,0FFh ; вернуться с номером 255 - ошибка - POP IX - RET -RUN_M_1: - LD A,(5B00H) - CP #F5 ; СРАВНИТЬ А С КОДОМ PUSH AF - JR NZ,RUN_MN_ERR - - - LD HL,LEN_P_M - ADD HL,BC ; HL - нужная длина памяти - LD B,H ; HL -> BC - LD C,L - LD HL,(5C61h) ; HL - начало раб обл - - PUSH BC - PUSH HL - - CALL C_1655 ; получить рабочую память - - POP DE - PUSH DE ; начало раб обл - - LD BC,LEN_P_M ; длина программы меню - LD HL,MENU_128 ; сама программа - LDIR ; программа перемещена. DE - место для MENU - POP BC - PUSH BC ; начало программы - - PUSH DE ; сохранить место для MENU - LD DE,MN_128_S ; данные для shifter - CALL SHIFTER ; изменить данные в соответствии с положением в MEM - POP DE ; вернуть место для MENU - - POP HL ; начало программы - POP IX ; длина данных - POP BC ; длина меню - EX (SP),HL ; HL - меню - LDIR ; переместить данные MENU - - POP HL ; адрес программы MENU - PUSH HL - PUSH IX ; длина раб. обл - CALL JP_HL ; вызов программы MENU - POP BC ; вернуть длину раб обл - POP HL ; и начала программы - - PUSH AF ; сохранить номер выбора - CALL C_19E8 ; освободить память !! - POP AF ; вернуть номер выбора - POP IX - RET ; возврат из программы RUN_MENU - -;************************************** -; 128k MENU -;************************************** -MENU_PROG EQU 25B9h -SWAP_ROM EQU 5B00h -NEW_SP EQU 1F45h -RET_SP EQU 1F20h - -;************************************** -; Программа вызова MENU_128 из ОЗУ. -;************************************** -MN_128_S: - DB SH_1 - MENU_128+1 - DB SH_2 - MENU_128+1 - DB SH_3 - MENU_128+1 - DB SH_4 - MENU_128+1 - DB SH_5 - MENU_128 - DB SH_6 - MENU_128 - DB SH_7 - MENU_128 - DB SH_8 - MENU_128 - DB SH_9 - MENU_128 - DB SH_A - MENU_128 - DB SH_B - MENU_128 - DB SH_C - MENU_128 - DB 0 -;************************************** -; Эта программа перемещается в озу -;************************************** -MENU_128: - LD A,0 - OUT (SYS_PORT_OFF),A - CALL SWAP_ROM - CALL NEW_SP - -SH_1: LD DE,MENU_DAT - MENU_128 - LD HL,#F6EA - LD BC,4 - LDIR - -SH_2: LD HL,MENU_128_E - MENU_128 - LD (#F6EA),HL -SH_3: LD HL,MENU_128_E2 - MENU_128 - LD (#F6EC),HL - JP MENU_PROG - -RET_M EQU $-MENU_128 -SH_4: LD HL,MENU_DAT - MENU_128 - LD DE,#F6EA - LD BC,4 - LDIR - - CALL RET_SP - CALL SWAP_ROM - EX AF,AF' - LD A,0 - OUT (CNF_PORT),A - EX AF,AF' - RET -MENU_DAT: - DW 0,0 -MENU_128_E: - DB 8 - DB 0 -SH_5: DW RET_M - DB 1 -SH_6: DW RET_M - DB 2 -SH_7: DW RET_M - DB 3 -SH_8: DW RET_M - DB 4 -SH_9: DW RET_M - DB 5 -SH_A: DW RET_M - DB 6 -SH_B: DW RET_M - DB 7 -SH_C: DW RET_M -MENU_128_E2: - -LEN_P_M EQU $-MENU_128 - -;************************************** -; RST 30 - получение BC SPACES с адреса HL -; 19E8h - освобождение BC spaces с адреса HL -; HL - раб. ячейка -; BC - адрес программы -; DE - адрес данных для перемещения -SHIFTER: - LD A,(DE) ; (DE) - SHIFT IN PROG - AND A - RET Z - INC DE - LD L,A - LD H,0 - - ADD HL,BC ; HL - ADRESS FOR SHIFT - LD A,(HL) ; (HL)=(HL)+BC - ADD A,C - LD (HL),A - INC HL - LD A,(HL) - ADC A,B - LD (HL),A - JR SHIFTER - -;******************************************* -; МЕНЮ : байт 1 - для результата -; байт 2 - число пунктов +1 -; название меню, код 0FFh ( COPY ) -; пункты меню окончание байтом с -; уст, 7-м битом + пустая строка !! -;******************************************* -BASIC_MENU: -; LD A,(HL) -; CP 'S' -; JP Z,SET_SYSTEM - - LD DE,(CH_ADR) - PUSH DE - LD (CH_ADR),HL - CALL_48X 1C8Ch ; SYMBOL VAR - CALL_48X 2BF1h ; input txt !!! - ; DE - adr - ; BC - len - PUSH DE - PUSH BC - INC DE - CALL TST_M - JR C,NO_EXE_M - CALL RUN_MENU - LD (IY+0),255 -NO_EXE_M: - POP BC - POP DE - LD (DE),A - POP HL - LD (CH_ADR),HL - JP SW_ROM -TST_M: - PUSH DE - PUSH BC - EX DE,HL - LD D,(HL) - INC D - LD A,255 - CPIR - JR NZ,ERR_TST_M -LOOP_TST_M: - LD A,B - OR C - JR Z,ERR_TST_M - - BIT 7,(HL) - INC HL - DEC BC - JR Z,LOOP_TST_M - DEC D - JR NZ,LOOP_TST_M - POP BC - POP DE - AND A - RET - -ERR_TST_M: - POP BC - POP DE - LD A,255 - SCF - RET - -;************************************** - -CALL_DOS_MOVE: - LD DE,5C00H-.Size - LD HL,DOS_PROG - LD BC,.Size - LDIR - RET -; -; HL - адрес команды, BC - длина команды -CALL_DOS1: - LD C,(HL) - INC HL - LD B,0 - LD DE,(ZX_VARS.E_LINE) - LD (ZX_VARS.CH_ADR),DE - LDIR - LD (ZX_VARS.WORK_SP),DE - LD (ZX_VARS.STK_BOT),DE - LD (ZX_VARS.STK_END),DE - CALL CALL_DOS_MOVE - JP 5C00H-.Size -CALL_DOS: - PUSH HL - PUSH DE - PUSH BC - PUSH AF - CALL CALL_DOS_MOVE - LD A,13H - LD (5C00H-.Size+DOS_PROG_A),A - POP AF - POP BC - POP DE - POP HL - JP 5C00H-.Size - -DOS_PROG: - PUSH AF - XOR A - OUT (SYS_PORT_OFF),A - POP AF - CALL #3D03 ;!HARDCODE -DOS_PROG_A EQU $-DOS_PROG-1 - PUSH AF - LD A,0 - OUT (CNF_PORT),A - POP AF - RET -.Size EQU $-DOS_PROG - -CONT_PROG: - LD HL,1AFDH - PUSH HL - LD HL,5B00H - PUSH HL - LD DE,5C71H - LD BC,1 - LD A,0E8H - LD (DE),A - JP SW_ROM - - - - diff --git a/src/bios/exp/ZX_MODE.ASM b/src/bios/exp/ZX_MODE.ASM deleted file mode 100644 index 1c3123b..0000000 --- a/src/bios/exp/ZX_MODE.ASM +++ /dev/null @@ -1,380 +0,0 @@ -;.PRINTX "Service." - -SERVICE: - LD HL,SR_TAB - LD DE,SR_MENU - LD BC,SR_MENU.Size - PUSH HL - CALL RUN_MENU ;09f3 - POP HL - CALL EXEC_PNT - JR SERVICE - -SR_TAB: DW UTILIT - DW GOTO_TRDOS.m128 - DW GOTO_TRDOS.m48 - DW TURBO_OFF - DW TURBO_ON - DW CLEAR_RAM - DW RET_FROM_M - -; DC - every last character of a string will have bit 7 set -SR_MENU: - BYTE 8 ; количество пунктов - BYTE 'Options ',#FF ; заголовок меню - DC 'RUN disk.trd' - DC '128 TR-DOS' - DC '48 TR-DOS' - DC 'TURBO OFF ' - DC 'TURBO ON ' - DC 'Clear RAM' - DC 'RETURN' - DC ' ' ; маркер конца -.Size EQU $-SR_MENU - -;***************************** - -;SR_48R: -GOTO_TRDOS: -.m128: LD A,#10 - JR .RUN -;SR_48: -.m48: LD A,#30 ; Стопор на PORT_128 !!! -;SR_48A: -.RUN: LD BC,#7FFD - OUT (C),A - LD BC,0 ; НА 0 !! - PUSH BC - LD BC,#3D2F ; В DOS ! - PUSH BC - JP SW_ROM - -;******************************* -TURBO_OFF: - LD A,BIOS.FN_TURBO.OFF - LD C,BIOS.FN_TURBO - JP ToBIOS_18 -TURBO_ON: - LD A,BIOS.FN_TURBO.ON - LD C,BIOS.FN_TURBO - JP ToBIOS_18 - -;******************************* - -CLEAR_RAM: - DI - LD C,BIOS.FullInit - RST ToBIOS_18 - ; при очистке памяти из меню спектрума возврат в DSS по CAD - ; будет опасным (RAM Blocks освободились), - ; поэтому отключаем перехват ресета. - ;!TODO придумать как отключать перехват только на возврат в DSS - LD A,Conf_port.RET_PORT - LD BC,BIOS.SET_PORTS - CALL ToBIOS_3D13 - EI - RET - -;SR_CL_MEM: -; DI -; LD A,10H -;SR_CL_R2: -; LD BC,1FFDH -; OUT (C),A -; EX AF,AF' -; XOR A -;SR_CL_R1: -; LD BC,7FFDH -; OUT (C),A -; LD HL,0C000H -; LD DE,0C001H -; LD BC,03FFFH -; LD (HL),L -; LDIR -; INC A -; CP 48H -; JR NZ,SR_CL_R1 -; EX AF,AF' -; CP 0 -; JP Z,BASIC_128 ; выход на сброс BASIC 128 -; LD A,0 -; JR SR_CL_R2 - -;***************************** -; *** MENU IS-DOS *** -;***************************** - -ISDOS: - LD HL,IS_TAB - LD DE,IS_MENU - LD BC,IS_MENU.Size - PUSH HL - CALL RUN_MENU - POP HL - CALL EXEC_PNT - JR ISDOS - -IS_TAB: -; DW TR_DOS -; DW SP_DOS - DW SPRINTER_1X - DW AY8910_X - DW PENTAGON - DW SCORPION - DW PENTAGON512 - DW SPRINTER_reset ;SPRINTER_2X - DW RET_FROM_M - -; DC - every last character of a string will have bit 7 set -IS_MENU: - BYTE 8 ; количество пунктов - BYTE 'Hardware',#FF ; заголовок меню - DC 'Sprinter ZX ' - DC 'ZX Spectrum' - DC 'Pentagon 128' - DC 'Scorpion 256' - DC 'Pentagon 512' - DC 'Restart ' - DC 'RETURN' - DC ' ' ; маркер конца -.Size EQU $-IS_MENU - -;****************************** -;SP_DOS: -; LD B,0E2H -; LD A,0E1H -; JR TR_DOS1 -;TR_DOS: -; LD B,0EAH -; LD A,0E1H -;TR_DOS1: -; CALL DOS_ON -; CALL SET_ROM_PAGES -; CALL DOS_OFF -; RET -;****************************** - - -;************************************************** -;Sprinter ZX -SPRINTER_1X: - CALL _SET_CNF - LD C,BIOS.RST_CONF.SP97_1 - RST ToBIOS_18 - CALL CNF_PN_320 - LD L,2 ;FN_SYNC.INT_PENT - JR 1F ;!FIXIT метку придумать -; -;ZX Spectrum -AY8910_X: - CALL _SET_CNF - LD C,BIOS.RST_CONF.AY8910 - RST ToBIOS_18 - - LD A,#FA ; no ACC, Original waits - LD (Port_All_Mode),A - - CALL CNF_SC_312 - LD L,3 ;FN_SYNC.INT_ORIG -1: LD DE,CNF_PORT.CNF_0 + CNF_PORT.TURBO.ON - CALL CONFIG_SET - CALL CLS ;!FIXIT нужно ли? - RET -; - -SCORPION: - CALL _SET_CNF - CALL CNF_SC_312 - LD L,1 ;FN_SYNC.INT_SCORP - LD DE,CNF_PORT.CNF_1 + CNF_PORT.TURBO.ON - JR CONFIG_SET - -PENTAGON: - CALL _SET_CNF - CALL CNF_PN_320 - LD L,2 ;FN_SYNC.INT_PENT - LD DE,CNF_PORT.CNF_2 + CNF_PORT.TURBO.ON - JR CONFIG_SET - -PENTAGON512: - CALL _SET_CNF - CALL CNF_PN_320 - LD L,2 ;FN_SYNC.INT_PENT - LD DE,CNF_PORT.CNF_2 + CNF_PORT.TURBO.ON + CNF_PORT.CNF_512 -; JR CONFIG_SET -CONFIG_SET: - PUSH DE - - EI - HALT - DI - - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD (SYS_PAGE.CONFIG_DE),DE - ;!FIXIT есть ли смысл делать до FN_SYNC? - LD A,(ZX_VARS.BORDER) - RRCA - RRCA - RRCA - AND 7 - OUT (BorderColor),A - ; - EX AF,AF' - OUT (SLOT3),A - - LD A,L - LD C,BIOS.FN_SYNC - RST ToBIOS_18 - - LD HL,#4104 ;!HARDCODE - LD E,0 - LD BC,256*4 + BIOS.LP_OPEN_S ;!HARDCODE - RST ToBIOS_18 - - LD HL,#5104 ;!HARDCODE - LD E,0 - LD BC,256*4 + BIOS.LP_OPEN_S - RST ToBIOS_18 - - POP DE - LD A,E - OUT (SYS_PORT.ROM),A - - IM 1 - EI - RET - -SPRINTER_reset: - CALL _SET_CNF - LD BC,256*BIOS.REINIT.SOFT_RESET + BIOS.REINIT - JP ToBIOS_18 - -_SET_CNF: - DI - LD A,CNF_PORT.CNF_0 + CNF_PORT.TURBO.ON - OUT (SYS_PORT.ROM),A - RET - -CNF_SC_312: - LD A,Port_VSYNC.SET_312L - OUT (Port_VSYNC),A - RET - -CNF_PN_320: - LD A,Port_VSYNC.SET_320L - OUT (Port_VSYNC),A - RET -; LD A,CNF_0 -; OUT (SYS_PORT.ROM),A -; CALL DOS_OFF -; JP 0 - -;***************************** -; *** MENU UTILITES *** -;***************************** - -UTILIT: - LD HL,C_DISK_C - CALL CALL_DOS1 - - CALL DOS_ON - LD A,0 ; DETECT_HDD - CALL HDD_EXE - CALL DOS_OFF - - JR C,DISK_UTILIT - - LD HL,C_DISK_C3 - CALL CALL_DOS1 - -UTIL_DISK: - LD A,0 - CALL EMM_FN3 - - LD HL,C_DEMO6 - CALL CALL_DOS1 - - LD A,0 - CALL GET_RAMD_ST - JR C,UTIL_DISK_L1 - JR Z,UTIL_DISK_L1 - - LD HL,C_DISK_C1 - CALL CALL_DOS1 - LD HL,C_DISK_C2 - CALL CALL_DOS1 - RET - -UTIL_DISK_L1: - LD A,(ZX_VARS.OPER_DISK) - INC A - CP 2 - JR Z,DISK_UTIL_RET - LD HL,C_DISK_C5 - CALL CALL_DOS1 - JR UTIL_DISK - -DISK_UTIL_RET: - LD HL,C_DISK_C6 - CALL CALL_DOS1 - RET - -DISK_UTILIT: - LD HL,C_DISK_C4 - CALL CALL_DOS1 - JR UTIL_DISK - -C_DEMO6: DB .Size, ZX_Token.rem, ':/disk.trd', 13,80 -.Size EQU $-C_DEMO6-1 - -;*************************************** - -;VERSION: DEFB 22,21,0 -; DEFB 16,2,"Expansion 3.02  1997 ELSY Co.",16,1,0FFh - -;********************************************** - -DOS_RUN: - LD HL,C_DISK_C1 - CALL CALL_DOS1 - - LD HL,C_DISK_C2 - CALL CALL_DOS1 - RET - -START_TRD: - LD HL,C_DISK_C - CALL CALL_DOS1 - LD HL,C_DISK_C0 - CALL CALL_DOS1 - LD HL,C_DISK_C3 - CALL CALL_DOS1 - RET - -C_DISK_C: DB .Size, ZX_Token.rem, ':', 13,80 -.Size EQU $-C_DISK_C-1 - -C_DISK_C0: DB .Size, ZX_Token.rem, ':/CLEAR E', 13,80 -.Size EQU $-C_DISK_C0-1 - -C_DISK_C1: DB .Size, ZX_Token.rem, ':/RMD E', 13,80 -.Size EQU $-C_DISK_C1-1 - -C_DISK_C2: DB .Size, ZX_Token.rem, ':RUN', 13,80 -.Size EQU $-C_DISK_C2-1 - -C_DISK_C3: DB .Size, ZX_Token.rem, ':/HDD', 13,80 -.Size EQU $-C_DISK_C3-1 - -C_DISK_C4: DB .Size, ZX_Token.rem, ':/FDD', 13,80 -.Size EQU $-C_DISK_C4-1 - -C_DISK_C5: DB .Size, ZX_Token.rem, ':/B:', 13,80 -.Size EQU $-C_DISK_C5-1 - -C_DISK_C6: DB .Size, ZX_Token.rem, ':/A:', 13,80 -.Size EQU $-C_DISK_C6-1 -; \ No newline at end of file diff --git a/src/bios/exp/clean.cmd b/src/bios/exp/clean.cmd deleted file mode 100644 index ca561e9..0000000 --- a/src/bios/exp/clean.cmd +++ /dev/null @@ -1,4 +0,0 @@ -@echo off -del *.bin /s -del *.lst /s -del *.log /s diff --git a/src/bios/exp/make.cmd b/src/bios/exp/make.cmd deleted file mode 100644 index 80272e6..0000000 --- a/src/bios/exp/make.cmd +++ /dev/null @@ -1,20 +0,0 @@ -@echo off -set BIN=..\..\bin -set LOG=compile.log -for /F %%i in ('date /t') do set mydate=%%i -for /F %%i in ('time /t') do set mytime=%%i -set mydt=%mydate% %mytime% - -echo 6. [1/1] EXPANSION -echo %mydt%: [1/1] EXPANSION >> %LOG% -%BIN%\sjasmplus.exe -Wall --msg=war --nologo --syntax=w --fullpath --lst=EXP.LST --raw=EXP.BIN EXP.ASM >> %LOG% 2>&1 -if errorlevel 1 goto error - -goto quit - -:error -echo ERROR during compile EXPANSION -pause 0 -exit 3 - -:quit diff --git a/src/bios/loader/bitstream_header.inc b/src/bios/loader/bitstream_header.inc index 418357b..6093006 100644 --- a/src/bios/loader/bitstream_header.inc +++ b/src/bios/loader/bitstream_header.inc @@ -1,3 +1,5 @@ ; Header of bitstream which non packed - DB #FF,#FF,#62,#7B,#39,#00,#FF,#FF + DB #FF,#FF,#62,#7B,#39,#00;,#FF,#FF ; 1k30 +; Packed: + ;DB #FF,#FF,#62,#7B,#3C,#00;,#01,#FF ; 1k50 ; \ No newline at end of file diff --git a/src/bios/loader/clean.cmd b/src/bios/loader/clean.cmd deleted file mode 100644 index ca561e9..0000000 --- a/src/bios/loader/clean.cmd +++ /dev/null @@ -1,4 +0,0 @@ -@echo off -del *.bin /s -del *.lst /s -del *.log /s diff --git a/src/bios/loader/loader.asm b/src/bios/loader/loader.asm index b7fd045..21158c3 100644 --- a/src/bios/loader/loader.asm +++ b/src/bios/loader/loader.asm @@ -1,33 +1,28 @@ ; ;**********************************; -; FLEX Loading program ; +; ACEX Loading program ; ;**********************************; -; ORG 0 - -; INCLUDE 'src/bios/shared/SPRINT00.asm' - MACRO Conf_loader altera_chip .START: DI - LD BC,#FFEE ; !HARDCODE - XOR A ; Z84.REG.WaitState_Ctrl - register - waits - OUT (C),A ; Z84.SYS.Control - INC C ; LD BC,#FFEF - LD A,4 ; !HARDCODE Memory waits set to 1 - OUT (C),A ; Z84.SYS.Data + LD BC,#FF*256 + Z84.SYS.Control + XOR A ; Z84.REG.WaitState_Ctrl - register - waits + OUT (C),A ; Z84.SYS.Control + INC C ; LD BC,#FFEF + LD A,4 ; Memory waits set to 1 + OUT (C),A ; Z84.SYS.Data - DEC C ; Z84.SYS.Control - DEC A ; LD A,3 3-nd register - boundaries - OUT (C),A ; Z84.REG.Misc_Ctrl - INC C ; cs0 enable, cs1 enable, 32-Bit CRC disable, reset output enable, Clock Divide-by-two - OUT (C),A ; Z84.SYS.Data + DEC C ; Z84.SYS.Control + DEC A ; LD A,3 - 3-nd register - boundaries + OUT (C),A ; Z84.REG.Misc_Ctrl + INC C ; cs0 enable, cs1 enable, 32-Bit CRC disable, reset output enable, Clock Divide-by-two + OUT (C),A ; Z84.SYS.Data - DEC C ; Z84.SYS.Control - DEC A ; LD A,2 Z84.REG..CS_Boundary 2-nd register - boundaries - OUT (C),A ; Z84.SYS.Data + DEC C ; Z84.SYS.Control + DEC A ; LD A,2 - Z84.REG..CS_Boundary 2-nd register - boundaries + OUT (C),A ; Z84.SYS.Data INC C - LD A,#FE ; !HARDCODE - OUT (C),A ; boundaries FFFF..F000 - CS1 -; EFFF..0000 - CS0 + LD A,#FE ; boundaries FFFF..F000 - CS1 + OUT (C),A ; EFFF..0000 - CS0 JR .LOOP_S1 ;************************************** @@ -36,7 +31,7 @@ ;************************************** .LOOP_S1: - LD HL,#FEF0 ; !HARDCODE + LD HL,#FEF0 ; !HARDCODE LD DE,.STRING .LOOP_S: LD A,(DE) @@ -44,17 +39,17 @@ JR NZ,.NO_CNF_RAM INC E INC L - JR NZ,.LOOP_S ; !!!!! привязка к адресу в HL + JR NZ,.LOOP_S ; !!!!! привязка к адресу в HL ; !TODO убрать вейты для кэша? - LD BC,#FFEE ; !HARDCODE - LD A,2 ; !HARDCODE - OUT (C),A ; 0 register - waits + LD BC,#FF*256 + Z84.SYS.Control + LD A,Z84.REG.CS_Boundary + OUT (C),A ; 0 register - waits INC C LD A,#F0 - OUT (C),A ; boundaries FFFF..1000 - CS1 -; 0FFF..0000 - CS0 - LD HL,#1000 ; !!!!! Load bitstream from Fast-RAM + OUT (C),A ; boundaries FFFF..1000 - CS1 +; ; 0FFF..0000 - CS0 + LD HL,#1000 ; !!!!! Load bitstream from Fast-RAM JR .NEW_SHM @@ -64,11 +59,11 @@ ;************************************** .NO_CNF_RAM: - LD HL,#0100 ; !!!!! Load bitstream from ROM + LD HL,#0100 ; !!!!! Load bitstream from ROM .NEW_SHM: ;--------------[conf check]------------- - LD A,H ; сохраняем старший адрес начала конфы, -; начало конфы должно быть с младшим адресом = 0 + LD A,H ; сохраняем старший адрес начала конфы, +; начало конфы должно быть с младшим адресом = 0 EXX LD L,0 LD H,A @@ -77,15 +72,15 @@ ; в HL адрес первого байта конфы LD DE,.Conf_header LD B,.Conf_header.length -1: +.conf_header_loop: LD A,(DE) CP (HL) JR NZ,.Conf_Packed INC DE INC L - DJNZ 1B + DJNZ .conf_header_loop - XOR A + ;XOR A JR .exit_conf_check .Conf_Packed: SCF @@ -94,7 +89,7 @@ EXX ;--------------------------------------- - LD DE,#FE00 ; !!!!! Check flag "don't erase fast-ram bitstream" - "IM" + LD DE,#FE00 ;!HARDCODE ; !!!!! Check flag "don't erase fast-ram bitstream" - "IM" LD A,(#FEE0) CP "I" JR NZ,.ONES_CONFIG @@ -105,11 +100,10 @@ DEC D ; multiple config! .ONES_CONFIG: - LD IY,#0107 ;!!!!! подумать))) - ;!TEST - ;LD IX,#FFFD ;!!!!! подумать))) - LD IX,SP2000_ConfID ;!!!!! подумать))) - ; + LD IY,SP2000_Loader_Flag + ;LD IX,#FFFD + LD IX,ACEX.Config_ID.Sp2000 + .LOOP1: LD A,(HL) @@ -147,7 +141,7 @@ INC HL JR .LOOP1 -.STRING: DB "ACEX_30K_LOADING" +.STRING: DB ACEX.RELOAD_STRING .Conf_header: include 'src/bios/Loader/bitstream_header.inc' .Conf_header.length EQU $-.Conf_header @@ -157,12 +151,12 @@ ; Это, скорее всего, рудимент, тот самый байт описателя конфы, ; который ищет загрузчик для Sp97 по старому адресу #C090. ; Воткнул его в конце загрузчика, может потом пригодится. -.DEF_SYM: DW SP2000_ConfID +.DEF_SYM: DW ACEX.Config_ID.Sp2000 ;------------------------------[Loader end] DEFINE Altera_Chip altera_chip LUA - local file_path = 'Build/Bin/temp/' + local file_path = 'Build/ACEX/' local file_ext = '.BIN' local altera_ver = sj.get_define("Altera_Chip") sj.insert_define("Altera_File", '"' .. file_path .. altera_ver .. file_ext .. '"') diff --git a/src/bios/loader/make.cmd b/src/bios/loader/make.cmd deleted file mode 100644 index 4a9e87d..0000000 --- a/src/bios/loader/make.cmd +++ /dev/null @@ -1,23 +0,0 @@ -@echo off -set BIN=..\..\bin -set LOG=compile.log -for /F %%i in ('date /t') do set mydate=%%i -for /F %%i in ('time /t') do set mytime=%%i -set mydt=%mydate% %mytime% - -rem Altera K30 | Altera K50 -set ALT_LOADER=loader.ASM - -echo 7. [1/1] ALTERA LOADER -echo %mydt%: [1/1] ALTERA LOADER >> %LOG% -%BIN%\sjasmplus.exe -Wall --msg=war --nologo --syntax=w --fullpath --lst=LOADER.LST --raw=LOADER.BIN %ALT_LOADER% >> %LOG% 2>&1 -if errorlevel 1 goto error - -goto quit - -:error -echo ERROR during compile ALTERA LOADER -pause 0 -exit 3 - -:quit diff --git a/src/bios/loader/make_vs.cmd b/src/bios/loader/make_vs.cmd deleted file mode 100644 index e7fce22..0000000 --- a/src/bios/loader/make_vs.cmd +++ /dev/null @@ -1,27 +0,0 @@ -@echo -------------------------------------------------------[LOADER START] -@set BIN=..\..\bin -@set BUILD=..\..\..\Build -@set SJASM_PARAM=-DVS_CODE_COMPILE -Wall --msg=war --nologo --syntax=w --fullpath -for /F %%i in ('chdir') do set fulldir=%%i - -@rem Altera K30 | Altera K50 -@set ALT_LOADER=loader.ASM - -@echo 7. [1/1] ALTERA LOADER -@sjasmplus.exe %SJASM_PARAM% --lst=%BUILD%\LOADER.LST --raw=%BUILD%\LOADER.BIN %fulldir%\%ALT_LOADER% -@if errorlevel 1 goto error%no_stop% -@echo [OK ] -@goto quit - -:error0 -@echo -------------------------------------------------------[ERROR during compile ALTERA LOADER] -@pause 0 -@exit 3 - -:error1 -@echo -------------------------------------------------------[ERROR during compile ALTERA LOADER] -@set error_level="1" - -:quit -@echo -------------------------------------------------------[LOADER DONE] -@echo. diff --git a/src/bios/logo/3.bmp b/src/bios/logo/3.bmp deleted file mode 100644 index 2553ac6..0000000 Binary files a/src/bios/logo/3.bmp and /dev/null differ diff --git a/src/bios/logo/4.bmp b/src/bios/logo/4.bmp deleted file mode 100644 index 9831c77..0000000 Binary files a/src/bios/logo/4.bmp and /dev/null differ diff --git a/src/bios/logo/5.bmp b/src/bios/logo/5.bmp deleted file mode 100644 index 061995c..0000000 Binary files a/src/bios/logo/5.bmp and /dev/null differ diff --git a/src/bios/logo/6.bmp b/src/bios/logo/6.bmp deleted file mode 100644 index 7529664..0000000 Binary files a/src/bios/logo/6.bmp and /dev/null differ diff --git a/src/bios/logo/Set_Pictures.asm b/src/bios/logo/Set_Pictures.asm index f798653..d7f9aff 100644 --- a/src/bios/logo/Set_Pictures.asm +++ b/src/bios/logo/Set_Pictures.asm @@ -52,8 +52,8 @@ Raster: INCBIN 'Build/Bin/LOGO_DAT.BIN' .length EQU $-Raster +/* IF Pashalki -; [ ] - сделать тут табличку-ссылки на нужную таблицу спрайтов и завязать это на даты MACRO _PASHALKI_CODE @@ -106,7 +106,6 @@ NewYear: INCLUDE './src/bios/logo/use/New_Year.inc' ENDIF -/* and a ld b,0 diff --git a/src/bios/logo/_LOGO_DAT.BIN b/src/bios/logo/_LOGO_DAT.BIN deleted file mode 100644 index 62d0c7a..0000000 Binary files a/src/bios/logo/_LOGO_DAT.BIN and /dev/null differ diff --git a/src/bios/logo/_LOGO_PAL.BIN b/src/bios/logo/_LOGO_PAL.BIN deleted file mode 100644 index 324e29c..0000000 Binary files a/src/bios/logo/_LOGO_PAL.BIN and /dev/null differ diff --git a/src/bios/logo/fathers.bmp b/src/bios/logo/fathers.bmp deleted file mode 100644 index 3e3e957..0000000 Binary files a/src/bios/logo/fathers.bmp and /dev/null differ diff --git a/src/bios/logo/test.bmp b/src/bios/logo/test.bmp deleted file mode 100644 index d5b16f5..0000000 Binary files a/src/bios/logo/test.bmp and /dev/null differ diff --git a/src/bios/logo/test2.bmp b/src/bios/logo/test2.bmp deleted file mode 100644 index c3b4136..0000000 Binary files a/src/bios/logo/test2.bmp and /dev/null differ diff --git a/src/bios/logo/use/New_Year.inc b/src/bios/logo/use/New_Year.inc index a16e2e5..5489409 100644 --- a/src/bios/logo/use/New_Year.inc +++ b/src/bios/logo/use/New_Year.inc @@ -6,7 +6,7 @@ print() ENDLUA - BYTE 2 ; количество спрайтов + BYTE 2 ; количество спрайтов EasterTable 48, 42, 13, 2, sprite1 EasterTable 37, 6, 69, 26, sprite2 sprite1: INCBIN './src/bios/logo/use/NY_Kokoshnik_DAT.bin' diff --git a/src/bios/make_bios.cmd b/src/bios/make_bios.cmd deleted file mode 100644 index 71c4bba..0000000 --- a/src/bios/make_bios.cmd +++ /dev/null @@ -1,71 +0,0 @@ -@if [%1]==[] (set NO_STOP="0") else (set NO_STOP="%1") -@if %NO_STOP% == "5" (goto all) -@set cur_STEP=0 -@set BIOS_DIR=%cd%\src\bios -@set BIN=%BIOS_DIR%\..\bin -@set BUILD=%BIOS_DIR%\..\..\Build -@set RAW=%BUILD%\Bin -@set error_level="0" - - -@goto start_tasks - -:all -@__make_all_.cmd - -:start_tasks -@echo -------------------------------------------------------[BIOS START] -@echo STEP [1/2], Compiling ROM, EXP, Loader -@set main_file=BIOS -@sjasmplus.exe -Wall --msg=war --nologo --syntax=w --fullpath --color=on --lst=%BUILD%\BIOS.LST %BIOS_DIR%\BIOS.ASM -@if errorlevel 1 (call :error_handler) else (echo [OK ]) -@echo -------------------------------------------------------[BIOS DONE] -@echo. - -@echo -------------------------------------------------------[LOGO START] -@set LOGO_FILE=psfathers.bmp -@echo STEP [2/2], Extracting data for LOGO from BMP -@set main_file=Logo -@echo. -@%BIN%\bmp_extract.exe %BIOS_DIR%\logo\%LOGO_FILE% /pn %RAW%\LOGO_PAL.BIN /dn %RAW%\LOGO_DAT.BIN /pt 4 -@if errorlevel 1 (call :error_handler) else (echo [OK ]) -@set /a "cur_STEP=cur_STEP+1" -@echo -------------------------------------------------------[LOGO DONE] -@echo. - -@if %error_level% == "1" (goto end_task_err) else (goto end_task_ok) - -:error_handler -@color 04 -@if %NO_STOP% == "1" (goto next) else (goto err_stop) - -:next -@echo [ERR] -@set error_level="1" -@echo ---------------------------------------------------------------------[ERROR in %main_file% on STEP %cur_STEP%] -@goto :eof - -:err_stop -@echo ---------------------------------------------------------------------[ERROR in %main_file% on STEP %cur_STEP%] -@cd %BIOS_DIR% -@IF NOT (%NO_STOP% == "1") pause 0 -@color -@exit 3 - -:end_task_err -@echo ---------------------------------------------------------------------[Make firmware ERROR!!!] -@echo. -@cd %BIOS_DIR% -@echo %NO_STOP% -@IF %NO_STOP% == "3" pause 0 -@IF %NO_STOP% == "0" pause 0 -@color -@exit 3 - - -:end_task_ok -@echo --------------------------------------------------------------------------[Make firmware DONE] -@echo. -@cd %BIOS_DIR% -@echo on -@IF (%NO_STOP% == "0") pause 0 diff --git a/src/bios/mem_map.txt b/src/bios/mem_map.txt index f22fccf..7ac2697 100644 --- a/src/bios/mem_map.txt +++ b/src/bios/mem_map.txt @@ -1,15 +1,15 @@ -#10 - ROM +#10 - EXTENSION #11 - LOGO #2800 bytes #12 - sp_128 #13 - sp_48 #14 - sp_trd -#15 - sp_exp -#16 - sp_exp -#17 - sp_exp2 -#18 - EXP -#19 - empty -#1A - empty -#1B - empty +#15 - ROM Disk Recovery +#16 - ROM Disk Recovery +#17 - ROM Disk Recovery +#18 - BIOS +#19 - ROM Disk Recovery +#1A - ROM Disk Recovery +#1B - ROM Disk Recovery #1C - Loader #100 bytes, bitstream #3F00 bytes #1D - Bitstream #4000 bytes #1E - Bitstream #4000 bytes diff --git a/src/bios/old_files/DCP_PAGE.bin b/src/bios/old_files/DCP_PAGE.bin deleted file mode 100644 index 8f766b8..0000000 Binary files a/src/bios/old_files/DCP_PAGE.bin and /dev/null differ diff --git a/src/bios/old_files/EXP_DCP.LZ b/src/bios/old_files/EXP_DCP.LZ deleted file mode 100644 index d0f93ea..0000000 Binary files a/src/bios/old_files/EXP_DCP.LZ and /dev/null differ diff --git a/src/bios/old_files/EXP_DCP2.asm b/src/bios/old_files/EXP_DCP2.asm deleted file mode 100644 index 9c7bd28..0000000 --- a/src/bios/old_files/EXP_DCP2.asm +++ /dev/null @@ -1,460 +0,0 @@ -; - IFN SET_NEWdcp -;-----------------------------------------------------------------------; -; !TODO сравнить как запакуется DCP алгоритмом для k50 -DCP_INIT: - EXX - LD HL,DCP_DATA - LD DE,#C000 -.loop0: - LD B,8 - LD C,(HL) - INC HL -.loop1: - RLC C - JR C,.loop2 - SUB A - LD (DE),A - INC DE - DJNZ .loop1 - JR .loop3 -.loop2: - LD A,(HL) - INC HL - LD (DE),A - INC DE - DJNZ .loop1 -.loop3: - inc d - dec d - JR NZ,.loop0 - - LD HL,#C000 ; CONFIG-3 for DOS & other fns - LD DE,#F000 - LD BC,#0400 - LDIR - LD HL,#F000 - LD DE,#F400 - LD BC,#0C00 - LDIR - -; First IN command - OPEN DCP - IN A,(SLOT3) - EXX - JP (HL) -;-----------------------------------------------------------------------; - - ELSE - -;-----------------------------------------------------------------------; -DCP_INIT: - LD C,XL - LD B,XH - LD E,YL - LD D,YH - EXX - - LD HL,#C000 - LD DE,#C001 - LD BC,#3FFF - LD (HL),L - LDIR - - LD IY,.data - LD IX,.ret - -.loop: - LD L,(IY) - LD H,(IY+1) - LD E,(IY+2) - LD D,(IY+3) - LD B,(IY+4) - JR DCP_FN0M - -.ret: - LD BC,5 - ADD IY,BC - LD A,(IY+2) - OR (IY+3) - JR NZ,.loop - - EXX - LD XL,C - LD XH,B - LD YL,E - LD YH,D - -; First IN command - OPEN DCP - IN A,(SLOT3) - JP (HL) -;-----------------------------------------------------------------------; - ENDIF - - -;-----------------------------------------------------------------------; -; Функция дешифратора портов. -; HL - адрес -; DE - маска - 0 изменяемые биты, 1 неизменяемые -; B - порт - -DCP_FN0M: - LD A,L - AND E - LD L,A - - LD A,H - AND D -; AND #3F - OR #C0 - LD H,A - - LD A,D - OR #C0 - LD D,A - -.loop: LD (HL),B - - LD A,L ; замаскировать неизменяемые биты 1-ми - OR E ; для прохождения переноса - INC A ; увеличить адрес - JR Z,.carry ; возник перенос - - OR E - XOR E ; обнулить неизменяемые биты - LD C,A ; изменяемая часть - - LD A,L - AND E ; выделить неизменяемую - OR C - LD L,A ; добавить изменяемую часть - - JR .loop ; цикл - -.carry: ; A = 0 -; OR E -; XOR E -; LD C,A - LD A,L ; забить изменяемые биты нулями - AND E -; OR C - LD L,A - - LD A,H ; замаскировать неизменяемые биты 1-ми - OR D ; для прохождения переноса - INC A ; увеличить адрес - JR Z,.exit - - OR D - XOR D - LD C,A ; изменяемая часть - - LD A,H - AND D ; выделить неизменяемую - OR C - LD H,A ; добавить изменяемую часть - JR .loop - -.exit: JP (IX) -; - - IF SET_NEWdcp -;-----------------------------------------------------------------------; -; DATA FOR DCP -; вбиваем в таблицу DCP.XLSX нужный внешний порт, -; смотрим смещение для OUT (С),x - это адрес -; -; C C E D / A A A A A A A A A -; N N 1 O W 1 1 6 5 1 7 2 1 0 -; F F 2 S R 5 4 3 -; 1 0 8 -; -; CCED/AAAAAAAAA -; NN1OW116517210 -; FF2SR54 3 -DCP_INIT.data: ; 108 -; Border ....0..11.1110 - DW %00000001101110 ; - адрес - DW %00001001101111 ; - маска - 0 изменяемые биты, 1 неизменяемые - DB #C2 ; - порт -; Keyboard ....1..11.1110 - DW %00001001101110 - DW %00001001101111 - DB #40 -; Kempston ...11..00.0111 - DW %00011000000111 - DW %00011001101111 - DB #15 - -; DRQ/INTRQ ...01..11.1111 - DW %00001001101111 - DW %00011001101111 - DB #15 -; WR_PDOS ...00..11.1111 - DW %00000001101111 - DW %00011001101111 - DB #14 -; CS_WG93_1F ...0...00.0111 - DW %00000000000111 - DW %00010001101111 - DB #10 -; CS_WG93_3F ...0...01.0111 - DW %00000000100111 - DW %00010001101111 - DB #11 -; CS_WG93_5F ...0...10.0111 - DW %00000001000111 - DW %00010001101111 - DB #12 -; CS_WG93_7F ...0...11.0111 - DW %00000001100111 - DW %00010001101111 - DB #13 -; -; CNF_PORT ........1.0100 - DW %00000000100100 - DW %00000000101111 - DB #C6 -; -; SOUND_BFFD_WR ....0101111101 - DW %00000101111101 - DW %00001111111111 - DB #91 -; SOUND_FFFD_WR ....0111111101 - DW %00000111111101 - DW %00001111111111 - DB #90 -; SOUND_FFFD_RD ....11.1111101 - DW %00001101111101 - DW %00001101111111 - DB #00 -; -; COVOX_4F ...10.....0111 - DW %00010000000111 - DW %00011000001111 - DB #88 -; COVOX_FB ...10..11.1011 - DW %00010001101011 - DW %00011001101111 - DB #88 -; CASH__FB ...11..11..011 - DW %00011001100011 - DW %00011001100111 - DB #88 -; CASH__80 ...11..00.1000 - DW %00011000001000 - DW %00011001101111 - DB #88 -; -; P_XTR ...1...01.1.11 - DW %00010000101011 - DW %00010001101011 - DB #32 -; -; SC_256_1FFDH 0....001101101 - DW %00000001101101 - DW %10000111111111 - DB #C0 -; ZX_128_7FFDH 0.0..0111.1101 - DW %00000011101101 - DW %10100111101111 - DB #C1 -; ZX_128_7FFDH 0..0.0111.1101 - DW %00000011101101 - DW %10010111101111 - DB #C1 - -; ZX_128_7FFDH 100..0.11.1101 - DW %10000001101101 - DW %11100101101111 - DB #C1 -; ZX_128_7FFDH 10.0.0.11.1101 - DW %10000001101101 - DW %11010101101111 - DB #C1 - -; SC_256_1FFDH 11...001101101 - DW %11000001101101 - DW %11000111111111 - DB #C0 -; ZX_128_7FFDH 110..0111.1101 - DW %11000011101101 - DW %11100111101111 - DB #C1 -; ZX_128_7FFDH 11.0.0111.1101 - DW %11000011101101 - DW %11010111101111 - DB #C1 -; -; HDD_DATA ...0...10.0000 - DW %00000001000000 - DW %00010001101111 - DB #20 -; HDD_1F1 ...0.0010.0001 - DW %00000001000001 - DW %00010111101111 - DB #21 -; HDD_1F2 ...0.0010.0010 - DW %00000001000010 - DW %00010111101111 - DB #22 -; HDD_1F3 ...0.0010.0011 - DW %00000001000011 - DW %00010111101111 - DB #23 -; HDD_1F4 ...0.0010.0100 - DW %00000001000100 - DW %00010111101111 - DB #24 -; HDD_1F5 ...0.0010.0101 - DW %00000001000101 - DW %00010111101111 - DB #25 -; HDD_1F6 ...0.0110.0010 - DW %00000011000010 - DW %00010111101111 - DB #26 -; HDD_1F7 ...0.0110.0011 - DW %00000011000011 - DW %00010111101111 - DB #27 -; HDD_3F6 ...0.0110.0100 - DW %00000011000100 - DW %00010111101111 - DB #28 -; HDD_3F7 ...0.0110.0101 - DW %00000011000101 - DW %00010111101111 - DB #29 -; -; HDD_DATA 00.....10.0000 - DW %00000001000000 - DW %11000001101111 - DB #20 -; HDD_1F1 00...0010.0001 - DW %00000001000001 - DW %11000111101111 - DB #21 -; HDD_1F2 00...0010.0010 - DW %00000001000010 - DW %11000111101111 - DB #22 -; HDD_1F3 00...0010.0011 - DW %00000001000011 - DW %11000111101111 - DB #23 -; HDD_1F4 00...0010.0100 - DW %00000001000100 - DW %11000111101111 - DB #24 -; HDD_1F5 00...0010.0101 - DW %00000001000101 - DW %11000111101111 - DB #25 -; HDD_1F6 00...0110.0010 - DW %00000011000010 - DW %11000111101111 - DB #26 -; HDD_1F7 00...0110.0011 - DW %00000011000011 - DW %11000111101111 - DB #27 -; HDD_3F6 00...0110.0100 - DW %00000011000100 - DW %11000111101111 - DB #28 -; HDD_3F7 00...0110.0101 - DW %00000011000101 - DW %11000111101111 - DB #29 -; -; PAGE0 ...0...00.1010 - DW %00000000001010 - DW %00010001101111 - DB #E8 -; PAGE1 ...0...01.1010 - DW %00000000101010 - DW %00010001101111 - DB #E9 -; PAGE2 ...0...10.1010 - DW %00000001001010 - DW %00010001101111 - DB #EA -; PAGE3 ...0...11.1010 - DW %00000001101010 - DW %00010001101111 - DB #F0 -; -; PAGE0 00.....00.1010 - DW %00000000001010 - DW %11000001101111 - DB #E8 -; PAGE1 00.....01.1010 - DW %00000000101010 - DW %11000001101111 - DB #E9 -; PAGE2 00.....10.1010 - DW %00000001001010 - DW %11000001101111 - DB #EA -; PAGE3 00.....11.1010 - DW %00000001101010 - DW %11000001101111 - DB #F0 -; -; Y_PORT(RGADR) ...0...00.1001 - DW %00000000001001 - DW %00010001101111 - DB #C4 -; RGMOD ...0...10.1001 - DW %00000001001001 - DW %00010001101111 - DB #C5 -; -; Y_PORT(RGADR) 00.....00.1001 - DW %00000000001001 - DW %11000001101111 - DB #C4 -; RGMOD 00.....10.1001 - DW %00000001001001 - DW %11000001101111 - DB #C5 -; -; ISA_REG ...00100101101 - DW %00000100101101 - DW %00011111111111 - DB #1B -; CMOS_DWR ...001.0111101 - DW %00000100111101 - DW %00011101111111 - DB #1E -; CMOS_AWR ...00110101101 - DW %00000110101101 - DW %00011111111111 - DB #1D -; CMOS_DRD ...011.0111101 - DW %00001100111101 - DW %00011101111111 - DB #1C -; -; ISA_REG 00..0100101101 - DW %00000100101101 - DW %11001111111111 - DB #1B -; CMOS_DWR 00..01.0111101 - DW %00000100111101 - DW %11001101111111 - DB #1E -; CMOS_AWR 00..0110101101 - DW %00000110101101 - DW %11001111111111 - DB #1D -; CMOS_DRD 00..11.0111101 - DW %00001100111101 - DW %11001101111111 - DB #1C - -; DCP END MARKER - DW 0,0,0 -;-----------------------------------------------------------------------; - ENDIF -; \ No newline at end of file diff --git a/src/bios/old_files/EXP_DCP_GENERATOR.ASM b/src/bios/old_files/EXP_DCP_GENERATOR.ASM deleted file mode 100644 index 082adbb..0000000 --- a/src/bios/old_files/EXP_DCP_GENERATOR.ASM +++ /dev/null @@ -1,9 +0,0 @@ - - DEFINE FNAME_DCPpage './src/bios/old_files/DCP_PAGE.bin' - DEFINE FNAME_DCP './src/bios/old_files/EXP_DCP_TABLE_GENERATED.ASM' - - includelua 'Shared_includes/lua/Functions.lua' - - LUA PASS1 - Generate_DCPASM_fromPAGE(sj.get_define("FNAME_DCPpage"), sj.get_define("FNAME_DCP")) - ENDLUA diff --git a/src/bios/old_files/EXP_DCP_TABLE_GENERATED.ASM b/src/bios/old_files/EXP_DCP_TABLE_GENERATED.ASM deleted file mode 100644 index 1a1b144..0000000 --- a/src/bios/old_files/EXP_DCP_TABLE_GENERATED.ASM +++ /dev/null @@ -1,639 +0,0 @@ -; -;-----------------------------------------------------------------------; - -; - DW %00000000000111 - DW %11010001101111 - DB #10 -; - DW %01000000000111 - DW %11010001101111 - DB #10 -; - DW %10000000000111 - DW %11010001101111 - DB #10 -; - DW %11000000000111 - DW %11000001101111 - DB #10 -; - DW %00000000100111 - DW %11010001101111 - DB #11 -; - DW %01000000100111 - DW %11010001101111 - DB #11 -; - DW %10000000100111 - DW %11010001101111 - DB #11 -; - DW %11000000100111 - DW %11000001101111 - DB #11 -; - DW %00000001000111 - DW %11010001101111 - DB #12 -; - DW %01000001000111 - DW %11010001101111 - DB #12 -; - DW %10000001000111 - DW %11010001101111 - DB #12 -; - DW %11000001000111 - DW %11000001101111 - DB #12 -; - DW %00000001100111 - DW %11010001101111 - DB #13 -; - DW %01000001100111 - DW %11010001101111 - DB #13 -; - DW %10000001100111 - DW %11010001101111 - DB #13 -; - DW %11000001100111 - DW %11000001101111 - DB #13 -; - DW %00000001101111 - DW %11011001101111 - DB #14 -; - DW %01000001101111 - DW %11011001101111 - DB #14 -; - DW %10000001101111 - DW %11011001101111 - DB #14 -; - DW %11000001101111 - DW %11001001101111 - DB #14 -; - DW %00001000000111 - DW %11001000000111 - DB #15 -; - DW %01001000000111 - DW %11001000000111 - DB #15 -; - DW %10001000000111 - DW %11001000000111 - DB #15 -; - DW %11001001101111 - DW %11001001101111 - DB #15 -; - DW %00000000101101 - DW %11011111111111 - DB #16 -; - DW %11000000101101 - DW %11001111111111 - DB #16 -; - DW %00000000111101 - DW %11011111111111 - DB #17 -; - DW %11000000111101 - DW %11001111111111 - DB #17 -; - DW %10000100101101 - DW %11010111111111 - DB #18 -; - DW %10000100111101 - DW %11010111111111 - DB #19 -; - DW %10000110101101 - DW %11010111111111 - DB #1A -; - DW %00000100101101 - DW %11001111111111 - DB #1B -; - DW %10000110111101 - DW %11010111111111 - DB #1B -; - DW %11000100101101 - DW %11001111111111 - DB #1B -; - DW %00001100111101 - DW %11001101111111 - DB #1C -; - DW %11001100111101 - DW %11001101111111 - DB #1C -; - DW %00000110101101 - DW %11001111111111 - DB #1D -; - DW %11000110101101 - DW %11001111111111 - DB #1D -; - DW %00000100111101 - DW %11001101111111 - DB #1E -; - DW %11000100111101 - DW %11001101111111 - DB #1E -; - DW %00000001000000 - DW %11000001101111 - DB #20 -; - DW %01000001000000 - DW %11010001101111 - DB #20 -; - DW %10000001000000 - DW %11010001101111 - DB #20 -; - DW %11000001000000 - DW %11000001101111 - DB #20 -; - DW %00000001000001 - DW %11000111101111 - DB #21 -; - DW %01000001000001 - DW %11010111101111 - DB #21 -; - DW %10000001000001 - DW %11010111101111 - DB #21 -; - DW %11000001000001 - DW %11000111101111 - DB #21 -; - DW %00000001000010 - DW %11000111101111 - DB #22 -; - DW %01000001000010 - DW %11010111101111 - DB #22 -; - DW %10000001000010 - DW %11010111101111 - DB #22 -; - DW %11000001000010 - DW %11000111101111 - DB #22 -; - DW %00000001000011 - DW %11000111101111 - DB #23 -; - DW %01000001000011 - DW %11010111101111 - DB #23 -; - DW %10000001000011 - DW %11010111101111 - DB #23 -; - DW %11000001000011 - DW %11000111101111 - DB #23 -; - DW %00000001000100 - DW %11000111101111 - DB #24 -; - DW %01000001000100 - DW %11010111101111 - DB #24 -; - DW %10000001000100 - DW %11010111101111 - DB #24 -; - DW %11000001000100 - DW %11000111101111 - DB #24 -; - DW %00000001000101 - DW %11000111101111 - DB #25 -; - DW %01000001000101 - DW %11010111101111 - DB #25 -; - DW %10000001000101 - DW %11010111101111 - DB #25 -; - DW %11000001000101 - DW %11000111101111 - DB #25 -; - DW %00000011000010 - DW %11000111101111 - DB #26 -; - DW %01000011000010 - DW %11010111101111 - DB #26 -; - DW %10000011000010 - DW %11010111101111 - DB #26 -; - DW %11000011000010 - DW %11000111101111 - DB #26 -; - DW %00000011000011 - DW %11000111101111 - DB #27 -; - DW %01000011000011 - DW %11010111101111 - DB #27 -; - DW %10000011000011 - DW %11010111101111 - DB #27 -; - DW %11000011000011 - DW %11000111101111 - DB #27 -; - DW %00000011000100 - DW %11000111101111 - DB #28 -; - DW %01000011000100 - DW %11010111101111 - DB #28 -; - DW %10000011000100 - DW %11010111101111 - DB #28 -; - DW %11000011000100 - DW %11000111101111 - DB #28 -; - DW %00000011000101 - DW %11000111101111 - DB #29 -; - DW %01000011000101 - DW %11010111101111 - DB #29 -; - DW %10000011000101 - DW %11010111101111 - DB #29 -; - DW %11000011000101 - DW %11000111101111 - DB #29 -; - DW %00000000101100 - DW %11001111111111 - DB #2A -; - DW %11000000101100 - DW %11001111111111 - DB #2A -; - DW %00000000111100 - DW %11001111111111 - DB #2B -; - DW %11000000111100 - DW %11001111111111 - DB #2B -; - DW %00000010101101 - DW %11001111111111 - DB #2C -; - DW %11000010101101 - DW %11001111111111 - DB #2C -; - DW %00000010111101 - DW %11001111111111 - DB #2D -; - DW %11000010111101 - DW %11001111111111 - DB #2D -; - DW %00000010101100 - DW %11001111111111 - DB #2E -; - DW %11000010101100 - DW %11001111111111 - DB #2E -; - DW %00000010111100 - DW %11001111111111 - DB #2F -; - DW %11000010111100 - DW %11001111111111 - DB #2F -; - DW %00010000101011 - DW %11010001101011 - DB #32 -; - DW %00011001101110 - DW %11011001101111 - DB #40 -; - DW %01011001101110 - DW %11011001101111 - DB #40 -; - DW %10011001101110 - DW %11011001101111 - DB #40 -; - DW %00001111111101 - DW %11001111111111 - DB #52 -; - DW %01001111111101 - DW %11001111111111 - DB #52 -; - DW %10001111111101 - DW %11001111111111 - DB #52 -; - DW %11001111111101 - DW %11001111111111 - DB #52 -; - DW %00001111011111 - DW %11001111111111 - DB #58 -; - DW %11001111011111 - DW %11001111111111 - DB #58 -; - DW %00010000000000 - DW %11010000000000 - DB #88 -; - DW %01010001100011 - DW %11010001100111 - DB #88 -; - DW %10010001100011 - DW %11010001100111 - DB #88 -; - DW %00000001000110 - DW %11001111111111 - DB #89 -; - DW %11000001000110 - DW %11001111111111 - DB #89 -; - DW %00000111111101 - DW %11001111111111 - DB #90 -; - DW %01000111111101 - DW %11001111111111 - DB #90 -; - DW %10000111111101 - DW %11001111111111 - DB #90 -; - DW %11000111111101 - DW %11001111111111 - DB #90 -; - DW %00000101111101 - DW %11001111111111 - DB #91 -; - DW %01000101111101 - DW %11001111111111 - DB #91 -; - DW %10000101111101 - DW %11001111111111 - DB #91 -; - DW %11000101111101 - DW %11001111111111 - DB #91 -; - DW %00000001101101 - DW %11000111111111 - DB #C0 -; - DW %01000001101101 - DW %11000111111111 - DB #C0 -; - DW %11000001101101 - DW %11000111111111 - DB #C0 -; - DW %00000011101101 - DW %11000111101111 - DB #C1 -; - DW %01000011101101 - DW %11100111101111 - DB #C1 -; - DW %10000001101101 - DW %11100101101111 - DB #C1 -; - DW %11000011101101 - DW %11000111101111 - DB #C1 -; - DW %00000001101110 - DW %11001001101111 - DB #C2 -; - DW %01000001101110 - DW %11001001101111 - DB #C2 -; - DW %10000001101110 - DW %11001001101111 - DB #C2 -; - DW %11000001101110 - DW %11001001101111 - DB #C2 -; - DW %00000001010110 - DW %11001111111111 - DB #C3 -; - DW %11000001010110 - DW %11001111111111 - DB #C3 -; - DW %00000000001001 - DW %11000001101111 - DB #C4 -; - DW %01000000001001 - DW %11010001101111 - DB #C4 -; - DW %10000000001001 - DW %11010001101111 - DB #C4 -; - DW %11000000001001 - DW %11000001101111 - DB #C4 -; - DW %00000001001001 - DW %11000001101111 - DB #C5 -; - DW %01000001001001 - DW %11010001101111 - DB #C5 -; - DW %10000001001001 - DW %11010001101111 - DB #C5 -; - DW %11000001001001 - DW %11000001101111 - DB #C5 -; - DW %00000000100100 - DW %11000000101111 - DB #C6 -; - DW %01000000100100 - DW %11000000101111 - DB #C6 -; - DW %10000000100100 - DW %11000000101111 - DB #C6 -; - DW %11000000100100 - DW %11000000101111 - DB #C6 -; - DW %00000001101100 - DW %11001001101111 - DB #C7 -; - DW %11000001101100 - DW %11001001101111 - DB #C7 -; - DW %00000000001010 - DW %11000001101111 - DB #E8 -; - DW %01000000001010 - DW %11010001101111 - DB #E8 -; - DW %10000000001010 - DW %11010001101111 - DB #E8 -; - DW %11000000001010 - DW %11000001101111 - DB #E8 -; - DW %00000000101010 - DW %11000001101111 - DB #E9 -; - DW %01000000101010 - DW %11010001101111 - DB #E9 -; - DW %10000000101010 - DW %11010001101111 - DB #E9 -; - DW %11000000101010 - DW %11000001101111 - DB #E9 -; - DW %00000001001010 - DW %11000001101111 - DB #EA -; - DW %01000001001010 - DW %11010001101111 - DB #EA -; - DW %10000001001010 - DW %11010001101111 - DB #EA -; - DW %11000001001010 - DW %11000001101111 - DB #EA -; - DW %00000001101010 - DW %11000001101111 - DB #F0 -; - DW %01000001101010 - DW %11010001101111 - DB #F0 -; - DW %10000001101010 - DW %11010001101111 - DB #F0 -; - DW %11000001101010 - DW %11000001101111 - DB #F0 -; DCP END MARKER - DW 0,0,0 -;-----------------------------------------------------------------------; -; \ No newline at end of file diff --git a/src/bios/old_files/EXP_DCP_UNPACKER.asm b/src/bios/old_files/EXP_DCP_UNPACKER.asm deleted file mode 100644 index 1e7964d..0000000 --- a/src/bios/old_files/EXP_DCP_UNPACKER.asm +++ /dev/null @@ -1,110 +0,0 @@ -; -;-----------------------------------------------------------------------; -; !TODO сравнить как запакуется DCP алгоритмом для k50 -DCP_INIT: - EXX - LD HL,DCP_DATA - LD DE,#C000 -.loop0: - LD B,8 - LD C,(HL) - INC HL -.loop1: - RLC C - JR C,.loop2 - SUB A - LD (DE),A - INC DE - DJNZ .loop1 - JR .loop3 -.loop2: - LD A,(HL) - INC HL - LD (DE),A - INC DE - DJNZ .loop1 -.loop3: - INC D - DEC D - JR NZ,.loop0 - - LD HL,#C000 ; CONFIG-3 for DOS & other fns - LD DE,#F000 - LD BC,#0400 - LDIR ; DE = #F400 !!! - LD HL,#F000 - ;LD DE,#F400 - LD BC,#0C00 - LDIR - -; First IN command - OPEN DCP - IN A,(SLOT3) - EXX - JP (HL) -;-----------------------------------------------------------------------; - - -;-----------------------------------------------------------------------; -; Функция дешифратора портов. -; HL - адрес -; DE - маска - 0 изменяемые биты, 1 неизменяемые -; B - порт -; DCP_FN0M: -; LD A,L -; AND E -; LD L,A - -; LD A,H -; AND D -; ; AND #3F -; OR #C0 -; LD H,A - -; LD A,D -; OR #C0 -; LD D,A - -; .loop: LD (HL),B - -; LD A,L ; замаскировать неизменяемые биты 1-ми -; OR E ; для прохождения переноса -; INC A ; увеличить адрес -; JR Z,.carry ; возник перенос - -; OR E -; XOR E ; обнулить неизменяемые биты -; LD C,A ; изменяемая часть - -; LD A,L -; AND E ; выделить неизменяемую -; OR C -; LD L,A ; добавить изменяемую часть - -; JR .loop ; цикл - -; .carry: ; A = 0 -; ; OR E -; ; XOR E -; ; LD C,A -; LD A,L ; забить изменяемые биты нулями -; AND E -; ; OR C -; LD L,A - -; LD A,H ; замаскировать неизменяемые биты 1-ми -; OR D ; для прохождения переноса -; INC A ; увеличить адрес -; JR Z,.exit - -; OR D -; XOR D -; LD C,A ; изменяемая часть - -; LD A,H -; AND D ; выделить неизменяемую -; OR C -; LD H,A ; добавить изменяемую часть -; JR .loop - -; .exit: JP (IX) -;-----------------------------------------------------------------------; diff --git a/src/bios/old_files/FONT.FNT b/src/bios/old_files/FONT.FNT deleted file mode 100644 index 441e654..0000000 Binary files a/src/bios/old_files/FONT.FNT and /dev/null differ diff --git a/src/bios/old_files/SP_EXP2_dasm.asm b/src/bios/old_files/SP_EXP2_dasm.asm deleted file mode 100644 index fee15df..0000000 --- a/src/bios/old_files/SP_EXP2_dasm.asm +++ /dev/null @@ -1,565 +0,0 @@ -; z80dasm 1.2.0 -; command line: z80dasm -a -l -u -t -g 0x0000 -o /Users/tolik/Library/CloudStorage/GoogleDrive-tolik.trek@gmail.com/╨Ь╨╛╨╣ ╨┤╨╕╤Б╨║/Progs/ASM/GIT/DSS 1.70b/Build/SP_EXP2_dasm.a80 /Users/tolik/Downloads/SP_EXP2.BIN - - org 00000h -;-----------------------------------------------------------------------; -l0000h: di ;0000 f3 . - halt ;0001 76 v -; - BLOCK #10-$,#FF - ret ;0010 c9 . -; - BLOCK #38-$,#FF - ei ;0038 fb . - reti ;0039 ed 4d . M -; - BLOCK #66-$,#C9 - retn ;0066 ed 45 . E -; -;-----------------------------------------------------------------------; -; - -; -;-----------------------------------------------------------------------; - BLOCK #100-$,#FF -l0100h: pop af ;0100 f1 . - call sub_010eh ;0101 cd 0e 01 . . . - jp l3fe8h ;0104 c3 e8 3f . . ? -l0107h: - pop af ;0107 f1 . - call sub_010eh ;0108 cd 0e 01 . . . - jp l3ff0h ;010b c3 f0 3f . . ? - - -sub_010eh: - push af ;010e f5 . - ld a,c ;010f 79 y - and a ;0110 a7 . - jp z,l030ch ;0111 ca 0c 03 . . . - dec a ;0114 3d = - jp z,l02b1h ;0115 ca b1 02 . . . - dec a ;0118 3d = - jp z,l02cch ;0119 ca cc 02 . . . - dec a ;011c 3d = - jp z,l017bh ;011d ca 7b 01 . { . - dec a ;0120 3d = - jp z,l019ch ;0121 ca 9c 01 . . . - dec a ;0124 3d = - jp z,l01a7h ;0125 ca a7 01 . . . - dec a ;0128 3d = - jp z,l0247h ;0129 ca 47 02 . G . - dec a ;012c 3d = - jp z,l0424h ;012d ca 24 04 . $ . - pop af ;0130 f1 . - scf ;0131 37 7 - ret ;0132 c9 . - - -sub_0133h: - ld d,a ;0133 57 W - in a,(0e2h) ;0134 db e2 . . - ex af,af' ;0136 08 . - ld a,0feh ;0137 3e fe > . - out (0e2h),a ;0139 d3 e2 . . - ld a,(0c60ch) ;013b 3a 0c c6 : . . - ld e,a ;013e 5f _ - ex af,af' ;013f 08 . - out (0e2h),a ;0140 d3 e2 . . - ld a,d ;0142 7a z - ld d,000h ;0143 16 00 . . - ld ix,0 ;0145 dd 21 00 00 . ! . . - ld b,001h ;0149 06 01 . . -sub_014bh: - push af ;014b f5 . - push hl ;014c e5 . - call sub_03d4h ;014d cd d4 03 . . . -l0150h: - jr nc,l0156h ;0150 30 04 0 . -l0152h: - pop hl ;0152 e1 . -l0153h: - pop af ;0153 f1 . -l0154h: - scf ;0154 37 7 -l0155h: - ret ;0155 c9 . -l0156h: - ld a,b ;0156 78 x - ld bc,l0152h ;0157 01 52 01 . R . - out (c),a ;015a ed 79 . y - ld bc,l0153h ;015c 01 53 01 . S . - out (c),l ;015f ed 69 . i - ld bc,l0154h ;0161 01 54 01 . T . - out (c),e ;0164 ed 59 . Y - ld bc,l0155h ;0166 01 55 01 . U . - out (c),d ;0169 ed 51 . Q - ld bc,04152h ;016b 01 52 41 . R A - dec b ;016e 05 . - in a,(c) ;016f ed 78 . x - and 0f0h ;0171 e6 f0 . . - or h ;0173 b4 . - inc b ;0174 04 . - out (c),a ;0175 ed 79 . y - pop hl ;0177 e1 . - pop af ;0178 f1 . - and a ;0179 a7 . - ret ;017a c9 . -l017bh: - pop af ;017b f1 . - and a ;017c a7 . - inc b ;017d 04 . - dec b ;017e 05 . - ret z ;017f c8 . - call sub_03aeh ;0180 cd ae 03 . . . - ret c ;0183 d8 . - call sub_014bh ;0184 cd 4b 01 . K . - ret c ;0187 d8 . - exx ;0188 d9 . - ld c,0e2h ;0189 0e e2 . . - in b,(c) ;018b ed 40 . @ - exx ;018d d9 . - out (0e2h),a ;018e d3 e2 . . - ex af,af' ;0190 08 . - ld a,0c0h ;0191 3e c0 > . - out (089h),a ;0193 d3 89 . . - ld bc,04153h ;0195 01 53 41 . S A - ld a,020h ;0198 3e 20 > - and a ;019a a7 . - ret ;019b c9 . -l019ch: - pop af ;019c f1 . - call sub_03aeh ;019d cd ae 03 . . . - ret c ;01a0 d8 . - call sub_0133h ;01a1 cd 33 01 . 3 . - ret c ;01a4 d8 . - jr l01b4h ;01a5 18 0d . . -l01a7h: - pop af ;01a7 f1 . - and a ;01a8 a7 . - inc b ;01a9 04 . - dec b ;01aa 05 . - ret z ;01ab c8 . - call sub_03aeh ;01ac cd ae 03 . . . - ret c ;01af d8 . - call sub_014bh ;01b0 cd 4b 01 . K . - ret c ;01b3 d8 . -l01b4h: - exx ;01b4 d9 . - ld c,0e2h ;01b5 0e e2 . . - in b,(c) ;01b7 ed 40 . @ - exx ;01b9 d9 . - out (0e2h),a ;01ba d3 e2 . . - ex af,af' ;01bc 08 . - ld a,0c0h ;01bd 3e c0 > . - out (089h),a ;01bf d3 89 . . - ld bc,04153h ;01c1 01 53 41 . S A - ld a,020h ;01c4 3e 20 > - out (c),a ;01c6 ed 79 . y -l01c8h: - ld bc,04053h ;01c8 01 53 40 . S @ - in a,(c) ;01cb ed 78 . x - bit 7,a ;01cd cb 7f . . - jr nz,l01c8h ;01cf 20 f7 . - bit 3,a ;01d1 cb 5f . _ - jr nz,l01e8h ;01d3 20 13 . - ld a,000h ;01d5 3e 00 > . - out (089h),a ;01d7 d3 89 . . -l01d9h: - exx ;01d9 d9 . - out (c),b ;01da ed 41 . A - exx ;01dc d9 . - ld bc,#0051 ;01dd 01 51 00 . Q . - in a,(c) ;01e0 ed 78 . x - and a ;01e2 a7 . - scf ;01e3 37 7 - ret nz ;01e4 c0 . - ex af,af' ;01e5 08 . - and a ;01e6 a7 . - ret ;01e7 c9 . -l01e8h: - ld bc,#0050 ;01e8 01 50 00 . P . -l01ebh: - ini ;01eb ed a2 . . - ini ;01ed ed a2 . . - ini ;01ef ed a2 . . - ini ;01f1 ed a2 . . - ini ;01f3 ed a2 . . - ini ;01f5 ed a2 . . - ini ;01f7 ed a2 . . - ini ;01f9 ed a2 . . - ini ;01fb ed a2 . . - ini ;01fd ed a2 . . - ini ;01ff ed a2 . . - ini ;0201 ed a2 . . - ini ;0203 ed a2 . . - ini ;0205 ed a2 . . - ini ;0207 ed a2 . . - ini ;0209 ed a2 . . - jp nz,l01ebh ;020b c2 eb 01 . . . -l020eh: - ini ;020e ed a2 . . - ini ;0210 ed a2 . . - ini ;0212 ed a2 . . - ini ;0214 ed a2 . . - ini ;0216 ed a2 . . - ini ;0218 ed a2 . . - ini ;021a ed a2 . . - ini ;021c ed a2 . . - ini ;021e ed a2 . . - ini ;0220 ed a2 . . - ini ;0222 ed a2 . . - ini ;0224 ed a2 . . - ini ;0226 ed a2 . . - ini ;0228 ed a2 . . - ini ;022a ed a2 . . - ini ;022c ed a2 . . - jp nz,l020eh ;022e c2 0e 02 . . . - ld a,h ;0231 7c | - or l ;0232 b5 . - jr nz,l01c8h ;0233 20 93 . - ld a,0feh ;0235 3e fe > . - out (0e2h),a ;0237 d3 e2 . . - ex af,af' ;0239 08 . - ld hl,0c200h ;023a 21 00 c2 ! . . - ld l,a ;023d 6f o - ld a,(hl) ;023e 7e ~ - out (0e2h),a ;023f d3 e2 . . - ex af,af' ;0241 08 . - ld hl,0c000h ;0242 21 00 c0 ! . . - jr l01c8h ;0245 18 81 . . -l0247h: - pop af ;0247 f1 . - and a ;0248 a7 . - inc b ;0249 04 . - dec b ;024a 05 . - ret z ;024b c8 . - call sub_03aeh ;024c cd ae 03 . . . - ret c ;024f d8 . - call sub_014bh ;0250 cd 4b 01 . K . -l0253h: - ret c ;0253 d8 . - exx ;0254 d9 . - ld c,0e2h ;0255 0e e2 . . - in b,(c) ;0257 ed 40 . @ - exx ;0259 d9 . - out (0e2h),a ;025a d3 e2 . . - ex af,af' ;025c 08 . - ld bc,04153h ;025d 01 53 41 . S A - ld a,030h ;0260 3e 30 > 0 - out (c),a ;0262 ed 79 . y -l0264h: - ld bc,04053h ;0264 01 53 40 . S @ - in a,(c) ;0267 ed 78 . x - bit 7,a ;0269 cb 7f . . - jr nz,l0264h ;026b 20 f7 . - bit 3,a ;026d cb 5f . _ - jp z,l01d9h ;026f ca d9 01 . . . - ld bc,l0150h ;0272 01 50 01 . P . - ld d,020h ;0275 16 20 . -l0277h: - outi ;0277 ed a3 . . - outi ;0279 ed a3 . . - outi ;027b ed a3 . . - outi ;027d ed a3 . . - outi ;027f ed a3 . . - outi ;0281 ed a3 . . - outi ;0283 ed a3 . . - outi ;0285 ed a3 . . - outi ;0287 ed a3 . . - outi ;0289 ed a3 . . - outi ;028b ed a3 . . - outi ;028d ed a3 . . - outi ;028f ed a3 . . - outi ;0291 ed a3 . . - outi ;0293 ed a3 . . - outi ;0295 ed a3 . . - dec d ;0297 15 . - jp nz,l0277h ;0298 c2 77 02 . w . - ld a,h ;029b 7c | - or l ;029c b5 . - jr nz,l0264h ;029d 20 c5 . - ld a,0feh ;029f 3e fe > . - out (0e2h),a ;02a1 d3 e2 . . - ex af,af' ;02a3 08 . - ld hl,0c200h ;02a4 21 00 c2 ! . . - ld l,a ;02a7 6f o - ld a,(hl) ;02a8 7e ~ - out (0e2h),a ;02a9 d3 e2 . . - ex af,af' ;02ab 08 . - ld hl,0c000h ;02ac 21 00 c0 ! . . - jr l0264h ;02af 18 b3 . . -l02b1h: - pop af ;02b1 f1 . - ld a,0a0h ;02b2 3e a0 > . - ld bc,04152h ;02b4 01 52 41 . R A - out (c),a ;02b7 ed 79 . y - ld a,090h ;02b9 3e 90 > . - call sub_03a5h ;02bb cd a5 03 . . . - and a ;02be a7 . - bit 0,a ;02bf cb 47 . G - ret z ;02c1 c8 . - ld bc,#0051 ;02c2 01 51 00 . Q . - in a,(c) ;02c5 ed 78 . x - cp 001h ;02c7 fe 01 . . - ret z ;02c9 c8 . - scf ;02ca 37 7 - ret ;02cb c9 . -l02cch: - pop af ;02cc f1 . - ld e,000h ;02cd 1e 00 . . - ld bc,04152h ;02cf 01 52 41 . R A - ld a,0a0h ;02d2 3e a0 > . - out (c),a ;02d4 ed 79 . y - call sub_02f1h ;02d6 cd f1 02 . . . - jr nz,l02ddh ;02d9 20 02 . - set 0,e ;02db cb c3 . . -l02ddh: - ld bc,04152h ;02dd 01 52 41 . R A - ld a,0b0h ;02e0 3e b0 > . - out (c),a ;02e2 ed 79 . y - call sub_02f1h ;02e4 cd f1 02 . . . - jr nz,l02ebh ;02e7 20 02 . - set 1,e ;02e9 cb cb . . -l02ebh: - ld a,e ;02eb 7b { - and a ;02ec a7 . - scf ;02ed 37 7 - ret z ;02ee c8 . - and a ;02ef a7 . - ret ;02f0 c9 . -sub_02f1h: - ld hl,001feh ;02f1 21 fe 01 ! . . - ld bc,l0152h ;02f4 01 52 01 . R . - out (c),l ;02f7 ed 69 . i - ld bc,l0153h ;02f9 01 53 01 . S . - out (c),h ;02fc ed 61 . a - ld bc,00252h ;02fe 01 52 02 . R . - in a,(c) ;0301 ed 78 . x - cp l ;0303 bd . - ret nz ;0304 c0 . - ld bc,l0253h ;0305 01 53 02 . S . - in a,(c) ;0308 ed 78 . x - cp h ;030a bc . - ret ;030b c9 . -l030ch: - pop af ;030c f1 . - ld bc,04152h ;030d 01 52 41 . R A - ld a,0a0h ;0310 3e a0 > . - out (c),a ;0312 ed 79 . y - call sub_02f1h ;0314 cd f1 02 . . . - jr nz,l0338h ;0317 20 1f . -l0319h: - ld bc,04053h ;0319 01 53 40 . S @ - in a,(c) ;031c ed 78 . x - bit 7,a ;031e cb 7f . . - jr nz,l0319h ;0320 20 f7 . - ld bc,04153h ;0322 01 53 41 . S A - ld a,0ech ;0325 3e ec > . - out (c),a ;0327 ed 79 . y -l0329h: - ld bc,04053h ;0329 01 53 40 . S @ - in a,(c) ;032c ed 78 . x - bit 7,a ;032e cb 7f . . - jr nz,l0329h ;0330 20 f7 . - bit 3,a ;0332 cb 5f . _ - jr nz,l0346h ;0334 20 10 . - scf ;0336 37 7 - ret ;0337 c9 . -l0338h: - ld bc,04152h ;0338 01 52 41 . R A - ld a,0b0h ;033b 3e b0 > . - out (c),a ;033d ed 79 . y - call sub_02f1h ;033f cd f1 02 . . . - jr z,l0319h ;0342 28 d5 ( . - scf ;0344 37 7 - ret ;0345 c9 . -l0346h: - ld bc,#0050 ;0346 01 50 00 . P . - ld hl,0c600h ;0349 21 00 c6 ! . . - in a,(0e2h) ;034c db e2 . . - ld d,a ;034e 57 W - ld a,0feh ;034f 3e fe > . - out (0e2h),a ;0351 d3 e2 . . - inir ;0353 ed b2 . . - inir ;0355 ed b2 . . - ld a,(0c60ch) ;0357 3a 0c c6 : . . - ld c,a ;035a 4f O - ld b,000h ;035b 06 00 . . - ld hl,0 ;035d 21 00 00 ! . . - ld a,(0c606h) ;0360 3a 06 c6 : . . -l0363h: - add hl,bc ;0363 09 . - dec a ;0364 3d = - jr nz,l0363h ;0365 20 fc . - ld (0c604h),hl ;0367 22 04 c6 " . . -l036ah: - ld bc,04053h ;036a 01 53 40 . S @ - in a,(c) ;036d ed 78 . x - bit 7,a ;036f cb 7f . . - jr nz,l036ah ;0371 20 f7 . - ld bc,04152h ;0373 01 52 41 . R A - dec b ;0376 05 . - in a,(c) ;0377 ed 78 . x - and 010h ;0379 e6 10 . . - ld b,a ;037b 47 G - ld a,(0c606h) ;037c 3a 06 c6 : . . - dec a ;037f 3d = - and 00fh ;0380 e6 0f . . - or 0a0h ;0382 f6 a0 . . - or b ;0384 b0 . - ld h,a ;0385 67 g - ld a,(0c663h) ;0386 3a 63 c6 : c . - bit 1,a ;0389 cb 4f . O - jr z,l038fh ;038b 28 02 ( . - set 6,h ;038d cb f4 . . -l038fh: - ld bc,04152h ;038f 01 52 41 . R A - out (c),h ;0392 ed 61 . a - ld a,(0c60ch) ;0394 3a 0c c6 : . . - ld bc,l0152h ;0397 01 52 01 . R . - out (c),a ;039a ed 79 . y - ld a,d ;039c 7a z - out (0e2h),a ;039d d3 e2 . . - ld a,091h ;039f 3e 91 > . - call sub_03a5h ;03a1 cd a5 03 . . . - ret ;03a4 c9 . -sub_03a5h: - call sub_03aeh ;03a5 cd ae 03 . . . - ret c ;03a8 d8 . - ld bc,04153h ;03a9 01 53 41 . S A - out (c),a ;03ac ed 79 . y -sub_03aeh: - push de ;03ae d5 . - push bc ;03af c5 . - push af ;03b0 f5 . - ld de,0 ;03b1 11 00 00 . . . -l03b4h: - ld bc,04053h ;03b4 01 53 40 . S @ - in a,(c) ;03b7 ed 78 . x - bit 7,a ;03b9 cb 7f . . - jr z,l03c7h ;03bb 28 0a ( . - dec de ;03bd 1b . - ld a,d ;03be 7a z - or e ;03bf b3 . - jr nz,l03b4h ;03c0 20 f2 . - pop af ;03c2 f1 . - pop bc ;03c3 c1 . - pop de ;03c4 d1 . - scf ;03c5 37 7 - ret ;03c6 c9 . -l03c7h: - pop af ;03c7 f1 . - pop bc ;03c8 c1 . - pop de ;03c9 d1 . - and a ;03ca a7 . - ret ;03cb c9 . -l03cch: - pop bc ;03cc c1 . - ld l,e ;03cd 6b k - ld e,d ;03ce 5a Z - ld d,ixl ;03cf dd 55 . U - xor a ;03d1 af . - ld h,a ;03d2 67 g - ret ;03d3 c9 . -sub_03d4h: - ld a,ixh ;03d4 dd 7c . | - and a ;03d6 a7 . - scf ;03d7 37 7 - ret nz ;03d8 c0 . - push bc ;03d9 c5 . - ld bc,04152h ;03da 01 52 41 . R A - dec b ;03dd 05 . - in a,(c) ;03de ed 78 . x - bit 6,a ;03e0 cb 77 . w - jr nz,l03cch ;03e2 20 e8 . - push ix ;03e4 dd e5 . . - pop hl ;03e6 e1 . - in a,(0e2h) ;03e7 db e2 . . - ld c,a ;03e9 4f O - ld a,0feh ;03ea 3e fe > . - out (0e2h),a ;03ec d3 e2 . . - ld a,c ;03ee 79 y - ld (0c107h),a ;03ef 32 07 c1 2 . . - ld bc,(0c604h) ;03f2 ed 4b 04 c6 . K . . - ld a,010h ;03f6 3e 10 > . - scf ;03f8 37 7 -l03f9h: - ex de,hl ;03f9 eb . - add hl,hl ;03fa 29 ) - ex de,hl ;03fb eb . - adc hl,hl ;03fc ed 6a . j - sbc hl,bc ;03fe ed 42 . B - jr nc,l0408h ;0400 30 06 0 . - add hl,bc ;0402 09 . - dec a ;0403 3d = - jr nz,l03f9h ;0404 20 f3 . - jr l040ch ;0406 18 04 . . -l0408h: - inc de ;0408 13 . - dec a ;0409 3d = - jr nz,l03f9h ;040a 20 ed . -l040ch: - ld a,(0c60ch) ;040c 3a 0c c6 : . . - ld b,000h ;040f 06 00 . . - ld c,a ;0411 4f O - xor a ;0412 af . -l0413h: - sbc hl,bc ;0413 ed 42 . B - inc a ;0415 3c < - jr nc,l0413h ;0416 30 fb 0 . - dec a ;0418 3d = - add hl,bc ;0419 09 . - inc l ;041a 2c , - ld h,a ;041b 67 g - ld a,(0c107h) ;041c 3a 07 c1 : . . - out (0e2h),a ;041f d3 e2 . . - pop bc ;0421 c1 . - and a ;0422 a7 . - ret ;0423 c9 . -l0424h: - pop af ;0424 f1 . - bit 0,a ;0425 cb 47 . G - ld a,021h ;0427 3e 21 > ! - jr z,l042dh ;0429 28 02 ( . - ld a,001h ;042b 3e 01 > . -l042dh: - out (0bch),a ;042d d3 bc . . - ret ;042f c9 . - -; -;-----------------------------------------------------------------------; - BLOCK #3FD0-$,#FF - push af ;3fd0 f5 . - ld a,000h ;3fd1 3e 00 > . - out (07ch),a ;3fd3 d3 7c . | - pop af ;3fd5 f1 . -l3fd6h: - ret ;3fd6 c9 . -l3fd7h: - jp l0107h ;3fd7 c3 07 01 . . . - - - BLOCK #3FE0-$,#FF -l3fe0h: - ld a,000h ;3fe0 3e 00 > . - out (03ch),a ;3fe2 d3 3c . < - jp l3fe0h ;3fe4 c3 e0 3f . . ? - rst 38h ;3fe7 ff . -l3fe8h: - push af ;3fe8 f5 . - ld a,000h ;3fe9 3e 00 > . - out (07ch),a ;3feb d3 7c . | - jp l0100h ;3fed c3 00 01 . . . -l3ff0h: - push af ;3ff0 f5 . - di ;3ff1 f3 . - ld a,000h ;3ff2 3e 00 > . - out (03ch),a ;3ff4 d3 3c . < - jr l3fd7h ;3ff6 18 df . . - push af ;3ff8 f5 . - ld a,000h ;3ff9 3e 00 > . - out (03ch),a ;3ffb d3 3c . < - jp l3fd6h ;3ffd c3 d6 3f . . ? - - BLOCK #4000-$,0 -;-----------------------------------------------------------------------; diff --git a/src/bios/rom/MEM_MAP.inc b/src/bios/rom/MEM_MAP.inc index 1852c02..2f86374 100644 --- a/src/bios/rom/MEM_MAP.inc +++ b/src/bios/rom/MEM_MAP.inc @@ -8,6 +8,7 @@ ; ROM_MAP: .EXP EQU 0 +.EXP.STACK EQU #C000 .ROM EQU 0 .LOADER EQU 0 .LOGO EQU 0 @@ -44,7 +45,7 @@ COMPILE_ADDR: .MAIN EQU #8000 .SETUP EQU #8000 .DEPACK EQU #D000 -.SETUP_STARTER EQU #C000 +.SETUP_STARTER EQU .SETUP + SETUP_MAIN.Size ;#C000 ; ; ██████╗ ███████╗██████╗ █████╗ ██████╗██╗ ██╗███████╗██████╗ ; ██╔══██╗██╔════╝██╔══██╗██╔══██╗██╔════╝██║ ██╔╝██╔════╝██╔══██╗ diff --git a/src/bios/rom/ROM.asm b/src/bios/rom/ROM.asm index 1fa2ae8..e9a3cb4 100644 --- a/src/bios/rom/ROM.asm +++ b/src/bios/rom/ROM.asm @@ -1,3 +1,6 @@ +; +; MODULE ROM_PART + DISPLAY "\r\n/=====================[ROM part]=====================\\" ;------------[Begin of ROM]------------- ROM_START: DI @@ -5,40 +8,40 @@ ROM_START: ;--------------------------------------- ;--------------[checksum]--------------- - BLOCK 4-$,#FF + _mInfoBLOCK 4-$,#FF Check_Sum: DB #FF,#FF,#FF,#FF ; место для контрольной суммы ;--------------------------------------- - BLOCK #10-$,#FF + _mInfoBLOCK #10-$,#FF RET ;--------------------------------------- ;!TODO прикрутить к ROM.BIOS ;----------------[int]------------------ - BLOCK #38-$,#FF -INT: PUSH BC - PUSH AF + _mInfoBLOCK #38-$,#FF +; INT: PUSH BC +; PUSH AF - LD C,SLOT3 - IN B,(C) - LD A,SYS_PAGE - OUT (C),A +; LD C,SLOT3 +; IN B,(C) +; LD A,SYS_PAGE +; OUT (C),A - LD A,(SYS_PAGE.INT_ID) - CP #AA - JR Z,YESINT - OUT (C),B - JR NOINT -YESINT: PUSH HL - LD HL,(SYS_PAGE.INT_ADRESS) - LD A,H - OR L - LD A,(SYS_PAGE.INT_PAGE) - OUT (C),B - CALL NZ,EXTINT - POP HL -NOINT: POP AF - POP BC +; LD A,(SYS_PAGE.INT_ID) +; CP #AA +; JR Z,YESINT +; OUT (C),B +; JR NOINT +; YESINT: PUSH HL +; LD HL,(SYS_PAGE.INT_ADRESS) +; LD A,H +; OR L +; LD A,(SYS_PAGE.INT_PAGE) +; OUT (C),B +; CALL NZ,EXTINT +; POP HL +; NOINT: POP AF +; POP BC EI RETI ;--------------------------------------- @@ -48,39 +51,113 @@ NOINT: POP AF NMI: RETN ;--------------------------------------- -;!FIXIT перенести в ROM.BIOS и сделать -; так, чтоб могла правильно прыгать в -; любые слоты и работать с DSS -;----------------[int]------------------ -EXTINT: OR A - RET Z +; ;----------------[int]------------------ +; EXTINT: OR A +; RET Z - ;LD C,SLOT1 - BIT 7,H - JR Z,.L2 - LD C,SLOT2 - BIT 6,H - JR Z,.L1 - LD C,SLOT3 +; ;LD C,SLOT1 +; BIT 7,H +; JR Z,.L2 +; LD C,SLOT2 +; BIT 6,H +; JR Z,.L1 +; LD C,SLOT3 -.L1: IN B,(C) - PUSH BC - OUT (C),A - CALL JPHL - POP BC - OUT (C),B - RET - ; проверка на нулевой слот -.L2: BIT 6,H - LD C,SLOT1 - JR NZ,.L1 ; продолжаем если ненулевой слот -; ВОТ ТУТ МОЖНО ВЛУПИТЬ ПРОЦЕДУРУ ДЛЯ ПОДСТАНОВКИ СТРАНИЦЫ В SLOT0 И -; ПЕРЕХОД ПО ПРЕРЫВАНИЮ В ОБРАБОТЧИК ПОЛЬЗОВАТЕЛЯ ЧЕРЕЗ процедуру на стэк, например - SCF - RET -JPHL: JP (HL) +; .L1: IN B,(C) +; PUSH BC +; OUT (C),A +; CALL .JPHL +; POP BC +; OUT (C),B +; RET +; ; проверка на нулевой слот +; .L2: BIT 6,H +; LD C,SLOT1 +; JR NZ,.L1 ; продолжаем если ненулевой слот +; ; ВОТ ТУТ МОЖНО ВЛУПИТЬ ПРОЦЕДУРУ ДЛЯ ПОДСТАНОВКИ СТРАНИЦЫ В SLOT0 И +; ; ПЕРЕХОД ПО ПРЕРЫВАНИЮ В ОБРАБОТЧИК ПОЛЬЗОВАТЕЛЯ ЧЕРЕЗ процедуру на стэк, например + + +; IF TEST_INT +; LD HL,-.stackDepth - .switchProcedure.size + .patch+2 +; ADD HL,SP +; PUSH HL + +; LD HL,-.stackDepth - .switchProcedure.size ; memory stack use! +; ADD HL,SP ; stack +; PUSH HL ; адрес программы .readProcedure + +; LD DE,.switchProcedure ; перенести программу на стек +; EX DE,HL +; LD BC,.switchProcedure.size +; LDIR +; RET + +; ; процедура, переносимая на стек для вызова прерывания пользователя из SLOT0 +; ; осторожнее с PUSH, если надо много, то увеличивай .stackDepth +; .switchProcedure: +; DEC DE +; POP HL +; LD (HL),E +; INC HL +; LD (HL),D + + +; LD C,SLOT0 +; IN B,(C) +; PUSH BC +; OUT (C),A + +; XOR A +; OUT (SYS_PORT.RAM),A +; .patch EQU $+1-.switchProcedure +; CALL .JPHL + +; DI + +; XOR A +; OUT (SYS_PORT.ROM),A + +; POP BC +; OUT (C),B + +; RET +; .JPHL: JP (HL) +; .stackDepth EQU 32 ; расстояние от конца процедуры до вершины стека. +; .switchProcedure.size EQU $-.switchProcedure +; ELSE + +; SCF +; RET +; .JPHL: JP (HL) +; ENDIF ;--------------------------------------- +/* + + + +*/ + +; +; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ [___FOR ZX-MODE___] _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ; + +; +;----------------------------[ FOR ZX-MODE ]----------------------------; +;!HARDCODE на этот адрес #С0 прыгает в vROM Basic-48 по адресу #3CF0 +; можно попробовать переделать этот адрес там + _mInfoBLOCK #C0-$,#FF +; Вход через USR 15600 +RET_FROM_BIOS_TO_BASIC48: + CALL CH_2 + CALL COMAND_LINE ; ВЫПОЛНЕНИЕ КОМАНДЫ, ЕСЛИ ЕСТЬ + ; Вход без команды + JP _SW_ROM_1 ; ВОЗВРАТ В << MAIN MENU >> + INCLUDE 'ZX/ZX_FUNC.ASM' + INCLUDE 'ZX/ZX_MENU.ASM' +;-----------------------------------------------------------------------; +; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ; +; @@ -90,58 +167,193 @@ JPHL: JP (HL) BLOCK_Setup EQU $ ; - IF PACKED_MAIN - BLOCK ROM_MAP.SETUP-$,#FF + IF PACKED_MAIN + BLOCK ROM_MAP.SETUP-$,#FF - DISP COMPILE_ADDR.SETUP + DISP COMPILE_ADDR.SETUP ; Depacker version SETUP_MAIN: - LD HL,DEPACKER.UnpackedEXECaddr; точка входа в распакованном коде - PUSH HL - LD DE,DEPACKER.WorkAddr ; адрес процедуры депакера - PUSH DE + LD HL,DEPACKER.UnpackedEXECaddr; точка входа в распакованном коде + PUSH HL + LD DE,DEPACKER.WorkAddr ; адрес процедуры депакера + PUSH DE - LD HL,DEPACKER.Addr - LD BC,DEPACKER.Length - LDIR + LD HL,DEPACKER.Addr + LD BC,DEPACKER.Length + LDIR - LD HL,DEPACKER.PackedMAIN ; где архив - LD DE,DEPACKER.UnpackAddr ; куда распаковывать - RET + LD HL,DEPACKER.PackedMAIN ; где архив + LD DE,DEPACKER.UnpackAddr ; куда распаковывать + RET -.Depacker EQU $ - ENT +.Depacker EQU $ + ENT ;-----------------[v] DEPACK_DATA: - DISP DEPACKER.WorkAddr - MODULE UnPacker - INCLUDE 'src/bios/ROM/SETUP/DEHRUST.asm' ; !TODO сделать на LUA автовыбор декомпрессора и компрессора -PackedMAIN: INCBIN 'Build/Bin/temp/MAIN.PAK' - ENDMODULE - ENT + DISP DEPACKER.WorkAddr + MODULE UnPacker + INCLUDE 'src/bios/ROM/SETUP/DEHRUST.asm' ; !TODO сделать на LUA автовыбор декомпрессора и компрессора +PackedMAIN: INCBIN 'Build/Bin/temp/MAIN.PAK' + ENDMODULE + ENT DEPACK_DATA.length EQU $-DEPACK_DATA ;-----------------[^] - ELSE - DISP COMPILE_ADDR.SETUP - ShowInfo 'Setup block DISP start', 1 ; !!!!! test -SETUP_MAIN: INCLUDE 'src/bios/ROM/SETUP/Main.asm' - ShowInfo 'Setup block DISP end', 1 ; !!!!! test - ENT - ENDIF - + ELSE + DISP COMPILE_ADDR.SETUP + ShowInfo 'Setup block DISP start', 1 ; !!!!! test +SETUP_MAIN: INCLUDE 'src/bios/ROM/SETUP/Main.asm' +SETUP_MAIN.Size EQU $-SETUP_MAIN + ShowInfo 'Setup block DISP end', 1 ; !!!!! test + ENT + ENDIF + ASSERT ($ + Setup_Starter.Size) < (STACK - STACK.Size), "WARNING: Stack area overlaps code..." ShowInfo 'Setup block of ROM end', 0 ; !!!!! test BLOCK_Setup.Length EQU $-BLOCK_Setup + + ;--------------------------------------- +; + + + + + +; +; !FIXIT сделать эти фиксированные адреса отдельным файлом и с IF/ELSE и подключать их потом куда надо. +;----------------------------------------------------------------------; +; BLOCK #3CC0-$,255 + ; no-magics! +;MAGIC_1: ; ЗАГЛУШКА ДЛЯ MAGIC +; PUSH AF +; LD A,ROM.EXT +; OUT (SYS_PORT.OFF),A +; POP AF +; JP MAGIC_1 +;MAGIC_3: +; PUSH AF +; LD A,ROM.EXT +; OUT (SYS_PORT.OFF),A +; POP AF +; RETN +;MAGIC_2: +;; CALL MG_BEGIN +; JR MAGIC_3 + +;************************* + _mInfoBLOCK #3CE0-$,#FF ;!TEST 0 +_SW_ROM_1 EQU SW_ROM_1 + LD HL,#259F ;!HARDCODE Show Main Menu in BASIC-128 + PUSH HL + LD HL,#5B00 ;!HARDCODE + LD A,(HL) + CP #F5 ; #F5 - опкод 'PUSH AF'. Проверяется в #5B00 + JR Z,_JP_HL_48 ; ВОЗВРАТ К МЕНЮ BASIC128 + POP HL + JR _SW_ROM_1 ; ПРОСТОЙ ВОЗВРАТ +;************************* + + _mInfoBLOCK #3CF0-$,#FF ;!TEST 0 +;JMP_48: +; LD HL,00h +; JR _JP_HL_48 +; +; NOP +; NOP +; NOP + +;*************************************** + _mInfoBLOCK #3CF8-$,#FF ;!TEST 0 + ; no basic-48! +_JP_HL_48 EQU JP_HL_48 + PUSH HL +_SW_ROM EQU SW_ROM + PUSH AF + LD A,ROM.BIOS + OUT (SYS_PORT.RAM),A + POP AF + RET +;*************************************** +;----------------------------------------------------------------------; +; + +;!TODO спектрумовские утилиты +;----------------------------------------------------------------------; + ; _mInfoBLOCK #3CFA-$,#FF + ; LD A,0 ;!HARDCODE + ; OUT (SYS_PORT.OFF),A + ; POP AF +;----------------------------------------------------------------------; +; + + +; +;----------------------------------------------------------------------; + _mInfoBLOCK #3D00-$,#FF +;DOS_ON: + NOP + RET +;*************************************** + +;*************************************** +; BLOCK #3D02-$,FF +; !TODO можно оприходовать тут 17 байтов +; +;*************************************** + +;*************************************** + _mInfoBLOCK #3D13-$,#FF + NOP + CALL ToBIOS_FromEXT + JP DOS_OFF +;*************************************** + +;*************************************** +; BLOCK #3D17-$,FF +; !TODO можно оприходовать тут 233 байта +; +;*************************************** + +;*************************************** + _mInfoBLOCK #3E00-$,#FF +;DOS_OFF: + PUSH AF + LD A,R + DI + PUSH AF + PUSH BC + ; + LD BC,(#5BFF) ; !HARDCODE + LD A,#C9 ; Opcode RET + LD (#5BFF),A ; !HARDCODE + CALL #5BFF ; !HARDCODE + LD (#5BFF),BC ; !HARDCODE + ; + POP BC + POP AF + JP PO,.no_EI + EI +.no_EI: POP AF + RET +;*************************************** ;*************************************** +; BLOCK #3E16-$,FF +; !TODO можно оприходовать тут 10 байтов +; +;*************************************** +; + + + +; +;--------------------------------------- ; _mInfoBLOCK #3FC6-$,#FF -;!FIXIT переделать ПЗУ трдоса и спектрумов под правильный вызов функций биоса (а не вместо функций 4x функции 0x) ; или можно добавить функции ; TRDOS_HD_CMD: ; ; LD A,C @@ -149,58 +361,58 @@ BLOCK_Setup.Length EQU $-BLOCK_Setup ; ; LD C,A ; POP AF ; SET 6,C -; CALL ToBIOS_FromEXT +; RST_to_BIOS ; JR RET_TO_TRDOS -;*************************************** +;--------------------------------------- ; -;---------------[SET BIOS]--------------- - _mInfoBLOCK ToBIOS_FromEXT-$,#FF ; #3FD0 -; call BIOS from EXTENSION -;RST18h: +;--------------[GOTO BIOS]-------------- + _mInfoBLOCK #3FD0-$,#FF +;ToBIOS_FromEXT: call BIOS from EXTENSION PUSH AF - LD A,ROM.BIOS ; set exp-rom to slot0 + LD A,ROM.BIOS ; set BIOS to slot0 OUT (SYS_PORT.ROM),A POP AF RET ;--------------------------------------- - ;--------[ From TR-DOS to HDD part2]-------- _mInfoBLOCK #3FD8-$,#FF TRDOS_HD_CMD: POP AF - SET 6,C ;!FIXIT переделать ПЗУ трдоса и спектрумов под правильный вызов функций биоса (а не вместо функций 4x функции 0x) - CALL ToBIOS_FromEXT + SET 6,C + RST_to_BIOS JR RET_TO_TRDOS ;--------------------------------------- -;!FIXIT остатки от спектрума +;!FIXIT остатки от тестов Ивана со звуковой картой ;-------------[SND_TEST_RET]------------- _mInfoBLOCK #3FE0-$,#FF -SND_TEST_RET: - LD A,ROM.BIOS - OUT (SYS_PORT.RAM),A -; JP SOUND_TEST - JP #0000 +; SND_TEST_RET: +; LD A,ROM.BIOS +; OUT (SYS_PORT.RAM),A +; ;JP SOUND_TEST +; JP #0000 ;--------------------------------------- -;------------[HDD_5x portal]------------ -; точка входа/выхода для функций 5х из BIOS +;------------[Portal to EXT]------------ +; точка входа/выхода для функций из BIOS _mInfoBLOCK #3FE8-$,#FF -;RET_TO_EXP: - ; PUSH AF - ; LD A,ROM.BIOS - ; OUT (SYS_PORT.ROM),A +RET_TO_BIOS: ;RET_TO_EXP: + PUSH AF + LD A,ROM.BIOS + OUT (SYS_PORT.ROM),A ; from BIOS EXTENSION_FNs + POP AF + RET ; JP HDD_FN_5x ;--------------------------------------- -;!FIXIT эта точка входа очень странная из страницы в страницу прыгает -;---------[ From TR-DOS to HDD ]-------- - _mInfoBLOCK #3FF0-$,255 +;!FIXIT Можно поправить номера функций при вызовах из TR-DOS и прыгать сразу в BIOS +;-------[ From TR-DOS to API 4x ]------- + _mInfoBLOCK #3FF0-$,#FF RET_TO_TRDOS: PUSH AF DI @@ -212,13 +424,22 @@ RET_TO_TRDOS: ;-----[???????????????????????????]----- - _mInfoBLOCK #3FF8-$,255 -A3FF8: PUSH AF - LD A,ROM.BIOS - OUT (SYS_PORT.RAM),A -; !FIXIT может убрать заглушку и сделать, чтоб переключалось на BIOS и дальше как в EXP_FNS_RET ? -; или своего чего-нибудь добавить. - JP #0000 + _mInfoBLOCK #3FF8-$,#FF + ; PUSH AF + ; LD A,ROM.BIOS + ; OUT (SYS_PORT.RAM),A + ; JP #0000 ;--------------------------------------- - _mInfoBLOCK #4000-$,255 + _mInfoBLOCK #4000-$,#FF ;======================================= + + IFNDEF PREBUILD + DISPLAY ' -------------------[Main.asm]-------------------' + DISPLAY 'End code address: ',/A,MAIN_END_CODE_ADDRESS + DISPLAY 'Code size: ',/A,MAIN_END_CODE_ADDRESS + 1 - COMPILE_ADDR.MAIN + DISPLAY 'End buffers address: ',/A,memBUFFER.End - 1 + DISPLAY 'Free memory: ',/A,#C000 - (memBUFFER.End-1) - STACK.Size + DISPLAY 'Unused bytes before INT_POINTER: ',/A,INT_POINTER-before_intPointer + ENDIF +; ENDMODULE ;ROM_PART +; \ No newline at end of file diff --git a/src/bios/rom/SETUP/AUTOIDE.asm b/src/bios/rom/SETUP/AUTOIDE.asm index 0fc571d..ed6836b 100644 --- a/src/bios/rom/SETUP/AUTOIDE.asm +++ b/src/bios/rom/SETUP/AUTOIDE.asm @@ -1,400 +1,1128 @@ - -; -;R01 01.08.2001 FIX BUG INT "SELECT_IDE" -;R00 24.07.2001 ADD SECONDARY IDE -;INITIAL NEW VERSION (2.48) 24.07.2001 -;======================================================== - -; MODULE AUTOIDE -/* -;Write -HDW_3F7 EQU #4155 ;3F7H Command -HDW_3F6 EQU #4154 ;3F6H Device Control -;Read -HDR_3F7 EQU #4055 ;3F7H Drive Address -HDR_3F6 EQU #4054 ;3F6H Alt. Status - -;Write -IDE.Write.Command EQU #4153 ; #1F7 Command -HDW_DRV EQU #4152 ; #1F6 Drive Control - -HDW_CLH EQU #0155 ; #1F5 Cylinder High -HDW_CLL EQU #0154 ; #1F4 Cylinder Low -HDW_SEC EQU #0153 ; #1F3 Sector -HDW_CNT EQU #0152 ; #1F2 Counter -HDW_ERR EQU #0151 ; #1F1 Error -HDW_DAT EQU #0150 ; #1F0 Data - -;Read -HDR_CTL EQU #4053 ; #1F7 Status (Control) -HDR_DRV EQU #4052 ; #1F6 Drive Control - -HDR_CLH EQU #0055 ; #1F5 Cylinder High -HDR_CLL EQU #0054 ; #1F4 Cylinder Low -HDR_SEC EQU #0053 ; #1F3 Sector -HDR_CNT EQU #0052 ; #1F2 Counter -HDR_ERR EQU #0051 ; #1F1 Error -HDR_DAT EQU #0050 ; #1F0 Data - -;Bits for HDR_CTL -;---[] -BSY EQU 7 -RDY EQU 6 -DRQ EQU 3 -ERR EQU 0 -;---[] - -HDD EQU 1 -CDROM EQU 2 - - -;EQU FOR IY+ -;---[] -DRVHD_H EQU 0 -SC_PT_H EQU 1 -IDE.HDD_INIT_TABLE.HeadsNumber EQU 2 -CYL_L_H EQU 3 -CYL_H_H EQU 4 -SPCLL_H EQU 5 -SPCLH_H EQU 6 -DTYPE_H EQU 7 -;---[] -;-------[ ;!!!!! hardcoded table]------- -IDE0 EQU #C1C0 -IDE1 EQU #C1C8 -IDE2 EQU #C1D0 -IDE3 EQU #C1D8 -;--------------------------------------- -*/ - -;IDE0 DB #FF ;DRIVE/HEAD REGISTER ;00 -; DB #FF ;SECTORS PER TRACK ;01 -; DB #FF ;HEADS ;02 -; DB #FF ;CYLINDERS LOW ;03 -; DB #FF ;CYLINDERS HIGH ;04 -; DB #FF ;SECTOR PER CYLINDER LOW ;05 -; DB #FF ;SECTOR PER CYLINDER HIGH ;06 -; DB #FF ;DEVICE TYPE ;07 - -;IDE1 DB #FF ;DRIVE/HEAD REGISTER ;00 -; DB #FF ;SECTORS PER TRACK ;01 -; DB #FF ;HEADS ;02 -; DB #FF ;CYLINDERS LOW ;03 -; DB #FF ;CYLINDERS HIGH ;04 -; DB #FF ;SECTOR PER CYLINDER LOW ;05 -; DB #FF ;SECTOR PER CYLINDER HIGH ;06 -; DB #FF ;DEVICE TYPE ;07 - -IDE__CD: - CALL SELECT_IDE -;MASTER -CDAUTO: - LD A,IDE.Device.CDROM - LD (IDEDEV),A - LD A,#FF - JP CDMASTR - -SELECT_IDE: - AND A ;%00000011 - LD D,#A0 - JR Z,IAUTO0 - DEC A - LD D,#B0 - JR Z,IAUTO0 - DEC A - LD D,#A0 ;R00 - JR Z,IAUTO1 ;R00 - DEC A ;R00 - LD D,#B0 ;R00 -IAUTO1: - LD A,#01 ;R00 ;SELECT SECONDARY - OUT (#BC),A ;R00 - LD A,1 - JR IAUTO ;R00 - -IAUTO0: - LD A,#21 ;R00 ;SELECT PRIMARY - OUT (#BC),A ;R00 - LD A,0 -IAUTO: - LD (ICHANEL),A - LD BC,IDE.Write.DriveCtrl ;R01 - OUT (C),D ;R01 - RET - -IDEAUTO: - CALL SELECT_IDE -;MASTER - LD A,#FF - LD (IDEDEV),A -CDMASTR: - LD (SKIP),A - LD BC,IDE.Write.DriveCtrl - OUT (C),D - - LD BC,IDE.Read.Status - IN A,(C) - AND #80 - LD HL,280 - JR Z,NO_BUSY - LD HL,1550 - EI -CLRBUSY: - HALT - DEC HL - LD A,H - OR L - JP Z,ABSENT - CALL SKIPKEY - JP C,ABSENT - LD BC,IDE.Read.Status - IN A,(C) - AND #80 - JR NZ,CLRBUSY - -NO_BUSY: - LD E,#05 - LD BC,IDE.Write.Counter - OUT (C),E - LD BC,#0010 - DJNZ $ ;!HARDCODE - DEC C - JR NZ,$-3 ;!HARDCODE - LD BC,IDE.Read.Counter - IN A,(C) - CP E - JP NZ,ABSENT - - LD A,(IDEDEV) - CP IDE.Device.CDROM - JP Z,NOHDD - - LD E,#00 ;NOP - LD BC,IDE.Write.Command - OUT (C),E - -WXREADY: - HALT - DEC HL - LD A,H - OR L - JP Z,ABSENT - CALL SKIPKEY - JP C,ABSENT - LD BC,IDE.Read.Status - IN A,(C) - AND #C0 - CP #40 - JR NZ,WXREADY - -; LD A,#90 ; -; CALL IDE_CMD - - LD A,IDE.Device.HDD - LD (IDEDEV),A - LD E,#EC ;IDENTIFY ATA - LD BC,IDE.Write.Command - OUT (C),E - LD B,#00 - DJNZ $ ;!HARDCODE - LD HL,(WAITSML) - LD DE,#0101 - LD BC,IDE.Read.Status - CALL WAIT_PRT - JP NC,NOHDD - -GETPARM: - LD HL,(WAITIDE) - LD DE,#0808 - LD BC,IDE.Read.Status - CALL WAIT_PRT - JP C,ABSENT - LD BC,IDE.Read.Data - LD HL,TEMP - INIR - INIR - CALL IDESPEC - AND A - RET - -NOHDD: LD A,IDE.Device.CDROM - LD (IDEDEV),A - LD E,#A1 ;IDENTIFY ATAPI - LD BC,IDE.Write.Command - OUT (C),E - LD B,#00 - DJNZ $ - LD HL,(WAITSML) - LD DE,#0101 - LD BC,IDE.Read.Status - CALL WAIT_PRT - JP C,GETPARM -ABSENT: - SCF - RET - -IDESPEC: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,(IDEDEV) - LD (IY+IDE.HDD_INIT_TABLE.DriveType),A - CP IDE.Device.CDROM - JP Z,FOR_CDR - LD BC,IDE.Read.Control - IN A,(C) - AND #F0 - LD B,A - LD A,(TEMP+#06) ; !TODO сделать через структуру. HEADS PER TRACK - LD (IY+IDE.HDD_INIT_TABLE.HeadsNumber),A - DEC A - AND #0F - OR B - LD B,A - LD A,(TEMP+#63) ; !TODO сделать через структуру. LBA/NON-LBA bit 1 (FROM ZERO!) - BIT 1,A - JR Z,NONLBA - SET 6,B -NONLBA: - LD A,B - LD BC,IDE.Write.DriveCtrl - OUT (C),A - AND #F0 - LD HL,ICHANEL - OR (HL) - LD (IY+IDE.HDD_INIT_TABLE.Chanel),A - LD HL,(TEMP+#02) ; !TODO сделать через структуру. CYLINDERS - LD (IY+IDE.HDD_INIT_TABLE.CylinderNumberLow),L - LD (IY+IDE.HDD_INIT_TABLE.CylinderNumberHigh),H - LD A,(TEMP+#0C) ; !TODO сделать через структуру. SECTOR PER TRACK - LD (IY+IDE.HDD_INIT_TABLE.SectorsPerTrack),A - LD BC,IDE.Write.Counter - OUT (C),A - LD A,#91 ; - CALL IDE_CMD -; RET C - LD C,(IY+IDE.HDD_INIT_TABLE.SectorsPerTrack) ; Sector per track - LD B,0 - LD A,(IY+IDE.HDD_INIT_TABLE.HeadsNumber) ; Head per HDD - LD HL,0 -HDDINI3: - ADD HL,BC - DEC A - JR NZ,HDDINI3 - LD (IY+IDE.HDD_INIT_TABLE.SectorsPerCylinderLow),L - LD (IY+IDE.HDD_INIT_TABLE.SectorsPerCylinderHigh),H -NOSPEC: - EX AF,AF' - OUT (SLOT3),A - AND A - RET - -FOR_CDR: - LD BC,IDE.Read.Control - IN A,(C) - AND #F0 - LD HL,ICHANEL - OR (HL) - LD (IY+IDE.HDD_INIT_TABLE.Chanel),A - JR NOSPEC - -IDE_CMD: - PUSH AF - LD HL,(WAITIDE) - LD DE,#C040 - LD BC,IDE.Read.Status - CALL WAIT_PRT - POP DE - RET C - LD BC,IDE.Write.Command - OUT (C),D - LD HL,(WAITIDE) - LD DE,#C040 - LD BC,IDE.Read.Status - JP WAIT_PRT - -WAITHDD: - EI - LD HL,1533 -WTREADY: - HALT - LD BC,IDE.Read.Status - IN A,(C) - AND #C0 - CP #40 - RET Z - DEC HL - LD A,H - OR L - JR NZ,WTREADY - SCF - RET - -;WAITHDD DEC L -; RET NZ -; DEC H -; RET NZ -; DEC E -; RET NZ -; SCF -; RET - -; E - Second * 10 - -;PAUSE LD HL,#0000 -;PAUSE1 DEC L -; JR NZ,PAUSE1 -; DEC H -; JR NZ,PAUSE1 -; DEC E -; JR NZ,PAUSE1 -; RET - -; D - MASK -; E - PATTERN -; BC - PORT -WAIT_PRT: - IN A,(C) - AND D - CP E - JR NZ,.P2 - AND A - RET -.P2: DEC HL - CALL SKIPKEY - RET C - LD A,L - OR H - JP NZ,WAIT_PRT -.error: SCF - RET - -SKIPKEY: - EXX - CALL SCANKEY - EXX - SCF - CCF - RET Z - EXX - LD HL,#3E00 ;!HARDCODE - AND A - SBC HL,DE - EXX - SCF - CCF - RET NZ - LD A,0 - LD (SKIP),A - SCF - RET - -WAITIDE: DW #0000 -WAITSML: DW #0400 -SKIP: DB #FF -IDEDEV: DB #FF -ICHANEL: DB #00 - -; ENDMODULE +;[BEGIN] +;//MODULE: AUTOIDE +;//CREATE: 27-07-2001 AUTHOR: Denis Parinov +;----------------------------------------------------------------------- +;Rev Date Name Description +;----------------------------------------------------------------------- +;R02 17.08.2023 BAO New AUTODETECT ATA/ATAPI procedure +;R01 01.08.2001 DNS FIX BUG INT "SELECT_IDE" +;R00 24.07.2001 DNS ADD SECONDARY IDE +; 24.07.2001 DNS INITIAL NEW VERSION 2.48 +;======================================================================= + +; MODULE AUTOIDE +/* +;Write +HDW_3F7 EQU #4155 ;3F7H Command +HDW_3F6 EQU #4154 ;3F6H Device Control +;Read +HDR_3F7 EQU #4055 ;3F7H Drive Address +HDR_3F6 EQU #4054 ;3F6H Alt. Status + +;Write +IDE.Write.Command EQU #4153 ; #1F7 Command +HDW_DRV EQU #4152 ; #1F6 Drive Control + +HDW_CLH EQU #0155 ; #1F5 Cylinder High +HDW_CLL EQU #0154 ; #1F4 Cylinder Low +HDW_SEC EQU #0153 ; #1F3 Sector +HDW_CNT EQU #0152 ; #1F2 Counter +HDW_ERR EQU #0151 ; #1F1 Error +HDW_DAT EQU #0150 ; #1F0 Data + +;Read +HDR_CTL EQU #4053 ; #1F7 Status (Control) +HDR_DRV EQU #4052 ; #1F6 Drive Control + +HDR_CLH EQU #0055 ; #1F5 Cylinder High +HDR_CLL EQU #0054 ; #1F4 Cylinder Low +HDR_SEC EQU #0053 ; #1F3 Sector +HDR_CNT EQU #0052 ; #1F2 Counter +HDR_ERR EQU #0051 ; #1F1 Error +HDR_DAT EQU #0050 ; #1F0 Data + +;Bits for HDR_CTL +;---[] +BSY EQU 7 +RDY EQU 6 +DRQ EQU 3 +ERR EQU 0 +;---[] + +HDD EQU 1 +CDROM EQU 2 + + +;EQU FOR IY+ +;---[] +DRVHD_H EQU 0 +SC_PT_H EQU 1 +IDE.HDD_INIT_TABLE.HeadsNumber EQU 2 +CYL_L_H EQU 3 +CYL_H_H EQU 4 +SPCLL_H EQU 5 +SPCLH_H EQU 6 +DTYPE_H EQU 7 +;---[] +;-------[ ;!!!!! hardcoded table]------- +IDE0 EQU #C1C0 +IDE1 EQU #C1C8 +IDE2 EQU #C1D0 +IDE3 EQU #C1D8 +;--------------------------------------- +*/ + +;IDE0 DB #FF ;DRIVE/HEAD REGISTER ;00 +; DB #FF ;SECTORS PER TRACK ;01 +; DB #FF ;HEADS ;02 +; DB #FF ;CYLINDERS LOW ;03 +; DB #FF ;CYLINDERS HIGH ;04 +; DB #FF ;SECTOR PER CYLINDER LOW ;05 +; DB #FF ;SECTOR PER CYLINDER HIGH ;06 +; DB #FF ;DEVICE TYPE ;07 + +;IDE1 DB #FF ;DRIVE/HEAD REGISTER ;00 +; DB #FF ;SECTORS PER TRACK ;01 +; DB #FF ;HEADS ;02 +; DB #FF ;CYLINDERS LOW ;03 +; DB #FF ;CYLINDERS HIGH ;04 +; DB #FF ;SECTOR PER CYLINDER LOW ;05 +; DB #FF ;SECTOR PER CYLINDER HIGH ;06 +; DB #FF ;DEVICE TYPE ;07 + + MODULE CONFIGURE_IDE_DRIVES + + MODULE PAUSES +HALT: +.Time_2s EQU 100 +.SMALL EQU 200 ; 04 сек +.MEDIUM EQU 400 ; 08 сек +.BIG EQU 1550 ; 31 сек +WAIT: +.IDE EQU #0000 +.SMALL EQU #0200 +.ERROR EQU #0400 + ENDMODULE + +; WAIT_IDE EQU #0000 +; WAIT_SML EQU #1000 +; WAIT_ERROR EQU #0400 + +; M_CYLL EQU #12 +; M_CYLH EQU #13 +; M_HEAD EQU #14 +; M_SECT EQU #15 + +; S_CYLL EQU #16 +; S_CYLH EQU #17 +; S_HEAD EQU #18 +; S_SECT EQU #19 + +; SM_CYLL EQU #37 +; SM_CYLH EQU #38 +; SM_HEAD EQU #39 +; SM_SECT EQU #3A + +; SS_CYLL EQU #3B +; SS_CYLH EQU #3C +; SS_HEAD EQU #3D +; SS_SECT EQU #3E + + MACRO PAUSE_DJNZ num + IF num<256 + LD B,num +.loop: DJNZ .loop + ELSE + ASSERT 0, "WRONG PAUSE NUMBER!!!" + ENDIF + ENDM + +/////////////////////////////////////////////////////////////////////[v] +START: ; reset all + LD A,IDE.Chanel.Primary + OUT (IDE.Chanel.Set),A + CALL RESET_IDE_CHANEL + LD A,IDE.Chanel.Secondary ;SELECT SECONDARY + OUT (IDE.Chanel.Set),A + CALL RESET_IDE_CHANEL + ; + ; + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD HL,IDE.INIT_TBL_IDE0 + LD BC,256*(IDE.HDD_INIT_TABLE * 4) + #FF ;R02 +;CLEAR HDD VARIABLE +.FILLIDE: + LD (HL),C + INC HL + DJNZ .FILLIDE + EX AF,AF' + OUT (SLOT3),A + + LD IY,IDE.INIT_TBL_IDE0 + XOR A + CALL STEP1_GETCMOS + + LD IY,IDE.INIT_TBL_IDE1 + LD A,#01 + CALL STEP1_GETCMOS + + LD IY,IDE.INIT_TBL_IDE2 + LD A,#02 + CALL STEP1_GETCMOS + + LD IY,IDE.INIT_TBL_IDE3 + LD A,#03 + CALL STEP1_GETCMOS + + ;[x] save hdd parameters to cmos for "setup" in settings + CALL WRITING + ; + JP ScreenPOS.CRLF + ;RET +/////////////////////////////////////////////////////////////////////[^] + +/////////////////////////////////////////////////////////////////////[v] +RESET_IDE_CHANEL: + LD BC,IDE.Write.DeviceControl + LD A,IDE.DeviceControlByte.setReset + OUT (C),A + DJNZ $ + LD B,high IDE.Write.DeviceControl + LD A,IDE.DeviceControlByte.resReset + OUT (C),A + RET +/////////////////////////////////////////////////////////////////////[^] + +/////////////////////////////////////////////////////////////////////[v] +AUTODETECT: LD A,L ;DETECT MESSAGE + CALL POSTMSG + CALL ScreenPOS.SUBNAME + LD A,(MasterSlave) + CALL AUTODETECTING +.IDEJUMPBACK: CALL NC,PRINT_IDE_MODEL + LD A,(SKIP) + INC A + LD A,msgStrings.ideNone + JR Z,.NOSKIPKEY + LD A,msgStrings.ideSkiped +.NOSKIPKEY: CALL C,POSTMSG + CALL ScreenPOS.CRLF + RET +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +STEP1_GETCMOS: + LD (MasterSlave),A + LD H,A ;SAVE DRIVE NUMBER + CALL SELECT_IDE + LD A,IDE.Device.NONE + LD (IDEDEV),A + LD (SKIP),A + LD A,H + ; + AND A + LD BC,CMOS_CELL.DrivesSetup_1.Mask.PriIDEmaster ;#3011 + LD L,msgStrings.detectIdePrMA + JR Z,.choose + ; + DEC A + LD BC,CMOS_CELL.DrivesSetup_1.Mask.PriIDEslave ;#C011 + LD L,msgStrings.detectIdePrSL + JR Z,.choose + ; + DEC A + LD BC,CMOS_CELL.DrivesSetup_2.Mask.SecIDEmaster + LD L,msgStrings.detectIdeSecMA + JR Z,.choose + ; + ;DEC A + LD BC,CMOS_CELL.DrivesSetup_2.Mask.SecIDEslave + LD L,msgStrings.detectIdeSecSL + ;JR Z,.choose + ;SCF + ;RET + ;0 - AUTODETECT + ;1 - GETTING FROM SETUP + ;2 - CD-ROM (ATAPI device) + ;3 - DISABLED +.choose: + EI + ; + CALL GET_CMOS_VALUE + OR A + JR Z,AUTODETECT ;AUTO DETECT + ; + DEC A + JR Z,SETUP_FROM_CMOS ;Get from CMOS (SETUP) + ; + DEC A + RET NZ ;DON'T CHECK THIS DEVICE + ;JR Z,IT_IS_ATAPI ;CD-ROM +/////////////////////////////////////////////////////////////////////[^] +/////////////////////////////////////////////////////////////////////[v] +IT_IS_ATAPI: + LD A,L ;DETECT MESSAGE + CALL POSTMSG + CALL ScreenPOS.SUBNAME + + LD HL,PAUSES.HALT.BIG + CALL BITS_WAITS.Clear_BUSY + JR C,AUTODETECTING.IDE_ABSENT + + CALL AUTODETECTING.Its_ATAPI + JP AUTODETECT.IDEJUMPBACK +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +SEND_NOP: XOR A + LD BC,IDE.Write.Features + OUT (C),A + LD BC,IDE.Write.Command + LD E,IDE.CMD.ATA.Nop + OUT (C),E + PAUSE_DJNZ 32 + RET +/////////////////////////////////////////////////////////////////////[^] + +/////////////////////////////////////////////////////////////////////[v] +AUTODETECTING: CALL SEND_NOP + ; + CALL DETECTORS.CheckChanel + JR C,.IDE_ABSENT + + CALL Bug31SecCheck + JR NC,.next + + LD HL,PAUSES.HALT.BIG + CALL BITS_WAITS.Clear_BUSY + JR C,.IDE_ABSENT + +.next: CALL DETECTORS.Counter + JR C,.IDE_ABSENT + + CALL DETECTORS.NOP_Check + JR C,.IDE_ABSENT + + ; CALL DISABLE_8bit ; DISABLE 8 bit data transfer + + CALL DETECTORS.IdentDevCheck + JR C,.IDE_ABSENT + JR Z,.Its_ATA + ; enter point for ATAPI in setup +.Its_ATAPI: CALL DETECTORS.IdentPDevChk + JR C,.IDE_ABSENT + LD A,IDE.Device.ATAPI + JR .get + +.Its_ATA: LD A,IDE.Device.HDD +.get: LD (IDEDEV),A + CALL GETPARAM + RET NC + ;JR C,.IDE_ABSENT + ;CALL DisableWriteCache + ;CALL DisableStandBy + ;AND A + ;RET +.IDE_ABSENT: LD A,IDE.Device.NONE + LD (IDEDEV),A + ;LD A,IDE.CMD.ATA.Nop + ;LD BC,IDE.Write.Command + ;OUT (C),A + ;; + ; ;DEC B + ; PAUSE_DJNZ 0 + ; LD BC,IDE.Read.Status + ;; + ;IN A,(C) ; IDE.Read.Status + SCF + RET +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +SETUP_FROM_CMOS: + LD A,H + LD IX,PRIM_MASTER_CMOS_TABLE + OR A + JR Z,.step1 + ; + LD IX,PRIM_SLAVE_CMOS_TABLE + DEC A + JR Z,.step1 + ; + LD IX,SEC_MASTER_CMOS_TABLE + DEC A + JR Z,.step1 + ; + LD IX,SEC_SLAVE_CMOS_TABLE +.step1: LD HL,IDENTIFY_DEVICE_BUFFER + LD DE,IDENTIFY_DEVICE_BUFFER+1 + LD BC,511 + LD (HL),0 + LDIR + ; + CALL Bug31SecCheck + JR NC,.step2 + ; + LD HL,PAUSES.HALT.BIG + CALL BITS_WAITS.Clear_BUSY + JR C,AUTODETECTING.IDE_ABSENT + ; +.step2: LD A,(IX + IDE_CMOS_TABLE.Heads) + CALL READCMS + LD (IDENTIFY_DEVICE_BUFFER.NumHeads),A + ; + LD A,(IX + IDE_CMOS_TABLE.CylindersHigh) + CALL READCMS + PUSH AF + ; + LD A,(IX + IDE_CMOS_TABLE.CylindersLow) + CALL READCMS + POP HL + LD L,A + LD (IDENTIFY_DEVICE_BUFFER.NumCylinders),HL + ; + LD A,(IX + IDE_CMOS_TABLE.Sectors) + CALL READCMS + LD (IDENTIFY_DEVICE_BUFFER.NumSectorsPerTrack),A + ; + LD A,IDE.Device.HDD + LD (IDEDEV),A + ; CALL IDESPEC + ; RET +/////////////////////////////////////////////////////////////////////[^] +/////////////////////////////////////////////////////////////////////[v] +PARSE_IdentifyDevice: + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD A,(IDEDEV) + LD (IY+IDE.HDD_INIT_TABLE.DriveType),A + CP IDE.Device.ATAPI + JR Z,.FOR_ATAPI + ; + LD BC,IDE.Read.Control + IN A,(C) + AND #F0 + LD B,A + LD A,(IDENTIFY_DEVICE_BUFFER.NumHeads) + LD (IY+IDE.HDD_INIT_TABLE.HeadsNumber),A + DEC A + AND #0F + OR B + LD B,A + LD A,(IDENTIFY_DEVICE_BUFFER.Capabilities_high) + AND %0000'0010 + JR Z,.NONLBA + ; + SET 6,B +.NONLBA: LD A,B + LD BC,IDE.Write.DeviceHead + OUT (C),A + AND #F0 ;!HARDCODE DRIVE/HEAD REGISTER PHISICAL DISK bitmask + LD HL,ICHANEL + OR (HL) + LD (IY+IDE.HDD_INIT_TABLE.DRV_Flags),A + LD HL,(IDENTIFY_DEVICE_BUFFER.NumCylinders) + LD (IY+IDE.HDD_INIT_TABLE.CylinderNumberLow),L + LD (IY+IDE.HDD_INIT_TABLE.CylinderNumberHigh),H + ; [ ] removable media + LD A,(IDENTIFY_DEVICE_BUFFER.GeneralConfiguration) + RLCA + AND %0000'0001 + LD (IY+IDE.HDD_INIT_TABLE.MediaParameters),A + ; + LD A,(IDENTIFY_DEVICE_BUFFER.NumSectorsPerTrack) + LD (IY+IDE.HDD_INIT_TABLE.SectorsPerTrack),A + LD B,high IDE.Write.Counter + OUT (C),A + LD A,IDE.CMD.ATA.InitializeDeviceParameters + CALL IDE_CMD + LD C,(IY+IDE.HDD_INIT_TABLE.SectorsPerTrack) ; Sector per track + LD B,0 + LD H,B + LD L,B + LD A,(IY+IDE.HDD_INIT_TABLE.HeadsNumber) ; Head per HDD + ; +.loop: ADD HL,BC + DEC A + JR NZ,.loop + ; + LD (IY+IDE.HDD_INIT_TABLE.SectorsPerCylinderLow),L + LD (IY+IDE.HDD_INIT_TABLE.SectorsPerCylinderHigh),H +.END: RES 1,(IY + IDE.HDD_INIT_TABLE.MediaParameters) ; [ ] removable media + ; [x] save hdd parameters to cmos for "setup" in settings +.END_2: LD A,(IY+IDE.HDD_INIT_TABLE.DRV_Flags) ; for save to cmos in GETPARM + ; + EX AF,AF' + OUT (SLOT3),A + AND A + RET + ; +.FOR_ATAPI: LD BC,IDE.Read.Control + IN A,(C) + AND #F0 + LD HL,ICHANEL + OR (HL) + LD (IY+IDE.HDD_INIT_TABLE.DRV_Flags),A + ; + LD (IY+IDE.HDD_INIT_TABLE.MediaParameters),%0000'0001 + LD B,200 ; счётчик попыток (1 попытка - 1 HALT) +.get_error_loop: + PUSH BC + ;LD HL,ATAPI_CMD_PACKET.TEST_UNIT_READY + ;CALL EXEC_PACKET_COMMAND.start + CALL EXEC_TEST_CMD + POP BC + JR NC,.s_size + ; + CP BIOS.Error.ATAPI.UnitAttention + JR Z,PARSE_IdentifyDevice.END ;!TEST ;!FIXIT ZIP bug + ; + HALT + ; + PUSH AF + CALL SKIPKEY + JR NC,.noSkipKey + ; CF=1 + LD A,#FF + LD (SKIP),A + ; LD (IY+IDE.HDD_INIT_TABLE.SectorSize),A + ; LD (IY+IDE.HDD_INIT_TABLE.SectorSize + 1),A + SET 2,(IY + IDE.HDD_INIT_TABLE.MediaParameters) ; [ ] removable media + POP AF + SCF + JR .set_sector +.noSkipKey: POP AF + ; + CP BIOS.Error.ATAPI.NotReady + JR Z,.get_error_loop + DJNZ .get_error_loop + ; + ; [ ] sector size ATAPI +.s_size: LD DE,IDENTIFY_DEVICE_BUFFER.ReservedWord224 ; просто нужен был буфер + CALL ATAPI_READ_CAPACITY_DATA + ; +.set_sector: LD HL,#FFFF + JR C,.No_Media + ; + LD HL,(IDENTIFY_DEVICE_BUFFER.ReservedWord224) ; media size high + LD (IY+IDE.HDD_INIT_TABLE.MediaSizeHigh),H + LD (IY+IDE.HDD_INIT_TABLE.MediaSizeHigh+1),L + LD HL,(IDENTIFY_DEVICE_BUFFER.ReservedWord224 + 2) ; media size low + LD (IY+IDE.HDD_INIT_TABLE.MediaSizeLow),H + LD (IY+IDE.HDD_INIT_TABLE.MediaSizeLow+1),L + LD HL,(IDENTIFY_DEVICE_BUFFER.ReservedWord224 + 6) ; sector size + ; +.No_Media: LD (IY+IDE.HDD_INIT_TABLE.SectorSize),H + LD (IY+IDE.HDD_INIT_TABLE.SectorSize + 1),L + ; + JR PARSE_IdentifyDevice.END ;!TEST ;!FIXIT ZIP bug + ; +/* +;====; ;!TEST ;!FIXIT ZIP bug +.TEST_SET: LD HL,.MODE_SENSE + LD DE,SYS_PAGE.MS_BPB ; просто нужен был буфер + LD BC,BIOS.DRV_EXTENDED.ATAPI_Custom_PCMD + CALL ATAPI_CUSTOM_CMD + JR NC,.OK_DONE + ; + LD A,COLORS.CGA.BORDER.CYAN + OUT (BorderColor),A + JR .go_exit + ; +.OK_DONE: LD A,(SYS_PAGE.MS_BPB + 2) + AND A + JR NZ,.go_exit + ; + LD (SYS_PAGE.MS_BPB + 10),A + LD HL,(SYS_PAGE.MS_BPB) + LD (.MODE_SELECT.Size),HL + LD HL,.MODE_SELECT + LD DE,SYS_PAGE.MS_BPB ; просто нужен был буфер + LD BC,BIOS.DRV_EXTENDED.ATAPI_Custom_PCMD + CALL ATAPI_CUSTOM_CMD + JR NC,.go_exit + ; + LD A,COLORS.CGA.BORDER.GREEN + OUT (BorderColor),A + ;JR .go_exit + ; +.go_exit: AND A + JP PARSE_IdentifyDevice.END + ; + ; + +.MODE_SENSE: BYTE #5A + BYTE #08 +.MODE_SENSE.Page: BYTE #08 ;bit7..6 - Page Control, bit5..0 - Page Code + BLOCK 4,0 + BYTE #02,#00 + BLOCK 3,0 + ; +.MODE_SELECT: BYTE #55 + BYTE #08 +.MODE_SELECT.Page: BYTE #08 ;bit7..6 - Page Control, bit5..0 - Page Code + BLOCK 4,0 +.MODE_SELECT.Size: BYTE #02,#00 + BLOCK 3,0 + ; +;====; ;!TEST +*/ ; +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +IDE_CMD: + PUSH AF + LD HL,PAUSES.WAIT.IDE + LD DE,256*IDE.CtrlByte.Busy + 0 + CALL BITS_WAITS.WAIT_PRT + POP HL + RET C + INC B ; LD BC,IDE.Write.Command + OUT (C),H + LD HL,PAUSES.WAIT.IDE + ;LD DE,256*IDE.CtrlByte.Busy + 0 + JR BITS_WAITS.WAIT_PRT +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +PRINT_IDE_MODEL: + LD HL,IDENTIFY_DEVICE_BUFFER.ModelNumber + LD A,(HL) + OR A + JR Z,.unknown + LD B,+(_ATA_IDENTIFY_DEVICE_DATA.MaximumBlockTransfer - _ATA_IDENTIFY_DEVICE_DATA.ModelNumber)/2 + CALL PRINT_STR_BIG_ENDIAN + AND A + RET + ; +.unknown: LD A,msgStrings.ideUnknown + CALL POSTMSG + AND A + RET +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +BITS_WAITS: + ; IN: + ; HL - Waiting delay + ; DE - MASK : PATTERN + ; OUT: + ; NC: (PORT & D)-E = 0 + ; CF: waiting delay exceeded +.WAIT_PRT: LD BC,IDE.Read.Status +.loop: IN A,(C) + AND D + CP E + RET Z + DEC HL + CALL SKIPKEY + RET C + LD A,L + OR H + JP NZ,.loop + SCF + RET + ; + ; Pause for clear BUSY and DATA REQUEST +.Clear_BUSY: LD BC,IDE.Read.Status + IN A,(C) + AND IDE.CtrlByte.Busy; + IDE.CtrlByte.DataRequest + RET Z + ; + HALT + DEC HL + LD A,H + OR L + SCF + RET Z + ; + CALL SKIPKEY + RET C + JR .Clear_BUSY +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +SELECT_IDE: AND A ;%0000'0011 + LD B,IDE.Drive.Master + JR Z,.AUTO_0 + ; + DEC A + LD B,IDE.Drive.Slave + JR Z,.AUTO_0 + ; + DEC A + ;R00 + LD B,IDE.Drive.Master + JR Z,.AUTO_1 + ; + DEC A + LD B,IDE.Drive.Slave +.AUTO_1: LD A,IDE.Chanel.Secondary ;SELECT SECONDARY + OUT (IDE.Chanel.Set),A + JP .AUTO + ; +.AUTO_0: LD A,IDE.Chanel.Primary ;SELECT PRIMARY + OUT (IDE.Chanel.Set),A + ; + XOR A +.AUTO: LD (ICHANEL),A + ;R01 + LD A,B + LD BC,IDE.Write.DeviceHead + OUT (C),A + ; + RET +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +SKIPKEY: EXX + CALL SCANKEY + EXX + ;SCF + ;CCF + RET Z + EXX + LD HL,#3E00 ;!HARDCODE + ;XOR A + SBC HL,DE + EXX + SCF + CCF + RET NZ + ;A=0 + LD (SKIP),A + INC A + SCF + RET ;ZF=0, CF=1 +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +; [x] save hdd parameters to cmos for "setup" in settings +; IN: A' = DRV_Flags +SaveToCMOS: + LD A,(IDEDEV) + CP IDE.Device.HDD + RET NZ + + EX AF,AF' + ;LD A,(IY+IDE.HDD_INIT_TABLE.DRV_Flags) + AND %0001'0001 + LD IX,PRIM_MASTER_CMOS_TABLE + JR Z,.save_to_cmos + ; + DEC A + LD IX,SEC_MASTER_CMOS_TABLE + JR Z,.save_to_cmos + ; + CP %0001'0000 + LD IX,SEC_SLAVE_CMOS_TABLE + JR Z,.save_to_cmos + ; + LD IX,PRIM_SLAVE_CMOS_TABLE +.save_to_cmos: + LD HL,(IDENTIFY_DEVICE_BUFFER.NumCylinders) + LD B,L + LD A,(IX + IDE_CMOS_TABLE.CylindersLow) + CALL WRITCMS + + LD B,H + LD A,(IX + IDE_CMOS_TABLE.CylindersHigh) + CALL WRITCMS + + LD A,(IDENTIFY_DEVICE_BUFFER.NumHeads) + LD B,A + LD A,(IX + IDE_CMOS_TABLE.Heads) + CALL WRITCMS ; Heads + + LD A,(IDENTIFY_DEVICE_BUFFER.NumSectorsPerTrack) + LD B,A + LD A,(IX + IDE_CMOS_TABLE.Sectors) + JP WRITCMS +/////////////////////////////////////////////////////////////////////[^] + +/////////////////////////////////////////////////////////////////////[v] +; Check bug with 31 sec freeze +; Bug31SecCheck: LD A,(MasterSlave) +; AND 1 +; RET NZ +; ; +; LD HL,PAUSES.HALT.Time_2s +; CALL BITS_WAITS.Clear_BUSY +; CCF +; RET C +; ; +; .RESET_Slave_ATAPI: +; LD A,IDE.Drive.Slave +; LD BC,IDE.Write.DeviceHead +; OUT (C),A +; PAUSE_DJNZ 16 +; LD BC,IDE.Write.Command +; LD A,IDE.CMD.ATAPI.Reset +; OUT (C),A +; PAUSE_DJNZ 16 +; LD A,IDE.Drive.Master +; LD BC,IDE.Write.DeviceHead +; OUT (C),A +; RET +/////////////////////////////////////////////////////////////////////[^] +/////////////////////////////////////////////////////////////////////[v] +; Check bug with 31 sec freeze +Bug31SecCheck: LD A,(MasterSlave) + ;AND 1 + RRA + RET C + ; + LD HL,PAUSES.HALT.Time_2s + CALL BITS_WAITS.Clear_BUSY + RET NC + JR NZ,.skip + ; +.RESET_Slave_ATAPI: + LD A,IDE.Drive.Slave + LD BC,IDE.Write.DeviceHead + OUT (C),A + PAUSE_DJNZ 32 + LD BC,IDE.Write.Command + LD A,IDE.CMD.ATAPI.Reset + OUT (C),A + PAUSE_DJNZ 64 + LD A,IDE.Drive.Master + LD BC,IDE.Write.DeviceHead + OUT (C),A + PAUSE_DJNZ 32 + ; + ;CALL SEND_NOP + ;SCF + ;CF=1 + RET + ; +.skip: POP BC ; баланс стека + JP AUTODETECTING.IDE_ABSENT +/////////////////////////////////////////////////////////////////////[^] + +/////////////////////////////////////////////////////////////////////[v] +GETPARAM: LD HL,PAUSES.WAIT.IDE + ;LD DE,256*(IDE.CtrlByte.Busy + IDE.CtrlByte.DataRequest) + IDE.CtrlByte.DataRequest + LD DE,256*IDE.CtrlByte.DataRequest + IDE.CtrlByte.DataRequest + CALL BITS_WAITS.WAIT_PRT + RET C + LD BC,IDE.Read.Data + LD HL,IDENTIFY_DEVICE_BUFFER + INIR + INIR + CALL PARSE_IdentifyDevice + ; [x] save hdd parameters to cmos for "setup" in settings + CALL SaveToCMOS + AND A + RET +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +DETECTORS: +;-------; + ; CHECK BY COUNTER PORT. + ; Exit: CF - No device +.test_counter EQU 5 +.Counter: LD A,.test_counter + LD BC,IDE.Write.Counter + OUT (C),A + LD HL,PAUSES.WAIT.SMALL + LD DE,IDE.CtrlByte.Busy*256 + 0 + CALL BITS_WAITS.WAIT_PRT + RET C + ; + LD BC,IDE.Read.Counter + IN A,(C) + CP .test_counter + SCF + RET NZ + AND A + RET + ; + ; забиваем туфтой для теста ATAPI в .IdentDevCheck + ;XOR A + ;INC B + ;INC C ; IDE.Write.Sector + ;OUT (C),A + ;INC C ; IDE.Write.CylinderLow + ;OUT (C),A + ;INC C ; IDE.Write.CylinderHigh + ;OUT (C),A + ;RET +;-------; + +;-------; + ; CHECK BY EXECUTING NOP COMMAND AND WAIT. + ; Exit: CF - No device +.NOP_Check: CALL SEND_NOP + LD HL,PAUSES.HALT.MEDIUM + LD BC,IDE.Read.Status + ; +.loop: IN A,(C) + SCF + RET Z + ; old CF bug fix + CP IDE.CtrlByte.Ready + IDE.CtrlByte.SeekComplete + RET Z + ; + AND IDE.CtrlByte.Busy + IDE.CtrlByte.DataRequest + IDE.CtrlByte.Error + CP IDE.CtrlByte.Error + RET Z + ; + HALT + DEC HL + LD A,H + OR L + ;JR Z,.nop_exit + SCF + RET Z ; Absent + ; + CALL SKIPKEY + RET C ; Skipped = Absent + JR .loop + ; +; .nop_exit: IN A,(C) +; CP IDE.CtrlByte.Ready + IDE.CtrlByte.SeekComplete +; RET Z ; old CF bug fix +; SCF +; RET ; Absent +;-------; + +;-------; + ; CHECK WITH Identify Device. + ; Exit: CF - No device + ; NC and ZF - ATA + ; NC and NZ - ATAPI +.IdentDevCheck: LD E,IDE.CMD.ATA.IdentifyDevice + LD BC,IDE.Write.Command + OUT (C),E + ; + LD DE,IDE.CtrlByte.Busy * 256 + 0 + LD HL,PAUSES.WAIT.IDE + CALL BITS_WAITS.WAIT_PRT + RET C ; Absent + ; + LD BC,IDE.Read.Status + IN A,(C) + RRCA + JR C,.non_ATA + ; + AND (IDE.CtrlByte.DataRequest + IDE.CtrlByte.Ready) / 2 + SCF + RET Z + ; + XOR A + RET ; ATA + ; +.non_ATA: LD BC,IDE.Read.Error + IN A,(C) + AND IDE.ErrorByte.Abort + ; + RET NZ ; ATAPI + SCF + RET ; Absent + ; check signature #0114EB + ;SCF + ;RET Z ; Absent + ;LD C,low IDE.Read.Sector + ;IN A,(C) + ;DEC A + ;;CF=1 + ;RET NZ + ;; + ;INC C ; LD BC,IDE.Read.CylinderLow + ;IN L,(C) + ;INC C ; LD BC,IDE.Read.CylinderHigh + ;IN H,(C) + ;;AND A + ;LD BC,#EB14 - 1 ; CF=1 + ;SBC HL,BC + ;SCF + ;RET NZ + ;;A=0, CF=1 + ;ADC A,A ; CF=0,ZF=0 + ;RET ; ATAPI + ; +;-------; + +;-------; + ; ATAPI or Absent + ; Exit: CF - No device + ; NC - ATAPI +.IdentPDevChk: LD E,IDE.CMD.ATAPI.IdentifyPacketDevice + LD BC,IDE.Write.Command + OUT (C),E + ; + LD HL,PAUSES.HALT.Time_2s + LD DE,IDE.CtrlByte.Busy*256 + 0 + CALL BITS_WAITS.Clear_BUSY + RET C + ; + ; BC = IDE.Read.Status + IN A,(C) + RRCA + RET +;-------; + +;-------; +; если канал пустой, то читается из порта то, что было выставлено +; последним на шину c чётного адреса в памяти а это первый или второй +; байт кода команды + ALIGN 2 ; тут нужно выравнивание по задуманным адресам для команд чтения из портов +.CheckChanel: LD BC,IDE.Read.Status + IN A,(C) ;#ED78 A=#78 + IN L,(C) ;#ED68 L=#68 + LD D,A + IN A,(C) ;#ED60 A=#ED + LD E,L + ; если пустой: DE=#7868, A=#ED + ; + LD HL,#7868 ; #7868 + #ED = #7955 + AND A + SBC HL,DE + JR Z,.NOT_HL + ; + AND A + RET ; not absent + ; +.NOT_HL: XOR #ED + RET NZ + SCF + RET ; absent +;-------; +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] + IFUSED Nop_CHANELS +Nop_CHANELS: + LD A,1 + CALL .CMD + LD A,3 + CALL .CMD + XOR A ; LD A,0 + CALL .CMD + LD A,2 +.CMD: CALL SELECT_IDE + PAUSE_DJNZ 32 + LD BC,IDE.Write.Command + LD H,IDE.CMD.ATA.Nop + OUT (C),H + PAUSE_DJNZ 64 + LD BC,IDE.Read.Status + IN A,(C) + RET + ; Disable INTRQ + ; LD BC,IDE.Write.DeviceControl + ; LD A,%0000'0010 + ; OUT (C),A + ; PAUSE_DJNZ 32 + ; ; + ; CALL DisableStandBy + ; PAUSE_DJNZ 32 + ENDIF +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +; DisableWriteCache: +; LD BC,IDE.Write.Features +; LD A,IDE.CMD.ATA.SetFeatures.DisableWriteCache +; OUT (C),A +; LD A,IDE.CMD.ATA.SetFeatures +; JP IDE_CMD +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +;Disable StandBy timer +; DisableStandBy: +; LD BC,IDE.Write.Counter +; XOR A +; OUT (C),A +; LD A,IDE.CMD.ATA.Idle +; JP IDE_CMD +/////////////////////////////////////////////////////////////////////[^] + + +/////////////////////////////////////////////////////////////////////[v] +; DISABLE_8bit: +; LD BC,IDE.Write.Features +; LD A,IDE.CMD.ATA.SetFeatures.Disable8bit +; OUT (C),A +; LD A,IDE.CMD.ATA.SetFeatures +; JP IDE_CMD +/////////////////////////////////////////////////////////////////////[^] + +IDE_CMOS_TABLE: +.CylindersLow EQU 0 +.CylindersHigh EQU 1 +.Heads EQU 2 +.Sectors EQU 3 +; +PRIM_MASTER_CMOS_TABLE: + DB CMOS_CELL.IDE_Setup.PriMaster.CylindersLow + DB CMOS_CELL.IDE_Setup.PriMaster.CylindersHigh + DB CMOS_CELL.IDE_Setup.PriMaster.Heads + DB CMOS_CELL.IDE_Setup.PriMaster.Sectros +PRIM_SLAVE_CMOS_TABLE: + DB CMOS_CELL.IDE_Setup.PriSlave.CylindersLow + DB CMOS_CELL.IDE_Setup.PriSlave.CylindersHigh + DB CMOS_CELL.IDE_Setup.PriSlave.Heads + DB CMOS_CELL.IDE_Setup.PriSlave.Sectros +SEC_MASTER_CMOS_TABLE: + DB CMOS_CELL.IDE_Setup.SecMaster.CylindersLow + DB CMOS_CELL.IDE_Setup.SecMaster.CylindersHigh + DB CMOS_CELL.IDE_Setup.SecMaster.Heads + DB CMOS_CELL.IDE_Setup.SecMaster.Sectros +SEC_SLAVE_CMOS_TABLE: + DB CMOS_CELL.IDE_Setup.SecSlave.CylindersLow + DB CMOS_CELL.IDE_Setup.SecSlave.CylindersHigh + DB CMOS_CELL.IDE_Setup.SecSlave.Heads + DB CMOS_CELL.IDE_Setup.SecSlave.Sectros + + +SKIP: BYTE #FF +IDEDEV: BYTE #FF +ICHANEL: BYTE #00 +MasterSlave BYTE #00 + + +;WAITHDD DEC L +; RET NZ +; DEC H +; RET NZ +; DEC E +; RET NZ +; SCF +; RET + +; E - Second * 10 + +;PAUSE LD HL,#0000 +;PAUSE1 DEC L +; JR NZ,PAUSE1 +; DEC H +; JR NZ,PAUSE1 +; DEC E +; JR NZ,PAUSE1 +; RET + + ENDMODULE ; \ No newline at end of file diff --git a/src/bios/rom/SETUP/IM2_INT.asm b/src/bios/rom/SETUP/IM2_INT.asm new file mode 100644 index 0000000..f923a6c --- /dev/null +++ b/src/bios/rom/SETUP/IM2_INT.asm @@ -0,0 +1,54 @@ +; +; before_intPointer EQU #C000 +; INT_POINTER EQU #C002 +; INT_HANDLER EQU #C004 + + +before_intPointer EQU $ + BLOCK #FF - low $,0 ; выравнивание на #xxFF +INT_POINTER: WORD 0 + + ASSERT +low INT_POINTER = #FF, 'ERROR! Not valid interrupt pointer!' + IFDEF PREBUILD + ASSERT INT_POINTER-before_intPointer < 16, 'Warning! To much space before INT_POINTER.' + ELSE + IF INT_POINTER-before_intPointer > 16 + DISPLAY 'Warning! To much space before INT_POINTER: ',/D,INT_POINTER-before_intPointer + ENDIF + ENDIF + +INT_HANDLER: PUSH AF + EX AF,AF' + PUSH AF + PUSH BC + PUSH DE + PUSH HL + EXX + PUSH BC + PUSH DE + PUSH HL + PUSH IX + PUSH IY + CALL KEYSCAN + ; + IF STARTUP_SND + SCF +.sndSwitch: CCF ; SCF/CCF + CALL C,STARTUP_SOUND + ENDIF + ; + POP IY + POP IX + POP HL + POP DE + POP BC + EXX + POP HL + POP DE + POP BC + POP AF + EX AF,AF' + POP AF + EI + RETI +; \ No newline at end of file diff --git a/src/bios/rom/SETUP/KEY.asm b/src/bios/rom/SETUP/KEY.asm index a9fde70..40134bb 100644 --- a/src/bios/rom/SETUP/KEY.asm +++ b/src/bios/rom/SETUP/KEY.asm @@ -1,10 +1,10 @@ ; - _mInfoALIGN 256,0 ; выравнивание на адрес #XX00 + _mInfoALIGN 256,0 ; выравнивание на адрес #XX00 SBUF: BLOCK 64,0 -HEAD: DB 0 -HOST: DB 0 +HEAD: DB 0 +HOST: DB 0 ; K_LOCK EQU $-KEYFLAG @@ -16,7 +16,7 @@ NUM_L EQU 3 SCRL_L EQU 2 INS_L EQU 1 CAPS_L EQU 0 -KEYFLAG DB 2 ;D0-Key Pressed +KEYFLAG: DB 2 ;D0-Key Pressed ; K_SHIFT EQU $-KEYFLAG L_SHIFT EQU 7 @@ -27,7 +27,7 @@ L_CTRL EQU 3 L_ALT EQU 2 R_CTRL EQU 1 R_ALT EQU 0 -KEYCTRL DB 0 +KEYCTRL: DB 0 ; KEYFLG EQU $-KEYFLAG FLAG_E0 EQU 7 @@ -51,7 +51,7 @@ SF_ALT EQU 1 SF_BUFF EQU 0 DB 3 ; -UNCODE: DW 0000 +;UNCODE: DW 0000 ; ; D15 - LShift @@ -81,115 +81,131 @@ UNCODE: DW 0000 ; D8 ; D7..D0 - ASCII code -WAITKEY: - LD HL,HOST - LD A,(HEAD) - CP (HL) - JR Z,WAITKEY - CALL GETSYM - LD A,E - AND A - RET +WAITKEY: LD HL,HOST + LD A,(HEAD) + CP (HL) + JR Z,WAITKEY + CALL GETSYM + LD A,E + ;AND A + RET -SCANKEY: - LD HL,HOST - LD A,(HEAD) - CP (HL) - RET Z - CALL GETSYM - LD A,E - RET +SCANKEY: LD HL,HOST + LD A,(HEAD) + CP (HL) + RET Z + CALL GETSYM + LD A,E + RET -CTRLKEY: - LD HL,HOST - LD A,(HEAD) - CP (HL) - LD BC,(KEYFLAG) - LD A,#00 - RET Z - DEC A - RET +CTRLKEY: LD HL,HOST + LD A,(HEAD) + CP (HL) + LD BC,(KEYFLAG) + LD A,#00 + RET Z + DEC A + RET -PUTSYM: - LD HL,HEAD - LD A,(HOST) - SUB 4 - AND #3F - CP (HL) - JR Z,FULL_BF - LD A,(HL) - INC (HL) - INC (HL) - INC (HL) - INC (HL) - RES 6,(HL) - LD L,A - LD H,high SBUF - LD (HL),E - INC L - LD (HL),D - INC L - LD (HL),B - INC L - LD (HL),C - RET +PUTSYM: LD HL,HEAD + LD A,(HOST) + SUB 4 + AND #3F + CP (HL) + JR Z,FULL_BF + ; + CALL GetSymAddr + ; + LD (HL),E + INC L + LD (HL),D + INC L + LD (HL),B + INC L + LD (HL),C + RET -GETSYM: LD HL,HOST - LD A,(HEAD) - CP (HL) - RET Z - LD A,(HL) - INC (HL) - INC (HL) - INC (HL) - INC (HL) - RES 6,(HL) - LD L,A - LD H,high SBUF - LD E,(HL) - INC L - LD D,(HL) - INC L - LD B,(HL) - INC L - LD C,(HL) - RET +GetSymAddr: LD A,(HL) + INC (HL) + INC (HL) + INC (HL) + INC (HL) + RES 6,(HL) + LD L,A + LD H,high SBUF + RET -FULL_BF: - EX AF,AF' - BIT SF_BUFF,(IX+SOUND_K) - JR Z,.FBF - EXX - LD DE,230 - LD HL,50 - CALL BEEP - EXX -.FBF: EX AF,AF' - RET +GETSYM: LD HL,HOST + LD A,(HEAD) + CP (HL) + RET Z + AND A + ; + CALL GetSymAddr + ; + LD E,(HL) + INC L + LD D,(HL) + INC L + LD B,(HL) + INC L + LD C,(HL) + RET -KEYSCAN: - LD IX,KEYFLAG +FULL_BF: EX AF,AF' + BIT SF_BUFF,(IX+SOUND_K) + JR Z,.FBF + EXX + LD DE,230 + LD HL,50 + CALL BEEP + EXX +.FBF: EX AF,AF' + RET + +KEYSCAN: LD IX,KEYFLAG RESCANN: IN A,(Z84.SIO.Ch_A.Ctrl) - BIT 0,A - RET Z + AND 1 + RET Z + ;[x] 18/02/2024 проверка на переполнение буфера + ; A = 1 + ; reg 1 + OUT (Z84.SIO.Ch_A.Ctrl),A + IN A,(Z84.SIO.Ch_A.Ctrl) + AND %0010'0000 ; check receiver overrun error + JP NZ,Receiver_Overrun + ; IN A,(Z84.SIO.Ch_A.Data) CP #F0 JR Z,F0_KEY CP #E0 JR Z,E0_KEY - CP #E1 - JR Z,E1_KEY + ; + CP #E1 + IF USE_E1_SCANCODE + JR Z,E1_KEY + ELSE + JR Z,RESCANN + ENDIF + ; BIT FLAG_F0,(IX+KEYFLG) JR NZ,UN_KEY + ; LD L,A CALL XLAT CALL SHIFTS RES FLAG_E0,(IX+KEYFLG) - RES FLAG_E1,(IX+KEYFLG) - RET Z ;IT'S SHIFT KEY + IF USE_E1_SCANCODE + RES FLAG_E1,(IX+KEYFLG) + ENDIF + ; + ;[x] 29/02/2024 выгребсти весь буфер + JR Z,RESCANN ;IT'S SHIFT KEY + ; RET Z ;IT'S SHIFT KEY + ; CALL INPCODE ;L - AT POS. CODE -.PUTCODE: + ;PUTCODE LD HL,#1C00 ;Caps Lock AND A SBC HL,DE @@ -225,7 +241,7 @@ RESCANN: ;-----------------------; LD BC,(KEYFLAG) CALL PUTSYM - RET + JP RESCANN E0_KEY: SET FLAG_E0,(IX+KEYFLG) JR RESCANN @@ -233,41 +249,43 @@ E0_KEY: SET FLAG_E0,(IX+KEYFLG) F0_KEY: SET FLAG_F0,(IX+KEYFLG) JR RESCANN -E1_KEY: SET FLAG_E1,(IX+KEYFLG) - JR RESCANN + IF USE_E1_SCANCODE +E1_KEY: SET FLAG_E1,(IX+KEYFLG) + JR RESCANN + ENDIF UN_KEY: RES FLAG_F0,(IX+KEYFLG) LD L,A CALL XLAT CALL UNSHIFT RES FLAG_E0,(IX+KEYFLG) - LD H,0 - LD (UNCODE),HL + ;LD H,0 + ;LD (UNCODE),HL RET -CAPS_X: LD A,(IX+K_LOCK) - XOR #01 - LD (IX+K_LOCK),A +CAPS_X: LD A,(KEYFLAG) + XOR 1< 16 - DISPLAY 'Warning! To much space before INT_POINTER: ',/D,INT_POINTER-before_intPointer - ENDIF - ENDIF +; ASSERT +low INT_POINTER = #FF, 'ERROR! Not valid interrupt pointer!' +; IFDEF PREBUILD +; ASSERT INT_POINTER-before_intPointer < 16, 'Warning! To much space before INT_POINTER.' +; ELSE +; IF INT_POINTER-before_intPointer > 16 +; DISPLAY 'Warning! To much space before INT_POINTER: ',/D,INT_POINTER-before_intPointer +; ENDIF +; ENDIF -INT_HANDLER: - PUSH AF - EX AF,AF' - PUSH AF - PUSH BC - PUSH DE - PUSH HL - EXX - PUSH BC - PUSH DE - PUSH HL - PUSH IX - PUSH IY - CALL KEYSCAN - POP IY - POP IX - POP HL - POP DE - POP BC - EXX - POP HL - POP DE - POP BC - POP AF - EX AF,AF' - POP AF - EI - RETI -; -INT_OFF: - DI - LD A,#3F - LD I,A - IM 1 - RET +; INT_HANDLER: +; PUSH AF +; EX AF,AF' +; PUSH AF +; PUSH BC +; PUSH DE +; PUSH HL +; EXX +; PUSH BC +; PUSH DE +; PUSH HL +; PUSH IX +; PUSH IY +; CALL KEYSCAN +; POP IY +; POP IX +; POP HL +; POP DE +; POP BC +; EXX +; POP HL +; POP DE +; POP BC +; POP AF +; EX AF,AF' +; POP AF +; EI +; RETI +; ; -INT_ON: - DI - LD A,+high INT_POINTER - LD I,A - LD HL,INT_HANDLER - LD (INT_POINTER),HL - IM 2 - EI - RET +INT_OFF: DI + LD A,#3F + LD I,A + IM 1 + RET + ; +INT_ON: DI + LD A,+high INT_POINTER + LD I,A + LD HL,INT_HANDLER + LD (INT_POINTER),HL + IM 2 + EI + RET ; ; ;------------------------[go to spectrum from bios]---------------------; -EXIT_SETUP: - CALL INT_OFF -; -; LD BC,#020E -; CALL G_VALUE -; OR A -; LD A,#EC ;SPRINTER -; JR Z,XFLEX -; LD A,#EA ;SPECTRUM -;XFLEX: - LD A,ROM.BIOS - OUT (SYS_PORT.ROM),A - POP HL ; пихается в EXP.ASM в процедуре - JP (HL) -; LD (JMPHL),HL +EXIT_SETUP: CALL INT_OFF + CALL TRD_MOUNT ; !TEST 24/09/2024 перенос в EXIT_SETUP (перед запуском ZX) + CALL SetUp_ZX_HDD - ; LD C,#F3 - ; RST ToBIOS_18 -; JMPHL EQU $+1 -; JP #0000 +; IF FREE_ZX_PAGES + LD A,Spec_Page + OUT (SLOT3),A + ; + LD A,(Spec_Page.flag_Z) + CP 'Z' + LD A,(Spec_Page.flag_X) + LD B,A + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,B + JR NZ,.Set_Page41 + CP 'X' +.Set_Page41: CALL NZ,ZXMODE_SETUP.Set_Page41 + +.set_ZX_params: LD BC,CMOS_CELL.QuickStartSetUp.Mask.ZxRom + CALL GET_CMOS_VALUE + LD L,A + LD BC,CMOS_CELL.QuickStartSetUp.Mask.Hardware + CALL GET_CMOS_VALUE + ; + EX AF,AF + LD A,ROM.EXTENSION + OUT (SYS_PORT.ROM),A + EX AF,AF + OR A + JP Z,SPRINTER_ZX.custom_ROM + DEC A + JP Z,Pentagon_48.custom_ROM + DEC A + JP Z,PENTAGON_128.custom_ROM + DEC A + JP Z,PENTAGON_512.custom_ROM + DEC A + JP Z,SCORPION_256.custom_ROM + DEC A + JP Z,ZX_Spectrum_48.custom_ROM + DEC A + JP Z,ZX_SPECTRUM_128.custom_ROM + ; error + XOR A + OUT (SYS_PORT.ROM),A + LD D,CMOS_CELL.QuickStartSetUp ; обнуляем параметр на всякий случай + CALL CMOS_WR + ; + CALL ScreenPOS.CRLF + LD A,msgStrings.errorZXmode + LD E,COLORS.CGA.INK.RED + CALL POSTMSC +.loop_di: DI + HALT + JR .loop_di + + + +SetUp_ZX_HDD: LD D,CMOS_CELL.TRDOSmount + CALL CMOS_RD + AND %1010'1010 ; маска для 4-х HDD + RET Z + ; find first good partition + ; + ; чистка переменных ZX HDD + IN A,(SLOT3) + EX AF,AF + LD A,SYS_PAGE + OUT (SLOT3),A + ; + XOR A + LD H,A + LD L,A + LD (SYS_PAGE.CURRENT_DIR_SEC_L),HL + LD (SYS_PAGE.CURRENT_DIR_SEC_H),HL + DEC A + LD (SYS_PAGE.CURRENT_HDD),A + LD (SYS_PAGE.CURRENT_DIR_DRIVE),A + LD (SYS_PAGE.CURRENT_DIR_DRIVE_COPY),A + ; + EX AF,AF + OUT (SLOT3),A + EX AF,AF + ; + XOR A +.loop: PUSH AF + CALL FN_HDD_PART + POP BC + RET NC + LD A,B + INC A + CP #10 + JR C,.loop + RET ;-----------------------------------------------------------------------; - INSTALL: CALL INT_ON CALL SET_CGA XOR A - OUT (#FE),A + OUT (BorderColor),A LD IX,win_descriptor.tab80x32 - LD HL,#0000 - LD E,1 - ;LD C,BIOS.WIN_OPEN - ;RST ToBIOS_18 - CALL WIN_OPEN + CALL WIN_OPEN.SCR1 LD DE,0 LD HL,#2050 - ;LD BC,7*256 + BIOS.LP_CLS_WIN - ;RST ToBIOS_18 LD B,7 CALL LP_CLS_WIN LD DE,0 LD HL,#0820 - ;LD BC,0*256 + BIOS.LP_CLS_WIN - ;RST ToBIOS_18 LD B,0 CALL LP_CLS_WIN CALL SETLAND CALL GET_ID - LD DE,#0028 ; !HARDCODE - ;CALL ScreenPOS.LOCAT + LD DE,#0028 ; !HARDCODE CALL LP_SET_PLACE LD HL,memBUFFER.ID - LD A,COLORS.INC.LCYAN - CALL CPRINTZ - LD HL,BUILD - LD A,COLORS.INC.LCYAN + LD A,COLORS.CGA.INK.LCYAN CALL CPRINTZ + ; LD HL,BUILD + ; LD A,COLORS.CGA.INK.LCYAN + ; CALL CPRINTZ - LD DE,#0128 ; !HARDCODE - ;CALL ScreenPOS.LOCAT + LD DE,#0128 ; !HARDCODE CALL LP_SET_PLACE LD A,msgStrings.copyRightPeters - LD E,COLORS.INC.LGREEN + LD E,COLORS.CGA.INK.LGREEN CALL POSTMSC - LD DE,#0228 ; !HARDCODE - ;CALL ScreenPOS.LOCAT + LD DE,#0228 ; !HARDCODE CALL LP_SET_PLACE LD A,msgStrings.copyRightSPTeam - LD E,COLORS.INC.GREEN + LD E,COLORS.CGA.INK.GREEN CALL POSTMSC - IF DEBUG LD DE,#0328 - ;CALL ScreenPOS.LOCAT CALL LP_SET_PLACE - LD A,msgStrings.testBIOSmsg - LD E,COLORS.FLASH + COLORS.INC.RED ; !HARDCODE - CALL POSTMSC + LD A,msgStrings.extBIOSmsg + IF BETA_BUILD > 0 + LD E,COLORS.CGA.FLASH + COLORS.CGA.INK.RED + ELSE + LD E,COLORS.CGA.INK.LGRAY ENDIF + CALL POSTMSC IN A,(SLOT3) PUSH AF @@ -487,26 +552,26 @@ INSTALL: OUT (SLOT3),A RET -BUILD: - db ', BIOS v', Disk_subsystem_ver_txt,0 ; !FIXIT может воткнуть вместе с msgStrings ? +RESTART_ID: +.str: DZ "RESTART" +.size EQU $ - RESTART_ID.str -RSTID: DB "RESTART",0 -.size EQU $-RSTID - -Start_again: - ld sp,STACK-2 -START: - DI - PUSH AF - XOR A - LD (ERRSUM),A - ld (ERRSUM.ErrDateTime),a +Start_again: LD SP,STACK-2 +START: DI + PUSH AF + XOR A + LD (ERRSUM),A + LD (ERRSUM.ErrDateTime),A + ; + LD A,R ; reg R bit7 - признак запуска с отработкой лоадера конфы (из SET_CONFIG_ID) + LD (LOGOTYPE.playSnd),A + ; ; LD C,#97 -; RST ToBIOS_18 +; RST_to_BIOS_18 ; XOR A ; LD C,#F2 -; RST ToBIOS_18 +; RST_to_BIOS_18 ;------------------------------ ;!!!!! посмотреть ; CALL KINIT ;------------------------------ ;!!!!! посмотреть @@ -523,19 +588,22 @@ START: ;R08 CALL OPENDOS - CALL ZXCLS + ;!TEST 20/08/2024 + ;CALL ZXCLS + ; CALL READING - CALL TCHEKSM + CALL TEST_CHECKSUM CALL NZ,SETDEFX - -; LD A,#1C ;!TODO CMOS Disabled use of CONFIG_DE (#C13A) word -; CALL READCMS -; PUSH AF -; LD A,#1B ;!TODO CMOS -; CALL READCMS -; POP DE -; LD E,A + ;!TODO CMOS Disabled use of CONFIG_DE (#C13A) word + ;LD A,#1C + ;CALL READCMS + ;PUSH AF + ;LD A,CMOS_CELL.HardwareConfiguration + ;CALL READCMS + ;POP DE + ;LD E,A + ; LD C,SLOT3 IN B,(C) @@ -543,9 +611,9 @@ START: LD A,SYS_PAGE OUT (C),A -; LD (#C13A),DE CONFIG_DE +; LD (SYS_PAGE.CONFIG_DE),DE - LD HL,SYS_PAGE.INT_ADRESS ;EXTENDED INTERRUPT + LD HL,SYS_PAGE.INT_ADRESS ;EXTENDED INTERRUPT XOR A LD (HL),A INC L @@ -557,18 +625,19 @@ START: POP BC OUT (C),B - CALL TRQUICK - CALL FINSTAL - CALL CLEARM - CALL RESCREEN + + ;CALL TRD_MOUNT ; !TEST 24/09/2024 перенос в EXIT_SETUP (перед запуском ZX) + CALL FDD_INSTAL + CALL CLEAR_MEM + CALL ZXMODE_SETUP + CALL XY_SCREEN -;R06 - LD BC,#010E ; QUICK START - CALL G_VALUE +;R06 ;[Check Quick Start ROM] + LD BC,CMOS_CELL.BootUpParams.Mask.QuickStartROM ;#010E + CALL GET_CMOS_VALUE POP BC - INC B - DEC B - JR NZ,QIGNORE ; результат проверки Space из exp.asm [space_check] + RR C + JR NC,IGNORE_QuickStartROM ; результат проверки Space из exp.asm [Check SPACE] PUSH AF LD C,SLOT3 IN B,(C) @@ -576,62 +645,62 @@ START: LD A,SYS_PAGE OUT (C),A LD HL,SYS_PAGE.RESTART_ID - LD DE,RSTID - LD B,RSTID.size - CALL COMPARE - CALL NZ,SETRSTS + LD DE,RESTART_ID.str + LD B,RESTART_ID.size + CALL COMPARE_RESTART_ID + CALL NZ,SET_RESTART_ID POP BC OUT (C),B - JR Z,HOTST + JR Z,YES_QuickStartROM POP AF - JR QIGNORE + JR IGNORE_QuickStartROM -SETRSTS: +SET_RESTART_ID: PUSH AF - LD HL,RSTID + LD HL,RESTART_ID.str LD DE,SYS_PAGE.RESTART_ID - LD BC,RSTID.size + LD BC,RESTART_ID.size LDIR LD HL,PowerOnDate ; !TODO изменить под структуру, когда структура переменных будет готова CALL GETTIME POP AF RET -HOTST: +YES_QuickStartROM: POP AF OR A JP NZ,EXIT_SETUP -QIGNORE: +IGNORE_QuickStartROM: CALL INSTALL LD DE,#0528 ;CALL ScreenPOS.LOCAT CALL LP_SET_PLACE LD A,msgStrings.toSetupButton - LD E,COLORS.FLASH + COLORS.INC.WHITE + LD E,COLORS.CGA.FLASH + COLORS.CGA.INK.WHITE CALL POSTMSC LD DE,#0900 ;CALL ScreenPOS.LOCAT CALL LP_SET_PLACE ERRSUM+1: - LD A,#00 ;MEM Patch! + LD A,#00 OR A JR Z,.ErrDateTime - xor a - ld (.ErrDateTime+1),a ; если контрольная сумма слетела, то сообщение о кривых дате/времени в кмос не выводим + XOR A + LD (.ErrDateTime+1),A ; если контрольная сумма слетела, то сообщение о кривых дате/времени в кмос не выводим LD A,msgStrings.cmosChecksumErr - LD E,COLORS.INC.RED + LD E,COLORS.CGA.INK.RED CALL POSTMSC CALL ScreenPOS.CRLF CALL ScreenPOS.CRLF JR CHEKOK .ErrDateTime+1: - ld a,0 - or a - jr z,CHEKOK + LD A,0 + OR A + JR Z,CHEKOK LD A,msgStrings.cmosDateTimeErr - LD E,COLORS.INC.RED + LD E,COLORS.CGA.INK.RED CALL POSTMSC CALL ScreenPOS.CRLF CALL ScreenPOS.CRLF @@ -639,7 +708,7 @@ ERRSUM+1: CHEKOK: ;CALL ScreenPOS.GET_CUR CALL LP_GET_PLACE PUSH DE - CALL LOGOTYP + CALL LOGOTYPE LD DE,#0000 ;CALL ScreenPOS.LOCAT @@ -654,10 +723,13 @@ CHEKOK: ;CALL ScreenPOS.GET_CUR CALL PIDBOARD CALL ScreenPOS.CRLF + LD A,msgStrings.spCNFver + CALL POSTMSG + CALL CNF_VER_PRINT + CALL ScreenPOS.CRLF + LD A,msgStrings.spMemory CALL POSTMSG - ;LD C,BIOS.GetMemSize - ;RST ToBIOS_18 CALL EMM.GetMemSize PUSH BC CALL PMEMORY @@ -672,7 +744,8 @@ CHEKOK: ;CALL ScreenPOS.GET_CUR CALL CMOS_TEST LD A,msgStrings.cmosNone - JR C,NOCMOS + JR C,CMOS_ABSENT + ; CMOS OK CALL CMOSINIT LD A,msgStrings.cmosFound CALL POSTMSG @@ -683,101 +756,118 @@ CHEKOK: ;CALL ScreenPOS.GET_CUR LD HL,RebootDate CALL PRNTIME CALL ScreenPOS.CRLF - JR NOCMOS2 - -NOCMOS: + JR INFO_MESSAGE +CMOS_ABSENT: CALL POSTMSG -NOCMOS2: ;!FIXIT название неправильное +INFO_MESSAGE: + ; for recovery boot + ; LD DE,#0428 + ; CALL LP_SET_PLACE + ; LD A,msgStrings.forCtrlBootButton + ; LD E,COLORS.CGA.INK.WHITE + ; CALL POSTMSC + ; + ; For alternative boot LD DE,#0528 - ;CALL ScreenPOS.LOCAT - CALL LP_SET_PLACE + CALL LP_SET_PLACE LD A,msgStrings.forAltBootButton - LD E,COLORS.INC.WHITE + LD E,COLORS.CGA.INK.WHITE CALL POSTMSC + POP DE - ;CALL ScreenPOS.LOCAT CALL LP_SET_PLACE - CALL TSETUP + CALL TSETUP ;!TODO может пихнуть её на прерывания? - CALL AUTODET + CALL CONFIGURE_IDE_DRIVES.START + ;CALL CONFIGURE_IDE_DRIVES.Nop_CHANELS CALL CTRLKEY LD A,B - AND #10 - JR NZ,ABOOT + ; [x] 05/07/2024 + BIT X_CTRL,A + LD BC,#FFFF ; маркер для PrepareToBOOT, чтоб грузил Recovery + JR NZ,RECOVERY_BOOT + ; + BIT X_ALT,A + JR NZ,ALT_BOOT + ; CALL TSETUP - - - LD BC,#0710 ; !HARDCODE маска и ячейка для чтения значения кмос для основного загрузочного драйва + ; + LD BC,CMOS_CELL.BootDrives.Mask.SysDisk ;#0710 +RECOVERY_BOOT: CALL PrepareToBOOT LD A,msgStrings.bootFail - CALL C,POSTMSG + LD E,COLORS.CGA.INK.LRED + CALL C,POSTMSC CALL ScreenPOS.CRLF + ; + CALL INT_ON +ALT_BOOT: + LD A,msgStrings.bootAltDrv + LD E,COLORS.CGA.INK.LGREEN + CALL POSTMSC -ABOOT: LD A,msgStrings.bootAltDrv - CALL POSTMSG - - LD BC,#7010 ; !HARDCODE маска и ячейка для чтения значения кмос для альтернативного загрузочного драйва + LD BC,CMOS_CELL.BootDrives.Mask.AltSysDisk ;#7010 CALL PrepareToBOOT LD A,msgStrings.bootFail - CALL C,POSTMSG + LD E,COLORS.CGA.INK.LRED + CALL C,POSTMSC CALL ScreenPOS.CRLF -;NO START DISK - RESTART / SETUP / ZX SPECTRUM mode - LD BC,#021D - CALL G_VALUE + ;NO START DISK - RESTART / SETUP / ZX SPECTRUM mode + LD BC,CMOS_CELL.Options.Mask.RebootMSG ;#021D + CALL GET_CMOS_VALUE OR A JP Z,EXIT_SETUP CALL ScreenPOS.CRLF LD A,msgStrings.afterBootFail - LD E,COLORS.INC.RED + LD E,COLORS.CGA.INK.RED CALL POSTMSC ;EI CALL INT_ON -AGAKEY: CALL WAITKEY - LD HL,#4F00 ; DEL - go to settings - AND A - SBC HL,DE - JR Z,CSETUP - CP #1B ; ESC - go to zx spectrum mode - JP Z,EXIT_SETUP - CP #0D ; ENTER - restart - JP NZ,AGAKEY - XOR A - JP Start_again +StartUpKey: CALL WAITKEY + LD HL,#4F00 ; DEL - go to settings + ;AND A + SBC HL,DE + JR Z,ENTER_SETUP + ; + CP #1B ; ESC - go to zx spectrum mode + JP Z,EXIT_SETUP + CP #0D ; ENTER - restart + JP NZ,StartUpKey + XOR A + JP Start_again -TSETUP: - CALL SCANKEY - RET Z - LD HL,#4F00 - AND A - SBC HL,DE - JR Z,CSETUP - LD HL,#011B - AND A - SBC HL,DE - JR NZ,TSETUP - POP HL - JP EXIT_SETUP -CSETUP: -; POP HL -;------------test ; !!!!! посмотреть +TSETUP: CALL SCANKEY + RET Z + LD HL,#4F00 ; DEL - go to settings + AND A + SBC HL,DE + JR Z,ENTER_SETUP + ; + LD HL,#011B ; ESC + AND A + SBC HL,DE + JR NZ,TSETUP + POP HL ; убираем лишнее + JP EXIT_SETUP +ENTER_SETUP: XOR A LD (ITEM_Restore),A CALL SETTINGS XOR A JP Start_again -COMPARE: +COMPARE_RESTART_ID: LD A,(DE) CP (HL) RET NZ INC HL INC DE - DJNZ COMPARE + DJNZ COMPARE_RESTART_ID RET ; ????? перенести это в функции БИОС? @@ -785,105 +875,92 @@ COMPARE: writeDateTimeToCmos: ;!FIXIT LD A,(HL) LD D,CMOS.Register.hours - ;LD C,BIOS.CMOS_WR - ;RST ToBIOS_18 CALL CMOS_WR INC HL LD A,(HL) LD D,CMOS.Register.minutes - ;LD C,BIOS.CMOS_WR - ;RST ToBIOS_18 CALL CMOS_WR INC HL LD A,(HL) LD D,CMOS.Register.seconds - ;LD C,BIOS.CMOS_WR - ;RST ToBIOS_18 CALL CMOS_WR INC HL LD A,(HL) LD D,CMOS.Register.date - ;LD C,BIOS.CMOS_WR - ;RST ToBIOS_18 CALL CMOS_WR INC HL LD A,(HL) LD D,CMOS.Register.month - ;LD C,BIOS.CMOS_WR - ;RST ToBIOS_18 CALL CMOS_WR INC HL LD A,(HL) LD D,CMOS.Register.century - ;LD C,BIOS.CMOS_WR - ;RST ToBIOS_18 CALL CMOS_WR INC HL LD A,(HL) LD D,CMOS.Register.year - ;LD C,BIOS.CMOS_WR - ;RST ToBIOS_18 CALL CMOS_WR RET -RESCREEN: -;R06 - LD A,#1F ;!HARDCODE READ SCREEN POSITION - CALL READCMS - PUSH AF - IN A,(SLOT3) - LD E,A - LD A,DCP_PAGE - OUT (SLOT3),A - LD A,(#C400) ;c400 for first cfg 50176 ; !TODO можно переделать на вызов функции биоса - LD D,A - LD A,#CB - LD (#C400),A - POP AF - LD BC,0 - OUT (C),A - LD A,D - LD (#C400),A - LD A,E - OUT (SLOT3),a -;R06 - RET +XY_SCREEN: ;R06 + LD A,CMOS_CELL.ScreenPosition + CALL READCMS + LD B,A + LD A,ACEX.HOLD + JP SET_PORTS + ; PUSH AF + ; IN A,(SLOT3) + ; LD E,A + ; LD A,DCP_PAGE + ; OUT (SLOT3),A + ; LD A,(#C400) ;c400 for first cfg 50176 + ; LD D,A + ; LD A,ACEX.HOLD + ; LD (#C400),A + ; POP AF + ; LD BC,0 + ; OUT (C),A + ; LD A,D + ; LD (#C400),A + ; LD A,E + ; OUT (SLOT3),a + ; RET ; ;R07 ; CMOSINIT: ; LD D,10 ;FREQ ; LD C,#F6 ;READ CMOS -; RST ToBIOS_18 +; RST_to_BIOS ; CP #26 ; JR NZ,CMSERR ; LD D,12 ; LD C,#F6 -; RST ToBIOS_18 +; RST_to_BIOS ; CP #50 ; RET Z ; CMSERR: ; LD D,10 ; LD A,#26 ;FREQ ; LD C,#F7 -; RST ToBIOS_18 +; RST_to_BIOS ; LD D,11 ; LD A,#02 ;TIME FORMAT ; LD C,#F7 -; RST ToBIOS_18 +; RST_to_BIOS ; LD D,12 ; LD A,#50 ; LD C,#F7 -; RST ToBIOS_18 +; RST_to_BIOS ; LD D,13 ; LD A,#80 ; LD C,#F7 -; RST ToBIOS_18 +; RST_to_BIOS ; RET ;------------------- ;!!!!! посмотреть @@ -910,24 +987,18 @@ RECOVERYstart: ; прибиваем последний рамдиск, если занят .killRAMdisk: LD A,SYS_PAGE.RAMD_KEYS.NUM-1 LD (.RDkey),A - ;LD C,BIOS.FreeMemRMD - ;RST ToBIOS_18 CALL EMM.FreeMemRMD JR NC,.setRAMdisk JR Z,.setRAMdisk RET ; непонятная ошибка - выходим .setRAMdisk: LD A,(.RDkey) - ;LD BC,ROM_DISK.Pages.Size * 256 + BIOS.GetMemRMD - ;RST ToBIOS_18 LD B,ROM_DISK.Pages.Size CALL EMM.GetMemRMD JR NC,.IMGread ; свободный рамдиск найден DEC A JR Z,.FreeMem ; ошибка - недостаточно памяти, вызываем очистку памяти RET ; непонятная ошибка - выходим -.FreeMem: ;LD C,BIOS.FullInit - ;RST ToBIOS_18 - CALL EMM.FullInit +.FreeMem: CALL EMM.FullInit JR .killRAMdisk ; @@ -938,434 +1009,249 @@ RECOVERYstart: ; ;Exit from "ROM Disk to RAM disk" procedure .RDkey+*: LD A,0 - OR #60 ; !HARDCODE сделать им всем названия + OR DRIVE_CODES.SPRINTER.RAM LD B,A ; передаём загрузочное устройство в OS_LOAD JP OS_LOAD ; ;[ ][ ][ ][ ][ ][ ][ ][ ][ ][ ][ ][ ][ ][ ][ ][ ][ ][ ] ; - -PrepareToBOOT: - CALL INT_OFF - CALL G_VALUE - LD B,A - ; FDD - OR A - JR Z,FDSTART ; FDD A: - INC B - DEC A - JR Z,FDSTART ; FDD B: - ; IDE - LD B,#80 - DEC A - JR Z,HDSTART - INC B ;LD B,#81 - DEC A - JR Z,HDSTART - INC B ;LD B,#82 - DEC A - JR Z,HDSTART - INC B ;LD B,#83 - DEC A - JR Z,HDSTART - ; RAM - DEC A - JR Z,RDSTART - ; ROM - DEC A - JP Z,RECOVERYstart - ; Error - SCF - RET - -FDSTART: - PUSH BC - PUSH BC - LD A,msgStrings.bootFdd - CALL POSTMSG - POP AF - ;LD C,BIOS.DRV_RESET - ;RST ToBIOS_18 - CALL FDD_5x.RESET - POP BC - RET C - JP OS_LOAD -;!TODO -CDSTART: - PUSH BC - LD A,msgStrings.bootCd - CALL POSTMSG - POP BC - SET 6,B - SCF - RET - -RDSTART: - LD A,msgStrings.bootRamDrv - CALL POSTMSG - ld b,#60 ; !HARDCODE: 6 - тип драйва RAM-DRV, 0 - номер драйва -.loop: push bc - CALL OS_LOAD - pop bc - inc b - ld a,#6F ; !HARDCODE - максимальное число рамдисков - sub b - jr nc,.loop - RET +PrepareToBOOT: ;CALL INT_ON + HALT + CALL PORTS_INIT.clean_kbd_buf ;Clearing the keyboard buffer + CALL PORTS_INIT.clean_mouse_buf ;Clearing the mouse buffer + CALL INT_OFF + ; тут не должно быть испорчено значение BC + ; [x] 05/07/2024 + INC BC + LD A,B + OR C + JP Z,RECOVERYstart + DEC BC + ; + CALL GET_CMOS_VALUE + LD B,DRIVE_CODES.SPRINTER.FDD + ; FDD + OR A + JR Z,FDSTART ; FDD A: + INC B + DEC A + JR Z,FDSTART ; FDD B: + ; IDE + LD B,DRIVE_CODES.SPRINTER.HDD + DEC A + JR Z,HDSTART + INC B ;LD B,#81 + DEC A + JR Z,HDSTART + INC B ;LD B,#82 + DEC A + JR Z,HDSTART + INC B ;LD B,#83 + DEC A + JR Z,HDSTART + ; RAM + DEC A + JR Z,RDSTART + ; ROM + DEC A + JP Z,RECOVERYstart + ; Error + SCF + RET + ; +FDSTART: PUSH BC + PUSH BC + LD A,msgStrings.bootFdd + CALL POSTMSG + POP AF + CALL FDD_5x_RESET + POP BC + RET C + JR OS_LOAD + ; +CDSTART: LD A,B ; [ ] 15/02/2025 boot from ATAPI + OR DRIVE_CODES.SPRINTER.ATAPI + LD B,A + PUSH BC + LD A,msgStrings.bootCd + CALL POSTMSG + POP AF + PUSH AF + CALL PRINT_CHANEL + ; + POP BC + PUSH BC + CALL OS_LOAD + POP BC + RET NC + LD HL,2048 ;!HARDCODE sector size + LD IX,#0011 + JR OS_LOAD.CD + ; +RDSTART: LD A,msgStrings.bootRamDrv + CALL POSTMSG + LD B,DRIVE_CODES.SPRINTER.RAM ; 6 - тип драйва RAM-DRV, 0 - номер драйва +.loop: PUSH BC + CALL OS_LOAD + POP BC + INC B + LD A,DRIVE_CODES.SPRINTER.RAM + SYS_PAGE.RAMD_KEYS.NUM-1 ; максимальный номер рамдиска + SUB B + JR NC,.loop + RET -HDSTART: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD A,B +HDSTART: IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,B + ; + AND #03 ;R02 %00000011 + LD IY,IDE.INIT_TBL_IDE0 + JR Z,.next + ; + LD IY,IDE.INIT_TBL_IDE1 + CP 1 ;R02 + JR Z,.next + ; + LD IY,IDE.INIT_TBL_IDE2 ;R02 + CP 2 ;R02 + JR Z,.next + ; + LD IY,IDE.INIT_TBL_IDE3 ;R02 + ; +.next: LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + CP IDE.Device.ATAPI + JP Z,CDSTART + PUSH AF + PUSH BC + LD A,msgStrings.bootHdd + CALL POSTMSG + POP AF + PUSH AF + CALL PRINT_CHANEL + ; + POP BC + POP AF + CP #FF + SCF + RET Z + ; +OS_LOAD: LD HL,512 ;!HARDCODE + LD IX,#0001 +.CD: LD (.SectorSizeAddr),HL + LD HL,#0000 + LD DE,TEMP + LD A,B + LD BC,1*256 + BIOS.DRV_READ + PUSH AF + RST ToBIOS_18 + ; + POP BC + RET C + LD A,B + EX AF,AF' + LD HL,TEMP + LD DE,SYSID + LD B,SYSID.length +.loop: LD A,(DE) + CP (HL) + SCF + RET NZ + INC HL + INC DE + DJNZ .loop + EX AF,AF' + PUSH AF + LD A,msgStrings.bootOk + LD E,COLORS.CGA.INK.LGREEN + CALL POSTMSC + CALL ScreenPOS.CRLF + POP AF ; физический номер диска + POP HL +.MOVE0: DI + IM 1 + LD HL,MOVE1 + LD DE,OS_LOAD.SectorSizeAddr - MOVE1.length ; !HARDCODE + LD BC,MOVE1.length + LDIR + JP OS_LOAD.SectorSizeAddr - MOVE1.length + ; +MOVE1: LD HL,#8000 ; !HARDCODE + LD SP,HL + EX DE,HL + LD HL,TEMP + LD BC,(OS_LOAD.SectorSizeAddr) + LDIR + JP #8000+SYSID.length ;#800C ; !HARDCODE + ; +.length EQU $-MOVE1 - AND #03 ;R02 %00000011 - LD IY,IDE.INIT_TBL_IDE0 - JR Z,.next - LD IY,IDE.INIT_TBL_IDE1 - CP 1 ;R02 - JR Z,.next - - LD IY,IDE.INIT_TBL_IDE2 ;R02 - CP 2 ;R02 - JR Z,.next - - LD IY,IDE.INIT_TBL_IDE3 ;R02 -.next: LD A,(IY+IDE.HDD_INIT_TABLE.DriveType) - EX AF,AF' - OUT (SLOT3),A - EX AF,AF' - CP IDE.Device.CDROM - JP Z,CDSTART - PUSH AF - PUSH BC - LD A,msgStrings.bootHdd - CALL POSTMSG - POP BC - POP AF - CP #FF - SCF - RET Z -OS_LOAD: - LD HL,#0000 - LD IX,#0001 - LD DE,TEMP - LD A,B - LD BC,1*256 + BIOS.DRV_READ - PUSH AF - RST ToBIOS_18 - - POP BC - RET C - LD A,B - EX AF,AF' - LD HL,TEMP - LD DE,SYSID - LD B,SYSID.length -.loop: LD A,(DE) - CP (HL) - SCF - RET NZ - INC HL - INC DE - DJNZ .loop - EX AF,AF' - PUSH AF - LD A,msgStrings.bootOk - CALL POSTMSG - CALL ScreenPOS.CRLF - POP AF - POP HL -; JP MOVE0 -MOVE0: - DI - IM 1 - LD HL,MOVE1 - LD DE,#7C00 ; !HARDCODE - LD BC,MOVE1.length - LDIR - JP #7C00 -MOVE1: - LD SP,#7FFF ; !HARDCODE - LD HL,TEMP - LD DE,#8000 ; !HARDCODE - LD BC,#0200 ; !HARDCODE - LDIR - JP #8000+SYSID.length ;#800C ; !HARDCODE -.length EQU $-MOVE1 SYSID: DZ "Starting..." .length EQU $-SYSID -FD144A: DB #80,#12,#02,#50,#00,#00,#02,FDD_INI_TABLE.FDD -FD720A: DB #00,#09,#02,#50,#00,#00,#02,FDD_INI_TABLE.FDD -FINSTAL: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD HL,FDD_INI_TABLE.FDD_0 - LD BC,#20FF ;!HARDCODE table -FILLFDD: - LD (HL),C - INC HL - DJNZ FILLFDD - EX AF,AF' - OUT (SLOT3),A - LD BC,#0311 - CALL G_VALUE - LD HL,FD720A - OR A - JR Z,SETFD0 - LD HL,FD144A - DEC A - JR NZ,NOFDD0 -SETFD0: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD DE,FDD_INI_TABLE.FDD_0 - LD BC,#0008 ; !HARDCODE - LDIR - EX AF,AF' - OUT (SLOT3),A -NOFDD0: - LD BC,#0C11 - CALL G_VALUE - LD HL,FD720A - OR A - JR Z,SETFD1 - LD HL,FD144A - DEC A - JR NZ,NOFDD1 -SETFD1: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD DE,FDD_INI_TABLE.FDD_1 - LD BC,#0008 ; !HARDCODE - LDIR - EX AF,AF' - OUT (SLOT3),A -NOFDD1: - RET +;FD144A: DB #80,#12,#02,#50,#00,#00,#02,FDD_INIT_TABLE.FDD +; .Size EQU $ - FD144A +; FD720A: DB #00,#09,#02,#50,#00,#00,#02,FDD_INIT_TABLE.FDD +; .Size EQU $ - FD720A +FDD_INIT_TABLE: FDD_1440_TABLE +FDD_INSTAL: IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD HL,SYS_PAGE.FDD_TABLE + LD BC,SYS_PAGE.FDD_TABLE.Size*256 + #FF ; table_size*256 + fill_byte +.FILLFDD: LD (HL),C + INC HL + DJNZ .FILLFDD + ; + ;EX AF,AF' + ;OUT (SLOT3),A + ;LD BC,CMOS_CELL.DrivesSetup_1.Mask.FirstFDD ;#0311 + ;CALL GET_CMOS_VALUE + ;LD HL,FD720A + ;OR A + ;JR Z,.SETFD0 + LD HL,FDD_INIT_TABLE + ;DEC A + ;JR NZ,.NOFDD0 +;.SETFD0: ;IN A,(SLOT3) + ;EX AF,AF' + ;LD A,SYS_PAGE + ;OUT (SLOT3),A + LD DE,SYS_PAGE.FDD_TABLE + ; B=0 + LD C,SYS_PAGE.FDD_TABLE.Size + LDIR + ;EX AF,AF' + ;OUT (SLOT3),A +;.NOFDD0: LD BC,CMOS_CELL.DrivesSetup_1.Mask.SecondFDD ;#0C11 + ;CALL GET_CMOS_VALUE + ;LD HL,FD720A + ;OR A + ;JR Z,.SETFD1 + ;LD HL,FD144A + ;DEC A + ;JR NZ,.NOFDD1 +;.SETFD1: IN A,(SLOT3) + ;EX AF,AF' + ;LD A,SYS_PAGE + ;OUT (SLOT3),A + ;LD DE,SYS_PAGE.FDD_1_TABLE + ;LD BC,FD144A.Size + ;LDIR + EX AF,AF' + OUT (SLOT3),A +.NOFDD1: RET -AUTODET: - IN A,(SLOT3) - EX AF,AF' - LD A,SYS_PAGE - OUT (SLOT3),A - LD HL,IDE.INIT_TBL_IDE0 - LD BC,#20FF ;R02 ;!HARDCODE table -FILLIDE: - LD (HL),C ;CLEAR HDD VARIABLE - INC HL - DJNZ FILLIDE - EX AF,AF' - OUT (SLOT3),A - -;==== ;!!!!! старая нумерация дисков !!!!!==== - ; CALL GET_AVAILABLE_STRUCT - ; LD A,#00 - ; CALL COMMONIDE - - ; CALL GET_AVAILABLE_STRUCT - ; LD A,#01 - ; CALL COMMONIDE - - ; CALL GET_AVAILABLE_STRUCT - ; LD A,#02 - ; CALL COMMONIDE - - ; CALL GET_AVAILABLE_STRUCT - ; LD A,#03 - ; CALL COMMONIDE -;========================================== - - LD IY,IDE.INIT_TBL_IDE0 - LD A,#00 - CALL COMMONIDE - - LD IY,IDE.INIT_TBL_IDE1 - LD A,#01 - CALL COMMONIDE - - LD IY,IDE.INIT_TBL_IDE2 - LD A,#02 - CALL COMMONIDE - - LD IY,IDE.INIT_TBL_IDE3 - LD A,#03 - CALL COMMONIDE - - CALL ScreenPOS.CRLF - RET -; -;==== ;!!!!! старая нумерация дисков !!!!!==== -; GET_AVAILABLE_STRUCT -; LD C,SLOT3 -; IN B,(C) -; LD A,SYS_PAGE -; OUT (C),A -; CALL FIND_AVAILABLE_STRUCT -; OUT (C),B -; RET - -; FIND_AVAILABLE_STRUCT -; LD IY,IDE0 -; LD A,(IY+DTYPE_H) -; INC A -; RET Z -; LD IY,IDE1 -; LD A,(IY+DTYPE_H) -; INC A -; RET Z -; LD IY,IDE2 -; LD A,(IY+DTYPE_H) -; INC A -; RET Z -; LD IY,IDE3 -; LD A,(IY+DTYPE_H) -; INC A -; RET -;========================================== -; - -; !HARDCODE заменить числа на метки в этой процедуре -COMMONIDE: - AND A - LD H,A ;SAVE DRIVE NUMBER - LD BC,#3011 ;CMOS VALUE - LD L,msgStrings.detectIdePrMA - JR Z,COMMON2 - DEC A - LD BC,#C011 ;CMOS VALUE - LD L,msgStrings.detectIdePrSL - JR Z,COMMON2 - DEC A - -; !HARDCODE заменить числа на метки в этой процедуре - LD BC,#3020 - LD L,msgStrings.detectIdeSecMA - JR Z,COMMON2 - DEC A - LD BC,#C020 - LD L,msgStrings.detectIdeSecSL - JR Z,COMMON2 - SCF - RET - -;0 - AUTODETECT -;1 - GETTING FROM SETUP -;2 - CD-ROM -;3 - DISABLED - -COMMON2: - CALL G_VALUE - OR A - JP Z,AUTODETECT ;AUTODECECT - DEC A - JP Z,SETUPDETECT ;SETUP - DEC A - JP Z,IT_IS_CDROM ;CDROM - RET ;DON'T CHECK THIS DEVICE - -AUTODETECT: - PUSH HL - LD A,L ;DETECT MESSAGE - CALL POSTMSG - CALL ScreenPOS.SUBNAME -; - EI -; - POP HL - LD A,H ;RESTORE DRIVE NUMBER - CALL IDEAUTO -IDEJUMPBACK: - CALL NC,MODEL - LD A,(SKIP) - INC A - LD A,msgStrings.ideNone - JR Z,NOSKIPKEY - LD A,msgStrings.ideSkiped -NOSKIPKEY: - CALL C,POSTMSG - CALL ScreenPOS.CRLF - RET - -IT_IS_CDROM: - PUSH HL - LD A,L ;DETECT MESSAGE - CALL POSTMSG - CALL ScreenPOS.SUBNAME -; - EI -; - POP HL - LD A,H ;RESTORE DRIVE NUMBER - CALL IDE__CD - JP IDEJUMPBACK -; ????? посмотреть -PRIM_MASTER_CMOS_T: - DB M_CYLL,M_CYLH,M_HEAD,M_SECT -PRIM_SLAVE_CMOS_T: - DB S_CYLL,S_CYLH,S_HEAD,S_SECT -SEC_MASTER_CMOS_T: - DB SM_CYLL,SM_CYLH,SM_HEAD,SM_SECT -SEC_SLAVE_CMOS_T: - DB SS_CYLL,SS_CYLH,SS_HEAD,SS_SECT - -SETUPDETECT: - LD A,H - LD IX,PRIM_MASTER_CMOS_T - CP 0 - JR Z,SETUPD2 - LD IX,PRIM_SLAVE_CMOS_T - CP 1 - JR Z,SETUPD2 - LD IX,SEC_MASTER_CMOS_T - CP 2 - JR Z,SETUPD2 - LD IX,SEC_SLAVE_CMOS_T -SETUPD2: - CALL SELECT_IDE - LD HL,TEMP - LD DE,TEMP+1 - LD BC,511 - LD (HL),0 - LDIR - CALL WAITHDD - RET C - LD A,(IX+2) ;M_HEAD - CALL READCMS - LD (TEMP+#06),A ; !TODO сделать через структуру. HEADS PER TRACK - LD A,(IX+1) ;M_CYLH - CALL READCMS - PUSH AF - LD A,(IX+0) ;M_CYLL - CALL READCMS - POP HL - LD L,A - LD (TEMP+#02),HL ; !TODO сделать через структуру. CYLINDERS - LD A,(IX+3) ;M_SECT - CALL READCMS - LD (TEMP+#0C),A ; !TODO сделать через структуру. SECTOR PER TRACK - LD A,#A0 - LD BC,IDE.Write.DriveCtrl - OUT (C),A - LD A,IDE.Device.HDD - LD (IDEDEV),A - CALL IDESPEC - RET - -;ID_BUFFER: BLOCK #100,0 ;!HARDCODE ; !FIXIT уменьшить буфер или перенести? PIDNUM: LD HL,memBUFFER.ID LD BC,#00FF @@ -1377,33 +1263,74 @@ PIDNUM: LD HL,memBUFFER.ID CALL PRINTZ RET -PIDBOARD: - ;LD BC,1*256 + BIOS.FN_CRIPT - ;RST ToBIOS_18 - LD B,1 - CALL FN_CRIPT +PIDBOARD: CALL FN_CRIPT.board_id + ; + IF MotherBoardType > 0 + PUSH AF + ENDIF + PUSH DE + PUSH HL + PUSH BC + LD A,B + CALL PRNHEX + LD A,'-' + CALL PRINT_CHAR + POP BC + LD A,C + CALL PRNHEX + LD A,'-' + CALL PRINT_CHAR + POP HL + CALL IPRINT.Z + POP DE + PUSH DE + LD A,D + CALL PRNHEX + POP DE + LD A,E + IF MotherBoardType == 0 + JP PRNHEX + ELSE + CALL PRNHEX + LD A,' ' + CALL PRINT_CHAR + POP AF + ; type 0 - Classic + RET Z + ; type 1 - DX + LD HL,.ver_DX + DEC A + JP Z,PRINTZ + ; type 2 - DP + LD HL,.ver_DP + DEC A + JP Z,PRINTZ + ; type 3 - Max + LD HL,.ver_Max + DEC A + JP Z,PRINTZ + ; type 4 - test + LD HL,.Test + DEC A + JP Z,PRINTZ + RET + ; +.ver_DX: DZ "DX" +.ver_DP: DZ "DP" +.ver_Max: DZ "Max" +.Test DZ "0123456789A" + ENDIF - PUSH DE - PUSH HL - PUSH BC - LD A,B - CALL PRNHEX - LD A,'-' - CALL PRINT_CHAR - POP BC - LD A,C - CALL PRNHEX - LD A,'-' - CALL PRINT_CHAR - POP HL - CALL IZPRINT - POP DE - PUSH DE - LD A,D - CALL PRNHEX - POP DE - LD A,E - JP PRNHEX + +CNF_VER_PRINT: + LD HL,memBUFFER.ID + IFN BIOS.FN_VERSION.STR.BitstreamVer = 0 + LD BC,BIOS.FN_VERSION.STR.BitstreamVer*256 + XOR A +.loop: CPIR + DJNZ .loop + ENDIF + JP PRINTZ ;PIDNUM LD A,#0D ; LD HL,ID_BUFFER @@ -1412,13 +1339,13 @@ PIDBOARD: ; RET NZ ; INC HL ; LD BC,#0286 -; RST ToBIOS_18 +; RST_to_BIOS_18 ; INC HL ; LD BC,#0586 -; RST ToBIOS_18 +; RST_to_BIOS_18 ; INC HL ; LD BC,#0286 -; RST ToBIOS_18 +; RST_to_BIOS_18 ; XOR A ; RET @@ -1433,7 +1360,11 @@ PIDBOARD: ; RET NZ ; INC HL ; LD BC,#0A86 -; JP ToBIOS_18 +; JP_to_BIOS + +////////////////////////////////////////////////////////////////////// +; INCLUDE 'IM2_INT.asm' +////////////////////////////////////////////////////////////////////// PRNHEX: LD D,A RRCA @@ -1488,19 +1419,6 @@ PRNTIME: OUT (SLOT3),A RET -MODEL: LD HL,TEMP+27*2 ; !TODO сделать через структуру. - LD A,(HL) - OR A - JR Z,.unknown - LD B,20 - CALL DWPRINT - AND A - RET -.unknown: - LD A,msgStrings.ideUnknown - CALL POSTMSG - AND A - RET PMEMORY: ADD HL,HL @@ -1511,16 +1429,18 @@ PMEMORY: LD A,"K" JP PRINT_CHAR + IFUSED ZXCLS ZXCLS: LD HL,#4000 LD DE,#4001 LD BC,#1AFF LD (HL),L LDIR RET + ENDIF GET_ID: LD HL,memBUFFER.ID ;LD C,BIOS.FN_VERSION - ;JP ToBIOS_18 + ;JP_to_BIOS JP FN_VERSION @@ -1545,108 +1465,104 @@ GET_ID: LD HL,memBUFFER.ID ;R01 RET -RCHAIN: - LD E,L - LDI - DEC L - LD L,(HL) - INC L - RET Z - DEC L - JR RCHAIN +; COPY_CHAIN: LD E,L +; LDI +; DEC L +; LD L,(HL) +; INC L +; RET Z +; DEC L +; JR COPY_CHAIN -CCHAIN: - LD HL,MEMMAP2 - LD DE,#C200 - XOR A -CCHAINC: - CP (HL) - JR Z,NOCOPYC - LD E,L - LDI - DEC L -NOCOPYC: - INC L - JR NZ,CCHAINC - LD HL,TPOINTD - LD DE,SYS_PAGE.RAMD_KEYS - LD BC,SYS_PAGE.RAMD_KEYS.NUM - LDIR - RET +; ; Вход: HL - копия RAM_TABLE откуда копировать +; RESTORE_CHAINS: LD DE,SYS_PAGE.RAM_TABLE +; XOR A +; .loop: CP (HL) +; JR Z,.NoCopy +; LD E,L +; LDI +; DEC L +; .NoCopy: INC L +; JR NZ,.loop +; RET -TRQUICK: +;---------------------------------------------------------------[] ;REGISTER #1E -; %00000011 - TR DOS A: Default / FDD / HDD / RMD -; %00001100 - TR DOS B: Default / FDD / HDD / RMD -; %00110000 - TR DOS C: Default / FDD / HDD / RMD -; %11000000 - TR DOS D: Default / FDD / HDD / RMD - LD BC,#031E - LD A,0 - CALL TRDOSX - LD BC,#0C1E - LD A,1 - CALL TRDOSX - LD BC,#301E - LD A,2 - CALL TRDOSX - LD BC,#C01E - LD A,3 +; %0000'0011 - TR DOS A: Default / FDD / HDD / RMD +; %0000'1100 - TR DOS B: Default / FDD / HDD / RMD +; %0011'0000 - TR DOS C: Default / FDD / HDD / RMD +; %1100'0000 - TR DOS D: Default / FDD / HDD / RMD -TRDOSX: - ; PUSH AF - ; CALL G_VALUE - ; POP BC - ; OR A - ; RET Z - ; LD C,BIOS.FDD_TO_DRV - ; DEC A - ; JP Z,ToBIOS_18 - ; LD C,BIOS.HDD_TO_DRV - ; DEC A - ; JP Z,ToBIOS_18 - ; SCF - ; RET - PUSH AF - CALL G_VALUE - POP BC - OR A - RET Z - DEC A - JP Z,FDD_TO_DRV - DEC A - JP Z,HDD_TO_DRV - SCF - RET +TRD_MOUNT: LD BC,CMOS_CELL.TRDOSmount.Mask.A ;#031E + LD A,0 + CALL .TRDOSX + LD BC,CMOS_CELL.TRDOSmount.Mask.B ;#0C1E + LD A,1 + CALL .TRDOSX + LD BC,CMOS_CELL.TRDOSmount.Mask.C ;#301E + LD A,2 + CALL .TRDOSX + LD BC,CMOS_CELL.TRDOSmount.Mask.D ;#C01E + LD A,3 +.TRDOSX: ; PUSH AF + ; CALL GET_CMOS_VALUE + ; POP BC + ; OR A + ; RET Z + ; LD C,BIOS.FDD_TO_DRV + ; DEC A + ; JP Z,ToBIOS_18 + ; LD C,BIOS.HDD_TO_DRV + ; DEC A + ; JP Z,ToBIOS_18 + ; SCF + ; RET + PUSH AF + CALL GET_CMOS_VALUE + POP BC + OR A + RET Z + DEC A + JP Z,FDD_TO_DRV + DEC A + JP Z,HDD_TO_DRV + SCF + RET +;---------------------------------------------------------------[] -; открывает порт #FE на чтение в 3-й карте портов -; OPENDOS: -; DI -; IN A,(SLOT3) -; EX AF,AF' -; LD A,#40 -; OUT (SLOT3),A -; LD HL,#C000 -; LD DE,#F000 -; LD BC,#0400 -; LDIR -; LD A,#40 -; LD (#F26E),A -; LD (#F27E),A -; LD (#F2EE),A -; LD (#F2FE),A -; LD (#F36E),A -; LD (#F37E),A -; LD (#F3EE),A -; LD (#F3FE),A -; LD HL,#F000 -; LD DE,#F400 -; LD BC,#0C00 -; LDIR -; EX AF,AF' -; OUT (SLOT3),A -; RET +;!TODO посмотреть + ;открывает порт #FE на чтение в 3-й карте портов + ;OPENDOS: + ; DI + ; IN A,(SLOT3) + ; EX AF,AF' + ; LD A,#40 + ; OUT (SLOT3),A + ; LD HL,#C000 + ; LD DE,#F000 + ; LD BC,#0400 + ; LDIR + ; LD A,#40 + ; LD (#F26E),A + ; LD (#F27E),A + ; LD (#F2EE),A + ; LD (#F2FE),A + ; LD (#F36E),A + ; LD (#F37E),A + ; LD (#F3EE),A + ; LD (#F3FE),A + ; LD HL,#F000 + ; LD DE,#F400 + ; LD BC,#0C00 + ; LDIR + ; EX AF,AF' + ; OUT (SLOT3),A + ; RET ; + + + setFRAME: .double: LD HL,.dataDoubleAll @@ -1686,94 +1602,15 @@ ElementsBuffer: .DownCenter: BYTE "┴" ; DC - DownCenter .Size EQU $-ElementsBuffer ; -/* -SDOUBLE: - DB #C9 - DB #BB - DB #CD - DB #BA - DB #C8 - DB #BC - - DB #CC - DB #B9 - DB #CB - DB #CA - -SSINGLE: - DB #DA - DB #BF - DB #C4 - DB #B3 - DB #C0 - DB #D9 - - DB #C3 - DB #B4 - DB #C2 - DB #C1 - -SSIN_DW: - DB #C9 - DB #BB - DB #C4 - DB #BA - DB #C7 - DB #B6 - - DB #C7 - DB #B6 - DB #D1 - DB #C1 - -SSIN_UP: - DB #C7 - DB #B6 - DB #C4 - DB #BA - DB #C8 - DB #BC - - DB #C7 - DB #B6 - DB #C2 - DB #CF - -SSIN_AL: - DB #C7 - DB #B6 - DB #C4 - DB #BA - DB #C7 - DB #B6 - - DB #C7 - DB #B6 - DB #C2 - DB #C1 -; - -SELEM: -UL: DB #DA -UR: DB #BF -ZL: DB #C4 -VL: DB #B3 -LL: DB #C0 -LR: DB #D9 - -LC: DB #C3 -RC: DB #B4 -UC: DB #C2 -DC: DB #C1 -; -*/ - + IF STARTUP_SND + INCLUDE 'startup_sound.asm' + ENDIF INCLUDE 'VIDEO_IO.asm' INCLUDE 'AUTOIDE.asm' INCLUDE 'SETTINGS.asm' INCLUDE 'KEY.asm' ;....................................... -; + KEY: EI JP WAITKEY @@ -1782,29 +1619,15 @@ FindStringAddr: LD H,0 LD BC,memBUFFER.Messages ADD HL,HL - ADD HL,BC - LD A,(HL) - INC HL - LD H,(HL) - LD L,A - RET -/* -Get_Item_Address: - LD L,A - LD H,0 - LD BC,MSG_Buffer - ADD HL,HL ADD HL,BC LD A,(HL) INC HL LD H,(HL) - LD L,A - INC HL - INC HL + LD L,A RET -*/ + POSTLEN: - CALL FindStringAddr + CALL FindStringAddr LD BC,#0100 XOR A CPIR @@ -1818,53 +1641,213 @@ POSTLEN: ;JP ScreenPOS.LOCAT JP LP_SET_PLACE -POSTMSG: - CALL FindStringAddr - JP PRINTZ - -POSTMSC: - CALL FindStringAddr - LD A,E - JP CPRINTZ - -; SETLAND: - LD A,#0E ; !HARDCODE CMOS ячейка options - CALL READCMS - AND #04 ; !HARDCODE CMOS значение языка - JR NZ,.RUS - - LD HL,MSG_ENG - LD DE,memBUFFER.Messages - LD BC,MSG_ENG.size - LDIR - RET -.RUS: + LD A,#0E ; !HARDCODE CMOS ячейка options + CALL READCMS ;!TODO переделать на GET_CMOS_VALUE + AND #04 ; !HARDCODE CMOS значение языка LD HL,MSG_RUS - LD DE,memBUFFER.Messages - LD BC,MSG_RUS.size + JR NZ,.set + LD HL,MSG_ENG + ; +.set: LD DE,memBUFFER.Messages + LD BC,MSG_TABLE.Size LDIR RET -; ; +; print boot drive number +PRINT_CHANEL: AND #0F + LD C,A + ; + LD A,msgStrings.parPriIdeMA + JR Z,.print_chanel + ; + LD A,msgStrings.parPriIdeSl + DEC C + JR Z,.print_chanel + ; + LD A,msgStrings.parSecIdeMA + DEC C + JR Z,.print_chanel + ; + LD A,msgStrings.parSecIdeSl +.print_chanel: CALL FindStringAddr + ;CALL LP_GET_PLACE + ;LD A,ScreenPOS.SUBNAME.POS + ;SUB E + ;LD B,A + LD B,0 + LD D,#FF + JP LP_PRINT_LINE6 +; + +POSTMSC: CALL FindStringAddr + LD A,E + JP CPRINTZ +; +////////////////////////////////////////////////////////////////////// + INCLUDE 'IM2_INT.asm' +////////////////////////////////////////////////////////////////////// + +POSTMSG: CALL FindStringAddr + JP PRINTZ + + + +;----------------------------------------------------------------------[] +;!TODO сделать выбор в Setup, что грузить в vПЗУ при старте. Варианты: +;[x] 0 - Не грузить ПЗУ спектрума, инитить страницу #41 как в 3.04 +;[x] 1 - Грузит ПЗУ спектрума из ROM при старте если нет флага ZX +;[x] 2 - Грузит ПЗУ спектрума из ROM при каждом перезапуске +;[ ] 3 - Не грузить ПЗУ спектрума, инитить страницу #41 так, +; чтоб код в ней подгружал ПЗУ спектрума при обращении +ZXMODE_SETUP: IN A,(SLOT3) + PUSH AF + LD A,Spec_Page + OUT (SLOT3),A + ; + LD BC,CMOS_CELL.Options.Mask.LoadZXroms + CALL GET_CMOS_VALUE + ; + OR A + JR Z,.init_41h + DEC A + JR Z,.CheckAndLoad + DEC A + JR Z,.Load_ZXROMS + ;!TODO + ;DEC A + ;JR Z,.New_init_41h + ; + ; Check ZX ROMS Loaded +.CheckAndLoad: LD A,(Spec_Page.flag_Z) + CP 'Z' + JR NZ,.Load_ZXROMS + LD A,(Spec_Page.flag_X) + CP 'X' + JR NZ,.Load_ZXROMS + ; [x] 31/12/23 подстраховка от недоутечки памяти + LD A,R + AND #80 + JR Z,.No_Need_To_Load_ZXROMS +.Load_ZXROMS: XOR A + LD R,A + ; Load ZX ROM's + LD BC,64*256 + BIOS.ZX_MEMORY_MANAGER ; [ ] free zx pages! MANAGE_ZX_PAGES.FREE_vMEMORY + RST ToBIOS_18 + ; + LD B,3 ; !HARDCODE zx-rom number of pages + CALL EMM.GetMem + JR C,.init_41h ;!FIXIT печатать ошибку ; [ ] free zx pages! + CALL init_zx_roms + ; IFN FREE_ZX_PAGES + ; ; ставим метку если прогрузили ПЗУ спектрума + ; LD HL,'XZ' + ; LD (Spec_Page.flag_Z),HL + ; ENDIF ; +.No_Need_To_Load_ZXROMS: + POP AF + OUT (SLOT3),A + RET + ; +.init_41h: CALL init_zx_roms.init_41h + LD A,SYS_PAGE + OUT (SLOT3),A + CALL .Set_Page41 + ;!FIXIT установить во все vROM страницу #41 ; [ ] free zx pages! + JR .No_Need_To_Load_ZXROMS + ; +.Set_Page41: LD HL,SYS_PAGE.SHARED_BUFFER_256b + 11 + LD DE,SYS_PAGE.SHARED_BUFFER_256b + 11-1 + LD BC,11-1 ; !HARDCODE кол-во страниц vROM + RAM BLOCK ID + LD (HL),#FF + LDDR ; зачищаем + EX DE,HL + ; + ; LD A,SYS_PORT.EXTENSION + ; OUT (SYS_PORT.ROM),A + ; JP MANAGE_ZX_PAGES.INIT_vROM + ; XOR A ;LD A,SYS_PORT.BIOS + ; OUT (SYS_PORT.ROM),A + LD BC,128*256 + BIOS.ZX_MEMORY_MANAGER ; [ ] free zx pages! HARDCODE + JP ToBIOS_18 + ;RET +; +;--------------------[copy zx-roms to zx-pages]-----------------; +; SLOT0 - ROM 8, sys_port - on. +; RAM SLOT0 - page 0 +; RAM SLOT3 - Spec_Page +; для режима zx spectrum +; !HARDCODE номера страниц для эмулятора ПЗУ +init_zx_roms: DI + ; ;;;;;;;; + ; IF FREE_ZX_PAGES + ; ;;;;;;;; + ; НА ВХООДЕ A = SYS_PAGE.Block_ID.vROM + ; добиваем буфер до 11 байтов пустыми страницами + ; в буфер упадут 1 RAM BLOCK ID, 3 страницы для vROM и #FF + LD HL,#FFFF + LD (memBUFFER.Shared + 5),HL ; !HARDCODE zx-rom number of pages + LD (memBUFFER.Shared + 7),HL ; !HARDCODE zx-rom number of pages + LD (memBUFFER.Shared + 9),HL ; !HARDCODE zx-rom number of pages + ; получаем список страниц для vROM + LD HL,memBUFFER.Shared + LD (HL),A + INC HL + LD B,A + CALL EMM.GetMemBlkPages + ; + LD A,SYS_PAGE + OUT (SLOT3),A + ; устанавливаем номера страниц vROM в порты ALTERA + DEC HL + LD A,ROM.EXTENSION + OUT (SYS_PORT.ROM),A + CALL MANAGE_ZX_PAGES.INIT_vROM + ; Копируем образы ZX-ROM из ПЗУ в страницы vROM + LD A,2 ; !HARDCODE + LD BC,+(3*2)*256 + SLOT3 ; !HARDCODE B = (zx-rom number of pages)*2 + LD HL,memBUFFER.Shared + 1 +.loop: OUTI + OUT (ROM.SLOT0),A + EXX + LD HL,0 + LD DE,#C000 + LD BC,#4000 + LDIR + EXX + INC A + DJNZ .loop + ; возвращаем страницы на место + XOR A + OUT (ROM.SLOT0),A + OUT (SYS_PORT.ROM),A + LD A,Spec_Page + OUT (SLOT3),A +.init_41h: ; забить FF-ами + LD HL,#C000 + LD DE,#C001 + LD BC,#3FFF - 2 + LD (HL),#FF + LDIR + ; Заглушка для страницы #41 + LD HL,PROG_NO_ROM + LD DE,#C000 + Spec_Page.no_zx_rom + LD BC,PROG_NO_ROM.size + LDIR + ; + LD HL,RAM_BIOS_PROG + LD DE,#C000 + Spec_Page.to_bios + LD BC,RAM_BIOS_PROG.Length + LDIR + RET +;---------------------------------------------------------------------[] + + ;--------------------------------------- INCLUDE 'src/bios/ROM/SETUP/messages.z80' ;--------------------------------------- ; -/* -MSG_Buffer_Length EQU MSG_ENG_END-MSG_ENG - -STACK EQU $+128 -MSG_Buffer EQU STACK+2 -TMP_BUFFER EQU MSG_Buffer+MSG_Buffer_Length - - - IF TMP_BUFFER+1024 > #C000 - DISPLAY 'Page limit exceeded by: ',/A,$-#C000 - ASSERT TMP_BUFFER+1024 > #C000 - ENDIF -*/ STRUCT MAIN_BUFFERS ID BLOCK #100 @@ -1876,14 +1859,10 @@ End BYTE memBUFFER MAIN_BUFFERS = $ STACK EQU #C000 -.size EQU 128 +.Size EQU 128 -; ID_BUFFER EQU $ -; MSG_Buffer EQU ID_BUFFER+#100 -; TMP_BUFFER EQU MSG_Buffer + MSG_ENG.size - - IF memBUFFER.End-1 > #C000-STACK.size + IF memBUFFER.End-1 > #C000-STACK.Size DISPLAY 'memBUFFER.Shared overlaps STACK by: ',/A,(memBUFFER.End-1)-(#C000-STACK.size) ASSERT memBUFFER.End-1 < #C000-STACK.size ENDIF @@ -1897,11 +1876,83 @@ STACK EQU #C000 INCLUDE 'src/bios/logo/Set_Pictures.asm' DISPLAY '-----[Set_Pictures Prebuild done ]-----' ELSE - DISPLAY '------------------[Main.asm]------------------' - DISPLAY 'End code address: ',/A,$-1 - DISPLAY 'Code size: ',/A,$-COMPILE_ADDR.MAIN - DISPLAY 'End buffers address: ',/A,memBUFFER.End-1 - DISPLAY 'Free memory: ',/A,#C000-(memBUFFER.End-1)-STACK.size - DISPLAY 'Unused bytes before INT_POINTER: ',/A,INT_POINTER-before_intPointer +MAIN_END_CODE_ADDRESS EQU $-1 + ; DISPLAY ' -------------------[Main.asm]-------------------' + ; DISPLAY 'End code address: ',/A,$-1 + ; DISPLAY 'Code size: ',/A,$-COMPILE_ADDR.MAIN + ; DISPLAY 'End buffers address: ',/A,memBUFFER.End-1 + ; DISPLAY 'Free memory: ',/A,#C000-(memBUFFER.End-1)-STACK.Size + ; DISPLAY 'Unused bytes before INT_POINTER: ',/A,INT_POINTER-before_intPointer ENDIF -; \ No newline at end of file +; + + + +;======================================================================================================================= + +; ;;;;;;;; +; ELSE +; ;;;;;;;; +; IN A,(SLOT3) +; EX AF,AF' +; ; +; LD A,SYS_PORT.EXTENSION +; OUT (SYS_PORT.ROM),A +; INC A ; !HARDCODE LD A,2 +; LD B,3 ; !HARDCODE zx-rom number of pages +; ; +; .loop: EXX +; ; +; OUT (ROM.SLOT0),A +; OR %0100'0000 ; !HARDCODE номера страниц для эмулятора ПЗУ +; OUT (SLOT3),A +; AND %1011'1111 ; !HARDCODE номера страниц для эмулятора ПЗУ +; ; +; LD HL,0 +; LD DE,#C000 +; LD BC,#4000 +; LDIR +; ; +; INC A +; EXX +; DJNZ .loop +; ; +; XOR A +; OUT (ROM.SLOT0),A +; OUT (SYS_PORT.ROM),A +; EX AF,AF' +; OUT (SLOT3),A +; ; +; ;[x] SET_PORTS: no need to call from #3D13 and DI. 31/12/23 +; [ ] free zx pages! переделать на вызов FREE_ZX_PAGES.INIT_vROM +; LD A,ACEX.vROM.BASIC_128 ; ROM-ID - BASIC 128 +; LD B,#42 ;!HARDCODE page +; CALL SET_PORTS +; ; +; LD A,ACEX.vROM.BASIC_48 ; ROM-ID - BASIC 48 +; LD B,#43 ;!HARDCODE page +; CALL SET_PORTS +; ; +; LD A,ACEX.vROM.TR_DOS ; ROM-ID - TR-DOS +; LD B,#44 ;!HARDCODE page +; CALL SET_PORTS +; ; +; ; эти страницы пока не используются +; LD A,ACEX.vROM.EXPANSION ; ROM-ID - BIOS +; ;LD B,#45 ;!HARDCODE page +; LD B,#41 +; CALL SET_PORTS +; ; +; LD A,ACEX.vROM.BIOS_1 ; ROM-ID - BIOS-1 +; ;LD B,#46 ;!HARDCODE page +; LD B,#41 +; CALL SET_PORTS +; ; +; LD A,ACEX.vROM.BIOS_2 ; ROM-ID - BIOS-2 +; ;LD B,#47 ;!HARDCODE page +; LD B,#41 +; CALL SET_PORTS +; ; можно задействовать ещё 4 страницы на порты #E4..#E7 +; ;;;;;;;; +; ENDIF +; ;;;;;;;; \ No newline at end of file diff --git a/src/bios/rom/SETUP/PITEM_OLD.as b/src/bios/rom/SETUP/PITEM_OLD.as deleted file mode 100644 index 2e863fb..0000000 --- a/src/bios/rom/SETUP/PITEM_OLD.as +++ /dev/null @@ -1,32 +0,0 @@ -;--------------------------------------- -PITEM: -; HL - item's address - LD E,(HL) ; x-coordinate - INC HL - LD D,(HL) ; y-coordinate - INC HL ; address of next parametr - CALL LOCAT ; set position of item - CALL PRINTZ ; print item's name - LD A,(HL) ; address of next parametr - CALL READCMS ; read item`s value from cmos - INC HL - LD B,(HL) ; item's value mask - INC HL - INC HL - AND B -RRLP: - RRCA - RRC B - JR NC,RRLP - RLCA - OR A - JP Z,PRINTZ - LD B,A - XOR A -NIT: - LD C,#FF - CPIR - RET NZ - DJNZ NIT - JP PRINTZ -;--------------------------------------- \ No newline at end of file diff --git a/src/bios/rom/SETUP/SETTINGS.asm b/src/bios/rom/SETUP/SETTINGS.asm index fab5e36..ff06cd2 100644 --- a/src/bios/rom/SETUP/SETTINGS.asm +++ b/src/bios/rom/SETUP/SETTINGS.asm @@ -1,16 +1,14 @@ ;U_SETUP: SETTINGS: - LD A,#1A ; !HARDCODE + LD A,CMOS_CELL.ScreenSET CALL READCMS - AND #0F + AND high CMOS_CELL.ScreenSET.Mask.ColorStyle LD L,A CALL CSET LD DE,0 LD HL,#2050 LD A,(NORCLR) LD B,A - ;LD C,BIOS.LP_CLS_WIN - ;RST ToBIOS_18 CALL LP_CLS_WIN @@ -40,7 +38,7 @@ SETTINGS: LD DE,#0602 LD BC,#134C - CALL PBORDER + CALL PBORDER ;!FIXIT CALL setFRAME.single @@ -190,7 +188,7 @@ DEF_VAL: ;--------------------------------------- RestartSetup: ;setXYpos - CALL RESCREEN + CALL XY_SCREEN ;setLang CALL SETLAND ;setVsinc @@ -250,16 +248,15 @@ DECITM: JP PCURSOR CCHANGE: - LD A,#1A + LD A,CMOS_CELL.ScreenSET CALL READCMS INC A - AND #0F + AND high CMOS_CELL.ScreenSET.Mask.ColorStyle LD L,A LD B,A - LD A,#1A + LD A,CMOS_CELL.ScreenSET CALL WRITCMS -CSET: - LD H,0 +CSET: LD H,0 LD DE,STYLES ADD HL,HL ADD HL,HL @@ -270,7 +267,8 @@ CSET: LDI LDI CALL FSCREEN -REFRESH: + ; + ;REFRESH: LD BC,SettingsItemsTabsAddrs.max*256 LD A,(ITEM) PUSH AF @@ -371,14 +369,10 @@ FSCREEN: HALT FSC1: PUSH DE - ;LD C,BIOS.LP_SET_PLACE - ;RST ToBIOS_18 CALL LP_SET_PLACE LD A,(NORCLR) LD E,A - ;LD BC,#50*256+BIOS.LP_PRINT_ATR ;#5083 - ;RST ToBIOS_18 LD B,#50 CALL LP_PRINT_ATR @@ -392,10 +386,10 @@ FSC1: ITEM: DB #00 ITEM_Restore: DB #00 -NORCLR: DB #1F -HLTCLR: DB #1E -CURCLR: DB #4F -WRMCLR: DB #1F +NORCLR: DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.WHITE +HLTCLR: DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.YELLOW +CURCLR: DB COLORS.CGA.PAPER.RED + COLORS.CGA.INK.WHITE +WRMCLR: DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.WHITE ;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\-[v] @@ -551,7 +545,7 @@ PITEM: LD E,(IY+MenusItem.Column) ; x-coor JR NZ,.printParameter ; если это не строка с изменяемым параметром, то просто печать LD A,(IY+MenusItem.CMOSreg) ; address of next parametr - CALL READCMS ; read item`s value from cmos + CALL READCMS ; read item`s value from cmos LD B,(IY+MenusItem.ValueMask) ; item's value mask AND B @@ -572,14 +566,13 @@ PITEM: LD E,(IY+MenusItem.Column) ; x-coor jp POSTMSG ELSE -; !FIXIT вызовы процедур биоса надеются на то, что некоторые регистры не портятся +; вызовы процедур биоса надеются на то, что некоторые регистры не портятся ; HL - item's address PITEM: LD E,(HL) ; x-coordinate INC HL LD D,(HL) ; y-coordinate INC HL ; address of next parametr PUSH HL - ;CALL ScreenPOS.LOCAT CALL LP_SET_PLACE ; set position of item LD A,(HL) CALL POSTMSG @@ -610,37 +603,46 @@ PITEM: LD E,(HL) ; x-coordinate ENDIF ;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\-[^] -G_VALUE: +; Не портит HL +GET_CMOS_VALUE: PUSH BC LD A,C CALL READCMS POP BC AND B -RRLPX: - RRCA +.loop: RRCA RRC B - JR NC,RRLPX + JR NC,.loop RLCA RET -READCMS: - LD D,high CMOSARE - LD E,A - LD A,(DE) - RET +; [x] чтоб не влезло куда не надо +READCMS: LD D,high CMOSARE + LD E,A + CP CMOS.USED_MAX_ADDRESS+1 + JR NC,.error + LD A,(DE) + RET + ; +.error: SCF + RET +; [x] чтоб не влезло куда не надо WRITCMS: LD D,high CMOSARE LD E,A + CP CMOS.USED_MAX_ADDRESS+1 + JR NC,.error LD A,B LD (DE),A + RET +.error: SCF RET CHEKSUM: - LD BC,DEFVAL.Length*256+#000E - LD H,#DE -CHSUM1: - LD A,C + LD BC,DEFVAL.Size*256 + CMOS.USED_MIN_ADDRESS + LD H,#DE ;!HARDCODE +.loop: LD A,C CALL READCMS LD L,A LD A,H @@ -649,79 +651,70 @@ CHSUM1: SUB L LD H,A INC C - DJNZ CHSUM1 + DJNZ .loop RET -TCHEKSM: +TEST_CHECKSUM: CALL CHEKSUM - LD A,#3F + LD A,CMOS_CELL.CheckSum CALL READCMS CP H RET ; TSTCMOS: ; LD C,BIOS.CMOS_TEST -; JP ToBIOS_18 +; JP_to_BIOS ; RDCMOS: ; LD C,BIOS.CMOS_RD -; JP ToBIOS_18 +; JP_to_BIOS ; WRCMOS: ; LD C,BIOS.CMOS_WR -; JP ToBIOS_18 +; JP_to_BIOS READING: - LD D,#0E ; !HARDCODE CMOS -.loop: - PUSH DE - - ;CALL RDCMOS + LD D,CMOS.USED_MIN_ADDRESS +.loop: PUSH DE CALL CMOS_RD - POP DE LD H,high CMOSARE LD L,D LD (HL),A - LD A,#40 ; !HARDCODE CMOS + LD A,CMOS.USED_MAX_ADDRESS+1 INC D CP D JR NZ,.loop RET -WRITING: - CALL CHEKSUM - LD B,H - LD A,#3F - CALL WRITCMS - LD D,#0E ; !HARDCODE CMOS -.loop: - LD H,high CMOSARE - LD L,D - LD A,(HL) - PUSH DE - - ;CALL WRCMOS - CALL CMOS_WR - - POP DE - LD A,#40 ; !HARDCODE CMOS - INC D - CP D - JR NZ,.loop - RET +WRITING: CALL CHEKSUM + LD B,H + LD A,CMOS.Cell.CheckSum + CALL WRITCMS + LD D,CMOS.USED_MIN_ADDRESS +.loop: LD H,high CMOSARE + LD L,D + LD A,(HL) + PUSH DE + CALL CMOS_WR + POP DE + LD A,CMOS.USED_MAX_ADDRESS+1 + INC D + CP D + JR NZ,.loop + RET SETDEFX: - LD A,#FF + LD A,#FF LD (ERRSUM),A CALL SETDEF JP WRITING SETDEF: ;!TODO может бахнуть LDIRом? посмотреть LD HL,DEFVAL - LD C,DEFVAL.Length - LD A,#0E ; !HARDCODE CMOS cмещение в таблице до ячеек памяти + LD C,DEFVAL.Size + LD A,CMOS.USED_MIN_ADDRESS .loop: LD B,(HL) INC HL @@ -731,143 +724,108 @@ SETDEF: ;!TODO INC A DEC C JR NZ,.loop -;REGISTER #35 - BASIC SETTING 1 - LD A,#35 - LD B,#00 + + LD A,CMOS_CELL.HardwareConfiguration ; не используется + LD B,0 CALL WRITCMS -;REGISTER #36 - BASIC SETTING 2 - LD A,#36 - LD B,#00 + + LD A,CMOS_CELL.QuickStartSetUp + LD B,CMOS_CELL.QuickStartSetUp.ZxRom.Basic128 CALL WRITCMS CALL CHEKSUM LD B,H - LD A,#3F + LD A,CMOS_CELL.CheckSum CALL WRITCMS RET ;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\-[v] - IF NEW_FEATURE ; New procedure with IY reg + IF NEW_FEATURE Get_Item_Address: - LD A,(ITEM) - LD L,A - LD H,0 - LD DE,SettingsItemsTabsAddrs - ADD HL,HL - ADD HL,DE - LD A,(HL) - INC HL - LD H,(HL) - LD L,A - PUSH HL - POP IY - RET - ELSE + LD A,(ITEM) + LD L,A + LD H,0 + LD DE,SettingsItemsTabsAddrs + ADD HL,HL + ADD HL,DE + LD A,(HL) + INC HL + LD H,(HL) + LD L,A + PUSH HL + POP IY + RET + + ELSE Get_Item_Address: - LD A,(ITEM) - LD L,A - LD H,0 - LD DE,SettingsItemsTabsAddrs - ADD HL,HL - ADD HL,DE - LD A,(HL) - INC HL - LD H,(HL) - LD L,A - INC HL - INC HL - RET - ENDIF + LD A,(ITEM) + LD L,A + LD H,0 + LD DE,SettingsItemsTabsAddrs + ADD HL,HL + ADD HL,DE + LD A,(HL) + INC HL + LD H,(HL) + LD L,A + INC HL + INC HL + RET + ENDIF ;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\-[^] ; MODULE OnChangeAction nothing: ret - IF NEW_FEATURE + + ; !TODO New Feature + ; !TODO замутить что-то типа API для рисования всплывающих окон + IF NEW_FEATURE SetTime: -; !TODO New Feature -; !TODO замутить что-то типа API для рисования всплывающих окон - xor a - ld hl,#050E - ld de,#0C20 - ld ix,memBUFFER.Shared - ;ld c,BIOS.WIN_COPY - ;RST ToBIOS_18 - CALL WIN_COPY + xor a + ld hl,#050E + ld de,#0C20 + ld ix,memBUFFER.Shared + CALL WIN_COPY - LD DE,#0C20 ; !HARDCODE - ld b,5 - DI + LD DE,#0C20 ; !HARDCODE + ld b,5 + DI -.loop: push bc - push de - ;CALL ScreenPOS.LOCAT - CALL LP_SET_PLACE - ; печать атрибутов - LD E,COLORS.INC.RED - ;LD BC,#0E * 256 + BIOS.LP_PRINT_ATR - ;RST ToBIOS_18 - LD B,#0E - CALL LP_PRINT_ATR +.loop: push bc + push de + CALL LP_SET_PLACE + ; печать атрибутов + LD E,COLORS.CGA.INK.RED + LD B,#0E + CALL LP_PRINT_ATR - pop de - inc d - pop bc - DJNZ .loop + pop de + inc d + pop bc + DJNZ .loop - CALL setFRAME.single - LD DE,#0C20 ;yx. y=0..1F, x=0..4F координаты левого верхнего угла - LD BC,#050E ;yx. длина и высота линии - CALL PBORDER + CALL setFRAME.single + LD DE,#0C20 ;yx. y=0..1F, x=0..4F координаты левого верхнего угла + LD BC,#050E ;yx. длина и высота линии + CALL PBORDER -;------------------[v] -; ВОТ ТУТ КОД - ; DISPLAY '---------------------Delete me!!!---------------------' - ; DISPLAY /A, $ - ; DISPLAY '------------------------------------------------------' -; for tests - ; ld hl,#c000 - ; ld de,319 - ; ld b,2 - ; ld a,1 - ; ex af,af' - ; ld a,#46 - ; ex af,af' - ; ld c,BIOS.BLK_RD_WR - ; rst ToBIOS_18 -;------------------[^] + CALL KEY + xor a + ld hl,#050E + ld de,#0C20 + ld ix,memBUFFER.Shared + JP WIN_RESTORE + ENDIF - CALL KEY - xor a - ld hl,#050E - ld de,#0C20 - ld ix,memBUFFER.Shared - ;ld c,BIOS.WIN_RESTORE - ;JP ToBIOS_18 - ;RET - JP WIN_RESTORE - - ENDIF setXYpos: - JP RESCREEN -; setVsinc: -; ld a,@CMOS.Cell.ScreenSET -; call READCMS -; and @CMOS.Cell.ScreenSET.Mask.Sinc -; SCF -; jr z,.skip ;320 -; SLA A -; .skip: ld a,128+7 ;312 -; jr nc,.set -; dec a ;320 -; .set: -; ld c,BIOS.FN_SYNC -; jp ToBIOS_18 + JP XY_SCREEN + setVsinc: - ld a,@CMOS.Cell.ScreenSET + ld a,CMOS_CELL.ScreenSET call READCMS - and @CMOS.Cell.ScreenSET.Mask.Sinc + and high CMOS_CELL.ScreenSET.Mask.Sinc SCF jr z,.skip ;320 SLA A @@ -882,9 +840,9 @@ setLang: ld (ITEM_Restore),a pop hl ; delete return adress from stack jp SETTINGS -setInt: ld a,@CMOS.Cell.ScreenSET +setInt: ld a,CMOS_CELL.ScreenSET call READCMS - and @CMOS.Cell.ScreenSET.Mask.Int + and high CMOS_CELL.ScreenSET.Mask.Int jr nz,.skipDefaultInt ld a,2 ; Pentagon sync - default jr .set @@ -894,16 +852,10 @@ setInt: ld a,@CMOS.Cell.ScreenSET SRA A SRA A SRA A ; byte %00xx0000 --> %000000xx -.set: ;ld c,BIOS.FN_SYNC - ;rst ToBIOS_18 - CALL FN_SYNC +.set: CALL FN_SYNC LD IX,win_descriptor.tab80x32 - LD HL,#0000 - LD E,1 - ;LD C,BIOS.WIN_OPEN - ;RST ToBIOS_18 - CALL WIN_OPEN + CALL WIN_OPEN.SCR1 ld a,(ITEM) ld (ITEM_Restore),a @@ -911,9 +863,12 @@ setInt: ld a,@CMOS.Cell.ScreenSET jp SETTINGS ENDMODULE ; -MEMTEST EQU #80 -SAVERAM EQU #40 -EXTBIOS EQU #20 +;-----------------------------------------------------------------------; +;!FIXIT прибраться тут +SETBOOTSOUND EQU high CMOS_CELL.BootUpParams.Mask.BootSound +MEMTEST EQU high CMOS_CELL.BootUpParams.Mask.MemTest +SAVERAM EQU high CMOS_CELL.BootUpParams.Mask.SaveRAMdisks +EXTBIOS EQU high CMOS_CELL.BootUpParams.Mask.UpdBios SDELAY2 EQU #10 SDELAY1 EQU #08 @@ -941,6 +896,7 @@ SDIDE2 EQU #03 SDRAM EQU #04 ASDFDD1 EQU #00 ASDFDD2 EQU #10 +ASDRECOVERY EQU #70 ASDIDE1 EQU #20 ASDIDE2 EQU #30 ASDRAM EQU #40 @@ -970,237 +926,167 @@ TRD48 EQU #04 BAS48 EQU #05 REBOOTM EQU #02 HDDWP EQU #01 +;-----------------------------------------------------------------------; STYLES: ; Color Style 0 - DB COLORS.PAPER.BLUE + COLORS.INC.WHITE - DB COLORS.PAPER.BLUE + COLORS.INC.YELLOW - DB COLORS.PAPER.RED + COLORS.INC.WHITE - DB COLORS.PAPER.BLUE + COLORS.INC.WHITE + DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.YELLOW + DB COLORS.CGA.PAPER.RED + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.WHITE ; Color Style 1 - DB COLORS.PAPER.BLUE + COLORS.INC.LGREEN - DB COLORS.PAPER.BLUE + COLORS.INC.LMAGENT - DB COLORS.PAPER.MAGENTA + COLORS.INC.WHITE - DB COLORS.PAPER.BLUE + COLORS.INC.WHITE + DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.LGREEN + DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.LMAGENT + DB COLORS.CGA.PAPER.MAGENTA + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.WHITE ; Color Style 2 - DB COLORS.PAPER.GREEN + COLORS.INC.LCYAN - DB COLORS.PAPER.GREEN + COLORS.INC.YELLOW - DB COLORS.PAPER.CYAN + COLORS.INC.BLACK - DB COLORS.PAPER.GREEN + COLORS.INC.BLACK + DB COLORS.CGA.PAPER.GREEN + COLORS.CGA.INK.LCYAN + DB COLORS.CGA.PAPER.GREEN + COLORS.CGA.INK.YELLOW + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.BLACK + DB COLORS.CGA.PAPER.GREEN + COLORS.CGA.INK.BLACK ; Color Style 3 - DB COLORS.PAPER.CYAN + COLORS.INC.BLACK - DB COLORS.PAPER.CYAN + COLORS.INC.YELLOW - DB COLORS.PAPER.GREEN + COLORS.INC.BLACK - DB COLORS.PAPER.CYAN + COLORS.INC.LGREEN + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.BLACK + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.YELLOW + DB COLORS.CGA.PAPER.GREEN + COLORS.CGA.INK.BLACK + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.LGREEN ; Color Style 4 - DB COLORS.PAPER.CYAN + COLORS.INC.WHITE - DB COLORS.PAPER.CYAN + COLORS.INC.BLACK - DB COLORS.PAPER.LGRAY + COLORS.INC.BLUE - DB COLORS.PAPER.CYAN + COLORS.INC.YELLOW + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.BLACK + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.BLUE + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.YELLOW ; Color Style 5 - DB COLORS.PAPER.CYAN + COLORS.INC.BLACK - DB COLORS.PAPER.CYAN + COLORS.INC.BROWN - DB COLORS.PAPER.BROWN + COLORS.INC.LGRAY - DB COLORS.PAPER.CYAN + COLORS.INC.WHITE + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.BLACK + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.BROWN + DB COLORS.CGA.PAPER.BROWN + COLORS.CGA.INK.LGRAY + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.WHITE ; Color Style 6 - DB COLORS.PAPER.RED + COLORS.INC.YELLOW - DB COLORS.PAPER.RED + COLORS.INC.WHITE - DB COLORS.PAPER.BLACK + COLORS.INC.GREEN - DB COLORS.PAPER.RED + COLORS.INC.GREEN + DB COLORS.CGA.PAPER.RED + COLORS.CGA.INK.YELLOW + DB COLORS.CGA.PAPER.RED + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.GREEN + DB COLORS.CGA.PAPER.RED + COLORS.CGA.INK.GREEN ; Color Style 7 - DB COLORS.PAPER.RED + COLORS.INC.LGRAY - DB COLORS.PAPER.RED + COLORS.INC.WHITE - DB COLORS.PAPER.BLUE + COLORS.INC.WHITE - DB COLORS.PAPER.RED + COLORS.INC.WHITE + DB COLORS.CGA.PAPER.RED + COLORS.CGA.INK.LGRAY + DB COLORS.CGA.PAPER.RED + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.BLUE + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.RED + COLORS.CGA.INK.WHITE ; Color Style 8 - DB COLORS.PAPER.MAGENTA + COLORS.INC.LCYAN - DB COLORS.PAPER.MAGENTA + COLORS.INC.LGREEN - DB COLORS.PAPER.LGRAY + COLORS.INC.BLACK - DB COLORS.PAPER.MAGENTA + COLORS.INC.WHITE + DB COLORS.CGA.PAPER.MAGENTA + COLORS.CGA.INK.LCYAN + DB COLORS.CGA.PAPER.MAGENTA + COLORS.CGA.INK.LGREEN + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.BLACK + DB COLORS.CGA.PAPER.MAGENTA + COLORS.CGA.INK.WHITE ; Color Style 9 - DB COLORS.PAPER.MAGENTA + COLORS.INC.WHITE - DB COLORS.PAPER.MAGENTA + COLORS.INC.YELLOW - DB COLORS.PAPER.GREEN + COLORS.INC.BLUE - DB COLORS.PAPER.MAGENTA + COLORS.INC.LRED + DB COLORS.CGA.PAPER.MAGENTA + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.MAGENTA + COLORS.CGA.INK.YELLOW + DB COLORS.CGA.PAPER.GREEN + COLORS.CGA.INK.BLUE + DB COLORS.CGA.PAPER.MAGENTA + COLORS.CGA.INK.LRED ; Color Style 10 - DB COLORS.PAPER.LGRAY + COLORS.INC.BLACK - DB COLORS.PAPER.LGRAY + COLORS.INC.RED - DB COLORS.PAPER.CYAN + COLORS.INC.WHITE - DB COLORS.PAPER.LGRAY + COLORS.INC.WHITE + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.BLACK + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.RED + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.WHITE ; Color Style 11 - DB COLORS.PAPER.LGRAY + COLORS.INC.BLUE - DB COLORS.PAPER.LGRAY + COLORS.INC.YELLOW - DB COLORS.PAPER.MAGENTA + COLORS.INC.WHITE - DB COLORS.PAPER.LGRAY + COLORS.INC.WHITE + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.BLUE + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.YELLOW + DB COLORS.CGA.PAPER.MAGENTA + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.WHITE ; Color Style 12 - DB COLORS.PAPER.LGRAY + COLORS.INC.LGREEN - DB COLORS.PAPER.LGRAY + COLORS.INC.LCYAN - DB COLORS.PAPER.GREEN + COLORS.INC.WHITE - DB COLORS.PAPER.LGRAY + COLORS.INC.WHITE + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.LGREEN + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.LCYAN + DB COLORS.CGA.PAPER.GREEN + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.WHITE ; Color Style 13 - DB COLORS.PAPER.BLACK + COLORS.INC.LGREEN - DB COLORS.PAPER.BLACK + COLORS.INC.LCYAN - DB COLORS.PAPER.CYAN + COLORS.INC.YELLOW - DB COLORS.PAPER.BLACK + COLORS.INC.YELLOW + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.LGREEN + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.LCYAN + DB COLORS.CGA.PAPER.CYAN + COLORS.CGA.INK.YELLOW + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.YELLOW ; Color Style 14 (Mono) - DB COLORS.PAPER.BLACK + COLORS.INC.LGRAY - DB COLORS.PAPER.BLACK + COLORS.INC.WHITE - DB COLORS.PAPER.LGRAY + COLORS.INC.BLACK - DB COLORS.PAPER.BLACK + COLORS.INC.LGRAY + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.LGRAY + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.WHITE + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.BLACK + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.LGRAY ; Color Style 15 - DB COLORS.PAPER.BLACK + COLORS.INC.LMAGENT - DB COLORS.PAPER.BLACK + COLORS.INC.LGREEN - DB COLORS.PAPER.LGRAY + COLORS.INC.RED - DB COLORS.PAPER.BLACK + COLORS.INC.RED + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.LMAGENT + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.LGREEN + DB COLORS.CGA.PAPER.LGRAY + COLORS.CGA.INK.RED + DB COLORS.CGA.PAPER.BLACK + COLORS.CGA.INK.RED -DEFVAL: DB SAVERAM+EXTBIOS+SDELAY1 ;X0E - OPTIONS - DB TDL250+TRATE30 ;X0F - KEYBOARD - DB SDIDE1+ASDFDD2 ;X10 - SYSTEM DISKS - DB FD1720+FD2720+HD1AUTO+HD2AUTO ;X11 - FDD & Primary HDD's - DB 0 ;X12 - CYLINDERS LOW MASTER - DB 0 ;X13 - CYLINDERS HIGH MASTER - DB 0 ;X14 - HEADS MASTER - DB 0 ;X15 - SECTORS MASTER - DB 0 ;X16 - CYLINDERS LOW SLAVE - DB 0 ;X17 - CYLINDERS HIGH SLAVE - DB 0 ;X18 - HEADS SLAVE - DB 0 ;X19 - SECTORS SLAVE - DB 0 ;X1A - Int conf, Screen sync, COLOR STYLE - DB TURBON+SPRIN ;X1B - HARDARE CONF - DB BAS128 ;X1C - RESET MODE - DB REBOOTM ;X1D - REBOOT - DB 0 ;X1E - TRDOS - DB #77 ;X1F - SCREEN POSITION - DB HD1AUTO+HD2AUTO ;X20 - Secondary HDD's -.Length EQU $-DEFVAL +DEFVAL: DB SAVERAM + SETBOOTSOUND + SDELAY1 ;#0E - OPTIONS + DB TDL250 + TRATE30 ;#0F - KEYBOARD + DB SDIDE1 + ASDFDD1 ;#10 - SYSTEM DISKS + DB FD1720 + FD2720+HD1AUTO+HD2AUTO ;#11 - FDD & Primary HDD's + DB 0 ;#12 - CYLINDERS LOW MASTER + DB 0 ;#13 - CYLINDERS HIGH MASTER + DB 0 ;#14 - HEADS MASTER + DB 0 ;#15 - SECTORS MASTER + DB 0 ;#16 - CYLINDERS LOW SLAVE + DB 0 ;#17 - CYLINDERS HIGH SLAVE + DB 0 ;#18 - HEADS SLAVE + DB 0 ;#19 - SECTORS SLAVE + DB 0 ;#1A - Int conf, Screen sync, COLOR STYLE + DB CNF_PORT.TURBO.ON + CNF_PORT.CNF_0 ;#1B - HARDARE CONF + DB BAS128 ;#1C - RESET MODE + DB REBOOTM + 4 ;#1D - REBOOT + LoadZXroms by ZX flag + DB 0 ;#1E - TRDOS + DB #77 ;#1F - SCREEN POSITION + DB HD1AUTO + HD2AUTO ;#20 - Secondary HDD's +.Size EQU $-DEFVAL +;!FIXIT расписать тут ячейки кмоса и это смещение меткой привязать вместо #0E в SETDEF _mInfoALIGN 256,0 ; выравнивание на адрес #XX00 CMOSARE: - DS 14 ;!FIXIT расписать тут ячейки кмоса и это смещение меткой привязать вместо #0E в SETDEF - - DB SAVERAM+EXTBIOS ;X0E - OPTIONS - DB TDL250+TRATE30 ;X0F - KEYBOARD - DB SDIDE1+ASDFDD2 ;X10 - SYSTEM DISKS - DB FD1720+FD2720+HD1AUTO+HD2AUTO ;X11 - FDD & HDD - DB 0 ;X12 - CYLINDERS LOW MASTER - DB 0 ;X13 - CYLINDERS HIGH MASTER - DB 0 ;X14 - HEADS MASTER - DB 0 ;X15 - SECTORS MASTER - DB 0 ;X16 - CYLINDERS LOW SLAVE - DB 0 ;X17 - CYLINDERS HIGH SLAVE - DB 0 ;X18 - HEADS SLAVE - DB 0 ;X19 - SECTORS SLAVE - DB 0 ;X1A - Int conf, Screen sync, COLOR STYLE - DB TURBON+SPRIN ;X1B - HARDARE CONF - DB BAS128 ;X1C - RESET MODE - DB REBOOTM ;X1D - REBOOT MSG, HDD W/P - DB %00000000 ;X1E - TRDOS - DB %01110111 ;X1F - SCREEN POSITION - DB HD1AUTO+HD2AUTO ;X20 - Secondary HDD's - DB %00000000 ;X21 - DB %00000000 ;X22 - DB %00000000 ;X23 - DB %00000000 ;X24 - DB %00000000 ;X25 - DB %00000000 ;X26 - DB %00000000 ;X27 - DB %00000000 ;X28 - DB %00000000 ;X29 - DB %00000000 ;X2A - DB %00000000 ;X2B - DB %00000000 ;X2C - DB %00000000 ;X2D - DB %00000000 ;X2E - DB %00000000 ;X2F - DB %00000000 ;X30 - DB %00000000 ;X31 - DB #20 ;X32 - CENTURY - DB %00000000 ;X33 - DB %00000000 ;X34 - DB %00000000 ;X35 - DB %00000000 ;X36 - DB %00000000 ;X37 - DB %00000000 ;X38 - DB %00000000 ;X39 - DB %00000000 ;X3A - DB %00000000 ;X3B - DB %00000000 ;X3C - DB %00000000 ;X3D - DB %00000000 ;X3E - DB %00000000 ;X3F - CHECKSUM - BLOCK #100 - low $ ; добивка CMOSARE до размера в 256 байтов + DS 14 + ; + DB SAVERAM + SETBOOTSOUND + SDELAY1 ;#0E - OPTIONS + DB TDL250+TRATE30 ;#0F - KEYBOARD + DB SDIDE1 + ASDFDD1 ;#10 - SYSTEM DISKS + DB FD1720+FD2720+HD1AUTO+HD2AUTO ;#11 - FDD & HDD + DB 0 ;#12 - CYLINDERS LOW MASTER + DB 0 ;#13 - CYLINDERS HIGH MASTER + DB 0 ;#14 - HEADS MASTER + DB 0 ;#15 - SECTORS MASTER + DB 0 ;#16 - CYLINDERS LOW SLAVE + DB 0 ;#17 - CYLINDERS HIGH SLAVE + DB 0 ;#18 - HEADS SLAVE + DB 0 ;#19 - SECTORS SLAVE + DB 0 ;#1A - Int conf, Screen sync, COLOR STYLE + DB TURBON+SPRIN ;#1B - HARDARE CONF + DB BAS128 ;#1C - RESET MODE + DB REBOOTM ;#1D - REBOOT MSG, HDD W/P + DB %0000'0000 ;#1E - TRDOS + DB %0111'0111 ;#1F - SCREEN POSITION + DB HD1AUTO+HD2AUTO ;#20 - Secondary HDD's + DB %0000'0000 ;#21 + DB %0000'0000 ;#22 + DB %0000'0000 ;#23 + DB %0000'0000 ;#24 + DB %0000'0000 ;#25 + DB %0000'0000 ;#26 + DB %0000'0000 ;#27 + DB %0000'0000 ;#28 + DB %0000'0000 ;#29 + DB %0000'0000 ;#2A + DB %0000'0000 ;#2B + DB %0000'0000 ;#2C + DB %0000'0000 ;#2D + DB %0000'0000 ;#2E + DB %0000'0000 ;#2F + DB %0000'0000 ;#30 + DB %0000'0000 ;#31 + DB #20 ;#32 - CENTURY + DB %0000'0000 ;#33 + DB %0000'0000 ;#34 + DB %0000'0000 ;#35 + DB %0000'0000 ;#36 + DB %0000'0000 ;#37 + DB %0000'0000 ;#38 + DB %0000'0000 ;#39 + DB %0000'0000 ;#3A + DB %0000'0000 ;#3B + DB %0000'0000 ;#3C + DB %0000'0000 ;#3D + DB %0000'0000 ;#3E + DB %0000'0000 ;#3F - CHECKSUM + BLOCK #100 - low $ ; добивка CMOSARE до размера в 256 байтов ;DONT MOVE !!! ADDRESS - - -; !TODO всё правильно? -;REGISTER #0E -; %10000000 - MEMORY TEST -; %01000000 - SAVE RAM DISKS -; %00100000 - UPDATE BIOS -; %00011000 - START DELAY -; %00000100 - LANGUAGE -; %00000010 - NOT USED -; %00000001 - QUICK START -;REGISTER #0F -; %10000000 - TYPEMATIC ON/OFF -; %01100000 - TYPEMATIC DELAY 00-250, 01-500, 10-750, 11-1000 -; %00011111 - TYPEMATIC RATE -; 0-6, 1-8, 2-10, 3-12, 4-15, 5-20, 6-24, 7-30 -;REGISTER #10 -; %00000111 - SYSTEM DISK -; %01110000 - ALT SYSTEM DISK -;REGISTER #11 -; %00000011 - FDD FIRST 720 / 1.44 / NONE -; %00001100 - FDD SECOND -; %00110000 - IDE Primary MASTER AUTO / SETUP / DISABLED -; %11000000 - IDE Primary SLAVE -----//------ -;REGISTER #12 - CYLINDERS (MASTER) -;REGISTER #14 - HEADS (MASTER) -;REGISTER #15 - SECTORS (MASTER) -;REGISTER #16 - CYLINDERS (SLAVE) -;REGISTER #18 - HEADS (SLAVE) -;REGISTER #19 - SECTORS (SLAVE) -;REGISTER #1A -; %00001111 - COLOR STYLE -; %00110000 - Frame Int (Default/Pentagon/Scorpion/Original) -; %11000000 - Screen V-Sinc (Default/312 lines 50 HZ/320 Lines 49 Hz) -;REGISTER #1B - HARDWARE CONFIGURATION -; %00000001 - TURBO MODE (D0..D3 - 6 OR 7) -; %00000010 - TURBO EXCHANGE ON/OFF - 1 -; %00000100 - PORT EXCHANGE ON/OFF - 1 -; %00011000 - COMPUTER -; 0-SPRINTER -; 1-SPECTRUM 256 -; 2-PENTAGON 128 -; 3-OTHER -; %11100000 - RESERVED -;REGISTER #1C - RESET MODE -; 0-RESET 128 Basic -; 1-RESET 48 Basic & 128 mem -; 2-RESET TR-DOS & 128 mem -; 3-RESET EXPANSION (Disabled) -; 4-RESET TR-DOS & 48 mem -; 5-RESET 48 Basic -;REGISTER #1D -; %00000010 - Reboot message -; %00000001 - HDD Write protect -;REGISTER #1E -; %00000011 - TR DOS A: Default / FDD / HDD / RMD -; %00001100 - TR DOS B: Default / FDD / HDD / RMD -; %00110000 - TR DOS C: Default / FDD / HDD / RMD -; %11000000 - TR DOS D: Default / FDD / HDD / RMD -;REGISTER #1F ;R06 -; %11110000 - X-Screen position -; %00001111 - Y-Screen position -;REGISTER #20 -; %00110000 - IDE Secondary MASTER AUTO / SETUP / DISABLED -; %11000000 - IDE Secondary SLAVE -----//------ -; . -; . -;REGISTER #37 - CYLINDERS (MASTER) -;REGISTER #39 - HEADS (MASTER) -;REGISTER #3A - SECTORS (MASTER) -;REGISTER #3B - CYLINDERS (SLAVE) -;REGISTER #3D - HEADS (SLAVE) -;REGISTER #3E - SECTORS (SLAVE) \ No newline at end of file +; \ No newline at end of file diff --git a/src/bios/rom/SETUP/SETUP.AS b/src/bios/rom/SETUP/SETUP.AS deleted file mode 100644 index 6e5931e..0000000 --- a/src/bios/rom/SETUP/SETUP.AS +++ /dev/null @@ -1,35 +0,0 @@ -; DEFINE MAX_END_ADDR #A2FF ;!!!!! привязка к адресу -; INCLUDE '../MEM_MAP.INC' - -; ORG #8000 - DB "SETUP" - JR JUMP - DB "(C) 2001 PETERS PLUS LTD " -JUMP: - DI - POP HL - LD SP,#7FFF - PUSH HL - PUSH AF - LD HL,#8000 ;!!!!!!!!!!hardcode - PUSH HL - LD DE,Depacker_start ; адрес процедуры депакера !!!!! - PUSH DE - LD HL,DEPAKER - LD BC,LENBLOK - LDIR - LD HL,PAKCODE ; где архив - LD DE,MAIN_Unpacked_Start ; куда распаковывать - RET - -DEPAKER: -; INCBIN 'Build/Bin/DEPACK.BIN' - DISP Depacker_start - INCLUDE 'src/bios/ROM/SETUP/DEPACK.ASM' - ENT - - -PAKCODE: - INCBIN 'Build/Bin/MAIN.HR' -LENBLOK EQU $-DEPAKER - diff --git a/src/bios/rom/SETUP/Test_Temp.asm b/src/bios/rom/SETUP/Test_Temp.asm deleted file mode 100644 index fe6fa37..0000000 --- a/src/bios/rom/SETUP/Test_Temp.asm +++ /dev/null @@ -1,50 +0,0 @@ - LUA PASS1 - SettingsTabsOrder = { - [1]={ - "Lang", - "MemTest", - "SaveRAMdrvs", - "UpdBios", - "StartDelay", - "TypRate", - "TypDelay", - "RebootMsg", - "SysDsk", - "AltSysDsk", - "FddFirst", - "FddSecond", - "PriIdeMA", - "PriIdeSl", - "SecIdeMA", - "SecIdeSl", - "HddWrPr" - }, - [2]={ - "ScreenY", - "ScreenX", - "FrameInt", - "VSync", - "QuickStartROM", - "TrDosA", - "TrDosB", - "TrDosC", - "TrDosD" - } - } - ENDLUA - - - MACRO itemName? -@.itemName? EQU $ - DEFINE TmpDef Suffix? - LUA ALLPASS - function get_key_for_value(t, value) - for k,v in pairs(t) do - if v==value then return k end - end - return nil - end - print(get_key_for_value(SettingsTabsOrder, sj.get_define("TmpDef"))) - ENDLUA - UNDEFINE TmpDef - ENDM \ No newline at end of file diff --git a/src/bios/rom/SETUP/VIDEO_IO.asm b/src/bios/rom/SETUP/VIDEO_IO.asm index 54487dc..aeddc70 100644 --- a/src/bios/rom/SETUP/VIDEO_IO.asm +++ b/src/bios/rom/SETUP/VIDEO_IO.asm @@ -2,125 +2,173 @@ def_pal_mask EQU #FF PIC_SET_PAL_FF EQU def_pal_mask*256+BIOS.PIC_SET_PAL - - IF NEW_FEATURE - - - - ENDIF - ;; ScreenPOS: -;.GET_CUR: -; LD C,BIOS.LP_GET_PLACE -; JP ToBIOS_18 - .SUBNAME: - ;CALL ScreenPOS.GET_CUR CALL LP_GET_PLACE - LD E,#24 -;.LOCAT: -; LD C,BIOS.LP_SET_PLACE -; JP ToBIOS_18 + LD E,.SUBNAME.POS ;!HARDCODE autodetected hdd/cdrom info JP LP_SET_PLACE - -.CRLF: ;CALL ScreenPOS.GET_CUR - CALL LP_GET_PLACE +.SUBNAME.POS EQU 37 + ; +.CRLF: CALL LP_GET_PLACE INC D LD E,#00 - ;JP ScreenPOS.LOCAT - JP LP_SET_PLACE + JP LP_SET_PLACE ;; -DWPRINT: - LD A,(HL) - CP ' ' - JR NZ,PRINTDW - INC HL - LD A,(HL) - DEC HL - CP ' ' - JR NZ,PRINTDW - INC HL - INC HL - DJNZ DWPRINT - RET -PRINTDW: - PUSH BC - LD E,(HL) - INC HL - LD A,(HL) - INC HL - CALL PRINT_CHAR - LD A,E - CALL PRINT_CHAR - POP BC - DJNZ PRINTDW - RET -PRINTA: LD E,A -; LD C,BIOS.LP_PRINT_ATR -; JP ToBIOS_18 - JP LP_PRINT_ATR + IF BIG_ENDIAN_STR_PRINT = 2 +PRINT_STR_BIG_ENDIAN: + LD A,(HL) + CP ' ' + JR NZ,.PRINTDW + INC HL + LD A,(HL) + DEC HL + CP ' ' + JR NZ,.PRINTDW + INC HL + INC HL +.no_space: DJNZ DWPRINT + RET + ; +.PRINTDW: PUSH BC + LD E,(HL) + INC HL + LD A,(HL) + INC HL + CALL PRINT_CHAR + LD A,E + CALL PRINT_CHAR + POP BC + LD A,' ' + CP E + JR Z,.no_space + DJNZ .PRINTDW + RET -PRINT_CHAR: -; LD BC,1*256 + BIOS.LP_PRINT_SYM -; JP ToBIOS_18 - LD B,1 - JP LP_PRINT_SYM + ELSEIF BIG_ENDIAN_STR_PRINT = 0 +PRINT_STR_BIG_ENDIAN: + PUSH HL + PUSH BC + LD D,H + LD E,L + INC HL + ; +.loop_ch: LD A,(DE) + LDI + LD (DE),A + INC HL + INC DE + DJNZ .loop_ch + ; + POP BC + POP HL + LD A,B + ADD A,B + LD B,A + ; +.print_loop: CALL .no_space + RET Z + LD D,H + LD E,L + PUSH DE + PUSH BC + LD D,' ' + CALL LP_PRINT_LINE6 + POP BC + POP DE + PUSH HL + AND A + SBC HL,DE + LD A,B + SUB L + LD B,A + JR Z,.exit + LD A,' ' + INC B + PUSH BC + CALL PRINT_CHAR + POP BC + POP HL + DJNZ .print_loop + RET + ; +.no_space: LD A,(HL) + CP ' ' + RET NZ + INC HL + DJNZ .no_space + RET + ; +.exit: POP HL + RET + + ELSEIF BIG_ENDIAN_STR_PRINT = 1 +PRINT_STR_BIG_ENDIAN: + PUSH HL + PUSH BC + LD D,H + LD E,L + INC HL + ; +.loop_ch: LD A,(DE) + LDI + LD (DE),A + INC HL + INC DE + DJNZ .loop_ch + ; + POP BC + POP HL + LD A,B + ADD A,B + LD B,A + JP LP_PRINT_LINE2 + ENDIF + + + +PRINTA: LD E,A + JP LP_PRINT_ATR +; +PRINT_CHAR: LD B,1 + JP LP_PRINT_SYM ; -TPRINTZ: - ;CALL ScreenPOS.LOCAT - CALL LP_SET_PLACE -; LD BC,0*256 + BIOS.LP_PRINT_LINE6 -PRINTZ: - LD B,0 - LD D,B -; JP ToBIOS_18 - JP LP_PRINT_LINE6 +;TPRINTZ: CALL LP_SET_PLACE +PRINTZ: LD B,0 + LD D,B + JP LP_PRINT_LINE6 +; -; PRINTZ: -; ; LD BC,0*256 + BIOS.LP_PRINT_LINE6 -; LD B,0 -; LD D,B -; ; JP ToBIOS_18 -; JP LP_PRINT_LINE6 +; HPRINTZ: LD B,0 +; LD D,B +; LD E,COLORS.CGA.INK.WHITE +; JP LP_PRINT_LINE5 -HPRINTZ: - ;LD BC,0*256 + BIOS.LP_PRINT_LINE5 - LD B,0 - LD D,B - LD E,#0F - ;JP ToBIOS_18 - JP LP_PRINT_LINE5 +CPRINTZ: LD B,0 + LD D,B + LD E,A + JP LP_PRINT_LINE5 +; -CPRINTZ: - ;LD BC,0*256 + BIOS.LP_PRINT_LINE5 - LD B,0 - LD D,B - LD E,A - ;JP ToBIOS_18 - JP LP_PRINT_LINE5 - -;HL - NUMBER -IZPRINT: - LD D,1 - JR IPRIN -IPRINT: - LD D,0 -IPRIN: LD BC,10000 - CALL PRINTDG - LD BC,1000 - CALL PRINTDG - LD BC,100 - CALL PRINTDG - LD BC,10 - CALL PRINTDG - LD A,L - ADD A,#30 - JP PRINT_CHAR +IPRINT: LD D,0 +.I: LD BC,10000 + CALL PRINTDG + LD BC,1000 + CALL PRINTDG + LD BC,100 + CALL PRINTDG + LD BC,10 + CALL PRINTDG + LD A,L + ADD A,#30 + JP PRINT_CHAR + ;HL - NUMBER +.Z: LD D,1 + JR .I PRINTDG: LD A,#2F @@ -187,239 +235,227 @@ TLINEH: ; E - X ; B - CY ; C - CX -PBORDER: - PUSH BC - LD A,C - DEC A - LD (.BSHI),A - DEC A - LD (.BHOR),A - LD (.BHOR2),A - ;CALL ScreenPOS.LOCAT - CALL LP_SET_PLACE - LD A,(ElementsBuffer.UpLeft) - LD H,E - CALL PRSYM - LD A,(ElementsBuffer.HorizontalLine) -.BHOR+1: - LD B,1 +PBORDER: PUSH BC + LD A,C + DEC A + LD (.BSHI),A + DEC A + LD (.BHOR),A + LD (.BHOR2),A + CALL LP_SET_PLACE + LD A,(ElementsBuffer.UpLeft) + LD H,E + CALL PRSYM + LD A,(ElementsBuffer.HorizontalLine) +.BHOR+1: LD B,1 + CALL LP_PRINT_SYM - ;CALL PRSYMB - CALL LP_PRINT_SYM + LD A,(ElementsBuffer.UpRight) + CALL PRSYM + POP BC + DEC B + DEC B + INC D + LD E,H +.loop: PUSH BC + CALL LP_SET_PLACE + LD A,(ElementsBuffer.VerticalLine) + CALL PRSYM + LD A,H +.BSHI+1: ADD A,#00 + LD E,A + CALL LP_SET_PLACE + LD A,(ElementsBuffer.VerticalLine) + CALL PRSYM + POP BC + LD E,H + INC D + DJNZ .loop - LD A,(ElementsBuffer.UpRight) - CALL PRSYM - POP BC - DEC B - DEC B - INC D - LD E,H + CALL LP_SET_PLACE + LD A,(ElementsBuffer.DownLeft) + CALL PRSYM + LD A,(ElementsBuffer.HorizontalLine) +.BHOR2+1: LD B,1 + CALL LP_PRINT_SYM + LD A,(ElementsBuffer.DownRight) + CALL PRSYM + RET -.loop: PUSH BC - ;CALL ScreenPOS.LOCAT - CALL LP_SET_PLACE - LD A,(ElementsBuffer.VerticalLine) - CALL PRSYM - LD A,H -.BSHI+1: - ADD A,#00 - LD E,A - ;CALL ScreenPOS.LOCAT - CALL LP_SET_PLACE - LD A,(ElementsBuffer.VerticalLine) - CALL PRSYM - POP BC - LD E,H - INC D - DJNZ .loop - - ;CALL ScreenPOS.LOCAT - CALL LP_SET_PLACE - LD A,(ElementsBuffer.DownLeft) - CALL PRSYM - LD A,(ElementsBuffer.HorizontalLine) -.BHOR2+1: - LD B,1 - - ;CALL PRSYMB - CALL LP_PRINT_SYM - - LD A,(ElementsBuffer.DownRight) - CALL PRSYM - RET - -PRSYM: ;LD BC,1*256 + BIOS.LP_PRINT_SYM - ;JP ToBIOS_18 - LD B,1 +PRSYM: LD B,1 JP LP_PRINT_SYM -; PRSYMB: LD C,BIOS.LP_PRINT_SYM -; JP ToBIOS_18 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +//////////////////// LOGO \\\\\\\\\\\\\\\\\\\\ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +LOGOTYPE: CALL SHOW_LOGO + ; + IF STARTUP_SND +.playSnd+1: LD A,#80 + RLA + JR NC,.noSound + ; + LD BC,CMOS_CELL.BootUpParams.Mask.BootSound + CALL GET_CMOS_VALUE + OR A + JR Z,.noSound + LD A,#37 ; opcode SCF, play sound on + LD (INT_HANDLER.sndSwitch),A +.noSound: ; + ENDIF + ; + LD BC,CMOS_CELL.BootUpParams.Mask.StartDelay + CALL GET_CMOS_VALUE + OR A + JR Z,.MinDelay + DEC A + JR Z,.AverageDelay + ; Delay enabled + LD B,LOGO_DELAY_NORM +.loop EI + push bc + HALT + CALL go_setup + pop bc + DJNZ .loop + ; Delay average +.AverageDelay: LD B,LOGO_DELAY_MAX +.MMA: PUSH BC + EI + HALT + DI + CALL FADE + POP BC + DJNZ .MMA + ; ; +.ERASE_LOGO: LD IX,win_descriptor.tab80x32 + ;LD HL,#0000 + ;LD E,1 + ; + EI + HALT + DI + CALL WIN_OPEN.SCR1 + ; + IF STARTUP_SND + LD A,#3F ; opcode CCF, play sound off + LD (INT_HANDLER.sndSwitch),A + CALL STARTUP_SOUND.mute + ENDIF + ; + LD DE,0 + LD HL,#0920 ;!HARDCODE LOGOTYPE SIZE + LD B,7 + JP LP_CLS_WIN + ; Delay disabled +.MinDelay: LD B,LOGO_DELAY_MIN +.loop2: EI + HALT + DJNZ .loop2 + DI + JR .ERASE_LOGO +; ; ; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -LOGOTYP: - CALL LOGOX - LD BC,#180E - CALL G_VALUE - OR A - JR Z,EASYDLY ;MIN (DISABLE) - DEC A - JR Z,SKIPDLY ;NORMAL - - LD B,LOGO_DELAY_NORM -.loop EI - push bc - HALT - call go_setup - pop bc - DJNZ .loop -SKIPDLY: - LD B,LOGO_DELAY_MAX -.MMA: PUSH BC - EI - HALT - DI - CALL FADE - POP BC - DJNZ .MMA - -NOWLOGO: - LD IX,win_descriptor.tab80x32 - LD HL,#0000 - LD E,1 - - ;LD C,BIOS.WIN_OPEN - EI - HALT - DI - ;RST ToBIOS_18 - CALL WIN_OPEN - - LD DE,0 - LD HL,#0920 ;LOGOTYPE SIZE - ;LD BC,7*256 + BIOS.LP_CLS_WIN - ;JP ToBIOS_18 - LD B,7 - JP LP_CLS_WIN - -EASYDLY: - LD B,LOGO_DELAY_MIN -.loop: EI - HALT - DJNZ .loop - DI - JR NOWLOGO - -LOGOX: LD IX,win_descriptor.tab320x256 - LD HL,#0000 - LD E,1 - ;LD C,BIOS.WIN_OPEN - ;RST ToBIOS_18 - CALL WIN_OPEN +SHOW_LOGO: LD IX,win_descriptor.tab320x256 + CALL WIN_OPEN.SCR1 SAFE_PORTY - DI - LD A,1 - OUT (SYS_PORT.ON),A - OUT (ROM.SLOT0),A + DI + LD A,SYS_PORT.PAGE0 + OUT (SYS_PORT.ON),A + OUT (ROM.SLOT0),A - LD HL,MAIN_LOGO.Pallete - LD DE,memBUFFER.Shared - LD BC,MAIN_LOGO.Pallete.length - LDIR + LD HL,MAIN_LOGO.Pallete + LD DE,memBUFFER.Shared + LD BC,MAIN_LOGO.Pallete.length + LDIR - XOR A - OUT (ROM.SLOT0),A - OUT (SYS_PORT.ON),A - EI + XOR A + OUT (ROM.SLOT0),A + OUT (SYS_PORT.ON),A + EI - LD HL,memBUFFER.Shared - ; A = 0 - LD D,A ; SET DESKTOP PALETTE & CURSOR COLORS - LD E,A - ;LD BC,PIC_SET_PAL_FF - ;RST ToBIOS_18 - LD B,def_pal_mask - CALL PIC_SET_PAL + LD HL,memBUFFER.Shared + ; A = 0 + LD D,A ; SET DESKTOP PALETTE & CURSOR COLORS + LD E,A + LD B,def_pal_mask + CALL PIC_SET_PAL SAFE_PORTY - DI - LD A,1 - OUT (SYS_PORT.ON),A - ;LD A,1 - OUT (ROM.SLOT0),A - - LD HL,MAIN_LOGO.Raster ; начало картинки в банке ПЗУ -; CALL DECODE - CALL LOGO_TO_SCREEN - ; - ;--------------[Пасхалка]--------------[] - IF Pashalki - _PASHALKI_CODE - ENDIF - ;--------------------------------------[] - ; - XOR A - OUT (SYS_PORT.ON),A - OUT (ROM.SLOT0),A - EI - RET - + DI + LD A,SYS_PORT.PAGE0 + OUT (SYS_PORT.ON),A + OUT (ROM.SLOT0),A + LD HL,MAIN_LOGO.Raster ; начало картинки в банке ПЗУ + ; CALL DECODE + CALL LOGO_TO_SCREEN + XOR A + OUT (SYS_PORT.ON),A + OUT (ROM.SLOT0),A + EI + RET +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; win_descriptor: -.tab80x32: - DB 40 - DB 32 - DB 0 - DB 0 - DB %00011011 - DB 0 - DB 0 - DB 0 -.tab320x256: - DB 16 ; горизонтальный размер окна в знакоместах - DB 9 ; вертикальный размер в знакоместах - DB 0 ; положение окна по горизонтали на экране - DB 0 ; положение окна по вертикали на экране - DB %00100000 ; режим знакоместа - DB 0 ; дополнительный режим знакоместа - DB 8 ; положение по X в поле графики (по знакоместам) - DB 0 ; положение по Y в поле графики (по знакоместам) - +.tab80x32 Window_UserVars{ + 40, ; горизонтальный размер окна в знакоместах + 32, ; вертикальный размер в знакоместах + 0, ; положение окна по горизонтали на экране + 0, ; положение окна по вертикали на экране + %0001'1011, ; режим знакоместа + 0, ; дополнительный режим знакоместа + 0, ; положение по X в поле графики (по знакоместам) + 0 ; положение по Y в поле графики (по знакоместам) + } +.tab320x256 Window_UserVars{ + 16, ; горизонтальный размер окна в знакоместах + 9, ; вертикальный размер в знакоместах + 0, ; положение окна по горизонтали на экране + 0, ; положение окна по вертикали на экране + %0010'0000, ; режим знакоместа + 0, ; дополнительный режим знакоместа + 8, ; положение по X в поле графики (по знакоместам) + 0 ; положение по Y в поле графики (по знакоместам) + } +; MACRO _mFADE - LD HL,memBUFFER.Shared - ; A = 0 - LD B,A -.loop: - DUP 3 - CP (HL) - JR Z,1F - DEC (HL) -1: INC HL - EDUP - INC HL - DJNZ .loop + LD HL,memBUFFER.Shared + ; A = 0 + LD B,A +.loop: DUP 3 + CP (HL) + JR Z,1F + DEC (HL) +1: INC HL + EDUP + INC HL + DJNZ .loop ENDM + + FADE: XOR A _mFADE _mFADE ; A = 0 LD HL,memBUFFER.Shared - ;LD DE,#0000 ; !HARDCODE & CURSOR COLORS - ;XOR A - LD D,A - LD E,A - ;LD BC,PIC_SET_PAL_FF ; !HARDCODE #EE,#EF - ;RST ToBIOS_18 + ; LD DE,#0000 + LD D,A + LD E,A + ; LD B,def_pal_mask CALL PIC_SET_PAL SAFE_PORTY -go_setup: ; !FIXIT переделать на TSETUP +go_setup: ; !FIXIT переделать на TSETUP CALL SCANKEY RET Z @@ -432,12 +468,8 @@ go_setup: ; !FIXIT jr nz,go_setup LD IX,win_descriptor.tab80x32 - LD HL,#0000 - LD E,1 - ;LD C,BIOS.WIN_OPEN - ;RST ToBIOS_18 - CALL WIN_OPEN - JP CSETUP + CALL WIN_OPEN.SCR1 + JP ENTER_SETUP .to_EXIT_SETUP: LD HL,(RET_TO_EXP_ADDR) @@ -455,14 +487,14 @@ LOGO_TO_SCREEN: LD A,#50 OUT (SLOT1),A - LD A,72 ; !HARDCODE координата картинки по Y + высота картинки + LD A,72 ; !HARDCODE координата картинки по Y + высота картинки .loop: DEC A OUT (PORT_Y),A - LD DE,#4040 ; !HARDCODE координата картинки по Х - LD BC,128 ; !HARDCODE длина горизонтальной линии картинки + LD DE,#4040 ; !HARDCODE координата картинки по Х + LD BC,128 ; !HARDCODE длина горизонтальной линии картинки LDIR - OR A ; !!!!! or a + OR A JP NZ,.loop POP BC @@ -474,7 +506,7 @@ LOGO_TO_SCREEN: RET ; IF !ROM_LOGO_TEST - ; LOGPAL: ; palitre for logotype + ; LOGPAL: ; palitre for logotype ; IF TEST_Build ; INCBIN './test/test2_pal.bin' ; ELSE @@ -527,28 +559,36 @@ LOGO_TO_SCREEN: SET_CGA: + ; LD A,4 + ; LD B,3 + ; CALL SET_PAL_INIT + ; LD A,5 + ; LD B,3 + ; CALL SET_PAL_INIT + ; LD A,6 + ; LD B,3 + ; CALL SET_PAL_INIT + ; LD A,7 + ; LD B,3 + ; CALL SET_PAL_INIT + ; RET + CALL SETPAL4 LD A,4 ; page_pal LD HL,memBUFFER.Shared LD DE,#0000 ; D - ELEMENTS,E - COLOR - ;LD BC,PIC_SET_PAL_FF ; #FFA4 - ;RST ToBIOS_18 LD B,def_pal_mask CALL PIC_SET_PAL LD A,6 ; page_pal LD HL,memBUFFER.Shared LD DE,#0000 ;D - ELEMENTS,E - COLOR - ;LD BC,PIC_SET_PAL_FF ; #FFA4 - ;RST ToBIOS_18 LD B,def_pal_mask CALL PIC_SET_PAL LD A,7 ; page_pal LD HL,#80*4+memBUFFER.Shared LD DE,#8080 ;D - ELEMENTS,E - COLOR - ;LD BC,PIC_SET_PAL_FF ; #FFA4 - ;RST ToBIOS_18 LD B,def_pal_mask CALL PIC_SET_PAL ; @@ -557,16 +597,12 @@ SET_CGA: LD A,5 ; page_pal LD HL,memBUFFER.Shared LD DE,#0000 ;D - ELEMENTS,E - COLOR - ;LD BC,PIC_SET_PAL_FF ; #FFA4 - ;RST ToBIOS_18 LD B,def_pal_mask CALL PIC_SET_PAL LD A,7 ; page_pal LD HL,memBUFFER.Shared LD DE,#8000 ;D - ELEMENTS,E - COLOR - ;LD BC,PIC_SET_PAL_FF ; #FFA4 - ;RST ToBIOS_18 LD B,def_pal_mask CALL PIC_SET_PAL ; @@ -575,24 +611,25 @@ SETPAL4: LD HL,COLORS.CGA.PALETTE LD DE,memBUFFER.Shared LD C,#08 -DCR0: - LD B,#10 -DCR1: - PUSH BC + +.DCR0: LD B,COLORS.CGA.PALETTE.ColNum PUSH HL + ; +.DCR1: POP HL + PUSH HL + PUSH BC LDI LDI LDI LDI - POP HL POP BC - DJNZ DCR1 - INC HL - INC HL - INC HL - INC HL + DJNZ .DCR1 + ; + INC SP + INC SP DEC C - JR NZ,DCR0 + JR NZ,.DCR0 + LD HL,memBUFFER.Shared LD BC,512 LDIR @@ -602,114 +639,18 @@ SETPAL5: LD HL,COLORS.CGA.PALETTE LD DE,memBUFFER.Shared LD B,#08 -DCR01: +.DCR01: PUSH BC PUSH HL LD BC,16*4 LDIR POP HL POP BC - DJNZ DCR01 + DJNZ .DCR01 LD HL,memBUFFER.Shared LD BC,512 LDIR RET - MODULE COLORS -CGA: - ; B G R _ -.PALETTE: DB #00,#00,#00,#00 ; 0 BLACK - DB #A8,#00,#00,#00 ; 1 BLUE - DB #00,#A8,#00,#00 ; 2 GREEN - DB #A8,#A8,#00,#00 ; 3 CYAN - DB #00,#00,#A8,#00 ; 4 RED - DB #A8,#00,#A8,#00 ; 5 MAGENTA - DB #00,#54,#A8,#00 ; 6 BROWN - DB #A8,#A8,#A8,#00 ; 7 WHITE - DB #54,#54,#54,#00 ; 8 GRAY - DB #FC,#54,#54,#00 ; 9 BRIGHT BLUE - DB #54,#FC,#54,#00 ; 10 BRIGHT GREEN - DB #FC,#FC,#54,#00 ; 11 BRIGHT CYAN - DB #54,#54,#FC,#00 ; 12 BRIGHT RED - DB #FC,#54,#FC,#00 ; 13 BRIGHT MAGENTA - DB #54,#FC,#FC,#00 ; 14 YELLOW - DB #FC,#FC,#FC,#00 ; 15 WHITE -; -; -INC: -.BLACK EQU #00 -.BLUE EQU #01 -.GREEN EQU #02 -.CYAN EQU #03 -.RED EQU #04 -.MAGENTA EQU #05 -.BROWN EQU #06 -.LGRAY EQU #07 -.DGRAY EQU #08 -.LBLUE EQU #09 -.LGREEN EQU #0A -.LCYAN EQU #0B -.LRED EQU #0C -.LMAGENT EQU #0D -.YELLOW EQU #0E -.WHITE EQU #0F -PAPER: -.BLACK EQU 16*INC.BLACK -.BLUE EQU 16*INC.BLUE -.GREEN EQU 16*INC.GREEN -.CYAN EQU 16*INC.CYAN -.RED EQU 16*INC.RED -.MAGENTA EQU 16*INC.MAGENTA -.BROWN EQU 16*INC.BROWN -.LGRAY EQU 16*INC.LGRAY -.DGRAY EQU 16*INC.DGRAY -.LBLUE EQU 16*INC.LBLUE -.LGREEN EQU 16*INC.LGREEN -.LCYAN EQU 16*INC.LCYAN -.LRED EQU 16*INC.LRED -.LMAGENT EQU 16*INC.LMAGENT -.YELLOW EQU 16*INC.YELLOW -.WHITE EQU 16*INC.WHITE - -FLASH EQU #80 - -/* -INC_COLOR: -.BLACK EQU #00 -.BLUE EQU #01 -.GREEN EQU #02 -.CYAN EQU #03 -.RED EQU #04 -.MAGENTA EQU #05 -.BROWN EQU #06 -.LGRAY EQU #07 -.DGRAY EQU #08 -.LBLUE EQU #09 -.LGREEN EQU #0A -.LCYAN EQU #0B -.LRED EQU #0C -.LMAGENT EQU #0D -.YELLOW EQU #0E -.WHITE EQU #0F -.FLASH EQU #80 -PAPER_COLOR: -.BLACK EQU 16*COLORS.INC.BLACK -.BLUE EQU 16*COLORS.INC.BLUE -.GREEN EQU 16*COLORS.INC.GREEN -.CYAN EQU 16*COLORS.INC.CYAN -.RED EQU 16*COLORS.INC.RED -.MAGENTA EQU 16*COLORS.INC.MAGENTA -.BROWN EQU 16*COLORS.INC.BROWN -.LGRAY EQU 16*COLORS.INC.LGRAY -.DGRAY EQU 16*COLORS.INC.DGRAY -.LBLUE EQU 16*COLORS.INC.LBLUE -.LGREEN EQU 16*COLORS.INC.LGREEN -.LCYAN EQU 16*COLORS.INC.LCYAN -.LRED EQU 16*COLORS.INC.LRED -.LMAGENT EQU 16*COLORS.INC.LMAGENT -.YELLOW EQU 16*COLORS.INC.YELLOW -.WHITE EQU 16*COLORS.INC.WHITE -.FLASH EQU #80 -*/ - ENDMODULE + include 'shared_includes/constants/standart_colors.inc' ; \ No newline at end of file diff --git a/src/bios/rom/SETUP/ayfxplay.asm b/src/bios/rom/SETUP/ayfxplay.asm new file mode 100755 index 0000000..fe1e582 --- /dev/null +++ b/src/bios/rom/SETUP/ayfxplay.asm @@ -0,0 +1,403 @@ +; -Minimal ayFX player (Improved) v2.05 25/01/21--------------; +; https://github.com/Threetwosevensixseven/ayfxedit-improved ; +; Zeus format (http://www.desdes.com/products/oldfiles) ; +; ; +; Forked from v0.15 06/05/06 ; +; https://shiru.untergrund.net/software.shtml ; +; ; +; The simplest effects player. Plays effects on one AY, ; +; without music in the background. ; +; Priority of the choice of channels: if there are free ; +; channels, one of them is selected if free. ; +; If there are are no free channels, the longest-sounding ; +; one is selected. ; +; Procedure plays registers AF, BC, DE, HL, IX. ; +; ; +; Initialization: ; +; ld hl, the address of the effects bank ; +; call AFXInit ; +; ; +; Start the effect: ; +; ld a, the number of the effect (0..255) ; +; call AFXPlay ; +; ; +; In the interrupt handler: ; +; call AFXFrame ; +; ; +; Start the effect on a specified channel: ; +; ld a, the number of the effect (0..255) ; +; ld e, the number of the channel (A=0, B=1, C=2) ; +; call AFXPlayChannel ; +; ; +; Start the effect with sustain loop enabled: ; +; ld a, the number of the effect (0..255) ; +; ld e, the number of the channel (A=0, B=1, C=2) ; +; ld bc, the bank address + the release address offset ; +; call AFXPlayChannel ; +; ; +; Notify AFX.Frame that the should be should be looped back to ; +; the sustain point once the release point has been reached: ; +; ld a, the number of the effect (0..255) ; +; ld e, the number of the channel (A=0, B=1, C=2) ; +; ld bc, the bank address + the sustain address offset ; +; call AFXSustain ; +; ; +; Change log: +; v2.05 25/01/21 Bug fix: AFXInit was overwriting itself ; +; the first time it was called, so it ; +; couldn't ever be called a second time. ; ; +; v2.04 22/10/17 Bug fix: EffectTime was not fully ; +; initialised. ; +; v2.03 22/10/17 Bug fix: disabled loop markers should have ; +; MSB $00, as $FF could be a valid address. ; +; Backported Zeus player to Pasmo format. ; +; v2.02 21/10/17 Added the ability to loop a sound while ; +; receiving sustain messages. ; +; v2.01 21/10/17 Added the ability to play a sound on a ; +; specific channel. ; +; v2.00 27/08/17 Converted Z80 player to Zeus format. ; +; --------------------------------------------------------------; + +; Channel descriptors, 4 bytes per channel: +; +0 (2) current address (channel is free if high byte=$00) +; +2 (2) sound effect time +; +2 (2) start address of sustain loop (disabled if high byte=$00) +; +2 (2) end address of sustain loop (disabled if high byte=$00) +afxChDescCount equ 3 +afxChDesc DS afxChDescCount*8 +AFXSMC equ 0 + +; --------------------------------------------------------------; +; Initialize the effects player. ; +; Turns off all channels, sets variables. ; +; ; +; Input: HL = bank address with effects ; +; --------------------------------------------------------------; + +AFXInit: + inc hl + ld (afxBnkAdr1+1), hl ; Save the address of the table of offsets + ld (afxBnkAdr2+1), hl ; Save the address of the table of offsets + ld hl, afxChDesc ; Mark all channels as empty + ld de, $00ff + ld bc, afxChDescCount*256+$fd +afxInit0: + ld (hl), d + inc hl + ld (hl), d + inc hl + ld (hl), e + inc hl + ld (hl), e + inc hl + ld (hl), d + inc hl + ld (hl), d + inc hl + ld (hl), d + inc hl + ld (hl), d + inc hl + djnz afxInit0 + + ld hl, $ffbf ; Initialize AY + ld e, $15 +afxInit1: + dec e + ld b, h + out (c), e + ld b,l + out (c), d + jr nz, afxInit1 + + ld (afxNseMix+1), de ; Reset the player variables + + ret + + + +; --------------------------------------------------------------; +; Play the current frame. ; +; ; +; No parameters. ; +; --------------------------------------------------------------; +AFXFrame: + ld bc, $03fd + ld ix, afxChDesc +afxFrame0: + push bc + + ld a,11 + ld h,(ix+1) ; Compare high-order byte of address to <11 + cp h + jr nc, afxFrame7 ; The channel does not play, we skip + ld l, (ix+0) + ld e, (hl) ; We take the value of the information byte + inc hl + + sub b ; Select the volume register: + ld d, b ; (11-3=8, 11-2=9, 11-1=10) + + ld b, $ff ; Output the volume value + out (c), a + ld b, $bf + ld a, e + and $0f + out (c), a + + bit 5, e ; Will the tone change? + jr z, afxFrame1 ; Tone does not change + + ld a, 3 ; Select the tone registers: + sub d ; 3-3=0, 3-2=1, 3-1=2 + add a, a ; 0*2=0, 1*2=2, 2*2=4 + + ld b, $ff ; Output the tone values + out (c), a + ld b, $bf + ld d, (hl) + inc hl + out (c), d + ld b, $ff + inc a + out (c), a + ld b, $bf + ld d, (hl) + inc hl + out (c), d + +afxFrame1: + bit 6, e ; Will the noise change? + jr z, afxFrame3 ; Noise does not change + + ld a, (hl) ; Read the meaning of noise + sub $20 + jr c, afxFrame2 ; Less than $20, play on + ld h, a ; Otherwise the end of the effect + ld c,$ff + ld b, c ; In BC we record the most time + jr afxFrame6 + +afxFrame2: + inc hl + ld (afxNseMix+1), a ; Keep the noise value + +afxFrame3: + pop bc ; Restore the value of the cycle in B + push bc + inc b ; Number of shifts for flags TN + + ld a, %01101111 ; Mask for flags TN +afxFrame4: + rrc e ; Shift flags and mask + rrca + djnz afxFrame4 + ld d, a + + ld bc, afxNseMix+2 ; Store the values of the flags + ld a, (bc) + xor e + and d + xor e ; E is masked with D + ld (bc), a + +afxFrame5: + ld c, (ix+2) ; Increase the time counter + ld b, (ix+3) + inc bc + +afxFrame6: + ld (ix+2), c + ld (ix+3), b + + ld (ix+0), l ; Save the changed address + ld (ix+1), h + + call CheckRelease +afxFrame7: + ld bc, 8 ; Go to the next channel + add ix, bc + pop bc + djnz afxFrame0 + + ld hl, $ffbf ; Output the value of noise and mixer +afxNseMix: + ld de, 0 ; +1(E)=noise, +2(D)=mixer + ld a, 6 + ld b, h + out (c), a + ld b, l + out (c), e + inc a + ld b, h + out (c), a + ld b, l + out (c), d + ret +CheckRelease: + ld a, (ix+6) ; get release LSB + cp l + ret nz ; Carry on if no MLB match + ld a, (ix+7) ; get release MSB + or a + ret z ; Carry on if release disabled + cp h + ret nz ; Carry on if no MSB match + push bc + ld a, (ix+4) + or a + jp z, NoLoop + ld a, (ix+5) ; Set CurrentAddrCh[N] back + ld (ix+1), a ; to SustainAddrCh[N] LSB + ld a, (ix+4) ; + ld (ix+0), a ; and MSB + xor a + ld (ix+4), a ; then toggle off the sustain + ld (ix+5), a ; to require it to be resent +NoLoop: + pop bc + ret + +; --------------------------------------------------------------; +; Launch the effect on a specific channel. Any sound currently ; +; playing on that channel is terminated next frame. ; +; ; +; Input: A = Effect number 0..255 ; +; E = Channel (A=0, B=1, C=2) ; +; --------------------------------------------------------------; +AFXPlayChannel: + ld bc, $0000 + +; --------------------------------------------------------------; +; Launch the effect on a specific channel. Any sound currently ; +; playing on that channel is terminated next frame. ; +; During playback, when reaching ReleaseAddrCh[N], if an ; +; AFXSustain call has been received since this AFXPlayLooped ; +; returned, the playback time frame will loop back to ; +; SustainAddrCh[N]. ; +; ; +; Input: A = Effect number 0..255 ; +; E = Channel (A=0, B=1, C=2) ; +; BC = ReleaseAddrCh[N] ; +; --------------------------------------------------------------; +AFXPlayLooped: + push af + ld a, c + ld (ReleaseLoSMC), a ; SMC> + ld a, b + ld (ReleaseHiSMC), a ; SMC> + ld a, e + add a, a + add a, a + add a, a + ld e, a + ld d, 0 + ld ix, afxChDesc + add ix, de + ld e, 3 + add ix, de + pop af + ld de, 0 ; In DE the longest time in search + ld h, e + ld l, a + add hl, hl +afxBnkAdr2: + ld bc, 0 ; Address of the effect offsets table + add hl, bc + ld c, (hl) + inc hl + ld b, (hl) + add hl, bc ; The effect address is obtained in hl + push hl ; Save the effect address on the stack + jp DoPlay + +; --------------------------------------------------------------; +; Launch the effect on a free channel. If no free channels, ; +; the longest sounding is selected. ; +; ; +; Input: A = Effect number 0..255 ; +; --------------------------------------------------------------; +AFXPlay: + push af + ld a, c + ld (ReleaseLoSMC), a ; SMC> + ld a, b + ld (ReleaseHiSMC), a ; SMC> + pop af + ld de, 0 ; In DE the longest time in search + ld h, e + ld l, a + add hl, hl +afxBnkAdr1: + ld bc, 0 ; Address of the effect offsets table + add hl, bc + ld c, (hl) + inc hl + ld b, (hl) + add hl, bc ; The effect address is obtained in hl + push hl ; Save the effect address on the stack + ld hl, afxChDesc ; Empty channel search + ld b, 3 +afxPlay0: + inc hl + inc hl + ld a, (hl) ; Compare the channel time with the largest + inc hl + cp e + jr c, afxPlay1 + ld c, a + ld a, (hl) + cp d + jr c, afxPlay1 + ld e, c ; Remember the longest time + ld d, a + push hl ; Remember the channel address+3 in IX + pop ix +afxPlay1: + ld a, 5 + add a, l ; Add(hl, a) } + ld l, a ; } + adc a, h ; } + sub l ; } + ld h, a ; } + djnz afxPlay0 +DoPlay: + pop de ; Take the effect address from the stack + ld (ix-3), e ; Put in the channel descriptor + ld (ix-2), d + ld (ix-1), b ; Zero the playing time + ld (ix-0), b +ReleaseLoSMC equ $+3 + ld (ix+3), AFXSMC ; UnusedSettingsFeatures + "UpdBios", -- DEFINES.INC --> UnusedSettingsFeatures + "TypRate", -- DEFINES.INC --> UnusedSettingsFeatures + "TypDelay", -- DEFINES.INC --> UnusedSettingsFeatures }, - [2]={ - "ScreenY", - "ScreenX", - "FrameInt", - "VSync", - "QuickStartROM", - "TrDosA", - "TrDosB", - "TrDosC", - "TrDosD", - --"SetTime", + [2]={ + "PlayStartUpSound", -- 1 + "LoadZXroms", -- 2 + "QS_SetUpHardware", -- 3 + "QS_SetUpZxRom", -- 4 + "TrDosA", -- 5 + "TrDosB", -- 6 + "TrDosC", -- 7 + "TrDosD", -- 8 + "SetTime", -- 9 DEFINES.INC --> NEW_FEATUREDEFINES.INC --> HDDwriteProtect + --"HddWrPr", -- 10 DEFINES.INC --> HDDwriteProtect + -- 11 + -- 12 + -- 13 + -- 14 + -- 15 + -- 16 + -- 17 } } + DeleteValueByDEFINE(SettingsTabsOrder,"NEW_FEATURE","SetTime") + --DeleteValueByDEFINE(SettingsTabsOrder,"HDDwriteProtect","HddWrPr") + DeleteValueByDEFINE(SettingsTabsOrder,"UnusedSettingsFeatures","MemTest") + DeleteValueByDEFINE(SettingsTabsOrder,"UnusedSettingsFeatures","UpdBios") + DeleteValueByDEFINE(SettingsTabsOrder,"UnusedSettingsFeatures","TypRate") + DeleteValueByDEFINE(SettingsTabsOrder,"UnusedSettingsFeatures","TypDelay") + -- DeleteValueByDEFINE(SettingsTabsOrder,"UnusedSettingsFeatures","") + -- DeleteValueByDEFINE(SettingsTabsOrder,"UnusedSettingsFeatures","") ENDLUA ; @@ -61,15 +85,6 @@ @.itemName? EQU $ DEFINE TmpDef itemName? LUA ALLPASS - function get_key_for_value(t, value) - for column=1,2 do - for line,name in pairs(t[column]) do - if name==value then return column,line end - end - end - return nil - end - local tmpName = sj.get_define("TmpDef") local column,line = get_key_for_value(SettingsTabsOrder, tmpName) if (column == nil or line == nil) then sj.error("Settings Tab not found",tmpName) end @@ -133,99 +148,108 @@ folderLine EQU 1 ENDIF ; -firstColumn EQU 03 ; смещение по X для первого столбца -secondColumn EQU 43 ; смещение по X для второго столбца -firstLine EQU 07 ; смещение по Y для первой строки +firstColumn EQU 03 ; смещение по X для первого столбца +secondColumn EQU 43 ; смещение по X для второго столбца +firstLine EQU 07 ; смещение по Y для первой строки SettingsItemsTabs: _mSETitemParams Lang - DW OnChangeAction.setLang ; действие при изменении - IF NEW_FEATURE : DB paramLine : ENDIF ; тип параметра (строка со значением или каталог) - DB columnNum,lineNum ; столбец, строка - DB paramName ; Название параметра - DB #0E,%00000100,%00000100 ; CMOS, MASK - DB msgStrings.valLangEng ; 1-й вариант параметра - DB msgStrings.valLangRus ; 2-й вариант параметра + DW OnChangeAction.setLang ; действие при изменении + IF NEW_FEATURE : DB paramLine : ENDIF ; тип параметра (строка со значением или каталог) + DB columnNum,lineNum ; столбец, строка + DB paramName ; Название параметра + DW CMOS_CELL.BootUpParams.Mask.Language : DB %0000'0100 ; CMOS : MASK + DB msgStrings.valLangEng ; 1-й вариант параметра + DB msgStrings.valLangRus ; 2-й вариант параметра - _mSETitemParams MemTest - DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF - DB columnNum,lineNum - DB paramName - DB #0E,%10000000,%10000000 - DB msgStrings.valDisabled - DB msgStrings.valEnabled + + IF UnusedSettingsFeatures ; !TODO + _mSETitemParams MemTest + DW OnChangeAction.nothing + IF NEW_FEATURE : DB paramLine : ENDIF + DB columnNum,lineNum + DB paramName + DW CMOS_CELL.BootUpParams.Mask.MemTest : DB %1000'0000 + DB msgStrings.valDisabled + DB msgStrings.valEnabled + ENDIF _mSETitemParams SaveRAMdrvs DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #0E,%01000000,%01000000 + DW CMOS_CELL.BootUpParams.Mask.SaveRAMdisks : DB %0100'0000 DB msgStrings.valDisabled DB msgStrings.valEnabled - _mSETitemParams UpdBios - DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF - DB columnNum,lineNum - DB paramName - DB #0E,%00100000,%00100000 - DB msgStrings.valDisabled - DB msgStrings.valEnabled + IF UnusedSettingsFeatures ; !TODO + _mSETitemParams UpdBios + DW OnChangeAction.nothing + IF NEW_FEATURE : DB paramLine : ENDIF + DB columnNum,lineNum + DB paramName + DW CMOS_CELL.BootUpParams.Mask.UpdBios : DB %0010'0000 + DB msgStrings.valDisabled + DB msgStrings.valEnabled + ENDIF _mSETitemParams StartDelay DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #0E,%00011000,%00010000 + DW CMOS_CELL.BootUpParams.Mask.StartDelay : DB %0001'0000 DB msgStrings.valDisabled - DB msgStrings.valNormal - DB msgStrings.valEnabled + DB msgStrings.valShort + DB msgStrings.valLong - _mSETitemParams TypRate - DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF - DB columnNum,lineNum - DB paramName - DB #0F,%00000111,%00000111 - DB msgStrings.val_6 - DB msgStrings.val_8 - DB msgStrings.val_10 - DB msgStrings.val_12 - DB msgStrings.val_15 - DB msgStrings.val_20 - DB msgStrings.val_24 - DB msgStrings.val_30 + IF UnusedSettingsFeatures ; !TODO + _mSETitemParams TypRate + DW OnChangeAction.nothing + IF NEW_FEATURE : DB paramLine : ENDIF + DB columnNum,lineNum + DB paramName + DW CMOS_CELL.Typematic.Mask.Rate : DB %0000'0111 + DB msgStrings.val_6 + DB msgStrings.val_8 + DB msgStrings.val_10 + DB msgStrings.val_12 + DB msgStrings.val_15 + DB msgStrings.val_20 + DB msgStrings.val_24 + DB msgStrings.val_30 + ENDIF - _mSETitemParams TypDelay - DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF - DB columnNum,lineNum - DB paramName - DB #0F,%01100000,%01100000 - DB msgStrings.val_250 - DB msgStrings.val_500 - DB msgStrings.val_750 - DB msgStrings.val_1000 + IF UnusedSettingsFeatures ; !TODO + _mSETitemParams TypDelay + DW OnChangeAction.nothing + IF NEW_FEATURE : DB paramLine : ENDIF + DB columnNum,lineNum + DB paramName + DW CMOS_CELL.Typematic.Mask.Delay : DB %0110'0000 + DB msgStrings.val_250 + DB msgStrings.val_500 + DB msgStrings.val_750 + DB msgStrings.val_1000 + ENDIF _mSETitemParams RebootMsg DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #1D,%00000010,%00000010 + DW CMOS_CELL.Options.Mask.RebootMSG : DB %0000'0010 DB msgStrings.valDisabled DB msgStrings.valEnabled _mSETitemParams SysDsk DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #10,%00000111,%00000111 ; !!!!! + DW CMOS_CELL.BootDrives.Mask.SysDisk : DB %0000'0111 DB msgStrings.val1stFDD DB msgStrings.val2ndFDD DB msgStrings.val1stIDE @@ -237,10 +261,10 @@ SettingsItemsTabs: _mSETitemParams AltSysDsk DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #10,%01110000,%01110000 + DW CMOS_CELL.BootDrives.Mask.AltSysDisk : DB %0111'0000 DB msgStrings.val1stFDD DB msgStrings.val2ndFDD DB msgStrings.val1stIDE @@ -252,32 +276,32 @@ SettingsItemsTabs: _mSETitemParams FddFirst DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #11,%00000011,%00000000 + DW CMOS_CELL.DrivesSetup_1.Mask.FirstFDD : DB %0000'0000 DB msgStrings.valAuto -; DB msgStrings.val720 -; DB msgStrings.val1440 -; DB msgStrings.valDash6 + ; DB msgStrings.val720 + ; DB msgStrings.val1440 + ; DB msgStrings.valDash6 _mSETitemParams FddSecond DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #11,%00001100,%00000000 + DW CMOS_CELL.DrivesSetup_1.Mask.SecondFDD : DB %0000'0000 DB msgStrings.valAuto -; DB msgStrings.val720 -; DB msgStrings.val1440 -; DB msgStrings.valDash6 + ; DB msgStrings.val720 + ; DB msgStrings.val1440 + ; DB msgStrings.valDash6 _mSETitemParams PriIdeMA DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #11,%00110000,%00110000 + DW CMOS_CELL.DrivesSetup_1.Mask.PriIDEmaster : DB %0011'0000 DB msgStrings.valAuto DB msgStrings.valSetup DB msgStrings.valCdRom @@ -285,10 +309,10 @@ SettingsItemsTabs: _mSETitemParams PriIdeSl DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #11,%11000000,%11000000 + DW CMOS_CELL.DrivesSetup_1.Mask.PriIDEslave : DB %1100'0000 DB msgStrings.valAuto DB msgStrings.valSetup DB msgStrings.valCdRom @@ -296,10 +320,10 @@ SettingsItemsTabs: _mSETitemParams SecIdeMA DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #20,%00110000,%00110000 + DW CMOS_CELL.DrivesSetup_2.Mask.SecIDEmaster : DB %0011'0000 DB msgStrings.valAuto DB msgStrings.valSetup DB msgStrings.valCdRom @@ -307,30 +331,32 @@ SettingsItemsTabs: _mSETitemParams SecIdeSl DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #20,%11000000,%11000000 + DW CMOS_CELL.DrivesSetup_2.Mask.SecIDEslave : DB %1100'0000 DB msgStrings.valAuto DB msgStrings.valSetup DB msgStrings.valCdRom DB msgStrings.valDash6 - _mSETitemParams HddWrPr - DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF - DB columnNum,lineNum - DB paramName - DB #1D,%00000001,%00000001 - DB msgStrings.valDisabled - DB msgStrings.valEnabled + ; IF HDDwriteProtect + ; _mSETitemParams HddWrPr + ; DW OnChangeAction.nothing + ; IF NEW_FEATURE : DB paramLine : ENDIF + ; DB columnNum,lineNum + ; DB paramName + ; DW CMOS_CELL.Options.Mask.HDDwriteProtect : DB %0000'0001 + ; DB msgStrings.valDisabled + ; DB msgStrings.valEnabled + ; ENDIF _mSETitemParams ScreenY DW OnChangeAction.setXYpos - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #1F,%11110000,%11100000 + DW CMOS_CELL.ScreenPosition.Mask.X : DB %1110'0000 DB msgStrings.valMinus7 DB msgStrings.valMinus6 DB msgStrings.valMinus5 @@ -349,10 +375,10 @@ SettingsItemsTabs: _mSETitemParams ScreenX DW OnChangeAction.setXYpos - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #1F,%00001111,%00001110 + DW CMOS_CELL.ScreenPosition.Mask.Y : DB %0000'1110 DB msgStrings.valPlus7 DB msgStrings.valPlus6 DB msgStrings.valPlus5 @@ -371,10 +397,10 @@ SettingsItemsTabs: _mSETitemParams FrameInt DW OnChangeAction.setInt - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #1A,%00110000,%00110000 + DW CMOS_CELL.ScreenSET.Mask.Int : DB %0011'0000 DB msgStrings.valDash8 DB msgStrings.valScorpion DB msgStrings.valPentagon @@ -382,72 +408,120 @@ SettingsItemsTabs: _mSETitemParams VSync DW OnChangeAction.setVsinc - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #1A,%11000000,%10000000 + DW CMOS_CELL.ScreenSET.Mask.Sinc : DB %1000'0000 DB msgStrings.valDash8 DB msgStrings.val312_50 DB msgStrings.val320_49 _mSETitemParams QuickStartROM DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #0E,%00000001,%00000001 - DB msgStrings.valDisabled - DB msgStrings.valEnabled + DW CMOS_CELL.BootUpParams.Mask.QuickStartROM : DB %0000'0001 + DB msgStrings.valQuickStartSP + DB msgStrings.valSpectrum + + + _mSETitemParams QS_SetUpZxRom + DW OnChangeAction.nothing + IF NEW_FEATURE : DB paramLine : ENDIF + DB columnNum,lineNum + DB paramName + DW CMOS_CELL.QuickStartSetUp.Mask.ZxRom : DB %0000'0101 + DB msgStrings.valQS_SetUpBasic128 + DB msgStrings.valQS_SetUpBasic48p + DB msgStrings.valQS_SetUpTrDos + DB msgStrings.valQS_SetUpExp + DB msgStrings.valQS_SetUpTrDos48 + DB msgStrings.valQS_SetUpBasic48 + + _mSETitemParams QS_SetUpHardware + DW OnChangeAction.nothing + IF NEW_FEATURE : DB paramLine : ENDIF + DB columnNum,lineNum + DB paramName + DW CMOS_CELL.QuickStartSetUp.Mask.Hardware : DB %0011'0000 + DB msgStrings.valSprinterZX + DB msgStrings.valPentagon48 + DB msgStrings.valPentagon128 + DB msgStrings.valPentagon512 + DB msgStrings.valScorpion256 + DB msgStrings.valZXSpectrum48 + DB msgStrings.valZXSpectrum128 + _mSETitemParams TrDosA DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #1E,%00000011,%00000010 + DW CMOS_CELL.TRDOSmount.Mask.A : DB %0000'0010 DB msgStrings.valDefault DB msgStrings.valFDD DB msgStrings.valHDD _mSETitemParams TrDosB DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #1E,%00001100,%00001000 + DW CMOS_CELL.TRDOSmount.Mask.B : DB %0000'1000 DB msgStrings.valDefault DB msgStrings.valFDD DB msgStrings.valHDD _mSETitemParams TrDosC DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #1E,%00110000,%00100000 + DW CMOS_CELL.TRDOSmount.Mask.C : DB %0010'0000 DB msgStrings.valDefault DB msgStrings.valFDD DB msgStrings.valHDD _mSETitemParams TrDosD DW OnChangeAction.nothing - IF NEW_FEATURE : DB paramLine : ENDIF + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #1E,%11000000,%10000000 + DW CMOS_CELL.TRDOSmount.Mask.D : DB %1000'0000 DB msgStrings.valDefault DB msgStrings.valFDD DB msgStrings.valHDD - IF NEW_FEATURE - _mSETitemParams SetTime - DW OnChangeAction.SetTime - DB folderLine + _mSETitemParams LoadZXroms + DW OnChangeAction.nothing + IF NEW_FEATURE : DB paramLine : ENDIF DB columnNum,lineNum DB paramName - DB #00,%00000000,%00000000 - DB msgStrings.valFolder - ENDIF + DW CMOS_CELL.Options.Mask.LoadZXroms : DB %0000'1000 + DB msgStrings.valLoadZXromsManually + DB msgStrings.valLoadZXromsFlag + DB msgStrings.valLoadZXromsCAD + + _mSETitemParams PlayStartUpSound + DW OnChangeAction.nothing + IF NEW_FEATURE : DB paramLine : ENDIF + DB columnNum,lineNum + DB paramName + DW CMOS_CELL.BootUpParams.Mask.BootSound : DB %0000'0010 + DB msgStrings.valDisabled + DB msgStrings.valEnabled + + IF NEW_FEATURE + _mSETitemParams SetTime + DW OnChangeAction.SetTime + DB folderLine + DB columnNum,lineNum + DB paramName + DB #00,%0000'0000,%0000'0000 + DB msgStrings.valFolder + ENDIF ;--------------------[Items Addresses table]--------------------[] SettingsItemsTabsAddrs: _mCreateSettingsItemsTabsAddrs @@ -495,132 +569,166 @@ SettingsItemsTabsAddrs: ; Не менять бездумно название метки msgStrings !!! Участвует в LUA макросе в этом же файле. tmp_Counter DEFL 0 msgStrings: - _mSetStr copyRightPeters, tmp_Counter : DZ 'Copyright (c) 2002 Peters Plus' - _mSetStr copyRightSPTeam, tmp_Counter : DZ 'Copyright (c) 2009-', SPTeam_year, ' Sprinter Team' - _mSetStr setupBiosVer, tmp_Counter : DZ 'Sprinter BIOS v', Disk_subsystem_ver_txt - _mSetStr setupCopyRight, tmp_Counter : DZ 'Copyright (c) 2002 Peters Plus, (c) 2009-', SPTeam_year, ' Sprinter Team' - _mSetStr setupUtilityVer, tmp_Counter : DZ 'SETUP Utility v', SetupVer - _mSetStr setupHelpStr1, tmp_Counter : DZ 'ESC : Quit F10 : Save & Exit Setup' - _mSetStr setupHelpStr2, tmp_Counter : DZ 'F2 : Save Values ',24,32,25,32,26,32,27,' : Select Item' ; коды стрелок вместе с пробелами: 24,32,25,32,26,32,27 - _mSetStr setupHelpStr3, tmp_Counter : DZ 'F5 : Old Values PU/PD/+/- : Modify' - _mSetStr setupHelpStr4, tmp_Counter : DZ 'F7 : Default Values F3 : Color ' - _mSetStr toSetupButton, tmp_Counter : DZ ' to enter SETUP' - _mSetStr forAltBootButton, tmp_Counter : DZ ' for Alternative boot' - _mSetStr cmosChecksumErr, tmp_Counter : DZ 'WARNING! CMOS CHECKSUM ERROR, DEFAULT VALUES SET!' - _mSetStr cmosDateTimeErr, tmp_Counter : DZ 'WARNING! CMOS DATE/TIME ERROR, DEFAULT VALUES SET!' - _mSetStr detectIdePrMA, tmp_Counter : DZ ' Detecting IDE Primary Master ... [Press F4 to skip]' - _mSetStr detectIdePrSL, tmp_Counter : DZ ' Detecting IDE Primary Slave ... [Press F4 to skip]' - _mSetStr detectIdeSecMA, tmp_Counter : DZ ' Detecting IDE Secondary Master ... [Press F4 to skip]' - _mSetStr detectIdeSecSL, tmp_Counter : DZ ' Detecting IDE Secondary Slave ... [Press F4 to skip]' - _mSetStr ideUnknown, tmp_Counter : DZ 'Unknown ' - _mSetStr ideNone, tmp_Counter : DZ 'None ' - _mSetStr ideSkiped, tmp_Counter : DZ 'Skipped ' - _mSetStr ideFail, tmp_Counter : DZ 'Fail ' ; !FIXIT strFail - _mSetStr spModel, tmp_Counter : DZ 'Model name: ' - _mSetStr spMemory, tmp_Counter : DZ 'Memory : ' - _mSetStr cmosFound, tmp_Counter : DZ 'CMOS : Found' - _mSetStr cmosNone, tmp_Counter : DZ 'CMOS : None' - _mSetStr memoryAvailable, tmp_Counter : DZ 'Available : ' -; _mSetStr unknownSTR1, tmp_Counter : DZ "7" -; _mSetStr unknownSTR2, tmp_Counter : DZ "8" - _mSetStr boardID, tmp_Counter : DZ 'Board ID : ' - _mSetStr bootFdd, tmp_Counter : DZ 'Start from Diskette... ' - _mSetStr bootHdd, tmp_Counter : DZ 'Start from Hard disk... ' - _mSetStr bootCd, tmp_Counter : DZ 'Start from CD-ROM... ' - _mSetStr bootRamDrv, tmp_Counter : DZ 'Start from RAM disk... ' - _mSetStr bootRecovery, tmp_Counter : DZ 'Starting recovery...' - _mSetStr bootAltDrv, tmp_Counter : DZ 'Alternative ' - _mSetStr bootFail, tmp_Counter : DZ 'fail' ; !FIXIT strFail - _mSetStr bootOk, tmp_Counter : DZ 'OK' - _mSetStr afterBootFail, tmp_Counter : DZ 'PRESS TO REBOOT, TO ENTER SETUP OR TO ZX-MODE . . .' + _mSetStr copyRightPeters, tmp_Counter : DZ 'Copyright (c) 2002 Peters Plus' + _mSetStr copyRightSPTeam, tmp_Counter : DZ 'Copyright (c) 2009-', SPTeam_year, ' Sprinter Team' + _mSetStr setupBiosVer, tmp_Counter : DZ 'Sprinter BIOS v', BIOS_ver_string + _mSetStr setupCopyRight, tmp_Counter : DZ 'Copyright (c) 2002 Peters Plus, (c) 2009-', SPTeam_year, ' Sprinter Team' + _mSetStr setupUtilityVer, tmp_Counter : DZ 'SETUP Utility v', SetupVer + _mSetStr setupHelpStr1, tmp_Counter : DZ 'ESC : Quit F10 : Save & Exit Setup' + _mSetStr setupHelpStr2, tmp_Counter : DZ 'F2 : Save Values ',24,32,25,32,26,32,27,' : Select Item' ; коды стрелок вместе с пробелами: 24,32,25,32,26,32,27 + _mSetStr setupHelpStr3, tmp_Counter : DZ 'F5 : Old Values PU/PD/+/- : Modify' + _mSetStr setupHelpStr4, tmp_Counter : DZ 'F7 : Default Values F3 : Color ' + _mSetStr toSetupButton, tmp_Counter : DZ ' to enter SETUP' +;_mSetStr forCtrlBootButton, tmp_Counter : DZ ' for Recovery boot' + _mSetStr forAltBootButton, tmp_Counter : DZ ' for Alternative boot' + _mSetStr cmosChecksumErr, tmp_Counter : DZ 'WARNING! CMOS CHECKSUM ERROR, DEFAULT VALUES SET!' + _mSetStr cmosDateTimeErr, tmp_Counter : DZ 'WARNING! CMOS DATE/TIME ERROR, DEFAULT VALUES SET!' + _mSetStr detectIdePrMA, tmp_Counter : DZ ' Detecting IDE Primary Master ... [Press F4 to skip]' + _mSetStr detectIdePrSL, tmp_Counter : DZ ' Detecting IDE Primary Slave ... [Press F4 to skip]' + _mSetStr detectIdeSecMA, tmp_Counter : DZ ' Detecting IDE Secondary Master ... [Press F4 to skip]' + _mSetStr detectIdeSecSL, tmp_Counter : DZ ' Detecting IDE Secondary Slave ... [Press F4 to skip]' + _mSetStr ideUnknown, tmp_Counter : DZ 'Unknown ' + _mSetStr ideNone, tmp_Counter : DZ 'None ' + _mSetStr ideSkiped, tmp_Counter : DZ 'Skipped ' + _mSetStr ideFail, tmp_Counter : DZ 'Fail ' ; !FIXIT strFail + _mSetStr spModel, tmp_Counter : DZ 'Model : ' +.str_ACEX_MODEL EQU $$$+7 ; указатель на строку ниже для патча апдейтером + _mSetStr spCNFver, tmp_Counter : DZ 'Core 1K30 : v' + _mSetStr spMemory, tmp_Counter : DZ 'Memory : ' + _mSetStr cmosFound, tmp_Counter : DZ 'CMOS : Found' + _mSetStr cmosNone, tmp_Counter : DZ 'CMOS : None' + _mSetStr memoryAvailable, tmp_Counter : DZ 'Available : ' +; _mSetStr unknownSTR1, tmp_Counter : DZ "7" +; _mSetStr unknownSTR2, tmp_Counter : DZ "8" + _mSetStr boardID, tmp_Counter : DZ 'Board ID : ' + _mSetStr bootFdd, tmp_Counter : DZ 'Boot from Diskette' +; _mSetStr bootHdd, tmp_Counter : DZ 'Boot from Hard disk ' + _mSetStr bootHdd, tmp_Counter : DZ 'Boot from HDD ' + _mSetStr bootCd, tmp_Counter : DZ 'Boot from CD-ROM ' + _mSetStr bootRamDrv, tmp_Counter : DZ 'Boot from RAM disk' + _mSetStr bootRecovery, tmp_Counter : DZ 'Starting recovery' + _mSetStr bootAltDrv, tmp_Counter : DZ 'Alternative ' + _mSetStr bootFail, tmp_Counter : DZ ' fail' ; !FIXIT strFail + _mSetStr bootOk, tmp_Counter : DZ ' OK' + _mSetStr afterBootFail, tmp_Counter : DZ 'PRESS TO REBOOT, TO ENTER SETUP OR TO ZX-MODE . . .' + _mSetStr errorZXmode, tmp_Counter : DZ 'Error! Spectrum mode launch failed. Press CTRL+ALT+DEL or RESET.' ; - _mSetStr parLang, tmp_Counter : DZ 'Language (Язык) : ' - _mSetStr valLangEng, tmp_Counter : DZ 'English ' - _mSetStr valLangRus, tmp_Counter : DZ 'Русский ' - _mSetStr parMemTest, tmp_Counter : DZ 'Memory Test : ' - _mSetStr valDisabled, tmp_Counter : DZ 'Disabled' - _mSetStr valEnabled, tmp_Counter : DZ 'Enabled ' - _mSetStr parSaveRAMdrvs, tmp_Counter : DZ 'Save RAM-disks : ' - _mSetStr parUpdBios, tmp_Counter : DZ 'Update BIOS : ' - _mSetStr parStartDelay, tmp_Counter : DZ 'Start Delay : ' - _mSetStr valNormal, tmp_Counter : DZ 'Normal ' - _mSetStr parTypRate, tmp_Counter : DZ 'Typematic Rate (Chars/Sec) : ' - _mSetStr val_6, tmp_Counter : DZ '6 ' - _mSetStr val_8, tmp_Counter : DZ '8 ' - _mSetStr val_10, tmp_Counter : DZ '10' - _mSetStr val_12, tmp_Counter : DZ '12' - _mSetStr val_15, tmp_Counter : DZ '15' - _mSetStr val_20, tmp_Counter : DZ '20' - _mSetStr val_24, tmp_Counter : DZ '24' - _mSetStr val_30, tmp_Counter : DZ '30' - _mSetStr parTypDelay, tmp_Counter : DZ 'Typematic Delay (Msec) : ' - _mSetStr val_250, tmp_Counter : DZ '250 ' - _mSetStr val_500, tmp_Counter : DZ '500 ' - _mSetStr val_750, tmp_Counter : DZ '750 ' - _mSetStr val_1000, tmp_Counter : DZ '1000' - _mSetStr parRebootMsg, tmp_Counter : DZ 'Reboot message : ' - _mSetStr parSysDsk, tmp_Counter : DZ 'System Disk : ' - _mSetStr val1stFDD, tmp_Counter : DZ '1-st FDD' - _mSetStr val2ndFDD, tmp_Counter : DZ '2-nd FDD' - _mSetStr val1stIDE, tmp_Counter : DZ '1-st IDE' - _mSetStr val2ndIDE, tmp_Counter : DZ '2-nd IDE' - _mSetStr val3rdIDE, tmp_Counter : DZ '3-rd IDE' - _mSetStr val4thIDE, tmp_Counter : DZ '4-th IDE' - _mSetStr valRamDsk, tmp_Counter : DZ 'RAM-DISK' - _mSetStr valRecovery, tmp_Counter : DZ 'RECOVERY' - _mSetStr parAltSysDsk, tmp_Counter : DZ 'Alt. System Disk : ' - _mSetStr parFddFirst, tmp_Counter : DZ 'FDD First : ' - _mSetStr valAuto, tmp_Counter : DZ 'Auto ' -; _mSetStr val720, tmp_Counter : DZ '720K ' -; _mSetStr val1440, tmp_Counter : DZ '1.44M ' - _mSetStr valDash6, tmp_Counter : DZ '------' - _mSetStr parFddSecond, tmp_Counter : DZ 'FDD Second : ' - _mSetStr parPriIdeMA, tmp_Counter : DZ 'Primary IDE Master : ' - _mSetStr valSetup, tmp_Counter : DZ 'Setup ' - _mSetStr valCdRom, tmp_Counter : DZ 'CD-ROM' - _mSetStr parPriIdeSl, tmp_Counter : DZ 'Primary IDE Slave : ' - _mSetStr parSecIdeMA, tmp_Counter : DZ 'Secondary IDE Master : ' - _mSetStr parSecIdeSl, tmp_Counter : DZ 'Secondary IDE Slave : ' - _mSetStr parHddWrPr, tmp_Counter : DZ 'HDD Write protect : ' - _mSetStr parScreenY, tmp_Counter : DZ 'Y-Screen position : ' - _mSetStr valMinus7, tmp_Counter : DZ '-7' - _mSetStr valMinus6, tmp_Counter : DZ '-6' - _mSetStr valMinus5, tmp_Counter : DZ '-5' - _mSetStr valMinus4, tmp_Counter : DZ '-4' - _mSetStr valMinus3, tmp_Counter : DZ '-3' - _mSetStr valMinus2, tmp_Counter : DZ '-2' - _mSetStr valMinus1, tmp_Counter : DZ '-1' - _mSetStr val_0, tmp_Counter : DZ ' 0' - _mSetStr valPlus1, tmp_Counter : DZ '+1' - _mSetStr valPlus2, tmp_Counter : DZ '+2' - _mSetStr valPlus3, tmp_Counter : DZ '+3' - _mSetStr valPlus4, tmp_Counter : DZ '+4' - _mSetStr valPlus5, tmp_Counter : DZ '+5' - _mSetStr valPlus6, tmp_Counter : DZ '+6' - _mSetStr valPlus7, tmp_Counter : DZ '+7' - _mSetStr parScreenX, tmp_Counter : DZ 'X-Screen position : ' - _mSetStr parFrameInt, tmp_Counter : DZ 'Frame interrupt : ' - _mSetStr valDash8, tmp_Counter : DZ '--------' - _mSetStr valScorpion, tmp_Counter : DZ 'Scorpion' - _mSetStr valPentagon, tmp_Counter : DZ 'Pentagon' - _mSetStr valSpectrum, tmp_Counter : DZ 'Spectrum' - _mSetStr parVSync, tmp_Counter : DZ 'V-synchronization : ' - _mSetStr val312_50, tmp_Counter : DZ '312/50Hz' - _mSetStr val320_49, tmp_Counter : DZ '320/49Hz' - _mSetStr parQuickStartROM, tmp_Counter : DZ 'Quick ROM Start : ' - _mSetStr parTrDosA, tmp_Counter : DZ 'TR DOS A:> : ' - _mSetStr valDefault, tmp_Counter : DZ 'Default' - _mSetStr valFDD, tmp_Counter : DZ 'FDD ' ; ????? подумать какие варианты возможны - _mSetStr valHDD, tmp_Counter : DZ 'HDD ' ; ????? подумать какие варианты возможны - _mSetStr parTrDosB, tmp_Counter : DZ 'TR DOS B:> : ' - _mSetStr parTrDosC, tmp_Counter : DZ 'TR DOS C:> : ' - _mSetStr parTrDosD, tmp_Counter : DZ 'TR DOS D:> : ' + _mSetStr parLang, tmp_Counter : DZ 'Language (язык) : ' + _mSetStr valLangEng, tmp_Counter : DZ 'English ' + _mSetStr valLangRus, tmp_Counter : DZ 'Русский ' + _mSetStr parMemTest, tmp_Counter : DZ 'Memory test : ' + _mSetStr valDisabled, tmp_Counter : DZ 'Disabled' + _mSetStr valEnabled, tmp_Counter : DZ 'Enabled ' + _mSetStr parSaveRAMdrvs, tmp_Counter : DZ 'Save RAM-disks : ' + _mSetStr parUpdBios, tmp_Counter : DZ 'Update BIOS : ' + _mSetStr parStartDelay, tmp_Counter : DZ 'Start delay : ' + _mSetStr valShort, tmp_Counter : DZ 'Short ' + _mSetStr valLong, tmp_Counter : DZ 'Long ' + _mSetStr parTypRate, tmp_Counter : DZ 'Typematic rate (chars/sec) : ' + _mSetStr val_6, tmp_Counter : DZ '6 ' + _mSetStr val_8, tmp_Counter : DZ '8 ' + _mSetStr val_10, tmp_Counter : DZ '10' + _mSetStr val_12, tmp_Counter : DZ '12' + _mSetStr val_15, tmp_Counter : DZ '15' + _mSetStr val_20, tmp_Counter : DZ '20' + _mSetStr val_24, tmp_Counter : DZ '24' + _mSetStr val_30, tmp_Counter : DZ '30' + _mSetStr parTypDelay, tmp_Counter : DZ 'Typematic delay (Msec) : ' + _mSetStr val_250, tmp_Counter : DZ '250 ' + _mSetStr val_500, tmp_Counter : DZ '500 ' + _mSetStr val_750, tmp_Counter : DZ '750 ' + _mSetStr val_1000, tmp_Counter : DZ '1000' + _mSetStr parRebootMsg, tmp_Counter : DZ 'Reboot message : ' + _mSetStr parSysDsk, tmp_Counter : DZ 'System disk : ' + _mSetStr val1stFDD, tmp_Counter : DZ '1-st FDD' + _mSetStr val2ndFDD, tmp_Counter : DZ '2-nd FDD' + _mSetStr val1stIDE, tmp_Counter : DZ '1-st IDE' + _mSetStr val2ndIDE, tmp_Counter : DZ '2-nd IDE' + _mSetStr val3rdIDE, tmp_Counter : DZ '3-rd IDE' + _mSetStr val4thIDE, tmp_Counter : DZ '4-th IDE' + _mSetStr valRamDsk, tmp_Counter : DZ 'RAM-DISK' + _mSetStr valRecovery, tmp_Counter : DZ 'RECOVERY' + _mSetStr parAltSysDsk, tmp_Counter : DZ 'Alt. system disk : ' + _mSetStr parFddFirst, tmp_Counter : DZ 'FDD first : ' + _mSetStr valAuto, tmp_Counter : DZ 'Auto ' +; _mSetStr val720, tmp_Counter : DZ '720K ' +; _mSetStr val1440, tmp_Counter : DZ '1.44M ' + _mSetStr valDash6, tmp_Counter : DZ '------' + _mSetStr parFddSecond, tmp_Counter : DZ 'FDD second : ' + _mSetStr parPriIdeMA, tmp_Counter : DZ 'Primary IDE Master',#FF,' : ' + _mSetStr valSetup, tmp_Counter : DZ 'Setup ' + _mSetStr valCdRom, tmp_Counter : DZ 'CD-ROM' + _mSetStr parPriIdeSl, tmp_Counter : DZ 'Primary IDE Slave',#FF,' : ' + _mSetStr parSecIdeMA, tmp_Counter : DZ 'Secondary IDE Master',#FF,' : ' + _mSetStr parSecIdeSl, tmp_Counter : DZ 'Secondary IDE Slave',#FF,' : ' +; IF HDDwriteProtect +; _mSetStr parHddWrPr, tmp_Counter : DZ 'HDD write protect : ' +; ENDIF + _mSetStr parScreenY, tmp_Counter : DZ 'Y-screen position : ' + _mSetStr valMinus7, tmp_Counter : DZ '-7' + _mSetStr valMinus6, tmp_Counter : DZ '-6' + _mSetStr valMinus5, tmp_Counter : DZ '-5' + _mSetStr valMinus4, tmp_Counter : DZ '-4' + _mSetStr valMinus3, tmp_Counter : DZ '-3' + _mSetStr valMinus2, tmp_Counter : DZ '-2' + _mSetStr valMinus1, tmp_Counter : DZ '-1' + _mSetStr val_0, tmp_Counter : DZ ' 0' + _mSetStr valPlus1, tmp_Counter : DZ '+1' + _mSetStr valPlus2, tmp_Counter : DZ '+2' + _mSetStr valPlus3, tmp_Counter : DZ '+3' + _mSetStr valPlus4, tmp_Counter : DZ '+4' + _mSetStr valPlus5, tmp_Counter : DZ '+5' + _mSetStr valPlus6, tmp_Counter : DZ '+6' + _mSetStr valPlus7, tmp_Counter : DZ '+7' + _mSetStr parScreenX, tmp_Counter : DZ 'X-screen position : ' + _mSetStr parFrameInt, tmp_Counter : DZ 'Frame interrupt : ' + _mSetStr valDash8, tmp_Counter : DZ '--------' + _mSetStr valScorpion, tmp_Counter : DZ 'Scorpion' + _mSetStr valPentagon, tmp_Counter : DZ 'Pentagon' + _mSetStr valSpectrum, tmp_Counter : DZ 'Spectrum' + _mSetStr parVSync, tmp_Counter : DZ 'V-synchronization : ' + _mSetStr val312_50, tmp_Counter : DZ '312/50Hz' + _mSetStr val320_49, tmp_Counter : DZ '320/49Hz' + _mSetStr parQuickStartROM, tmp_Counter : DZ 'Run in mode : ' + _mSetStr valQuickStartSP, tmp_Counter : DZ 'Sprinter' + _mSetStr valDefault, tmp_Counter : DZ 'Default' + _mSetStr valFDD, tmp_Counter : DZ 'FDD ' ; ????? подумать какие варианты возможны + _mSetStr valHDD, tmp_Counter : DZ 'HDD ' ; ????? подумать какие варианты возможны + _mSetStr parTrDosA, tmp_Counter : DZ 'TR DOS A:> : ' + _mSetStr parTrDosB, tmp_Counter : DZ 'TR DOS B:> : ' + _mSetStr parTrDosC, tmp_Counter : DZ 'TR DOS C:> : ' + _mSetStr parTrDosD, tmp_Counter : DZ 'TR DOS D:> : ' + _mSetStr parPlayStartUpSound, tmp_Counter : DZ 'Startup sound : ' + _mSetStr parLoadZXroms, tmp_Counter : DZ 'Load ZX ROMs : ' + _mSetStr valLoadZXromsManually, tmp_Counter : DZ 'Manually ' + _mSetStr valLoadZXromsFlag, tmp_Counter : DZ 'By ZX flag' + _mSetStr valLoadZXromsCAD, tmp_Counter : DZ 'On restart' +; + _mSetStr parQS_SetUpHardware, tmp_Counter : DZ 'ZX Mode : ' + _mSetStr valSprinterZX, tmp_Counter : DZ 'Sprinter ZX ' + _mSetStr valPentagon48, tmp_Counter : DZ 'Pentagon 48 ' + _mSetStr valPentagon128, tmp_Counter : DZ 'Pentagon 128' + _mSetStr valPentagon512, tmp_Counter : DZ 'Pentagon 512' + _mSetStr valScorpion256, tmp_Counter : DZ 'Scorpion 256' + _mSetStr valZXSpectrum48, tmp_Counter : DZ 'Spectrum 48 ' + _mSetStr valZXSpectrum128, tmp_Counter : DZ 'Spectrum 128' +; + _mSetStr parQS_SetUpZxRom, tmp_Counter : DZ 'ZX Mode start in : ' + _mSetStr valQS_SetUpBasic128, tmp_Counter : DZ 'Basic 128' + _mSetStr valQS_SetUpBasic48p, tmp_Counter : DZ 'Basic 48+' + _mSetStr valQS_SetUpTrDos, tmp_Counter : DZ 'TR-DOS ' + _mSetStr valQS_SetUpExp, tmp_Counter : DZ 'Expansion' + _mSetStr valQS_SetUpTrDos48, tmp_Counter : DZ 'TR-DOS 48' + _mSetStr valQS_SetUpBasic48, tmp_Counter : DZ 'Basic 48 ' +; _mSetStrRus valLoadZXromsAuto, tmp_Counter : DZ 'On call ' IF NEW_FEATURE - _mSetStr parSetTime, tmp_Counter : DZ 'Date and Time setup : ' - _mSetStr valFolder, tmp_Counter : DB 16,'ENTER',17,0 + _mSetStr parSetTime, tmp_Counter : DZ 'Date and time setup : ' + _mSetStr valFolder, tmp_Counter : DB 16,'ENTER',17,0 ENDIF - IF DEBUG - _mSetStr testBIOSmsg, tmp_Counter : DZ 'Test build! ',BUILD_DATE,', ',__TIME__ + IF BETA_BUILD > 0 + _mSetStr extBIOSmsg, tmp_Counter : DZ 'Test build! ',BUILD_DATE,', ',__TIME__ + ELSE + _mSetStr extBIOSmsg, tmp_Counter : DZ 'Release ',RELEASE_BUILD_DATE ENDIF ; @@ -641,132 +749,165 @@ MSG_ENG.size EQU $-MSG_ENG ;================================================================================================================================== tmp_Counter = 0 msgRusStrings: - _mSetStrRus copyRightPeters, tmp_Counter : DZ 'Copyright (c) 2002 Peters Plus' - _mSetStrRus copyRightSPTeam, tmp_Counter : DZ 'Copyright (c) 2009-', SPTeam_year, ' Sprinter Team' - _mSetStrRus setupBiosVer, tmp_Counter : DZ 'Sprinter BIOS v', Disk_subsystem_ver_txt - _mSetStrRus setupCopyRight, tmp_Counter : DZ 'Copyright (c) 2002 Peters Plus, (c) 2009-', SPTeam_year, ' Sprinter Team' - _mSetStrRus setupUtilityVer, tmp_Counter : DZ 'SETUP Utility v', SetupVer - _mSetStrRus setupHelpStr1, tmp_Counter : DZ 'ESC : Выйти F10 : Сохранить и выйти' - _mSetStrRus setupHelpStr2, tmp_Counter : DZ 'F2 : Сохранить значения ',24,32,25,32,26,32,27,' : Выбор пункта' - _mSetStrRus setupHelpStr3, tmp_Counter : DZ 'F5 : Старые значения PU/PD/+/- : Изменение' - _mSetStrRus setupHelpStr4, tmp_Counter : DZ 'F7 : Значения по умолчанию F3 : Цвета ' - _mSetStrRus toSetupButton, tmp_Counter : DZ ' для входа в SETUP' - _mSetStrRus forAltBootButton, tmp_Counter : DZ ' для Альтернативной загрузки' - _mSetStrRus cmosChecksumErr, tmp_Counter : DZ 'ВНИМАНИЕ! ОШИБКА КОНТРОЛЬНОЙ СУММЫ CMOS, УСТАНОВЛЕНЫ ЗНАЧЕНИЯ ПО УМОЛЧАНИЮ' - _mSetStrRus cmosDateTimeErr, tmp_Counter : DZ 'ВНИМАНИЕ! ОШИБКА ДАТЫ/ВРЕМЕНИ CMOS, УСТАНОВЛЕНЫ ЗНАЧЕНИЯ ПО УМОЛЧАНИЮ' - _mSetStrRus detectIdePrMA, tmp_Counter : DZ 'Определяем Первичный IDE Master ... [F4 для пропуска] ' - _mSetStrRus detectIdePrSL, tmp_Counter : DZ 'Определяем Первичный IDE Slave ... [F4 для пропуска] ' - _mSetStrRus detectIdeSecMA, tmp_Counter : DZ 'Определяем Вторичный IDE Master ... [F4 для пропуска] ' - _mSetStrRus detectIdeSecSL, tmp_Counter : DZ 'Определяем Вторичный IDE Slave ... [F4 для пропуска] ' - _mSetStrRus ideUnknown, tmp_Counter : DZ 'Неизвестный ' - _mSetStrRus ideNone, tmp_Counter : DZ 'Нет ' - _mSetStrRus ideSkiped, tmp_Counter : DZ 'Пропущен ' - _mSetStrRus ideFail, tmp_Counter : DZ 'Не определён ' - _mSetStrRus spModel, tmp_Counter : DZ 'Модель : ' - _mSetStrRus spMemory, tmp_Counter : DZ 'Память : ' - _mSetStrRus cmosFound, tmp_Counter : DZ 'CMOS : Найден' - _mSetStrRus cmosNone, tmp_Counter : DZ 'CMOS : Нет' - _mSetStrRus memoryAvailable, tmp_Counter : DZ 'Доступно : ' -; _mSetStrRus unknownSTR1, tmp_Counter : DZ '7" -; _mSetStrRus unknownSTR2, tmp_Counter : DZ '8" - _mSetStrRus boardID, tmp_Counter : DZ 'ID платы : ' - _mSetStrRus bootFdd, tmp_Counter : DZ 'Запуск с дискеты... ' - _mSetStrRus bootHdd, tmp_Counter : DZ 'Запуск с жесткого диска... ' - _mSetStrRus bootCd, tmp_Counter : DZ 'Запуск с CD-ROM... ' - _mSetStrRus bootRamDrv, tmp_Counter : DZ 'Запуск с RAM диска... ' - _mSetStrRus bootRecovery, tmp_Counter : DZ 'Запуск восстановления... ' - _mSetStrRus bootAltDrv, tmp_Counter : DZ 'Альтернативный ' - _mSetStrRus bootFail, tmp_Counter : DZ 'невозможен' - _mSetStrRus bootOk, tmp_Counter : DZ 'OK' - _mSetStrRus afterBootFail, tmp_Counter : DZ 'НАЖМИТЕ ДЛЯ ПЕРЕЗАГРУЗКИ, ДЛЯ НАСТРОЕК ИЛИ ДЛЯ ZX-MODE . . .' + _mSetStrRus copyRightPeters, tmp_Counter : DZ 'Copyright (c) 2002 Peters Plus' + _mSetStrRus copyRightSPTeam, tmp_Counter : DZ 'Copyright (c) 2009-', SPTeam_year, ' Sprinter Team' + _mSetStrRus setupBiosVer, tmp_Counter : DZ 'Sprinter BIOS v', BIOS_ver_string + _mSetStrRus setupCopyRight, tmp_Counter : DZ 'Copyright (c) 2002 Peters Plus, (c) 2009-', SPTeam_year, ' Sprinter Team' + _mSetStrRus setupUtilityVer, tmp_Counter : DZ 'SETUP Utility v', SetupVer + _mSetStrRus setupHelpStr1, tmp_Counter : DZ 'ESC : Выйти F10 : Сохранить и выйти' + _mSetStrRus setupHelpStr2, tmp_Counter : DZ 'F2 : Сохранить значения ',24,32,25,32,26,32,27,' : Выбор пункта' + _mSetStrRus setupHelpStr3, tmp_Counter : DZ 'F5 : Старые значения PU/PD/+/- : Изменение' + _mSetStrRus setupHelpStr4, tmp_Counter : DZ 'F7 : Значения по умолчанию F3 : Цвета ' + _mSetStrRus toSetupButton, tmp_Counter : DZ ' для входа в SETUP' +;_mSetStrRus forCtrlBootButton, tmp_Counter : DZ ' для загрузки Recovery' + _mSetStrRus forAltBootButton, tmp_Counter : DZ ' для Альтернативной загрузки' + _mSetStrRus cmosChecksumErr, tmp_Counter : DZ 'ВНИМАНИЕ! ОШИБКА КОНТРОЛЬНОЙ СУММЫ CMOS, УСТАНОВЛЕНЫ ЗНАЧЕНИЯ ПО УМОЛЧАНИЮ' + _mSetStrRus cmosDateTimeErr, tmp_Counter : DZ 'ВНИМАНИЕ! ОШИБКА ДАТЫ/ВРЕМЕНИ CMOS, УСТАНОВЛЕНЫ ЗНАЧЕНИЯ ПО УМОЛЧАНИЮ' + _mSetStrRus detectIdePrMA, tmp_Counter : DZ ' Определяем Первичный IDE Master ... [F4 для пропуска] ' + _mSetStrRus detectIdePrSL, tmp_Counter : DZ ' Определяем Первичный IDE Slave ... [F4 для пропуска]' + _mSetStrRus detectIdeSecMA, tmp_Counter : DZ ' Определяем Вторичный IDE Master ... [F4 для пропуска]' + _mSetStrRus detectIdeSecSL, tmp_Counter : DZ ' Определяем Вторичный IDE Slave ... [F4 для пропуска]' + _mSetStrRus ideUnknown, tmp_Counter : DZ 'Неизвестный ' + _mSetStrRus ideNone, tmp_Counter : DZ 'Нет ' + _mSetStrRus ideSkiped, tmp_Counter : DZ 'Пропущен ' + _mSetStrRus ideFail, tmp_Counter : DZ 'Не определён ' + _mSetStrRus spModel, tmp_Counter : DZ 'Модель : ' +.str_ACEX_MODEL EQU $$$+7 ; указатель на строку ниже для патча апдейтером ; !FIXIT ? вытягивать через FN_CRIPT.Acex_ver ? + _mSetStrRus spCNFver, tmp_Counter : DZ 'Ядро 1K30 : v' + _mSetStrRus spMemory, tmp_Counter : DZ 'Память : ' + _mSetStrRus cmosFound, tmp_Counter : DZ 'CMOS : Найден' + _mSetStrRus cmosNone, tmp_Counter : DZ 'CMOS : Нет' + _mSetStrRus memoryAvailable, tmp_Counter : DZ 'Доступно : ' +; _mSetStrRus unknownSTR1, tmp_Counter : DZ '7' +; _mSetStrRus unknownSTR2, tmp_Counter : DZ '8' + _mSetStrRus boardID, tmp_Counter : DZ 'ID платы : ' + _mSetStrRus bootFdd, tmp_Counter : DZ 'Запуск с дискеты' + _mSetStrRus bootHdd, tmp_Counter : DZ 'Запуск с HDD ' + _mSetStrRus bootCd, tmp_Counter : DZ 'Запуск с CD-ROM ' + _mSetStrRus bootRamDrv, tmp_Counter : DZ 'Запуск с RAM диска' + _mSetStrRus bootRecovery, tmp_Counter : DZ 'Запуск восстановления' + _mSetStrRus bootAltDrv, tmp_Counter : DZ 'Альтернативный ' + _mSetStrRus bootFail, tmp_Counter : DZ ' невозможен' + _mSetStrRus bootOk, tmp_Counter : DZ ' OK' + _mSetStrRus afterBootFail, tmp_Counter : DZ 'НАЖМИТЕ ДЛЯ ПЕРЕЗАГРУЗКИ, ДЛЯ НАСТРОЕК ИЛИ ДЛЯ ZX-MODE . . .' + _mSetStrRus errorZXmode, tmp_Counter : DZ 'Ошибка! Запуск режима Spectrum не удался. Нажмите CTRL+ALT+DEL или RESET.' ; - _mSetStrRus parLang, tmp_Counter : DZ 'Язык (Language) : ' - _mSetStrRus valLangEng, tmp_Counter : DZ 'English ' - _mSetStrRus valLangRus, tmp_Counter : DZ 'Русский ' - _mSetStrRus parMemTest, tmp_Counter : DZ 'Тестирование памяти : ' - _mSetStrRus valDisabled, tmp_Counter : DZ 'Отключено' - _mSetStrRus valEnabled, tmp_Counter : DZ 'Включено ' - _mSetStrRus parSaveRAMdrvs, tmp_Counter : DZ 'Сохранение RAM-дисков : ' - _mSetStrRus parUpdBios, tmp_Counter : DZ 'Обновление BIOS : ' - _mSetStrRus parStartDelay, tmp_Counter : DZ 'Начальное ожидание : ' - _mSetStrRus valNormal, tmp_Counter : DZ 'Обычное ' - _mSetStrRus parTypRate, tmp_Counter : DZ 'Скорость автоповтора : ' - _mSetStrRus val_6, tmp_Counter : DZ '6 ' - _mSetStrRus val_8, tmp_Counter : DZ '8 ' - _mSetStrRus val_10, tmp_Counter : DZ '10' - _mSetStrRus val_12, tmp_Counter : DZ '12' - _mSetStrRus val_15, tmp_Counter : DZ '15' - _mSetStrRus val_20, tmp_Counter : DZ '20' - _mSetStrRus val_24, tmp_Counter : DZ '24' - _mSetStrRus val_30, tmp_Counter : DZ '30' - _mSetStrRus parTypDelay, tmp_Counter : DZ 'Задержка автоповтора (Мсек): ' - _mSetStrRus val_250, tmp_Counter : DZ '250 ' - _mSetStrRus val_500, tmp_Counter : DZ '500 ' - _mSetStrRus val_750, tmp_Counter : DZ '750 ' - _mSetStrRus val_1000, tmp_Counter : DZ '1000' - _mSetStrRus parRebootMsg, tmp_Counter : DZ 'Сообщение о перезагрузке : ' - _mSetStrRus parSysDsk, tmp_Counter : DZ 'Системный диск : ' - _mSetStrRus val1stFDD, tmp_Counter : DZ '1-ый FDD' - _mSetStrRus val2ndFDD, tmp_Counter : DZ '2-ой FDD' - _mSetStrRus val1stIDE, tmp_Counter : DZ '1-ый IDE' - _mSetStrRus val2ndIDE, tmp_Counter : DZ '2-ой IDE' - _mSetStrRus val3rdIDE, tmp_Counter : DZ '3-ий IDE' - _mSetStrRus val4thIDE, tmp_Counter : DZ '4-ый IDE' - _mSetStrRus valRamDsk, tmp_Counter : DZ 'RAM-DISK' - _mSetStrRus valRecovery, tmp_Counter : DZ 'RECOVERY' - _mSetStrRus parAltSysDsk, tmp_Counter : DZ 'Алт. Системный диск : ' - _mSetStrRus parFddFirst, tmp_Counter : DZ 'FDD первый : ' - _mSetStrRus valAuto, tmp_Counter : DZ 'Авто ' -; _mSetStrRus val720, tmp_Counter : DZ '720K ' -; _mSetStrRus val1440, tmp_Counter : DZ '1.44M ' - _mSetStrRus valDash6, tmp_Counter : DZ '------' - _mSetStrRus parFddSecond, tmp_Counter : DZ 'FDD второй : ' - _mSetStrRus parPriIdeMA, tmp_Counter : DZ 'Primary IDE Master : ' - _mSetStrRus valSetup, tmp_Counter : DZ 'Setup ' - _mSetStrRus valCdRom, tmp_Counter : DZ 'CD-ROM' - _mSetStrRus parPriIdeSl, tmp_Counter : DZ 'Primary IDE Slave : ' - _mSetStrRus parSecIdeMA, tmp_Counter : DZ 'Secondary IDE Master : ' - _mSetStrRus parSecIdeSl, tmp_Counter : DZ 'Secondary IDE Slave : ' - _mSetStrRus parHddWrPr, tmp_Counter : DZ 'Защита записи на HDD : ' - _mSetStrRus parScreenY, tmp_Counter : DZ 'Сдвиг экрана по Y : ' - _mSetStrRus valMinus7, tmp_Counter : DZ '-7' - _mSetStrRus valMinus6, tmp_Counter : DZ '-6' - _mSetStrRus valMinus5, tmp_Counter : DZ '-5' - _mSetStrRus valMinus4, tmp_Counter : DZ '-4' - _mSetStrRus valMinus3, tmp_Counter : DZ '-3' - _mSetStrRus valMinus2, tmp_Counter : DZ '-2' - _mSetStrRus valMinus1, tmp_Counter : DZ '-1' - _mSetStrRus val_0, tmp_Counter : DZ ' 0' - _mSetStrRus valPlus1, tmp_Counter : DZ '+1' - _mSetStrRus valPlus2, tmp_Counter : DZ '+2' - _mSetStrRus valPlus3, tmp_Counter : DZ '+3' - _mSetStrRus valPlus4, tmp_Counter : DZ '+4' - _mSetStrRus valPlus5, tmp_Counter : DZ '+5' - _mSetStrRus valPlus6, tmp_Counter : DZ '+6' - _mSetStrRus valPlus7, tmp_Counter : DZ '+7' - _mSetStrRus parScreenX, tmp_Counter : DZ 'Сдвиг экрана по X : ' - _mSetStrRus parFrameInt, tmp_Counter : DZ 'Кадровое прерывание : ' - _mSetStrRus valDash8, tmp_Counter : DZ '--------' - _mSetStrRus valScorpion, tmp_Counter : DZ 'Скорпион' - _mSetStrRus valPentagon, tmp_Counter : DZ 'Пентагон' - _mSetStrRus valSpectrum, tmp_Counter : DZ 'Спектрум' - _mSetStrRus parVSync, tmp_Counter : DZ 'Верт. синхронизация : ' - _mSetStrRus val312_50, tmp_Counter : DZ '312/50Гц' - _mSetStrRus val320_49, tmp_Counter : DZ '320/49Гц' - _mSetStrRus parQuickStartROM, tmp_Counter : DZ 'Быстрый запуск ПЗУ : ' - _mSetStrRus parTrDosA, tmp_Counter : DZ 'TR DOS A:> : ' - _mSetStrRus valDefault, tmp_Counter : DZ 'По умолчанию' - _mSetStrRus valFDD, tmp_Counter : DZ 'FDD ' - _mSetStrRus valHDD, tmp_Counter : DZ 'HDD ' - _mSetStrRus parTrDosB, tmp_Counter : DZ 'TR DOS B:> : ' - _mSetStrRus parTrDosC, tmp_Counter : DZ 'TR DOS C:> : ' - _mSetStrRus parTrDosD, tmp_Counter : DZ 'TR DOS D:> : ' + _mSetStrRus parLang, tmp_Counter : DZ 'Язык (language) : ' + _mSetStrRus valLangEng, tmp_Counter : DZ 'English ' + _mSetStrRus valLangRus, tmp_Counter : DZ 'Русский ' + _mSetStrRus parMemTest, tmp_Counter : DZ 'Тестирование памяти : ' + _mSetStrRus valDisabled, tmp_Counter : DZ 'Отключено' + _mSetStrRus valEnabled, tmp_Counter : DZ 'Включено ' + _mSetStrRus parSaveRAMdrvs, tmp_Counter : DZ 'Сохранение RAM-дисков : ' + _mSetStrRus parUpdBios, tmp_Counter : DZ 'Обновление BIOS : ' + _mSetStrRus parStartDelay, tmp_Counter : DZ 'Начальное ожидание : ' + _mSetStrRus valShort, tmp_Counter : DZ 'Короткое ' + _mSetStrRus valLong, tmp_Counter : DZ 'Длинное ' + _mSetStrRus parTypRate, tmp_Counter : DZ 'Скорость автоповтора : ' + _mSetStrRus val_6, tmp_Counter : DZ '6 ' + _mSetStrRus val_8, tmp_Counter : DZ '8 ' + _mSetStrRus val_10, tmp_Counter : DZ '10' + _mSetStrRus val_12, tmp_Counter : DZ '12' + _mSetStrRus val_15, tmp_Counter : DZ '15' + _mSetStrRus val_20, tmp_Counter : DZ '20' + _mSetStrRus val_24, tmp_Counter : DZ '24' + _mSetStrRus val_30, tmp_Counter : DZ '30' + _mSetStrRus parTypDelay, tmp_Counter : DZ 'Задержка автоповтора (Мсек): ' + _mSetStrRus val_250, tmp_Counter : DZ '250 ' + _mSetStrRus val_500, tmp_Counter : DZ '500 ' + _mSetStrRus val_750, tmp_Counter : DZ '750 ' + _mSetStrRus val_1000, tmp_Counter : DZ '1000' + _mSetStrRus parRebootMsg, tmp_Counter : DZ 'Сообщение о перезагрузке : ' + _mSetStrRus parSysDsk, tmp_Counter : DZ 'Системный диск : ' + _mSetStrRus val1stFDD, tmp_Counter : DZ '1-ый FDD' + _mSetStrRus val2ndFDD, tmp_Counter : DZ '2-ой FDD' + _mSetStrRus val1stIDE, tmp_Counter : DZ '1-ый IDE' + _mSetStrRus val2ndIDE, tmp_Counter : DZ '2-ой IDE' + _mSetStrRus val3rdIDE, tmp_Counter : DZ '3-ий IDE' + _mSetStrRus val4thIDE, tmp_Counter : DZ '4-ый IDE' + _mSetStrRus valRamDsk, tmp_Counter : DZ 'RAM-DISK' + _mSetStrRus valRecovery, tmp_Counter : DZ 'RECOVERY' + _mSetStrRus parAltSysDsk, tmp_Counter : DZ 'Алт. Системный диск : ' + _mSetStrRus parFddFirst, tmp_Counter : DZ 'FDD первый : ' + _mSetStrRus valAuto, tmp_Counter : DZ 'Авто ' +; _mSetStrRus val720, tmp_Counter : DZ '720K ' +; _mSetStrRus val1440, tmp_Counter : DZ '1.44M ' + _mSetStrRus valDash6, tmp_Counter : DZ '------' + _mSetStrRus parFddSecond, tmp_Counter : DZ 'FDD второй : ' + _mSetStrRus parPriIdeMA, tmp_Counter : DZ 'Primary IDE Master',#FF,' : ' + _mSetStrRus valSetup, tmp_Counter : DZ 'Setup ' + _mSetStrRus valCdRom, tmp_Counter : DZ 'CD-ROM' + _mSetStrRus parPriIdeSl, tmp_Counter : DZ 'Primary IDE Slave',#FF,' : ' + _mSetStrRus parSecIdeMA, tmp_Counter : DZ 'Secondary IDE Master',#FF,' : ' + _mSetStrRus parSecIdeSl, tmp_Counter : DZ 'Secondary IDE Slave',#FF,' : ' +; IF HDDwriteProtect +; _mSetStrRus parHddWrPr, tmp_Counter : DZ 'Защита записи на HDD : ' +; ENDIF + _mSetStrRus parScreenY, tmp_Counter : DZ 'Сдвиг экрана по Y : ' + _mSetStrRus valMinus7, tmp_Counter : DZ '-7' + _mSetStrRus valMinus6, tmp_Counter : DZ '-6' + _mSetStrRus valMinus5, tmp_Counter : DZ '-5' + _mSetStrRus valMinus4, tmp_Counter : DZ '-4' + _mSetStrRus valMinus3, tmp_Counter : DZ '-3' + _mSetStrRus valMinus2, tmp_Counter : DZ '-2' + _mSetStrRus valMinus1, tmp_Counter : DZ '-1' + _mSetStrRus val_0, tmp_Counter : DZ ' 0' + _mSetStrRus valPlus1, tmp_Counter : DZ '+1' + _mSetStrRus valPlus2, tmp_Counter : DZ '+2' + _mSetStrRus valPlus3, tmp_Counter : DZ '+3' + _mSetStrRus valPlus4, tmp_Counter : DZ '+4' + _mSetStrRus valPlus5, tmp_Counter : DZ '+5' + _mSetStrRus valPlus6, tmp_Counter : DZ '+6' + _mSetStrRus valPlus7, tmp_Counter : DZ '+7' + _mSetStrRus parScreenX, tmp_Counter : DZ 'Сдвиг экрана по X : ' + _mSetStrRus parFrameInt, tmp_Counter : DZ 'Кадровое прерывание : ' + _mSetStrRus valDash8, tmp_Counter : DZ '--------' + _mSetStrRus valScorpion, tmp_Counter : DZ 'Скорпион' + _mSetStrRus valPentagon, tmp_Counter : DZ 'Пентагон' + _mSetStrRus valSpectrum, tmp_Counter : DZ 'Спектрум' + _mSetStrRus parVSync, tmp_Counter : DZ 'Верт. синхронизация : ' + _mSetStrRus val312_50, tmp_Counter : DZ '312/50Гц' + _mSetStrRus val320_49, tmp_Counter : DZ '320/49Гц' + _mSetStrRus parQuickStartROM, tmp_Counter : DZ 'Запуск в режиме : ' + _mSetStrRus valQuickStartSP, tmp_Counter : DZ 'Спринтер' + _mSetStrRus valDefault, tmp_Counter : DZ 'По умолчанию' + _mSetStrRus valFDD, tmp_Counter : DZ 'FDD ' + _mSetStrRus valHDD, tmp_Counter : DZ 'HDD ' + _mSetStrRus parTrDosA, tmp_Counter : DZ 'TR DOS A:> : ' + _mSetStrRus parTrDosB, tmp_Counter : DZ 'TR DOS B:> : ' + _mSetStrRus parTrDosC, tmp_Counter : DZ 'TR DOS C:> : ' + _mSetStrRus parTrDosD, tmp_Counter : DZ 'TR DOS D:> : ' + _mSetStrRus parPlayStartUpSound, tmp_Counter : DZ 'Стартовый звук : ' + _mSetStrRus parLoadZXroms, tmp_Counter : DZ 'Загружать ZX ПЗУ : ' + _mSetStrRus valLoadZXromsManually, tmp_Counter : DZ 'Вручную ' + _mSetStrRus valLoadZXromsFlag, tmp_Counter : DZ 'По флагу ZX ' + _mSetStrRus valLoadZXromsCAD, tmp_Counter : DZ 'При рестарте' +; + _mSetStrRus parQS_SetUpHardware, tmp_Counter : DZ 'Режим ZX : ' + _mSetStrRus valSprinterZX, tmp_Counter : DZ 'Спринтер ZX ' + _mSetStrRus valPentagon48, tmp_Counter : DZ 'Пентагон 48 ' + _mSetStrRus valPentagon128, tmp_Counter : DZ 'Пентагон 128' + _mSetStrRus valPentagon512, tmp_Counter : DZ 'Пентагон 512' + _mSetStrRus valScorpion256, tmp_Counter : DZ 'Скорпион 256' + _mSetStrRus valZXSpectrum48, tmp_Counter : DZ 'Спектрум 48 ' + _mSetStrRus valZXSpectrum128, tmp_Counter : DZ 'Спектрум 128' +; + _mSetStrRus parQS_SetUpZxRom, tmp_Counter : DZ 'Старт режима ZX в : ' + _mSetStrRus valQS_SetUpBasic128, tmp_Counter : DZ 'Basic 128' + _mSetStrRus valQS_SetUpBasic48p, tmp_Counter : DZ 'Basic 48+' + _mSetStrRus valQS_SetUpTrDos, tmp_Counter : DZ 'TR-DOS ' + _mSetStrRus valQS_SetUpExp, tmp_Counter : DZ 'Expansion' + _mSetStrRus valQS_SetUpTrDos48, tmp_Counter : DZ 'TR-DOS 48' + _mSetStrRus valQS_SetUpBasic48, tmp_Counter : DZ 'Basic 48 ' +; _mSetStrRus valLoadZXromsAuto, tmp_Counter : DZ 'При вызове ' IF NEW_FEATURE - _mSetStrRus parSetTime, tmp_Counter : DZ 'Дата и время : ' - _mSetStrRus valFolder, tmp_Counter : DB 16,'ВВОД',17,0 + _mSetStrRus parSetTime, tmp_Counter : DZ 'Дата и время : ' + _mSetStrRus valFolder, tmp_Counter : DB 16,'ВВОД',17,0 ENDIF - IF DEBUG - _mSetStrRus testBIOSmsg, tmp_Counter : DZ 'Тестовая сборка! ',BUILD_DATE,', ',__TIME__ + IF BETA_BUILD > 0 + _mSetStrRus extBIOSmsg, tmp_Counter : DZ 'Тестовая сборка! ',BUILD_DATE,', ',__TIME__ + ELSE + _mSetStrRus extBIOSmsg, tmp_Counter : DZ 'Релиз ',RELEASE_BUILD_DATE ENDIF ; MSG_RUS: @@ -774,5 +915,5 @@ MSG_RUS: MSG_RUS.size EQU $-MSG_RUS ;================================================================================================================================== ASSERT MSG_ENG.size = MSG_RUS.size, "ERROR IN MESSAGE STRINGS: RUS and ENG do not match" -; +MSG_TABLE.Size EQU MSG_RUS.size ; \ No newline at end of file diff --git a/src/bios/rom/SETUP/netherworld_8.afx b/src/bios/rom/SETUP/netherworld_8.afx new file mode 100755 index 0000000..f673bab Binary files /dev/null and b/src/bios/rom/SETUP/netherworld_8.afx differ diff --git a/src/bios/rom/SETUP/startup_sound.asm b/src/bios/rom/SETUP/startup_sound.asm new file mode 100644 index 0000000..f4980ea --- /dev/null +++ b/src/bios/rom/SETUP/startup_sound.asm @@ -0,0 +1,164 @@ +; CODE BY Александр -=TmK deMarche=- +; play frame +; use: af,hl,de,bc 251 +STARTUP_SOUND: LD HL,.BYTE_POS + LD A,(HL) + LD C,SP_SND.AY + ; + AND A + JR NZ,.no_init + ; + LD DE,7*256 + %0011'1011 + LD B,high SP_SND.AY.CTRL + OUT (C),D + LD B,high SP_SND.AY.DATA + OUT (C),E + ; +.no_init: CP .volDataSize + JR C,.play + ;-- mus off +.mute: XOR A + LD E,A +.offLp: CALL .set_regs + CP 14 + JR NZ,.offLp + ; + LD A,7 + DEC E + CALL .set_regs + RET + ; +.play: ; + ;--- set tone + LD HL,(.WORD_TONE) + ;A=0 + LD A,4 ;REG C +.playToneLp: LD B,high SP_SND.AY.CTRL + OUT (C),A + LD B,high SP_SND.AY.DATA + 1 + OUTI + INC A + CP 6 + JR NZ,.playToneLp + ; + LD (.WORD_TONE),HL + ;--- set volume +.playVol: LD HL,(.WORD_VOL) + LD A,10 + LD E,(HL) + INC HL +.playVolLp: CALL .set_regs + ; + LD (.WORD_VOL),HL + LD HL,.BYTE_POS + INC (HL) + RET + ; ; +.set_regs: LD B,high SP_SND.AY.CTRL + OUT (C),A + LD B,high SP_SND.AY.DATA + OUT (C),E + INC A + RET +;----------------------------------------------------------------------- +.BYTE_POS: DB 0 +.WORD_VOL: DW .volData +.WORD_TONE: DW .toneData +;----------------------------------------------------------------------- +.toneData: DW #022, #044, #088, #110, #220, #440 + DW #880, #440, #220, #110, #088, #044 + DW #022, #044, #088, #110, #220, #440 + DW #880, #440, #220, #110, #088, #044 + DW #022 +.volData: DB #02, #04, #06, #08, #0A, #0C + DB #0E, #0D, #0C, #0B, #0A, #09 + DB #08, #07, #06, #05, #04, #03 + DB #02, #06, #08, #0A, #0C, #0E + DB #0F +.volDataSize EQU $ - .volData + +.codeEnd: DISPLAY "StartUp Sound size: ",/A,.codeEnd - STARTUP_SOUND + + +/* +; CODE BY Александр -=TmK deMarche=- +; play frame +; use: af,hl,de,bc 251 +STARTUP_SOUND: LD HL,.BYTE_POS + LD A,(HL) + LD C,SP_SND.AY + ; + AND A + JR NZ,.no_init + ; + LD DE,7*256 + %0011'1011 + LD B,high SP_SND.AY.CTRL + OUT (C),D + LD B,high SP_SND.AY.DATA + OUT (C),E + ; +.no_init: CP .volDataSize + JR C,.play + ;-- mus off +.mute: XOR A + LD E,A +.offLp: CALL .set_regs + CP 14 + JR NZ,.offLp + ; + LD A,7 + DEC E + CALL .set_regs + RET + ; +.play: ; + ;--- set tone + LD HL,(.WORD_TONE) + ;A=0 + LD A,4 ;REG C +.playToneLp: LD B,high SP_SND.AY.CTRL + OUT (C),A + LD B,high SP_SND.AY.DATA + 1 + OUTI + INC A + CP 6 + JR NZ,.playToneLp + ; + LD (.WORD_TONE),HL + ;--- set volume +.playVol: LD HL,(.WORD_VOL) + LD A,10 + LD E,(HL) + INC HL +.playVolLp: CALL .set_regs + ; + LD (.WORD_VOL),HL + LD HL,.BYTE_POS + INC (HL) + RET + ; ; +.set_regs: LD B,high SP_SND.AY.CTRL + OUT (C),A + LD B,high SP_SND.AY.DATA + OUT (C),E + INC A + RET +;----------------------------------------------------------------------- +.BYTE_POS: DB 0 +.WORD_VOL: DW .volData +.WORD_TONE: DW .toneData +;----------------------------------------------------------------------- +.toneData: DW #022, #044, #088, #110, #220, #440 + DW #880, #440, #220, #110, #088, #044 + DW #022, #044, #088, #110, #220, #440 + DW #880, #440, #220, #110, #088, #044 + DW #022 +.volData: DB #02, #04, #06, #08, #0A, #0C + DB #0E, #0D, #0C, #0B, #0A, #09 + DB #08, #07, #06, #05, #04, #03 + DB #02, #06, #08, #0A, #0C, #0E + DB #0F +.volDataSize EQU $ - .volData + +.codeEnd: DISPLAY "StartUp Sound size: ",/A,.codeEnd - STARTUP_SOUND +*/ \ No newline at end of file diff --git a/src/bios/rom/ZX/ZX_FUNC.ASM b/src/bios/rom/ZX/ZX_FUNC.ASM new file mode 100644 index 0000000..eb57b64 --- /dev/null +++ b/src/bios/rom/ZX/ZX_FUNC.ASM @@ -0,0 +1,935 @@ +; +;----------------------------[ ??????????? ]----------------------------; +; TURBO_OFF: +; LD A,D_TBOFF +; OUT (SYS_PORT.ON),A +; RET +; +; TURBO_ON: +; LD A,D_TBON +; OUT (SYS_PORT.ON),A +; RET +; +; JP_HL: JP (HL) +; +;PRINT_LINE: +; LD A,(HL) +; INC HL +; CP 0FFh +; RET Z +; RST 10H +; JR PRINT_LINE +; +; JP RESET_128 +;-----------------------------------------------------------------------; +; + + +;-----------------------------------------------------------------------; +; ******* SERVICE ******* +;-----------------------------------------------------------------------; + +; коэффициент смещения по номеру таски +; MACRO GET_ZX_TASK_DATA_OFFSET +; RLCA +; RLCA +; RLCA +; RLCA +; AND #30 ; новая задача 0..3 +; ENDM + + +;------[ ДЕШИФРАЦИЯ КОМАНДНОЙ СТРОКИ,ПЕРЕДАННОЙ ДЛЯ "EXPANSION" ]-------; +COMAND_LINE: + LD HL,(#5C5D) ;!HARDCODE CH_ADR +COMAND_LOOP: + LD A,(HL) + INC HL + CP ":" + JR Z,COMAND_L1 + CP ZX_Char.carriage_return + JR NZ,COMAND_LOOP + RET + +COMAND_L1: + LD A,(HL) + CP ZX_Token.rem + RET NZ + INC HL +COMAND_OK: ; ОБНАРУЖЕНА КОМАНДА ДЛЯ 'expansion' + LD A,(HL) + INC HL + CP ':' + JP Z,MENU_S1 + CP ZX_Char.carriage_return + JP Z,MENU_S1 + ; + AND %1101'1111 + CP 'I' + JR Z,COMMAND_HARDWARE_MENU + ;CP 'T' + ;JR Z,TASK_SWITCH + DEC HL + POP BC + JP BASIC_MENU +MENU_S1: + POP BC + CALL SERVICE + JP SW_ROM_1 + +COMMAND_HARDWARE_MENU: + LD A,(HL) + INC HL + AND %1101'1111 + CP 'S' + RET NZ + ; + POP BC + CALL Hardware_Menu + JP SW_ROM_1 +;-----------------------------------------------------------------------; + + + +;-----------------------------------------------------------------------; +; *** UTILITES *** +;-----------------------------------------------------------------------; + +; C_0030: ; получить раб обл +; CALL_48X 0030h +; RET +C_19E8: ; очистить раб обл + CALL_48X #19E8 ;!HARDCODE + RET +C_1655: ; получить пространство + CALL_48X #1655 ;!HARDCODE + RET +CLS: +C_0D6B: CALL_48 #0D6B ;!HARDCODE + RET +CH_2: LD A,2 +C_1601: ; OPEN CHANEL + CALL_48 #1601 ;!HARDCODE + RET +;-----------------------------------------------------------------------; + + + + +;-----------------------------------------------------------------------; +; MANAGE_ZX_PAGES +;-----------------------------------------------------------------------; +;-------------------------------------------------------------------------------------------------------------------; +;Выбор в Setup, что грузить в vПЗУ при старте. Варианты: +;[x] 0 - Не грузить ПЗУ спектрума, инитить страницу #41 как в 3.04 +;[x] 1 - Грузит ПЗУ спектрума из ROM при старте если нет флага ZX +;[x] 2 - Грузит ПЗУ спектрума из ROM при каждом перезапуске (может быть опасно) +;-------------------------------------------------------------------------------------------------------------------; +; для входа в режим спектрума: +; 0. Проверка метки ZX +; 1. CONFIG_DE.CNF_PORT Тип тачки, как инитить память, размер ОЗУ, турба +; 2. CONFIG_DE.ZX_START страница vROM для запуска +; 3. Настройки экрана (INT, Sync) +; 4. Торможение памяти (port all mode) +; 5. Block_ID.vROM +; 6. Block_ID.vRAM + +; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ [___FOR ZX-MODE___] _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ; + + +;░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░; +; [ ] free zx pages! +; ????? SYS_PAGE.SHARED_BUFFER_256b +; +; [ ] Страница ОЗУ для скорпа в SLOT0 должна совпадать с нулевой страницей порта #7FFD + MODULE MANAGE_ZX_PAGES + +;-----------------------------------------------------------------------; +; Не портить DE +;Вход: A - TASK NUMBER +; GET_ZX_TASK_DATA: +; GET_ZX_TASK_DATA_OFFSET +; ADD A,_ZX_TASK_DATA +; LD C,A +; LD B,0 +; LD IX,SYS_PAGE.ZX_TASK.CURRENT +; ADD IX,BC ; данные новой задачи +; RET +;-----------------------------------------------------------------------; + + +;-----------------------------------------------------------------------; +;ВХОД: HL - список страниц +; E - 0 = 128kb, 1 = 512kb +INIT_vRAM: XOR A +.set_1ffd: LD BC,#1FFD + OUT (C),A + ; set 128 + LD B,#7F + LD D,%0000'0000 + CALL SET_7FFD + ; + XOR A + OUT (C),A + BIT 0,E ; 128/512 + RET Z + ; set 128 + 384 + LD A,SYS_PORT.CNF_512 + SYS_PORT.CNF_0 + SYS_PORT.TURBO.ON + OUT (SYS_PORT.ROM),A + ; + LD D,%0100'0000 + CALL SET_7FFD + LD D,%1000'0000 + CALL SET_7FFD + LD D,%1100'0000 + CALL SET_7FFD + ; + XOR A + OUT (C),A + RET +;-----------------------------------------------------------------------; + +;-----------------------------------------------------------------------; +;ВХОД: HL - список страниц +; D - начальное значение для 7FFD +SET_7FFD: LD A,(HL) + OUT (C),D + OUT (SLOT3),A + INC HL + INC D + BIT 3,D ; количество страниц + JR Z,SET_7FFD + RET +;-----------------------------------------------------------------------; + +;-----------------------------------------------------------------------; +;Вход: HL - буфер страниц (SLOT1..SLOT2) на которые маппим (всегда 11 шт.) +; Первый байт списка - RAM BLOCK ID. Далее как угодно номера +; страниц для каждого типа страницы vROM. Если какая-то страница +; vROM не используется, то ставится #FF +INIT_vROM: LD A,(HL) + OR A + SCF + RET Z + INC A + JR NZ,.free_pages + LD (HL),A + JR .set_vROM + ; +.free_pages: LD A,(SYS_PAGE.Block_ID.vROM) + CP (HL) + EX DE,HL + LD C,BIOS.FreeMem + CALL NZ,ToBIOS_FromEXT + EX DE,HL + ; + LD A,(HL) +.set_vROM: LD (SYS_PAGE.Block_ID.vROM),A + ; установка портов ROM + LD DE,.PORTS + LD B,.PORTS.Size +.loop: PUSH BC + INC HL + LD A,(HL) + CP #FF + JR NZ,.not_Spec_Page + LD A,Spec_Page +.not_Spec_Page: LD B,A + LD A,(DE) + INC DE + PUSH DE + PUSH HL + LD C,BIOS.SET_PORTS + CALL ToBIOS_FromEXT + ;CALL SET_PORTS + POP HL + POP DE + POP BC + DJNZ .loop + ; установка метки ZX если рамблок не 0 + LD A,(SYS_PAGE.Block_ID.vROM) + OR A + RET Z + ; +.set_ZX_flag: IN A,(SLOT3) + LD D,A + LD A,Spec_Page + OUT (SLOT3),A + ; + LD HL,'XZ' + LD (Spec_Page.flag_Z),HL + ; + LD A,D + OUT (SLOT3),A + RET + ; +.PORTS: DB ACEX.vROM.BASIC_128 ; ROM-ID - BASIC 128 + DB ACEX.vROM.BASIC_48 ; ROM-ID - BASIC 48 + DB ACEX.vROM.TR_DOS ; ROM-ID - TR-DOS + DB ACEX.vROM.ZX_EXPANSION ; ROM-ID - EXPANSION + DB ACEX.vROM.ZX_BIOS_1 ; ROM-ID - BIOS-1 + DB ACEX.vROM.ZX_BIOS_2 ; ROM-ID - BIOS-2 + DB ACEX.vROM.BASIC_128_2 ; BASIC 128 - 2 + DB ACEX.vROM.BASIC_48_2 ; BASIC 48 - 2 + DB ACEX.vROM.TR_DOS_2 ; TR-DOS - 2 + DB ACEX.vROM.ZX_EXPANSION_2; BIOS (ZX_EXP) - 2 +.PORTS.Size EQU $-.PORTS +;-----------------------------------------------------------------------; + +;!FIXIT +;-------------[Выделение/освобождение/инит страниц спектрума]-----------; +;вход: рег B: +; FN 0x +; 0 - зарезервировано +; 1 - выделение памяти Pentagon 48k. 3 страницы +; 2 - выделение памяти Pentagon 128k. 2+6 страницы +; 3 - выделение памяти Pentagon 512k. 2+30 страницы +; 4 - выделение памяти Scorpion 256k. 2+6+8 страницы +; 5..15 - зарезервированы +; FN 1x +; 16 - получить рамблоки инициализированных vROM и VRAM +; 17..31 - зарезервированы +; FN 2x ;!TODO +; 32 - зарезервировано +; 33 - выделение памяти Spectrum 48k и инит 1-й страниц vROM +; 34 - выделение памяти Pentagon 128k и инит 3-х страниц vROM +; 35 - выделение памяти Pentagon 512k и инит 3-х страниц vROM +; 36 - выделение памяти Scorpion 256k и инит 3-х страниц vROM +; 33..63 - зарезервированы +; FN 4x +; 64 - освободить рамблоки vROM и vRAM +; 65 - освободить рамблок vRAM +; 66 - освободить рамблок vROM +; 65..127 - зарезервированы +; FN 8x +; 128 - инициализировать свой набор страниц vROM +; +; рег HL: при рег B[7]=1 адрес страниц (11 шт): +; byte1 - RAM block ID, byte2..11 - страницы для vROM - ZXSlot: 1,2,3(=0),расширенная +;выход: CF = 0: HL - номера рамблоков для режимов 0..16. H=vRAM, L=vROM +; CF = 1: A - номер ошибки +; +;если стэк находится в третьем слоте, то вызов с выключенными прерываниями +FN_ENTRANCE: ;!TODO A - TASK NUMBER + AND A + ; LD A,BIOS.Error.NotSupported + ; SCF + ; RET NZ + ; CCF + ; + EXX + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (C),A + EXX + ; + LD (SYS_PAGE.SP_SAVE),SP + LD SP,SYS_PAGE.SYS_SP + LD DE,.EXIT + PUSH DE + ;-----------------------------------; + ; Sub FN #8x +.API: BIT 7,B + JR NZ,INIT_vROM ; B = 128 + ; Sub FN #4x + BIT 6,B + JR NZ,FREE_vMEMORY ; B = 64..127 + ; Sub FN #2x ;!TODO ; [ ] free zx pages! + ;BIT 5,B + ;JR NZ, ; B = 32..63 + ; Sub FN #1x + BIT 4,B + JR Z,.x0x_FN ; B = 16 + ; +.GET_RAMBLOCK_IDs: ;Вход: A - TASK NUMBER. Выход: H - vRAM block ID, L - vROM block ID + LD HL,(SYS_PAGE.Block_IDs) + RET + ; + ; Sub FN #0x +.x0x_FN: DEC B + JR Z,GET_48k_MEM ; B = 1 + DEC B + JR Z,GET_128k_MEM ; B = 2 + DEC B + JR Z,GET_512k_MEM ; B = 3 + DEC B + JR Z,GET_SCORP_RAM ; B = 4 + ;-----------------------------------; + LD A,BIOS.Error.InvalidSubFunction + SCF + RET + ; +.EXIT: LD SP,(SYS_PAGE.SP_SAVE) + EXX + OUT (C),B + EXX + RET +;-----------------------------------------------------------------------; + + +;-----------------------------------------------------------------------; +FREE_vMEMORY: LD A,B + AND 3 + JR Z,FREE_ALL_vMEMORY ; 0 + DEC A + JR Z,FREE_vRAM ; 1 + DEC A + JR Z,FREE_vROM ; 2 + LD A,BIOS.Error.InvalidSubFunction + SCF + RET +;--------------; +FREE_vRAM: LD A,(SYS_PAGE.Block_ID.vRAM) + OR A + RET Z + LD C,BIOS.FreeMem + CALL ToBIOS_FromEXT + LD A,0 + LD (SYS_PAGE.Block_ID.vRAM),A + RET +;--------------; +FREE_ALL_vMEMORY: + CALL FREE_vRAM +;--------------; +FREE_vROM: LD A,(SYS_PAGE.Block_ID.vROM) + OR A + RET Z + LD C,BIOS.FreeMem + CALL ToBIOS_FromEXT + PUSH AF + XOR A + LD (SYS_PAGE.Block_ID.vROM),A +;--------------; +RES_FLAG_ZXvROM: ; не должно портить DE + EX AF,AF' + IN A,(SLOT3) + EX AF,AF' + LD A,Spec_Page + OUT (SLOT3),A + XOR A + LD (Spec_Page.flag_Z),A + LD (Spec_Page.flag_X),A + EX AF,AF' + OUT (SLOT3),A + POP AF + RET +;-----------------------------------------------------------------------; + +;-----------------------------------------------------------------------; +;Выполняется для выделения трёх страниц ОЗУ 48k +GET_48k_MEM: LD D,BIOS.ZX_MEMORY_MANAGER.MODE_48k + JR GET_XXX_MEM +;Выполняется для инита 3 страниц ОЗУ 48k и 29 страниц ОЗУ Pent512k +GET_512k_MEM: LD D,BIOS.ZX_MEMORY_MANAGER.MODE_512k + JR GET_XXX_MEM +;Выполняется для выделения 3 страниц ОЗУ 48k и 5 страниц ОЗУ 128k тачек +GET_128k_MEM: LD D,BIOS.ZX_MEMORY_MANAGER.MODE_128k + ;JR GET_XXX_MEM +GET_XXX_MEM: CALL FREE_vRAM +.init: LD B,D + LD C,BIOS.GetMem + CALL ToBIOS_FromEXT + RET C + LD (SYS_PAGE.Block_ID.vRAM),A + RET +;-----------------------------------------------------------------------; + + + +;-----------------------------------------------------------------------; +;Выполняется для выделения 3 страниц ОЗУ 48k и 14 страниц ОЗУ Scorp256k +;Вход: --- +;Выход: A - RAM block ID +GET_SCORP_RAM: CALL FREE_vRAM + ; выделить страницы скорпа + XOR A + LD DE,#F0D0 ; для фильтра. #F0 - маска, #D0 - страницы ISA #D0..#DF + LD BC,256*8 + #FF ; B - количество страниц, C - Метка конца рамблока + LD HL,SYS_PAGE.RAM_TABLE +.allocate_loop: DEC L + JR Z,.error_no_mem + CP (HL) + JR NZ,.allocate_loop + ; + CALL .check_barred_pages + LD A,0 + JR Z,.allocate_loop + ; + LD (HL),C + LD C,L + DJNZ .allocate_loop + ; L = указатель цепочки. + AND A + LD D,L + ; Get Pent128 mem + LD BC,256*BIOS.ZX_MEMORY_MANAGER.MODE_128k + BIOS.GetMem + CALL ToBIOS_FromEXT + ;CALL EMM.GetMem + ; A - Pent128 mem block id + LD B,D ; Scorp128 mem block id + LD C,BIOS.MergeMemBlocks + CALL ToBIOS_FromEXT + ;CALL EMM.MergeMemBlocks + LD (SYS_PAGE.Block_ID.vRAM),A + RET + ; + ; фильтр для страниц скорпа + ;выход: ZF=1 - страница не подходит +.check_barred_pages: + ; check reset page + LD A,L + CP RESET_PAGE + RET C + RET Z + ; check isa page + AND D + XOR E ; страницы ISA #D0..#DF + RET NZ + LD L,E + RET + ; +.error_no_mem: LD A,C + LD C,BIOS.FreeMem + CALL ToBIOS_FromEXT + ;CALL EMM.FreeMem + LD A,BIOS.Error.EMM.NoMemory + SCF + RET +;-----------------------------------------------------------------------; + ENDMODULE +;░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░; + + +;░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░; +; [ ] free zx pages! +; Вход: D: 0 - BASIC 128, 1 - BASIC 48, 2 - TR-DOS 128, +; 3 - EXPANSION. C закрытыми 128-ми портами: +; 4 - TR-DOS, 5 - BASIC 48 +; E: значение для SYS_PORT/CNF_PORT +; L: Block_ID.vROM +; H: Block_ID.vRAM +; B: Port All Mode +;A [1..0]: 1 - int scorp, 2 - int pent, 3 - int ZX +; A'[2]: 0 - set default palette, 1 - don't change palette +; A'[7]: 0 - 320, 1 - 312 строк + +GOTO_SPECTRUM: DI + LD C,A + ; + ; + ; set shared pages + XOR A + OUT (SLOT2),A ; ZERO_PAGE + DEC A + OUT (SLOT1),A ; SHARED_PAGE + ; + LD A,SYS_PAGE + OUT (SLOT3),A + ; + LD (SYS_PAGE.CONFIG_DE),DE + LD (SYS_PAGE.Block_IDs),HL ;!FIXIT освободить старые значения? ; [ ] free zx pages! + ; + LD A,C + AND %0000'0011 + LD SP,#C000 + ;!TODO сделать активацию винта для параметра из Setup + ; установка инта + EXX + LD C,BIOS.FN_SYNC + CALL ToBIOS_FromEXT + EXX + ; установка развёртки + LD A,C + EXX + RLCA + AND %0000'0001 + OR %1000'0110 + LD C,BIOS.FN_SYNC + CALL ToBIOS_FromEXT + EXX + ; + LD A,C + PUSH BC + EXX + AND %0000'0100 ;!TODO запомнить/восстановить кастомную палитру? + LD BC,BIOS.SET_PAL_INIT.ZX + CALL Z,ToBIOS_FromEXT + ; + ; [x] фикс неполной дешифрации порта #FFFD (пишут в #C0FD) для ZX mode + LD A,#FF + LD HL,%00'010'1'1110'1101 + LD DE,%10'111'1'1111'1111 ; CNF_0, CNF_1 + LD BC,ACEX.AY_FFFD_WRITE*256 + BIOS.DCP_CONFIG + CALL ToBIOS_FromEXT + ; + LD E,0 + LD BC,BIOS.LP_OPEN_S.ZX_32x24_Default + CALL ToBIOS_FromEXT + ; + LD E,0 + LD HL,#5104 + LD BC,BIOS.LP_OPEN_S.ZX_32x24 + CALL ToBIOS_FromEXT + ; + LD BC,BIOS.SWAP_RAM_DRIVES.ZX + CALL ToBIOS_FromEXT + ; + LD A,(SYS_PAGE.Block_ID.vRAM) + LD HL,SYS_PAGE.SHARED_BUFFER_256b + 1 + LD C,BIOS.GetMemBlkPages + CALL ToBIOS_FromEXT + ;!FIXIT + ;RET C + ; !FIXIT проверка размера блока, сделать, чтоб выбирался объём памяти + ;LD A,B + ;CP 16 + ; + LD D,B + EXX + POP BC + EXX + ; + XOR A + OUT (RGADR),A ; регистр видео адреса + OUT (RGMOD),A ; регистр моды + ; подготовка страниц + PUSH DE + ; + LD HL,SYS_PAGE.SHARED_BUFFER_256b+30 + LD DE,SYS_PAGE.SHARED_BUFFER_256b+32 + LD BC,26 + LDDR + ; + INC L + LD (HL),ZX_PAGE.SLOT1 + LD HL,SYS_PAGE.SHARED_BUFFER_256b+2 + LD E,(HL) + LD (HL),ZX_PAGE.SLOT2 + LD HL,SYS_PAGE.SHARED_BUFFER_256b+6 + LD (HL),E + LD HL,SYS_PAGE.SHARED_BUFFER_256b + LD (HL),A + ; + POP DE + ; + ; DEC HL + ; LD (HL),A ; ZX_PAGE.SLOT0 + ; INC HL + ; INC HL + ; LD A,(HL) + ; LD (HL),ZX_PAGE.SLOT1 + ; INC HL + ; INC HL + ; LD E,(HL) + ; LD (HL),ZX_PAGE.SLOT2 + ; INC HL + ; LD (HL),A + ; INC HL + ; LD (HL),E + ; + ;LD HL,SYS_PAGE.SHARED_BUFFER_256b + ;LD IY,.BASIC_128 + ;JR INIT_PAGES ; инициализация номеров страниц режима спектрума + ; инициализация страниц zx spectrum + ; HL - адрес блока страниц в SYS_PAGE SLOT3 + ; D - количество этих страниц +INIT_PAGES: LD A,SYS_PAGE + OUT (SLOT1),A + ; [ ] free zx pages! переделать инит. если 512, то нет 1ffd и наоборот + LD A,SYS_PORT.TURBO.ON + SYS_PORT.CNF_0; + SYS_PORT.CNF_512 + OUT (SYS_PORT.ROM),A + ; + RES 7,H + ; + LD A,D + CP BIOS.ZX_MEMORY_MANAGER.MODE_48k + JR Z,.set_48k + ; + LD E,0 ; pent128 + CP BIOS.ZX_MEMORY_MANAGER.MODE_256k + JR Z,.set_scorp + ; + CP BIOS.ZX_MEMORY_MANAGER.MODE_128k + JR Z,.set_pent + INC E + CP BIOS.ZX_MEMORY_MANAGER.MODE_512k + JR Z,.set_pent + ;!FIXIT обработка ошибки + DI +.error_loop: LD A,R + AND 7 + OUT (BorderColor),A + JR .error_loop + ; +.set_48k: LD A,5 ; !HARDCODE CONFIG_DE.ZX_START ВХОД В BASIC 48 с закрытыми 128-ми портами + LD (SYS_PAGE.CONFIG_DE.ZX_START - #8000),A + ;LD A,(HL) ; SLOT0, SLOT3 page + ;INC HL + ;LD E,(HL) ; SLOT1 page + ;INC HL + ;LD D,(HL) ; SLOT2 page + ;JR .set_slots + ; + JR .set_table + ; +.set_scorp: CALL MANAGE_ZX_PAGES.INIT_vRAM + LD A,#10 + CALL MANAGE_ZX_PAGES.INIT_vRAM.set_1ffd + ; A = 0, BC = #7FFD + LD B,#1F + OUT (C),A + INC A ; reset ZF + ; +.set_pent: CALL Z,MANAGE_ZX_PAGES.INIT_vRAM + ; меняем порядок для процедуры .set_slots +.set_table: LD A,(SYS_PAGE.SHARED_BUFFER_256b+2 - #8000) ; SLOT2 page + LD D,A + LD A,(SYS_PAGE.SHARED_BUFFER_256b+5 - #8000) ; SLOT1 page + LD E,A + LD A,(SYS_PAGE.SHARED_BUFFER_256b+0 - #8000) ; SLOT0, SLOT3 page + ; +.set_slots: OUT (SLOT0),A + OUT (SLOT3),A + LD A,E + OUT (SLOT1),A + LD A,D + OUT (SLOT2),A + ;JP (IY) + ; +;.BASIC_128: ;start_basic: + LD SP,#C000 + LD HL,RES128_PROG + LD DE,ZX_VARS.PRINTER_BUFFER ; запуск программы на BASIC-е. + LD BC,RES128_PROG.Size + LDIR + JP ZX_VARS.PRINTER_BUFFER +;----------------------------------------------------------------------; +; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 +; x 0 x 1 2 x 3 4 +; x 0 1 2 3 4 +;p 0 1 2 3 4 5 6 7 +; 0 x 2 x x 5 x x +;-----------------------------------------------------------------------; +;***************************************** +; +; Инициализация страниц для +; спектрумовского режима и +; восстановление спектрумовского +; экрана +; +; Возврат по IY +; +; !!! NO USE STACK !!! +; +;***************************************** + +;-----------------------------------------------------------------------; + +; +;>$< >$< >$< >$< >$< >$< [ ПЕРЕМЕЩАЕМАЯ В ОЗУ ] >$< >$< >$< >$< >$< >$< ; +;--------[ Программа, размещаемая с #5B00 для запуска Spectrum ]--------; +RES128_PROG: + DISP ZX_VARS.PRINTER_BUFFER ;#5B00 + XOR A + OUT (SYS_PORT.RAM),A ; Возврат в 128k ROM + LD C,SLOT3 + IN B,(C) + LD A,SYS_PAGE + OUT (SLOT3),A + LD DE,(SYS_PAGE.CONFIG_DE) + OUT (C),B + ; + EXX + LD A,B + EXX + LD BC,Port_All_Mode + OUT (C),A + ; + XOR A + LD BC,#1FFD + OUT (C),A ; Scorp порт + LD B,#7F + OUT (C),A ; 128 порт + ; + LD A,E ; установка конфигурации и режима TURBO + OUT (SYS_PORT.RAM),A ; CONFIG_SET + ; + INC D + DEC D + ; 0 ВХОД В BASIC-128 + JP Z,0 + ; 1 ВХОД В BASIC-48 + LD A,#10 + OUT (C),A + DEC D + JP Z,0 + ; 2 ВХОД В TR-DOS + LD HL,0 + PUSH HL + DEC D + JP Z,#3D29 + ; 3 ВХОД В EXPANSION + ;!TODO пока не работает. Page #45, BIOS (ZX_EXP) #E0 + XOR A + OUT (C),A ; 7FFD + LD A,#02 + LD B,#1F + OUT (C),A + DEC D + JP Z,0 + ; + XOR A + OUT (C),A + LD A,#30 + LD B,#7F + OUT (C),A + ;!TEST + LD A,CNF_PORT.PENT_RESET + CNF_PORT.SCORP_RESET + OUT (CNF_PORT.OFF),A + ; + DEC D + ; 4 ВХОД В TR-DOS с закрытыми 128-ми портами + JP Z,#3D29 + ; 5 ВХОД В BASIC-48 с закрытыми 128-ми портами + JP 0 + ENT +.Size EQU $-RES128_PROG +;-----------------------------------------------------------------------; +;>$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$< >$<; +; +; _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ _ZX_ ; + + + + +/* +;!TODO переделать под переключение на разные спектрумы с запущенными задачами + +TASK_SWITCH: +; *** Сохранить задачу *** + PUSH IY + PUSH IX + PUSH AF + PUSH BC + PUSH DE + PUSH HL + + EXX + EX AF,AF' + + PUSH AF + PUSH BC + PUSH DE + PUSH HL + + LD A,R + PUSH AF + LD A,I + PUSH AF + + LD A,(HL) + GET_ZX_TASK_DATA_OFFSET + LD C,A + + IN A,(SLOT3) + LD B,A ; 3-я страница текущей задачи + LD A,SYS_PAGE + OUT (SLOT3),A + + LD IX,SYS_PAGE.ZX_TASK.CURRENT ; данные задач + LD A,_ZX_TASK_DATA ; смещение данных в таблице задач + ADD A,(IX) ; смещение данных текущей задачи + LD E,A + LD D,0 + ADD IX,DE ; данные текущей задачи + + LD (IX + _ZX_TASK_DATA.SLOT3_PAGE),B ; сохранить страницу 3 + LD HL,0 + ADD HL,SP + LD (IX + _ZX_TASK_DATA.SP),L ; сохранить стек задачи + LD (IX + _ZX_TASK_DATA.SP + 1),H + SET 0,(IX + _ZX_TASK_DATA.STATE) ; установить флаг сохраненности текущей задачи + RES 1,(IX + _ZX_TASK_DATA.STATE) ; установить флаг, что задача покинута + + LD IX,SYS_PAGE.ZX_TASK.CURRENT + LD A,_ZX_TASK_DATA ; смещение данных в таблице задач + ADD A,C ; смещение данных новой задачи + LD E,A + LD D,0 + ADD IX,DE ; данные новой задачи + +; BIT 1,(IX + _ZX_TASK_DATA.STATE) +; JR NZ,TASK_IN_WORK ; задача в работе ??? неверное завершение +; ; сбрасывать или просто возвращаться + + BIT 0,(IX + _ZX_TASK_DATA.STATE) ; была сохранена/нет + JR NZ,TASK_SET ; задача существует + +; задачи не было! + LD IX,SYS_PAGE.ZX_TASK.CURRENT + LD A,C ; задача + LD (IX),A ; установить новую задачу текущей + + JP GOTO_SPEC.START_TASK ; запустить новую задачу! +; ; и пока пофиг распределение памяти! + +TASK_SET: + IF FREE_ZX_PAGES + LD IY,TASK_RESTORE + ELSE + LD IX,TASK_RESTORE + ENDIF + LD A,C + EXX + JP INIT_PAGES ; переключить все страницы! + +TASK_RESTORE: + EXX + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,C + LD IX,SYS_PAGE.ZX_TASK.CURRENT + LD (IX),A ; установить новую задачу текущей + + ; !TEST + ;LD E,A + ;LD D,0 + ;ADD IX,DE ; новая задача + ;LD E,16 + ADD A,_ZX_TASK_DATA ; смещение данных в таблице задач + LD E,A + LD D,0 + ; + ADD IX,DE + + LD L,(IX + _ZX_TASK_DATA.SP) ; вспомнить стек + LD H,(IX + _ZX_TASK_DATA.SP + 1) + LD SP,HL + LD A,(IX + _ZX_TASK_DATA.SLOT3_PAGE); вспомнить третью страницу + OUT (SLOT3),A + + + POP AF ; восстановить + LD I,A + POP AF + LD R,A + POP HL + POP DE + POP BC + POP AF + EX AF,AF' + EXX + POP HL + POP DE + POP BC + POP AF + POP IX + POP IY + ; вернуться в задачу + +NO_TASK: + POP BC + JP SW_ROM_1 +*/ +; 259F - ADRESS BASIC128 - MAIN_MENU \ No newline at end of file diff --git a/src/bios/rom/ZX/ZX_MENU.ASM b/src/bios/rom/ZX/ZX_MENU.ASM new file mode 100644 index 0000000..32a8234 --- /dev/null +++ b/src/bios/rom/ZX/ZX_MENU.ASM @@ -0,0 +1,748 @@ +; "MENU PROGRAMS." +;********************************* +; FOR INCLUDE !!! +;********************************* +; Обслуживание МЕНЮ +; HL - адрес таблицы программ +; A - номер в таблице +; если A=-1, то возврат, +; иначе выполнение +;***************************** +EXEC_PNT: + INC A + RET Z + ;!FIXIT почему не так? + ; DEC A + ; JR Z,EXEC_HL + ; LD D,0 + ; LD E,A + ; XOR A + ; ADC HL,DE + ; ADC HL,DE + ; +EXEC_PNT_LOOP: + DEC A + JR Z,EXEC_HL + INC HL + INC HL + JR EXEC_PNT_LOOP +EXEC_HL: + LD E,(HL) + INC HL + LD D,(HL) + INC HL + EX DE,HL + JP (HL) +RET_FROM_M: + POP HL + RET + +;**************************************** +; РАБОТА С MENU_128 +;**************************************** +; ВХОД: DE - адрес меню +; BC - длина меню +; ВЫХОД: A - выбранный пункт +;**************************************** +RUN_MENU: + PUSH IX + PUSH DE ; DE - MENU + PUSH BC ; BC - len_menu + + LD A,(DE) + DEC A ; число CMD + CP 9 ; !HARDCODE макисмальное число пунктов меню + JR C,RUN_M_1 +RUN_MN_ERR: + POP BC + POP DE + LD A,#FF ; вернуться с номером 255 - ошибка + POP IX + RET +RUN_M_1: + LD A,(ZX_VARS.PROG.SWAP_ROM) + CP #F5 ; сравнить А с опкодом PUSH AF + JR NZ,RUN_MN_ERR + + + LD HL,LEN_P_M + ADD HL,BC ; HL - нужная длина памяти + LD B,H ; HL -> BC + LD C,L + LD HL,(ZX_VARS.WORK_SPACE) ; HL - начало раб обл + + PUSH BC + PUSH HL + + CALL C_1655 ; получить рабочую память + + POP DE + PUSH DE ; начало раб обл + + LD BC,LEN_P_M ; длина программы меню + LD HL,MENU_128 ; сама программа + LDIR ; программа перемещена. DE - место для MENU + POP BC + PUSH BC ; начало программы + + PUSH DE ; сохранить место для MENU + LD DE,MN_128_S ; данные для shifter + CALL SHIFTER ; изменить данные в соответствии с положением в MEM + POP DE ; вернуть место для MENU + + POP HL ; начало программы + POP IX ; длина данных + POP BC ; длина меню + EX (SP),HL ; HL - меню + LDIR ; переместить данные MENU + + POP HL ; адрес программы MENU + PUSH HL + PUSH IX ; длина раб. обл + CALL JP_HL ; вызов программы MENU + POP BC ; вернуть длину раб обл + POP HL ; и начала программы + + PUSH AF ; сохранить номер выбора + CALL C_19E8 ; освободить память !! + POP AF ; вернуть номер выбора + POP IX + RET ; возврат из программы RUN_MENU +JP_HL: JP (HL) +;************************************** +; 128k MENU +;************************************** +;!HARDCODE +MENU_PROG EQU #25B9 ; #25B9 in sp_128.asm +;SWAP_ROM EQU #5B00 +NEW_SP EQU #1F45 ; L1F45: in sp_128.asm +RET_SP EQU #1F20 ; L1F20: in sp_128.asm + +;************************************** +; Программа вызова MENU_128 из ОЗУ. +;************************************** +MN_128_S: + DB SH_1 - MENU_128+1 + DB SH_2 - MENU_128+1 + DB SH_3 - MENU_128+1 + DB SH_4 - MENU_128+1 + DB SH_5 - MENU_128 + DB SH_6 - MENU_128 + DB SH_7 - MENU_128 + DB SH_8 - MENU_128 + DB SH_9 - MENU_128 + DB SH_A - MENU_128 + DB SH_B - MENU_128 + DB SH_C - MENU_128 + DB 0 +;************************************** +; Эта программа перемещается в озу +;************************************** +MENU_128: + XOR A + OUT (SYS_PORT.RAM),A + CALL ZX_VARS.PROG.SWAP_ROM + CALL NEW_SP + +SH_1: LD DE,MENU_DAT - MENU_128 + LD HL,ZX_VARS.MENU_TBL.JUMP + LD BC,4 + LDIR + +SH_2: LD HL,MENU_128_E - MENU_128 + LD (ZX_VARS.MENU_TBL.JUMP),HL +SH_3: LD HL,MENU_128_E2 - MENU_128 + LD (ZX_VARS.MENU_TBL.TEXT),HL + JP MENU_PROG + +RET_M EQU $-MENU_128 +SH_4: LD HL,MENU_DAT - MENU_128 + LD DE,ZX_VARS.MENU_TBL.JUMP + LD BC,4 + LDIR + + CALL RET_SP + CALL ZX_VARS.PROG.SWAP_ROM + EX AF,AF' + LD A,SYS_PORT.EXTENSION + OUT (SYS_PORT.ROM),A + EX AF,AF' + RET +MENU_DAT: + DW 0,0 +MENU_128_E: + DB 8 + DB 0 +SH_5: DW RET_M + DB 1 +SH_6: DW RET_M + DB 2 +SH_7: DW RET_M + DB 3 +SH_8: DW RET_M + DB 4 +SH_9: DW RET_M + DB 5 +SH_A: DW RET_M + DB 6 +SH_B: DW RET_M + DB 7 +SH_C: DW RET_M +MENU_128_E2: + +LEN_P_M EQU $-MENU_128 + +;************************************** +; RST 30 - получение BC SPACES с адреса HL +; #19E8 - освобождение BC spaces с адреса HL +; HL - раб. ячейка +; BC - адрес программы +; DE - адрес данных для перемещения +SHIFTER: + LD A,(DE) ; (DE) - SHIFT IN PROG + AND A + RET Z + INC DE + LD L,A + LD H,0 + + ADD HL,BC ; HL - ADRESS FOR SHIFT + LD A,(HL) ; (HL)=(HL)+BC + ADD A,C + LD (HL),A + INC HL + LD A,(HL) + ADC A,B + LD (HL),A + JR SHIFTER + +;******************************************* +; МЕНЮ : байт 1 - для результата +; байт 2 - число пунктов +1 +; название меню, код 0FFh ( COPY ) +; пункты меню окончание байтом с +; уст, 7-м битом + пустая строка !! +;******************************************* +BASIC_MENU: +; LD A,(HL) +; CP 'S' +; JP Z,SET_SYSTEM + + LD DE,(ZX_VARS.CH_ADR) + PUSH DE + LD (ZX_VARS.CH_ADR),HL + CALL_48X #1C8C ; SYMBOL VAR + CALL_48X #2BF1 ; input txt !!! + ; DE - adr + ; BC - len + PUSH DE + PUSH BC + INC DE + CALL TST_M + JR C,NO_EXE_M + CALL RUN_MENU + LD (IY+0),255 +NO_EXE_M: + POP BC + POP DE + LD (DE),A + POP HL + LD (ZX_VARS.CH_ADR),HL + JP SW_ROM +TST_M: + PUSH DE + PUSH BC + EX DE,HL + LD D,(HL) + INC D + LD A,255 + CPIR + JR NZ,ERR_TST_M +LOOP_TST_M: + LD A,B + OR C + JR Z,ERR_TST_M + + BIT 7,(HL) + INC HL + DEC BC + JR Z,LOOP_TST_M + DEC D + JR NZ,LOOP_TST_M + POP BC + POP DE + AND A + RET + +ERR_TST_M: + POP BC + POP DE + LD A,255 + SCF + RET + +;************************************** + +CALL_DOS_MOVE: + LD HL,DOS_PROG + LD DE,DOS_PROG.Exec + LD BC,DOS_PROG.Size + LDIR + RET +; +; HL - адрес команды, BC - длина команды +CALL_DOS1: + LD C,(HL) + INC HL + LD B,0 + LD DE,(ZX_VARS.E_LINE) + LD (ZX_VARS.CH_ADR),DE + LDIR + LD (ZX_VARS.WORK_SPACE),DE + LD (ZX_VARS.STK_BOT),DE + LD (ZX_VARS.STK_END),DE + CALL CALL_DOS_MOVE + JP DOS_PROG.Exec + +DOS_PROG: + DISP #5C00 - DOS_PROG.Size ;!HARDCODE + //DOS_PROG: +.Exec: PUSH AF + XOR A + OUT (SYS_PORT.RAM),A + POP AF + //DOS_PROG_A+1: +.Patch+2: CALL #3D03 ;!HARDCODE + PUSH AF + ;!FIXIT сделать через условие компиляции ZX_ROM_BIOS + //LD A,0 + //OUT (CNF_PORT),A + LD A,SYS_PORT.EXTENSION + OUT (SYS_PORT.ROM),A ;!!!!! версия для ПЗУ + POP AF + RET + //DOS_PROG_LEN +.Size EQU $ - .Exec + ENT + + ;????? вроде, не используются +CONT_PROG: + LD HL,#1AFD ;!HARDCODE COM_LN: + PUSH HL + LD HL,#5B00 ;!HARDCODE + PUSH HL + LD DE,ZX_VARS.FLG_INPUT + LD BC,1 + LD A,#E8 ;!HARDCODE + LD (DE),A + JP SW_ROM +CALL_DOS: + PUSH HL + PUSH DE + PUSH BC + PUSH AF + CALL CALL_DOS_MOVE + LD A,#13 ;!HARDCODE #13 из AUTO_1303 + LD (DOS_PROG.Patch),A + POP AF + POP BC + POP DE + POP HL + JP DOS_PROG.Exec + ; +; + +;=======================================================================; +;=======================================================================; +;=======================================================================; +SERVICE: + //LD HL,SR_TAB + LD DE,SR_MENU + LD BC,SR_MENU.Size + //PUSH HL + CALL RUN_MENU ;09f3 + LD HL,SR_TAB + //POP HL + CALL EXEC_PNT + JR SERVICE + +SR_TAB: DW RUN_DISK_TRD + DW GOTO_TRDOS.m128 + DW GOTO_TRDOS.m48 + DW TURBO_OFF + DW TURBO_ON + DW CLEAR_RAM + DW RET_FROM_M + +; DC - every last character of a string will have bit 7 set +SR_MENU: + BYTE 8 ; количество пунктов + BYTE 'Options ',#FF ; заголовок меню + DC 'RUN disk.trd' + DC '128 TR-DOS' + DC '48 TR-DOS' + DC 'TURBO OFF ' + DC 'TURBO ON ' + DC 'Clear RAM' + DC 'RETURN' + DC " " ; маркер конца +.Size EQU $-SR_MENU + +;***************************** + +;SR_48R: +GOTO_TRDOS: +.m128: LD A,#10 + JR .RUN +;SR_48: +.m48: LD A,#30 ; Стопор на PORT_128 !!! +;SR_48A: +.RUN: LD BC,#7FFD + OUT (C),A + LD BC,0 ; НА 0 !! + PUSH BC + LD BC,#3D2F ; В DOS ! + PUSH BC + JP SW_ROM + +;******************************* +TURBO_OFF: + LD A,BIOS.FN_TURBO.OFF + LD C,BIOS.FN_TURBO + JP_to_BIOS +TURBO_ON: + LD A,BIOS.FN_TURBO.ON + LD C,BIOS.FN_TURBO + JP_to_BIOS + +;******************************* + +CLEAR_RAM: + DI + ; [ ] free zx pages! + LD BC,BIOS.REINIT.FREE_NO_ZX_MEM + ;LD C,BIOS.FullInit + ; + CALL ToBIOS_FromEXT + ; при очистке памяти из меню спектрума возврат в DSS по CAD + ; будет опасным (RAM Blocks освободились), + ; поэтому отключаем перехват ресета. + LD A,ACEX.RET_PORT + LD BC,BIOS.SET_PORTS + ;[x] SET_PORTS: no need to call from #3D13 and DI. 31/12/23 + ;CALL ToBIOS_3D13 + CALL ToBIOS_FromEXT + ; + EI + RET + + +;***************************** +; *** MENU Hardware *** +;***************************** + +Hardware_Menu: + LD HL,Hardware_Menu_TAB + LD DE,Hardware_Menu_STR + LD BC,Hardware_Menu_STR.Size + PUSH HL + CALL RUN_MENU + POP HL + CALL EXEC_PNT + JR Hardware_Menu + +Hardware_Menu_TAB: +; DW TR_DOS +; DW SP_DOS + DW SPRINTER_ZX + DW SCORPION_256 + DW Pentagon_48 + DW PENTAGON_128 + DW PENTAGON_512 + DW ZX_SPECTRUM_128 + DW SPRINTER_reset ;SPRINTER_2X + DW RET_FROM_M + +; DC - every last character of a string will have bit 7 set +Hardware_Menu_STR: + BYTE 9 ; количество пунктов + BYTE 'Hardware',#FF ; заголовок меню + DC 'Sprinter ZX ' + DC 'Scorpion 256' + DC 'Pentagon 48 ' + DC 'Pentagon 128' + DC 'Pentagon 512' + DC 'Spectrum 128' + DC 'Restart ' + DC 'RETURN' + DC " " ; маркер конца +.Size EQU $ - Hardware_Menu_STR + + +;[ ] free zx pages! +;************************************************** +SPRINTER_ZX: LD L,0 ; точка входа в ПЗУ +.custom_ROM: LD H,BIOS.RST_CONF.SP97_1 + LD BC,#FE*256 + %0000'0010 ; !HARDCODE Port All Mode data. int pent, set default palette, 320 строк + LD DE,4*256 + CNF_PORT.TURBO.ON + CNF_PORT.CNF_0 ; !HARDCODE 4 - выделение памяти Scorpion 256k. 2+6+8 страницы + JR PREPARE_TO_START_ZX + ; +ZX_SPECTRUM_128: + LD L,0 ; точка входа в ПЗУ +.custom_ROM: LD H,BIOS.RST_CONF.AY8910 + LD BC,#FA*256 + %1000'0011 + JR PENTAGON_128.zx + ; +SCORPION_256: LD L,0 ; точка входа в ПЗУ +.custom_ROM: LD H,BIOS.RST_CONF.AY8910 + LD BC,#FE*256 + %1000'0001 + LD DE,4*256 + CNF_PORT.TURBO.ON + CNF_PORT.CNF_1 ; !HARDCODE 4 - выделение памяти Scorpion 256k. 2+6+8 страницы +PREPARE_TO_START_ZX: + DI + LD A,CNF_PORT.CNF_0 + CNF_PORT.TURBO.ON + OUT (SYS_PORT.ROM),A + LD A,SYS_PAGE + OUT (SLOT3),A + ; + PUSH HL + PUSH BC + PUSH DE + PUSH DE + ; + LD C,H + CALL ToBIOS_FromEXT + ; + POP DE + LD B,D + CALL MANAGE_ZX_PAGES.FN_ENTRANCE.API + JR C,.loop_rst + ; + POP DE + POP BC + POP HL + ; + LD D,L ; !HARDCODE точка входа в ПЗУ спектрума + LD H,A + LD A,(SYS_PAGE.Block_ID.vROM) + LD L,A + LD A,C + JP GOTO_SPECTRUM + ; +.loop_rst: LD BC,BIOS.REINIT.HARD_RESET + CALL ToBIOS_FromEXT + JR .loop_rst + ; +PENTAGON_128: LD L,0 ; точка входа в ПЗУ +.custom_ROM: LD H,BIOS.RST_CONF.AY8910 + LD BC,#FE*256 + %0000'0010 +.zx: LD DE,2*256 + CNF_PORT.CNF_1 + CNF_PORT.TURBO.ON + CNF_PORT.SCORP_RESET ; !HARDCODE 2 - выделение памяти Pentagon 128 + JR PREPARE_TO_START_ZX + ; +PENTAGON_512: LD L,0 ; точка входа в ПЗУ +.custom_ROM: LD H,BIOS.RST_CONF.AY8910 + LD BC,#FE*256 + %0000'0010 + LD DE,3*256 + CNF_PORT.CNF_1 + CNF_PORT.TURBO.ON + CNF_PORT.CNF_512 + CNF_PORT.SCORP_RESET ; !HARDCODE 3 - выделение памяти Pentagon 512 + JR PREPARE_TO_START_ZX + ; +Pentagon_48: LD L,0 ; точка входа в ПЗУ +.custom_ROM: LD H,BIOS.RST_CONF.AY8910 + LD BC,#FE*256 + %0000'0010 +.zx: LD DE,1*256 + CNF_PORT.TURBO.ON + CNF_PORT.CNF_1 ; !HARDCODE 1 - выделение памяти 48 кб + JR PREPARE_TO_START_ZX + ; +ZX_Spectrum_48: LD L,0 ; точка входа в ПЗУ +.custom_ROM: LD H,BIOS.RST_CONF.AY8910 + LD BC,#FA*256 + %1000'0011 + JR Pentagon_48.zx + +SPRINTER_reset: + DI + LD A,CNF_PORT.CNF_0 + CNF_PORT.TURBO.ON + OUT (SYS_PORT.ROM),A + LD BC,BIOS.REINIT.SOFT_RESET + JP_to_BIOS + + +;***************************** +; *** MENU UTILITES *** +;***************************** +;!FIXIT BIOS SIZE. это запуск c:\disk.trd - не думаю, что это нужно, можно заменить +RUN_DISK_TRD: + LD HL,C_DISK_C + CALL CALL_DOS1 + + ; [ ] исправлен баг с запуском disk.trd с CNF != 0 + LD A,SYS_PORT.CNF_0 + SYS_PORT.EXTENSION + OUT (SYS_PORT.ROM),A + ; + + LD C,BIOS.HDD_INIT + CALL ToBIOS_FromEXT + JR C,.DISK_UTILIT + + LD HL,C_DISK_C3 + CALL CALL_DOS1 + +.UTIL_DISK: + XOR A + LD C,BIOS.FreeMemRMD + CALL ToBIOS_FromEXT + + LD HL,C_DEMO6 + CALL CALL_DOS1 + + XOR A + LD C,BIOS.GET_RAMD_ST + CALL ToBIOS_FromEXT + + JR C,.UTIL_DISK_L1 + JR Z,.UTIL_DISK_L1 + + LD HL,C_DISK_C1 + CALL CALL_DOS1 + ; [ ] исправлен баг с запуском disk.trd с CNF != 0 + IN A,(SLOT3) + EX AF,AF' + LD A,SYS_PAGE + OUT (SLOT3),A + LD A,(SYS_PAGE.CONFIG_DE.CNF_PORT) + EX AF,AF' + OUT (SLOT3),A + EX AF,AF' + OUT (SYS_PORT.ROM),A + ; + LD HL,C_DISK_C2 + CALL CALL_DOS1 + RET + +.UTIL_DISK_L1: + LD A,(ZX_VARS.OPER_DISK) + INC A + CP 2 + JR Z,.DISK_UTIL_RET + LD HL,C_DISK_C5 + CALL CALL_DOS1 + JR .UTIL_DISK + +.DISK_UTIL_RET: + LD HL,C_DISK_C6 + CALL CALL_DOS1 + RET + +.DISK_UTILIT: + LD HL,C_DISK_C4 + CALL CALL_DOS1 + JR .UTIL_DISK + +C_DEMO6: DB .Size, ZX_Token.rem, ':/disk.trd', 13,80 +.Size EQU $-C_DEMO6-1 + +C_DISK_C: DB .Size,ZX_Token.rem,':',13,80 +.Size EQU $-C_DISK_C-1 + +; C_DISK_C0: DB .Size,ZX_Token.rem,':/CLEAR E',13,80 +; .Size EQU $-C_DISK_C0-1 + +C_DISK_C1: DB .Size,ZX_Token.rem,':/RMD E',13,80 +.Size EQU $-C_DISK_C1-1 + +C_DISK_C2: DB .Size,ZX_Token.rem,':RUN',13,80 +.Size EQU $-C_DISK_C2-1 + +C_DISK_C3: DB .Size,ZX_Token.rem,':/HDD',13,80 +.Size EQU $-C_DISK_C3-1 + +C_DISK_C4: DB .Size,ZX_Token.rem,':/FDD',13,80 +.Size EQU $-C_DISK_C4-1 + +C_DISK_C5: DB .Size,ZX_Token.rem,':/B:',13,80 +.Size EQU $-C_DISK_C5-1 + +C_DISK_C6: DB .Size,ZX_Token.rem,':/A:',13,80 +.Size EQU $-C_DISK_C6-1 +; + +;*************************************** + +;VERSION: DEFB 22,21,0 +; DEFB 16,2,"Expansion 3.02  1997 ELSY Co.",16,1,0FFh + +;********************************************** + +;****************************** +;SP_DOS: +; LD B,#E2 +; LD A,#E1 +; JR TR_DOS1 +;TR_DOS: +; LD B,#EA +; LD A,#E1 +;TR_DOS1: +; CALL DOS_ON +; CALL SET_ROM_PAGES +; CALL DOS_OFF +; RET +;****************************** + + +; _SET_CNF: +; ;DI +; LD A,CNF_PORT.CNF_0 + CNF_PORT.TURBO.ON +; OUT (SYS_PORT.ROM),A +; RET + +; CNF_SC_312: +; LD A,Port_VSYNC.SET_312L +; OUT (Port_VSYNC),A +; RET + +; CNF_PN_320: +; LD A,Port_VSYNC.SET_320L +; OUT (Port_VSYNC),A +; RET + +; LD A,CNF_0 +; OUT (SYS_PORT.ROM),A +; CALL DOS_OFF +; JP 0 + + +; DOS_RUN: LD HL,C_DISK_C1 +; CALL CALL_DOS1 +; ; +; LD HL,C_DISK_C2 +; CALL CALL_DOS1 +; RET + +; START_TRD: LD HL,C_DISK_C +; CALL CALL_DOS1 +; LD HL,C_DISK_C0 +; CALL CALL_DOS1 +; LD HL,C_DISK_C3 +; CALL CALL_DOS1 +; RET + +;SR_CL_MEM: +; DI +; LD A,10H +;SR_CL_R2: +; LD BC,1FFDH +; OUT (C),A +; EX AF,AF' +; XOR A +;SR_CL_R1: +; LD BC,7FFDH +; OUT (C),A +; LD HL,0C000H +; LD DE,0C001H +; LD BC,03FFFH +; LD (HL),L +; LDIR +; INC A +; CP 48H +; JR NZ,SR_CL_R1 +; EX AF,AF' +; CP 0 +; JP Z,BASIC_128 ; выход на сброс BASIC 128 +; LD A,0 +; JR SR_CL_R2 diff --git a/src/bios/rom/_MEM_MAP.INC.txt b/src/bios/rom/_MEM_MAP.INC.txt deleted file mode 100644 index 9616ef6..0000000 --- a/src/bios/rom/_MEM_MAP.INC.txt +++ /dev/null @@ -1,17 +0,0 @@ -; -; ██████╗ ███████╗██████╗ █████╗ ██████╗██╗ ██╗███████╗██████╗ -; ██╔══██╗██╔════╝██╔══██╗██╔══██╗██╔════╝██║ ██╔╝██╔════╝██╔══██╗ -; ██║ ██║█████╗ ██████╔╝███████║██║ █████╔╝ █████╗ ██████╔╝ -; ██║ ██║██╔══╝ ██╔═══╝ ██╔══██║██║ ██╔═██╗ ██╔══╝ ██╔══██╗ -; ██████╔╝███████╗██║ ██║ ██║╚██████╗██║ ██╗███████╗██║ ██║ -; ╚═════╝ ╚══════╝╚═╝ ╚═╝ ╚═╝ ╚═════╝╚═╝ ╚═╝╚══════╝╚═╝ ╚═╝ -; -Depacker_start EQU #D000 -;Depacked_logo_start EQU #D900 -;MAIN_Unpacked_Start EQU #8000 - -COMPILE_ADDR: -.EXP: EQU 0 -.ROM: EQU 0 -.MAIN EQU #8000 - diff --git a/src/bios/rom/_ROM.txt b/src/bios/rom/_ROM.txt deleted file mode 100644 index 7355d0c..0000000 --- a/src/bios/rom/_ROM.txt +++ /dev/null @@ -1,119 +0,0 @@ -;-----------[#0000 Extended]------------ - INCLUDE 'src/bios/rom/EXTENDED/EXTENDED.ASM' -;--------------------------------------- - - - -;-------------[#1000 SETUP]------------- - BLOCK #1000-$,#FF -setup_start EQU $ - - DISP #8000 ;!!!!!!!!!!hardcode - - DB "SETUP" -; JR JUMP - DB " (C) 2001 PETERS PLUS LTD " -SETUP_DEPACK: - DI - POP HL - LD SP,#7FFF ;!!!!!!!!!!hardcode - PUSH HL - PUSH AF - LD HL,#8000 ;!!!!!!!!!!hardcode - PUSH HL - LD DE,Depacker_start ; адрес процедуры депакера !!!!! - PUSH DE - LD HL,Depacker - LD BC,Depacker.length - LDIR - LD HL,Depacker.packcode ; где архив - LD DE,COMPILE_ADDR.MAIN ; куда распаковывать - RET - -Depacker: - ENT - - -DEPACK_CODE: - DISP Depacker_start -; сделать тут условие для исходника депакера, чтоб автоматом выбирался разный алгоритм запаковки и распаковки - INCLUDE 'src/bios/ROM/SETUP/DEHRUST.ASM' - ENT -DEPACK_CODE.length EQU $-DEPACK_CODE - - - DISP Depacker+DEPACK_CODE.length -Depacker.packcode: - INCBIN 'Build/Bin/MAIN.PAK' -Depacker.length EQU $-Depacker.packcode+DEPACK_CODE.length - ENT - -setup_length EQU $-setup_start -;--------------------------------------- - - - -;---------------[SET EXP]--------------- - BLOCK #3FD0-$,#FF -; call exp bios from setup -RST18h: - PUSH AF - LD A,D_ROM16OFF ; set exp-rom to bank0 - OUT (SYS_PORT_ON),A - POP AF - RET -;--------------------------------------- - - - -;-------------[???????????]------------- - BLOCK #3FD8-$,#FF -A3FD8: - JP #0107 -;--------------------------------------- - - - -;-------------[???????????]------------- - BLOCK #3FE0-$,#FF - -A3FE0: - LD A,#00 - OUT (SYS_PORT_OFF),A - JP #0000 -;--------------------------------------- - - - -;-------------[???????????]------------- - BLOCK #3FE8-$,#FF -RET_EXP_ROM: - PUSH AF - LD A,D_ROM16OFF - OUT (SYS_PORT_ON),A - JP #0100 -;--------------------------------------- - - - -;-------------[???????????]------------- - BLOCK #3FF0-$,255 -A3FF0: - PUSH AF - DI - LD A,D_ROM16OFF - OUT (SYS_PORT_OFF),A - JR A3FD8 -;--------------------------------------- - - - -;-------------[???????????]------------- -A3FF8: - PUSH AF - LD A,#00 - OUT (SYS_PORT_OFF),A - JP #0000 -;--------------------------------------- -A4000: -;======================================= \ No newline at end of file diff --git a/src/bios/rom/SETUP/EasterSprites.asm b/src/bios/rom/_not_used/EasterSprites.asm similarity index 67% rename from src/bios/rom/SETUP/EasterSprites.asm rename to src/bios/rom/_not_used/EasterSprites.asm index a1820fb..981249e 100644 --- a/src/bios/rom/SETUP/EasterSprites.asm +++ b/src/bios/rom/_not_used/EasterSprites.asm @@ -14,15 +14,15 @@ Sprites: inc ix .loop: push bc - LD A,(ix+str_EasterSprites.SpHeight) ; !!!!! координата картинки по Y + высота картинки + LD A,(ix+str_EasterSprites.SpHeight) ; !!!!! координата картинки по Y + высота картинки ld l,(ix+str_EasterSprites.SpAddress) ld h,(ix+str_EasterSprites.SpAddress+1) .putSprite: DEC A OUT (PORT_Y),A - LD E,(ix+str_EasterSprites.SpXCoord) ; !HARDCODE координата картинки по Х + LD E,(ix+str_EasterSprites.SpXCoord) ; !HARDCODE координата картинки по Х LD D,(ix+str_EasterSprites.SpXCoord+1) - LD C,(ix+str_EasterSprites.SpWidth) ; !HARDCODE длина горизонтальной линии картинки + LD C,(ix+str_EasterSprites.SpWidth) ; !HARDCODE длина горизонтальной линии картинки LD B,(ix+str_EasterSprites.SpWidth+1) LDIR CP (IX+str_EasterSprites.SpYCoord) diff --git a/src/bios/rom/SETUP/LZ4_DEC.asm b/src/bios/rom/_not_used/LZ4_DEC.asm similarity index 100% rename from src/bios/rom/SETUP/LZ4_DEC.asm rename to src/bios/rom/_not_used/LZ4_DEC.asm diff --git a/src/bios/rom/clean.cmd b/src/bios/rom/clean.cmd deleted file mode 100644 index 3add054..0000000 --- a/src/bios/rom/clean.cmd +++ /dev/null @@ -1,5 +0,0 @@ -@echo off -del *.bin /s -del *.lst /s -del *.hr /s -del *.log /s diff --git a/src/bios/rom/make.cmd b/src/bios/rom/make.cmd deleted file mode 100644 index 4c10a32..0000000 --- a/src/bios/rom/make.cmd +++ /dev/null @@ -1,46 +0,0 @@ -@echo off -set BIN=..\..\bin -set LOG=compile.log -for /F %%i in ('date /t') do set mydate=%%i -for /F %%i in ('time /t') do set mytime=%%i -set mydt=%mydate% %mytime% - -echo 1. [1/3] DEPACK -echo %mydt%: [1/4] DEPACK >> %LOG% -%BIN%\sjasmplus.exe -Wall --msg=war --nologo --syntax=w --fullpath --lst=DEPACK\DEPACK.LST --raw=DEPACK\DEPACK.BIN DEPACK\DEPACK.ASM >> %LOG% 2>&1 -if errorlevel 1 goto error - -echo 2. [2/3] SETUP -echo - MAIN.ASM -echo %mydt%: [2/4] SETUP >> %LOG% -echo %mydt%: - MAIN.ASM >> %LOG% -%BIN%\sjasmplus.exe -Wall --msg=war --nologo --syntax=w --fullpath --lst=SETUP\MAIN.LST --raw=SETUP\MAIN.BIN SETUP\MAIN.ASM >> %LOG% 2>&1 -if errorlevel 1 goto error - -echo - MAIN.HR -echo %mydt%: - MAIN.HR >> %LOG% -%BIN%\hrust.exe SETUP\MAIN.HR SETUP\MAIN.BIN >> %LOG% - -echo - SETUP.ASM -echo %mydt%: - SETUP.ASM >> %LOG% -%BIN%\sjasmplus.exe -Wall --msg=war --nologo --syntax=w --fullpath --lst=SETUP\SETUP.LST --raw=SETUP\SETUP.BIN SETUP\SETUP.ASM >> %LOG% 2>&1 -if errorlevel 1 goto error - -rem echo 3. [3/4] EXTENDED -rem echo %mydt%: [3/4] EXTENDED >> %LOG% -rem %BIN%\sjasmplus.exe -Wall --msg=war --nologo --syntax=w --fullpath --lst=EXTENDED\EXTENDED.LST --raw=EXTENDED\EXTENDED.BIN EXTENDED\EXTENDED.ASM >> %LOG% 2>&1 -rem if errorlevel 1 goto error - -echo 4. [3/3] ROM -echo %mydt%: [4/4] ROM >> %LOG% -%BIN%\sjasmplus.exe -Wall --msg=war --nologo --syntax=w --fullpath --lst=ROM.LST --raw=ROM.BIN ROM.ASM >> %LOG% 2>&1 -if errorlevel 1 goto error - -goto quit - -:error -echo ERROR during compile ROM -pause 0 -exit 3 - -:quit diff --git a/src/bios/shared/CompMacro.asm b/src/bios/shared/CompMacro.asm index cdf63c9..d6b4f43 100644 --- a/src/bios/shared/CompMacro.asm +++ b/src/bios/shared/CompMacro.asm @@ -24,29 +24,14 @@ ; ; Вход: ширина спрайта, высота, координата X, координата Y, адрес спрайта в памяти MACRO EasterTable width, height, Xcoord, Ycoord, addr - WORD addr ; адрес спрайта в памяти - WORD width ; Ширина - BYTE height+Ycoord ; Высота + Y coord - WORD Xcoord+#4040 ; X coord ; !HARDCODE Срочно исправить на метку #4040 - адрес лого - BYTE Ycoord ; Y coord + WORD addr ; адрес спрайта в памяти + WORD width ; Ширина + BYTE height+Ycoord ; Высота + Y coord + WORD Xcoord+#4040 ; X coord ; !HARDCODE исправить на метку #4040 - адрес лого + BYTE Ycoord ; Y coord ENDM ; -; на входе в A номер строки. На выходе в HL адрес начала строки. портит A, HL, BC -; MACRO FIND_STRING_ADDR ; !TODO переделать на CALL FIND_STRING_ADDR ? -; SLA A ; !FIXIT переделать под количество строк > 127 -; LD HL,MSG_Buffer -; LD B,0 -; LD C,A -; ADD HL,BC -; LD A,(HL) -; INC HL -; LD H,(HL) -; LD L,A -; ENDM -; - - ; MACRO _mRECOVERYrdChooseTYPE vers IF vers = 1 @@ -62,8 +47,6 @@ DEC A LD (RECOVERYstart.RDkey),A PUSH BC - ;LD BC,ROM_DISK.Pages.Size * 256 + BIOS.GetMemRMD - ;RST ToBIOS_18 LD B,ROM_DISK.Pages.Size CALL EMM.GetMemRMD POP BC @@ -82,9 +65,7 @@ IF vers = 1 ; Более быстрый, но захардкоженный вариант LD HL,TEMP - ;LD C,BIOS.GetMemBlkPages - ;RST ToBIOS_18 ; кидаем в буфер номера страниц RAM disk - CALL EMM.GetMemBlkPages + CALL EMM.GetMemBlkPages ; кидаем в буфер номера страниц RAM disk IN A,(SLOT3) LD (.slot3save),A @@ -93,10 +74,10 @@ LD B,0 LD C,(HL) INC C - LD DE,TEMP+5 + LD DE,TEMP+ROM_DISK.Pages.Size LDIR ; кидаем дальше в буфер номера страниц ROM disk - LD IY,TEMP+5 ; ROM_DISK.Pages.Number + LD IY,TEMP+ROM_DISK.Pages.Size ; ROM_DISK.Pages.Number LD IX,TEMP LD B,(IY+0) @@ -142,9 +123,7 @@ LD A,#46 ;чтение из ROM-Disk EX AF,AF' LD HL,TEMP ;адрес буфера данных - ;LD BC,2*256 + BIOS.BLK_RD_WR ;число секторов и номер функции - ;RST ToBIOS_18 - LD B,2 + LD B,2 ;число секторов CALL BLK_RD_WR ;write to ram disk @@ -157,8 +136,6 @@ LD A,#FF ;запись в RAM-Disk EX AF,AF' LD HL,TEMP ;адрес буфера данных - ;LD BC,2*256 + BIOS.BLK_RD_WR ;число секторов и номер функции - ;RST ToBIOS_18 LD B,2 ;число секторов CALL BLK_RD_WR @@ -171,4 +148,25 @@ ASSERT 0, Invalid 'RECOVERYmountTYPE' variant - RECOVERYmountTYPE ENDIF ENDM -; \ No newline at end of file +; + +; + MACRO RST_to_BIOS + IF (IsInBIOS = 0) && ($ < #4000) + CALL ToBIOS_FromEXT + ELSE + RST ToBIOS_18 + ENDIF + ENDM + +; + +; + MACRO JP_to_BIOS + IF (IsInBIOS = 0) && ($ < #4000) + JP ToBIOS_FromEXT + ELSE + JP ToBIOS_18 + ENDIF + ENDM +; diff --git a/src/bios/shared/DCP_PAGE.bin b/src/bios/shared/DCP_PAGE.bin deleted file mode 100644 index 8f766b8..0000000 Binary files a/src/bios/shared/DCP_PAGE.bin and /dev/null differ diff --git a/src/bios/shared/DEFINES.INC b/src/bios/shared/DEFINES.INC index 5dacf55..7a8638e 100644 --- a/src/bios/shared/DEFINES.INC +++ b/src/bios/shared/DEFINES.INC @@ -1,25 +1,33 @@ -; _________________ -;---------[All shared defines]----------\/ \/ - DEFINE DEBUG 1;| ; добавляет строку и сообщение о тестовой сборке на стартовом экране - DEFINE NEW_FEATURE 0;| /\ ; !TODO пункты в сетап - DEFINE SET_NEWdcp 1;| \/ \/ ; !FIXIT тест нового dcp_init, пока не готова таблица портов - DEFINE PACKED_MAIN 0;| | ; паковать MAIN или влезает без этого? - DEFINE SetFullZXromLoader 0;| ; добавлять в прошивку и грузить все ROM спектрума или часть? - DEFINE IDE_Optimization 1;| ; слегка оптимизирует некоторые процедуры работы с HDD - DEFINE NeedSafePort_Y 1;| ============== ; говорит само за себя))) - DEFINE Pashalki 0; \__________________/\ - DEFINE PICTURE_FILE './src/bios/logo/psfathers.bmp';| -;____________________________________________________________/ - DEFINE RECOVERYrdChooseTYPE 1 ; 1 - RECOVERY всегда грузится в диск 15, 2 - ищется свободный рамдиск и если такого нет, то занимается 15ый - DEFINE RECOVERYmountTYPE 1 ; 1 - быстрый немного захардкоженый вариант. 2 - более "правильный" - - DEFINE SP2000_ConfID #FEFF - - DEFINE BIOS_ZXMODE 0 - - ; Задержка в кадрах после отрисовки логотипа (0 = 256) - DEFINE LOGO_DELAY_MIN 25 - DEFINE LOGO_DELAY_NORM 100 - DEFINE LOGO_DELAY_MAX 130 - ; -; \ No newline at end of file +;=======================[All shared EQUs]=======================; +BETA_BUILD EQU 0 ; 40 ; добавляет строку и сообщение о тестовой сборке на стартовом экране +BETA_RC EQU 0 ; 2 ; +RELEASEhotFIX EQU 0 ; + DEFINE RELEASE_BUILD_DATE "25.06.2025" +;======================[All shared defines]=====================; + DEFINE PACKED_MAIN 0 ; паковать MAIN или влезает без этого? + DEFINE SP2000_Loader_Flag #0107 ; + DEFINE IDE_Optimization 1 ; слегка оптимизирует некоторые процедуры работы с HDD + DEFINE NeedSafePort_Y 1 ; если 0, то в режиме без акселя некоторые процедуры могут засрать экран + DEFINE PICTURE_FILE './src/bios/logo/psfathers.bmp' ; + DEFINE StandartCGApallete 1 ; Подключать палитру из standart_colors.inc + DEFINE BitStream_SizeInPages 4 ; + DEFINE USE_E1_SCANCODE 0 ; + DEFINE RECOVERYmountTYPE 1 ; 1 - быстрый немного захардкоженый вариант. 2 - более "правильный" + DEFINE RECOVERYrdChooseTYPE 1 ; 1 - RECOVERY грузится в диск 15, 2 - ищется свободный рамдиск, если нет, то в 15-ый +;----[ Задержка в кадрах после отрисовки логотипа (0 = 256) ]---; + DEFINE LOGO_DELAY_MIN 25 ; + DEFINE LOGO_DELAY_NORM 100 ; + DEFINE LOGO_DELAY_MAX 130 ; +;----------------------------[ TEST ]---------------------------; + DEFINE STARTUP_SND 1 ; + DEFINE ERROR_POST_5 0 ; виснуть на ошибке в POST 5 + DEFINE TEST_INT 1 ; Тестовый обработчик пользовательского INT + DEFINE NEW_FEATURE 0 ; !TODO пункты в сетап +;DEFINE HDDwriteProtect 0 ; старая фишка для функций 5x + DEFINE UnusedSettingsFeatures 0 ; +;DEFINE OPTIMIZE_RW_PROCEDURE 0 ; + DEFINE BIG_ENDIAN_STR_PRINT 1 ; +; ; 0 - печать с порчей буфера и пропуском двойных пробелов - в 1,5 раза шустрее стока ;!FIXIT не затирает предыдущую строку +; ; 1 - печать с порчей буфера без пропуска двойных пробелов - в 3 раза шустрее стока +; ; 2 - печать без порчи буфера без пропуска двойных пробелов - сток +;===============================================================; \ No newline at end of file diff --git a/src/bios/shared/RECOVERY.IMG b/src/bios/shared/RECOVERY.IMG index 046720b..3df68d9 100644 Binary files a/src/bios/shared/RECOVERY.IMG and b/src/bios/shared/RECOVERY.IMG differ diff --git a/src/bios/shared/VERSION.inc b/src/bios/shared/VERSION.inc index f827a71..63f9d5d 100644 --- a/src/bios/shared/VERSION.inc +++ b/src/bios/shared/VERSION.inc @@ -1,41 +1,59 @@ ;============[For EXP part]============= -;---[Version of bitstream "VER.MOD"]---- - MODULE EXP_ID -VER EQU 3 ; Номер версии менять тут! -MOD EQU 05 ; Номер версии менять тут! - ENDMODULE -bitstream_ver_hex EQU EXP_ID.VER*256+EXP_ID.MOD +;------[Version of BIOS "VER.MOD"]------ +EXP_ID: +.VER EQU 3 ; Номер версии менять тут! +.MOD EQU 06 ; Номер версии менять тут! +BIOS_ver_hex EQU EXP_ID.VER*256+EXP_ID.MOD - DEFINE bitstream_ver_string '0'+EXP_ID.VER, '.', '0'+EXP_ID.MOD/10, '0'+EXP_ID.MOD-(EXP_ID.MOD/10)*10 + DEFINE BIOS_ver_string '0'+EXP_ID.VER, '.', '0'+EXP_ID.MOD/10, '0'+EXP_ID.MOD-(EXP_ID.MOD/10)*10 + + IF BETA_BUILD > 0 + IF BETA_RC > 0 + DEFINE BETA_str_ver "RC","0"+BETA_RC + ELSE + DEFINE BETA_str_ver "BETA ","0"+BETA_BUILD + ENDIF + ENDIF ;--------------------------------------- - - -; DEFINE Sp_MB_Ver '2000' - DEFINE BoardID_start #5283 - DEFINE BoardID_end #47E8 - DEFINE MotherBoardID #0000 + DEFINE BoardID_start #5283 + DEFINE BoardID_end #47E8 + DEFINE MotherBoardID #0000 + DEFINE MotherBoardType #00 ; !TODO 0 - Legacy, 1 - DX, 2 - Max ;======================================= +;█████████████████████████████████████████████████████████████████████████████████████████████████████████; - -;============[For ROM part]============= +;============[For ROM part]============= ;!FIXIT вы не понимаете, это другое)) ;-[Version of disk subsystem "VER.MOD"]- - MODULE ROM_ID -VER EQU 2 ; Номер версии менять тут! -MOD EQU 55 ; Номер версии менять тут! - ENDMODULE -Disk_subsystem_ver_hex EQU ROM_ID.VER*256+ROM_ID.MOD +ROM_ID: +.VER EQU 2 ; Номер версии менять тут! +.MOD EQU 56 ; Номер версии менять тут! +Disk_subsystem_ver_hex EQU ROM_ID.VER*256+ROM_ID.MOD DEFINE Disk_subsystem_ver_txt '0'+ROM_ID.VER, '.', '0'+ROM_ID.MOD/10, '0'+ROM_ID.MOD-(ROM_ID.MOD/10)*10 ;--------------------------------------- + IF RELEASEhotFIX != 0 + IF RELEASEhotFIX > 9 + DEFINE ReleaseHotFix ' Hotfix ', '0' + RELEASEhotFIX/10, '0' + (RELEASEhotFIX - (RELEASEhotFIX/10)*10) + ELSE + DEFINE ReleaseHotFix ' Hotfix ', '0' + RELEASEhotFIX + ENDIF + ELSE + DEFINE ReleaseHotFix "" + ENDIF +;█████████████████████████████████████████████████████████████████████████████████████████████████████████; - DEFINE SPTeam_year '2022' +;============[For CNF part]============= +CNF_ID: +.VER EQU 3 ; Номер версии менять тут! +.MOD EQU 05 ; Номер версии менять тут! +bitstream_ver_hex EQU CNF_ID.VER*256+CNF_ID.MOD + + DEFINE bitstream_ver_string '0'+CNF_ID.VER, '.', '0'+CNF_ID.MOD/10, '0'+CNF_ID.MOD-(CNF_ID.MOD/10)*10 +;--------------------------------------- +;█████████████████████████████████████████████████████████████████████████████████████████████████████████; + +;======================================= + DEFINE SPTeam_year BUILD_YEAR ;'2024' DEFINE SetupVer '1.60' - - -; -;2.48 New BIOS for Sp2000 -;2.50 02-08-2001 ADD BUILD-IN CD DRIVER (Not release) -;2.51 14-09-2001 Removed 2 IDE (if with_2ide) and added print board serial number -;2.52 Add new items to SETUP Utility for screen position. -;2.53 Add CMOS install routine. Disabled TRDOS install. -;======================================= \ No newline at end of file +;--------------------------------------- +;█████████████████████████████████████████████████████████████████████████████████████████████████████████; \ No newline at end of file diff --git a/src/bios/shared/includes.inc b/src/bios/shared/includes.inc index f94f13f..a3ecdd6 100644 --- a/src/bios/shared/includes.inc +++ b/src/bios/shared/includes.inc @@ -1,15 +1,16 @@ ; ;---------[All shared includes]--------- - INCLUDE 'src/bios/shared/DEFINES.INC' ; Shared defines - IF Pashalki - INCLUDE 'Shared_Includes/structures/EasterSprites.inc' - ENDIF - INCLUDE 'src/bios/Loader/Loader.asm' ; Bitstream loader as macros - INCLUDE 'src/bios/shared/CompMacro.asm' ; макросы - INCLUDE 'Shared_Includes/constants/SP2000.inc' ; константы + INCLUDE 'src/bios/shared/DEFINES.INC' ; Shared defines + INCLUDE 'Shared_Includes/structures/FileSystem.inc' + INCLUDE 'Shared_Includes/structures/ATA_ATAPI.inc' + INCLUDE 'src/bios/Loader/Loader.asm' ; Bitstream loader as macros + INCLUDE 'src/bios/shared/CompMacro.asm' ; макросы + INCLUDE 'Shared_Includes/constants/SP2000.inc' ; константы + INCLUDE 'Shared_Includes/constants/zx_char_codes.inc' ; константы + INCLUDE 'Shared_Includes/constants/zx_vars.inc' ; INCLUDE 'Shared_Includes/macroses/macros.z80' - INCLUDE 'src/bios/ROM/MEM_MAP.inc' ; карта памяти - INCLUDE 'src/bios/shared/VERSION.inc' ; Версия EXP и ROM + INCLUDE 'src/bios/ROM/MEM_MAP.inc' ; карта памяти + INCLUDE 'src/bios/shared/VERSION.inc' ; Версия EXP и ROM INCLUDE 'Shared_Includes/constants/BIOS_EQU.inc' INCLUDE 'src/bios/ROM/BIOS.inc' ;--------------------------------------- diff --git a/src/bios/test2.cmd b/src/bios/test2.cmd deleted file mode 100644 index 8e6fe81..0000000 --- a/src/bios/test2.cmd +++ /dev/null @@ -1,15 +0,0 @@ -@set variable=0 -@set main_file=0 -@setlocal disabledelayedexpansion -@set test=set variable=!main_file! - -@call :testing trtrt -@goto :eof - -:testing -@setlocal enabledelayedexpansion -@set main_file=%1 -@%test% -@setlocal disabledelayedexpansion -@echo %variable% -@goto :eof diff --git a/src/build_firmware.cmd b/src/build_firmware.cmd deleted file mode 100644 index 3c90b5f..0000000 --- a/src/build_firmware.cmd +++ /dev/null @@ -1,78 +0,0 @@ -@echo ------------------------------------------------------------[Build firmware start] -@if [%1]==[] (set NO_STOP="0") else (set NO_STOP=%1) -@if [%error_level%]==[] (set error_level="0") -@if %error_level% == "1" goto error -@set BIN=..\..\src\bin -@set ROMS=..\..\src\ZX_ROMS -@set BITSTREAM=..\..\src\altera\acex - -@cd ..\Build\Bin - -@if not exist ROM.BIN goto error_roms -@if not exist EXP.BIN goto error_roms -@if not exist LOADER_K30.BIN goto error_roms -@if not exist LOADER_K50.BIN goto error_roms - -@if not exist LOGO_PAL.BIN goto error_logo -@if not exist LOGO_DAT.BIN goto error_logo - -@if not exist %ROMS%\SP_128.BIN goto error_zxroms -@if not exist %ROMS%\SP__48.BIN goto error_zxroms -@if not exist %ROMS%\SP_TRD.BIN goto error_zxroms -@if not exist %ROMS%\SP_EXP.BIN goto error_zxroms -@if not exist %ROMS%\SP_EXP2.BIN goto error_zxroms - -@set FW=..\_SPRIN.BIN -@set LOADER=LOADER_K30.BIN -@call :make_rom_file -@set FW=..\_SPRIN50.BIN -@set LOADER=LOADER_K50.BIN -@call :make_rom_file -@goto quit - -:make_rom_file -@%BIN%\disk3.exe %FW% NUL 0H,40000H,0 -@%BIN%\disk3.exe %FW% ROM.BIN 0000H,4000H,0H -@%BIN%\disk3.exe %FW% LOGO_PAL.BIN 4000H,400H,0H -@%BIN%\disk3.exe %FW% LOGO_DAT.BIN 4400H,2400H -@%BIN%\disk3.exe %FW% %ROMS%\SP_128.BIN 8000H,4000H,0H -@%BIN%\disk3.exe %FW% %ROMS%\SP__48.BIN C000H,4000H,0H -@%BIN%\disk3.exe %FW% %ROMS%\SP_TRD.BIN 10000H,4000H,0H -@%BIN%\disk3.exe %FW% %ROMS%\SP_EXP.BIN 14000H,4000H,0H -@%BIN%\disk3.exe %FW% %ROMS%\SP_EXP.BIN 18000H,4000H,0H -@%BIN%\disk3.exe %FW% %ROMS%\SP_EXP2.BIN 1C000H,4000H,0H -@%BIN%\disk3.exe %FW% EXP.BIN 20000H,4000H,0H -@%BIN%\disk3.exe %FW% %LOADER% 30000H,4000H,0 -@goto :eof - -:error_roms -@echo. -@echo -------------------------------------------------------[ERROR during building firmware. ROM not found!] -@pause 0 -@exit 3 - -:error_logo -@echo. -@echo -------------------------------------------------------[ERROR during building firmware. LOGO not found!] -@pause 0 -@exit 3 - -:error_zxroms -@echo. -@echo -------------------------------------------------------[ERROR during building firmware. ZX-ROM not found!] -@pause 0 -@exit 3 - -:error -@echo. -@echo -------------------------------------------------------[ERROR during making firmware] -@pause 0 -@exit 3 - -:quit -@echo ------------------------------------------------------------[Build firmware done] -@echo. -@cd .. -@IF %NO_STOP% == "3" pause 0 -@IF %NO_STOP% == "0" pause 0 -@goto :eof diff --git a/src/doc/ATA Command Table in OpCode Order.pdf b/src/doc/ATA Command Table in OpCode Order.pdf deleted file mode 100644 index 55fff95..0000000 Binary files a/src/doc/ATA Command Table in OpCode Order.pdf and /dev/null differ diff --git a/src/doc/ATA Command Table in OpCode Order.xlsx b/src/doc/ATA Command Table in OpCode Order.xlsx deleted file mode 100644 index a0af16e..0000000 Binary files a/src/doc/ATA Command Table in OpCode Order.xlsx and /dev/null differ diff --git a/src/doc/ATA-ATAPI Command Set 3.pdf b/src/doc/ATA-ATAPI Command Set 3.pdf deleted file mode 100644 index 079b801..0000000 Binary files a/src/doc/ATA-ATAPI Command Set 3.pdf and /dev/null differ diff --git a/src/doc/changes.txt b/src/doc/changes.txt index 20e4e05..6f62241 100644 --- a/src/doc/changes.txt +++ b/src/doc/changes.txt @@ -1,41 +1,50 @@ -!TODO -- / Сделать EXP нового биоса совместимым с режимом спектрума, тогда освободится 1 страница в ПЗУ -- -| Адаптировать под новый совместимый EXP спектрумовские ПЗУ, тогда грузить на 1 страницу меньше -- \ получится, что EXP которое сейчас на месте расширенного Виртуального ПЗУ будет в ПЗУ????? -- Сжать хрустом ПЗУ спектрума и Логотип, ещё 1-2 страницы освободятся -- в сетап для сохранения ручных настроек HDD не те ячейки CMOS -- баг в режиме спектрума при выборе Clear RAM в меню и последующим выходом в ДОС по CAD - зависает, потому что вызывается процедура FullInit для очистки +TODO: +- пункт в сетапе "сохранять страницы спектрума при перезагрузке" +- перед инициализацией страниц спектрума и страницы 41 проверять, не заняты ли они рамдиском - чистить буфер клавы не втупую, а какими-нибудь командами для этих всяких SIO/PIO, если есть --+ ! в Setup добавлен пункт настройки времени и даты +-+ ! в Setup добавить пункт настройки времени и даты -+ исправлен баг со стеком в BLK_TO_RAMD и ещё несколько багов в процедурах чтения с РАМ-ДИСКА -+ теперь зарезервированные под режим спектрума страницы можно легко освободить, номер блока - 1 -+ активирован второй канал IDE -+ нумерация устройств IDE переделана с последовательной на физическую -+ выбор загрузочного IDE изменён с последовательного на физический -+ добавлена возможность установки IDE со второго канала в качестве основного и альтернативного загрузочного диска -+ сделан универсальный загрузчик битстрима для 1k30 и 1k50 -+ немного доработана система перехвата ресета для устранения некоторых глюков и на будущее -+ убрано залипание клавиш при ресете по Ctrl+Alt+Del -+ при некорректных значениях даты и времени в CMOS данные заменяются на дефолтные значения, выводится сообщение об ошибке -+ в Setup добавлен выбор режима развёртки (--------/Scorpion/Pentagon/Spectrum) -+ в Setup добавлен выбор вертикальной синхронизации (--------/312 50Гц/320 49Гц) -+ добавлена загрузка RECOVERY с ROM-Disk в ПЗУ -+ добавлена загрузка системы с RAM Disk -+ при холодном старте устанавливается инт пентагона (а не скорпиона), если в CMOS не задано иное +Done: ++ немного доработана система перехвата ресета для устранения некоторых глюков и на будущее ++ в сетап работает сохранение настроек HDD "Setup" после первого удачного автодетекта ++ Сделан универсальный загрузчик битстрима для 1k30 и 1k50 ++ Активирован второй канал IDE ++ Нумерация устройств IDE переделана с последовательной на физическую ++ Выбор загрузочного IDE изменён с последовательного на физический ++ Добавлена возможность установки IDE со второго канала в качестве основного и альтернативного загрузочного диска ++ Убрано залипание клавиш при ресете по Ctrl+Alt+Del ++ При некорректных значениях даты и времени в CMOS данные заменяются на дефолтные значения, выводится сообщение об ошибке ++ В Setup добавлен выбор режима развёртки (--------/Scorpion/Pentagon/Spectrum) ++ В Setup добавлен выбор вертикальной синхронизации (--------/312 50Гц/320 49Гц) ++ Добавлена загрузка системы с RAM Disk ++ Исправлен баг со стеком в BLK_TO_RAMD и ещё несколько багов в процедурах чтения с РАМ-ДИСКА ++ Добавлена загрузка RECOVERY с ROM-Disk в ПЗУ ++ При холодном старте устанавливается инт пентагона (а не скорпиона), если в CMOS не задано иное + Функция БИОС FN_SINC (#F2) при удачном завершении не сбрасывала флаг CF на выходе - исправлено -+ новая функция GET_RAMD_NUM -+ добавленые дополнительные опции в функцию БИОС FN_SINC (#F2), bit7 регистра A теперь отвечает за переключение старого/нового варианта работы функции (для сохранения совместимости со старыми программами) -+ добавлены образы ПЗУ ZX-Sprinter для запуска режима спектрума без загрузки DSS -+ новое лого при старте, разрешение изменено с 256х64 16 цветов на 128х72 256 цветов -+ изменена процедура вывода логотипа, логотип перенесён в другую страницу ПЗУ -+ смена языка, развёртки и инта происходит в Setup сразу -+ поправлен маловероятный, но возможный глюк с переполнением стека при входе-выходе из SETUP -+ поправлены буферы, оптимизированы некоторые процедуры, освобождено ббольше 1,5 кб ОЗУ для работы BIOS во время старта -+ изменены некоторые надписи и поправлена структура SETUP -+ найдено несколько древних мелких огрехов copy/paste, при работе было незаметно, но приятно, что нашлись -+ доделана функция FN_RESET -+ постепенный рефакторинг кода))) ++ Новая функция GET_RAMD_NUM ++ Добавленые дополнительные опции в функцию БИОС FN_SINC (#F2), bit7 регистра A теперь отвечает за переключение старого/нового + варианта работы функции (для сохранения совместимости со старыми программами) ++ Новое лого при старте, разрешение изменено с 256х64 16 цветов на 128х72 256 цветов ++ Изменена процедура вывода логотипа, логотип перенесён в другую страницу ПЗУ ++ Смена языка, развёртки и инта происходит в Setup сразу ++ Изменены некоторые надписи и поправлена структура SETUP ++ Доделана функция FN_RESET ++ Доделана функция DCP_CONFIG - функция управления дешифратором портов ++ Убрано задвоение функций 4х ++ Функции 5х перенесены из 0 в 8 страницу ПЗУ ++ Изменена функция инициализации DCP, освободилось около 4,5 кб ++ Теперь зарезервированные под режим спектрума страницы можно легко освободить, номер блока - 1 ++ Добавлены образы ПЗУ ZX-Sprinter для запуска режима спектрума без загрузки DSS ++ Страница BIOS совместима с адаптированными образами ПЗУ спектрума. Теперь отдельные страницы оригинальных SP_EXP и SP_EXP2 + не требуются. ++ Исправлен баг в режиме спектрума. При выборе Clear RAM в меню и последующим выходом в ДОС по CAD зависало, + потому что вызывалась процедура FullInit для очистки памяти. Теперь вместе с очисткой памяти сбрасывается перехват ресета ++ Поправлены буферы, оптимизированы некоторые процедуры, освобождено ббольше 1,5 кб ОЗУ для работы BIOS во время старта ++ Найдено несколько древних мелких огрехов copy/paste, при работе было незаметно, но приятно, что нашлись ++ Поправлен маловероятный, но возможный глюк с переполнением стека при входе-выходе из SETUP ++ Постепенный рефакторинг кода))) ++ Всего и не вспомнить уже... +==================================================================================================================================================================================================================== Новое описание функции БИОС FN_SINC (#F2) LD A,sync_mode ; режим синхронизации @@ -106,6 +115,7 @@ FN_RESET: ; ; старая версия BIOS ; + Новое описание функции GET_RAMD_NUM (#9B) GET_RAMD_NUM: ; получить номер RAM-Disk-а (0..15) по его block id LD A,id_blk ; идентификатор блока @@ -114,6 +124,7 @@ GET_RAMD_NUM: ; ; CF -> ошибка в идентификаторе блока или биос ниже 2.55 ; + Новое описание функции БИОС BLK_RD_WR (#C8) BLK_RD_WR: ; чтение/запись из/в блок(а) памяти секторами ; по 256 байт @@ -133,3 +144,12 @@ s_lines312 equ 7 s_wait_orig equ #18 s_wait_def equ #10 + +DCP_CONFIG: ; [x] функция управления дешифратором портов. + ;A - если ноль, то вызов функции переинициализации портов PORTS_INIT + ;HL - адрес + ;DE - маска - 0 изменяемые биты, 1 неизменяемые + ;B - порт + ;C - #F4 номер функции +; !FIXIT Функция позволяет открывать/закрывать дополнительные порты компьютера. +; \ No newline at end of file diff --git a/src/doc/testing.txt b/src/doc/testing.txt deleted file mode 100644 index 80ed436..0000000 --- a/src/doc/testing.txt +++ /dev/null @@ -1,166 +0,0 @@ -#55,#70,#64,#61,#74,#65,#20,#42,#49,#4F,#53 - - -#41,#76,#61,#69,#6C,#61,#62,#6C,#65 - -A - -IY+DRVHD_H - -ENDMSG - -FIND_AVAILABLE_STRUCT - -IDE2 - -DRVHD_H - - -ITMADDR EQU #BA00 - - - -IDE0 EQU #C1C0 -IDE1 EQU #C1C8 -IDE2 EQU #C1D0 -IDE3 EQU #C1D8 - - -sjasmplus.exe --nologo --syntax=f --fullpath --lst - -41482/256+256-41482 -24310+162 - -59 -246 - -=84 - - -csetup.bin = dsetup.asm packed -depack.bin = depack.asm -bsetup.bin = bsetup.asm + depack.bin + csetup.bin -extended.bin = extended.asm -ROM.BIN = rom.asm + extended.bin + bsetup.bin - - - -br pc == #D000 -b644 old -b71c new -ITMADDR EQU #BA00 ;;;;;;!!!!! -ITMTABS EQU #BA00 ;;;;!!!!!!b900 - -4D656D6F72792054 -#2C,#BA,#61,#BA,#96,#BA,#CB,#BA,#00,#BB,#3E,#BB,#79,#BB,#B0,#BB -2CBA61BA96BACBBA00BB3EBB79BBB0BB - - - -;Memory dump -;#0000-#3FFF : STANDART ROM BIOS -;#4000-#7BFF : NOT USED MEMORY -;#7C00-#7C7F : SYSTEM JUMP RESIDENT -;#7C80-#7DFF : NOT USED MEMORY -;#7E00-#7FFF : SECTOR BUFFER AND TEMPORY AREA -;#8000-#8002 : SETUP ENTRY POINT -;#8003-#80F0 : STACK FRAME -;#80F1-#80FD : NOT USED MEMORY -;#80FE-#80FF : INTERRUPT ADDRESS -;#8000-#B3FF : SETUP AND BOOT PROGRAM -;#B400-#BAFF : BOOT MESSAGES -;#B900-#BEFF : SETUP MESSAGES AND ITEMS -;#BF00-#BFFF : STACK FRAME -;#C000-#D8FF : NOT USED MEMORY -;#D900-#FFFF : UNPACKED LOGOTYPE - -;REGISTER #10 -; %00000111 - SYSTEM DISK -; %01110000 - ALT SYSTEM DISK - -;REGISTER #11 -; %00000011 - FDD FIRST 720 / 1.44 / NONE -; %00001100 - FDD SECOND -; %00110000 - IDE Primary MASTER AUTO / SETUP / DISABLED -; %11000000 - IDE Primary SLAVE -----//------ -;REGISTER #12 - CYLINDERS (MASTER) -;REGISTER #14 - HEADS (MASTER) -;REGISTER #15 - SECTORS (MASTER) -;REGISTER #16 - CYLINDERS (SLAVE) -;REGISTER #18 - HEADS (SLAVE) -;REGISTER #19 - SECTORS (SLAVE) -;REGISTER #1A - -;REGISTER #20 -; %00110000 - IDE Secondary MASTER AUTO / SETUP / DISABLED -; %11000000 - IDE Secondary SLAVE -----//------ - -ide0 #c1c0 -ide1 #c1c8 -ide2 #c1d0 -ide3 #c1d8 - -DTYPE_H = 7 - - CALL GET_AVAILABLE_STRUCT - LD A,#02 - CALL COMMONIDE - CALL GET_AVAILABLE_STRUCT - LD A,#03 - CALL COMMONIDE - - - CMOSARE: - DS 14 - DB SAVERAM+EXTBIOS ;X0E - OPTIONS - DB TDL250+TRATE30 ;X0F - KEYBOARD - DB SDIDE1+ASDFDD2 ;X10 - SYSTEM DISKS - DB FD1720+FD2720+HD1AUTO+HD2AUTO ;X11 - FDD & HDD - DB 0 ;X12 - CYLINDERS LOW MASTER - DB 0 ;X13 - CYLINDERS HIGH MASTER - DB 0 ;X14 - HEADS MASTER - DB 0 ;X15 - SECTORS MASTER - DB 0 ;X16 - CYLINDERS LOW SLAVE - DB 0 ;X17 - CYLINDERS HIGH SLAVE - DB 0 ;X18 - HEADS SLAVE - DB 0 ;X19 - SECTORS SLAVE - DB 0 ;X1A - COLOR STYLE - DB TURBON+SPRIN ;X1B - HARDARE CONF - DB BAS128 ;X1C - RESET MODE - DB REBOOTM ;X1D - REBOOT MSG, HDD W/P - DB %00000000 ;X1E - TRDOS - DB #77 ;X1F - SCREEN POSITION - DB HD1AUTO+HD2AUTO ;X20 - Secondary HDD's - DB %00000000 ;X21 - DB %00000000 ;X22 - DB %00000000 ;X23 - DB %00000000 ;X24 - DB %00000000 ;X25 - DB %00000000 ;X26 - DB %00000000 ;X27 - DB %00000000 ;X28 - DB %00000000 ;X29 - DB %00000000 ;X2A - DB %00000000 ;X2B - DB %00000000 ;X2C - DB %00000000 ;X2D - DB %00000000 ;X2E - DB %00000000 ;X2F - DB %00000000 ;X30 - DB %00000000 ;X31 - DB #19 ;X32 - CENTURY - DB %00000000 ;X33 - DB %00000000 ;X34 - DB %00000000 ;X35 - DB %00000000 ;X36 - DB %00000000 ;X37 - DB %00000000 ;X38 - DB %00000000 ;X39 - DB %00000000 ;X3A - DB %00000000 ;X3B - DB %00000000 ;X3C - DB %00000000 ;X3D - DB %00000000 ;X3E - DB %00000000 ;X3F - CHECKSUM - - logo_rastr_hrust.bin \ No newline at end of file diff --git a/src/doc/xFFD.txt b/src/doc/xFFD.txt deleted file mode 100644 index 50d12b1..0000000 --- a/src/doc/xFFD.txt +++ /dev/null @@ -1,25 +0,0 @@ -Pentagon & Scorpion - - #7FFD -bit0 \ -bit1 - ╨╜╨╛╨╝╨╡╤А ╤Б╤В╤А╨░╨╜╨╕╤Ж╤Л ╨Ю╨Ч╨г, ╨┐╨╛╨┤╨║╨╗╤О╤З╨╡╨╜╨╜╨╛╨╣ ╨▓ ╨▓╨╡╤А╤Е╨╜╨╕╨╡ 16 ╨Ъ╨С ╨┐╨░╨╝╤П╤В╨╕ ╤Б ╨░╨┤╤А╨╡╤Б╨░ #C000 -bit2 / - -bit3 - ╨▓╤Л╨▒╨╛╤А ╨╛╤В╨╛╨▒╤А╨░╨╢╨░╨╡╨╝╨╛╨╣ ╨▓╨╕╨┤╨╡╨╛╤Б╤В╤А╨░╨╜╨╕╤Ж╤Л. ╤Б╤В╤А╨░╨╜╨╕╤Ж╨░ 5 / ╤Б╤В╤А╨░╨╜╨╕╤Ж╨░ 7 -bit4 - ╨╜╨╛╨╝╨╡╤А ╤Б╤В╤А╨░╨╜╨╕╤Ж╤Л ╨Я╨Ч╨г. BASIC128 / BASIC48 - -bit5 \- ╨╖╨░╨┐╤А╨╡╤Й╨╡╨╜╨╕╨╡ ╤А╨░╤Б╤И╨╕╤А╨╡╨╜╨╜╨╛╨╣ ╨┐╨░╨╝╤П╤В╨╕ (48K ╨╖╨░╤Й╤С╨╗╨║╨░) ╨┐╤А╨╕ ╨▒╨╗╨╛╨║╨╕╤А╨╛╨▓╨░╨╜╨╜╨╛╨╣ ╨┐╨░╨╝╤П╤В╨╕ > 128 ╨║╨▒, ╨╕╨╜╨░╤З╨╡ ╤Б╤В╨░╤А╤И╨╕╨╣ ╨▒╨╕╤В ╨╜╨╛╨╝╨╡╤А╨░ ╤Б╤В╤А╨░╨╜╨╕╤Ж╤Л -bit6 - ╨╕╤Б╨┐╨╛╨╗╤М╨╖╤Г╤О╤В╤Б╤П ╨┐╤А╨╕ ╤А╨░╤Б╤И╨╕╤А╨╡╨╜╨╕╨╕ ╨┐╨░╨╝╤П╤В╨╕ ╨┤╨╛ 512K ╨▓ ╨▓╤Л╨▒╨╛╤А╨╡ ╨╜╨╛╨╝╨╡╤А╨░ ╤Б╤В╤А╨░╨╜╨╕╤Ж╤Л -bit7 / - - - #1FFD -bit0 тАУ ╨╛╤В╨║╤А╤Л╨▓╨░╨╡╤В ╨┤╨╛╤Б╤В╤Г╨┐ ╨╜╨░ ╤З╤В╨╡╨╜╨╕╨╡ ╨╕ ╨╖╨░╨┐╨╕╤Б╤М ╨▓ ╤Б╤В╤А╨░╨╜╨╕╤Ж╤Г RAM0 ╨╕╨╖ ╨╛╨║╨╜╨░ CPU0 (#0000-#3FFF). -bit1 тАУ ╨┐╤А╨╕ D1=1 ╨┐╨╛╨┤╤Б╤В╨░╨▓╨╗╤П╨╡╤В ╨▓ ╨╛╨║╨╜╨╛ CPU0 ╤Б╨╡╤А╨▓╨╕╤Б╨╜╤Г╤О ╤Б╤В╤А╨░╨╜╨╕╤Ж╤Г ╨╕╨╖ ╤В╨╡╨║╤Г╤Й╨╡╨│╨╛ ╨▓╤Л╨▒╤А╨░╨╜╨╜╨╛╨│╨╛ ╨▒╨░╨╜╨║╨░ ╨Я╨Ч╨г (ROM2) -bit2 - ╨╜╨╡ ╨╕╤Б╨┐╨╛╨╗╤М╨╖╤Г╨╡╤В╤Б╤П -bit3 - ╨╕╤Б╨┐╨╛╨╗╤М╨╖╤Г╨╡╤В╤Б╤П ╨║╨░╨║ ╤Б╨╕╨│╨╜╨░╨╗ ╨┐╨╡╤А╨╡╨┤╨░╤З╨╕ ╨┤╨░╨╜╨╜╤Л╤Е TxD ╨┐╤А╨╛╨│╤А╨░╨╝╨╝╨╜╨╛╨│╨╛ ╨╕╨╜╤В╨╡╤А╤Д╨╡╨╣╤Б╨░ RS232 - -bit4 - 1 - ╨┐╨╛╨┤╨║╨╗╤О╤З╨░╨╡╤В ╤Б╤В╤А╨░╨╜╨╕╤Ж╤Г ╨Ю╨Ч╨г ╨▓ ╨▒╨░╨╜╨║╤Г 3, ╨╜╨╛╨╝╨╡╤А ╤Б╤В╤А╨░╨╜╨╕╤Ж╤Л ╨▓ bit 2..0 #7FFD -bit5 - ╨╕╤Б╨┐╨╛╨╗╤М╨╖╤Г╨╡╤В╤Б╤П ╨║╨░╨║ ╤Б╨╕╨│╨╜╨░╨╗ ╨╕╨╜╤В╨╡╤А╤Д╨╡╨╣╤Б╨░ ╨┐╤А╨╕╨╜╤В╨╡╤А╨░ STROBE -bit6 - ╨╜╨╡ ╨╕╤Б╨┐╨╛╨╗╤М╨╖╤Г╨╡╤В╤Б╤П -bit7 - ╨╜╨╡ ╨╕╤Б╨┐╨╛╨╗╤М╨╖╤Г╨╡╤В╤Б╤П \ No newline at end of file diff --git a/src/doc/╨┐╨╡╤А╨╡╤Е╨▓╨░╤В╤Л ╤А╨╡╤Б╨╡╤В╨░.txt b/src/doc/╨┐╨╡╤А╨╡╤Е╨▓╨░╤В╤Л ╤А╨╡╤Б╨╡╤В╨░.txt index b69c7a0..7cf0991 100644 --- a/src/doc/╨┐╨╡╤А╨╡╤Е╨▓╨░╤В╤Л ╤А╨╡╤Б╨╡╤В╨░.txt +++ b/src/doc/╨┐╨╡╤А╨╡╤Е╨▓╨░╤В╤Л ╤А╨╡╤Б╨╡╤В╨░.txt @@ -1,9 +1,9 @@ -╨б╨╡╨╣╤З╨░╤Б ╨┐╤А╨╕ ╤Б╤В╨░╤А╤В╨╡ BIOS ╨╛╨▒╤А╨░╨▒╨░╤В╤Л╨▓╨░╤О╤В╤Б╤П ╤В╤А╨╕ ╨▓╨░╤А╨╕╨░╨╜╤В╨░ ╨┐╨╡╤А╨╡╤Е╨▓╨░╤В╨░ Reset: +Сейчас при старте BIOS обрабатываются три варианта перехвата Reset: --------------------------------[╨Т╨░╤А╨╕╨░╨╜╤В 1]------------------------------ -╨Я╨╛╤З╤В╨╕ ╤Б╤А╨░╨╖╤Г ╨┐╨╛╤Б╨╗╨╡ ╤А╨╡╤Б╨╡╤В╨░ ╤Б╨┐╨╡╤Ж╨╕╨░╨╗╤М╨╜╨░╤П ╨┐╤А╨╛╤Ж╨╡╨┤╤Г╤А╨░ ╨┐╤А╨╛╨▓╨╡╤А╤П╨╡╤В ╨▓ ╤Б╤В╤А╨░╨╜╨╕╤Ж╨╡ #40 -╨▓ ╨▒╨░╨╜╨║╨╡ 3 ╨┐╨╛ ╤Б╨╝╨╡╤Й╨╡╨╜╨╕╤О #FFE0 (RESTARTS) ╨╜╨░╨╗╨╕╤З╨╕╨╡ ╨┐╤А╨╛╨│╤А╨░╨╝╨╝╤Л ╨┐╨╡╤А╨╡╤Е╨▓╨░╤В╤З╨╕╨║╨░. -╨Я╨╡╤А╨▓╤Л╨╡ 12 ╨▒╨░╨╣╤В ╨┐╤А╨╛╨│╤А╨░╨╝╨╝╤Л ╨┤╨╛╨╗╨╢╨╜╤Л ╨▒╤Л╤В╤М ╤В╨░╨║╨╕╨╝╨╕ ╨┤╨╗╤П ╨┐╨╡╤А╨╡╤Е╨▓╨░╤В╨░: +-------------------------------[Вариант 1]------------------------------ +Почти сразу после ресета специальная процедура проверяет в странице #40 +в банке 3 по смещению #FFE0 (RESTARTS) наличие программы перехватчика. +Первые 12 байт программы должны быть такими для перехвата: ORG #FFE0 RESTARTS_PROG: LD HL,RESTARTS ; 3 @@ -14,24 +14,24 @@ RESTARTS_PROG: DJNZ .loop ; 2 NOP ; 1 NOP ; 1 -; ORG #FFEC ╤В╤Г╤В ╤А╨░╨╖╨╝╨╡╤Й╨░╨╡╤В╤Б╤П ╨┐╤А╨╛╨│╤А╨░╨╝╨╝╨░ ╨┐╨╡╤А╨╡╤Е╨▓╨░╤В╤З╨╕╨║ ╨┐╨╛╨╗╤М╨╖╨╛╨▓╨░╤В╨╡╨╗╤П -; ╨╛╤Б╤В╨░╤С╤В╤Б╤П 20 ╨▒╨░╨╣╤В╨╛╨▓ ╨╜╨░ ╨┐╤А╨╛╨│╤А╨░╨╝╨╝╤Г. +; ORG #FFEC тут размещается программа перехватчик пользователя +; остаётся 20 байтов на программу. -╨Я╤А╨╕ ╨┤╨░╨╜╨╜╨╛╨╝ ╨▓╨░╤А╨╕╨░╨╜╤В╨╡ ╨╖╨░╨│╤А╤Г╨╖╨║╨╕ ╨╢╨╡╨╗╨╡╨╖╨╛ ╨б╨┐╤А╨╕╨╜╤В╨╡╤А╨░ ╨╜╨╡ ╨┐╤А╨╛╨╕╨╜╨╕╤Ж╨╕╨░╨╗╨╕╨╖╨╕╤А╨╛╨▓╨░╨╜╨╛, -╨╜╨╡ ╤А╨░╨▒╨╛╤В╨░╨╡╤В ╨╡╤Й╤С ╨┤╨░╨╢╨╡ ╨║╨░╤А╤В╨░ ╨┐╨╛╤А╤В╨╛╨▓. ╨б╨║╨╛╤А╨╡╨╡ ╨▓╤Б╨╡╨│╨╛, ╤В╨░╨║╨╛╨╣ ╨▓╨░╤А╨╕╨░╨╜╤В -╨┐╨╡╤А╨╡╤Е╨▓╨░╤В╨░ - ╤Н╤В╨╛ ╨╜╨░╤Б╨╗╨╡╨┤╨╕╨╡ Sp97. ╨Ъ╨░╨║ ╨▓╨░╤А╨╕╨░╨╜╤В, ╨╡╨│╨╛ ╨╝╨╛╨╢╨╜╨╛ ╨╕╤Б╨┐╨╛╨╗╤М╨╖╨╛╨▓╨░╤В╤М ╨▓ ╤Б╨╗╤Г╤З╨░╨╡ -╨╖╨░╨┐╤Г╤Б╨║╨░ ╨║╨╛╨╜╤Д╤Л ╤Б╨╕╨╗╤М╨╜╨╛ ╨╛╤В╨╗╨╕╤З╨░╤О╤Й╨╡╨╣╤Б╤П ╨╛╤В ╤В╨╛╨╣, ╤З╤В╨╛ ╨╛╨╢╨╕╨┤╨░╨╡╤В BIOS. ╨Ф╨╗╤П ╤Н╤В╨╛╨│╨╛ ╨╜╤Г╨╢╨╜╨╛, -╤З╤В╨╛╨▒ ╨┐╤А╨╕ ╤Б╤В╨░╤А╤В╨╡ ╨░╨╗╤М╤В╨╡╤А╤Л ╨║╨╛╨╜╤Д╨░ ╨┐╨╛╨┤╨║╨╗╤О╤З╨░╨╗╨░ ╤Б╨╗╨╡╨┤╤Г╤О╤Й╨╕╨╡ ╤Б╤В╤А╨░╨╜╨╕╤Ж╤Л ╨┐╨╛ ╨▒╨░╨╜╨║╨░╨╝: +При данном варианте загрузки железо Спринтера не проинициализировано, +не работает ещё даже карта портов. Скорее всего, такой вариант +перехвата - это наследие Sp97. Как вариант, его можно использовать в случае +запуска конфы сильно отличающейся от той, что ожидает BIOS. Для этого нужно, +чтоб при старте альтеры конфа подключала следующие страницы по банкам: BANK0 - ROM #08 BANK1 - RAM #05 BANK2 - RAM #02 BANK3 - RAM #40 ------------------------------------------------------------------------ --------------------------------[╨Т╨░╤А╨╕╨░╨╜╤В 2]------------------------------ +-------------------------------[Вариант 2]------------------------------ ------------------------------------------------------------------------ --------------------------------[╨Т╨░╤А╨╕╨░╨╜╤В 3]------------------------------ +-------------------------------[Вариант 3]------------------------------ ------------------------------------------------------------------------ \ No newline at end of file diff --git a/src/make_firmware.cmd b/src/make_firmware.cmd deleted file mode 100644 index 2019faa..0000000 --- a/src/make_firmware.cmd +++ /dev/null @@ -1,19 +0,0 @@ -@echo ------------------------------------------------------------[Make firmware start] -@if [%1]==[] (set NO_STOP=0) else (set NO_STOP=%1) -@cd altera -@call make_altera.cmd - -@cd ..\.. -@call src\bios\make_bios.cmd %no_stop% -@if %error_level% == "0" goto exit - -:error -@echo. -@echo -------------------------------------------------------[ERROR during making firmware] -@pause 0 -@exit 3 - -:exit -@echo ------------------------------------------------------------[Make firmware done] -@echo. - diff --git a/start_emul.cmd b/start_emul.cmd deleted file mode 100644 index 5d3f569..0000000 --- a/start_emul.cmd +++ /dev/null @@ -1 +0,0 @@ -start Shared_Includes\Hide\Emulators\ZXMAK2\ZXMAK2.exe \ No newline at end of file