Sprinter-Core/src/bios/loader/loader.asm
Anatoliy Belyanskiy 8bd9b2a3fc temp
2024-01-05 01:20:40 +10:00

170 lines
3.9 KiB
NASM
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;
;**********************************;
; ACEX Loading program ;
;**********************************;
MACRO Conf_loader altera_chip
.START: DI
LD BC,#FF*256 + Z84.SYS.Control
XOR A ; Z84.REG.WaitState_Ctrl - register - waits
OUT (C),A ; Z84.SYS.Control
INC C ; LD BC,#FFEF
LD A,4 ; Memory waits set to 1
OUT (C),A ; Z84.SYS.Data
DEC C ; Z84.SYS.Control
DEC A ; LD A,3 - 3-nd register - boundaries
OUT (C),A ; Z84.REG.Misc_Ctrl
INC C ; cs0 enable, cs1 enable, 32-Bit CRC disable, reset output enable, Clock Divide-by-two
OUT (C),A ; Z84.SYS.Data
DEC C ; Z84.SYS.Control
DEC A ; LD A,2 - Z84.REG..CS_Boundary 2-nd register - boundaries
OUT (C),A ; Z84.SYS.Data
INC C
LD A,#FE ; boundaries FFFF..F000 - CS1
OUT (C),A ; EFFF..0000 - CS0
JR .LOOP_S1
;**************************************
BLOCK #38-$,#FF
JP 0
;**************************************
.LOOP_S1:
LD HL,#FEF0 ; !HARDCODE
LD DE,.STRING
.LOOP_S:
LD A,(DE)
CP (HL)
JR NZ,.NO_CNF_RAM
INC E
INC L
JR NZ,.LOOP_S ; !!!!! ¯à¨¢ï§ª  ª  ¤à¥áã ¢ HL
; !TODO ã¡à âì ¢¥©âë ¤«ï ªíè ?
LD BC,#FF*256 + Z84.SYS.Control
LD A,Z84.REG.CS_Boundary ; !HARDCODE
OUT (C),A ; 0 register - waits
INC C
LD A,#F0
OUT (C),A ; boundaries FFFF..1000 - CS1
; 0FFF..0000 - CS0
LD HL,#1000 ; !!!!! Load bitstream from Fast-RAM
JR .NEW_SHM
;**************************************
BLOCK #66-$,#FF
JP 0
;**************************************
.NO_CNF_RAM:
LD HL,#0100 ; !!!!! Load bitstream from ROM
.NEW_SHM:
;--------------[conf check]-------------
LD A,H ; á®å࠭塞 áâ à訩  ¤à¥á ­ ç «  ª®­äë,
; ­ ç «® ª®­äë ¤®«¦­® ¡ëâì á ¬« ¤è¨¬  ¤à¥á®¬ = 0
EXX
LD L,0
LD H,A
EX AF,AF'
; ¢ HL  ¤à¥á ¯¥à¢®£® ¡ ©â  ª®­äë
LD DE,.Conf_header
LD B,.Conf_header.length
.conf_header_loop:
LD A,(DE)
CP (HL)
JR NZ,.Conf_Packed
INC DE
INC L
DJNZ .conf_header_loop
XOR A
JR .exit_conf_check
.Conf_Packed:
SCF
.exit_conf_check:
EX AF,AF'
EXX
;---------------------------------------
LD DE,#FE00 ;!HARDCODE ; !!!!! Check flag "don't erase fast-ram bitstream" - "IM"
LD A,(#FEE0)
CP "I"
JR NZ,.ONES_CONFIG
LD A,(#FEE1)
CP "M"
JR NZ,.ONES_CONFIG
DEC D ; multiple config!
.ONES_CONFIG:
LD IY,SP2000_Loader_Flag
;LD IX,#FFFD
LD IX,ACEX.Config_ID.Sp2000
.LOOP1:
LD A,(HL)
ex af,AF'
ld b,1
jr nc,.no_packed_loop
ex af,AF'
LD B,A ; save byte to B to check later if we worked with zero
OR A
JR NZ,.LOOP1A
INC HL
LD C,(HL) ; set counter
jr .LOOP1A
.no_packed_loop:
ex af,AF'
.LOOP1A:
;---[Sending bits to Altera]---[v]
DUP 7
LD (DE),A
RRCA
EDUP
LD (DE),A
;------------------------------[^]
INC E
LD A,B ; was it zero?
OR A
JR NZ,.LOOP1E
; it was zero so we need to decrement counter
DEC C
JR NZ,.LOOP1A
; end of the counter reached
.LOOP1E:
INC HL
JR .LOOP1
.STRING: DB ACEX.RELOAD_STRING
.Conf_header: include 'src/bios/Loader/bitstream_header.inc'
.Conf_header.length EQU $-.Conf_header
;----------------------;
BLOCK #FE-$,#FF
; <20>â®, ᪮॥ ¢á¥£®, à㤨¬¥­â, â®â á ¬ë© ¡ ©â ®¯¨á â¥«ï ª®­äë,
; ª®â®àë© ¨é¥â § £àã§ç¨ª ¤«ï Sp97 ¯® áâ à®¬ã  ¤à¥áã #C090.
; ‚®âª­ã« ¥£® ¢ ª®­æ¥ § £àã§ç¨ª , ¬®¦¥â ¯®â®¬ ¯à¨£®¤¨âáï.
.DEF_SYM: DW ACEX.Config_ID.Sp2000
;------------------------------[Loader end]
DEFINE Altera_Chip altera_chip
LUA
local file_path = 'Build/Bin/temp/'
local file_ext = '.BIN'
local altera_ver = sj.get_define("Altera_Chip")
sj.insert_define("Altera_File", '"' .. file_path .. altera_ver .. file_ext .. '"')
ENDLUA
UNDEFINE Altera_Chip
INCBIN Altera_File
UNDEFINE Altera_File
ENDM
;