654 lines
17 KiB
Plaintext
654 lines
17 KiB
Plaintext
--
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-- Copyright (C) 1988-2000 Altera Corporation
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-- Any megafunction design, and related net list (encrypted or decrypted),
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-- support information, device programming or simulation file, and any other
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-- associated documentation or information provided by Altera or a partner
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-- under Altera's Megafunction Partnership Program may be used only to
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-- program PLD devices (but not masked PLD devices) from Altera. Any other
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-- use of such megafunction design, net list, support information, device
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-- programming or simulation file, or any other related documentation or
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-- information is prohibited for any other purpose, including, but not
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-- limited to modification, reverse engineering, de-compiling, or use with
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-- any other silicon devices, unless such use is explicitly licensed under
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-- a separate agreement with Altera or a megafunction partner. Title to
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-- the intellectual property, including patents, copyrights, trademarks,
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-- trade secrets, or maskworks, embodied in any such megafunction design,
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-- net list, support information, device programming or simulation file, or
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-- any other related documentation or information provided by Altera or a
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-- megafunction partner, remains with Altera, the megafunction partner, or
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-- their respective licensors. No other licenses, including any licenses
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-- needed under any third party's intellectual property, are provided herein.
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--
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CHIP SP2_MAX
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BEGIN
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DEVICE = EPM7064STC100-10;
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|GND65 : INPUT_PIN = 65;
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|GND33 : INPUT_PIN = 33;
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|/CONF_X : BIDIR_PIN = 54;
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|10K_D0 : OUTPUT_PIN = 58;
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|CLKZZ : BIDIR_PIN = 32;
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|10K_CLK : OUTPUT_PIN = 56;
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|XHD2_CS2 : OUTPUT_PIN = 83;
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|XHD2_CS1 : OUTPUT_PIN = 81;
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|XHD1_CS2 : OUTPUT_PIN = 80;
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|XHD1_CS1 : OUTPUT_PIN = 79;
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|XHD_WR : OUTPUT_PIN = 75;
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|XHD_RES : OUTPUT_PIN = 71;
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|XHD_RD : OUTPUT_PIN = 76;
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|WR_PDOS : OUTPUT_PIN = 8;
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|/WG_WR : OUTPUT_PIN = 93;
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|/WG_RD : OUTPUT_PIN = 97;
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|WDAT : OUTPUT_PIN = 98;
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|TG42_OUT : OUTPUT_PIN = 85;
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|TG42_BUF : OUTPUT_PIN = 36;
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|SINC_2 : OUTPUT_PIN = 19;
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|SINC_1 : OUTPUT_PIN = 20;
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|SINC_V : OUTPUT_PIN = 64;
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|SINC_H : OUTPUT_PIN = 68;
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|SINC : OUTPUT_PIN = 67;
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|QDAT : OUTPUT_PIN = 16;
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|HD_DIR : OUTPUT_PIN = 48;
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|HD_CS : OUTPUT_PIN = 52;
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|FDAT : OUTPUT_PIN = 14;
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|DENS_X : OUTPUT_PIN = 96;
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|CMOS_DWR : OUTPUT_PIN = 100;
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|CMOS_DRD : OUTPUT_PIN = 99;
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|CMOS_AS : OUTPUT_PIN = 6;
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|CLK14 : OUTPUT_PIN = 31;
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|CLK_WG : OUTPUT_PIN = 13;
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|BEEP : OUTPUT_PIN = 84;
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|AUD : OUTPUT_PIN = 35;
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|XHR_RDY : INPUT_PIN = 88;
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|XA2 : INPUT_PIN = 23;
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|XA1 : INPUT_PIN = 21;
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|XA0 : INPUT_PIN = 17;
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|XACS : INPUT_PIN = 37;
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|WSTB : INPUT_PIN = 10;
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|WR_CNF : INPUT_PIN = 57;
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|WD : INPUT_PIN = 9;
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|VGA_IN : INPUT_PIN = 61;
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|TR43 : INPUT_PIN = 12;
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|TG42_IN : INPUT_PIN = 87;
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|STE : INPUT_PIN = 94;
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|SR : INPUT_PIN = 29;
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|SL : INPUT_PIN = 30;
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|SINC_IN : INPUT_PIN = 69;
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|RSTB : INPUT_PIN = 25;
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|RDAT : INPUT_PIN = 92;
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|PW_GOOD : INPUT_PIN = 90;
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|HDD_C3 : INPUT_PIN = 40;
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|HDD_C2 : INPUT_PIN = 41;
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|HDD_C1 : INPUT_PIN = 42;
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|HDD_C0 : INPUT_PIN = 47;
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|FDD_C2 : INPUT_PIN = 46;
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|FDD_C1 : INPUT_PIN = 45;
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|FDD_C0 : INPUT_PIN = 44;
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|EPM_RES : INPUT_PIN = 89;
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|D0 : INPUT_PIN = 60;
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END;
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DEFAULT_DEVICES
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BEGIN
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AUTO_DEVICE = EPM7256SQC208-7;
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AUTO_DEVICE = EPM7256SRC208-7;
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AUTO_DEVICE = EPM7192SQC160-7;
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AUTO_DEVICE = EPM7160SQC160-6;
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AUTO_DEVICE = EPM7160STC100-6;
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AUTO_DEVICE = EPM7160SLC84-6;
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AUTO_DEVICE = EPM7128SQC160-6;
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AUTO_DEVICE = EPM7128STC100-6;
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AUTO_DEVICE = EPM7128SQC100-6;
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AUTO_DEVICE = EPM7128SLC84-6;
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AUTO_DEVICE = EPM7064STC100-5;
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AUTO_DEVICE = EPM7064SLC84-5;
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AUTO_DEVICE = EPM7064STC44-5;
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AUTO_DEVICE = EPM7064SLC44-5;
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AUTO_DEVICE = EPM7032STC44-5;
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AUTO_DEVICE = EPM7032SLC44-5;
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ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
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END;
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TIMING_POINT
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BEGIN
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DEVICE_FOR_TIMING_SYNTHESIS = EPM7064STC100-10;
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FREQUENCY = 100MHz;
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MAINTAIN_STABLE_SYNTHESIS = OFF;
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CUT_ALL_CLEAR_PRESET = ON;
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CUT_ALL_BIDIR = ON;
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END;
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IGNORED_ASSIGNMENTS
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BEGIN
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FIT_IGNORE_TIMING = ON;
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DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
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IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
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IGNORE_DEVICE_ASSIGNMENTS = OFF;
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IGNORE_LC_ASSIGNMENTS = OFF;
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IGNORE_PIN_ASSIGNMENTS = OFF;
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IGNORE_CHIP_ASSIGNMENTS = OFF;
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IGNORE_TIMING_ASSIGNMENTS = OFF;
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IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
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IGNORE_CLIQUE_ASSIGNMENTS = OFF;
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END;
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LOGIC_OPTIONS
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BEGIN
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|LR_T1 : TURBO_BIT = ON;
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|LR_T0 : TURBO_BIT = ON;
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|CLK_WG : TURBO_BIT = ON;
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|TG42_BUF : STYLE = WYSIWYG;
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|TG42_OUT : STYLE = WYSIWYG;
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|XHD_RD : TURBO_BIT = OFF;
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|XHD_RES : TURBO_BIT = OFF;
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|XHD_WR : TURBO_BIT = OFF;
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|XHD1_CS1 : TURBO_BIT = OFF;
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|XHD1_CS2 : TURBO_BIT = OFF;
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|XHD2_CS1 : TURBO_BIT = OFF;
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|XHD2_CS2 : TURBO_BIT = OFF;
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|10K_CLK : TURBO_BIT = OFF;
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|10K_D0 : TURBO_BIT = OFF;
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|REG_P0 : TURBO_BIT = ON;
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|REG_P1 : TURBO_BIT = ON;
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|REG_P2 : TURBO_BIT = ON;
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|TG42_BUF : TURBO_BIT = ON;
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|TG42_OUT : TURBO_BIT = ON;
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|STWG0 : TURBO_BIT = ON;
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|STWG1 : TURBO_BIT = ON;
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|STWG2 : TURBO_BIT = ON;
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|XCT0 : TURBO_BIT = ON;
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|XCT1 : TURBO_BIT = ON;
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END;
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GLOBAL_PROJECT_DEVICE_OPTIONS
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BEGIN
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MULTIVOLT_IO = OFF;
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SECURITY_BIT = ON;
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MAX7000B_ENABLE_VREFB = OFF;
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MAX7000B_ENABLE_VREFA = OFF;
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MAX7000B_VCCIO_IOBANK2 = 3.3V;
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MAX7000B_VCCIO_IOBANK1 = 3.3V;
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CONFIG_EPROM_PULLUP_RESISTOR = ON;
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CONFIG_EPROM_USER_CODE = FFFFFFFF;
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FLEX_CONFIGURATION_EPROM = AUTO;
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MAX7000AE_ENABLE_JTAG = ON;
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MAX7000AE_USER_CODE = FFFFFFFF;
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FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
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FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
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FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
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FLEX6000_ENABLE_JTAG = OFF;
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CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
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MAX7000S_ENABLE_JTAG = ON;
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FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
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MAX7000S_USER_CODE = FFFF;
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CONFIG_SCHEME_10K = PASSIVE_SERIAL;
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FLEX10K_JTAG_USER_CODE = 7F;
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ENABLE_INIT_DONE_OUTPUT = OFF;
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ENABLE_CHIP_WIDE_OE = OFF;
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ENABLE_CHIP_WIDE_RESET = OFF;
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nCEO = UNRESERVED;
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CLKUSR = UNRESERVED;
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ADD17 = UNRESERVED;
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ADD16 = UNRESERVED;
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ADD15 = UNRESERVED;
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ADD14 = UNRESERVED;
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ADD13 = UNRESERVED;
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ADD0_TO_ADD12 = UNRESERVED;
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SDOUT = RESERVED_DRIVES_OUT;
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RDCLK = UNRESERVED;
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RDYnBUSY = UNRESERVED;
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nWS_nRS_nCS_CS = UNRESERVED;
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DATA1_TO_DATA7 = UNRESERVED;
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DATA0 = RESERVED_TRI_STATED;
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FLEX8000_ENABLE_JTAG = OFF;
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CONFIG_SCHEME = ACTIVE_SERIAL;
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DISABLE_TIME_OUT = OFF;
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ENABLE_DCLK_OUTPUT = OFF;
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RELEASE_CLEARS = OFF;
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AUTO_RESTART = OFF;
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USER_CLOCK = OFF;
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RESERVED_PINS_PERCENT = 0;
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RESERVED_LCELLS_PERCENT = 0;
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END;
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GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
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BEGIN
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STYLE = NORMAL;
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AUTO_GLOBAL_CLEAR = OFF;
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AUTO_GLOBAL_CLOCK = OFF;
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DEVICE_FAMILY = MAX7000S;
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MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
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AUTO_IMPLEMENT_IN_EAB = OFF;
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AUTO_OPEN_DRAIN_PINS = ON;
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ONE_HOT_STATE_MACHINE_ENCODING = OFF;
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AUTO_REGISTER_PACKING = OFF;
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AUTO_FAST_IO = OFF;
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AUTO_GLOBAL_OE = ON;
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AUTO_GLOBAL_PRESET = ON;
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MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
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OPTIMIZE_FOR_SPEED = 5;
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END;
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COMPILER_PROCESSING_CONFIGURATION
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BEGIN
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FITTER_SETTINGS = ADVANCED;
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USE_QUARTUS_FITTER = OFF;
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PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
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SMART_RECOMPILE = OFF;
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GENERATE_AHDL_TDO_FILE = OFF;
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RPT_FILE_USER_ASSIGNMENTS = ON;
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RPT_FILE_LCELL_INTERCONNECT = ON;
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RPT_FILE_HIERARCHY = ON;
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RPT_FILE_EQUATIONS = ON;
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LINKED_SNF_EXTRACTOR = OFF;
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OPTIMIZE_TIMING_SNF = OFF;
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TIMING_SNF_EXTRACTOR = ON;
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FUNCTIONAL_SNF_EXTRACTOR = OFF;
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DESIGN_DOCTOR_RULES = EPLD;
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DESIGN_DOCTOR = OFF;
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END;
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COMPILER_INTERFACES_CONFIGURATION
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BEGIN
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NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
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EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
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EDIF_BUS_DELIMITERS = [];
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EDIF_FLATTEN_BUS = OFF;
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EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
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EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
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EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
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EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
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EDIF_OUTPUT_USE_EDC = OFF;
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EDIF_INPUT_USE_LMF2 = OFF;
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EDIF_INPUT_USE_LMF1 = OFF;
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EDIF_OUTPUT_GND = GND;
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EDIF_OUTPUT_VCC = VCC;
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EDIF_INPUT_GND = GND;
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EDIF_INPUT_VCC = VCC;
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EDIF_OUTPUT_EDC_FILE = *.edc;
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EDIF_INPUT_LMF2 = *.lmf;
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EDIF_INPUT_LMF1 = *.lmf;
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VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
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VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
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VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
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VHDL_FLATTEN_BUS = OFF;
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VERILOG_FLATTEN_BUS = OFF;
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EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
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VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
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VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
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VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
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VHDL_WRITER_VERSION = VHDL87;
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VHDL_READER_VERSION = VHDL87;
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SYNOPSYS_MAPPING_EFFORT = MEDIUM;
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SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
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SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
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SYNOPSYS_DESIGNWARE = OFF;
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SYNOPSYS_COMPILER = DESIGN;
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USE_SYNOPSYS_SYNTHESIS = OFF;
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VHDL_NETLIST_WRITER = OFF;
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VERILOG_NETLIST_WRITER = OFF;
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XNF_GENERATE_AHDL_TDX_FILE = ON;
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XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
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XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
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EDIF_OUTPUT_VERSION = 200;
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EDIF_NETLIST_WRITER = OFF;
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END;
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CUSTOM_DESIGN_DOCTOR_RULES
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BEGIN
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MASTER_RESET = OFF;
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EXPANDER_NETWORKS = ON;
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RACE_CONDITIONS = ON;
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DELAY_CHAINS = ON;
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ASYNCHRONOUS_INPUTS = ON;
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PRESET_CLEAR_NETWORKS = ON;
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STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
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STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
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MULTI_CLOCK_NETWORKS = ON;
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MULTI_LEVEL_CLOCKS = ON;
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GATED_CLOCKS = ON;
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RIPPLE_CLOCKS = ON;
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END;
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SIMULATOR_CONFIGURATION
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BEGIN
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END_TIME = 25.0us;
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BIDIR_PIN = STRONG;
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START_TIME = 0.0ns;
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GLITCH_TIME = 0.0ns;
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GLITCH = OFF;
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OSCILLATION_TIME = 0.0ns;
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OSCILLATION = OFF;
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CHECK_OUTPUTS = OFF;
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SETUP_HOLD = OFF;
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USE_DEVICE = OFF;
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END;
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TIMING_ANALYZER_CONFIGURATION
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BEGIN
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ANALYSIS_MODE = REGISTERED_PERFORMANCE;
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CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
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LIST_PATH_FREQUENCY = 10MHz;
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LIST_PATH_COUNT = 10;
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REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
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INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
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INCLUDE_PATHS_LESS_THAN = OFF;
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INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
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INCLUDE_PATHS_GREATER_THAN = OFF;
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DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
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CELL_WIDTH = 18;
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LIST_ONLY_LONGEST_PATH = ON;
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CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
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CUT_OFF_IO_PIN_FEEDBACK = ON;
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AUTO_RECALCULATE = OFF;
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END;
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OTHER_CONFIGURATION
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BEGIN
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LAST_MAXPLUS2_VERSION = 10.0;
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ROW_PINS_LCELL_INSERT = ON;
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CARRY_OUT_PINS_LCELL_INSERT = OFF;
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NORMAL_LCELL_INSERT = ON;
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EXPLICIT_FAMILY = 1;
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FLEX_10K_52_COLUMNS = 40;
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DEFAULT_9K_EXP_PER_LCELL = 1/2;
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LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
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LCELLS_PER_ROW_PERCENT = 100;
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FAN_IN_PER_LCELL_PERCENT = 100;
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EXP_PER_LCELL_PERCENT = 100;
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ROW_PINS_PERCENT = 50;
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ORIGINAL_MAXPLUS2_VERSION = 9.6;
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COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
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END;
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DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
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BEGIN
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REGISTER_OPTIMIZATION = ON;
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RESYNTHESIZE_NETWORK = ON;
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MULTI_LEVEL_FACTORING = ON;
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SUBFACTOR_EXTRACTION = ON;
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REFACTORIZATION = ON;
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NOT_GATE_PUSH_BACK = ON;
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DUPLICATE_LOGIC_EXTRACTION = ON;
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REDUCE_LOGIC = ON;
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DECOMPOSE_GATES = ON;
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SOFT_BUFFER_INSERTION = ON;
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CARRY_CHAIN = IGNORE;
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CASCADE_CHAIN = IGNORE;
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MINIMIZATION = FULL;
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FAST_IO = OFF;
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IGNORE_SOFT_BUFFERS = OFF;
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USE_LPM_FOR_AHDL_OPERATORS = OFF;
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PARALLEL_EXPANDERS = OFF;
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TURBO_BIT = OFF;
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XOR_SYNTHESIS = ON;
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SLOW_SLEW_RATE = OFF;
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END;
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DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
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BEGIN
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TURBO_BIT = ON;
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REGISTER_OPTIMIZATION = ON;
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RESYNTHESIZE_NETWORK = ON;
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MULTI_LEVEL_FACTORING = ON;
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SUBFACTOR_EXTRACTION = ON;
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REFACTORIZATION = ON;
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NOT_GATE_PUSH_BACK = ON;
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DUPLICATE_LOGIC_EXTRACTION = ON;
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REDUCE_LOGIC = ON;
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DECOMPOSE_GATES = ON;
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SOFT_BUFFER_INSERTION = ON;
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CARRY_CHAIN = IGNORE;
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CASCADE_CHAIN = IGNORE;
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MINIMIZATION = FULL;
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FAST_IO = OFF;
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IGNORE_SOFT_BUFFERS = OFF;
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USE_LPM_FOR_AHDL_OPERATORS = OFF;
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PARALLEL_EXPANDERS = OFF;
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XOR_SYNTHESIS = ON;
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SLOW_SLEW_RATE = OFF;
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END;
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DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
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BEGIN
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REGISTER_OPTIMIZATION = OFF;
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RESYNTHESIZE_NETWORK = ON;
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MULTI_LEVEL_FACTORING = OFF;
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SUBFACTOR_EXTRACTION = OFF;
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REFACTORIZATION = OFF;
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NOT_GATE_PUSH_BACK = ON;
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DUPLICATE_LOGIC_EXTRACTION = OFF;
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REDUCE_LOGIC = OFF;
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DECOMPOSE_GATES = ON;
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SOFT_BUFFER_INSERTION = ON;
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|
CARRY_CHAIN = IGNORE;
|
|
CASCADE_CHAIN = IGNORE;
|
|
MINIMIZATION = FULL;
|
|
FAST_IO = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
TURBO_BIT = ON;
|
|
XOR_SYNTHESIS = OFF;
|
|
SLOW_SLEW_RATE = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
|
|
BEGIN
|
|
CARRY_CHAIN_LENGTH = 32;
|
|
CASCADE_CHAIN_LENGTH = 2;
|
|
REGISTER_OPTIMIZATION = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
SUBFACTOR_EXTRACTION = ON;
|
|
REFACTORIZATION = ON;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
CARRY_CHAIN = IGNORE;
|
|
CASCADE_CHAIN = IGNORE;
|
|
MINIMIZATION = FULL;
|
|
IGNORE_SOFT_BUFFERS = ON;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
TURBO_BIT = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
SLOW_SLEW_RATE = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
|
|
BEGIN
|
|
REGISTER_OPTIMIZATION = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
REFACTORIZATION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
CARRY_CHAIN = IGNORE;
|
|
CASCADE_CHAIN = IGNORE;
|
|
MINIMIZATION = FULL;
|
|
FAST_IO = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
TURBO_BIT = OFF;
|
|
XOR_SYNTHESIS = ON;
|
|
SLOW_SLEW_RATE = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
|
|
BEGIN
|
|
TURBO_BIT = ON;
|
|
SLOW_SLEW_RATE = OFF;
|
|
XOR_SYNTHESIS = ON;
|
|
REGISTER_OPTIMIZATION = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
REFACTORIZATION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
CARRY_CHAIN = IGNORE;
|
|
CASCADE_CHAIN = IGNORE;
|
|
MINIMIZATION = FULL;
|
|
FAST_IO = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
PARALLEL_EXPANDERS = ON;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
|
|
BEGIN
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
REFACTORIZATION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
REDUCE_LOGIC = OFF;
|
|
DECOMPOSE_GATES = ON;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
CARRY_CHAIN = IGNORE;
|
|
CASCADE_CHAIN = IGNORE;
|
|
MINIMIZATION = FULL;
|
|
FAST_IO = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
TURBO_BIT = ON;
|
|
XOR_SYNTHESIS = OFF;
|
|
SLOW_SLEW_RATE = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
|
|
BEGIN
|
|
CARRY_CHAIN_LENGTH = 32;
|
|
CASCADE_CHAIN_LENGTH = 2;
|
|
REGISTER_OPTIMIZATION = ON;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
MULTI_LEVEL_FACTORING = ON;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
REFACTORIZATION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = ON;
|
|
REDUCE_LOGIC = ON;
|
|
DECOMPOSE_GATES = ON;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
CARRY_CHAIN = AUTO;
|
|
CASCADE_CHAIN = AUTO;
|
|
MINIMIZATION = FULL;
|
|
IGNORE_SOFT_BUFFERS = ON;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
TURBO_BIT = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
SLOW_SLEW_RATE = OFF;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
|
|
BEGIN
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
RESYNTHESIZE_NETWORK = OFF;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
REFACTORIZATION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
REDUCE_LOGIC = OFF;
|
|
DECOMPOSE_GATES = OFF;
|
|
SOFT_BUFFER_INSERTION = OFF;
|
|
FAST_IO = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
TURBO_BIT = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
SLOW_SLEW_RATE = OFF;
|
|
MINIMIZATION = PARTIAL;
|
|
CARRY_CHAIN = IGNORE;
|
|
CASCADE_CHAIN = IGNORE;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
|
|
BEGIN
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
RESYNTHESIZE_NETWORK = OFF;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
REFACTORIZATION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
REDUCE_LOGIC = OFF;
|
|
DECOMPOSE_GATES = OFF;
|
|
SOFT_BUFFER_INSERTION = OFF;
|
|
FAST_IO = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
TURBO_BIT = ON;
|
|
XOR_SYNTHESIS = OFF;
|
|
SLOW_SLEW_RATE = OFF;
|
|
MINIMIZATION = PARTIAL;
|
|
CARRY_CHAIN = IGNORE;
|
|
CASCADE_CHAIN = IGNORE;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
|
|
BEGIN
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
RESYNTHESIZE_NETWORK = ON;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
REFACTORIZATION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
REDUCE_LOGIC = OFF;
|
|
DECOMPOSE_GATES = ON;
|
|
SOFT_BUFFER_INSERTION = OFF;
|
|
FAST_IO = OFF;
|
|
IGNORE_SOFT_BUFFERS = OFF;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
TURBO_BIT = ON;
|
|
XOR_SYNTHESIS = OFF;
|
|
SLOW_SLEW_RATE = OFF;
|
|
MINIMIZATION = PARTIAL;
|
|
CARRY_CHAIN = IGNORE;
|
|
CASCADE_CHAIN = IGNORE;
|
|
END;
|
|
|
|
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
|
|
BEGIN
|
|
REGISTER_OPTIMIZATION = OFF;
|
|
USE_LPM_FOR_AHDL_OPERATORS = OFF;
|
|
RESYNTHESIZE_NETWORK = OFF;
|
|
MULTI_LEVEL_FACTORING = OFF;
|
|
SUBFACTOR_EXTRACTION = OFF;
|
|
REFACTORIZATION = OFF;
|
|
NOT_GATE_PUSH_BACK = ON;
|
|
DUPLICATE_LOGIC_EXTRACTION = OFF;
|
|
REDUCE_LOGIC = OFF;
|
|
DECOMPOSE_GATES = OFF;
|
|
SOFT_BUFFER_INSERTION = ON;
|
|
IGNORE_SOFT_BUFFERS = ON;
|
|
PARALLEL_EXPANDERS = OFF;
|
|
TURBO_BIT = OFF;
|
|
XOR_SYNTHESIS = OFF;
|
|
SLOW_SLEW_RATE = OFF;
|
|
MINIMIZATION = PARTIAL;
|
|
CARRY_CHAIN_LENGTH = 32;
|
|
CARRY_CHAIN = MANUAL;
|
|
CASCADE_CHAIN_LENGTH = 2;
|
|
CASCADE_CHAIN = MANUAL;
|
|
END;
|
|
|