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RTL VHDL (xHDL)
This commit is contained in:
dj Apendix
GitHub
parent
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207
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.pin
Normal file
207
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.pin
Normal file
@ -0,0 +1,207 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
--
|
||||
-- This is a Quartus II output file. It is for reporting purposes only, and is
|
||||
-- not intended for use as a Quartus II input file. This file cannot be used
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||||
-- to make Quartus II pin assignments - for instructions on how to make pin
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||||
-- assignments, please see Quartus II help.
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||||
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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-- NC : No Connect. This pin has no internal connection to the device.
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-- DNU : Do Not Use. This pin MUST NOT be connected.
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-- VCCINT : Dedicated power pin, which MUST be connected to VCC (3.3V).
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-- VCCIO : Dedicated power pin, which MUST be connected to VCC
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-- of its bank.
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-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
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-- It can also be used to report unused dedicated pins. The connection
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-- on the board for unused dedicated pins depends on whether this will
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||||
-- be used in a future design. One example is device migration. When
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||||
-- using device migration, refer to the device pin-tables. If it is a
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||||
-- GND pin in the pin table or if it will not be used in a future design
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-- for another purpose the it MUST be connected to GND. If it is an unused
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-- dedicated pin, then it can be connected to a valid signal on the board
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-- (low, high, or toggling) if that signal is required for a different
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-- revision of the design.
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-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
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-- This pin should be connected to GND. It may also be connected to a
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-- valid signal on the board (low, high, or toggling) if that signal
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-- is required for a different revision of the design.
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-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
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-- or leave it unconnected.
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-- RESERVED : Unused I/O pin, which MUST be left unconnected.
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-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
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-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
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-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
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-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
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-- NON_MIGRATABLE: This pin cannot be migrated.
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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-- Pin directions (input, output or bidir) are based on device operating in user mode.
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---------------------------------------------------------------------------------
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Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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CHIP "divmmc" ASSIGNED TO AN: EPM3256ATC144-10
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Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
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-------------------------------------------------------------------------------------------------------------
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A[15] : 1 : input : 3.3-V LVTTL : : : Y
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A[14] : 2 : input : 3.3-V LVTTL : : : Y
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GND : 3 : gnd : : : :
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TDI : 4 : input : 3.3-V LVTTL : : : N
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A[13] : 5 : input : 3.3-V LVTTL : : : Y
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A[12] : 6 : input : 3.3-V LVTTL : : : Y
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RESERVED_INPUT : 7 : : : : :
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RESERVED_INPUT : 8 : : : : :
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RESERVED_INPUT : 9 : : : : :
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RESERVED_INPUT : 10 : : : : :
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RESERVED_INPUT : 11 : : : : :
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iorq : 12 : input : 3.3-V LVTTL : : : Y
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GND : 13 : gnd : : : :
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rd : 14 : input : 3.3-V LVTTL : : : Y
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wr : 15 : input : 3.3-V LVTTL : : : Y
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reset : 16 : input : 3.3-V LVTTL : : : Y
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GND : 17 : gnd : : : :
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romcs : 18 : output : 3.3-V LVTTL : : : Y
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RESERVED_INPUT : 19 : : : : :
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TMS : 20 : input : 3.3-V LVTTL : : : N
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RESERVED_INPUT : 21 : : : : :
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m1 : 22 : input : 3.3-V LVTTL : : : Y
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RESERVED_INPUT : 23 : : : : :
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VCCIO : 24 : power : : 3.3V : :
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RESERVED_INPUT : 25 : : : : :
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GND : 26 : gnd : : : :
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RESERVED_INPUT : 27 : : : : :
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RESERVED_INPUT : 28 : : : : :
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RESERVED_INPUT : 29 : : : : :
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romoe : 30 : output : 3.3-V LVTTL : : : Y
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D[4] : 31 : bidir : 3.3-V LVTTL : : : Y
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D[3] : 32 : bidir : 3.3-V LVTTL : : : Y
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GND : 33 : gnd : : : :
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RESERVED_INPUT : 34 : : : : :
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RESERVED_INPUT : 35 : : : : :
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mreq : 36 : input : 3.3-V LVTTL : : : Y
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RESERVED_INPUT : 37 : : : : :
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RESERVED_INPUT : 38 : : : : :
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RESERVED_INPUT : 39 : : : : :
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RESERVED_INPUT : 40 : : : : :
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RESERVED_INPUT : 41 : : : : :
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RESERVED_INPUT : 42 : : : : :
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D[2] : 43 : bidir : 3.3-V LVTTL : : : Y
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D[5] : 44 : bidir : 3.3-V LVTTL : : : Y
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D[1] : 45 : bidir : 3.3-V LVTTL : : : Y
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D[6] : 46 : bidir : 3.3-V LVTTL : : : Y
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D[0] : 47 : bidir : 3.3-V LVTTL : : : Y
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D[7] : 48 : bidir : 3.3-V LVTTL : : : Y
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ramoe : 49 : output : 3.3-V LVTTL : : : Y
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VCCIO : 50 : power : : 3.3V : :
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VCCINT : 51 : power : : 3.3V : :
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GND : 52 : gnd : : : :
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A[0] : 53 : input : 3.3-V LVTTL : : : Y
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A[1] : 54 : input : 3.3-V LVTTL : : : Y
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A[10] : 55 : input : 3.3-V LVTTL : : : Y
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A[2] : 56 : input : 3.3-V LVTTL : : : Y
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GND : 57 : gnd : : : :
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VCCINT : 58 : power : : 3.3V : :
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GND : 59 : gnd : : : :
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RESERVED_INPUT : 60 : : : : :
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A[3] : 61 : input : 3.3-V LVTTL : : : Y
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A[11] : 62 : input : 3.3-V LVTTL : : : Y
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A[4] : 63 : input : 3.3-V LVTTL : : : Y
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GND : 64 : gnd : : : :
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A[9] : 65 : input : 3.3-V LVTTL : : : Y
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A[5] : 66 : input : 3.3-V LVTTL : : : Y
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A[8] : 67 : input : 3.3-V LVTTL : : : Y
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A[6] : 68 : input : 3.3-V LVTTL : : : Y
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RESERVED_INPUT : 69 : : : : :
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RESERVED_INPUT : 70 : : : : :
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RESERVED_INPUT : 71 : : : : :
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RESERVED_INPUT : 72 : : : : :
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VCCIO : 73 : power : : 3.3V : :
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RESERVED_INPUT : 74 : : : : :
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A[7] : 75 : input : 3.3-V LVTTL : : : Y
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VCCIO : 76 : power : : 3.3V : :
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GND : 77 : gnd : : : :
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RESERVED_INPUT : 78 : : : : :
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RESERVED_INPUT : 79 : : : : :
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romwr : 80 : output : 3.3-V LVTTL : : : Y
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bankout[1] : 81 : output : 3.3-V LVTTL : : : Y
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bankout[3] : 82 : output : 3.3-V LVTTL : : : Y
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bankout[5] : 83 : output : 3.3-V LVTTL : : : Y
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ramwr : 84 : output : 3.3-V LVTTL : : : Y
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GND : 85 : gnd : : : :
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RESERVED_INPUT : 86 : : : : :
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bankout[0] : 87 : output : 3.3-V LVTTL : : : Y
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bankout[4] : 88 : output : 3.3-V LVTTL : : : Y
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TCK : 89 : input : 3.3-V LVTTL : : : N
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bankout[2] : 90 : output : 3.3-V LVTTL : : : Y
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RESERVED_INPUT : 91 : : : : :
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RESERVED_INPUT : 92 : : : : :
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RESERVED_INPUT : 93 : : : : :
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GND : 94 : gnd : : : :
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VCCIO : 95 : power : : 3.3V : :
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card[1] : 96 : output : 3.3-V LVTTL : : : Y
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card[0] : 97 : output : 3.3-V LVTTL : : : Y
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spi_clock : 98 : output : 3.3-V LVTTL : : : Y
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spi_dataout : 99 : output : 3.3-V LVTTL : : : Y
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spi_datain : 100 : input : 3.3-V LVTTL : : : Y
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RESERVED_INPUT : 101 : : : : :
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RESERVED_INPUT : 102 : : : : :
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RESERVED_INPUT : 103 : : : : :
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TDO : 104 : output : 3.3-V LVTTL : : : N
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GND : 105 : gnd : : : :
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RESERVED_INPUT : 106 : : : : :
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RESERVED_INPUT : 107 : : : : :
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RESERVED_INPUT : 108 : : : : :
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RESERVED_INPUT : 109 : : : : :
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RESERVED_INPUT : 110 : : : : :
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RESERVED_INPUT : 111 : : : : :
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RESERVED_INPUT : 112 : : : : :
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RESERVED_INPUT : 113 : : : : :
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GND : 114 : gnd : : : :
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VCCIO : 115 : power : : 3.3V : :
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RESERVED_INPUT : 116 : : : : :
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RESERVED_INPUT : 117 : : : : :
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RESERVED_INPUT : 118 : : : : :
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RESERVED_INPUT : 119 : : : : :
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RESERVED_INPUT : 120 : : : : :
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RESERVED_INPUT : 121 : : : : :
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RESERVED_INPUT : 122 : : : : :
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VCCINT : 123 : power : : 3.3V : :
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GND : 124 : gnd : : : :
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clock : 125 : input : 3.3-V LVTTL : : : Y
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GND+ : 126 : : : : :
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GND+ : 127 : : : : :
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GND+ : 128 : : : : :
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GND : 129 : gnd : : : :
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VCCINT : 130 : power : : 3.3V : :
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RESERVED_INPUT : 131 : : : : :
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RESERVED_INPUT : 132 : : : : :
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RESERVED_INPUT : 133 : : : : :
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RESERVED_INPUT : 134 : : : : :
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GND : 135 : gnd : : : :
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mapcondout : 136 : output : 3.3-V LVTTL : : : Y
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poweron : 137 : input : 3.3-V LVTTL : : : Y
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eprom : 138 : input : 3.3-V LVTTL : : : Y
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RESERVED_INPUT : 139 : : : : :
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RESERVED_INPUT : 140 : : : : :
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RESERVED_INPUT : 141 : : : : :
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RESERVED_INPUT : 142 : : : : :
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RESERVED_INPUT : 143 : : : : :
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VCCIO : 144 : power : : 3.3V : :
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BIN
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.pof
Normal file
BIN
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.pof
Normal file
Binary file not shown.
30
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.qpf
Normal file
30
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.qpf
Normal file
@ -0,0 +1,30 @@
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# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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||||
# Date created = 22:21:41 July 29, 2025
|
||||
#
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||||
# -------------------------------------------------------------------------- #
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||||
|
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QUARTUS_VERSION = "13.0"
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DATE = "22:21:41 July 29, 2025"
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||||
# Revisions
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PROJECT_REVISION = "divmmc"
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103
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.qsf
Normal file
103
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.qsf
Normal file
@ -0,0 +1,103 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 22:21:41 July 29, 2025
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
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||||
# Notes:
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||||
#
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||||
# 1) The default values for assignments are stored in the file:
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||||
# divmmc_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
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||||
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||||
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set_global_assignment -name FAMILY MAX3000A
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set_global_assignment -name DEVICE "EPM3256ATC144-10"
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||||
set_global_assignment -name TOP_LEVEL_ENTITY divmmc
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||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:21:41 JULY 29, 2025"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name VHDL_FILE divmmc.vhd
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_location_assignment PIN_53 -to A[0]
|
||||
set_location_assignment PIN_54 -to A[1]
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||||
set_location_assignment PIN_48 -to D[7]
|
||||
set_location_assignment PIN_47 -to D[0]
|
||||
set_location_assignment PIN_46 -to D[6]
|
||||
set_location_assignment PIN_45 -to D[1]
|
||||
set_location_assignment PIN_1 -to A[15]
|
||||
set_location_assignment PIN_2 -to A[14]
|
||||
set_location_assignment PIN_5 -to A[13]
|
||||
set_location_assignment PIN_6 -to A[12]
|
||||
set_location_assignment PIN_44 -to D[5]
|
||||
set_location_assignment PIN_43 -to D[2]
|
||||
set_location_assignment PIN_22 -to m1
|
||||
set_location_assignment PIN_49 -to ramoe
|
||||
set_location_assignment PIN_32 -to D[3]
|
||||
set_location_assignment PIN_31 -to D[4]
|
||||
set_location_assignment PIN_30 -to romoe
|
||||
set_location_assignment PIN_18 -to romcs
|
||||
set_location_assignment PIN_16 -to reset
|
||||
set_location_assignment PIN_15 -to wr
|
||||
set_location_assignment PIN_14 -to rd
|
||||
set_location_assignment PIN_12 -to iorq
|
||||
set_location_assignment PIN_90 -to bankout[2]
|
||||
set_location_assignment PIN_96 -to card[1]
|
||||
set_location_assignment PIN_97 -to card[0]
|
||||
set_location_assignment PIN_55 -to A[10]
|
||||
set_location_assignment PIN_56 -to A[2]
|
||||
set_location_assignment PIN_61 -to A[3]
|
||||
set_location_assignment PIN_62 -to A[11]
|
||||
set_location_assignment PIN_63 -to A[4]
|
||||
set_location_assignment PIN_65 -to A[9]
|
||||
set_location_assignment PIN_98 -to spi_clock
|
||||
set_location_assignment PIN_99 -to spi_dataout
|
||||
set_location_assignment PIN_100 -to spi_datain
|
||||
set_location_assignment PIN_81 -to bankout[1]
|
||||
set_location_assignment PIN_68 -to A[6]
|
||||
set_location_assignment PIN_80 -to romwr
|
||||
set_location_assignment PIN_66 -to A[5]
|
||||
set_location_assignment PIN_67 -to A[8]
|
||||
set_location_assignment PIN_82 -to bankout[3]
|
||||
set_location_assignment PIN_83 -to bankout[5]
|
||||
set_location_assignment PIN_84 -to ramwr
|
||||
set_location_assignment PIN_87 -to bankout[0]
|
||||
set_location_assignment PIN_88 -to bankout[4]
|
||||
set_location_assignment PIN_138 -to eprom
|
||||
set_location_assignment PIN_137 -to poweron
|
||||
set_location_assignment PIN_136 -to mapcondout
|
||||
set_location_assignment PIN_75 -to A[7]
|
||||
set_location_assignment PIN_125 -to clock
|
||||
set_location_assignment PIN_36 -to mreq
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
|
||||
256
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.vhd
Normal file
256
CPLD/NemoBUS/EPM3256_144/Ver1_0_0/RTL/divmmc.vhd
Normal file
@ -0,0 +1,256 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Inital version 1.0 for xc9572xl-vq64
|
||||
-- Engineer: Mario Prato
|
||||
-- Create Date: 10:07:18 11/22/2012
|
||||
--
|
||||
-- Modified for Altera EPM3256ATC144-10N
|
||||
-- Redesign Date: 02:54:18 11/22/2020
|
||||
--
|
||||
-- Module Name: divmmc - Behavioral
|
||||
-- Project Name: divmmc CPLD
|
||||
-- Target Devices: EPM3256ATC144-10N
|
||||
-- Tool versions: Quartus II 13.0SP1
|
||||
-- Description: zx spectrum mmc sd interface
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
-- ============================================================================================================
|
||||
entity divmmc is
|
||||
Port (
|
||||
|
||||
-- z80 cpu signals
|
||||
A : in std_logic_vector (15 downto 0);
|
||||
D : inout std_logic_vector (7 downto 0);
|
||||
iorq : in std_logic;
|
||||
mreq : in std_logic;
|
||||
wr : in std_logic;
|
||||
rd : in std_logic;
|
||||
m1 : in std_logic;
|
||||
reset : in std_logic;
|
||||
clock : in std_logic; -- Z80 Clock from ula chip (must be negated from edge connector signal)
|
||||
|
||||
-- ram/rom signals
|
||||
romcs : out STD_LOGIC; -- 1 -> page out spectrum rom
|
||||
romoe : out STD_LOGIC; -- eeprom oe pin
|
||||
romwr : out STD_LOGIC; -- eeprom wr pin
|
||||
ramoe : out STD_LOGIC; -- ram oe pin
|
||||
ramwr : out STD_LOGIC; -- ram wr pin
|
||||
bankout : out STD_LOGIC_VECTOR (5 downto 0); --ram bank no.
|
||||
|
||||
-- spi interface
|
||||
card : out std_logic_vector(1 downto 0) :="11"; -- Cards CS
|
||||
spi_clock : out std_logic :='1'; -- card clock
|
||||
spi_dataout : out std_logic :='1'; -- card data in
|
||||
spi_datain : in std_logic :='1'; -- card data out
|
||||
|
||||
-- various
|
||||
poweron : in STD_LOGIC; -- low pulse on poweron
|
||||
eprom : in STD_LOGIC; -- eprom jumper
|
||||
mapcondout : out std_logic -- hi when divmmc mem paged in
|
||||
);
|
||||
end divmmc;
|
||||
-- ============================================================================================================
|
||||
|
||||
architecture Behavioral of divmmc is
|
||||
|
||||
signal address : std_logic_vector(7 downto 0);
|
||||
signal zxmmcio : std_logic;
|
||||
signal divideio : std_logic;
|
||||
|
||||
signal bank : std_logic_vector (5 downto 0) := "000000";
|
||||
|
||||
signal mapterm : std_logic := '0';
|
||||
signal mapcond : std_logic := '0';
|
||||
signal conmem : std_logic := '0';
|
||||
signal mapram : std_logic := '0';
|
||||
signal automap : std_logic := '0';
|
||||
|
||||
signal map3DXX : std_logic;
|
||||
signal map1F00 : std_logic;
|
||||
|
||||
signal bank3 : std_logic;
|
||||
|
||||
|
||||
-- Transmission states
|
||||
type transStates is (
|
||||
IDLE, -- Wait for a WR or RD request on port 0xEB
|
||||
SAMPLE, -- As there is an I/O request, prepare the transmission; sample the CPU databus if required
|
||||
TRANSMIT); -- Transmission (SEND or RECEIVE)
|
||||
signal transState : transStates := IDLE; -- Transmission state (initially IDLE)
|
||||
|
||||
signal TState : unsigned(3 downto 0) := (others => '0'); -- Counts the T-States during transmission
|
||||
|
||||
signal fromSDByte : std_logic_vector(7 downto 0) := (others => '1'); -- Byte received from SD
|
||||
signal toSDByte : std_logic_vector(7 downto 0) := (others => '1'); -- Byte to send to SD
|
||||
signal toCPUByte : std_logic_vector(7 downto 0) := (others => '1'); -- Byte seen by the CPU after a byte read
|
||||
|
||||
-- dichiarazioni constanti
|
||||
|
||||
constant divide_control_port : std_logic_vector(7 downto 0) := x"E3"; -- port %11100011
|
||||
constant zxmmc_control_port : std_logic_vector(7 downto 0) := x"E7"; -- era la porta 31 nella zxmmc+
|
||||
constant zxmmc_spi_port : std_logic_vector(7 downto 0) := x"EB"; -- era la porta 63 nella zxmmc+
|
||||
|
||||
|
||||
attribute PWR_MODE: string;
|
||||
attribute FAST: string;
|
||||
attribute BUFG: string;
|
||||
-- ============================================================================================================
|
||||
begin
|
||||
|
||||
address <= A(7 downto 0);
|
||||
|
||||
bank3 <= '1' when bank ="000011" else '0';
|
||||
|
||||
-- ROM RAM read write signals
|
||||
|
||||
|
||||
romoe <= rd or A(15) or A(14) or A(13) or (not conmem and mapram) or (not conmem and not automap) or (not conmem and eprom);
|
||||
|
||||
romwr <= '0' when wr ='0' and a(13)='0' and a(14)='0' and a(15)='0' and eprom='1' and conmem='1' else '1';
|
||||
|
||||
ramoe <= rd or A(15) or A(14) or ( not A(13) and not mapram) or ( not A(13) and conmem) or (not conmem and not automap) or (not conmem and eprom and not mapram);
|
||||
|
||||
ramwr <= wr or A(15) or A(14) or not a(13) or (not conmem and mapram and bank3 ) or (not conmem and not automap) or (not conmem and eprom and not mapram);
|
||||
|
||||
romcs <= '1' when ((automap and not eprom) or (automap and mapram) or conmem )='1' else '0' ; -- RDR
|
||||
|
||||
-- ============================================================================================================
|
||||
-- Divide Automapping logic
|
||||
|
||||
mapterm <= '1' when A(15 downto 0) = x"0000" or
|
||||
A(15 downto 0) = x"0008" or
|
||||
A(15 downto 0) = x"0038" or
|
||||
A(15 downto 0) = x"0066" or
|
||||
A(15 downto 0) = x"04c6" or
|
||||
A(15 downto 0) = x"0562" else '0';
|
||||
|
||||
map3DXX <= '1' when A(15 downto 8) = "00111101" else '0'; -- mappa 3D00 - 3DFF
|
||||
|
||||
map1F00 <= '0' when A(15 downto 3) = "0001111111111" else '1'; -- 1ff8 - 1fff
|
||||
-- ============================================================================================================
|
||||
process(mreq)
|
||||
begin
|
||||
|
||||
if falling_edge(mreq) then
|
||||
if m1='0' then
|
||||
mapcond <= mapterm or map3DXX or (mapcond and map1F00);
|
||||
automap <= mapcond or map3DXX;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mapcondout <= mapcond;
|
||||
-- ============================================================================================================
|
||||
-- divide control port
|
||||
|
||||
divideio <='0' when iorq='0' and wr='0' and M1='1' and address = divide_control_port else '1';
|
||||
|
||||
process(divideio,poweron)
|
||||
begin
|
||||
-- if poweron ='0' then -- originally by M.Prato
|
||||
if poweron ='0' or reset = '0' then -- patched by valerium
|
||||
|
||||
bank <= "000000";
|
||||
mapram <= '0';
|
||||
conmem <= '0';
|
||||
|
||||
elsif rising_edge(divideio) then
|
||||
|
||||
bank(5 downto 0) <= D(5 downto 0);
|
||||
mapram <= D(6) or mapram;
|
||||
conmem <= D(7);
|
||||
end if;
|
||||
|
||||
end process;
|
||||
-- ============================================================================================================
|
||||
-- ram banks
|
||||
|
||||
bankout(0) <= bank(0) or not A(13);
|
||||
bankout(1) <= bank(1) or not A(13);
|
||||
bankout(2) <= bank(2) and A(13);
|
||||
bankout(3) <= bank(3) and A(13);
|
||||
bankout(4) <= bank(4) and A(13);
|
||||
bankout(5) <= bank(5) and A(13);
|
||||
-- ============================================================================================================
|
||||
-- SD CS signal management
|
||||
zxmmcio <= '0' when address = zxmmc_control_port and iorq='0' and m1='1' and wr ='0' else '1';
|
||||
|
||||
|
||||
process(reset, zxmmcio)
|
||||
begin
|
||||
if reset = '0' then
|
||||
card(0) <= '1';
|
||||
card(1) <= '1';
|
||||
|
||||
elsif rising_edge(zxmmcio) then
|
||||
|
||||
card(0) <= D(0);
|
||||
card(1) <= D(1);
|
||||
|
||||
end if;
|
||||
end process;
|
||||
-- ============================================================================================================
|
||||
-- spi transmission/reception
|
||||
|
||||
-- Update transmission state
|
||||
process(clock, reset)
|
||||
begin
|
||||
if reset = '0' then
|
||||
transState <= IDLE;
|
||||
TState <= (others => '0');
|
||||
fromSDByte <= (others => '1');
|
||||
toSDByte <= (others => '1');
|
||||
toCPUByte <= (others => '1');
|
||||
|
||||
elsif falling_edge(clock) then
|
||||
case transState is
|
||||
|
||||
when IDLE => -- Intercept a new transmission request (port 0x3F)
|
||||
if address = zxmmc_spi_port and iorq='0' and m1='1' then -- If there is a transmission request, prepare to SAMPLE the databus
|
||||
transState <= SAMPLE;
|
||||
end if;
|
||||
|
||||
when SAMPLE =>
|
||||
if wr = '0' then -- If it is a SEND request, sample the CPU data bus
|
||||
toSDByte <= D;
|
||||
end if;
|
||||
transState <= TRANSMIT; -- then start the transmission
|
||||
|
||||
when TRANSMIT =>
|
||||
TState <= TState + 1;
|
||||
|
||||
if TState < 15 then
|
||||
|
||||
if TState(0) = '1' then
|
||||
toSDByte <= toSDByte(6 downto 0)&'1';
|
||||
fromSDByte <= fromSDByte(6 downto 0)& spi_datain;
|
||||
end if;
|
||||
else
|
||||
if TState = 15 then -- transmission is completed; intercept if there is a new transmission request
|
||||
if address = zxmmc_spi_port and iorq='0' and m1='1'and wr='0' then
|
||||
toSDByte <= D;
|
||||
transState <= TRANSMIT;
|
||||
else -- else we'll go in IDLE state.
|
||||
transState <= IDLE;
|
||||
-- TState <= "0000";
|
||||
end if;
|
||||
toCPUByte <= fromSDByte(6 downto 0)& spi_datain;
|
||||
end if;
|
||||
end if;
|
||||
when OTHERS =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
-- SPI SD Card pins
|
||||
SPI_clock <= TState(0);
|
||||
spi_dataout <= toSDByte(7);
|
||||
end process;
|
||||
|
||||
|
||||
D <= toCPUByte when (address = zxmmc_spi_port) and (iorq = '0') and (rd = '0') and m1='1' else "ZZZZZZZZ";
|
||||
|
||||
-- ============================================================================================================
|
||||
end Behavioral;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user