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----------------------------------------------------------------------------------
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-- Inital version 1.0 for xc9572xl-vq64
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-- Engineer: Mario Prato
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-- Create Date: 10:07:18 11/22/2012
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--
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-- Modified for Altera EPM3256ATC144-10N
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-- Redesign Date: 02:54:18 11/22/2020
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--
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-- Module Name: divmmc - Behavioral
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-- Project Name: divmmc CPLD
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-- Target Devices: EPM3256ATC144-10N
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-- Tool versions: Quartus II 13.0SP1
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-- Description: zx spectrum mmc sd interface
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- ============================================================================================================
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entity divmmc is
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Port (
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-- z80 cpu signals
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A : in std_logic_vector (15 downto 0);
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D : inout std_logic_vector (7 downto 0);
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iorq : in std_logic;
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mreq : in std_logic;
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wr : in std_logic;
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rd : in std_logic;
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m1 : in std_logic;
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reset : in std_logic;
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clock : in std_logic; -- Z80 Clock from ula chip (must be negated from edge connector signal)
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-- ram/rom signals
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romcs : out STD_LOGIC; -- 1 -> page out spectrum rom
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romoe : out STD_LOGIC; -- eeprom oe pin
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romwr : out STD_LOGIC; -- eeprom wr pin
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ramoe : out STD_LOGIC; -- ram oe pin
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ramwr : out STD_LOGIC; -- ram wr pin
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bankout : out STD_LOGIC_VECTOR (5 downto 0); --ram bank no.
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-- spi interface
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card : out std_logic_vector(1 downto 0) :="11"; -- Cards CS
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spi_clock : out std_logic :='1'; -- card clock
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spi_dataout : out std_logic :='1'; -- card data in
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spi_datain : in std_logic :='1'; -- card data out
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-- various
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poweron : in STD_LOGIC; -- low pulse on poweron
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eprom : in STD_LOGIC; -- eprom jumper
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mapcondout : out std_logic -- hi when divmmc mem paged in
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);
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end divmmc;
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-- ============================================================================================================
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architecture Behavioral of divmmc is
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signal address : std_logic_vector(7 downto 0);
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signal zxmmcio : std_logic;
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signal divideio : std_logic;
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signal bank : std_logic_vector (5 downto 0) := "000000";
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signal mapterm : std_logic := '0';
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signal mapcond : std_logic := '0';
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signal conmem : std_logic := '0';
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signal mapram : std_logic := '0';
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signal automap : std_logic := '0';
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signal map3DXX : std_logic;
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signal map1F00 : std_logic;
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signal bank3 : std_logic;
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-- Transmission states
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type transStates is (
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IDLE, -- Wait for a WR or RD request on port 0xEB
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SAMPLE, -- As there is an I/O request, prepare the transmission; sample the CPU databus if required
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TRANSMIT); -- Transmission (SEND or RECEIVE)
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signal transState : transStates := IDLE; -- Transmission state (initially IDLE)
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signal TState : unsigned(3 downto 0) := (others => '0'); -- Counts the T-States during transmission
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signal fromSDByte : std_logic_vector(7 downto 0) := (others => '1'); -- Byte received from SD
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signal toSDByte : std_logic_vector(7 downto 0) := (others => '1'); -- Byte to send to SD
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signal toCPUByte : std_logic_vector(7 downto 0) := (others => '1'); -- Byte seen by the CPU after a byte read
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-- dichiarazioni constanti
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constant divide_control_port : std_logic_vector(7 downto 0) := x"E3"; -- port %11100011
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constant zxmmc_control_port : std_logic_vector(7 downto 0) := x"E7"; -- era la porta 31 nella zxmmc+
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constant zxmmc_spi_port : std_logic_vector(7 downto 0) := x"EB"; -- era la porta 63 nella zxmmc+
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attribute PWR_MODE: string;
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attribute FAST: string;
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attribute BUFG: string;
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-- ============================================================================================================
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begin
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address <= A(7 downto 0);
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bank3 <= '1' when bank ="000011" else '0';
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-- ROM RAM read write signals
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romoe <= rd or A(15) or A(14) or A(13) or (not conmem and mapram) or (not conmem and not automap) or (not conmem and eprom);
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romwr <= '0' when wr ='0' and a(13)='0' and a(14)='0' and a(15)='0' and eprom='1' and conmem='1' else '1';
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ramoe <= rd or A(15) or A(14) or ( not A(13) and not mapram) or ( not A(13) and conmem) or (not conmem and not automap) or (not conmem and eprom and not mapram);
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ramwr <= wr or A(15) or A(14) or not a(13) or (not conmem and mapram and bank3 ) or (not conmem and not automap) or (not conmem and eprom and not mapram);
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romcs <= '1' when ((automap and not eprom) or (automap and mapram) or conmem )='1' else '0' ; -- RDR
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-- ============================================================================================================
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-- Divide Automapping logic
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mapterm <= '1' when A(15 downto 0) = x"0000" or
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A(15 downto 0) = x"0008" or
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A(15 downto 0) = x"0038" or
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A(15 downto 0) = x"0066" or
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A(15 downto 0) = x"04c6" or
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A(15 downto 0) = x"0562" else '0';
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map3DXX <= '1' when A(15 downto 8) = "00111101" else '0'; -- mappa 3D00 - 3DFF
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map1F00 <= '0' when A(15 downto 3) = "0001111111111" else '1'; -- 1ff8 - 1fff
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-- ============================================================================================================
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process(mreq)
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begin
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if falling_edge(mreq) then
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if m1='0' then
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mapcond <= mapterm or map3DXX or (mapcond and map1F00);
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automap <= mapcond or map3DXX;
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end if;
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end if;
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end process;
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mapcondout <= mapcond;
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-- ============================================================================================================
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-- divide control port
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divideio <='0' when iorq='0' and wr='0' and M1='1' and address = divide_control_port else '1';
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process(divideio,poweron)
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begin
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-- if poweron ='0' then -- originally by M.Prato
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if poweron ='0' or reset = '0' then -- patched by valerium
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bank <= "000000";
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mapram <= '0';
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conmem <= '0';
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elsif rising_edge(divideio) then
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bank(5 downto 0) <= D(5 downto 0);
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mapram <= D(6) or mapram;
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conmem <= D(7);
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end if;
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end process;
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-- ============================================================================================================
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-- ram banks
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bankout(0) <= bank(0) or not A(13);
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bankout(1) <= bank(1) or not A(13);
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bankout(2) <= bank(2) and A(13);
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bankout(3) <= bank(3) and A(13);
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bankout(4) <= bank(4) and A(13);
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bankout(5) <= bank(5) and A(13);
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-- ============================================================================================================
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-- SD CS signal management
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zxmmcio <= '0' when address = zxmmc_control_port and iorq='0' and m1='1' and wr ='0' else '1';
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process(reset, zxmmcio)
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begin
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if reset = '0' then
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card(0) <= '1';
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card(1) <= '1';
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elsif rising_edge(zxmmcio) then
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card(0) <= D(0);
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card(1) <= D(1);
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end if;
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end process;
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-- ============================================================================================================
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-- spi transmission/reception
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-- Update transmission state
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process(clock, reset)
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begin
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if reset = '0' then
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transState <= IDLE;
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TState <= (others => '0');
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fromSDByte <= (others => '1');
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toSDByte <= (others => '1');
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toCPUByte <= (others => '1');
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elsif falling_edge(clock) then
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case transState is
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when IDLE => -- Intercept a new transmission request (port 0x3F)
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if address = zxmmc_spi_port and iorq='0' and m1='1' then -- If there is a transmission request, prepare to SAMPLE the databus
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transState <= SAMPLE;
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end if;
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when SAMPLE =>
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if wr = '0' then -- If it is a SEND request, sample the CPU data bus
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toSDByte <= D;
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end if;
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transState <= TRANSMIT; -- then start the transmission
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when TRANSMIT =>
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TState <= TState + 1;
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if TState < 15 then
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if TState(0) = '1' then
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toSDByte <= toSDByte(6 downto 0)&'1';
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fromSDByte <= fromSDByte(6 downto 0)& spi_datain;
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end if;
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else
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if TState = 15 then -- transmission is completed; intercept if there is a new transmission request
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if address = zxmmc_spi_port and iorq='0' and m1='1'and wr='0' then
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toSDByte <= D;
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transState <= TRANSMIT;
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else -- else we'll go in IDLE state.
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transState <= IDLE;
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-- TState <= "0000";
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end if;
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toCPUByte <= fromSDByte(6 downto 0)& spi_datain;
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end if;
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end if;
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when OTHERS =>
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null;
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end case;
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end if;
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-- SPI SD Card pins
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SPI_clock <= TState(0);
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spi_dataout <= toSDByte(7);
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end process;
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D <= toCPUByte when (address = zxmmc_spi_port) and (iorq = '0') and (rd = '0') and m1='1' else "ZZZZZZZZ";
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-- ============================================================================================================
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end Behavioral;
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