diff --git a/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.pin b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.pin new file mode 100644 index 0000000..479f224 --- /dev/null +++ b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.pin @@ -0,0 +1,207 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (3.3V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + -- NON_MIGRATABLE: This pin cannot be migrated. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "divmmc" ASSIGNED TO AN: EPM3256ATC144-10 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +A[15] : 1 : input : 3.3-V LVTTL : : : Y +A[14] : 2 : input : 3.3-V LVTTL : : : Y +GND : 3 : gnd : : : : +TDI : 4 : input : 3.3-V LVTTL : : : N +A[13] : 5 : input : 3.3-V LVTTL : : : Y +A[12] : 6 : input : 3.3-V LVTTL : : : Y +RESERVED : 7 : : : : : +RESERVED : 8 : : : : : +RESERVED : 9 : : : : : +RESERVED : 10 : : : : : +RESERVED : 11 : : : : : +iorq : 12 : input : 3.3-V LVTTL : : : Y +GND : 13 : gnd : : : : +rd : 14 : input : 3.3-V LVTTL : : : Y +wr : 15 : input : 3.3-V LVTTL : : : Y +reset : 16 : input : 3.3-V LVTTL : : : Y +GND : 17 : gnd : : : : +romcs : 18 : output : 3.3-V LVTTL : : : Y +RESERVED : 19 : : : : : +TMS : 20 : input : 3.3-V LVTTL : : : N +RESERVED : 21 : : : : : +m1 : 22 : input : 3.3-V LVTTL : : : Y +RESERVED : 23 : : : : : +VCCIO : 24 : power : : 3.3V : : +RESERVED : 25 : : : : : +GND : 26 : gnd : : : : +RESERVED : 27 : : : : : +RESERVED : 28 : : : : : +RESERVED : 29 : : : : : +romoe : 30 : output : 3.3-V LVTTL : : : Y +D[4] : 31 : bidir : 3.3-V LVTTL : : : Y +D[3] : 32 : bidir : 3.3-V LVTTL : : : Y +GND : 33 : gnd : : : : +RESERVED : 34 : : : : : +RESERVED : 35 : : : : : +RESERVED : 36 : : : : : +RESERVED : 37 : : : : : +RESERVED : 38 : : : : : +RESERVED : 39 : : : : : +RESERVED : 40 : : : : : +RESERVED : 41 : : : : : +RESERVED : 42 : : : : : +D[2] : 43 : bidir : 3.3-V LVTTL : : : Y +D[5] : 44 : bidir : 3.3-V LVTTL : : : Y +D[1] : 45 : bidir : 3.3-V LVTTL : : : Y +D[6] : 46 : bidir : 3.3-V LVTTL : : : Y +D[0] : 47 : bidir : 3.3-V LVTTL : : : Y +D[7] : 48 : bidir : 3.3-V LVTTL : : : Y +ramoe : 49 : output : 3.3-V LVTTL : : : Y +VCCIO : 50 : power : : 3.3V : : +VCCINT : 51 : power : : 3.3V : : +GND : 52 : gnd : : : : +A[0] : 53 : input : 3.3-V LVTTL : : : Y +A[1] : 54 : input : 3.3-V LVTTL : : : Y +A[10] : 55 : input : 3.3-V LVTTL : : : Y +A[2] : 56 : input : 3.3-V LVTTL : : : Y +GND : 57 : gnd : : : : +VCCINT : 58 : power : : 3.3V : : +GND : 59 : gnd : : : : +RESERVED : 60 : : : : : +A[3] : 61 : input : 3.3-V LVTTL : : : Y +A[11] : 62 : input : 3.3-V LVTTL : : : Y +A[4] : 63 : input : 3.3-V LVTTL : : : Y +GND : 64 : gnd : : : : +A[9] : 65 : input : 3.3-V LVTTL : : : Y +A[5] : 66 : input : 3.3-V LVTTL : : : Y +A[8] : 67 : input : 3.3-V LVTTL : : : Y +A[6] : 68 : input : 3.3-V LVTTL : : : Y +RESERVED : 69 : : : : : +RESERVED : 70 : : : : : +RESERVED : 71 : : : : : +RESERVED : 72 : : : : : +VCCIO : 73 : power : : 3.3V : : +mreq : 74 : input : 3.3-V LVTTL : : : Y +A[7] : 75 : input : 3.3-V LVTTL : : : Y +VCCIO : 76 : power : : 3.3V : : +GND : 77 : gnd : : : : +RESERVED : 78 : : : : : +RESERVED : 79 : : : : : +romwr : 80 : output : 3.3-V LVTTL : : : Y +bankout[1] : 81 : output : 3.3-V LVTTL : : : Y +bankout[3] : 82 : output : 3.3-V LVTTL : : : Y +bankout[5] : 83 : output : 3.3-V LVTTL : : : Y +ramwr : 84 : output : 3.3-V LVTTL : : : Y +GND : 85 : gnd : : : : +RESERVED : 86 : : : : : +bankout[0] : 87 : output : 3.3-V LVTTL : : : Y +bankout[4] : 88 : output : 3.3-V LVTTL : : : Y +TCK : 89 : input : 3.3-V LVTTL : : : N +bankout[2] : 90 : output : 3.3-V LVTTL : : : Y +RESERVED : 91 : : : : : +RESERVED : 92 : : : : : +RESERVED : 93 : : : : : +GND : 94 : gnd : : : : +VCCIO : 95 : power : : 3.3V : : +card[1] : 96 : output : 3.3-V LVTTL : : : Y +card[0] : 97 : output : 3.3-V LVTTL : : : Y +spi_clock : 98 : output : 3.3-V LVTTL : : : Y +spi_dataout : 99 : output : 3.3-V LVTTL : : : Y +spi_datain : 100 : input : 3.3-V LVTTL : : : Y +RESERVED : 101 : : : : : +RESERVED : 102 : : : : : +RESERVED : 103 : : : : : +TDO : 104 : output : 3.3-V LVTTL : : : N +GND : 105 : gnd : : : : +RESERVED : 106 : : : : : +RESERVED : 107 : : : : : +RESERVED : 108 : : : : : +RESERVED : 109 : : : : : +RESERVED : 110 : : : : : +RESERVED : 111 : : : : : +RESERVED : 112 : : : : : +RESERVED : 113 : : : : : +GND : 114 : gnd : : : : +VCCIO : 115 : power : : 3.3V : : +RESERVED : 116 : : : : : +RESERVED : 117 : : : : : +RESERVED : 118 : : : : : +RESERVED : 119 : : : : : +RESERVED : 120 : : : : : +RESERVED : 121 : : : : : +RESERVED : 122 : : : : : +VCCINT : 123 : power : : 3.3V : : +GND : 124 : gnd : : : : +clock : 125 : input : 3.3-V LVTTL : : : Y +GND+ : 126 : : : : : +GND+ : 127 : : : : : +GND+ : 128 : : : : : +GND : 129 : gnd : : : : +VCCINT : 130 : power : : 3.3V : : +RESERVED : 131 : : : : : +RESERVED : 132 : : : : : +RESERVED : 133 : : : : : +RESERVED : 134 : : : : : +GND : 135 : gnd : : : : +mapcondout : 136 : output : 3.3-V LVTTL : : : Y +poweron : 137 : input : 3.3-V LVTTL : : : Y +eprom : 138 : input : 3.3-V LVTTL : : : Y +RESERVED : 139 : : : : : +RESERVED : 140 : : : : : +RESERVED : 141 : : : : : +RESERVED : 142 : : : : : +RESERVED : 143 : : : : : +VCCIO : 144 : power : : 3.3V : : diff --git a/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.pof b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.pof new file mode 100644 index 0000000..14dfc0b Binary files /dev/null and b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.pof differ diff --git a/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.qpf b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.qpf new file mode 100644 index 0000000..f11a054 --- /dev/null +++ b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 22:21:41 July 29, 2025 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "22:21:41 July 29, 2025" + +# Revisions + +PROJECT_REVISION = "divmmc" diff --git a/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.qsf b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.qsf new file mode 100644 index 0000000..f75ca72 --- /dev/null +++ b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.qsf @@ -0,0 +1,101 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 22:21:41 July 29, 2025 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# divmmc_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY MAX3000A +set_global_assignment -name DEVICE "EPM3256ATC144-10" +set_global_assignment -name TOP_LEVEL_ENTITY divmmc +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:21:41 JULY 29, 2025" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name VHDL_FILE divmmc.vhd +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_53 -to A[0] +set_location_assignment PIN_54 -to A[1] +set_location_assignment PIN_48 -to D[7] +set_location_assignment PIN_47 -to D[0] +set_location_assignment PIN_46 -to D[6] +set_location_assignment PIN_45 -to D[1] +set_location_assignment PIN_1 -to A[15] +set_location_assignment PIN_2 -to A[14] +set_location_assignment PIN_5 -to A[13] +set_location_assignment PIN_6 -to A[12] +set_location_assignment PIN_44 -to D[5] +set_location_assignment PIN_43 -to D[2] +set_location_assignment PIN_22 -to m1 +set_location_assignment PIN_49 -to ramoe +set_location_assignment PIN_32 -to D[3] +set_location_assignment PIN_31 -to D[4] +set_location_assignment PIN_30 -to romoe +set_location_assignment PIN_18 -to romcs +set_location_assignment PIN_16 -to reset +set_location_assignment PIN_15 -to wr +set_location_assignment PIN_14 -to rd +set_location_assignment PIN_12 -to iorq +set_location_assignment PIN_90 -to bankout[2] +set_location_assignment PIN_96 -to card[1] +set_location_assignment PIN_97 -to card[0] +set_location_assignment PIN_55 -to A[10] +set_location_assignment PIN_56 -to A[2] +set_location_assignment PIN_61 -to A[3] +set_location_assignment PIN_62 -to A[11] +set_location_assignment PIN_63 -to A[4] +set_location_assignment PIN_65 -to A[9] +set_location_assignment PIN_98 -to spi_clock +set_location_assignment PIN_99 -to spi_dataout +set_location_assignment PIN_100 -to spi_datain +set_location_assignment PIN_81 -to bankout[1] +set_location_assignment PIN_68 -to A[6] +set_location_assignment PIN_80 -to romwr +set_location_assignment PIN_66 -to A[5] +set_location_assignment PIN_67 -to A[8] +set_location_assignment PIN_82 -to bankout[3] +set_location_assignment PIN_83 -to bankout[5] +set_location_assignment PIN_84 -to ramwr +set_location_assignment PIN_87 -to bankout[0] +set_location_assignment PIN_88 -to bankout[4] +set_location_assignment PIN_138 -to eprom +set_location_assignment PIN_137 -to poweron +set_location_assignment PIN_136 -to mapcondout +set_location_assignment PIN_75 -to A[7] +set_location_assignment PIN_125 -to clock +set_location_assignment PIN_74 -to mreq \ No newline at end of file diff --git a/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.vhd b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.vhd new file mode 100644 index 0000000..8be21ba --- /dev/null +++ b/CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.vhd @@ -0,0 +1,259 @@ +---------------------------------------------------------------------------------- +-- Inital version 1.0 for xc9572xl-vq64 +-- Engineer: Mario Prato +-- Create Date: 10:07:18 11/22/2012 +-- +-- Modified for Altera EPM7128SLC84 +-- Redesign Date: 02:54:18 11/22/2020 +-- +-- Module Name: divmmc - Behavioral +-- Project Name: divmmc +-- Target Devices: EPM7128SLC84-15N +-- Tool versions: Quartus II 13.0SP1 +-- Description: zx spectrum mmc sd interface +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity divmmc is +Port ( + +-- z80 cpu signals + A : in std_logic_vector (15 downto 0); + D : inout std_logic_vector (7 downto 0); + iorq : in std_logic; + mreq : in std_logic; + wr : in std_logic; + rd : in std_logic; + m1 : in std_logic; + reset : in std_logic; + clock : in std_logic; -- Z80 Clock from ula chip (must be negated from edge connector signal) + +-- ram/rom signals + romcs : out STD_LOGIC; -- 1 -> page out spectrum rom + romoe : out STD_LOGIC; -- eeprom oe pin + romwr : out STD_LOGIC; -- eeprom wr pin + ramoe : out STD_LOGIC; -- ram oe pin + ramwr : out STD_LOGIC; -- ram wr pin + bankout : out STD_LOGIC_VECTOR (5 downto 0); --ram bank no. + +-- spi interface + card : out std_logic_vector(1 downto 0) :="11"; -- Cards CS + spi_clock : out std_logic :='1'; -- card clock + spi_dataout : out std_logic :='1'; -- card data in + spi_datain : in std_logic :='1'; -- card data out + +-- various + poweron : in STD_LOGIC; -- low pulse on poweron + eprom : in STD_LOGIC; -- eprom jumper + mapcondout : out std_logic -- hi when divmmc mem paged in +); +end divmmc; + + +architecture Behavioral of divmmc is + + signal address : std_logic_vector(7 downto 0) ; + signal zxmmcio : std_logic; + signal divideio : std_logic; + + signal bank : std_logic_vector (5 downto 0) := "000000"; + + signal mapterm : std_logic := '0'; + signal mapcond : std_logic := '0'; + signal conmem : std_logic := '0'; + signal mapram : std_logic := '0'; + signal automap : std_logic := '0'; + + signal map3DXX : std_logic; + signal map1F00 : std_logic; + + signal bank3 : std_logic; + + +-- Transmission states + type transStates is ( + IDLE, -- Wait for a WR or RD request on port 0xEB + SAMPLE, -- As there is an I/O request, prepare the transmission; sample the CPU databus if required + TRANSMIT); -- Transmission (SEND or RECEIVE) + signal transState : transStates := IDLE; -- Transmission state (initially IDLE) + + signal TState : unsigned(3 downto 0) := (others => '0'); -- Counts the T-States during transmission + + signal fromSDByte : std_logic_vector(7 downto 0) := (others => '1'); -- Byte received from SD + signal toSDByte : std_logic_vector(7 downto 0) := (others => '1'); -- Byte to send to SD + signal toCPUByte : std_logic_vector(7 downto 0) := (others => '1'); -- Byte seen by the CPU after a byte read + +-- dichiarazioni constanti + + constant divide_control_port : std_logic_vector(7 downto 0) := x"E3"; -- port %11100011 + constant zxmmc_control_port : std_logic_vector(7 downto 0) := x"E7"; -- era la porta 31 nella zxmmc+ + constant zxmmc_spi_port : std_logic_vector(7 downto 0) := x"EB"; -- era la porta 63 nella zxmmc+ + + +attribute PWR_MODE: string; +attribute FAST: string; +attribute BUFG: string; + +begin + + address <= A(7 downto 0); + + bank3 <= '1' when bank ="000011" else '0'; + +-- ROM RAM read write signals + + + romoe <= rd or A(15) or A(14) or A(13) or (not conmem and mapram) or (not conmem and not automap) or (not conmem and eprom); + + romwr <= '0' when wr ='0' and a(13)='0' and a(14)='0' and a(15)='0' and eprom='1' and conmem='1' else '1'; + + ramoe <= rd or A(15) or A(14) or ( not A(13) and not mapram) or ( not A(13) and conmem) or (not conmem and not automap) or (not conmem and eprom and not mapram); + + ramwr <= wr or A(15) or A(14) or not a(13) or (not conmem and mapram and bank3 ) or (not conmem and not automap) or (not conmem and eprom and not mapram); + + romcs <= '1' when ((automap and not eprom) or (automap and mapram) or conmem )='1' else '0' ; + + -- + -- Divide Automapping logic + + mapterm <= '1' when A(15 downto 0) = x"0000" or + A(15 downto 0) = x"0008" or + A(15 downto 0) = x"0038" or + A(15 downto 0) = x"0066" or + A(15 downto 0) = x"04c6" or + A(15 downto 0) = x"0562" else '0'; + + map3DXX <= '1' when A(15 downto 8) = "00111101" else '0'; -- mappa 3D00 - 3DFF + + map1F00 <= '0' when A(15 downto 3) = "0001111111111" else '1'; -- 1ff8 - 1fff + + +process(mreq) + begin + + if falling_edge(mreq) then + if m1='0' then + mapcond <= mapterm or map3DXX or (mapcond and map1F00); + automap <= mapcond or map3DXX; + end if; + end if; +end process; + + mapcondout <= mapcond; + +-- divide control port + + divideio <='0' when iorq='0' and wr='0' and M1='1' and address = divide_control_port else '1'; + +process(divideio,poweron) + begin +-- if poweron ='0' then -- originally by M.Prato + if poweron ='0' or reset = '0' then -- patched by valerium + + bank <= "000000"; + mapram <= '0'; + conmem <= '0'; + + elsif rising_edge(divideio) then + + bank(5 downto 0) <= D(5 downto 0); + mapram <= D(6) or mapram; + conmem <= D(7); + end if; + +end process; + +-- ram banks + + bankout(0) <= bank(0) or not A(13); + bankout(1) <= bank(1) or not A(13); + bankout(2) <= bank(2) and A(13); + bankout(3) <= bank(3) and A(13); + bankout(4) <= bank(4) and A(13); + bankout(5) <= bank(5) and A(13); + +-- SD CS signal management + zxmmcio <= '0' when address = zxmmc_control_port and iorq='0' and m1='1' and wr ='0' else '1'; + + +process(reset, zxmmcio) + begin + if reset = '0' then + card(0) <= '1'; + card(1) <= '1'; + + elsif rising_edge(zxmmcio) then + + card(0) <= D(0); + card(1) <= D(1); + + end if; +end process; + + + +-- spi transmission/reception + + -- Update transmission state +process(clock, reset) + begin + if reset = '0' then + transState <= IDLE; + TState <= (others => '0'); + fromSDByte <= (others => '1'); + toSDByte <= (others => '1'); + toCPUByte <= (others => '1'); + + elsif falling_edge(clock) then + case transState is + + when IDLE => -- Intercept a new transmission request (port 0x3F) + if address = zxmmc_spi_port and iorq='0' and m1='1' then -- If there is a transmission request, prepare to SAMPLE the databus + transState <= SAMPLE; + end if; + + when SAMPLE => + if wr = '0' then -- If it is a SEND request, sample the CPU data bus + toSDByte <= D; + end if; + transState <= TRANSMIT; -- then start the transmission + + when TRANSMIT => + TState <= TState + 1; + + if TState < 15 then + + if TState(0) = '1' then + toSDByte <= toSDByte(6 downto 0)&'1'; + fromSDByte <= fromSDByte(6 downto 0)& spi_datain; + end if; + else + if TState = 15 then -- transmission is completed; intercept if there is a new transmission request + if address = zxmmc_spi_port and iorq='0' and m1='1'and wr='0' then + toSDByte <= D; + transState <= TRANSMIT; + else -- else we'll go in IDLE state. + transState <= IDLE; + -- TState <= "0000"; + end if; + toCPUByte <= fromSDByte(6 downto 0)& spi_datain; + end if; + end if; + when OTHERS => + null; + end case; + end if; + -- SPI SD Card pins + SPI_clock <= TState(0); + spi_dataout <= toSDByte(7); +end process; + + + D <= toCPUByte when (address = zxmmc_spi_port) and (iorq = '0') and (rd = '0') and m1='1' else "ZZZZZZZZ"; + + +end Behavioral; +