dj-apendix/Div_MMC
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UPDATE (Original Firmware + cosmetic edit)

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(Original Firmware Mario Prato)
UPDATE (Original Firmware + cosmetic edit)
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dj Apendix 2025-07-31 03:07:24 +03:00 committed by GitHub
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commit f42a4695b7
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1 changed files with 51 additions and 54 deletions
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CPLD/NemoBUS/EPM3256_144/Ver1_0_0/divmmc.vhd
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@ -3,12 +3,12 @@
-- Engineer: Mario Prato -- Engineer: Mario Prato
-- Create Date: 10:07:18 11/22/2012 -- Create Date: 10:07:18 11/22/2012
-- --
-- Modified for Altera EPM7128SLC84 -- Modified for Altera EPM3256ATC144-10N
-- Redesign Date: 02:54:18 11/22/2020 -- Redesign Date: 02:54:18 11/22/2020
-- --
-- Module Name: divmmc - Behavioral -- Module Name: divmmc - Behavioral
-- Project Name: divmmc -- Project Name: divmmc CPLD
-- Target Devices: EPM7128SLC84-15N -- Target Devices: EPM3256ATC144-10N
-- Tool versions: Quartus II 13.0SP1 -- Tool versions: Quartus II 13.0SP1
-- Description: zx spectrum mmc sd interface -- Description: zx spectrum mmc sd interface
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
@ -16,7 +16,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ============================================================================================================
entity divmmc is entity divmmc is
Port ( Port (
@ -51,11 +51,11 @@ Port (
mapcondout : out std_logic -- hi when divmmc mem paged in mapcondout : out std_logic -- hi when divmmc mem paged in
); );
end divmmc; end divmmc;
-- ============================================================================================================
architecture Behavioral of divmmc is architecture Behavioral of divmmc is
signal address : std_logic_vector(7 downto 0) ; signal address : std_logic_vector(7 downto 0);
signal zxmmcio : std_logic; signal zxmmcio : std_logic;
signal divideio : std_logic; signal divideio : std_logic;
@ -96,7 +96,7 @@ architecture Behavioral of divmmc is
attribute PWR_MODE: string; attribute PWR_MODE: string;
attribute FAST: string; attribute FAST: string;
attribute BUFG: string; attribute BUFG: string;
-- ============================================================================================================
begin begin
address <= A(7 downto 0); address <= A(7 downto 0);
@ -116,8 +116,8 @@ begin
romcs <= '1' when ((automap and not eprom) or (automap and mapram) or conmem )='1' else '0' ; romcs <= '1' when ((automap and not eprom) or (automap and mapram) or conmem )='1' else '0' ;
-- -- ============================================================================================================
-- Divide Automapping logic -- Divide Automapping logic
mapterm <= '1' when A(15 downto 0) = x"0000" or mapterm <= '1' when A(15 downto 0) = x"0000" or
A(15 downto 0) = x"0008" or A(15 downto 0) = x"0008" or
@ -129,8 +129,7 @@ begin
map3DXX <= '1' when A(15 downto 8) = "00111101" else '0'; -- mappa 3D00 - 3DFF map3DXX <= '1' when A(15 downto 8) = "00111101" else '0'; -- mappa 3D00 - 3DFF
map1F00 <= '0' when A(15 downto 3) = "0001111111111" else '1'; -- 1ff8 - 1fff map1F00 <= '0' when A(15 downto 3) = "0001111111111" else '1'; -- 1ff8 - 1fff
-- ============================================================================================================
process(mreq) process(mreq)
begin begin
@ -143,7 +142,7 @@ process(mreq)
end process; end process;
mapcondout <= mapcond; mapcondout <= mapcond;
-- ============================================================================================================
-- divide control port -- divide control port
divideio <='0' when iorq='0' and wr='0' and M1='1' and address = divide_control_port else '1'; divideio <='0' when iorq='0' and wr='0' and M1='1' and address = divide_control_port else '1';
@ -165,7 +164,7 @@ process(divideio,poweron)
end if; end if;
end process; end process;
-- ============================================================================================================
-- ram banks -- ram banks
bankout(0) <= bank(0) or not A(13); bankout(0) <= bank(0) or not A(13);
@ -174,7 +173,7 @@ end process;
bankout(3) <= bank(3) and A(13); bankout(3) <= bank(3) and A(13);
bankout(4) <= bank(4) and A(13); bankout(4) <= bank(4) and A(13);
bankout(5) <= bank(5) and A(13); bankout(5) <= bank(5) and A(13);
-- ============================================================================================================
-- SD CS signal management -- SD CS signal management
zxmmcio <= '0' when address = zxmmc_control_port and iorq='0' and m1='1' and wr ='0' else '1'; zxmmcio <= '0' when address = zxmmc_control_port and iorq='0' and m1='1' and wr ='0' else '1';
@ -192,9 +191,7 @@ process(reset, zxmmcio)
end if; end if;
end process; end process;
-- ============================================================================================================
-- spi transmission/reception -- spi transmission/reception
-- Update transmission state -- Update transmission state
@ -254,6 +251,6 @@ end process;
D <= toCPUByte when (address = zxmmc_spi_port) and (iorq = '0') and (rd = '0') and m1='1' else "ZZZZZZZZ"; D <= toCPUByte when (address = zxmmc_spi_port) and (iorq = '0') and (rd = '0') and m1='1' else "ZZZZZZZZ";
-- ============================================================================================================
end Behavioral; end Behavioral;