commit 5979ca75a65c13b57095239c885bd68b4a79b4e5 Author: dj Apendix Date: Mon May 18 04:19:19 2026 +0300 Initial commit diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..dfe0770 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,2 @@ +# Auto detect text files and perform LF normalization +* text=auto diff --git a/Source/Project_ADHL/2mux1.tdf b/Source/Project_ADHL/2mux1.tdf new file mode 100644 index 0000000..861ab5a --- /dev/null +++ b/Source/Project_ADHL/2mux1.tdf @@ -0,0 +1,13 @@ +TITLE "Мультиплексор 2 в 1 "; + +SUBDESIGN 2MUX1 +( + A, B, SEL : INPUT; + Y : OUTPUT; +) +BEGIN + IF SEL ==0 THEN Y = A; + ELSE Y = B; + END IF; +END; + diff --git a/Source/Project_ADHL/4_8bitMUX1.tdf b/Source/Project_ADHL/4_8bitMUX1.tdf new file mode 100644 index 0000000..22e98f9 --- /dev/null +++ b/Source/Project_ADHL/4_8bitMUX1.tdf @@ -0,0 +1,19 @@ +TITLE "MULTIPLEXER 4 (8bit) in 1 "; + +SUBDESIGN 4_8bitMUX1 +( + A[7..0], B[7..0], C[7..0], D[7..0], SEL_A, SEL_B : INPUT; + Y[7..0] : OUTPUT; +) +BEGIN + IF SEL_B == 0 THEN + IF SEL_A == 0 THEN Y[] = A[]; + ELSE Y[] = B[]; + END IF; + ELSE + IF SEL_A == 0 THEN Y[] = C[]; + ELSE Y[] = D[]; + END IF; + END IF; +END; + diff --git a/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.pin b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.pin new file mode 100644 index 0000000..e7ce5b8 --- /dev/null +++ b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.pin @@ -0,0 +1,163 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCC : Dedicated power pin, which MUST be connected to VCC. + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + -- NON_MIGRATABLE: This pin cannot be migrated. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "Multi_Controller_IDE_FDD_SD_RTC_01" ASSIGNED TO AN: EPM7128STC100-7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +FDD_WRD : 1 : output : 3.3-V LVTTL : : : Y +VG93_RES : 2 : output : 3.3-V LVTTL : : : Y +VCCIO : 3 : power : : 3.3V : : +TDI : 4 : input : 3.3-V LVTTL : : : N +VG93_CLK : 5 : output : 3.3-V LVTTL : : : Y +VG93_RAWR : 6 : output : 3.3-V LVTTL : : : Y +VG93_SR : 7 : input : 3.3-V LVTTL : : : Y +VG93_S : 8 : output : 3.3-V LVTTL : : : Y +VG93_SL : 9 : input : 3.3-V LVTTL : : : Y +VG93_INRQ : 10 : input : 3.3-V LVTTL : : : Y +GND : 11 : gnd : : : : +VG93_DRQ : 12 : input : 3.3-V LVTTL : : : Y +VG93_TR43 : 13 : input : 3.3-V LVTTL : : : Y +VG93_WD : 14 : input : 3.3-V LVTTL : : : Y +TMS : 15 : input : 3.3-V LVTTL : : : N +VG93_WF/DE : 16 : input : 3.3-V LVTTL : : : Y +IDE_HDD[8] : 17 : bidir : 3.3-V LVTTL : : : Y +VCCIO : 18 : power : : 3.3V : : +IDE_HDD[9] : 19 : bidir : 3.3-V LVTTL : : : Y +IDE_HDD[10] : 20 : bidir : 3.3-V LVTTL : : : Y +IDE_HDD[11] : 21 : bidir : 3.3-V LVTTL : : : Y +IDE_HDD[12] : 22 : bidir : 3.3-V LVTTL : : : Y +IDE_HDD[13] : 23 : bidir : 3.3-V LVTTL : : : Y +IDE_HDD[14] : 24 : bidir : 3.3-V LVTTL : : : Y +IDE_HDD[15] : 25 : bidir : 3.3-V LVTTL : : : Y +GND : 26 : gnd : : : : +RTC_DS : 27 : output : 3.3-V LVTTL : : : Y +RTC_RW : 28 : output : 3.3-V LVTTL : : : Y +RTC_AS : 29 : output : 3.3-V LVTTL : : : Y +IDE_IOW : 30 : output : 3.3-V LVTTL : : : Y +VG93_IOFDC : 31 : output : 3.3-V LVTTL : : : Y +FDD_RDD : 32 : input : 3.3-V LVTTL : : : Y +pin33_NOT_USED : 33 : input : 3.3-V LVTTL : : : Y +VCCIO : 34 : power : : 3.3V : : +GLOBAL_CLK : 35 : input : 3.3-V LVTTL : : : Y +IDE_EBL : 36 : output : 3.3-V LVTTL : : : Y +IDE_IOR : 37 : output : 3.3-V LVTTL : : : Y +GND : 38 : gnd : : : : +VCCINT : 39 : power : : 5.0V : : +C_RS : 40 : input : 3.3-V LVTTL : : : Y +C_IORQGE : 41 : output : 3.3-V LVTTL : : : Y +BUS_A[14] : 42 : input : 3.3-V LVTTL : : : Y +GND : 43 : gnd : : : : +BUS_A[13] : 44 : input : 3.3-V LVTTL : : : Y +BUS_A[12] : 45 : input : 3.3-V LVTTL : : : Y +BUS_A[11] : 46 : input : 3.3-V LVTTL : : : Y +CD[7] : 47 : bidir : 3.3-V LVTTL : : : Y +C_DOS : 48 : bidir : 3.3-V LVTTL : : : Y +CD[0] : 49 : bidir : 3.3-V LVTTL : : : Y +CD[1] : 50 : bidir : 3.3-V LVTTL : : : Y +VCCIO : 51 : power : : 3.3V : : +CD[2] : 52 : bidir : 3.3-V LVTTL : : : Y +pin53_NOT_USED : 53 : input : 3.3-V LVTTL : : : Y +BUS_A[0] : 54 : input : 3.3-V LVTTL : : : Y +CD[6] : 55 : bidir : 3.3-V LVTTL : : : Y +BUS_A[1] : 56 : input : 3.3-V LVTTL : : : Y +CD[5] : 57 : bidir : 3.3-V LVTTL : : : Y +BUS_A[2] : 58 : input : 3.3-V LVTTL : : : Y +GND : 59 : gnd : : : : +CD[3] : 60 : bidir : 3.3-V LVTTL : : : Y +BUS_A[3] : 61 : input : 3.3-V LVTTL : : : Y +TCK : 62 : input : 3.3-V LVTTL : : : N +CD[4] : 63 : bidir : 3.3-V LVTTL : : : Y +BUS_A[7] : 64 : input : 3.3-V LVTTL : : : Y +pin65_NOT_USED : 65 : input : 3.3-V LVTTL : : : Y +VCCIO : 66 : power : : 3.3V : : +BUS_A[5] : 67 : input : 3.3-V LVTTL : : : Y +C_NMI : 68 : output : 3.3-V LVTTL : : : Y +C_MREQ : 69 : input : 3.3-V LVTTL : : : Y +C_IORQ : 70 : input : 3.3-V LVTTL : : : Y +C_RD : 71 : input : 3.3-V LVTTL : : : Y +C_WR : 72 : input : 3.3-V LVTTL : : : Y +TDO : 73 : output : 3.3-V LVTTL : : : N +GND : 74 : gnd : : : : +C_RESET : 75 : input : 3.3-V LVTTL : : : Y +BUS_A[6] : 76 : input : 3.3-V LVTTL : : : Y +C_M1 : 77 : input : 3.3-V LVTTL : : : Y +pin78_NOT_USED : 78 : input : 3.3-V LVTTL : : : Y +RTC_CS : 79 : output : 3.3-V LVTTL : : : Y +SW_SD : 80 : input : 3.3-V LVTTL : : : Y +SW_IDE : 81 : input : 3.3-V LVTTL : : : Y +VCCIO : 82 : power : : 3.3V : : +SW_DOS : 83 : input : 3.3-V LVTTL : : : Y +SW_Z_PAGE : 84 : input : 3.3-V LVTTL : : : Y +BT_MAGIC : 85 : input : 3.3-V LVTTL : : : Y +GND : 86 : gnd : : : : +BUS_A[4] : 87 : input : 3.3-V LVTTL : : : Y +BUS_A[8] : 88 : input : 3.3-V LVTTL : : : Y +BUS_A[9] : 89 : input : 3.3-V LVTTL : : : Y +BUS_A[10] : 90 : input : 3.3-V LVTTL : : : Y +VCCINT : 91 : power : : 5.0V : : +SD_MISO : 92 : input : 3.3-V LVTTL : : : Y +SD_SCK : 93 : output : 3.3-V LVTTL : : : Y +SD_MOSI : 94 : output : 3.3-V LVTTL : : : Y +GND : 95 : gnd : : : : +SD_CS[0] : 96 : output : 3.3-V LVTTL : : : Y +FDD_SEL_A : 97 : output : 3.3-V LVTTL : : : Y +FDD_SEL_B : 98 : output : 3.3-V LVTTL : : : Y +FDD_SIDE : 99 : output : 3.3-V LVTTL : : : Y +VG93_HRDY : 100 : output : 3.3-V LVTTL : : : Y diff --git a/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.pof b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.pof new file mode 100644 index 0000000..8ecd118 Binary files /dev/null and b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.pof differ diff --git a/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.qpf b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.qpf new file mode 100644 index 0000000..393084a --- /dev/null +++ b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 05:52:26 May 13, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "05:52:26 May 13, 2026" + +# Revisions + +PROJECT_REVISION = "Multi_Controller_IDE_FDD_SD_RTC_01" diff --git a/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.qsf b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.qsf new file mode 100644 index 0000000..f295f1f --- /dev/null +++ b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.qsf @@ -0,0 +1,137 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 00:30:12 January 12, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Multi_Controller_IDE_FDD_SD_RTC_01_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY MAX7000S +set_global_assignment -name DEVICE "EPM7128STC100-7" +set_global_assignment -name TOP_LEVEL_ENTITY Multi_Controller_IDE_FDD_SD_RTC_01 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:30:12 MAY 12, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name AHDL_FILE Multi_Controller_IDE_FDD_SD_RTC_01.tdf +set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_47 -to CD[7] +set_location_assignment PIN_49 -to CD[0] +set_location_assignment PIN_50 -to CD[1] +set_location_assignment PIN_52 -to CD[2] +set_location_assignment PIN_60 -to CD[3] +set_location_assignment PIN_63 -to CD[4] +set_location_assignment PIN_57 -to CD[5] +set_location_assignment PIN_55 -to CD[6] +set_location_assignment PIN_92 -to SD_MISO +set_location_assignment PIN_93 -to SD_SCK +set_location_assignment PIN_94 -to SD_MOSI +set_location_assignment PIN_96 -to SD_CS[0] +set_location_assignment PIN_35 -to GLOBAL_CLK +set_location_assignment PIN_41 -to C_IORQGE +set_location_assignment PIN_77 -to C_M1 +set_location_assignment PIN_69 -to C_MREQ +set_location_assignment PIN_71 -to C_RD +set_location_assignment PIN_75 -to C_RESET +set_location_assignment PIN_72 -to C_WR +set_location_assignment PIN_70 -to C_IORQ +set_location_assignment PIN_54 -to BUS_A[0] +set_location_assignment PIN_56 -to BUS_A[1] +set_location_assignment PIN_58 -to BUS_A[2] +set_location_assignment PIN_61 -to BUS_A[3] +set_location_assignment PIN_87 -to BUS_A[4] +set_location_assignment PIN_42 -to BUS_A[14] +set_location_assignment PIN_44 -to BUS_A[13] +set_location_assignment PIN_45 -to BUS_A[12] +set_location_assignment PIN_46 -to BUS_A[11] +set_location_assignment PIN_90 -to BUS_A[10] +set_location_assignment PIN_89 -to BUS_A[9] +set_location_assignment PIN_88 -to BUS_A[8] +set_location_assignment PIN_64 -to BUS_A[7] +set_location_assignment PIN_76 -to BUS_A[6] +set_location_assignment PIN_67 -to BUS_A[5] +set_location_assignment PIN_33 -to pin33_NOT_USED +set_location_assignment PIN_53 -to pin53_NOT_USED +set_location_assignment PIN_65 -to pin65_NOT_USED +set_location_assignment PIN_78 -to pin78_NOT_USED +set_location_assignment PIN_85 -to BT_MAGIC +set_location_assignment PIN_84 -to SW_Z_PAGE +set_location_assignment PIN_80 -to SW_SD +set_location_assignment PIN_81 -to SW_IDE +set_location_assignment PIN_83 -to SW_DOS +set_location_assignment PIN_13 -to VG93_TR43 +set_location_assignment PIN_12 -to VG93_DRQ +set_location_assignment PIN_10 -to VG93_INRQ +set_location_assignment PIN_9 -to VG93_SL +set_location_assignment PIN_8 -to VG93_S +set_location_assignment PIN_7 -to VG93_SR +set_location_assignment PIN_6 -to VG93_RAWR +set_location_assignment PIN_5 -to VG93_CLK +set_location_assignment PIN_2 -to VG93_RES +set_location_assignment PIN_97 -to FDD_SEL_A +set_location_assignment PIN_98 -to FDD_SEL_B +set_location_assignment PIN_14 -to VG93_WD +set_location_assignment PIN_99 -to FDD_SIDE +set_location_assignment PIN_16 -to VG93_WF/DE +set_location_assignment PIN_1 -to FDD_WRD +set_location_assignment PIN_32 -to FDD_RDD +set_location_assignment PIN_100 -to VG93_HRDY +set_location_assignment PIN_25 -to IDE_HDD[15] +set_location_assignment PIN_24 -to IDE_HDD[14] +set_location_assignment PIN_23 -to IDE_HDD[13] +set_location_assignment PIN_22 -to IDE_HDD[12] +set_location_assignment PIN_21 -to IDE_HDD[11] +set_location_assignment PIN_20 -to IDE_HDD[10] +set_location_assignment PIN_19 -to IDE_HDD[9] +set_location_assignment PIN_17 -to IDE_HDD[8] +set_location_assignment PIN_30 -to IDE_IOW +set_location_assignment PIN_37 -to IDE_IOR +set_location_assignment PIN_36 -to IDE_EBL +set_location_assignment PIN_29 -to RTC_AS +set_location_assignment PIN_27 -to RTC_DS +set_location_assignment PIN_28 -to RTC_RW +set_location_assignment PIN_48 -to C_DOS +set_location_assignment PIN_40 -to C_RS +set_location_assignment PIN_68 -to C_NMI +set_location_assignment PIN_79 -to RTC_CS +set_location_assignment PIN_31 -to VG93_IOFDC +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name BDF_FILE Multi_Controller_IDE_FDD_SD_RTC_01.bdf +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 \ No newline at end of file diff --git a/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.tdf b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.tdf new file mode 100644 index 0000000..022f02d --- /dev/null +++ b/Source/Project_ADHL/Multi_Controller_IDE_FDD_SD_RTC_01.tdf @@ -0,0 +1,707 @@ +---------------------------------------------------------------------------------------------------------------------------- +-- Описание: Прошивка микросхемы CPLD (модуль EPM7128STC100-7) +-- Устройство Multi_Controller_IDE_FDD_SD_RTC (PentaDIV) +-- Основано на проектах (Тарасов М.Н. (Mick)) +-- ADHL Ver. by dj_apendix (Jeckas Nameless) [13.05.2026] +-- Тип CPLD: EPM7128STC100-7 (возможно применение EPM3128*) +---------------------------------------------------------------------------------------------------------------------------- +TITLE "Multi_Controller_IDE_FDD_SD_RTC"; + +FUNCTION 2mux1 (a, b, sel) RETURNS (y); +FUNCTION 2x8mux (sel, a[7..0], b[7..0]) RETURNS (y[7..0]); + + +SUBDESIGN Multi_Controller_IDE_FDD_SD_RTC_01 + --===================================================================================== +( + -- Входная тактовая частоа CLK + GLOBAL_CLK : INPUT; -- 16 or 8 MHz + + -- Сигналы управления с CPU + BUS_A[14..0] : INPUT; +-- CA[15..0] : INPUT; + + CD[7..0] : BIDIR; + + -- Сигналы шины CPU + C_IORQ : INPUT; + C_MREQ : INPUT; + C_M1 : INPUT; + C_RD : INPUT; + C_WR : INPUT; + + -- Общие сигналы + C_RESET : INPUT; + C_IORQGE : OUTPUT; + C_NMI : OUTPUT; + + C_RS : INPUT; -- A14 ROM* CA[6] + C_DOS : BIDIR; -- A15 ROM + + -- Сигналы SD Card + SD_CS[0] : OUTPUT; -- Cards CS + SD_SCK : OUTPUT; -- card clock + SD_MOSI : OUTPUT; -- to card data in + SD_MISO : INPUT; -- to card data out + + -- TR-DOS контроллер + VG93_CLK : OUTPUT; + VG93_IOFDC : OUTPUT; + VG93_RES : OUTPUT; + + VG93_HRDY : OUTPUT; + VG93_S : OUTPUT; + VG93_RAWR : OUTPUT; + VG93_SL : INPUT; + VG93_SR : INPUT; + VG93_TR43 : INPUT; + VG93_WD : INPUT; + VG93_WF/DE : INPUT; + + VG93_DRQ : INPUT; + VG93_INRQ : INPUT; + + FDD_SIDE : OUTPUT; + + FDD_RDD : INPUT; + FDD_WRD : OUTPUT; + + FDD_SEL_A : OUTPUT; + FDD_SEL_B : OUTPUT; + + -- NemoIDE + IDE_HDD[15..8] : BIDIR; + IDE_IOW : OUTPUT; + IDE_IOR : OUTPUT; + IDE_EBL : OUTPUT; + + -- RTC + RTC_DS : OUTPUT; + RTC_RW : OUTPUT; + RTC_AS : OUTPUT; + + -- SWitchers + SW_Z_PAGE : INPUT; + SW_DOS : INPUT; + SW_IDE : INPUT; + SW_SD : INPUT; + RTC_CS : OUTPUT; + + + BT_MAGIC : INPUT; + + -- Reserved (EPM3128-100/EPM7128-100)* + pin78_NOT_USED : INPUT; + pin65_NOT_USED : INPUT; + pin53_NOT_USED : INPUT; + pin33_NOT_USED : INPUT; +) + --===================================================================================== +VARIABLE + + CLK_14MHZ : LCELL; -- частота 16 +-- CLK_14MHZ : NODE; -- частота 16 + + DATA_CPU[7..0] : TRI_STATE_NODE; + CA[15..0] : NODE; + + -- Переменные +-- Not Defined + + -- TR-DOS контроллер + Sel_code : NODE; -- выбор ПЗУ TRDOS + Sel_3dxx : NODE; -- выбор ПЗУ TRDOS + DOS_r : JKFF; -- выбор ПЗУ TRDOS + NMI_r : DFF; -- выбор ПЗУ TRDOS + DOS_En : LCELL; -- доступ к контроллеру дисковода + C_NMI : OPNDRN; + C_DOS : OPNDRN; -- A15 ROM + + VG93_CLK : NODE; + VG93_IOFDC : NODE; + VG93_RES : NODE; + VG93_RAWR : LCELL; + VG93_S : LCELL; + FDD_RDD_sig : LCELL; + FDD_SEL_A : NODE; + FDD_SEL_B : NODE; + + CLK4_BDI : LCELL; -- 4MHz + CLK8_BDI : LCELL; -- 8MHz + F_BDI_CLOCK : NODE; -- Тактовая частота BDI + F_BDI_count[3..0] : DFF; -- Тактовая частота BDI + + FF_BDI[4..0] : DFFE; -- Порт #FF Тр-Дос + + CSFDD_BDI : NODE; + WRFF_BDI : NODE; + RDFF_BDI : NODE; + RDFF_BDI_VG[1..0] :TRI; + + FDD_wdata[3..0] : DFF; -- 4-х разрядный регистр + FDD_indata[1..0] : DFF; -- 2-х разрядный регистр входной + FDD_cntpe[3..0] : DFF; -- 4-x разрядный счетчик + + -- Регистр порта EFF7h + Sel_EFF7 : NODE; + WR_EFF7 : LCELL; + RD_EFF7 : LCELL; + IODOS : NODE; + PORT_EFF7_r : DFF; -- RTC/IODOS + + -- Регистр порта 7FFDh + Sel_7FFD : NODE; + WR_7FFD : LCELL; + ROM128_r : DFF; -- 128 ПЗУ (4й - бит) + + -- RTC + RTC_DS_sig : NODE; + RTC_RW_sig : NODE; + RTC_AS_sig : NODE; + RTC_CS_sig : NODE; + + -- Сигналы управления памятью + Sel_A45 : NODE; -- доступ к ОЗУ + + -- NemoIDE + IDE_PORT_En : NODE; + IDE_EBL_addr : NODE; + + IDE_WRH_RG[7..0] : DFF; -- DD4 + IDE_IOW_RG[7..0] : TRI; -- DD4 + + IDE_RDH_RG[7..0] : DFF; -- DD5 + IDE_IOR_RG[7..0] : TRI; -- DD5 + +-- IDE_HDD[15..8] : LCELL; + IDE_EBL_sig : NODE; + + IDE_IOW_sig : NODE; + IDE_IOR_sig : NODE; + IDE_WRH_sig : NODE; + IDE_RDH_sig : NODE; + + IDE_IOW : LCELL; + IDE_IOR : LCELL; + IDE_WRH : NODE; + IDE_RDH : NODE; + + IDE_EBL : LCELL; + + -- SPI интерфейс карты + SD_ZC_57 : NODE; + SD_ZC_77 : NODE; + + SD_CTRL : NODE; + SD_SPI : NODE; + + SD_CLK_14 : LCELL; + WR_77 : LCELL; + WR_57 : LCELL; + RD_57 : LCELL; + CS_57 : LCELL; + SD_count[3..0] : DFFE; + SD_shift_in[7..0] : DFF; + SD_shift_out[7..0] : DFF; + SD_start_sync : DFF; + SD_count_en : LCELL; + SD_rule_r[0] : DFF; + REG_sddata[7..0] : TRI; -- буфер чтения SD карты + + -- Сигналы SD Card + SD_CS[0] : NODE; + SD_SCK : NODE; + SD_MOSI : NODE; + + -- Управляющие сигналы + IORQGE_sig : NODE; + IORQGE : TRI; + IO_ENABLE : NODE; -- доступ к портам + IO_RD : LCELL; -- чтение из портов + IO_WR : LCELL; -- запись в порты +-- ============================================================================================================ +BEGIN + +-- DEFAULTS +-- RTC_DS_sig =1; +-- RTC_RW_sig =1; +-- RTC_AS_sig =1; +-- RTC_CS_sig =1; +-- END DEFAULTS; + + CLK_14MHZ = GLOBAL_CLK; -- для делителя, если есть (Кварц на 16 МГц) + +-- ca 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 +--pin 42 44 45 46 90 89 88 64 76 87 67 87 61 58 56 54 +--bus 14 13 12 11 10 09 08 07 06 04 05 04 03 02 01 00 + + CA[15..0] = (BUS_A[14..6],C_RS,BUS_A[5..0]); -- RS=A[6] + + +-- CA[15..7] = BUS_A[14..6]; +-- CA[6] = BUS_A[4]; +-- CA[5] = BUS_A[5]; +-- CA[4] = BUS_A[4]; +-- CA[3..0] = BUS_A[3..0]; + + ------------------------------------------------------------------------------------ + -- Порты + ------------------------------------------------------------------------------------ + SD_ZC_57 = CA[7..0] == h"57"; -- SPI Z-Controller + SD_ZC_77 = CA[7..0] == h"77"; -- SEL Z-Controller + + -- FUNCTION 2mux1 (a, b, sel) RETURNS (y); -- sel-0=a sel-1=b + SD_CTRL = SD_ZC_77 & SW_SD; + SD_SPI = SD_ZC_57 & SW_SD; + + + CS_57 = !SD_SPI # IO_ENABLE; + WR_77 = !SD_CTRL # IO_WR; + ------------------------------------------------------------------------------------ + -- Сигнал управление портами + ------------------------------------------------------------------------------------ +-- IO_ENABLE = !C_M1 # C_IORQGE # C_IORQ; -- самый низкий приоритет для материнской платы + IO_ENABLE = !C_M1 # C_IORQ; -- средний/высокий/(либо без) приоритет для внешних устройств + ------------------------------------------------------------------------------------ + -- Сигнал чтения из портов + ------------------------------------------------------------------------------------ + IO_RD = IO_ENABLE # C_RD; + ------------------------------------------------------------------------------------ + -- Сигнал записи в порты + ------------------------------------------------------------------------------------ + IO_WR = IO_ENABLE # C_WR; + ------------------------------------------------------------------------------------ +-- ============================================================================================================ + IORQGE_sig = (!RDFF_BDI # IDE_PORT_En # SD_CTRL # SD_SPI) & C_M1; + + IORQGE.in = VCC; + IORQGE.oe = IORQGE_sig; + C_IORQGE = IORQGE.out; + -- IORQGE for exUSSR clone's on NemoBUS + -- (SL60, SL62 socked, like ISA slot in x386 machines) + -- Need Hi-Z or VCC pinOut state (VCC=Blocked all ports in ZX mainboard) +-- ============================================================================================================ +-- ============================================================================================================ + ------------------------------------------------------------------------------------ + -- RTC/GLUK часы + ------------------------------------------------------------------------------------ + -- порты часов GLUK + + --#define gluk_adr 0xDFF7 + --#define gluk_dat 0xBFF7 + --#define gluk_on 0xEFF7 + + ------------------------------------------------------------------------------------ + -- Селектор порта EFF7h + ----------------------------------------------------------------------------------- + Sel_EFF7 = !CA[15] # !(CA[11..0] == h"FF7") # IO_ENABLE; + ------------------------------------------------------------------------------------ + -- Порт EFF7h + ----------------------------------------------------------------------------------- + WR_EFF7 = Sel_EFF7 # IO_WR; + RD_EFF7 = Sel_EFF7 # IO_RD; + +-- -- Описание БИТ порта EFF7h +-- -- D0 - 16c +-- -- D1 - 512x192 bw +-- -- D2 - RAM page only 128K +-- -- D3 - BLK/ romram +-- -- D4 - turbo +-- -- D5 - harware multicolor +-- -- D6 - not used (384x304) +-- -- D7 - RTC/IODOS + + PORT_EFF7_r.d = CD[7]; + PORT_EFF7_r.clk = !WR_EFF7; + PORT_EFF7_r.clrn = C_RESET; + + RTC_CS_sig = PORT_EFF7_r.q; + +-- IF SW_Z_PAGE ==0 THEN +-- IODOS = RTC_CS_sig; +-- RTC_CS = VCC; +-- ELSE + RTC_CS = !RTC_CS_sig; +-- IODOS = VCC; +-- END IF; + ------------------------------------------------------------------------------------ + CASE (RTC_CS, Sel_EFF7, CA[14..12]) IS + WHEN B"00011" => RTC_DS_sig = GND; -- BFF7h rd + WHEN B"00011" => RTC_RW_sig = GND; -- BFF7h wr + WHEN B"00101" => RTC_AS_sig = GND; -- DFF7h wr + + WHEN OTHERS => (RTC_DS_sig, RTC_RW_sig, RTC_AS_sig) = VCC; --(RTC_AS_sig) = GND; + END CASE; + + -- RTC + RTC_DS = RTC_DS_sig # RD_EFF7; + RTC_RW = RTC_RW_sig # WR_EFF7; + RTC_AS = !(RTC_AS_sig # WR_EFF7); +-- ============================================================================================================ +-- ============================================================================================================ + ------------------------------------------------------------------------------------ + -- BDI/VG93 - селектор + ------------------------------------------------------------------------------------ + -- Управление памятью ROM + ------------------------------------------------------------------------------------ + -- Формирование управляющих сигналов ROM памяти + ------------------------------------------------------------------------------------ + + -- A14=0 A15=0 MONITOR + -- A14=1 A15=0 DOS + -- A14=0 A15=1 128 + -- A14=1 A15=1 48 + +-- ROM_A14 = ROM128_r.q;-- # !DOS_En; -- сигнал RA14 = ROM128/ & !PRN; +-- ROM_A15 = !DOS_r.q; -- сигнал RA15 = DOS/ & !PRN; + ------------------------------------------------------------------------------------ + -- Селектор порта 7FFDh + ----------------------------------------------------------------------------------- + Sel_7FFD = CA[15] # !(CA[7..0] == h"FD") # IO_WR; + ------------------------------------------------------------------------------------ + -- Порт 7FFDh + ----------------------------------------------------------------------------------- + WR_7FFD = Sel_7FFD; -- # (CA[15..8] == h"1F"); + +-- -- Описание БИТ порта 7FFDh для 128кБ +-- -- D0-D2 - RAM page from address #C000 +-- -- D3 - video RAM page: 0 - bank5, 1 - bank7 +-- -- D4 - ROM page A14: 0 - basic 128, 1 - basic48 +-- -- D5 - 48k RAM lock, 1 - locked, 0 - extended memory enabled +-- -- D6 - not used* +-- -- D7 - not used* + + ROM128_r.d = CD[4]; + ROM128_r.clk = WR_7FFD; + ROM128_r.clrn = C_RESET; + ------------------------------------------------------------------------------------ + -- Выбор памяти ОЗУ + ------------------------------------------------------------------------------------ + Sel_A45 = CA[15] # CA[14]; -- сигнал A45 = A15 # A14 # BLK + ------------------------------------------------------------------------------------ + -- TR-DOS контроллер + ------------------------------------------------------------------------------------ + -- Выбор окна ПЗУ + ------------------------------------------------------------------------------------ + Sel_code = C_M1 # C_MREQ; + + Sel_3dxx = !(CA[15..8] == h"3D") # !ROM128_r.q # Sel_code # !SW_DOS;-- # C_RDR; + ------------------------------------------------------------------------------------ + -- Сигнал выбора контроллера NMI/ + ------------------------------------------------------------------------------------ + NMI_r.d = BT_MAGIC # !Sel_A45; --VCC; + NMI_r.clk = Sel_code; + NMI_r.prn = Sel_3dxx; -- & C_RESET; + ------------------------------------------------------------------------------------ + -- Сигнал NMI/ + ------------------------------------------------------------------------------------ + C_NMI = NMI_r.q; + ------------------------------------------------------------------------------------ + -- Доступ к контроллеру дисковода + ------------------------------------------------------------------------------------ + IF SW_DOS !=0 THEN + DOS_En = !DOS_r.q; -- & IODOS; + ELSE + DOS_En = VCC; --!DOS_r.q; + END IF; +-- DOS_En = !DOS_r.q; + C_DOS = DOS_En; + ------------------------------------------------------------------------------------ + -- Сигнал выбора контроллера DOS/ + ------------------------------------------------------------------------------------ + + ---------------------------СИГНАЛ DOS НА ТМ7---------------------------------------- + DOS_r.clrn = C_RESET;-- & SW_DOS; + DOS_r.j = !(Sel_3dxx & NMI_r.q); + DOS_r.clk = !CLK_14MHZ; + DOS_r.k = !(Sel_code # !Sel_A45); + + ---------------------------СИГНАЛ DOS НА ТМ2---------------------------------------- + --DOS_r.prn = !(Sel_code # !Sel_A45) & C_RESET; + --DOS_r.clrn = (Sel_3dxx # Sel_code) & NMI_r.q; + --DOS_r.clk = vcc; + --DOS_r.d = vcc; + ------------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------------ + -- Задающий тактовый генератор BDI + ------------------------------------------------------------------------------------ + F_BDI_CLOCK = CLK_14MHZ; -- 16 MHz QUARTZ + + F_BDI_count[].clk = F_BDI_CLOCK; -- счетчик BDI + F_BDI_count[].d = F_BDI_count[].q+1; + +-- CLK1_BDI = F_BDI_count[3].q; -- 1MHz +-- CLK2_BDI = F_BDI_count[2].q; -- 2MHz + CLK4_BDI = F_BDI_count[1].q; -- 4MHz + CLK8_BDI = F_BDI_count[0].q; -- 8MHz + ------------------------------------------------------------------------------------ + -- BDI/VG93 - контроллер + ------------------------------------------------------------------------------------ + -- Порты xxxFh - FDD + ------------------------------------------------------------------------------------ + CSFDD_BDI = !(CA[1..0] == B"11") # IO_ENABLE # !DOS_r.q; + ------------------------------------------------------------------------------------ + -- Выбор КР1818ВГ93 + ------------------------------------------------------------------------------------ + VG93_IOFDC = CA[7] # CSFDD_BDI; -- CS VG93 + ------------------------------------------------------------------------------------ + -- Порт 0FFh - запись + ------------------------------------------------------------------------------------ + WRFF_BDI = !(CA[7]) # C_WR # CSFDD_BDI; + ------------------------------------------------------------------------------------ + -- Порт 0FFh - чтение + ------------------------------------------------------------------------------------ + RDFF_BDI = !(CA[7]) # C_RD # CSFDD_BDI;-- # !SW_DOS; + ------------------------------------------------------------------------------------ + -- Порт #FF BDI (WRFF_BDI) OUT + ------------------------------------------------------------------------------------ + FF_BDI[].clk = WRFF_BDI; +-- FF_BDI[4..2].clk = WRFF_BDI; +-- FF_BDI[0].clk = WRFF_BDI; + FF_BDI[].clrn = C_RESET; + +-- FF_BDI[4].d = CD[6]; +-- VG93_DDEN = FF_BDI[4].q; -- плотность (не используется) + + FF_BDI[3].d = CD[4]; + FDD_SIDE = !FF_BDI[3].q; -- сторона (инверсия выхода! по схеме*) + + FF_BDI[2].d = CD[3]; + VG93_HRDY = FF_BDI[2].q; -- VG93_HRDY : BIDIR* or OUTPUT*, OPNDRN; + + FF_BDI[1].d = CD[2]; + VG93_RES = FF_BDI[1].q; + +-- IF SW_DOS !=0 THEN +-- VG93_RES = FF_BDI[1].q; +-- VG93_RES = C_RESET; +-- ELSE +-- VG93_RES = VCC; +-- END IF; + + FF_BDI[0].d = CD[0]; +-- SELECT_FDD = FF_BDI[0].q; + + FF_BDI[4].d = CD[1]; + +-- IF FF_BDI[4].q ==0 THEN +-- FDD_SEL_A = FF_BDI[0].q; +-- FDD_SEL_B = !FF_BDI[0].q; +-- ELSE +-- FDD_SEL_A = GND; +-- FDD_SEL_B = GND; +-- END IF; + + CASE (FF_BDI[4].q, FF_BDI[0].q) IS + WHEN B"00" => FDD_SEL_A = VCC; -- SD0 + WHEN B"01" => FDD_SEL_B = VCC; -- SD1 + + WHEN OTHERS => (FDD_SEL_B, FDD_SEL_A) = GND; + END CASE; + ------------------------------------------------------------------------------------ + -- Чтение #FF Порта BDI (RDFF_BDI) + + RDFF_BDI_VG[0].in = VG93_DRQ; + RDFF_BDI_VG[1].in = VG93_INRQ; + + RDFF_BDI_VG[1..0].oe = !RDFF_BDI; + + DATA_CPU[6] = RDFF_BDI_VG[0].out; + DATA_CPU[7] = RDFF_BDI_VG[1].out; + ------------------------------------------------------------------------------------ + -- сдвигающий регистр ИР16 (Запись на дискету) + ------------------------------------------------------------------------------------ + FDD_wdata[].clk = !CLK4_BDI; -- FDD_count[0].q; -- 4MГц; + IF VG93_WD == 0 THEN + FDD_wdata[].d = (FDD_wdata[3-1..0].q,GND); + ELSE + FDD_wdata[0].d = VG93_SR & VG93_TR43; + FDD_wdata[1].d = !((VG93_SR & VG93_TR43) # (VG93_SL & VG93_TR43)); --!(VG93_TR43 & (VG93_SR # VG93_SL)); +-- FDD_wdata[1].d = !(VG93_SR # VG93_SL); + FDD_wdata[2].d = VG93_SL & VG93_TR43; + FDD_wdata[3].d = GND; + END IF; + ------------------------------------------------------------------------------------ + -- сигнал записи дисковода + ------------------------------------------------------------------------------------ + FDD_WRD = FDD_wdata[3].q; -- (инверсия выхода! по схеме*) + ------------------------------------------------------------------------------------ + -- входной триггер ТМ2 (чтение с дискеты данных) + ------------------------------------------------------------------------------------ + FDD_RDD_sig = !FDD_RDD; -- LCELL без этого не инвертирует QUARTUS + + -- FDD_indata[].clk = CLK8_BDI; -- 8MГц + FDD_indata[].clk = CLK4_BDI; -- 4MГц + FDD_indata[0].d = FDD_RDD_sig; + FDD_indata[1].d = FDD_indata[0].q; + +-- FDD_indata[0].clrn = !VG93_WF/DE; +-- FDD_indata[1].prn = !VG93_WF/DE; + ------------------------------------------------------------------------------------ + -- сигнал RAWR + ------------------------------------------------------------------------------------ + VG93_RAWR = (FDD_indata[0].q # !FDD_indata[1].q); + ------------------------------------------------------------------------------------ + -- входной cчетчик ИЕ10 + ------------------------------------------------------------------------------------ + FDD_cntpe[].clk = CLK4_BDI; -- 4MГц + + IF VG93_RAWR == 0 THEN + FDD_cntpe[2..0].d = B"100"; + FDD_cntpe[3].d = VG93_S; + ELSE + FDD_cntpe[].d = FDD_cntpe[].q+1; + END IF; + ------------------------------------------------------------------------------------ + -- частота ВГ93 + ------------------------------------------------------------------------------------ + VG93_CLK = FDD_cntpe[1].q; -- F_BDI_count[3].q; -- 1MHz 1818ВГ93 +-- VG93_CLK = F_BDI_count[3].q; -- 1MHz + ------------------------------------------------------------------------------------ + -- сигнал RCLK (VG93_S) + ------------------------------------------------------------------------------------ + VG93_S = FDD_cntpe[3].q; -- RCLK +-- ============================================================================================================ +-- ============================================================================================================ + ------------------------------------------------------------------------------------ + -- NemoIDE - контроллер + ------------------------------------------------------------------------------------ + IDE_EBL_addr = CA[7..0] == h"10" # + CA[7..0] == h"11" # + CA[7..0] == h"30" # + CA[7..0] == h"50" # + CA[7..0] == h"70" # + CA[7..0] == h"90" # + CA[7..0] == h"B0" # + CA[7..0] == h"D0" # + CA[7..0] == h"F0" # + CA[7..0] == h"C8"; + + +-- IDE_PORT_En = (CA[2..1] ==0) & SW_IDE & C_M1 & C_DOS; --C_DOS : BIDIR, OPNDRN; +-- IDE_PORT_En = (CA[2..1] ==0) & SW_IDE & C_M1 & DOS_En; --C_DOS : OUTPUT, OPNDRN; +-- IDE_PORT_En = IDE_EBL_addr & SW_IDE; + IDE_PORT_En = IDE_EBL_addr & SW_IDE & C_M1 & C_DOS; + IDE_EBL_sig = !IDE_PORT_En; + + + IDE_IOW_sig = !(IDE_EBL_sig ==0 & CA[0] ==0 & IO_WR ==0); + IDE_WRH_sig = !(IDE_EBL_sig ==0 & CA[0] ==1 & IO_WR ==0); + IDE_IOR_sig = !(IDE_EBL_sig ==0 & CA[0] ==0 & IO_RD ==0); + IDE_RDH_sig = !(IDE_EBL_sig ==0 & CA[0] ==1 & IO_RD ==0); + + +-- IDE_EBL = IDE_EBL_sig; + IDE_EBL = (IDE_IOR_sig & IDE_IOW_sig) # IDE_EBL_sig; + + + IDE_IOW = IDE_IOW_sig; + IDE_IOR = IDE_IOR_sig; + IDE_WRH = IDE_WRH_sig; + IDE_RDH = IDE_RDH_sig; + + + -- DD4 + IDE_WRH_RG[].clk = IDE_WRH; + IDE_WRH_RG[].d = CD[7..0]; + + IDE_IOW_RG[].oe = !IDE_IOW_sig; --!IDE_IOW; + IDE_IOW_RG[].in = IDE_WRH_RG[].q; + IDE_HDD[15..8] = IDE_IOW_RG[].out; + + -- DD5 + IDE_RDH_RG[].clk = IDE_IOR_sig; --IDE_IOR; + IDE_RDH_RG[].d = IDE_HDD[15..8]; + + IDE_IOR_RG[].oe = !IDE_RDH; + IDE_IOR_RG[].in = IDE_RDH_RG[].q; + DATA_CPU[] = IDE_IOR_RG[].out; +-- ============================================================================================================ +-- ============================================================================================================ + ------------------------------------------------------------------------------------ + -- Z - контроллер + ------------------------------------------------------------------------------------ + -- Интерфейс SD карты, работает на частоте 16МГц + ------------------------------------------------------------------------------------ + SD_CLK_14 = CLK_14MHZ; + ------------------------------------------------------------------------------------ + -- Порт xx57h = 01010111b + ------------------------------------------------------------------------------------ + SD_start_sync.d = !CS_57; + SD_start_sync.clk = SD_CLK_14; + ----------------------------------------------------------------------------------- + -- Счетчик + ------------------------------------------------------------------------------------ + SD_count_en = !(SD_count[3..0].q ==B"1000"); + + SD_count[].clk = !SD_CLK_14; + SD_count[].ena = SD_count_en; + SD_count[0].clrn = !SD_start_sync.q; + SD_count[3..1].prn = !SD_start_sync.q; + SD_count[].d = SD_count[].q + 1; + ------------------------------------------------------------------------------------ + -- Входной сдвигающий регистр + ------------------------------------------------------------------------------------ + SD_shift_in[].clk = SD_CLK_14; + + IF SD_count[3].q ==0 THEN + SD_shift_in[].d = (SD_shift_in[7-1..0].q,SD_MISO); + ELSE + SD_shift_in[].d = SD_shift_in[].q; + END IF; + ------------------------------------------------------------------------------------ + -- Выходной сдвигающий регистр = xx57h = 01010111b + ------------------------------------------------------------------------------------ + WR_57 = CS_57 # IO_WR; + + SD_shift_out[].clk = !SD_CLK_14; + + IF WR_57 ==0 THEN + SD_shift_out[].d = CD[]; + + ELSIF SD_count[3].q ==0 THEN + SD_shift_out[].d = (SD_shift_out[7-1..0].q,VCC); + ELSE + SD_shift_out[].d = SD_shift_out[].q; + END IF; + ----------------------------------------------------------------------------------- + -- Вывод данных в SD + ------------------------------------------------------------------------------------ + SD_MOSI = SD_shift_out[7].q; + ------------------------------------------------------------------------------------ + -- Выходная частота SD + ------------------------------------------------------------------------------------ + SD_SCK = SD_CLK_14 & !SD_count[3].q; + ------------------------------------------------------------------------------------ + -- Процесс записи в порт управления SD карты = xx77h = 01110111b + ------------------------------------------------------------------------------------ + SD_rule_r[0].d = CD[1]; + SD_rule_r[0].clk = WR_77; + SD_rule_r[0].prn = C_RESET; + +-- IF EPROM_EN==0 THEN +-- SD_CS[] = SD_rule_r[].q; +-- ELSE +---- SD_CS[1] = VCC; + SD_CS[0] = SD_rule_r[0].q; +-- END IF; + ------------------------------------------------------------------------------------ + -- Чтение из SD карты + ------------------------------------------------------------------------------------ + RD_57 = CS_57 # IO_RD; + + REG_sddata[].in = SD_shift_in[].q; + REG_sddata[].oe = !RD_57; + + DATA_CPU[] = REG_sddata[].out; +-- ============================================================================================================ +-- ============================================================================================================ + + ------------------------------------------------------------------------------------ + -- Взаимодействие с ШД процессора + ------------------------------------------------------------------------------------ + CD[] = DATA_CPU[]; +-- ============================================================================================================ +END; + diff --git a/Source/Project_ADHL/ReadMe.txt b/Source/Project_ADHL/ReadMe.txt new file mode 100644 index 0000000..34e2ebd --- /dev/null +++ b/Source/Project_ADHL/ReadMe.txt @@ -0,0 +1 @@ +This Files for Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition \ No newline at end of file diff --git a/Source/Shematic/MultiCard_IDE_FDD_SD_RTC.bmp b/Source/Shematic/MultiCard_IDE_FDD_SD_RTC.bmp new file mode 100644 index 0000000..e61d762 Binary files /dev/null and b/Source/Shematic/MultiCard_IDE_FDD_SD_RTC.bmp differ diff --git a/Source/pcb_TOP_BOTTOM/Bottom.bmp b/Source/pcb_TOP_BOTTOM/Bottom.bmp new file mode 100644 index 0000000..de2a573 Binary files /dev/null and b/Source/pcb_TOP_BOTTOM/Bottom.bmp differ diff --git a/Source/pcb_TOP_BOTTOM/Bottom_both.bmp b/Source/pcb_TOP_BOTTOM/Bottom_both.bmp new file mode 100644 index 0000000..5a40947 Binary files /dev/null and b/Source/pcb_TOP_BOTTOM/Bottom_both.bmp differ diff --git a/Source/pcb_TOP_BOTTOM/Bottom_solder.bmp b/Source/pcb_TOP_BOTTOM/Bottom_solder.bmp new file mode 100644 index 0000000..3ed70c8 Binary files /dev/null and b/Source/pcb_TOP_BOTTOM/Bottom_solder.bmp differ diff --git a/Source/pcb_TOP_BOTTOM/Top.bmp b/Source/pcb_TOP_BOTTOM/Top.bmp new file mode 100644 index 0000000..313fe1e Binary files /dev/null and b/Source/pcb_TOP_BOTTOM/Top.bmp differ diff --git a/Source/pcb_TOP_BOTTOM/Top_both.bmp b/Source/pcb_TOP_BOTTOM/Top_both.bmp new file mode 100644 index 0000000..b532758 Binary files /dev/null and b/Source/pcb_TOP_BOTTOM/Top_both.bmp differ diff --git a/Source/pcb_TOP_BOTTOM/Top_solder.bmp b/Source/pcb_TOP_BOTTOM/Top_solder.bmp new file mode 100644 index 0000000..32d0c79 Binary files /dev/null and b/Source/pcb_TOP_BOTTOM/Top_solder.bmp differ