diff --git a/cpld/rtl/top.v b/cpld/rtl/top.v
index 2bdc19a..54a1610 100644
--- a/cpld/rtl/top.v
+++ b/cpld/rtl/top.v
@@ -5,48 +5,47 @@ module zx_multisound(
 
     input [4:0] cfg,
 
-    input [15:0] a,
-    inout [7:0] d,
-    input n_rd,
-    input n_wr,
-    input n_iorq,
-    input n_mreq,
-    input n_m1,
-    output n_wait,
-    output n_iorqge,
-
-    input n_dos,
-    input n_iodos,
+    input [15:0] zxa,
+    inout [7:0] zxd,
+    input zxrd_n,
+    input zxwr_n,
+    input zxiorq_n,
+    input zxmreq_n,
+    input zxm1_n,
+    output zxwait_n,
+    output zxiorqge_n,
+    input zxdos_n,
+    input zxiodos_n,
 
     output aa0,
     inout [7:0] ad,
-    output n_rstout,
-    output n_ard,
-    output n_awr,
+    output rstout_n,
+    output ard_n,
+    output awr_n,
     output ym_m,
-    output n_ym1_cs,
-    output n_ym2_cs,
+    output ym1_cs_n,
+    output ym2_cs_n,
     output reg fm1_ena,
     output reg fm2_ena,
-    output n_saa_cs,
+    output saa_cs_n,
     output saa_clk,
     output midi_clk,
 
     input [15:0] ga,
     inout [7:0] gd,
-    output n_grst,
+    output grst_n,
     output gclk,
-    output reg n_gint,
-    input n_grd,
-    input n_gwr,
-    input n_gm1,
-    input n_gmreq,
-    input n_giorq,
-    output n_grom,
-    output n_gram1,
-    output n_gram2,
-    output n_gram3,
-    output n_gram4,
+    output reg gint_n,
+    input grd_n,
+    input gwr_n,
+    input gm1_n,
+    input gmreq_n,
+    input giorq_n,
+    output grom_n,
+    output gram1_n,
+    output gram2_n,
+    output gram3_n,
+    output gram4_n,
     output [18:15] gma,
 
     output dac0_out,
@@ -55,27 +54,27 @@ module zx_multisound(
     output dac3_out
 );
 
-assign n_rstout = rst_n;
+assign rstout_n = rst_n;
 
-// n_iorq are useless in zxevo :(
-// so we're detecting n_iorq cycle by n_rd/n_wr signal asserted without n_m1/n_mreq
+// iorq_n are useless in zxevo :(
+// so we're detecting iorq_n cycle by rd_n/wr_n signal asserted without m1_n/mreq_n
 reg ioreq, ioreq_prev;
 always @(negedge clk32) begin
     ioreq_prev <= ioreq;
-    // ioreq <= n_iorq == 1'b0 && n_m1 == 1'b1 && n_dos == 1'b1 && n_iodos == 1'b1;
-    ioreq <= n_m1 == 1'b1 && n_mreq == 1'b1 && (n_rd == 1'b0 || n_wr == 1'b0);
+    // ioreq <= zxiorq_n == 1'b0 && zxm1_n == 1'b1 && zxdos_n == 1'b1 && zxiodos_n == 1'b1;
+    ioreq <= zxm1_n == 1'b1 && zxmreq_n == 1'b1 && (zxrd_n == 1'b0 || zxwr_n == 1'b0);
 end
-wire ioreq_rd = ioreq && n_rd == 1'b0;
-wire ioreq_wr = ioreq && n_wr == 1'b0;
+wire ioreq_rd = ioreq && zxrd_n == 1'b0;
+wire ioreq_wr = ioreq && zxwr_n == 1'b0;
 
-// n_dos are useless in zxevo :(
+// dos_n are useless in zxevo :(
 // so we're just lock some ports access when instruction has been fetched from rom
 reg rom_m1_access;
 always @(negedge clk32 or negedge rst_n) begin
     if (!rst_n)
         rom_m1_access <= 0;
-    else if (n_m1 == 0)
-        rom_m1_access <= a[15:14] == 2'b00;
+    else if (zxm1_n == 0)
+        rom_m1_access <= zxa[15:14] == 2'b00;
 end
 
 
@@ -101,13 +100,13 @@ wire clk16  = clk8_cnt[0];
 
 
 /* TURBO SOUND FM */
-wire port_bffd      = a[15:14] == 2'b10  && a[3:0] == 4'b1101 && ym_ena;
-wire port_fffd      = a[15:14] == 2'b11  && a[3:0] == 4'b1101 && ym_ena;
-wire port_fffd_full = a[15:13] == 3'b111 && a[3:0] == 4'b1101 && ym_ena; // required for compatibility with #dffd port
+wire port_bffd      = zxa[15:14] == 2'b10  && zxa[3:0] == 4'b1101 && ym_ena;
+wire port_fffd      = zxa[15:14] == 2'b11  && zxa[3:0] == 4'b1101 && ym_ena;
+wire port_fffd_full = zxa[15:13] == 3'b111 && zxa[3:0] == 4'b1101 && ym_ena; // required for compatibility with #dffd port
 reg ym_chip_sel, ym_get_stat;
-wire ym_a0 = (~n_rd & a[14] & ~ym_get_stat) | (~n_wr & ~a[14]);
-assign n_ym1_cs = ~(~ym_chip_sel && (port_bffd || port_fffd));
-assign n_ym2_cs = ~( ym_chip_sel && (port_bffd || port_fffd));
+wire ym_a0 = (~zxrd_n & zxa[14] & ~ym_get_stat) | (~zxwr_n & ~zxa[14]);
+assign ym1_cs_n = ~(~ym_chip_sel && (port_bffd || port_fffd));
+assign ym2_cs_n = ~( ym_chip_sel && (port_bffd || port_fffd));
 
 always @(posedge clk32 or negedge rst_n) begin
     if (!rst_n) begin
@@ -116,11 +115,11 @@ always @(posedge clk32 or negedge rst_n) begin
         fm1_ena <= 0;
         fm2_ena <= 0;
     end
-    else if (port_fffd && ioreq_wr && d[7:4] == 4'b1111) begin
-        ym_chip_sel <= d[0];
-        ym_get_stat <= ~d[1];
-        fm1_ena <= d[2]? 1'b0 : 1'bz;
-        fm2_ena <= d[2]? 1'b0 : 1'bz;
+    else if (port_fffd && ioreq_wr && zxd[7:4] == 4'b1111) begin
+        ym_chip_sel <= zxd[0];
+        ym_get_stat <= ~zxd[1];
+        fm1_ena <= zxd[2]? 1'b0 : 1'bz;
+        fm2_ena <= zxd[2]? 1'b0 : 1'bz;
     end
 end
 
@@ -128,17 +127,17 @@ assign ym_m = clk3_5;
 
 
 /* SAA1099 */
-wire port_ff = a[7:0] == 8'hFF && saa_ena && !rom_m1_access;
-assign n_saa_cs = ~(port_ff && ioreq_wr);
-wire saa_a0 = a[8];
+wire port_ff = zxa[7:0] == 8'hFF && saa_ena && !rom_m1_access;
+assign saa_cs_n = ~(port_ff && ioreq_wr);
+wire saa_a0 = zxa[8];
 
-wire port_fffd_saa = a[15:14] == 2'b11 && a[3:0] == 4'b1101 && saa_ena;
+wire port_fffd_saa = zxa[15:14] == 2'b11 && zxa[3:0] == 4'b1101 && saa_ena;
 reg saa_clk_en;
 always @(posedge clk32 or negedge rst_n) begin
     if (!rst_n)
         saa_clk_en <= 0;
-    else if (port_fffd_saa && ioreq_wr && d[7:4] == 4'b1111)
-        saa_clk_en <= ~d[3];
+    else if (port_fffd_saa && ioreq_wr && zxd[7:4] == 4'b1111)
+        saa_clk_en <= ~zxd[3];
 end
 
 assign saa_clk = saa_clk_en? clk8 : 1'b0;
@@ -150,12 +149,12 @@ assign midi_clk = clk12;
 
 /* GENERAL SOUND */
 assign gclk = clk16;
-assign n_grst = n_rstout;
+assign grst_n = rstout_n;
 
 reg gioreq, gioreq_prev;
 always @(posedge clk32) begin
     gioreq_prev <= gioreq;
-    gioreq <= n_giorq == 1'b0 && n_gm1 == 1'b1;
+    gioreq <= giorq_n == 1'b0 && gm1_n == 1'b1;
 end
 
 reg [8:0] g_int_cnt;
@@ -163,7 +162,7 @@ wire g_int_reload = g_int_cnt[8:6] == 4'b101;
 always @(posedge clk12 or negedge rst_n) begin
     if (!rst_n) begin
         g_int_cnt <= 0;
-        n_gint <= 1'b1;
+        gint_n <= 1'b1;
     end
     else begin
         if (g_int_reload)
@@ -172,16 +171,16 @@ always @(posedge clk12 or negedge rst_n) begin
             g_int_cnt <= g_int_cnt + 1'b1;
 
         if (g_int_reload)
-            n_gint <= 1'b0;
+            gint_n <= 1'b0;
         else if (g_int_cnt[5])
-            n_gint <= 1'b1;
+            gint_n <= 1'b1;
     end
 end
 
 /* GS EXTERNAL REGISTERS */
 reg [7:0] gs_regdata, gs_regcmd;
-wire port_b3 = a[7:0] == 8'hB3 && gs_ena;
-wire port_bb = a[7:0] == 8'hBB && gs_ena;
+wire port_b3 = zxa[7:0] == 8'hB3 && gs_ena;
+wire port_bb = zxa[7:0] == 8'hBB && gs_ena;
 always @(posedge clk32 or negedge rst_n) begin
     if (!rst_n) begin
         gs_regdata <= 0;
@@ -189,9 +188,9 @@ always @(posedge clk32 or negedge rst_n) begin
     end
     else begin
         if (port_b3 && ioreq_wr)
-            gs_regdata <= d;
+            gs_regdata <= zxd;
         if (port_bb && ioreq_wr)
-            gs_regcmd <= d;
+            gs_regcmd <= zxd;
     end
 end
 
@@ -203,29 +202,29 @@ always @(posedge clk32 or negedge rst_n) begin
         gs_reg00 <= 0;
         gs_reg_out <= 0;
     end
-    else if (~n_giorq && ~n_gwr) begin
+    else if (~giorq_n && ~gwr_n) begin
         if (ga[3:0] == 4'h0) gs_reg00 <= gd;
         if (ga[3:0] == 4'h3) gs_reg_out <= gd;
     end
 end
 
 /* GS DAC REGISTERS */
-reg gs_vol0_cs; always @(posedge clk32) gs_vol0_cs = ~n_giorq && ga[3:0] == 4'h6;
-reg gs_vol1_cs; always @(posedge clk32) gs_vol1_cs = ~n_giorq && ga[3:0] == 4'h7;
-reg gs_vol2_cs; always @(posedge clk32) gs_vol2_cs = ~n_giorq && ga[3:0] == 4'h8;
-reg gs_vol3_cs; always @(posedge clk32) gs_vol3_cs = ~n_giorq && ga[3:0] == 4'h9;
-reg gs_dac0_cs; always @(posedge clk32) gs_dac0_cs = ~n_gmreq && ga[15:13] == 3'b011 && ga[9:8] == 2'd0;
-reg gs_dac1_cs; always @(posedge clk32) gs_dac1_cs = ~n_gmreq && ga[15:13] == 3'b011 && ga[9:8] == 2'd1;
-reg gs_dac2_cs; always @(posedge clk32) gs_dac2_cs = ~n_gmreq && ga[15:13] == 3'b011 && ga[9:8] == 2'd2;
-reg gs_dac3_cs; always @(posedge clk32) gs_dac3_cs = ~n_gmreq && ga[15:13] == 3'b011 && ga[9:8] == 2'd3;
-wire gs_vol0_wr = gs_vol0_cs && ~n_gwr;
-wire gs_vol1_wr = gs_vol1_cs && ~n_gwr;
-wire gs_vol2_wr = gs_vol2_cs && ~n_gwr;
-wire gs_vol3_wr = gs_vol3_cs && ~n_gwr;
-wire gs_dac0_wr = gs_dac0_cs && ~n_grd;
-wire gs_dac1_wr = gs_dac1_cs && ~n_grd;
-wire gs_dac2_wr = gs_dac2_cs && ~n_grd;
-wire gs_dac3_wr = gs_dac3_cs && ~n_grd;
+reg gs_vol0_cs; always @(posedge clk32) gs_vol0_cs = ~giorq_n && ga[3:0] == 4'h6;
+reg gs_vol1_cs; always @(posedge clk32) gs_vol1_cs = ~giorq_n && ga[3:0] == 4'h7;
+reg gs_vol2_cs; always @(posedge clk32) gs_vol2_cs = ~giorq_n && ga[3:0] == 4'h8;
+reg gs_vol3_cs; always @(posedge clk32) gs_vol3_cs = ~giorq_n && ga[3:0] == 4'h9;
+reg gs_dac0_cs; always @(posedge clk32) gs_dac0_cs = ~gmreq_n && ga[15:13] == 3'b011 && ga[9:8] == 2'd0;
+reg gs_dac1_cs; always @(posedge clk32) gs_dac1_cs = ~gmreq_n && ga[15:13] == 3'b011 && ga[9:8] == 2'd1;
+reg gs_dac2_cs; always @(posedge clk32) gs_dac2_cs = ~gmreq_n && ga[15:13] == 3'b011 && ga[9:8] == 2'd2;
+reg gs_dac3_cs; always @(posedge clk32) gs_dac3_cs = ~gmreq_n && ga[15:13] == 3'b011 && ga[9:8] == 2'd3;
+wire gs_vol0_wr = gs_vol0_cs && ~gwr_n;
+wire gs_vol1_wr = gs_vol1_cs && ~gwr_n;
+wire gs_vol2_wr = gs_vol2_cs && ~gwr_n;
+wire gs_vol3_wr = gs_vol3_cs && ~gwr_n;
+wire gs_dac0_wr = gs_dac0_cs && ~grd_n;
+wire gs_dac1_wr = gs_dac1_cs && ~grd_n;
+wire gs_dac2_wr = gs_dac2_cs && ~grd_n;
+wire gs_dac3_wr = gs_dac3_cs && ~grd_n;
 
 /* GS STATUS REGISTER */
 reg gs_flag_cmd, gs_flag_data;
@@ -258,38 +257,38 @@ always @(posedge clk32 or negedge rst_n) begin
 end
 
 /* GS BUS CONTROLLER */
-assign n_grom = (~n_gmreq && ((ga[15:14] == 2'b00) || (ga[15] && gs_page == 0)))? 1'b0 : 1'b1;
+assign grom_n = (~gmreq_n && ((ga[15:14] == 2'b00) || (ga[15] && gs_page == 0)))? 1'b0 : 1'b1;
 `ifdef GS_RAM_2MB
-    assign n_gram1 = (~n_gmreq && n_grom && ((gs_page[5:4] == 2'd0) || ~ga[15]))? 1'b0 : 1'b1;
-    assign n_gram2 = (~n_gmreq && n_grom &&  (gs_page[5:4] == 2'd1) &&  ga[15] )? 1'b0 : 1'b1;
-    assign n_gram3 = (~n_gmreq && n_grom &&  (gs_page[5:4] == 2'd2) &&  ga[15] )? 1'b0 : 1'b1;
-    assign n_gram4 = (~n_gmreq && n_grom &&  (gs_page[5:4] == 2'd3) &&  ga[15] )? 1'b0 : 1'b1;
+    assign gram1_n = (~gmreq_n && grom_n && ((gs_page[5:4] == 2'd0) || ~ga[15]))? 1'b0 : 1'b1;
+    assign gram2_n = (~gmreq_n && grom_n &&  (gs_page[5:4] == 2'd1) &&  ga[15] )? 1'b0 : 1'b1;
+    assign gram3_n = (~gmreq_n && grom_n &&  (gs_page[5:4] == 2'd2) &&  ga[15] )? 1'b0 : 1'b1;
+    assign gram4_n = (~gmreq_n && grom_n &&  (gs_page[5:4] == 2'd3) &&  ga[15] )? 1'b0 : 1'b1;
 `else
-    assign n_gram1 = (~n_gmreq && n_grom && (~gs_page[4] || ~ga[15]))? 1'b0 : 1'b1;
-    assign n_gram2 = (~n_gmreq && n_grom &&   gs_page[4] &&  ga[15] )? 1'b0 : 1'b1;
-    assign n_gram3 = 1'b1;
-    assign n_gram4 = 1'b1;
+    assign gram1_n = (~gmreq_n && grom_n && (~gs_page[4] || ~ga[15]))? 1'b0 : 1'b1;
+    assign gram2_n = (~gmreq_n && grom_n &&   gs_page[4] &&  ga[15] )? 1'b0 : 1'b1;
+    assign gram3_n = 1'b1;
+    assign gram4_n = 1'b1;
 `endif
 assign gma = (ga[15] == 1'b0)? 4'b0001 : gs_page[3:0];
 assign gd =
-    (~n_giorq && ~n_grd && ga[3:0] == 4'h4)? gs_status :
-    (~n_giorq && ~n_grd && ga[3:0] == 4'h2)? gs_regdata :
-    (~n_giorq && ~n_grd && ga[3:0] == 4'h1)? gs_regcmd :
-    (~n_giorq && (~n_grd || ~n_gm1))?        {8{1'b1}} :
+    (~giorq_n && ~grd_n && ga[3:0] == 4'h4)? gs_status :
+    (~giorq_n && ~grd_n && ga[3:0] == 4'h2)? gs_regdata :
+    (~giorq_n && ~grd_n && ga[3:0] == 4'h1)? gs_regcmd :
+    (~giorq_n && (~grd_n || ~gm1_n))?        {8{1'b1}} :
                                              {8{1'bz}} ;
 
 
 /* SOUNDRIVE */
-wire port_xf = sd_ena && a[7] == 1'b0 && a[5] == 1'b0 && a[3:0] == 4'hF && !rom_m1_access;
-wire [1:0] port_xf_chn = {a[6],a[4]};
+wire port_xf = sd_ena && zxa[7] == 1'b0 && zxa[5] == 1'b0 && zxa[3:0] == 4'hF && !rom_m1_access;
+wire [1:0] port_xf_chn = {zxa[6],zxa[4]};
 reg sd_dac0_cs; always @(posedge clk32) sd_dac0_cs = ioreq && port_xf && port_xf_chn == 2'd0;
 reg sd_dac1_cs; always @(posedge clk32) sd_dac1_cs = ioreq && port_xf && port_xf_chn == 2'd1;
 reg sd_dac2_cs; always @(posedge clk32) sd_dac2_cs = ioreq && port_xf && port_xf_chn == 2'd2;
 reg sd_dac3_cs; always @(posedge clk32) sd_dac3_cs = ioreq && port_xf && port_xf_chn == 2'd3;
-wire sd_dac0_wr = sd_dac0_cs && ~n_wr;
-wire sd_dac1_wr = sd_dac1_cs && ~n_wr;
-wire sd_dac2_wr = sd_dac2_cs && ~n_wr;
-wire sd_dac3_wr = sd_dac3_cs && ~n_wr;
+wire sd_dac0_wr = sd_dac0_cs && ~zxwr_n;
+wire sd_dac1_wr = sd_dac1_cs && ~zxwr_n;
+wire sd_dac2_wr = sd_dac2_cs && ~zxwr_n;
+wire sd_dac3_wr = sd_dac3_cs && ~zxwr_n;
 
 
 /* DAC */
@@ -323,14 +322,14 @@ always @(posedge clk32 or negedge rst_n) begin
     end
     else begin
         // quartus bug(?): without second condition inside "IF" expression incorrect design may be generated
-        if (sd_dac0_wr && !gs_dac0_wr) dac0 <= ( d[7]?  d : { d[7], ~d[6:0]});
-        else if           (gs_dac0_wr) dac0 <= (gd[7]? gd : {gd[7],~gd[6:0]});
-        if (sd_dac1_wr && !gs_dac1_wr) dac1 <= ( d[7]?  d : { d[7], ~d[6:0]});
-        else if           (gs_dac1_wr) dac1 <= (gd[7]? gd : {gd[7],~gd[6:0]});
-        if (sd_dac2_wr && !gs_dac2_wr) dac2 <= ( d[7]?  d : { d[7], ~d[6:0]});
-        else if           (gs_dac2_wr) dac2 <= (gd[7]? gd : {gd[7],~gd[6:0]});
-        if (sd_dac3_wr && !gs_dac3_wr) dac3 <= ( d[7]?  d : { d[7], ~d[6:0]});
-        else if           (gs_dac3_wr) dac3 <= (gd[7]? gd : {gd[7],~gd[6:0]});
+        if (sd_dac0_wr && !gs_dac0_wr) dac0 <= (zxd[7]? zxd : {zxd[7],~zxd[6:0]});
+        else if           (gs_dac0_wr) dac0 <= ( gd[7]? gd  : { gd[7],~gd[6:0]});
+        if (sd_dac1_wr && !gs_dac1_wr) dac1 <= (zxd[7]? zxd : {zxd[7],~zxd[6:0]});
+        else if           (gs_dac1_wr) dac1 <= ( gd[7]? gd  : { gd[7],~gd[6:0]});
+        if (sd_dac2_wr && !gs_dac2_wr) dac2 <= (zxd[7]? zxd : {zxd[7],~zxd[6:0]});
+        else if           (gs_dac2_wr) dac2 <= ( gd[7]? gd  : { gd[7],~gd[6:0]});
+        if (sd_dac3_wr && !gs_dac3_wr) dac3 <= (zxd[7]? zxd : {zxd[7],~zxd[6:0]});
+        else if           (gs_dac3_wr) dac3 <= ( gd[7]? gd  : { gd[7],~gd[6:0]});
     end
 end
 
@@ -355,14 +354,14 @@ end
 
 
 /* BUS CONTROLLER */
-assign n_ard = ~ioreq_rd;
-assign n_awr = ~ioreq_wr;
-assign aa0 = a[1]? saa_a0 : ym_a0 ;
-assign ad = ioreq_wr && (port_fffd || port_bffd || port_ff)? d : 8'bzzzzzzzz;
+assign ard_n = ~ioreq_rd;
+assign awr_n = ~ioreq_wr;
+assign aa0 = zxa[1]? saa_a0 : ym_a0 ;
+assign ad = ioreq_wr && (port_fffd || port_bffd || port_ff)? zxd : 8'bzzzzzzzz;
 
-assign n_wait = 1'bz;
-assign n_iorqge = (n_m1 && (port_fffd_full || port_bffd || port_b3 || port_bb))? 1'b0 : 1'b1;
-assign d =
+assign zxwait_n = 1'bz;
+assign zxiorqge_n = (zxm1_n && (port_fffd_full || port_bffd || port_b3 || port_bb))? 1'b0 : 1'b1;
+assign zxd =
     ioreq_rd && port_fffd? ad :
     ioreq_rd && port_b3? gs_reg_out :
     ioreq_rd && port_bb? gs_status :
diff --git a/cpld/syn/rev_A.qsf b/cpld/syn/rev_A.qsf
index e082849..dfdb871 100644
--- a/cpld/syn/rev_A.qsf
+++ b/cpld/syn/rev_A.qsf
@@ -55,13 +55,13 @@ set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
 set_global_assignment -name SAVE_DISK_SPACE OFF
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
-set_location_assignment PIN_1 -to n_gram2
+set_location_assignment PIN_1 -to gram2_n
 set_location_assignment PIN_2 -to gma[17]
 set_location_assignment PIN_5 -to gma[16]
 set_location_assignment PIN_6 -to gma[18]
-set_location_assignment PIN_7 -to n_gram1
-set_location_assignment PIN_8 -to n_gm1
-set_location_assignment PIN_9 -to n_grst
+set_location_assignment PIN_7 -to gram1_n
+set_location_assignment PIN_8 -to gm1_n
+set_location_assignment PIN_9 -to grst_n
 set_location_assignment PIN_10 -to ga[0]
 set_location_assignment PIN_11 -to ga[1]
 set_location_assignment PIN_12 -to ga[2]
@@ -73,16 +73,16 @@ set_location_assignment PIN_19 -to ga[7]
 set_location_assignment PIN_21 -to ga[8]
 set_location_assignment PIN_22 -to ga[9]
 set_location_assignment PIN_23 -to ga[10]
-set_location_assignment PIN_25 -to n_gwr
-set_location_assignment PIN_27 -to n_grd
-set_location_assignment PIN_28 -to n_giorq
-set_location_assignment PIN_29 -to n_gmreq
+set_location_assignment PIN_25 -to gwr_n
+set_location_assignment PIN_27 -to grd_n
+set_location_assignment PIN_28 -to giorq_n
+set_location_assignment PIN_29 -to gmreq_n
 set_location_assignment PIN_30 -to ga[11]
 set_location_assignment PIN_31 -to ga[12]
 set_location_assignment PIN_32 -to ga[13]
 set_location_assignment PIN_34 -to ga[14]
 set_location_assignment PIN_35 -to ga[15]
-set_location_assignment PIN_36 -to n_gint
+set_location_assignment PIN_36 -to gint_n
 set_location_assignment PIN_37 -to gd[3]
 set_location_assignment PIN_38 -to gd[5]
 set_location_assignment PIN_39 -to gd[6]
@@ -92,7 +92,7 @@ set_location_assignment PIN_42 -to gd[2]
 set_location_assignment PIN_43 -to gd[7]
 set_location_assignment PIN_44 -to gd[0]
 set_location_assignment PIN_45 -to gd[1]
-set_location_assignment PIN_46 -to n_grom
+set_location_assignment PIN_46 -to grom_n
 set_location_assignment PIN_47 -to gma[15]
 set_location_assignment PIN_48 -to cfg[0]
 set_location_assignment PIN_49 -to cfg[1]
@@ -103,17 +103,17 @@ set_location_assignment PIN_60 -to dac3_out
 set_location_assignment PIN_61 -to dac2_out
 set_location_assignment PIN_62 -to dac1_out
 set_location_assignment PIN_63 -to dac0_out
-set_location_assignment PIN_70 -to n_gram4
-set_location_assignment PIN_71 -to n_gram3
-set_location_assignment PIN_72 -to n_mreq
+set_location_assignment PIN_70 -to gram4_n
+set_location_assignment PIN_71 -to gram3_n
+set_location_assignment PIN_72 -to zxmreq_n
 set_location_assignment PIN_74 -to fm1_ena
 set_location_assignment PIN_75 -to ym_m
 set_location_assignment PIN_78 -to aa0
-set_location_assignment PIN_79 -to n_ard
-set_location_assignment PIN_80 -to n_awr
-set_location_assignment PIN_81 -to n_ym1_cs
-set_location_assignment PIN_82 -to n_ym2_cs
-set_location_assignment PIN_83 -to n_rstout
+set_location_assignment PIN_79 -to ard_n
+set_location_assignment PIN_80 -to awr_n
+set_location_assignment PIN_81 -to ym1_cs_n
+set_location_assignment PIN_82 -to ym2_cs_n
+set_location_assignment PIN_83 -to rstout_n
 set_location_assignment PIN_84 -to fm2_ena
 set_location_assignment PIN_86 -to ad[0]
 set_location_assignment PIN_87 -to ad[1]
@@ -123,44 +123,44 @@ set_location_assignment PIN_91 -to ad[4]
 set_location_assignment PIN_92 -to ad[5]
 set_location_assignment PIN_93 -to ad[6]
 set_location_assignment PIN_96 -to ad[7]
-set_location_assignment PIN_97 -to n_saa_cs
+set_location_assignment PIN_97 -to saa_cs_n
 set_location_assignment PIN_98 -to saa_clk
 set_location_assignment PIN_99 -to midi_clk
-set_location_assignment PIN_100 -to a[14]
-set_location_assignment PIN_101 -to a[15]
-set_location_assignment PIN_102 -to a[12]
-set_location_assignment PIN_103 -to a[13]
-set_location_assignment PIN_106 -to d[7]
-set_location_assignment PIN_107 -to n_dos
-set_location_assignment PIN_108 -to d[0]
-set_location_assignment PIN_109 -to d[1]
-set_location_assignment PIN_110 -to d[2]
-set_location_assignment PIN_111 -to a[0]
-set_location_assignment PIN_112 -to d[6]
-set_location_assignment PIN_113 -to a[1]
-set_location_assignment PIN_116 -to d[5]
-set_location_assignment PIN_117 -to a[2]
-set_location_assignment PIN_118 -to d[3]
-set_location_assignment PIN_119 -to a[3]
-set_location_assignment PIN_120 -to d[4]
-set_location_assignment PIN_121 -to n_iorqge
-set_location_assignment PIN_122 -to n_iorq
+set_location_assignment PIN_100 -to zxa[14]
+set_location_assignment PIN_101 -to zxa[15]
+set_location_assignment PIN_102 -to zxa[12]
+set_location_assignment PIN_103 -to zxa[13]
+set_location_assignment PIN_106 -to zxd[7]
+set_location_assignment PIN_107 -to zxdos_n
+set_location_assignment PIN_108 -to zxd[0]
+set_location_assignment PIN_109 -to zxd[1]
+set_location_assignment PIN_110 -to zxd[2]
+set_location_assignment PIN_111 -to zxa[0]
+set_location_assignment PIN_112 -to zxd[6]
+set_location_assignment PIN_113 -to zxa[1]
+set_location_assignment PIN_116 -to zxd[5]
+set_location_assignment PIN_117 -to zxa[2]
+set_location_assignment PIN_118 -to zxd[3]
+set_location_assignment PIN_119 -to zxa[3]
+set_location_assignment PIN_120 -to zxd[4]
+set_location_assignment PIN_121 -to zxiorqge_n
+set_location_assignment PIN_122 -to zxiorq_n
 set_location_assignment PIN_125 -to clkx
-set_location_assignment PIN_126 -to n_rd
+set_location_assignment PIN_126 -to zxrd_n
 set_location_assignment PIN_127 -to rst_n
 set_location_assignment PIN_128 -to clk32
-set_location_assignment PIN_131 -to n_wr
-set_location_assignment PIN_132 -to n_iodos
-set_location_assignment PIN_133 -to n_wait
-set_location_assignment PIN_134 -to a[7]
-set_location_assignment PIN_136 -to a[6]
-set_location_assignment PIN_137 -to a[5]
-set_location_assignment PIN_138 -to n_m1
-set_location_assignment PIN_139 -to a[4]
-set_location_assignment PIN_140 -to a[8]
-set_location_assignment PIN_141 -to a[9]
-set_location_assignment PIN_142 -to a[10]
-set_location_assignment PIN_143 -to a[11]
+set_location_assignment PIN_131 -to zxwr_n
+set_location_assignment PIN_132 -to zxiodos_n
+set_location_assignment PIN_133 -to zxwait_n
+set_location_assignment PIN_134 -to zxa[7]
+set_location_assignment PIN_136 -to zxa[6]
+set_location_assignment PIN_137 -to zxa[5]
+set_location_assignment PIN_138 -to zxm1_n
+set_location_assignment PIN_139 -to zxa[4]
+set_location_assignment PIN_140 -to zxa[8]
+set_location_assignment PIN_141 -to zxa[9]
+set_location_assignment PIN_142 -to zxa[10]
+set_location_assignment PIN_143 -to zxa[11]
 set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
 set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
 set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
diff --git a/cpld/syn/rev_A1.qsf b/cpld/syn/rev_A1.qsf
index aa88654..26fe7fa 100644
--- a/cpld/syn/rev_A1.qsf
+++ b/cpld/syn/rev_A1.qsf
@@ -55,14 +55,14 @@ set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
 set_global_assignment -name SAVE_DISK_SPACE OFF
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
-set_location_assignment PIN_1 -to n_gram4
-set_location_assignment PIN_2 -to n_gram2
+set_location_assignment PIN_1 -to gram4_n
+set_location_assignment PIN_2 -to gram2_n
 set_location_assignment PIN_5 -to gma[17]
 set_location_assignment PIN_6 -to gma[16]
 set_location_assignment PIN_7 -to gma[18]
-set_location_assignment PIN_8 -to n_gram1
-set_location_assignment PIN_9 -to n_gm1
-set_location_assignment PIN_10 -to n_grst
+set_location_assignment PIN_8 -to gram1_n
+set_location_assignment PIN_9 -to gm1_n
+set_location_assignment PIN_10 -to grst_n
 set_location_assignment PIN_11 -to ga[0]
 set_location_assignment PIN_12 -to ga[1]
 set_location_assignment PIN_14 -to ga[2]
@@ -74,10 +74,10 @@ set_location_assignment PIN_21 -to ga[7]
 set_location_assignment PIN_22 -to ga[8]
 set_location_assignment PIN_23 -to ga[9]
 set_location_assignment PIN_25 -to ga[10]
-set_location_assignment PIN_27 -to n_gwr
-set_location_assignment PIN_28 -to n_grd
-set_location_assignment PIN_29 -to n_giorq
-set_location_assignment PIN_30 -to n_gmreq
+set_location_assignment PIN_27 -to gwr_n
+set_location_assignment PIN_28 -to grd_n
+set_location_assignment PIN_29 -to giorq_n
+set_location_assignment PIN_30 -to gmreq_n
 set_location_assignment PIN_31 -to ga[11]
 set_location_assignment PIN_32 -to ga[12]
 set_location_assignment PIN_34 -to ga[13]
@@ -90,10 +90,10 @@ set_location_assignment PIN_40 -to gd[2]
 set_location_assignment PIN_41 -to gd[7]
 set_location_assignment PIN_42 -to gd[4]
 set_location_assignment PIN_43 -to gclk
-set_location_assignment PIN_44 -to n_gint
+set_location_assignment PIN_44 -to gint_n
 set_location_assignment PIN_45 -to gd[0]
 set_location_assignment PIN_46 -to gd[1]
-set_location_assignment PIN_47 -to n_grom
+set_location_assignment PIN_47 -to grom_n
 set_location_assignment PIN_48 -to gma[15]
 set_location_assignment PIN_49 -to cfg[0]
 set_location_assignment PIN_53 -to cfg[1]
@@ -107,11 +107,11 @@ set_location_assignment PIN_63 -to dac0_out
 set_location_assignment PIN_69 -to ym_m
 set_location_assignment PIN_70 -to fm1_ena
 set_location_assignment PIN_74 -to aa0
-set_location_assignment PIN_75 -to n_ard
-set_location_assignment PIN_78 -to n_awr
-set_location_assignment PIN_79 -to n_ym1_cs
-set_location_assignment PIN_80 -to n_ym2_cs
-set_location_assignment PIN_81 -to n_rstout
+set_location_assignment PIN_75 -to ard_n
+set_location_assignment PIN_78 -to awr_n
+set_location_assignment PIN_79 -to ym1_cs_n
+set_location_assignment PIN_80 -to ym2_cs_n
+set_location_assignment PIN_81 -to rstout_n
 set_location_assignment PIN_82 -to fm2_ena
 set_location_assignment PIN_83 -to ad[0]
 set_location_assignment PIN_84 -to ad[1]
@@ -121,46 +121,46 @@ set_location_assignment PIN_88 -to ad[4]
 set_location_assignment PIN_90 -to ad[5]
 set_location_assignment PIN_91 -to ad[6]
 set_location_assignment PIN_92 -to ad[7]
-set_location_assignment PIN_93 -to n_saa_cs
+set_location_assignment PIN_93 -to saa_cs_n
 set_location_assignment PIN_96 -to saa_clk
 set_location_assignment PIN_97 -to midi_clk
-set_location_assignment PIN_98 -to a[14]
-set_location_assignment PIN_99 -to a[15]
-set_location_assignment PIN_100 -to a[12]
-set_location_assignment PIN_101 -to a[13]
-set_location_assignment PIN_102 -to d[7]
-set_location_assignment PIN_103 -to d[0]
-set_location_assignment PIN_106 -to d[1]
-set_location_assignment PIN_107 -to d[2]
-set_location_assignment PIN_108 -to n_dos
-set_location_assignment PIN_109 -to a[0]
-set_location_assignment PIN_110 -to d[6]
-set_location_assignment PIN_111 -to a[1]
-set_location_assignment PIN_112 -to d[5]
-set_location_assignment PIN_113 -to a[2]
-set_location_assignment PIN_116 -to d[3]
-set_location_assignment PIN_117 -to a[3]
-set_location_assignment PIN_118 -to d[4]
-set_location_assignment PIN_119 -to n_iorqge
-set_location_assignment PIN_120 -to n_mreq
-set_location_assignment PIN_121 -to n_iorq
-set_location_assignment PIN_122 -to n_rd
+set_location_assignment PIN_98 -to zxa[14]
+set_location_assignment PIN_99 -to zxa[15]
+set_location_assignment PIN_100 -to zxa[12]
+set_location_assignment PIN_101 -to zxa[13]
+set_location_assignment PIN_102 -to zxd[7]
+set_location_assignment PIN_103 -to zxd[0]
+set_location_assignment PIN_106 -to zxd[1]
+set_location_assignment PIN_107 -to zxd[2]
+set_location_assignment PIN_108 -to zxdos_n
+set_location_assignment PIN_109 -to zxa[0]
+set_location_assignment PIN_110 -to zxd[6]
+set_location_assignment PIN_111 -to zxa[1]
+set_location_assignment PIN_112 -to zxd[5]
+set_location_assignment PIN_113 -to zxa[2]
+set_location_assignment PIN_116 -to zxd[3]
+set_location_assignment PIN_117 -to zxa[3]
+set_location_assignment PIN_118 -to zxd[4]
+set_location_assignment PIN_119 -to zxiorqge_n
+set_location_assignment PIN_120 -to zxmreq_n
+set_location_assignment PIN_121 -to zxiorq_n
+set_location_assignment PIN_122 -to zxrd_n
 set_location_assignment PIN_125 -to clkx
-set_location_assignment PIN_126 -to n_wr
+set_location_assignment PIN_126 -to zxwr_n
 set_location_assignment PIN_127 -to rst_n
 set_location_assignment PIN_128 -to clk32
-set_location_assignment PIN_131 -to n_iodos
-set_location_assignment PIN_132 -to n_wait
-set_location_assignment PIN_133 -to a[7]
-set_location_assignment PIN_134 -to a[6]
-set_location_assignment PIN_136 -to a[5]
-set_location_assignment PIN_137 -to n_m1
-set_location_assignment PIN_138 -to a[4]
-set_location_assignment PIN_139 -to a[8]
-set_location_assignment PIN_140 -to a[9]
-set_location_assignment PIN_141 -to a[10]
-set_location_assignment PIN_142 -to a[11]
-set_location_assignment PIN_143 -to n_gram3
+set_location_assignment PIN_131 -to zxiodos_n
+set_location_assignment PIN_132 -to zxwait_n
+set_location_assignment PIN_133 -to zxa[7]
+set_location_assignment PIN_134 -to zxa[6]
+set_location_assignment PIN_136 -to zxa[5]
+set_location_assignment PIN_137 -to zxm1_n
+set_location_assignment PIN_138 -to zxa[4]
+set_location_assignment PIN_139 -to zxa[8]
+set_location_assignment PIN_140 -to zxa[9]
+set_location_assignment PIN_141 -to zxa[10]
+set_location_assignment PIN_142 -to zxa[11]
+set_location_assignment PIN_143 -to gram3_n
 set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
 set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
 set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
diff --git a/cpld/syn/rev_A1_2mb.qsf b/cpld/syn/rev_A1_2mb.qsf
index 93f2b59..f1c978e 100644
--- a/cpld/syn/rev_A1_2mb.qsf
+++ b/cpld/syn/rev_A1_2mb.qsf
@@ -55,14 +55,14 @@ set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
 set_global_assignment -name SAVE_DISK_SPACE OFF
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
 set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
-set_location_assignment PIN_1 -to n_gram4
-set_location_assignment PIN_2 -to n_gram2
+set_location_assignment PIN_1 -to gram4_n
+set_location_assignment PIN_2 -to gram2_n
 set_location_assignment PIN_5 -to gma[17]
 set_location_assignment PIN_6 -to gma[16]
 set_location_assignment PIN_7 -to gma[18]
-set_location_assignment PIN_8 -to n_gram1
-set_location_assignment PIN_9 -to n_gm1
-set_location_assignment PIN_10 -to n_grst
+set_location_assignment PIN_8 -to gram1_n
+set_location_assignment PIN_9 -to gm1_n
+set_location_assignment PIN_10 -to grst_n
 set_location_assignment PIN_11 -to ga[0]
 set_location_assignment PIN_12 -to ga[1]
 set_location_assignment PIN_14 -to ga[2]
@@ -74,10 +74,10 @@ set_location_assignment PIN_21 -to ga[7]
 set_location_assignment PIN_22 -to ga[8]
 set_location_assignment PIN_23 -to ga[9]
 set_location_assignment PIN_25 -to ga[10]
-set_location_assignment PIN_27 -to n_gwr
-set_location_assignment PIN_28 -to n_grd
-set_location_assignment PIN_29 -to n_giorq
-set_location_assignment PIN_30 -to n_gmreq
+set_location_assignment PIN_27 -to gwr_n
+set_location_assignment PIN_28 -to grd_n
+set_location_assignment PIN_29 -to giorq_n
+set_location_assignment PIN_30 -to gmreq_n
 set_location_assignment PIN_31 -to ga[11]
 set_location_assignment PIN_32 -to ga[12]
 set_location_assignment PIN_34 -to ga[13]
@@ -90,10 +90,10 @@ set_location_assignment PIN_40 -to gd[2]
 set_location_assignment PIN_41 -to gd[7]
 set_location_assignment PIN_42 -to gd[4]
 set_location_assignment PIN_43 -to gclk
-set_location_assignment PIN_44 -to n_gint
+set_location_assignment PIN_44 -to gint_n
 set_location_assignment PIN_45 -to gd[0]
 set_location_assignment PIN_46 -to gd[1]
-set_location_assignment PIN_47 -to n_grom
+set_location_assignment PIN_47 -to grom_n
 set_location_assignment PIN_48 -to gma[15]
 set_location_assignment PIN_49 -to cfg[0]
 set_location_assignment PIN_53 -to cfg[1]
@@ -107,11 +107,11 @@ set_location_assignment PIN_63 -to dac0_out
 set_location_assignment PIN_69 -to ym_m
 set_location_assignment PIN_70 -to fm1_ena
 set_location_assignment PIN_74 -to aa0
-set_location_assignment PIN_75 -to n_ard
-set_location_assignment PIN_78 -to n_awr
-set_location_assignment PIN_79 -to n_ym1_cs
-set_location_assignment PIN_80 -to n_ym2_cs
-set_location_assignment PIN_81 -to n_rstout
+set_location_assignment PIN_75 -to ard_n
+set_location_assignment PIN_78 -to awr_n
+set_location_assignment PIN_79 -to ym1_cs_n
+set_location_assignment PIN_80 -to ym2_cs_n
+set_location_assignment PIN_81 -to rstout_n
 set_location_assignment PIN_82 -to fm2_ena
 set_location_assignment PIN_83 -to ad[0]
 set_location_assignment PIN_84 -to ad[1]
@@ -121,46 +121,46 @@ set_location_assignment PIN_88 -to ad[4]
 set_location_assignment PIN_90 -to ad[5]
 set_location_assignment PIN_91 -to ad[6]
 set_location_assignment PIN_92 -to ad[7]
-set_location_assignment PIN_93 -to n_saa_cs
+set_location_assignment PIN_93 -to saa_cs_n
 set_location_assignment PIN_96 -to saa_clk
 set_location_assignment PIN_97 -to midi_clk
-set_location_assignment PIN_98 -to a[14]
-set_location_assignment PIN_99 -to a[15]
-set_location_assignment PIN_100 -to a[12]
-set_location_assignment PIN_101 -to a[13]
-set_location_assignment PIN_102 -to d[7]
-set_location_assignment PIN_103 -to d[0]
-set_location_assignment PIN_106 -to d[1]
-set_location_assignment PIN_107 -to d[2]
-set_location_assignment PIN_108 -to n_dos
-set_location_assignment PIN_109 -to a[0]
-set_location_assignment PIN_110 -to d[6]
-set_location_assignment PIN_111 -to a[1]
-set_location_assignment PIN_112 -to d[5]
-set_location_assignment PIN_113 -to a[2]
-set_location_assignment PIN_116 -to d[3]
-set_location_assignment PIN_117 -to a[3]
-set_location_assignment PIN_118 -to d[4]
-set_location_assignment PIN_119 -to n_iorqge
-set_location_assignment PIN_120 -to n_mreq
-set_location_assignment PIN_121 -to n_iorq
-set_location_assignment PIN_122 -to n_rd
+set_location_assignment PIN_98 -to zxa[14]
+set_location_assignment PIN_99 -to zxa[15]
+set_location_assignment PIN_100 -to zxa[12]
+set_location_assignment PIN_101 -to zxa[13]
+set_location_assignment PIN_102 -to zxd[7]
+set_location_assignment PIN_103 -to zxd[0]
+set_location_assignment PIN_106 -to zxd[1]
+set_location_assignment PIN_107 -to zxd[2]
+set_location_assignment PIN_108 -to zxdos_n
+set_location_assignment PIN_109 -to zxa[0]
+set_location_assignment PIN_110 -to zxd[6]
+set_location_assignment PIN_111 -to zxa[1]
+set_location_assignment PIN_112 -to zxd[5]
+set_location_assignment PIN_113 -to zxa[2]
+set_location_assignment PIN_116 -to zxd[3]
+set_location_assignment PIN_117 -to zxa[3]
+set_location_assignment PIN_118 -to zxd[4]
+set_location_assignment PIN_119 -to zxiorqge_n
+set_location_assignment PIN_120 -to zxmreq_n
+set_location_assignment PIN_121 -to zxiorq_n
+set_location_assignment PIN_122 -to zxrd_n
 set_location_assignment PIN_125 -to clkx
-set_location_assignment PIN_126 -to n_wr
+set_location_assignment PIN_126 -to zxwr_n
 set_location_assignment PIN_127 -to rst_n
 set_location_assignment PIN_128 -to clk32
-set_location_assignment PIN_131 -to n_iodos
-set_location_assignment PIN_132 -to n_wait
-set_location_assignment PIN_133 -to a[7]
-set_location_assignment PIN_134 -to a[6]
-set_location_assignment PIN_136 -to a[5]
-set_location_assignment PIN_137 -to n_m1
-set_location_assignment PIN_138 -to a[4]
-set_location_assignment PIN_139 -to a[8]
-set_location_assignment PIN_140 -to a[9]
-set_location_assignment PIN_141 -to a[10]
-set_location_assignment PIN_142 -to a[11]
-set_location_assignment PIN_143 -to n_gram3
+set_location_assignment PIN_131 -to zxiodos_n
+set_location_assignment PIN_132 -to zxwait_n
+set_location_assignment PIN_133 -to zxa[7]
+set_location_assignment PIN_134 -to zxa[6]
+set_location_assignment PIN_136 -to zxa[5]
+set_location_assignment PIN_137 -to zxm1_n
+set_location_assignment PIN_138 -to zxa[4]
+set_location_assignment PIN_139 -to zxa[8]
+set_location_assignment PIN_140 -to zxa[9]
+set_location_assignment PIN_141 -to zxa[10]
+set_location_assignment PIN_142 -to zxa[11]
+set_location_assignment PIN_143 -to gram3_n
 set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
 set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
 set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF