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update cpld firmware - finally working version

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This commit is contained in:
Eugene Lozovoy 2022-11-15 20:44:01 +03:00
parent 81513481fe
commit fc319bd685
6 changed files with 340 additions and 273 deletions
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271
cpld/rtl/top.v
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@ -3,22 +3,24 @@ module zx_multisound(
input clk32, input clk32,
input clkx, input clkx,
input [2:0] cfg, input [4:0] cfg,
input [15:0] a, input [15:0] a,
inout [7:0] d, inout [7:0] d,
input n_rd, input n_rd,
input n_wr, input n_wr,
input n_iorq, input n_iorq,
input n_mreq,
input n_m1, input n_m1,
output n_wait, output n_wait,
output n_iorqge, output n_iorqge,
input dos, input n_dos,
input iodos, input n_iodos,
output aa0, output aa0,
inout [7:0] ad, inout [7:0] ad,
output n_rstout,
output n_ard, output n_ard,
output n_awr, output n_awr,
output ym_m, output ym_m,
@ -41,22 +43,44 @@ module zx_multisound(
input n_gmreq, input n_gmreq,
input n_giorq, input n_giorq,
output n_grom, output n_grom,
output n_gram, output n_gram1,
output n_gram2,
output [18:15] gma, output [18:15] gma,
output gdac0, output dac0_out,
output gdac1, output dac1_out,
output gdac2, output dac2_out,
output gdac3 output dac3_out
); );
wire n_iorq0 = n_iorq | ~dos | ~iodos; assign n_rstout = rst_n;
// n_iorq are useless in zxevo :(
// so we're detecting n_iorq cycle by n_rd/n_wr signal asserted without n_m1/n_mreq
reg ioreq;
always @(negedge clk32) begin
// ioreq <= n_iorq == 1'b0 && n_m1 == 1'b1 && n_dos == 1'b1 && n_iodos == 1'b1;
ioreq <= n_m1 == 1'b1 && n_mreq == 1'b1 && (n_rd == 1'b0 || n_wr == 1'b0);
end
wire ioreq_rd = ioreq && n_rd == 1'b0;
wire ioreq_wr = ioreq && n_wr == 1'b0;
// n_dos are useless in zxevo :(
// so we're just lock some ports access when instruction has been fetched from rom
reg rom_m1_access;
always @(negedge clk32 or negedge rst_n) begin
if (!rst_n)
rom_m1_access <= 0;
else if (n_m1 == 0)
rom_m1_access <= a[15:14] == 2'b00;
end
/* CONFIGURATION */ /* CONFIGURATION */
wire ym_ena = cfg[0]; wire ym_ena = cfg[0];
wire saa_ena = cfg[1]; wire saa_ena = cfg[1];
wire gs_ena = cfg[2]; wire gs_ena = cfg[2];
wire sd_ena = cfg[3];
/* TURBO SOUND FM */ /* TURBO SOUND FM */
@ -65,8 +89,8 @@ wire port_fffd = a[15:14] == 2'b11 && a[1:0] == 2'b01 && ym_ena;
wire port_fffd_full = a[15:13] == 3'b111 && a[1:0] == 2'b01 && ym_ena; // required for compatibility with #dffd port wire port_fffd_full = a[15:13] == 3'b111 && a[1:0] == 2'b01 && ym_ena; // required for compatibility with #dffd port
reg ym_chip_sel, ym_get_stat; reg ym_chip_sel, ym_get_stat;
wire ym_a0 = (~n_rd & a[14] & ~ym_get_stat) | (~n_wr & ~a[14]); wire ym_a0 = (~n_rd & a[14] & ~ym_get_stat) | (~n_wr & ~a[14]);
assign n_ym1_cs = ~(~ym_chip_sel && (port_bffd || port_fffd) && ~n_iorq0 && n_m1); assign n_ym1_cs = ~(~ym_chip_sel && (port_bffd || port_fffd));
assign n_ym2_cs = ~( ym_chip_sel && (port_bffd || port_fffd) && ~n_iorq0 && n_m1); assign n_ym2_cs = ~( ym_chip_sel && (port_bffd || port_fffd));
always @(posedge clk32 or negedge rst_n) begin always @(posedge clk32 or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
@ -75,7 +99,7 @@ always @(posedge clk32 or negedge rst_n) begin
fm1_ena <= 0; fm1_ena <= 0;
fm2_ena <= 0; fm2_ena <= 0;
end end
else if (port_fffd && ~n_iorq0 && ~n_wr && d[7:3] == 5'b11111) begin else if (port_fffd && ioreq_wr && d[7:4] == 4'b1111) begin
ym_chip_sel <= ~d[0]; ym_chip_sel <= ~d[0];
ym_get_stat <= ~d[1]; ym_get_stat <= ~d[1];
fm1_ena <= d[2]? 1'b0 : 1'bz; fm1_ena <= d[2]? 1'b0 : 1'bz;
@ -91,16 +115,17 @@ end
/* SAA1099 */ /* SAA1099 */
wire port_ff = a[7:0] == 8'hFF && saa_ena; wire port_ff = a[7:0] == 8'hFF && saa_ena && !rom_m1_access;
assign n_saa_cs = ~(port_ff && ~n_iorq0 && ~n_wr); assign n_saa_cs = ~(port_ff && ioreq_wr);
wire saa_a0 = a[8]; wire saa_a0 = a[8];
wire port_fffd_saa = a[15:14] == 2'b11 && a[1:0] == 2'b01 && saa_ena;
reg saa_clk_en; reg saa_clk_en;
always @(posedge clk32) begin always @(posedge clk32 or negedge rst_n) begin
if (!rst_n) if (!rst_n)
saa_clk_en <= 1'b0; saa_clk_en <= 0;
else if (~n_saa_cs && ~n_awr) else if (port_fffd_saa && ioreq_wr && d[7:4] == 4'b1111)
saa_clk_en <= 1'b1; saa_clk_en <= ~d[3];
end end
reg [1:0] saa_clk_cnt = 0; reg [1:0] saa_clk_cnt = 0;
@ -120,7 +145,7 @@ end
/* GENERAL SOUND */ /* GENERAL SOUND */
assign gclk = midi_clk; assign gclk = midi_clk;
assign n_grst = rst_n; assign n_grst = n_rstout;
reg [8:0] g_int_cnt; reg [8:0] g_int_cnt;
wire g_int_reload = g_int_cnt[8:6] == 4'b101; wire g_int_reload = g_int_cnt[8:6] == 4'b101;
@ -152,108 +177,72 @@ always @(posedge clk32 or negedge rst_n) begin
gs_regbb <= 0; gs_regbb <= 0;
end end
else begin else begin
if (port_b3 && ~n_iorq0 && ~n_wr) if (port_b3 && ioreq_wr)
gs_regb3 <= d; gs_regb3 <= d;
if (port_bb && ~n_iorq0 && ~n_wr) if (port_bb && ioreq_wr)
gs_regbb <= d; gs_regbb <= d;
end end
end end
/* GS INTERNAL REGISTERS */ /* GS INTERNAL REGISTERS */
reg [7:0] gs_reg00, gs_reg03; reg [7:0] gs_reg00, gs_reg03;
wire [3:0] gs_page = gs_reg00[3:0]; wire [5:0] gs_page = gs_reg00[5:0];
reg [5:0] gs_vol0, gs_vol1, gs_vol2, gs_vol3;
always @(posedge clk32 or negedge rst_n) begin always @(posedge clk32 or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
gs_reg00 <= 0; gs_reg00 <= 0;
gs_reg03 <= 0; gs_reg03 <= 0;
gs_vol0 <= 0;
gs_vol1 <= 0;
gs_vol2 <= 0;
gs_vol3 <= 0;
end end
else if (~n_giorq && ~n_gwr) begin else if (~n_giorq && ~n_gwr) begin
if (ga[3:0] == 4'h0) gs_reg00 <= gd; if (ga[3:0] == 4'h0) gs_reg00 <= gd;
if (ga[3:0] == 4'h3) gs_reg03 <= gd; if (ga[3:0] == 4'h3) gs_reg03 <= gd;
if (ga[3:0] == 4'h6) gs_vol0 <= gd[5:0];
if (ga[3:0] == 4'h7) gs_vol1 <= gd[5:0];
if (ga[3:0] == 4'h8) gs_vol2 <= gd[5:0];
if (ga[3:0] == 4'h9) gs_vol3 <= gd[5:0];
end end
end end
reg [7:0] gs_dac0, gs_dac1, gs_dac2, gs_dac3; /* GS DAC REGISTERS */
always @(posedge clk32 or negedge rst_n) begin reg gs_vol0_cs; always @(posedge clk32) gs_vol0_cs = ~n_giorq && ga[3:0] == 4'h6;
if (!rst_n) begin reg gs_vol1_cs; always @(posedge clk32) gs_vol1_cs = ~n_giorq && ga[3:0] == 4'h7;
gs_dac0 <= 0; reg gs_vol2_cs; always @(posedge clk32) gs_vol2_cs = ~n_giorq && ga[3:0] == 4'h8;
gs_dac1 <= 0; reg gs_vol3_cs; always @(posedge clk32) gs_vol3_cs = ~n_giorq && ga[3:0] == 4'h9;
gs_dac2 <= 0; reg gs_dac0_cs; always @(posedge clk32) gs_dac0_cs = ~n_gmreq && ga[15:13] == 3'b011 && ga[9:8] == 2'd0;
gs_dac3 <= 0; reg gs_dac1_cs; always @(posedge clk32) gs_dac1_cs = ~n_gmreq && ga[15:13] == 3'b011 && ga[9:8] == 2'd1;
end reg gs_dac2_cs; always @(posedge clk32) gs_dac2_cs = ~n_gmreq && ga[15:13] == 3'b011 && ga[9:8] == 2'd2;
else if (~n_gmreq && ~n_grd && ga[15:13] == 3'b011) begin reg gs_dac3_cs; always @(posedge clk32) gs_dac3_cs = ~n_gmreq && ga[15:13] == 3'b011 && ga[9:8] == 2'd3;
if (ga[9:8] == 2'b00) gs_dac0 <= gd; wire gs_vol0_wr = gs_vol0_cs && ~n_gwr;
if (ga[9:8] == 2'b01) gs_dac1 <= gd; wire gs_vol1_wr = gs_vol1_cs && ~n_gwr;
if (ga[9:8] == 2'b10) gs_dac2 <= gd; wire gs_vol2_wr = gs_vol2_cs && ~n_gwr;
if (ga[9:8] == 2'b11) gs_dac3 <= gd; wire gs_vol3_wr = gs_vol3_cs && ~n_gwr;
end wire gs_dac0_wr = gs_dac0_cs && ~n_grd;
end wire gs_dac1_wr = gs_dac1_cs && ~n_grd;
wire gs_dac2_wr = gs_dac2_cs && ~n_grd;
wire gs_dac3_wr = gs_dac3_cs && ~n_grd;
/* GS STATUS REGISTER */ /* GS STATUS REGISTER */
reg gs_status0, gs_status7; reg gs_flag_cmd, gs_flag_data;
wire [7:0] gs_status = {gs_status7, 6'b111111, gs_status0}; wire [7:0] gs_status = {gs_flag_data, 6'b111111, gs_flag_cmd};
always @(posedge clk32) begin always @(posedge clk32) begin
if ((~n_giorq && n_gm1 && ga[3:0] == 4'h2) || (~n_iorq0 && ~n_rd && port_b3)) if ((~n_giorq && n_gm1 && ga[3:0] == 4'h2) || (ioreq_rd && port_b3))
gs_status7 <= 1'b0; gs_flag_data <= 1'b0;
else if ((~n_giorq && n_gm1 && ga[3:0] == 4'h3) || (~n_iorq0 && ~n_wr && port_b3)) else if ((~n_giorq && n_gm1 && ga[3:0] == 4'h3) || (ioreq_wr && port_b3))
gs_status7 <= 1'b1; gs_flag_data <= 1'b1;
else if (~n_giorq && n_gm1 && ga[3:0] == 4'hA) else if (~n_giorq && n_gm1 && ga[3:0] == 4'hA)
gs_status7 <= ~gs_reg00[0]; gs_flag_data <= ~gs_reg00[0];
end end
always @(posedge clk32) begin always @(posedge clk32) begin
if (~n_giorq && n_gm1 && ga[3:0] == 4'h5) if (~n_giorq && n_gm1 && ga[3:0] == 4'h5)
gs_status0 <= 1'b0; gs_flag_cmd <= 1'b0;
else if (~n_iorq0 && ~n_wr && port_bb) else if (ioreq_wr && port_bb)
gs_status0 <= 1'b1; gs_flag_cmd <= 1'b1;
else if (~n_giorq && n_gm1 && ga[3:0] == 4'hB) else if (~n_giorq && n_gm1 && ga[3:0] == 4'hB)
gs_status0 <= gs_vol0[5]; gs_flag_cmd <= vol3[5];
end
/* GS DAC */
reg vol0_en, vol1_en, vol2_en, vol3_en;
reg [5:0] vol_cnt;
reg [8:0] dac0_cnt, dac1_cnt, dac2_cnt, dac3_cnt;
assign gdac0 = dac0_cnt[8];
assign gdac1 = dac1_cnt[8];
assign gdac2 = dac2_cnt[8];
assign gdac3 = dac3_cnt[8];
always @(posedge clk32 or negedge rst_n) begin
if (!rst_n) begin
{vol0_en, vol1_en, vol2_en, vol3_en} <= 0;
vol_cnt <= 0;
dac0_cnt <= 0;
dac1_cnt <= 0;
dac2_cnt <= 0;
dac3_cnt <= 0;
end
else begin
vol_cnt <= vol_cnt + 6'd31;
vol0_en <= vol_cnt < gs_vol0;
vol1_en <= vol_cnt < gs_vol1;
vol2_en <= vol_cnt < gs_vol2;
vol3_en <= vol_cnt < gs_vol3;
if (vol0_en) dac0_cnt <= dac0_cnt[7:0] + gs_dac0; else dac0_cnt[8] <= 0;
if (vol1_en) dac1_cnt <= dac1_cnt[7:0] + gs_dac1; else dac1_cnt[8] <= 0;
if (vol2_en) dac2_cnt <= dac2_cnt[7:0] + gs_dac2; else dac2_cnt[8] <= 0;
if (vol3_en) dac3_cnt <= dac3_cnt[7:0] + gs_dac3; else dac3_cnt[8] <= 0;
end
end end
/* GS BUS CONTROLLER */ /* GS BUS CONTROLLER */
assign n_grom = (~n_gmreq && ((ga[15:14] == 2'b00) || (ga[15] == 1'b1 && gs_page == 0)))? 1'b0 : 1'b1; assign n_grom = (~n_gmreq && ((ga[15:14] == 2'b00) || (ga[15] && gs_page == 0)))? 1'b0 : 1'b1;
assign n_gram = (~n_gmreq && n_grom)? 1'b0 : 1'b1; assign n_gram1 = (~n_gmreq && n_grom && (~gs_page[4] || ~ga[15]))? 1'b0 : 1'b1;
assign gma = (ga[15] == 1'b0)? 4'b0001 : gs_page; assign n_gram2 = (~n_gmreq && n_grom && gs_page[4] && ga[15] )? 1'b0 : 1'b1;
assign gma = (ga[15] == 1'b0)? 4'b0001 : gs_page[3:0];
assign gd = assign gd =
(~n_giorq && ~n_grd && ga[3:0] == 4'h4)? gs_status : (~n_giorq && ~n_grd && ga[3:0] == 4'h4)? gs_status :
(~n_giorq && ~n_grd && ga[3:0] == 4'h2)? gs_regb3 : (~n_giorq && ~n_grd && ga[3:0] == 4'h2)? gs_regb3 :
@ -262,25 +251,93 @@ assign gd =
{8{1'bz}} ; {8{1'bz}} ;
/* SOUNDRIVE */
wire port_xf = sd_ena && a[7] == 1'b0 && a[5] == 1'b0 && a[3:0] == 4'hF && !rom_m1_access;
wire [1:0] port_xf_chn = {a[6],a[4]};
reg sd_dac0_cs; always @(posedge clk32) sd_dac0_cs = ioreq && port_xf && port_xf_chn == 2'd0;
reg sd_dac1_cs; always @(posedge clk32) sd_dac1_cs = ioreq && port_xf && port_xf_chn == 2'd1;
reg sd_dac2_cs; always @(posedge clk32) sd_dac2_cs = ioreq && port_xf && port_xf_chn == 2'd2;
reg sd_dac3_cs; always @(posedge clk32) sd_dac3_cs = ioreq && port_xf && port_xf_chn == 2'd3;
wire sd_dac0_wr = sd_dac0_cs && ~n_wr;
wire sd_dac1_wr = sd_dac1_cs && ~n_wr;
wire sd_dac2_wr = sd_dac2_cs && ~n_wr;
wire sd_dac3_wr = sd_dac3_cs && ~n_wr;
/* DAC */
reg [5:0] vol0, vol1, vol2, vol3;
always @(posedge clk32 or negedge rst_n) begin
if (!rst_n) begin
vol0 <= 0;
vol1 <= 0;
vol2 <= 0;
vol3 <= 0;
end
else begin
if (sd_dac0_wr) vol0 <= 6'b111111;
else if (gs_vol0_wr) vol0 <= gd[5:0];
if (sd_dac1_wr) vol1 <= 6'b111111;
else if (gs_vol1_wr) vol1 <= gd[5:0];
if (sd_dac2_wr) vol2 <= 6'b111111;
else if (gs_vol2_wr) vol2 <= gd[5:0];
if (sd_dac3_wr) vol3 <= 6'b111111;
else if (gs_vol3_wr) vol3 <= gd[5:0];
end
end
reg [7:0] dac0, dac1, dac2, dac3;
always @(posedge clk32 or negedge rst_n) begin
if (!rst_n) begin
dac0 <= 0;
dac1 <= 0;
dac2 <= 0;
dac3 <= 0;
end
else begin
// quartus bug(?): without second condition inside "IF" expression incorrect design may be generated
if (sd_dac0_wr && !gs_dac0_wr) dac0 <= ( d[7]? d : { d[7], ~d[6:0]});
else if (gs_dac0_wr) dac0 <= (gd[7]? gd : {gd[7],~gd[6:0]});
if (sd_dac1_wr && !gs_dac1_wr) dac1 <= ( d[7]? d : { d[7], ~d[6:0]});
else if (gs_dac1_wr) dac1 <= (gd[7]? gd : {gd[7],~gd[6:0]});
if (sd_dac2_wr && !gs_dac2_wr) dac2 <= ( d[7]? d : { d[7], ~d[6:0]});
else if (gs_dac2_wr) dac2 <= (gd[7]? gd : {gd[7],~gd[6:0]});
if (sd_dac3_wr && !gs_dac3_wr) dac3 <= ( d[7]? d : { d[7], ~d[6:0]});
else if (gs_dac3_wr) dac3 <= (gd[7]? gd : {gd[7],~gd[6:0]});
end
end
reg vol0_en, vol1_en, vol2_en, vol3_en;
reg [5:0] vol_cnt;
reg [7:0] dac0_cnt, dac1_cnt, dac2_cnt, dac3_cnt;
assign dac0_out = dac0_cnt[7]? dac0[7] : clk32;
assign dac1_out = dac1_cnt[7]? dac1[7] : clk32;
assign dac2_out = dac2_cnt[7]? dac2[7] : clk32;
assign dac3_out = dac3_cnt[7]? dac3[7] : clk32;
always @(posedge clk32) begin
vol_cnt <= vol_cnt + 6'd31;
vol0_en <= (vol_cnt < vol0) || (&vol0);
vol1_en <= (vol_cnt < vol1) || (&vol1);
vol2_en <= (vol_cnt < vol2) || (&vol2);
vol3_en <= (vol_cnt < vol3) || (&vol3);
if (vol0_en) dac0_cnt <= dac0_cnt[6:0] + dac0[6:0]; else dac0_cnt[7] <= 0;
if (vol1_en) dac1_cnt <= dac1_cnt[6:0] + dac1[6:0]; else dac1_cnt[7] <= 0;
if (vol2_en) dac2_cnt <= dac2_cnt[6:0] + dac2[6:0]; else dac2_cnt[7] <= 0;
if (vol3_en) dac3_cnt <= dac3_cnt[6:0] + dac3[6:0]; else dac3_cnt[7] <= 0;
end
/* BUS CONTROLLER */ /* BUS CONTROLLER */
assign n_ard = n_rd | n_iorq0; assign n_ard = ~ioreq_rd;
assign n_awr = n_wr | n_iorq0; assign n_awr = ~ioreq_wr;
assign aa0 = a[1]? saa_a0 : ym_a0 ;
assign aa0 = n_iorq? aa0 : a[1]? saa_a0 : ym_a0 ; assign ad = ioreq_wr && (port_fffd || port_bffd || port_ff)? d : 8'bzzzzzzzz;
assign ad =
~n_awr && ~n_iorq0 && (port_fffd || port_bffd || port_ff)? d :
8'bzzzzzzzz;
assign n_wait = 1'bz; assign n_wait = 1'bz;
assign n_iorqge = (n_m1 && (port_fffd_full || port_bffd || port_b3 || port_bb || port_ff || port_xf))? 1'b0 : 1'b1;
assign n_iorqge = (n_m1 && (port_fffd_full || port_bffd || port_b3 || port_bb))? 1'b1 : 1'bz;
assign d = assign d =
~n_rd && ~n_iorq0 && port_fffd_full? ad : ioreq_rd && port_fffd? ad :
~n_rd && ~n_iorq0 && port_b3? gs_reg03 : ioreq_rd && port_b3? gs_reg03 :
~n_rd && ~n_iorq0 && port_bb? gs_status : ioreq_rd && port_bb? gs_status :
8'bzzzzzzzz; 8'bzzzzzzzz;

5
cpld/syn/Makefile
View File

@ -1,4 +1,5 @@
REVISION = zx_multisound REV = A
REVISION = rev_${REV}
.PHONY: build program clean .PHONY: build program clean
@ -12,7 +13,7 @@ clean:
rm -rf db incremental_db output rm -rf db incremental_db output
report: report:
cat output/${REVISION}.*.smsg output/${REVISION}.cmp.rpt |grep -e Error -e Critical -e Warning |grep -v -e "Family doesn't support jitter analysis" -e "Force Fitter to Avoid Periphery Placement Warnings" cat output/${REVISION}.*.smsg output/${REVISION}.*.rpt |grep -e Error -e Critical -e Warning |grep -v -e "Family doesn't support jitter analysis" -e "Force Fitter to Avoid Periphery Placement Warnings"
export PATH:=/opt/quartus13.0sp1/quartus/bin:/cygdrive/c/Hwdev/quartus130sp1/quartus/bin:${PATH} export PATH:=/opt/quartus13.0sp1/quartus/bin:/cygdrive/c/Hwdev/quartus130sp1/quartus/bin:${PATH}

2
cpld/syn/clocks.sdc
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@ -1,3 +1,5 @@
create_clock -period 32.1MHz -name {clk_32mhz} [get_ports {clk32}] create_clock -period 32.1MHz -name {clk_32mhz} [get_ports {clk32}]
create_generated_clock -name {gclk} -divide_by 2 -source [get_ports {clk32}] [get_registers {midi_clk_cnt[2]}] create_generated_clock -name {gclk} -divide_by 2 -source [get_ports {clk32}] [get_registers {midi_clk_cnt[2]}]
set_false_path -from [get_ports {cfg[*]}]

167
cpld/syn/rev_A.qsf Normal file
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@ -0,0 +1,167 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 12:04:27 October 04, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_multisound_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name DEVICE "EPM3256ATC144-10"
set_global_assignment -name TOP_LEVEL_ENTITY zx_multisound
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:04:27 OCTOBER 04, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE ../rtl/top.v
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_location_assignment PIN_1 -to n_gram2
set_location_assignment PIN_2 -to gma[17]
set_location_assignment PIN_5 -to gma[16]
set_location_assignment PIN_6 -to gma[18]
set_location_assignment PIN_7 -to n_gram1
set_location_assignment PIN_8 -to n_gm1
set_location_assignment PIN_9 -to n_grst
set_location_assignment PIN_10 -to ga[0]
set_location_assignment PIN_11 -to ga[1]
set_location_assignment PIN_12 -to ga[2]
set_location_assignment PIN_14 -to ga[3]
set_location_assignment PIN_15 -to ga[4]
set_location_assignment PIN_16 -to ga[5]
set_location_assignment PIN_18 -to ga[6]
set_location_assignment PIN_19 -to ga[7]
set_location_assignment PIN_21 -to ga[8]
set_location_assignment PIN_22 -to ga[9]
set_location_assignment PIN_23 -to ga[10]
set_location_assignment PIN_25 -to n_gwr
set_location_assignment PIN_27 -to n_grd
set_location_assignment PIN_28 -to n_giorq
set_location_assignment PIN_29 -to n_gmreq
set_location_assignment PIN_30 -to ga[11]
set_location_assignment PIN_31 -to ga[12]
set_location_assignment PIN_32 -to ga[13]
set_location_assignment PIN_34 -to ga[14]
set_location_assignment PIN_35 -to ga[15]
set_location_assignment PIN_36 -to n_gint
set_location_assignment PIN_37 -to gd[3]
set_location_assignment PIN_38 -to gd[5]
set_location_assignment PIN_39 -to gd[6]
set_location_assignment PIN_40 -to gd[4]
set_location_assignment PIN_41 -to gclk
set_location_assignment PIN_42 -to gd[2]
set_location_assignment PIN_43 -to gd[7]
set_location_assignment PIN_44 -to gd[0]
set_location_assignment PIN_45 -to gd[1]
set_location_assignment PIN_46 -to n_grom
set_location_assignment PIN_47 -to gma[15]
set_location_assignment PIN_48 -to cfg[0]
set_location_assignment PIN_49 -to cfg[1]
set_location_assignment PIN_53 -to cfg[2]
set_location_assignment PIN_54 -to cfg[3]
set_location_assignment PIN_55 -to cfg[4]
set_location_assignment PIN_60 -to dac3_out
set_location_assignment PIN_61 -to dac2_out
set_location_assignment PIN_62 -to dac1_out
set_location_assignment PIN_63 -to dac0_out
set_location_assignment PIN_74 -to fm1_ena
set_location_assignment PIN_75 -to ym_m
set_location_assignment PIN_78 -to aa0
set_location_assignment PIN_79 -to n_ard
set_location_assignment PIN_80 -to n_awr
set_location_assignment PIN_81 -to n_ym1_cs
set_location_assignment PIN_82 -to n_ym2_cs
set_location_assignment PIN_83 -to n_rstout
set_location_assignment PIN_84 -to fm2_ena
set_location_assignment PIN_86 -to ad[0]
set_location_assignment PIN_87 -to ad[1]
set_location_assignment PIN_88 -to ad[2]
set_location_assignment PIN_90 -to ad[3]
set_location_assignment PIN_91 -to ad[4]
set_location_assignment PIN_92 -to ad[5]
set_location_assignment PIN_93 -to ad[6]
set_location_assignment PIN_96 -to ad[7]
set_location_assignment PIN_97 -to n_saa_cs
set_location_assignment PIN_98 -to saa_clk
set_location_assignment PIN_99 -to midi_clk
set_location_assignment PIN_100 -to a[14]
set_location_assignment PIN_101 -to a[15]
set_location_assignment PIN_102 -to a[12]
set_location_assignment PIN_103 -to a[13]
set_location_assignment PIN_106 -to d[7]
set_location_assignment PIN_107 -to n_dos
set_location_assignment PIN_108 -to d[0]
set_location_assignment PIN_109 -to d[1]
set_location_assignment PIN_110 -to d[2]
set_location_assignment PIN_111 -to a[0]
set_location_assignment PIN_112 -to d[6]
set_location_assignment PIN_113 -to a[1]
set_location_assignment PIN_116 -to d[5]
set_location_assignment PIN_117 -to a[2]
set_location_assignment PIN_118 -to d[3]
set_location_assignment PIN_119 -to a[3]
set_location_assignment PIN_120 -to d[4]
set_location_assignment PIN_121 -to n_iorqge
set_location_assignment PIN_122 -to n_iorq
set_location_assignment PIN_125 -to clkx
set_location_assignment PIN_126 -to n_rd
set_location_assignment PIN_127 -to rst_n
set_location_assignment PIN_128 -to clk32
set_location_assignment PIN_131 -to n_wr
set_location_assignment PIN_132 -to n_iodos
set_location_assignment PIN_133 -to n_wait
set_location_assignment PIN_134 -to a[7]
set_location_assignment PIN_136 -to a[6]
set_location_assignment PIN_137 -to a[5]
set_location_assignment PIN_138 -to n_m1
set_location_assignment PIN_139 -to a[4]
set_location_assignment PIN_140 -to a[8]
set_location_assignment PIN_141 -to a[9]
set_location_assignment PIN_142 -to a[10]
set_location_assignment PIN_143 -to a[11]
set_location_assignment PIN_72 -to n_mreq
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

8
cpld/syn/zx_multisound.qpf
View File

@ -16,15 +16,15 @@
# #
# -------------------------------------------------------------------------- # # -------------------------------------------------------------------------- #
# #
# Quartus II 64-Bit # Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 12:04:27 October 04, 2020 # Date created = 11:12:50 November 18, 2022
# #
# -------------------------------------------------------------------------- # # -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0" QUARTUS_VERSION = "13.0"
DATE = "12:04:27 October 04, 2020" DATE = "11:12:50 November 18, 2022"
# Revisions # Revisions
PROJECT_REVISION = "zx_multisound" PROJECT_REVISION = "rev_A"

160
cpld/syn/zx_multisound.qsf
View File

@ -1,160 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 12:04:27 October 04, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_multisound_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name DEVICE "EPM3256ATC144-10"
set_global_assignment -name TOP_LEVEL_ENTITY zx_multisound
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:04:27 OCTOBER 04, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE ../rtl/top.v
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_location_assignment PIN_2 -to d[2]
set_location_assignment PIN_7 -to ad[1]
set_location_assignment PIN_8 -to ad[2]
set_location_assignment PIN_9 -to ad[3]
set_location_assignment PIN_10 -to ad[4]
set_location_assignment PIN_11 -to ad[5]
set_location_assignment PIN_12 -to ad[6]
set_location_assignment PIN_14 -to ad[7]
set_location_assignment PIN_15 -to n_saa_cs
set_location_assignment PIN_16 -to saa_clk
set_location_assignment PIN_19 -to n_ym2_cs
set_location_assignment PIN_18 -to n_ym1_cs
set_location_assignment PIN_21 -to n_awr
set_location_assignment PIN_22 -to n_ard
set_location_assignment PIN_23 -to aa0
set_location_assignment PIN_25 -to ym_m
set_location_assignment PIN_27 -to ad[0]
set_location_assignment PIN_28 -to fm2_ena
set_location_assignment PIN_29 -to fm1_ena
set_location_assignment PIN_35 -to midi_clk
set_location_assignment PIN_36 -to gdac3
set_location_assignment PIN_37 -to gdac2
set_location_assignment PIN_38 -to gdac1
set_location_assignment PIN_39 -to gdac0
set_location_assignment PIN_40 -to ga[11]
set_location_assignment PIN_41 -to gclk
set_location_assignment PIN_67 -to ga[1]
set_location_assignment PIN_42 -to ga[12]
set_location_assignment PIN_43 -to ga[13]
set_location_assignment PIN_44 -to ga[14]
set_location_assignment PIN_45 -to ga[15]
set_location_assignment PIN_46 -to ga[10]
set_location_assignment PIN_47 -to ga[9]
set_location_assignment PIN_48 -to ga[8]
set_location_assignment PIN_49 -to n_gint
set_location_assignment PIN_53 -to ga[7]
set_location_assignment PIN_54 -to n_gmreq
set_location_assignment PIN_55 -to ga[6]
set_location_assignment PIN_56 -to n_giorq
set_location_assignment PIN_60 -to ga[5]
set_location_assignment PIN_61 -to n_grst
set_location_assignment PIN_62 -to ga[4]
set_location_assignment PIN_63 -to n_gm1
set_location_assignment PIN_65 -to ga[3]
set_location_assignment PIN_66 -to ga[2]
set_location_assignment PIN_68 -to ga[0]
set_location_assignment PIN_69 -to gma[16]
set_location_assignment PIN_70 -to gma[17]
set_location_assignment PIN_71 -to gd[0]
set_location_assignment PIN_72 -to gd[7]
set_location_assignment PIN_74 -to gd[6]
set_location_assignment PIN_75 -to gd[1]
set_location_assignment PIN_78 -to gd[5]
set_location_assignment PIN_79 -to gd[2]
set_location_assignment PIN_80 -to gd[3]
set_location_assignment PIN_81 -to gd[4]
set_location_assignment PIN_82 -to n_grd
set_location_assignment PIN_83 -to n_gram
set_location_assignment PIN_84 -to n_gwr
set_location_assignment PIN_86 -to gma[18]
set_location_assignment PIN_87 -to gma[15]
set_location_assignment PIN_88 -to n_grom
set_location_assignment PIN_90 -to cfg[0]
set_location_assignment PIN_91 -to cfg[1]
set_location_assignment PIN_92 -to cfg[2]
set_location_assignment PIN_98 -to a[8]
set_location_assignment PIN_99 -to n_wait
set_location_assignment PIN_100 -to a[12]
set_location_assignment PIN_101 -to a[9]
set_location_assignment PIN_102 -to a[11]
set_location_assignment PIN_103 -to a[10]
set_location_assignment PIN_107 -to n_iorq
set_location_assignment PIN_108 -to d[7]
set_location_assignment PIN_109 -to n_wr
set_location_assignment PIN_110 -to d[6]
set_location_assignment PIN_111 -to n_rd
set_location_assignment PIN_112 -to d[5]
set_location_assignment PIN_113 -to n_iorqge
set_location_assignment PIN_116 -to a[13]
set_location_assignment PIN_117 -to d[4]
set_location_assignment PIN_118 -to d[3]
set_location_assignment PIN_119 -to a[15]
set_location_assignment PIN_120 -to a[14]
set_location_assignment PIN_121 -to n_m1
set_location_assignment PIN_132 -to a[7]
set_location_assignment PIN_133 -to a[6]
set_location_assignment PIN_134 -to a[4]
set_location_assignment PIN_136 -to a[3]
set_location_assignment PIN_137 -to a[2]
set_location_assignment PIN_138 -to a[1]
set_location_assignment PIN_139 -to a[0]
set_location_assignment PIN_140 -to a[5]
set_location_assignment PIN_141 -to d[0]
set_location_assignment PIN_142 -to d[1]
set_location_assignment PIN_128 -to clk32
set_location_assignment PIN_127 -to rst_n
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name SYNTHESIS_SEED 1
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
set_location_assignment PIN_125 -to clkx