Analysis & Synthesis report for OrionCOM-AY
Fri Feb  5 16:21:22 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Registers Removed During Synthesis
  9. Parameter Settings for Inferred Entity Instance: AyClkDiv:ayClkDiv|lpm_add_sub:Add0
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Feb  5 16:21:22 2021           ;
; Quartus II 32-bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name               ; OrionCOM-AY                                     ;
; Top-level Entity Name       ; OrionCOM_AY                                     ;
; Family                      ; MAX7000S                                        ;
; Total macrocells            ; 22                                              ;
; Total pins                  ; 31                                              ;
+-----------------------------+-------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                               ;
+----------------------------------------------------------------------------+----------------+---------------+
; Option                                                                     ; Setting        ; Default Value ;
+----------------------------------------------------------------------------+----------------+---------------+
; Device                                                                     ; EPM7064STC44-7 ;               ;
; Top-level entity name                                                      ; OrionCOM_AY    ; OrionCOM-AY   ;
; Family name                                                                ; MAX7000S       ; Cyclone IV GX ;
; Use smart compilation                                                      ; Off            ; Off           ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On             ; On            ;
; Enable compact report table                                                ; Off            ; Off           ;
; Create Debugging Nodes for IP Cores                                        ; Off            ; Off           ;
; Preserve fewer node names                                                  ; On             ; On            ;
; Disable OpenCore Plus hardware evaluation                                  ; Off            ; Off           ;
; Verilog Version                                                            ; Verilog_2001   ; Verilog_2001  ;
; VHDL Version                                                               ; VHDL_1993      ; VHDL_1993     ;
; State Machine Processing                                                   ; Auto           ; Auto          ;
; Safe State Machine                                                         ; Off            ; Off           ;
; Extract Verilog State Machines                                             ; On             ; On            ;
; Extract VHDL State Machines                                                ; On             ; On            ;
; Ignore Verilog initial constructs                                          ; Off            ; Off           ;
; Iteration limit for constant Verilog loops                                 ; 5000           ; 5000          ;
; Iteration limit for non-constant Verilog loops                             ; 250            ; 250           ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On             ; On            ;
; Infer RAMs from Raw Logic                                                  ; On             ; On            ;
; Parallel Synthesis                                                         ; On             ; On            ;
; NOT Gate Push-Back                                                         ; On             ; On            ;
; Power-Up Don't Care                                                        ; On             ; On            ;
; Remove Duplicate Registers                                                 ; On             ; On            ;
; Ignore CARRY Buffers                                                       ; Off            ; Off           ;
; Ignore CASCADE Buffers                                                     ; Off            ; Off           ;
; Ignore GLOBAL Buffers                                                      ; Off            ; Off           ;
; Ignore ROW GLOBAL Buffers                                                  ; Off            ; Off           ;
; Ignore LCELL Buffers                                                       ; Auto           ; Auto          ;
; Ignore SOFT Buffers                                                        ; Off            ; Off           ;
; Limit AHDL Integers to 32 Bits                                             ; Off            ; Off           ;
; Optimization Technique                                                     ; Speed          ; Speed         ;
; Allow XOR Gate Usage                                                       ; On             ; On            ;
; Auto Logic Cell Insertion                                                  ; On             ; On            ;
; Parallel Expander Chain Length                                             ; 4              ; 4             ;
; Auto Parallel Expanders                                                    ; On             ; On            ;
; Auto Open-Drain Pins                                                       ; On             ; On            ;
; Auto Resource Sharing                                                      ; Off            ; Off           ;
; Maximum Fan-in Per Macrocell                                               ; 100            ; 100           ;
; Use LogicLock Constraints during Resource Balancing                        ; On             ; On            ;
; Ignore translate_off and synthesis_off directives                          ; Off            ; Off           ;
; Report Parameter Settings                                                  ; On             ; On            ;
; Report Source Assignments                                                  ; On             ; On            ;
; Report Connectivity Checks                                                 ; On             ; On            ;
; HDL message level                                                          ; Level2         ; Level2        ;
; Suppress Register Optimization Related Messages                            ; Off            ; Off           ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000           ; 5000          ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000           ; 5000          ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100            ; 100           ;
; Block Design Naming                                                        ; Auto           ; Auto          ;
; Synthesis Effort                                                           ; Auto           ; Auto          ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On             ; On            ;
; Pre-Mapping Resynthesis Optimization                                       ; Off            ; Off           ;
; Analysis & Synthesis Message Level                                         ; Medium         ; Medium        ;
; Disable Register Merging Across Hierarchies                                ; Auto           ; Auto          ;
; Synthesis Seed                                                             ; 1              ; 1             ;
+----------------------------------------------------------------------------+----------------+---------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                             ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                         ; Library ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------+---------+
; OrionCOM_AY.sv                   ; yes             ; User SystemVerilog HDL File  ; /opt/cpld/OrionCOM-AY/OrionCOM_AY.sv                                                 ;         ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;         ;
; addcore.inc                      ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.inc             ;         ;
; look_add.inc                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/look_add.inc            ;         ;
; bypassff.inc                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/bypassff.inc            ;         ;
; altshift.inc                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/altshift.inc            ;         ;
; alt_stratix_add_sub.inc          ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;         ;
; aglobal130.inc                   ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/aglobal130.inc          ;         ;
; addcore.tdf                      ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.tdf             ;         ;
; a_csnbuffer.inc                  ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/a_csnbuffer.inc         ;         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/a_csnbuffer.tdf         ;         ;
; look_add.tdf                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/look_add.tdf            ;         ;
; altshift.tdf                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/altshift.tdf            ;         ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 22                   ;
; Total registers      ; 11                   ;
; I/O pins             ; 31                   ;
; Parallel expanders   ; 1                    ;
; Maximum fan-out node ; reset_n              ;
; Maximum fan-out      ; 12                   ;
; Total fan-out        ; 144                  ;
; Average fan-out      ; 2.72                 ;
+----------------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+---------------------------------------+------------+------+------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node            ; Macrocells ; Pins ; Full Hierarchy Name                                                                      ; Library Name ;
+---------------------------------------+------------+------+------------------------------------------------------------------------------------------+--------------+
; |OrionCOM_AY                          ; 22         ; 31   ; |OrionCOM_AY                                                                             ; work         ;
;    |AyClkDiv:ayClkDiv|                ; 11         ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv                                                           ; work         ;
;       |lpm_add_sub:Add0|              ; 1          ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0                                          ; work         ;
;          |addcore:adder[1]|           ; 1          ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]                         ; work         ;
;             |a_csnbuffer:result_node| ; 1          ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node ; work         ;
;    |ViClkDiv:viClkDiv|                ; 2          ; 0    ; |OrionCOM_AY|ViClkDiv:viClkDiv                                                           ; work         ;
+---------------------------------------+------------+------+------------------------------------------------------------------------------------------+--------------+


+-------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                            ;
+---------------------------------------+---------------------------------------+
; Register name                         ; Reason for Removal                    ;
+---------------------------------------+---------------------------------------+
; AyClkDiv:ayClkDiv|sum[0]              ; Merged with ViClkDiv:viClkDiv|div1[0] ;
; Total Number of Removed Registers = 1 ;                                       ;
+---------------------------------------+---------------------------------------+


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: AyClkDiv:ayClkDiv|lpm_add_sub:Add0 ;
+------------------------+-------------+----------------------------------------------+
; Parameter Name         ; Value       ; Type                                         ;
+------------------------+-------------+----------------------------------------------+
; LPM_WIDTH              ; 10          ; Untyped                                      ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                      ;
; LPM_DIRECTION          ; ADD         ; Untyped                                      ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                      ;
; LPM_PIPELINE           ; 0           ; Untyped                                      ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                      ;
; REGISTERED_AT_END      ; 0           ; Untyped                                      ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                      ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                      ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                      ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                           ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                                      ;
; USE_WYS                ; OFF         ; Untyped                                      ;
; STYLE                  ; FAST        ; Untyped                                      ;
; CBXI_PARAMETER         ; add_sub_4ph ; Untyped                                      ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                               ;
+------------------------+-------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Feb  5 16:21:19 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off OrionCOM-AY -c OrionCOM-AY
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 3 design units, including 3 entities, in source file OrionCOM_AY.sv
    Info (12023): Found entity 1: OrionCOM_AY
    Info (12023): Found entity 2: ViClkDiv
    Info (12023): Found entity 3: AyClkDiv
Info (12127): Elaborating entity "OrionCOM_AY" for the top level hierarchy
Info (12128): Elaborating entity "AyClkDiv" for hierarchy "AyClkDiv:ayClkDiv"
Info (12128): Elaborating entity "ViClkDiv" for hierarchy "ViClkDiv:viClkDiv"
Info (278001): Inferred 1 megafunctions from design logic
    Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "AyClkDiv:ayClkDiv|Add0"
Info (12130): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
Info (12133): Instantiated megafunction "AyClkDiv:ayClkDiv|lpm_add_sub:Add0" with the following parameter:
    Info (12134): Parameter "LPM_WIDTH" = "10"
    Info (12134): Parameter "LPM_DIRECTION" = "ADD"
    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[0]", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
Info (13014): Ignored 12 buffer(s)
    Info (13019): Ignored 12 SOFT buffer(s)
Info (280013): Promoted pin-driven signal(s) to global signal
    Info (280014): Promoted clock signal driven by pin "clk" to global clock signal
    Info (280015): Promoted clear signal driven by pin "reset_n" to global clear signal
Info (21057): Implemented 53 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 19 input pins
    Info (21059): Implemented 12 output pins
    Info (21063): Implemented 22 macrocells
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 335 megabytes
    Info: Processing ended: Fri Feb  5 16:21:22 2021
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:01


