 -- Copyright (C) 1991-2013 Altera Corporation
 -- Your use of Altera Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic 
 -- functions, and any output files from any of the foregoing 
 -- (including device programming or simulation files), and any 
 -- associated documentation or information are expressly subject 
 -- to the terms and conditions of the Altera Program License 
 -- Subscription Agreement, Altera MegaCore Function License 
 -- Agreement, or other applicable license agreement, including, 
 -- without limitation, that your use is for the sole purpose of 
 -- programming logic devices manufactured by Altera and sold by 
 -- Altera or its authorized distributors.  Please refer to the 
 -- applicable agreement for further details.
 -- 
 -- This is a Quartus II output file. It is for reporting purposes only, and is
 -- not intended for use as a Quartus II input file. This file cannot be used
 -- to make Quartus II pin assignments - for instructions on how to make pin
 -- assignments, please see Quartus II help.
 ---------------------------------------------------------------------------------



 ---------------------------------------------------------------------------------
 -- NC            : No Connect. This pin has no internal connection to the device.
 -- DNU           : Do Not Use. This pin MUST NOT be connected.
 -- VCC           : Dedicated power pin, which MUST be connected to VCC.
 -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
 --                 of its bank.
 -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
 --					It can also be used to report unused dedicated pins. The connection
 --					on the board for unused dedicated pins depends on whether this will
 --					be used in a future design. One example is device migration. When
 --					using device migration, refer to the device pin-tables. If it is a
 --					GND pin in the pin table or if it will not be used in a future design
 --					for another purpose the it MUST be connected to GND. If it is an unused
 --					dedicated pin, then it can be connected to a valid signal on the board
 --					(low, high, or toggling) if that signal is required for a different
 --					revision of the design.
 -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
 --					This pin should be connected to GND. It may also be connected  to a
 --					valid signal  on the board  (low, high, or toggling)  if that signal
 --					is required for a different revision of the design.
 -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
 --           	    or leave it unconnected.
 -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
 -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
 -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
 -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
 -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
 -- NON_MIGRATABLE: This pin cannot be migrated.
 ---------------------------------------------------------------------------------



 ---------------------------------------------------------------------------------
 -- Pin directions (input, output or bidir) are based on device operating in user mode.
 ---------------------------------------------------------------------------------

Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
CHIP  "OrionCOM-AY"  ASSIGNED TO AN: EPM7064STC44-7

Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
-------------------------------------------------------------------------------------------------------------
TDI                          : 1         : input  : TTL               :         :           : Y              
a[0]                         : 2         : input  : TTL               :         :           : Y              
a[1]                         : 3         : input  : TTL               :         :           : Y              
GND                          : 4         : gnd    :                   :         :           :                
a[2]                         : 5         : input  : TTL               :         :           : Y              
a[3]                         : 6         : input  : TTL               :         :           : Y              
TMS                          : 7         : input  : TTL               :         :           : Y              
a[4]                         : 8         : input  : TTL               :         :           : Y              
VCC                          : 9         : power  :                   :         :           :                
a[5]                         : 10        : input  : TTL               :         :           : Y              
a[6]                         : 11        : input  : TTL               :         :           : Y              
a[7]                         : 12        : input  : TTL               :         :           : Y              
irq4                         : 13        : output : TTL               :         :           : Y              
irq3                         : 14        : output : TTL               :         :           : Y              
a[8]                         : 15        : input  : TTL               :         :           : Y              
GND                          : 16        : gnd    :                   :         :           :                
VCC                          : 17        : power  :                   :         :           :                
a[9]                         : 18        : input  : TTL               :         :           : Y              
rd_n                         : 19        : input  : TTL               :         :           : Y              
wr_n                         : 20        : input  : TTL               :         :           : Y              
iorq_n                       : 21        : input  : TTL               :         :           : Y              
wait_n                       : 22        : input  : TTL               :         :           : Y              
m1_n                         : 23        : input  : TTL               :         :           : Y              
GND                          : 24        : gnd    :                   :         :           :                
cs_vi_n                      : 25        : output : TTL               :         :           : Y              
TCK                          : 26        : input  : TTL               :         :           : Y              
clk1                         : 27        : output : TTL               :         :           : Y              
w1                           : 28        : output : TTL               :         :           : Y              
VCC                          : 29        : power  :                   :         :           :                
cs_vv2_n                     : 30        : output : TTL               :         :           : Y              
rdy2                         : 31        : input  : TTL               :         :           : Y              
TDO                          : 32        : output : TTL               :         :           : Y              
debug                        : 33        : output : TTL               :         :           : Y              
reset                        : 34        : output : TTL               :         :           : Y              
cs_vv1_n                     : 35        : output : TTL               :         :           : Y              
GND                          : 36        : gnd    :                   :         :           :                
clk                          : 37        : input  : TTL               :         :           : Y              
rdy1                         : 38        : input  : TTL               :         :           : Y              
reset_n                      : 39        : input  : TTL               :         :           : Y              
GND+                         : 40        :        :                   :         :           :                
VCC                          : 41        : power  :                   :         :           :                
bc1                          : 42        : output : TTL               :         :           : Y              
bdir                         : 43        : output : TTL               :         :           : Y              
clk2                         : 44        : output : TTL               :         :           : Y              
