diff --git a/EasyEDA/1-Schematic_OProCOM-AY.json b/EasyEDA/1-Schematic_OProCOM-AY.json
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@@ -0,0 +1 @@
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\ No newline at end of file
diff --git a/EasyEDA/2-PCB_PCB_COMPACT_v1.json b/EasyEDA/2-PCB_PCB_COMPACT_v1.json
new file mode 100644
index 0000000..8beed2b
--- /dev/null
+++ b/EasyEDA/2-PCB_PCB_COMPACT_v1.json
@@ -0,0 +1 @@
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3545.5~gge7682~0","TRACK~1.5748~2~D2_9~4038 3555.5 4028.698 3555.5~gge7683~0","TRACK~1.5748~2~D2_10~4038 3565.5 4028.698 3565.5~gge7684~0","TRACK~1.5748~2~D2_12~4038 3585.5 4028.698 3585.5~gge7686~0","TRACK~1.5748~2~D2_13~4038 3595.5 4028.698 3595.5~gge7687~0","TRACK~1.5748~2~D2_14~4038 3605.5 4028.698 3605.5~gge7688~0","TRACK~3.937~2~VCC~4100.2 3565.5 4079 3565.5 4060 3546.5 4060 3511.5 4044 3495.5 4037.8 3495.5~gge7293~0","TRACK~1.1811~2~BC1~4110.5 3601 4110.5 3562 4104 3555.5 4100.2002 3555.5~gge3883~0","TRACK~1.5748~2~D2_11~4038 3575.5 4028.698 3575.5~gge7685~0","TRACK~3.937~2~VCC~4118.5024 3585.5 4115 3585.5~gge9413~0","TRACK~3.937~2~VCC~4173.5 3637 4173.5 3629 4169.5 3625 4161.5 3625 4122 3585.5 4118.5024 3585.5~gge9282~0","TRACK~1.1811~2~-WR~4266.5 3710 4250.5 3710 4240 3720.5 4240 3724.5~gge4018~0","TRACK~1.1811~2~-RD~4230 3724.5 4230 3720.5 4244 3706.5 4316 3706.5 4330 3692.5 4330 3685.5~gge3364~0","TRACK~1.1811~2~A0~4300 3685.5 4300 3689.5 4296 3693.5 4236 3693.5 4234 3691.5 4163.5 3691.5 4157.5 3685.5 4073 3685.5~gge3632~0","TRACK~1.1811~2~A1~4310 3685.5 4310 3689.5 4302.5 3697 4234.5 3697 4232 3694.5 4162 3694.5 4157 3689.5 4080 3689.5~gge3634~0","TRACK~3.937~2~VCC~4118.5 3609.5 4118.6024 3609.3976 4118.6024 3585.5~gge9409~0","TRACK~1.1811~2~RDY2~4275 3640 4246.5 3668.5 4217 3668.5 4212.5 3673 4172 3673 4167.5 3668.5 4167.5 3654.5 4163.5 3650.5 4155 3650.5 4153 3648.5 4153 3639.5~gge8715~0","TRACK~1.1811~2~-CS_VV2~4244.5 3636 4231 3636 4228.5 3633.5 4217 3633.5 4207.5 3643 4170 3643 4163.5 3636.5~gge3923~0","TRACK~1.1811~2~CLK1~4270 3625.5 4270 3630.5 4255 3645.5 4212.5 3645.5 4196.5 3661.5 4173.5 3661.5~gge3510~0","TRACK~1.1811~2~TCK~4049.5 3675.5 4054.5 3675.5 4058.5 3679.5 4071.5 3679.5 4087 3664 4112.5 3664 4119.5 3657 4138 3657~gge2639~0","TRACK~1.1811~10~~4020 3405.5 4413 3405.5 4413 3755.5 4020 3755.5 4020 3405.5~gge2410~0","TRACK~3.937~1~VCC~4330 3477.1581 4329.8419 3477 4320 3477~gge10161~0","TRACK~1.1811~1~RXD1~4310 3457 4320 3457~gge10163~0","TRACK~1.1811~1~RXD1~4170 3492.2 4170.02 3486.85 4200.15 3457 4310 3457~gge5713~0","TRACK~3.937~1~VCC~4170 3429.8 4170 3422 4174 3418 4321 3418 4330 3427 4330 3491.2 4324 3497.2 4324 3594 4335.5 3605.5 4337.5 3605.5~gge5703~0","TRACK~3.937~1~VCC~4324 3497.1955 4323.8045 3497 4300 3497~gge8665~0","TRACK~1.5748~1~F1.8~4193.3301 3662.98 4220.52 3662.98 4223 3660.5~gge7783~0","TRACK~1.5748~1~VCC~4116.95 3659.95 4117.25 3659.1565 4117.25 3627.15~gge3760~0","TRACK~1.5748~1~VCC~4123.55 3666.55 4123.55 3659.95 4136.15 3647.35 4146.8 3647.35~gge2835~0","TRACK~1.1811~1~DEBUG~4146.7998 3634.75 4152.75 3634.75 4156.5 3631~gge8378~0","TRACK~1.1811~1~RXD2~4286 3610 4286 3586.5~gge4226~0","TRACK~1.1811~1~RES0~4123.5 3652.5 4123.5 3627.1997 4123.5498 3627.1499~gge3507~0","TRACK~1.1811~1~RES0~4225 3698 4194 3698 4161 3665~gge3503~0","TRACK~1.1811~1~OUT3~4280 3671.5 4280 3685.5~gge3362~0","TRACK~1.1811~1~R10_1~4250 3685.5 4250 3625.5~gge3357~0","TRACK~1.1811~1~D5~4330 3734.5 4325 3729.5 4325 3650.5 4330 3645.5 4330 3625.5~gge3328~0","TRACK~1.1811~1~F10~4130 3634.5 4129.85 3634.35 4129.85 3627.15~gge2653~0","TRACK~1.1811~1~TCK~4138 3657 4138.2 3656.8 4146.7998 3656.8~gge2641~0","TRACK~1.1811~1~TDO~4138 3638 4138.1001 3637.8999 4146.7998 3637.8999~gge2638~0","TRACK~1.5748~1~VCC~4100.2 3659.95 4093.5 3659.95~gge2628~0","TRACK~1.1811~1~TMS~4100.2 3653.65 4093 3653.65~gge2620~0","TRACK~1.1811~1~A6~4100.2 3666.25 4100.2 3696.2 4125 3721 4125 3729.5 4120 3734.5~gge2617~0","TRACK~1.1811~1~A3~4100.2 3650.5 4091 3650.5 4088 3653.5 4088 3714 4095 3721 4095 3729.5 4090 3734.5~gge2614~0","TRACK~3.937~1~VCC~4073.5 3625 4073.5 3570.5 4078.5 3565.5 4097.7002 3565.5~gge4795~0","TRACK~1.5748~1~VCC~4100.2 3659.95 4116.95 3659.95 4123.5 3660 4123.55 3673.85~gge2834~0","TRACK~1.5748~1~VCC~4117.25 3627.1499 4117.25 3619.75 4118.5 3618.5 4118.5 3609.5~gge4798~0","TRACK~1.1811~1~D4~4320 3734.5 4314.5 3729 4314.5 3651 4320 3645.5 4320 3625.5~gge3327~0","TRACK~1.1811~1~D3~4310 3734.5 4305 3729.5 4305 3650.5 4310 3645.5 4310 3625.5~gge3326~0","TRACK~1.1811~1~D1~4290 3734.5 4285 3729.5 4285 3650.5 4290 3645.5 4290 3625.5~gge3323~0","TRACK~1.1811~1~D0~4280 3734.5 4275 3729.5 4275 3650.5 4280 3645.5 4280 3625.5~gge3322~0","TRACK~1.1811~1~D2~4300 3734.5 4295 3729.5 4295 3650.5 4300 3645.5 4300 3625.5~gge3325~0","TRACK~1.1811~1~D6~4340 3734.5 4335 3729.5 4335 3650.5 4340 3645.5 4340 3625.5~gge3329~0","TRACK~3.937~1~VCC~4375.5 3695.5 4360 3695.5 4350 3685.5~gge4658~0","TRACK~3.937~1~VCC~4360 3695.5 4340 3715.5 4340 3724.5~gge5984~0","TRACK~1.1811~1~R10_1~4250 3685.5 4250 3690.5 4252 3692.5 4268 3692.5 4270 3690.5 4270 3685.5~gge3363~0","TRACK~1.1811~1~IRQ4A~4110.95 3673.85 4110.95 3684.95 4123 3697 4127.5 3697~gge2828~0","TRACK~1.1811~1~IRQ3A~4142 3697 4137 3692 4123.5 3692 4114.1 3682.6 4114.1 3673.85~gge2829~0","TRACK~1.1811~1~IRQ3~4140 3724.5 4140 3717.5 4142 3715.5 4142 3707~gge2655~0","TRACK~1.1811~1~A7~4107.8 3673.85 4107.8 3696.8 4126.5 3715.5 4130 3715.5 4135 3720.5 4135 3729.5 4130 3734.5~gge3340~0","TRACK~1.1811~1~A5~4110 3734.5 4115 3729.5 4115 3720.5 4094 3699.5 4094 3664.5 4095.4 3663.1 4100.2 3663.1~gge2618~0","TRACK~1.1811~1~A4~4100.2 3656.8 4092.2 3656.8 4091 3658 4091 3706.5 4105 3720.5 4105 3729.5 4100 3734.5~gge2616~0","TRACK~1.1811~1~A2~4100.2 3647.35 4089.15 3647.35 4085 3651.5 4085 3729.5 4080 3734.5~gge2613~0","TRACK~1.1811~1~TCK~4067 3688 4054.5 3675.5 4049.5 3675.5~gge2632~0","TRACK~1.5748~1~VCC~4067 3673.5 4064 3670.5 4044.5 3670.5 4039.5 3665.5~gge4793~0","TRACK~1.1811~1~BC1~4114.1001 3627.1499 4114.1001 3617.6001 4110.5 3614 4110.5 3601~gge3881~0","TRACK~1.1811~1~TDI~4100.2 3634.75 4093.5 3634.75 4093.5 3625~gge5949~0","TRACK~1.1811~1~TDI~4093.5 3634.75 4079.7825 3634.7188 4079.0012 3635.5 4049.5 3635.5~gge7295~0","TRACK~1.1811~1~F10~4070 3724.5 4070 3720 4076.5 3713.5 4076.5 3648.5 4081 3644~gge2649~0","TRACK~1.1811~1~A0~4100.2 3637.9 4082.6 3637.9 4073 3647.5 4073 3711 4065 3719 4065 3729.5 4060 3734.5~gge2611~0","TRACK~3.937~1~VCC~4039.5 3665.5 4032 3665.5 4032 3631 4038 3625 4073.5 3625~gge4794~0","TRACK~3.937~1~VCC~4039.5 3665.5 4032 3665.5 4032 3696.5 4039.5 3704~gge5943~0","TRACK~1.1811~1~A1~4100.2 3641 4088.5 3641 4080 3649.5 4080 3716 4075 3721 4075 3729.5 4070 3734.5~gge2612~0","TRACK~3.937~1~VCC~4375.5 3695.5 4375.5 3623.47 4380.97 3618.05 4381 3611~gge4659~0","TRACK~1.1811~1~C3_1~4340 3497 4359.563 3477.437 4359.999 3477.437~gge8657~0","TRACK~1.1811~1~C3_2~4340 3477 4347.437 3469.563 4359.999 3469.563~gge8658~0","TRACK~1.1811~1~C4_1~4340 3467 4350.563 3456.437 4360 3456.437~gge8659~0","TRACK~1.1811~1~C4_2~4340 3457 4348.437 3448.563 4360 3448.563~gge8660~0","TRACK~1.1811~1~C8_2~4340 3447 4352.563 3434.437 4360 3434.437~gge8661~0","TRACK~3.937~1~VCC~4324 3505.5955 4352.8405 3505.5955 4360 3498.436~gge8663~0","TRACK~1.1811~1~C10_2~4340 3544 4352.063 3531.937 4360 3531.937~gge8672~0","TRACK~1.1811~1~C6_2~4340 3554 4348.437 3545.563 4360 3545.563~gge8673~0","TRACK~1.1811~1~C6_1~4340 3564 4350.563 3553.437 4360 3553.437~gge8674~0","TRACK~1.1811~1~C5_2~4340 3574 4346.437 3567.563 4360 3567.563~gge8675~0","TRACK~1.1811~1~C5_1~4340 3594 4358.563 3575.437 4360 3575.437~gge8676~0","TRACK~3.937~1~VCC~4337.5 3605.5 4360 3605.5 4365.5 3611 4381 3611~gge4655~0","TRACK~3.937~1~VCC~4360 3605.5 4360 3596.937~gge8677~0","TRACK~3.937~1~VCC~4324 3594 4310 3594~gge8678~0","TRACK~3.937~1~VCC~4310 3594 4300 3594~gge8680~0","TRACK~1.1811~1~D1~4155 3605 4155 3540.5 4150 3535.5 4150 3527.3~gge3351~0","TRACK~1.1811~1~D0~4155 3610 4165 3600 4165 3540.5 4160 3535.5 4160 3527.3~gge3354~0","TRACK~1.1811~1~TXD2~4240 3527.3 4240 3531.5 4252.5 3544 4310 3544~gge4221~0","TRACK~1.1811~1~CTS2~4310 3524 4300.5 3524 4297 3520.5 4263 3520.5 4260 3523.5 4260 3527.3~gge4219~0","TRACK~1.1811~1~RTS2~4200 3527.3 4211.3 3516 4313 3516 4316.5 3519.5 4316.5 3531.5 4314 3534 4310 3534~gge8702~0","TRACK~1.1811~1~D3~4115 3505.5 4122 3498.5 4157.5 3498.5 4160 3496 4160 3492.2~gge3913~0","TRACK~1.1811~1~D4~4120 3515.5 4133.5 3502 4185 3502 4190 3497 4190 3492.2~gge3914~0","TRACK~1.1811~1~D5~4125 3518 4137.5 3505.5 4191.5 3505.5 4200 3497 4200 3492.2~gge3916~0","TRACK~1.1811~1~-CS_VV2~4250 3589.7 4250 3602 4244.5 3607.5 4244.5 3636~gge3922~0","TRACK~1.1811~1~D7~4220 3589.7 4220 3580.5 4215.5 3576 4215.5 3537.5~gge3919~0","TRACK~1.1811~1~D5_9~4230 3589.698 4230 3572 4223.5 3565.5 4223.5 3546~gge8707~0","TRACK~1.1811~1~-WR~4240 3563.5 4240 3589.698~gge8711~0","TRACK~1.1811~1~CLK1~4270 3625.5 4270 3619.5 4265 3614.5 4265 3565.5 4230 3530.5 4230 3527.3~gge4223~0","TRACK~1.1811~1~CLK_VV~4255 3650 4255 3561.5 4233.5 3540 4225 3540~gge7787~0","TRACK~1.1811~1~RDY2~4280 3589.698 4275 3594.698 4275 3640~gge4105~0","TRACK~1.1811~1~RDY2~4146.7998 3641.05 4151.45 3641.05 4153 3639.5~gge8721~0","TRACK~1.1811~1~A0~4300 3685.5 4300 3650 4304.5 3645.5 4304.5 3622.5 4290 3608 4290 3596.5~gge4014~0","TRACK~1.1811~1~-RD~4330 3685.5 4330 3651 4335.5 3645.5 4335.5 3623 4315.5 3603 4298.5 3603 4294 3598.5 4294 3585 4287 3578 4272.5 3578 4270 3580.5 4270 3589.7~gge4011~0","TRACK~1.5748~1~VCC~4040.5 3495.5 4035.3 3495.5~gge4814~0","TRACK~3.937~1~VCC~4127.5 3450.5 4127.5 3432.5 4142 3418 4165 3418 4169 3422 4170 3422~gge8768~0","TRACK~1.1811~1~D6~4130 3535.5 4130 3521.5 4142.5 3509 4196 3509 4210 3495 4210 3492.2~gge3918~0","TRACK~1.1811~1~RES1~4220 3527.3 4220 3572 4225 3577 4225 3594 4216.5 3602.5 4179.5 3602.5 4157.83 3624.17 4145.33 3624.17 4142.35 3627.15 4139.3 3627.15~gge4125~0","TRACK~1.1811~1~-CS_VV1~4250 3492.2 4250 3500 4239 3511 4207.5 3511 4195 3523.5 4195 3593.5 4191 3597.5 4178.5 3597.5 4157 3619 4140 3619 4136.15 3622.85 4136.15 3627.15~gge4206~0","TRACK~1.1811~1~RDY1~4126.7 3627.15 4126.7 3622.8 4134 3615.5 4154.5 3615.5 4175 3595 4175 3584.5 4185 3574.5 4185 3522.5 4188 3519.5 4192 3519.5 4215.5 3496 4215.5 3488 4218.5 3485 4277.5 3485 4280 3487.5 4280 3492.2~gge8379~0","TRACK~1.1811~1~CLK1~4270 3625.5 4270 3645.5 4260 3655.5 4260 3685.5~gge3355~0","TRACK~1.1811~1~CLK2~4107.8 3627.15 4100.2 3619.55 4100.2 3605.5~gge3877~0","TRACK~1.1811~1~RES0~4123.5498 3627.1499 4123.5498 3602.55 4116.4998 3595.5 4100.2 3595.5~gge3880~0","TRACK~1.1811~1~BDIR~4110.95 3627.15 4110.95 3619.95 4107.22 3616.22 4107.22 3603.72 4104 3600.5 4095.5 3600.5 4093.5 3598.5 4093.5 3577.5 4095.5 3575.5 4100.2 3575.5~gge3878~0","TRACK~3.937~1~VCC~4100.2 3585.5 4104 3585.5 4107 3582 4107 3569 4104 3565.5 4100.2 3565.5~gge4799~0","TRACK~1.1811~1~D7~4140 3545.5 4100.2 3545.5~gge3903~0","TRACK~1.1811~1~D6~4130 3535.5 4100.2002 3535.5~gge3899~0","TRACK~1.1811~1~D4~4120 3515.5 4100.2002 3515.5~gge3894~0","TRACK~1.1811~1~D3~4115 3505.5 4100.2002 3505.5~gge3890~0","TRACK~1.1811~1~D5~4125 3518 4117.5 3525.5 4100.2002 3525.5~gge3897~0","TRACK~1.1811~1~D2~4100.2 3495.5 4112 3495.5 4115.3 3492.2 4150 3492.2~gge3912~0","TRACK~1.1811~1~D1~4100.2 3485.5 4125 3485.5 4150 3460.5 4150 3455.5~gge8744~0","TRACK~1.1811~1~D0~4100.2 3475.5 4123.5 3475.5 4160 3439 4160 3429.8~gge5710~0","TRACK~3.937~1~VCC~4078.5 3565.5 4080.5 3565.5 4080.5 3484.5 4103 3462 4103 3450.5 4127.5 3450.5~gge5376~0","TRACK~1.1811~1~R7_1~4065.5 3441.5 4073 3441.5~gge8736~0","TRACK~1.1811~1~R5_1~4037.8 3515.5 4042.5 3515.5 4065.5 3492.5 4065.5 3461~gge4626~0","TRACK~1.1811~1~R7_1~4037.8 3505.5 4042.51 3505.49 4056 3492.01 4056 3444.5 4059 3441.5 4065.5 3441.5~gge8735~0","TRACK~1.1811~1~W1~4224.5 3675 4184.5 3675 4178.5 3669 4178.5 3655 4174 3650.5 4147 3650.5~gge3641~0","TRACK~1.5748~1~V3.3~4193.5 3637.437 4183 3637.437~gge9252~0","TRACK~1.5748~1~VCC~4203.5 3637 4210 3630.5 4210 3624.5~gge9255~0","TRACK~1.5748~1~VCC~4210 3624.5 4183 3624.5 4183 3629.563~gge9256~0","TRACK~1.5748~1~VCC~4183 3624.5 4177 3624.5 4173.5 3628 4173.5 3637~gge9257~0","TRACK~1.1811~1~F1.8~4203.5 3667 4203.5 3662.98 4203.2002 3662.98~gge9241~0","TRACK~1.1811~1~-WR~4240 3589.7 4240 3601 4234.5 3606.5 4234.5 3671.5 4245 3682 4245 3691 4250.5 3696.5 4261.5 3696.5 4266.5 3701.5 4266.5 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diff --git a/EasyEDA/README.md b/EasyEDA/README.md
new file mode 100644
index 0000000..c145747
--- /dev/null
+++ b/EasyEDA/README.md
@@ -0,0 +1,5 @@
+Orion PRO COM and AY board
+==========================
+How to use：
+
+At editor, Click the document icon on the topbar, via "Document" > "Open" > "EasyEDA Source", and select json file, then open it at the editor.
diff --git a/Export/Schematic_OProCOM-AY_2021-02-05.pdf b/Export/Schematic_OProCOM-AY_2021-02-05.pdf
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diff --git a/Export/Schematic_OProCOM-AY_2021-02-05.png b/Export/Schematic_OProCOM-AY_2021-02-05.png
new file mode 100644
index 0000000..1b9b706
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diff --git a/Export/Schematic_OProCOM-AY_2021-02-05.svg b/Export/Schematic_OProCOM-AY_2021-02-05.svg
new file mode 100644
index 0000000..6423481
--- /dev/null
+++ b/Export/Schematic_OProCOM-AY_2021-02-05.svg
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+path, polyline, polygon {stroke-linejoin:round;}
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display="none" /></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="1" c_spicepin="2" c_origin="315,-515" id="gge7503" locked="0" c_rotation="180"><text x="330" y="-512" font-family="Verdana" font-size="7pt" fill="#000000" text-anchor="start" c_pinname="2"   >2</text><text x="325" y="-516" font-family="Verdana" font-size="7pt" fill="#000000" text-anchor="end" c_pinnumber="2" display="none"  >2</text><circle c_pindot="true" class="pindot" cx="315" cy="-515" r="2" fill="none" stroke="none" /><path d="M 315 -515 h 10" fill="none" stroke="#000000" stroke-width="1"/><circle cx="322" cy="-515" r="3" stroke="#000000" fill="none" stroke-width="1" display="none" /><path d="M 325 -512 L 328 -515 L 325 -518" fill="none" stroke="#000000" stroke-width="1"  display="none" /></g></g><g c_origin="330,-480" c_para="package`HDR-F-2.54_1X2`BOM_Supplier Part`C49661`BOM_Supplier`LCSC`BOM_Manufacturer``BOM_Manufacturer Part``image``Contributor`LCEDA_Lib`spicePre`H`spiceSymbolName`HDR-F-2.54_1x2`" c_partid="part_lib_gge5a38cd636b59bff3" id="gge5a38cd636b59bff3" locked="0" c_shapetype="group" c_etype="pinpart" puuid="36b1306a115341f4b4d9407fb34974e0" uuid="3ec77201bbcd4ecd8722658d581a4e60" convert_to_pcb="yes" add_into_bom="yes" ><g c_partid="part_annotation" id="gge7512"   c_shapetype="group"><text c_note="note_name" x="350.921875" y="-471.75" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >EN-IRQ4</text></g><g c_partid="part_annotation" id="gge7514"   c_shapetype="group"><text c_note="note_pre" x="350.171875" y="-486.75" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >J2</text></g><rect id="gge7516" locked="0" c_etype="" x="325" y="-495" rx="2" ry="2" width="20" height="30" stroke="#880000" stroke-width="1" fill="none"   /><g c_partid="part_pin" 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fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >IO2</text></g><g c_partid="part_annotation" id="gge11606"   c_shapetype="group"><text c_note="note_pre" x="489.7421875" y="-356.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >T3</text></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="0" c_spicepin="P" c_origin="480,-360" id="gge11608" locked="0" c_rotation="180"><text x="493" y="-357" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="start" c_pinname="P" display="none"  >P</text><text x="484" y="-361" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="end" c_pinnumber="P" display="none"  >P</text><circle c_pindot="true" class="pindot" cx="480" cy="-360" r="2" fill="none" stroke="none" /><path d="M 480 -360 h 4" fill="none" stroke="#8D2323" stroke-width="1"/><circle cx="487" cy="-360" r="3" stroke="#8D2323" fill="none" stroke-width="1"  /><path d="M 490 -357 L 493 -360 L 490 -363" fill="none" stroke="#8D2323" stroke-width="1"  display="none" /></g></g><g c_origin="485,-350" c_para="package`CON_PAD_ROUND_1.02MM`Contributor`DangerousPrototype`spicePre`T`spiceSymbolName`PAD_TERMINAL`BOM_Manufacturer Part``" c_partid="part_lib_ggef877e242adbc5845" id="ggef877e242adbc5845" locked="0" c_shapetype="group" c_etype="pinpart" puuid="7c5763efa6a94b838f5aa1433221e642" uuid="b8de1eea11ec4158bd87a581c51a3977" convert_to_pcb="yes" add_into_bom="yes" c_rotation="270"><g c_partid="part_annotation" id="gge15124" display="none"  c_shapetype="group"><text c_note="note_name" x="489.234375" y="-337.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >IO3</text></g><g c_partid="part_annotation" id="gge11621"   c_shapetype="group"><text c_note="note_pre" x="489.7421875" y="-346.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >T4</text></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="0" c_spicepin="P" c_origin="480,-350" id="gge11623" locked="0" c_rotation="180"><text x="493" y="-347" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="start" c_pinname="P" display="none"  >P</text><text x="484" y="-351" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="end" c_pinnumber="P" display="none"  >P</text><circle c_pindot="true" class="pindot" cx="480" cy="-350" r="2" fill="none" stroke="none" /><path d="M 480 -350 h 4" fill="none" stroke="#8D2323" stroke-width="1"/><circle cx="487" cy="-350" r="3" stroke="#8D2323" fill="none" stroke-width="1"  /><path d="M 490 -347 L 493 -350 L 490 -353" fill="none" stroke="#8D2323" stroke-width="1"  display="none" /></g></g><g c_origin="485,-340" c_para="package`CON_PAD_ROUND_1.02MM`Contributor`DangerousPrototype`spicePre`T`spiceSymbolName`PAD_TERMINAL`BOM_Manufacturer Part``" c_partid="part_lib_gge94ae34e68ca73ccd" id="gge94ae34e68ca73ccd" locked="0" c_shapetype="group" c_etype="pinpart" puuid="7c5763efa6a94b838f5aa1433221e642" uuid="b8de1eea11ec4158bd87a581c51a3977" convert_to_pcb="yes" add_into_bom="yes" c_rotation="270"><g c_partid="part_annotation" id="gge15125" display="none"  c_shapetype="group"><text c_note="note_name" x="489.234375" y="-327.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >IO4</text></g><g c_partid="part_annotation" id="gge11636"   c_shapetype="group"><text c_note="note_pre" x="489.7421875" y="-336.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >T5</text></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="0" c_spicepin="P" c_origin="480,-340" id="gge11638" locked="0" c_rotation="180"><text x="493" y="-337" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="start" c_pinname="P" display="none"  >P</text><text x="484" y="-341" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="end" c_pinnumber="P" display="none"  >P</text><circle c_pindot="true" class="pindot" cx="480" cy="-340" r="2" fill="none" stroke="none" /><path d="M 480 -340 h 4" fill="none" stroke="#8D2323" stroke-width="1"/><circle cx="487" cy="-340" r="3" stroke="#8D2323" fill="none" stroke-width="1"  /><path d="M 490 -337 L 493 -340 L 490 -343" fill="none" stroke="#8D2323" stroke-width="1"  display="none" /></g></g><g c_origin="485,-330" c_para="package`CON_PAD_ROUND_1.02MM`Contributor`DangerousPrototype`spicePre`T`spiceSymbolName`PAD_TERMINAL`BOM_Manufacturer Part``" c_partid="part_lib_ggecd022c672f93a581" id="ggecd022c672f93a581" locked="0" c_shapetype="group" c_etype="pinpart" puuid="7c5763efa6a94b838f5aa1433221e642" uuid="b8de1eea11ec4158bd87a581c51a3977" convert_to_pcb="yes" add_into_bom="yes" c_rotation="270"><g c_partid="part_annotation" id="gge15126" display="none"  c_shapetype="group"><text c_note="note_name" x="489.234375" y="-317.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >IO5</text></g><g c_partid="part_annotation" id="gge11651"   c_shapetype="group"><text c_note="note_pre" x="489.7421875" y="-326.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >T6</text></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="0" c_spicepin="P" c_origin="480,-330" id="gge11653" locked="0" c_rotation="180"><text x="493" y="-327" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="start" c_pinname="P" display="none"  >P</text><text x="484" y="-331" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="end" c_pinnumber="P" display="none"  >P</text><circle c_pindot="true" class="pindot" cx="480" cy="-330" r="2" fill="none" stroke="none" /><path d="M 480 -330 h 4" fill="none" stroke="#8D2323" stroke-width="1"/><circle cx="487" cy="-330" r="3" stroke="#8D2323" fill="none" stroke-width="1"  /><path d="M 490 -327 L 493 -330 L 490 -333" fill="none" stroke="#8D2323" stroke-width="1"  display="none" /></g></g><g c_origin="485,-320" c_para="package`CON_PAD_ROUND_1.02MM`Contributor`DangerousPrototype`spicePre`T`spiceSymbolName`PAD_TERMINAL`BOM_Manufacturer Part``" c_partid="part_lib_ggecb2a905505c9a709" id="ggecb2a905505c9a709" locked="0" c_shapetype="group" c_etype="pinpart" puuid="7c5763efa6a94b838f5aa1433221e642" uuid="b8de1eea11ec4158bd87a581c51a3977" convert_to_pcb="yes" add_into_bom="yes" c_rotation="270"><g c_partid="part_annotation" id="gge15127" display="none"  c_shapetype="group"><text c_note="note_name" x="489.234375" y="-307.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >IO6</text></g><g c_partid="part_annotation" id="gge11666"   c_shapetype="group"><text c_note="note_pre" x="489.7421875" y="-316.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >T7</text></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="0" c_spicepin="P" c_origin="480,-320" id="gge11668" locked="0" c_rotation="180"><text x="493" y="-317" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="start" c_pinname="P" display="none"  >P</text><text x="484" y="-321" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="end" c_pinnumber="P" display="none"  >P</text><circle c_pindot="true" class="pindot" cx="480" cy="-320" r="2" fill="none" stroke="none" /><path d="M 480 -320 h 4" fill="none" stroke="#8D2323" stroke-width="1"/><circle cx="487" cy="-320" r="3" stroke="#8D2323" fill="none" stroke-width="1"  /><path d="M 490 -317 L 493 -320 L 490 -323" fill="none" stroke="#8D2323" stroke-width="1"  display="none" /></g></g><g c_origin="485,-310" c_para="package`CON_PAD_ROUND_1.02MM`Contributor`DangerousPrototype`spicePre`T`spiceSymbolName`PAD_TERMINAL`BOM_Manufacturer Part``" c_partid="part_lib_gge1cda3c11e1c30ba5" id="gge1cda3c11e1c30ba5" locked="0" c_shapetype="group" c_etype="pinpart" puuid="7c5763efa6a94b838f5aa1433221e642" uuid="b8de1eea11ec4158bd87a581c51a3977" convert_to_pcb="yes" add_into_bom="yes" c_rotation="270"><g c_partid="part_annotation" id="gge15128" display="none"  c_shapetype="group"><text c_note="note_name" x="489.234375" y="-297.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >IO7</text></g><g c_partid="part_annotation" id="gge11681"   c_shapetype="group"><text c_note="note_pre" x="489.7421875" y="-306.67" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >T8</text></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="0" c_spicepin="P" c_origin="480,-310" id="gge11683" locked="0" c_rotation="180"><text x="493" y="-307" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="start" c_pinname="P" display="none"  >P</text><text x="484" y="-311" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="end" c_pinnumber="P" display="none"  >P</text><circle c_pindot="true" class="pindot" cx="480" cy="-310" r="2" fill="none" stroke="none" /><path d="M 480 -310 h 4" fill="none" stroke="#8D2323" stroke-width="1"/><circle cx="487" cy="-310" r="3" stroke="#8D2323" fill="none" stroke-width="1"  /><path d="M 490 -307 L 493 -310 L 490 -313" fill="none" stroke="#8D2323" stroke-width="1"  display="none" /></g></g><g c_origin="620,-310" c_para="package`CON_PAD_ROUND_1.02MM`Contributor`DangerousPrototype`spicePre`T`spiceSymbolName`PAD_TERMINAL`BOM_Manufacturer Part``" c_partid="part_lib_ggeaa2ec37996ca8b31" id="ggeaa2ec37996ca8b31" locked="0" c_shapetype="group" c_etype="pinpart" puuid="7c5763efa6a94b838f5aa1433221e642" uuid="b8de1eea11ec4158bd87a581c51a3977" convert_to_pcb="yes" add_into_bom="yes" c_rotation="90"><g c_partid="part_annotation" id="gge15120" display="none"  c_shapetype="group"><text c_note="note_name" x="598.921875" y="-297.69" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >GND</text></g><g c_partid="part_annotation" id="gge11697"   c_shapetype="group"><text c_note="note_pre" x="599.65" y="-306.84" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >T9</text></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="0" c_spicepin="P" c_origin="625,-310" id="gge11699" locked="0" c_rotation="0"><text x="612" y="-307" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="end" c_pinname="P" display="none"  >P</text><text x="621" y="-311" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="start" c_pinnumber="P" display="none"  >P</text><circle c_pindot="true" class="pindot" cx="625" cy="-310" r="2" fill="none" stroke="none" /><path d="M 625 -310 h -4" fill="none" stroke="#8D2323" stroke-width="1"/><circle cx="618" cy="-310" r="3" stroke="#8D2323" fill="none" stroke-width="1"  /><path d="M 615 -313 L 612 -310 L 615 -307" fill="none" stroke="#8D2323" stroke-width="1"  display="none" /></g></g><g c_origin="620,-320" c_para="package`CON_PAD_ROUND_1.02MM`Contributor`DangerousPrototype`spicePre`T`spiceSymbolName`PAD_TERMINAL`BOM_Manufacturer Part``" c_partid="part_lib_gge1d1bf7c9f8519419" id="gge1d1bf7c9f8519419" locked="0" c_shapetype="group" c_etype="pinpart" puuid="7c5763efa6a94b838f5aa1433221e642" uuid="b8de1eea11ec4158bd87a581c51a3977" convert_to_pcb="yes" add_into_bom="yes" c_rotation="90"><g c_partid="part_annotation" id="gge15119" display="none"  c_shapetype="group"><text c_note="note_name" x="596.34375" y="-307.69" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >VCC</text></g><g c_partid="part_annotation" id="gge11713"   c_shapetype="group"><text c_note="note_pre" x="597.06" y="-316.84" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >T10</text></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="0" c_spicepin="P" c_origin="625,-320" id="gge11715" locked="0" c_rotation="0"><text x="612" y="-317" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="end" c_pinname="P" display="none"  >P</text><text x="621" y="-321" font-family="Verdana" font-size="7pt" fill="#8D2323" text-anchor="start" c_pinnumber="P" display="none"  >P</text><circle c_pindot="true" class="pindot" cx="625" cy="-320" r="2" fill="none" stroke="none" /><path d="M 625 -320 h -4" fill="none" stroke="#8D2323" stroke-width="1"/><circle cx="618" cy="-320" r="3" stroke="#8D2323" fill="none" stroke-width="1"  /><path d="M 615 -323 L 612 -320 L 615 -317" fill="none" stroke="#8D2323" stroke-width="1"  display="none" /></g></g><polyline c_etype="wire" c_shapetype="line" points="625 -320 660 -320" stroke="#008800" id="gge11725" locked="0" stroke-width="1"   fill="none" stroke-linecap="round" /><polyline c_etype="wire" c_shapetype="line" points="625 -310 660 -310" stroke="#008800" id="gge11726" locked="0" stroke-width="1"   fill="none" stroke-linecap="round" /><g c_partid="part_busentry" c_origin="660,-310" id="gge11727" locked="0" c_rotation="" c_shapetype="group" c_etype="pinpart"><circle c_pindot="true" class="pindot" cx="660" cy="-310" r="2" fill="none" stroke="none"/><circle c_pindot="true" class="pindot" cx="670" cy="-320" r="2" fill="none" stroke="none"/><line x1="660" y1="-310" x2="670" y2="-320" stroke="#008800" stroke-width="1"/></g><g c_partid="part_busentry" c_origin="660,-320" id="gge11731" locked="0" c_rotation="" c_shapetype="group" c_etype="pinpart"><circle c_pindot="true" class="pindot" cx="660" cy="-320" r="2" fill="none" stroke="none"/><circle c_pindot="true" class="pindot" cx="670" cy="-330" r="2" fill="none" stroke="none"/><line x1="660" y1="-320" x2="670" y2="-330" stroke="#008800" stroke-width="1"/></g><g c_partid="part_netLabel_text" c_etype="pinpart" c_origin="660,-320" id="gge11739" locked="0" c_shapetype="group"><text x="658" y="-322.5" font-family="Times New Roman" font-size="7pt" fill="#0000ff" text-anchor="end"  >VCC</text><path d="M 660 -321 L 660 -319 M 659 -320 L 661 -320" stroke-width="0.1" stroke="#000000" stroke-linejoin="round"></path></g><g c_partid="part_netLabel_text" c_etype="pinpart" c_origin="660,-310" id="gge11743" locked="0" c_shapetype="group"><text x="658" y="-312.5" font-family="Times New Roman" font-size="7pt" fill="#0000ff" text-anchor="end"  >GND</text><path d="M 660 -311 L 660 -309 M 659 -310 L 661 -310" stroke-width="0.1" stroke="#000000" stroke-linejoin="round"></path></g><g c_origin="500,15" c_para="package`OSC-SMD_4P-L5.0-W3.2-BL`BOM_Supplier`LCSC`BOM_Supplier Part`C401162`BOM_Manufacturer`SiTime`BOM_Manufacturer Part`SIT8920AM-31-18E-24.000625`nameAlias`Frequency`Contributor`LCSC`spicePre`X`spiceSymbolName`SIT8920AM-31-18E-24.000625`" c_partid="part_lib_gge7a86a5b510a6b7c3" id="gge7a86a5b510a6b7c3" locked="0" c_shapetype="group" c_etype="pinpart" puuid="4b10eeb83b724d9cbe3c42e9cbf502dc" uuid="b3ad52f2c15045b29c9f95153830f8d7" convert_to_pcb="yes" add_into_bom="yes" ><g c_partid="part_annotation" id="gge14293"   c_shapetype="group"><text c_note="note_name" x="488.1328125" y="0.2" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >1.8432MHz</text></g><g c_partid="part_annotation" id="gge14295"   c_shapetype="group"><text c_note="note_pre" x="466.1171875" y="0.34" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >ZQ1</text></g><g c_partid="part_pin" c_etype="pinpart"  c_show="show"  c_elec="0" c_spicepin="4" c_origin="550,15" id="gge14297" locked="0" c_rotation="0"><text x="536.3" y="19" font-family="Verdana" font-size="7pt" fill="#FF0000" text-anchor="end" c_pinname="VDD"   >VDD</text><text x="540.5" y="14" font-family="Verdana" font-size="7pt" fill="#FF0000" text-anchor="start" c_pinnumber="4"   >4</text><circle c_pindot="true" class="pindot" cx="550" cy="15" r="2" fill="none" stroke="none" /><path d="M 550 15 h -10" fill="none" stroke="#FF0000" stroke-width="1"/><circle cx="543" cy="15" r="3" stroke="#FF0000" fill="none" stroke-width="1" display="none" /><path d="M 540 12 L 537 15 L 540 18" fill="none" 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c_partid="part_lib_ggedae423716486c3da" id="ggedae423716486c3da" locked="0" c_shapetype="group" c_etype="pinpart" puuid="7d441db52cb04c809670ae39aac6b010" uuid="691241d9a461439497367c112b274120" convert_to_pcb="yes" add_into_bom="yes" c_rotation="90"><g c_partid="part_annotation" id="gge15465"   c_shapetype="group"><text c_note="note_name" x="1208.171875" y="-66.75" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >0.1uF</text></g><g c_partid="part_annotation" id="gge15467"   c_shapetype="group"><text c_note="note_pre" x="1214.125" y="-76.75" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >C18</text></g><polyline points="1197 -78 1213 -78" stroke="#880000" id="gge15469" locked="0" stroke-width="1"   fill="none" stroke-linecap="round" /><polyline points="1197 -82 1213 -82" stroke="#880000" id="gge15470" locked="0" stroke-width="1"   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stroke-linecap="round" /></g><g c_origin="1170,-80" c_para="package`CAP-TH_L3.0-W2.0-P2.54-D0.7`BOM_Supplier`LCSC`BOM_Manufacturer`ReliaPro`BOM_Manufacturer Part`224K 100V`nameAlias`Value`Contributor`LCSC`BOM_Supplier Part`C14861`spicePre`C`spiceSymbolName`224K 100V`" c_partid="part_lib_gged3d73d3ea7e899d4" id="gged3d73d3ea7e899d4" locked="0" c_shapetype="group" c_etype="pinpart" puuid="7d441db52cb04c809670ae39aac6b010" uuid="691241d9a461439497367c112b274120" convert_to_pcb="yes" add_into_bom="yes" c_rotation="90"><g c_partid="part_annotation" id="gge15489"   c_shapetype="group"><text c_note="note_name" x="1173.171875" y="-66.75" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" text-anchor="start"  >0.1uF</text></g><g c_partid="part_annotation" id="gge15491"   c_shapetype="group"><text c_note="note_pre" x="1179.125" y="-76.75" fill="#000080" font-family="Arial" font-size="7pt" font-weight="" font-style="" dominant-baseline="" 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diff --git a/Export/com-ay.jpg b/Export/com-ay.jpg
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diff --git a/Firmware/OrionCOM-AY/OrionCOM-AY.qpf b/Firmware/OrionCOM-AY/OrionCOM-AY.qpf
new file mode 100644
index 0000000..aa8b1ea
--- /dev/null
+++ b/Firmware/OrionCOM-AY/OrionCOM-AY.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 14:21:14  November 28, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "14:21:14  November 28, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "OrionCOM-AY"
diff --git a/Firmware/OrionCOM-AY/OrionCOM-AY.qsf b/Firmware/OrionCOM-AY/OrionCOM-AY.qsf
new file mode 100644
index 0000000..c22a418
--- /dev/null
+++ b/Firmware/OrionCOM-AY/OrionCOM-AY.qsf
@@ -0,0 +1,91 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 14:21:14  November 28, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		OrionCOM-AY_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY MAX7000S
+set_global_assignment -name DEVICE "EPM7064STC44-7"
+set_global_assignment -name TOP_LEVEL_ENTITY OrionCOM_AY
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:21:14  NOVEMBER 28, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name SYSTEMVERILOG_FILE OrionCOM_AY.sv
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
+set_location_assignment PIN_33 -to debug
+set_location_assignment PIN_2 -to a[0]
+set_location_assignment PIN_3 -to a[1]
+set_location_assignment PIN_5 -to a[2]
+set_location_assignment PIN_1 -to TDI
+set_location_assignment PIN_32 -to TDO
+set_location_assignment PIN_26 -to TCK
+set_location_assignment PIN_7 -to TMS
+set_location_assignment PIN_6 -to a[3]
+set_location_assignment PIN_8 -to a[4]
+set_location_assignment PIN_10 -to a[5]
+set_location_assignment PIN_11 -to a[6]
+set_location_assignment PIN_12 -to a[7]
+set_location_assignment PIN_13 -to irq4
+set_location_assignment PIN_14 -to irq3
+set_location_assignment PIN_15 -to a[8]
+set_location_assignment PIN_18 -to a[9]
+set_location_assignment PIN_42 -to bc1
+set_location_assignment PIN_43 -to bdir
+set_location_assignment PIN_37 -to clk
+set_location_assignment PIN_27 -to clk1
+set_location_assignment PIN_44 -to clk2
+set_location_assignment PIN_25 -to cs_vi_n
+set_location_assignment PIN_35 -to cs_vv1_n
+set_location_assignment PIN_30 -to cs_vv2_n
+set_location_assignment PIN_21 -to iorq_n
+set_location_assignment PIN_23 -to m1_n
+set_location_assignment PIN_19 -to rd_n
+set_location_assignment PIN_38 -to rdy1
+set_location_assignment PIN_31 -to rdy2
+set_location_assignment PIN_39 -to reset_n
+set_location_assignment PIN_34 -to reset
+set_location_assignment PIN_28 -to w1
+set_location_assignment PIN_22 -to wait_n
+set_location_assignment PIN_20 -to wr_n
\ No newline at end of file
diff --git a/Firmware/OrionCOM-AY/OrionCOM-AY_description.txt b/Firmware/OrionCOM-AY/OrionCOM-AY_description.txt
new file mode 100644
index 0000000..e69de29
diff --git a/Firmware/OrionCOM-AY/OrionCOM_AY.sv b/Firmware/OrionCOM-AY/OrionCOM_AY.sv
new file mode 100644
index 0000000..60d94f2
--- /dev/null
+++ b/Firmware/OrionCOM-AY/OrionCOM_AY.sv
@@ -0,0 +1,154 @@
+//
+// Дешифратор портов и сигналов для платы OrionPro COM-AY
+//
+module OrionCOM_AY (
+	
+	// Сигналы шины Orion PRO
+	input wire clk,			// 10MHz Orion Clock
+	input wire reset_n,		// RES0
+	input wire iorq_n,		// -IORQ
+	input wire m1_n,			// -M1
+	input wire wr_n,			// -WR
+	input wire rd_n,			// -RD
+	input wire wait_n,		// -WAIT
+	input wire [9:0] a,		// A0-A7,A14,A15
+	
+	// Сигналы готовности от ВВ51
+	input wire rdy1,			// от порта COM1
+	input wire rdy2,			// от порта COM2
+	
+	// Выходные сигналы
+	output wire cs_vi_n,		// Выборка ВИ53
+	output wire cs_vv1_n,	// Выборка ВВ51 COM1
+	output wire cs_vv2_n,	// Выборка ВВ51 COM2
+	output wire bdir,			// Направление данных AY
+	output wire bc1,			// Выбор команды AY
+	output wire w1,			// Задержанный WR для ВИ53
+	output wire clk1,  		// Тактирование ВИ53, ВВ51
+	output wire clk2,  		// Тактирование AY
+	output wire reset,		// Инвертированный сброс для ВВ51
+	output wire irq3,			// Запрос прерывания 3 в шину Orion PRO
+	output wire irq4,			// Запрос прерывания 4 в шину Orion PRO
+	output wire debug
+);
+
+	wire sel3x;
+	wire cs_ay_opro;
+	wire cs_ay_lb;
+	wire cs_ay_ff;
+	wire cs_ay_bf;
+	wire cs_ay_3f;
+	wire cs_ay_3e;
+	wire cs_ay_0;
+	wire cs_ay_1;
+	
+	assign reset = !reset_n;
+	assign irq3 = !rdy1;
+	assign irq4 = !rdy2;
+	assign w1 = wait_n | wr_n;
+	
+	// Сигналы выборки портов IO
+	assign sel3x = (a[7:4] == 4'b0011) && !iorq_n;
+	
+	assign cs_vv1_n = !(sel3x & !a[3] & !a[2]);
+	assign cs_vv2_n = !(sel3x & !a[3] & a[2]);
+	assign cs_vi_n  = !(sel3x & a[3] & !a[2]);
+	
+	// Сигналы выборки AY
+	assign cs_ay_opro  = sel3x & a[2] & a[3];
+	
+	assign cs_ay_3f = cs_ay_opro & a[0];
+	assign cs_ay_3e = cs_ay_opro & !a[0];
+	
+	assign cs_ay_lb =  (a[7:0] == 8'hFD) ? (m1_n & !iorq_n) : 1'b0;
+	assign cs_ay_bf = a[9] & !a[8] & cs_ay_lb;
+	assign cs_ay_ff = a[9] & a[8] & cs_ay_lb;
+	
+	assign cs_ay_0 = cs_ay_bf || cs_ay_3e;
+	assign cs_ay_1 = cs_ay_ff || cs_ay_3f;
+	
+	
+	// Сигналы управления AY
+	assign bc1 = cs_ay_1 & (!rd_n | !wr_n);
+   assign bdir = (cs_ay_0 || cs_ay_1) & !wr_n;
+	// Тактирование AY
+	AyClkDiv ayClkDiv( .clk(clk), .reset_n(reset_n), .clk_out(clk2) );
+	
+	// Тактирование для ВИ53, ВВ51
+	ViClkDiv viClkDiv( .clk(clk), .reset_n(reset_n), .clk_out(clk1) );
+	
+	
+	// -- DEBUG
+	assign debug = clk2;			
+		
+endmodule
+
+
+module ViClkDiv(
+	input clk,
+	input reset_n,
+	output clk_out
+);
+
+	reg [1:0] div1;
+	
+	assign clk_out = div1[1];
+	
+	always @ (posedge clk, negedge reset_n)
+		if (!reset_n) div1 <= 2'b00;
+		else div1 <= div1 + 1'b1;
+
+endmodule
+
+
+/* Делитель частоты для AY
+	Коэффициенты 
+	для базовой частоты 10MHz:
+	k = 3/17,  F= 1.764705 MHz, c = 5h
+	k = 10/57, F= 1.754385 MHz, c = 2d	
+	k = 7/40,  F= 1.750000 MHz, c = 1Ch
+	для базовой частоты 20MHz:
+	k = 3/34,  F= 1.764705 MHz, c = 0Bh;
+	k = 5/57,  F= 1.754385 MHz, c = 4Fh;
+	k = 7/80,  F= 1.750000 MHz, c = 39h;
+	k = 8/91,  F= 1.758241 MHz, c = 71h;
+	k = N/M
+	k = 179/1024 F= 1.748046, c = 3F4h;
+*/
+
+module AyClkDiv(
+	input clk,
+	input reset_n,
+	output clk_out
+);
+
+	localparam N = 9;
+	localparam C = 8'd179;
+	
+	reg [N:0] sum;
+	assign clk_out = sum[N];
+
+	always_ff @ (posedge clk, negedge reset_n)
+		if (!reset_n) sum <= 0;		
+		else sum <= sum + C;
+	
+endmodule
+
+/*
+module AyClkDivV2(
+	input clk,
+	input reset_n,
+	output clk_out
+);
+
+   parameter M = 7;
+	parameter N = 40;
+	
+   localparam X = ((1<<$clog2(N)) - N + M);
+   bit [$clog2(N)-1:0] cnt; // счетчик
+   always @(posedge clk, negedge reset_n)
+      if (!reset_n) cnt <= 0;
+      else {clk_out, cnt} = cnt + (clk_out ? X:M);
+
+endmodule
+*/
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(0).cnf.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(0).cnf.cdb
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(5).cnf.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(5).cnf.cdb
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(5).cnf.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(5).cnf.hdb
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(6).cnf.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(6).cnf.cdb
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(6).cnf.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(6).cnf.hdb
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(7).cnf.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(7).cnf.cdb
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index 0000000..066ddce
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(7).cnf.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(7).cnf.hdb
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(8).cnf.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(8).cnf.cdb
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(8).cnf.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(8).cnf.hdb
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index 0000000..a3f4cb2
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(9).cnf.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(9).cnf.cdb
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.(9).cnf.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.(9).cnf.hdb
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index 0000000..f8cf628
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.ace_cmp.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.ace_cmp.cdb
new file mode 100644
index 0000000..a43a1b6
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.ace_cmp.cdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.ace_cmp.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.ace_cmp.hdb
new file mode 100644
index 0000000..6c619e5
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.ace_cmp.hdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.asm.qmsg b/Firmware/OrionCOM-AY/db/OrionCOM-AY.asm.qmsg
new file mode 100644
index 0000000..c62bc4b
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.asm.qmsg
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1612531289301 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612531289302 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 16:21:29 2021 " "Processing started: Fri Feb  5 16:21:29 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612531289302 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1612531289302 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY " "Command: quartus_asm --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1612531289303 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1612531289485 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "299 " "Peak virtual memory: 299 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612531289713 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 16:21:29 2021 " "Processing ended: Fri Feb  5 16:21:29 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612531289713 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612531289713 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612531289713 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1612531289713 ""}
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.asm.rdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.asm.rdb
new file mode 100644
index 0000000..5c5503a
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.asm.rdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.cbx.xml b/Firmware/OrionCOM-AY/db/OrionCOM-AY.cbx.xml
new file mode 100644
index 0000000..7648f12
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.cbx.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="OrionCOM-AY">
+		<CBX_INST_ENTRY INSTANCE_NAME="|OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0" CBX_FILE_NAME="add_sub_4ph.tdf"/>
+	</PROJECT>
+</LOG_ROOT>
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp.cdb
new file mode 100644
index 0000000..541088f
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp.hdb
new file mode 100644
index 0000000..464add4
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp.logdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp.rdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp.rdb
new file mode 100644
index 0000000..3aba43d
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp0.ddb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp0.ddb
new file mode 100644
index 0000000..a643cf9
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.cmp0.ddb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.db_info b/Firmware/OrionCOM-AY/db/OrionCOM-AY.db_info
new file mode 100644
index 0000000..13e82ef
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Fri Feb  5 16:20:44 2021
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.eco.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.eco.cdb
new file mode 100644
index 0000000..221e564
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.eco.cdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.eda.qmsg b/Firmware/OrionCOM-AY/db/OrionCOM-AY.eda.qmsg
new file mode 100644
index 0000000..561419f
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.eda.qmsg
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1612531294784 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612531294785 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 16:21:34 2021 " "Processing started: Fri Feb  5 16:21:34 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612531294785 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1612531294785 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY " "Command: quartus_eda --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1612531294786 ""}
+{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "OrionCOM-AY.vo OrionCOM-AY_v.sdo /opt/cpld/OrionCOM-AY/simulation/modelsim/ simulation " "Generated files \"OrionCOM-AY.vo\" and \"OrionCOM-AY_v.sdo\" in directory \"/opt/cpld/OrionCOM-AY/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204018 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "Quartus II" 0 -1 1612531294985 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "304 " "Peak virtual memory: 304 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612531295021 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 16:21:35 2021 " "Processing ended: Fri Feb  5 16:21:35 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612531295021 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612531295021 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612531295021 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1612531295021 ""}
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.fit.qmsg b/Firmware/OrionCOM-AY/db/OrionCOM-AY.fit.qmsg
new file mode 100644
index 0000000..ad0ea27
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.fit.qmsg
@@ -0,0 +1,4 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1612531286042 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "OrionCOM-AY EPM7064STC44-7 " "Selected device EPM7064STC44-7 for design \"OrionCOM-AY\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1612531286044 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCK " "Node \"TCK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1612531286203 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDI " "Node \"TDI\" is assigned to location or region, but does not exist in design" {  } { { "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1612531286203 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDO " "Node \"TDO\" is assigned to location or region, but does not exist in design" {  } { { "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1612531286203 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TMS " "Node \"TMS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TMS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1612531286203 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1612531286203 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "294 " "Peak virtual memory: 294 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612531286766 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 16:21:26 2021 " "Processing ended: Fri Feb  5 16:21:26 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612531286766 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612531286766 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612531286766 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1612531286766 ""}
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.hier_info b/Firmware/OrionCOM-AY/db/OrionCOM-AY.hier_info
new file mode 100644
index 0000000..3a81d99
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.hier_info
@@ -0,0 +1,71 @@
+|OrionCOM_AY
+clk => clk.IN2
+reset_n => reset_n.IN2
+iorq_n => sel3x.IN0
+m1_n => cs_ay_lb.IN1
+wr_n => w1.IN0
+wr_n => bdir.IN0
+rd_n => bc1.IN0
+wait_n => w1.IN1
+a[0] => cs_ay_3f.IN0
+a[0] => cs_ay_3e.IN0
+a[0] => Equal1.IN15
+a[1] => Equal1.IN14
+a[2] => cs_vv2_n.IN1
+a[2] => cs_vi_n.IN0
+a[2] => cs_ay_opro.IN0
+a[2] => Equal1.IN13
+a[3] => cs_vv1_n.IN0
+a[3] => cs_vi_n.IN0
+a[3] => cs_ay_opro.IN1
+a[3] => Equal1.IN12
+a[4] => Equal0.IN7
+a[4] => Equal1.IN11
+a[5] => Equal0.IN6
+a[5] => Equal1.IN10
+a[6] => Equal0.IN5
+a[6] => Equal1.IN9
+a[7] => Equal0.IN4
+a[7] => Equal1.IN8
+a[8] => cs_ay_bf.IN0
+a[8] => cs_ay_ff.IN1
+a[9] => cs_ay_bf.IN1
+a[9] => cs_ay_ff.IN0
+rdy1 => irq3.IN0
+rdy2 => irq4.IN0
+cs_vi_n <= cs_vi_n.DB_MAX_OUTPUT_PORT_TYPE
+cs_vv1_n <= cs_vv1_n.DB_MAX_OUTPUT_PORT_TYPE
+cs_vv2_n <= cs_vv2_n.DB_MAX_OUTPUT_PORT_TYPE
+bdir <= bdir.DB_MAX_OUTPUT_PORT_TYPE
+bc1 <= bc1.DB_MAX_OUTPUT_PORT_TYPE
+w1 <= w1.DB_MAX_OUTPUT_PORT_TYPE
+clk1 <= ViClkDiv:viClkDiv.clk_out
+clk2 <= AyClkDiv:ayClkDiv.clk_out
+reset <= reset.DB_MAX_OUTPUT_PORT_TYPE
+irq3 <= irq3.DB_MAX_OUTPUT_PORT_TYPE
+irq4 <= irq4.DB_MAX_OUTPUT_PORT_TYPE
+debug <= AyClkDiv:ayClkDiv.clk_out
+
+
+|OrionCOM_AY|AyClkDiv:ayClkDiv
+clk => sum[0].CLK
+clk => sum[1].CLK
+clk => sum[2].CLK
+clk => sum[3].CLK
+clk => sum[4].CLK
+clk => sum[5].CLK
+clk => sum[6].CLK
+clk => sum[7].CLK
+clk => sum[8].CLK
+clk => sum[9].CLK
+reset_n => always0.IN0
+clk_out <= sum[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|OrionCOM_AY|ViClkDiv:viClkDiv
+clk => div1[0].CLK
+clk => div1[1].CLK
+reset_n => always0.IN0
+clk_out <= div1[1].DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.hif b/Firmware/OrionCOM-AY/db/OrionCOM-AY.hif
new file mode 100644
index 0000000..1ee6de5
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.hif differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.ipinfo b/Firmware/OrionCOM-AY/db/OrionCOM-AY.ipinfo
new file mode 100644
index 0000000..6ff9cf3
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.ipinfo differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.lpc.html b/Firmware/OrionCOM-AY/db/OrionCOM-AY.lpc.html
new file mode 100644
index 0000000..078ccea
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.lpc.html
@@ -0,0 +1,50 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >viClkDiv</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ayClkDiv</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.lpc.rdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.lpc.rdb
new file mode 100644
index 0000000..6b4c714
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.lpc.txt b/Firmware/OrionCOM-AY/db/OrionCOM-AY.lpc.txt
new file mode 100644
index 0000000..df89116
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.lpc.txt
@@ -0,0 +1,8 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; viClkDiv  ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ayClkDiv  ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.cdb
new file mode 100644
index 0000000..e882b16
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.hdb
new file mode 100644
index 0000000..b4a986e
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.logdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.qmsg b/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.qmsg
new file mode 100644
index 0000000..3898815
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.qmsg
@@ -0,0 +1,22 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1612531280218 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612531280219 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 16:21:19 2021 " "Processing started: Fri Feb  5 16:21:19 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612531280219 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1612531280219 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off OrionCOM-AY -c OrionCOM-AY " "Command: quartus_map --read_settings_files=on --write_settings_files=off OrionCOM-AY -c OrionCOM-AY" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1612531280220 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1612531281032 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "OrionCOM_AY.sv 3 3 " "Found 3 design units, including 3 entities, in source file OrionCOM_AY.sv" { { "Info" "ISGN_ENTITY_NAME" "1 OrionCOM_AY " "Found entity 1: OrionCOM_AY" {  } { { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1612531281279 ""} { "Info" "ISGN_ENTITY_NAME" "2 ViClkDiv " "Found entity 2: ViClkDiv" {  } { { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 87 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1612531281279 ""} { "Info" "ISGN_ENTITY_NAME" "3 AyClkDiv " "Found entity 3: AyClkDiv" {  } { { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 119 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1612531281279 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1612531281279 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "OrionCOM_AY " "Elaborating entity \"OrionCOM_AY\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1612531281437 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AyClkDiv AyClkDiv:ayClkDiv " "Elaborating entity \"AyClkDiv\" for hierarchy \"AyClkDiv:ayClkDiv\"" {  } { { "OrionCOM_AY.sv" "ayClkDiv" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 75 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281441 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ViClkDiv ViClkDiv:viClkDiv " "Elaborating entity \"ViClkDiv\" for hierarchy \"ViClkDiv:viClkDiv\"" {  } { { "OrionCOM_AY.sv" "viClkDiv" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 78 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281442 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "AyClkDiv:ayClkDiv\|Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"AyClkDiv:ayClkDiv\|Add0\"" {  } { { "OrionCOM_AY.sv" "Add0" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1612531281495 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1612531281495 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1612531281684 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Instantiated megafunction \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 10 " "Parameter \"LPM_WIDTH\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281684 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281684 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281684 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281684 ""}  } { { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1612531281684 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\] AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281697 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:oflow_node AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281703 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:result_node AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281705 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[0\] AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281707 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|look_add:look_ahead_unit AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281716 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281720 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "OrionCOM_AY.sv" "" { Text "/opt/cpld/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612531281721 ""}
+{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "12 " "Ignored 12 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "12 " "Ignored 12 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1612531281815 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1612531281815 ""}
+{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1612531281876 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset_n " "Promoted clear signal driven by pin \"reset_n\" to global clear signal" {  } {  } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1612531281876 ""}  } {  } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1612531281876 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "53 " "Implemented 53 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "19 " "Implemented 19 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1612531281976 ""} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Implemented 12 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1612531281976 ""} { "Info" "ICUT_CUT_TM_MCELLS" "22 " "Implemented 22 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1612531281976 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1612531281976 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "335 " "Peak virtual memory: 335 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612531282664 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 16:21:22 2021 " "Processing ended: Fri Feb  5 16:21:22 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612531282664 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612531282664 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612531282664 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1612531282664 ""}
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.rdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.rdb
new file mode 100644
index 0000000..3a20fb6
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.map.rdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.pplq.rdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.pplq.rdb
new file mode 100644
index 0000000..ecdfe30
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.pplq.rdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.pre_map.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.pre_map.hdb
new file mode 100644
index 0000000..a587142
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.pre_map.hdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.pti_db_list.ddb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.pti_db_list.ddb
new file mode 100644
index 0000000..61ca8da
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.pti_db_list.ddb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.quiproj.14697.rdr.flock b/Firmware/OrionCOM-AY/db/OrionCOM-AY.quiproj.14697.rdr.flock
new file mode 100644
index 0000000..e69de29
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.root_partition.map.reg_db.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..193bde3
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.root_partition.map.reg_db.cdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.rpp.qmsg b/Firmware/OrionCOM-AY/db/OrionCOM-AY.rpp.qmsg
new file mode 100644
index 0000000..911c880
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.rpp.qmsg
@@ -0,0 +1,4 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1612509848878 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612509848879 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 10:24:08 2021 " "Processing started: Fri Feb  5 10:24:08 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612509848879 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1612509848879 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp OrionCOM-AY -c OrionCOM-AY --netlist_type=sgate " "Command: quartus_rpp OrionCOM-AY -c OrionCOM-AY --netlist_type=sgate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1612509848880 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "255 " "Peak virtual memory: 255 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612509848963 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 10:24:08 2021 " "Processing ended: Fri Feb  5 10:24:08 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612509848963 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612509848963 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612509848963 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1612509848963 ""}
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.rtlv.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.rtlv.hdb
new file mode 100644
index 0000000..5fec33e
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.rtlv_sg.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.rtlv_sg.cdb
new file mode 100644
index 0000000..bdd6e56
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.rtlv_sg_swap.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..f0e860d
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.rtlv_sg_swap.cdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.sgate.rvd b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sgate.rvd
new file mode 100644
index 0000000..e08bb5e
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.sgate_sm.rvd b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sgate_sm.rvd
new file mode 100644
index 0000000..67ca5fe
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.sgdiff.cdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sgdiff.cdb
new file mode 100644
index 0000000..70de0a0
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.sgdiff.hdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sgdiff.hdb
new file mode 100644
index 0000000..94aca97
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sgdiff.hdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.sld_design_entry.sci b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sld_design_entry.sci
new file mode 100644
index 0000000..35aa479
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diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.sld_design_entry_dsc.sci b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..35aa479
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sld_design_entry_dsc.sci differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.smart_action.txt b/Firmware/OrionCOM-AY/db/OrionCOM-AY.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.sta.qmsg b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sta.qmsg
new file mode 100644
index 0000000..42ac3e0
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sta.qmsg
@@ -0,0 +1,22 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1612531291650 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612531291650 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 16:21:31 2021 " "Processing started: Fri Feb  5 16:21:31 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612531291650 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1612531291650 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta OrionCOM-AY -c OrionCOM-AY " "Command: quartus_sta OrionCOM-AY -c OrionCOM-AY" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1612531291651 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1612531291704 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1612531291850 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1612531291889 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1612531291891 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." {  } {  } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1612531291984 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "OrionCOM-AY.sdc " "Synopsys Design Constraints File file not found: 'OrionCOM-AY.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1612531291994 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1612531291995 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292001 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292001 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1612531292012 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1612531292020 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -7.800 " "Worst-case setup slack is -7.800" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292021 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292021 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -7.800       -77.800 clk  " "   -7.800       -77.800 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292021 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1612531292021 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.000 " "Worst-case hold slack is 3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292023 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292023 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.000         0.000 clk  " "    3.000         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292023 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1612531292023 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1612531292024 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1612531292025 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.500 " "Worst-case minimum pulse width slack is -2.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292026 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292026 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.500       -55.000 clk  " "   -2.500       -55.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612531292026 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1612531292026 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1612531292044 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1612531292050 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1612531292050 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "285 " "Peak virtual memory: 285 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612531292074 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 16:21:32 2021 " "Processing ended: Fri Feb  5 16:21:32 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612531292074 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612531292074 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612531292074 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1612531292074 ""}
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.sta.rdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sta.rdb
new file mode 100644
index 0000000..4f6ae20
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sta.rdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.sta_cmp.7_slow.tdb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sta_cmp.7_slow.tdb
new file mode 100644
index 0000000..96a07fc
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.sta_cmp.7_slow.tdb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.syn_hier_info b/Firmware/OrionCOM-AY/db/OrionCOM-AY.syn_hier_info
new file mode 100644
index 0000000..e69de29
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.tis_db_list.ddb b/Firmware/OrionCOM-AY/db/OrionCOM-AY.tis_db_list.ddb
new file mode 100644
index 0000000..42a925d
Binary files /dev/null and b/Firmware/OrionCOM-AY/db/OrionCOM-AY.tis_db_list.ddb differ
diff --git a/Firmware/OrionCOM-AY/db/OrionCOM-AY.tmw_info b/Firmware/OrionCOM-AY/db/OrionCOM-AY.tmw_info
new file mode 100644
index 0000000..66f66eb
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/OrionCOM-AY.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:00:11
+start_analysis_synthesis:s:00:00:03-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:02-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:02-start_full_compilation
+start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/Firmware/OrionCOM-AY/db/add_sub_4ph.tdf b/Firmware/OrionCOM-AY/db/add_sub_4ph.tdf
new file mode 100644
index 0000000..61934d2
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/add_sub_4ph.tdf
@@ -0,0 +1,46 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=10 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 11 
+SUBDESIGN add_sub_4ph
+( 
+	cin	:	input;
+	dataa[9..0]	:	input;
+	datab[9..0]	:	input;
+	result[9..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[9..0] : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[9..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[9..9] & datab_node[9..9]) # ((dataa[9..9] # datab_node[9..9]) & add_sub_cella[8].cout)), ((dataa[8..8] & datab_node[8..8]) # ((dataa[8..8] # datab_node[8..8]) & add_sub_cella[7].cout)), ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[9..9] $ datab_node[9..9]) $ add_sub_cella[8].cout), ((dataa[8..8] $ datab_node[8..8]) $ add_sub_cella[7].cout), ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE
diff --git a/Firmware/OrionCOM-AY/db/add_sub_5kh.tdf b/Firmware/OrionCOM-AY/db/add_sub_5kh.tdf
new file mode 100644
index 0000000..5524a63
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/add_sub_5kh.tdf
@@ -0,0 +1,46 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=6 ONE_INPUT_IS_CONSTANT="NO" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 7 
+SUBDESIGN add_sub_5kh
+( 
+	cin	:	input;
+	dataa[5..0]	:	input;
+	datab[5..0]	:	input;
+	result[5..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[5..0] : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[5..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE
diff --git a/Firmware/OrionCOM-AY/db/add_sub_5ph.tdf b/Firmware/OrionCOM-AY/db/add_sub_5ph.tdf
new file mode 100644
index 0000000..c7ac2b2
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/add_sub_5ph.tdf
@@ -0,0 +1,46 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=11 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 12 
+SUBDESIGN add_sub_5ph
+( 
+	cin	:	input;
+	dataa[10..0]	:	input;
+	datab[10..0]	:	input;
+	result[10..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[10..0] : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[10..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[10..10] & datab_node[10..10]) # ((dataa[10..10] # datab_node[10..10]) & add_sub_cella[9].cout)), ((dataa[9..9] & datab_node[9..9]) # ((dataa[9..9] # datab_node[9..9]) & add_sub_cella[8].cout)), ((dataa[8..8] & datab_node[8..8]) # ((dataa[8..8] # datab_node[8..8]) & add_sub_cella[7].cout)), ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[10..10] $ datab_node[10..10]) $ add_sub_cella[9].cout), ((dataa[9..9] $ datab_node[9..9]) $ add_sub_cella[8].cout), ((dataa[8..8] $ datab_node[8..8]) $ add_sub_cella[7].cout), ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE
diff --git a/Firmware/OrionCOM-AY/db/add_sub_6kh.tdf b/Firmware/OrionCOM-AY/db/add_sub_6kh.tdf
new file mode 100644
index 0000000..f6f9221
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/add_sub_6kh.tdf
@@ -0,0 +1,46 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 ONE_INPUT_IS_CONSTANT="NO" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 8 
+SUBDESIGN add_sub_6kh
+( 
+	cin	:	input;
+	dataa[6..0]	:	input;
+	datab[6..0]	:	input;
+	result[6..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[6..0] : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[6..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE
diff --git a/Firmware/OrionCOM-AY/db/add_sub_gph.tdf b/Firmware/OrionCOM-AY/db/add_sub_gph.tdf
new file mode 100644
index 0000000..eab5cbc
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/add_sub_gph.tdf
@@ -0,0 +1,52 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=58 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 61 
+SUBDESIGN add_sub_gph
+( 
+	cin	:	input;
+	dataa[57..0]	:	input;
+	datab[57..0]	:	input;
+	result[57..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[57..0] : carry_sum;
+	cs1 : carry_sum;
+	cs2 : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[57..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[57..57] & datab_node[57..57]) # ((dataa[57..57] # datab_node[57..57]) & add_sub_cella[56].cout)), ((dataa[56..56] & datab_node[56..56]) # ((dataa[56..56] # datab_node[56..56]) & add_sub_cella[55].cout)), ((dataa[55..55] & datab_node[55..55]) # ((dataa[55..55] # datab_node[55..55]) & add_sub_cella[54].cout)), ((dataa[54..54] & datab_node[54..54]) # ((dataa[54..54] # datab_node[54..54]) & add_sub_cella[53].cout)), ((dataa[53..53] & datab_node[53..53]) # ((dataa[53..53] # datab_node[53..53]) & add_sub_cella[52].cout)), ((dataa[52..52] & datab_node[52..52]) # ((dataa[52..52] # datab_node[52..52]) & add_sub_cella[51].cout)), ((dataa[51..51] & datab_node[51..51]) # ((dataa[51..51] # datab_node[51..51]) & add_sub_cella[50].cout)), ((dataa[50..50] & datab_node[50..50]) # ((dataa[50..50] # datab_node[50..50]) & add_sub_cella[49].cout)), ((dataa[49..49] & datab_node[49..49]) # ((dataa[49..49] # datab_node[49..49]) & add_sub_cella[48].cout)), ((dataa[48..48] & datab_node[48..48]) # ((dataa[48..48] # datab_node[48..48]) & cs2.cout)), ((dataa[47..47] & datab_node[47..47]) # ((dataa[47..47] # datab_node[47..47]) & add_sub_cella[46].cout)), ((dataa[46..46] & datab_node[46..46]) # ((dataa[46..46] # datab_node[46..46]) & add_sub_cella[45].cout)), ((dataa[45..45] & datab_node[45..45]) # ((dataa[45..45] # datab_node[45..45]) & add_sub_cella[44].cout)), ((dataa[44..44] & datab_node[44..44]) # ((dataa[44..44] # datab_node[44..44]) & add_sub_cella[43].cout)), ((dataa[43..43] & datab_node[43..43]) # ((dataa[43..43] # datab_node[43..43]) & add_sub_cella[42].cout)), ((dataa[42..42] & datab_node[42..42]) # ((dataa[42..42] # datab_node[42..42]) & add_sub_cella[41].cout)), ((dataa[41..41] & datab_node[41..41]) # ((dataa[41..41] # datab_node[41..41]) & add_sub_cella[40].cout)), ((dataa[40..40] & datab_node[40..40]) # ((dataa[40..40] # datab_node[40..40]) & add_sub_cella[39].cout)), ((dataa[39..39] & datab_node[39..39]) # ((dataa[39..39] # datab_node[39..39]) & add_sub_cella[38].cout)), ((dataa[38..38] & datab_node[38..38]) # ((dataa[38..38] # datab_node[38..38]) & add_sub_cella[37].cout)), ((dataa[37..37] & datab_node[37..37]) # ((dataa[37..37] # datab_node[37..37]) & add_sub_cella[36].cout)), ((dataa[36..36] & datab_node[36..36]) # ((dataa[36..36] # datab_node[36..36]) & add_sub_cella[35].cout)), ((dataa[35..35] & datab_node[35..35]) # ((dataa[35..35] # datab_node[35..35]) & add_sub_cella[34].cout)), ((dataa[34..34] & datab_node[34..34]) # ((dataa[34..34] # datab_node[34..34]) & add_sub_cella[33].cout)), ((dataa[33..33] & datab_node[33..33]) # ((dataa[33..33] # datab_node[33..33]) & add_sub_cella[32].cout)), ((dataa[32..32] & datab_node[32..32]) # ((dataa[32..32] # datab_node[32..32]) & add_sub_cella[31].cout)), ((dataa[31..31] & datab_node[31..31]) # ((dataa[31..31] # datab_node[31..31]) & add_sub_cella[30].cout)), ((dataa[30..30] & datab_node[30..30]) # ((dataa[30..30] # datab_node[30..30]) & add_sub_cella[29].cout)), ((dataa[29..29] & datab_node[29..29]) # ((dataa[29..29] # datab_node[29..29]) & add_sub_cella[28].cout)), ((dataa[28..28] & datab_node[28..28]) # ((dataa[28..28] # datab_node[28..28]) & add_sub_cella[27].cout)), ((dataa[27..27] & datab_node[27..27]) # ((dataa[27..27] # datab_node[27..27]) & add_sub_cella[26].cout)), ((dataa[26..26] & datab_node[26..26]) # ((dataa[26..26] # datab_node[26..26]) & add_sub_cella[25].cout)), ((dataa[25..25] & datab_node[25..25]) # ((dataa[25..25] # datab_node[25..25]) & add_sub_cella[24].cout)), ((dataa[24..24] & datab_node[24..24]) # ((dataa[24..24] # datab_node[24..24]) & add_sub_cella[23].cout)), ((dataa[23..23] & datab_node[23..23]) # ((dataa[23..23] # datab_node[23..23]) & add_sub_cella[22].cout)), ((dataa[22..22] & datab_node[22..22]) # ((dataa[22..22] # datab_node[22..22]) & add_sub_cella[21].cout)), ((dataa[21..21] & datab_node[21..21]) # ((dataa[21..21] # datab_node[21..21]) & add_sub_cella[20].cout)), ((dataa[20..20] & datab_node[20..20]) # ((dataa[20..20] # datab_node[20..20]) & add_sub_cella[19].cout)), ((dataa[19..19] & datab_node[19..19]) # ((dataa[19..19] # datab_node[19..19]) & add_sub_cella[18].cout)), ((dataa[18..18] & datab_node[18..18]) # ((dataa[18..18] # datab_node[18..18]) & add_sub_cella[17].cout)), ((dataa[17..17] & datab_node[17..17]) # ((dataa[17..17] # datab_node[17..17]) & add_sub_cella[16].cout)), ((dataa[16..16] & datab_node[16..16]) # ((dataa[16..16] # datab_node[16..16]) & add_sub_cella[15].cout)), ((dataa[15..15] & datab_node[15..15]) # ((dataa[15..15] # datab_node[15..15]) & add_sub_cella[14].cout)), ((dataa[14..14] & datab_node[14..14]) # ((dataa[14..14] # datab_node[14..14]) & add_sub_cella[13].cout)), ((dataa[13..13] & datab_node[13..13]) # ((dataa[13..13] # datab_node[13..13]) & add_sub_cella[12].cout)), ((dataa[12..12] & datab_node[12..12]) # ((dataa[12..12] # datab_node[12..12]) & add_sub_cella[11].cout)), ((dataa[11..11] & datab_node[11..11]) # ((dataa[11..11] # datab_node[11..11]) & add_sub_cella[10].cout)), ((dataa[10..10] & datab_node[10..10]) # ((dataa[10..10] # datab_node[10..10]) & add_sub_cella[9].cout)), ((dataa[9..9] & datab_node[9..9]) # ((dataa[9..9] # datab_node[9..9]) & add_sub_cella[8].cout)), ((dataa[8..8] & datab_node[8..8]) # ((dataa[8..8] # datab_node[8..8]) & add_sub_cella[7].cout)), ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[57..57] $ datab_node[57..57]) $ add_sub_cella[56].cout), ((dataa[56..56] $ datab_node[56..56]) $ add_sub_cella[55].cout), ((dataa[55..55] $ datab_node[55..55]) $ add_sub_cella[54].cout), ((dataa[54..54] $ datab_node[54..54]) $ add_sub_cella[53].cout), ((dataa[53..53] $ datab_node[53..53]) $ add_sub_cella[52].cout), ((dataa[52..52] $ datab_node[52..52]) $ add_sub_cella[51].cout), ((dataa[51..51] $ datab_node[51..51]) $ add_sub_cella[50].cout), ((dataa[50..50] $ datab_node[50..50]) $ add_sub_cella[49].cout), ((dataa[49..49] $ datab_node[49..49]) $ add_sub_cella[48].cout), ((dataa[48..48] $ datab_node[48..48]) $ cs2.cout), ((dataa[47..47] $ datab_node[47..47]) $ add_sub_cella[46].cout), ((dataa[46..46] $ datab_node[46..46]) $ add_sub_cella[45].cout), ((dataa[45..45] $ datab_node[45..45]) $ add_sub_cella[44].cout), ((dataa[44..44] $ datab_node[44..44]) $ add_sub_cella[43].cout), ((dataa[43..43] $ datab_node[43..43]) $ add_sub_cella[42].cout), ((dataa[42..42] $ datab_node[42..42]) $ add_sub_cella[41].cout), ((dataa[41..41] $ datab_node[41..41]) $ add_sub_cella[40].cout), ((dataa[40..40] $ datab_node[40..40]) $ add_sub_cella[39].cout), ((dataa[39..39] $ datab_node[39..39]) $ add_sub_cella[38].cout), ((dataa[38..38] $ datab_node[38..38]) $ add_sub_cella[37].cout), ((dataa[37..37] $ datab_node[37..37]) $ add_sub_cella[36].cout), ((dataa[36..36] $ datab_node[36..36]) $ add_sub_cella[35].cout), ((dataa[35..35] $ datab_node[35..35]) $ add_sub_cella[34].cout), ((dataa[34..34] $ datab_node[34..34]) $ add_sub_cella[33].cout), ((dataa[33..33] $ datab_node[33..33]) $ add_sub_cella[32].cout), ((dataa[32..32] $ datab_node[32..32]) $ add_sub_cella[31].cout), ((dataa[31..31] $ datab_node[31..31]) $ add_sub_cella[30].cout), ((dataa[30..30] $ datab_node[30..30]) $ add_sub_cella[29].cout), ((dataa[29..29] $ datab_node[29..29]) $ add_sub_cella[28].cout), ((dataa[28..28] $ datab_node[28..28]) $ add_sub_cella[27].cout), ((dataa[27..27] $ datab_node[27..27]) $ add_sub_cella[26].cout), ((dataa[26..26] $ datab_node[26..26]) $ add_sub_cella[25].cout), ((dataa[25..25] $ datab_node[25..25]) $ add_sub_cella[24].cout), ((dataa[24..24] $ datab_node[24..24]) $ add_sub_cella[23].cout), ((dataa[23..23] $ datab_node[23..23]) $ add_sub_cella[22].cout), ((dataa[22..22] $ datab_node[22..22]) $ add_sub_cella[21].cout), ((dataa[21..21] $ datab_node[21..21]) $ add_sub_cella[20].cout), ((dataa[20..20] $ datab_node[20..20]) $ add_sub_cella[19].cout), ((dataa[19..19] $ datab_node[19..19]) $ add_sub_cella[18].cout), ((dataa[18..18] $ datab_node[18..18]) $ add_sub_cella[17].cout), ((dataa[17..17] $ datab_node[17..17]) $ add_sub_cella[16].cout), ((dataa[16..16] $ datab_node[16..16]) $ add_sub_cella[15].cout), ((dataa[15..15] $ datab_node[15..15]) $ add_sub_cella[14].cout), ((dataa[14..14] $ datab_node[14..14]) $ add_sub_cella[13].cout), ((dataa[13..13] $ datab_node[13..13]) $ add_sub_cella[12].cout), ((dataa[12..12] $ datab_node[12..12]) $ add_sub_cella[11].cout), ((dataa[11..11] $ datab_node[11..11]) $ add_sub_cella[10].cout), ((dataa[10..10] $ datab_node[10..10]) $ add_sub_cella[9].cout), ((dataa[9..9] $ datab_node[9..9]) $ add_sub_cella[8].cout), ((dataa[8..8] $ datab_node[8..8]) $ add_sub_cella[7].cout), ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	cs1.cin = B"0";
+	cs1.sin = add_sub_cella[47].cout;
+	cs2.cin = cs1.sout;
+	cs2.sin = B"0";
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE
diff --git a/Firmware/OrionCOM-AY/db/add_sub_onh.tdf b/Firmware/OrionCOM-AY/db/add_sub_onh.tdf
new file mode 100644
index 0000000..ada75ee
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/add_sub_onh.tdf
@@ -0,0 +1,46 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=5 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 6 
+SUBDESIGN add_sub_onh
+( 
+	cin	:	input;
+	dataa[4..0]	:	input;
+	datab[4..0]	:	input;
+	result[4..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[4..0] : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[4..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE
diff --git a/Firmware/OrionCOM-AY/db/add_sub_qnh.tdf b/Firmware/OrionCOM-AY/db/add_sub_qnh.tdf
new file mode 100644
index 0000000..bc75cdd
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/add_sub_qnh.tdf
@@ -0,0 +1,46 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 8 
+SUBDESIGN add_sub_qnh
+( 
+	cin	:	input;
+	dataa[6..0]	:	input;
+	datab[6..0]	:	input;
+	result[6..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[6..0] : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[6..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE
diff --git a/Firmware/OrionCOM-AY/db/add_sub_snh.tdf b/Firmware/OrionCOM-AY/db/add_sub_snh.tdf
new file mode 100644
index 0000000..80d55e5
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/add_sub_snh.tdf
@@ -0,0 +1,46 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=9 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:04:00:SJ cbx_lpm_add_sub 2013:06:12:18:04:00:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:04:00:SJ cbx_stratixii 2013:06:12:18:04:00:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+
+--synthesis_resources = lut 10 
+SUBDESIGN add_sub_snh
+( 
+	cin	:	input;
+	dataa[8..0]	:	input;
+	datab[8..0]	:	input;
+	result[8..0]	:	output;
+) 
+VARIABLE 
+	add_sub_cella[8..0] : carry_sum;
+	external_cin_cell : carry_sum;
+	datab_node[8..0]	: WIRE;
+	main_cin_wire	: WIRE;
+
+BEGIN 
+	add_sub_cella[].cin = ( ((dataa[8..8] & datab_node[8..8]) # ((dataa[8..8] # datab_node[8..8]) & add_sub_cella[7].cout)), ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
+	add_sub_cella[].sin = ( ((dataa[8..8] $ datab_node[8..8]) $ add_sub_cella[7].cout), ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
+	external_cin_cell.cin = cin;
+	external_cin_cell.sin = B"0";
+	datab_node[] = datab[];
+	main_cin_wire = external_cin_cell.cout;
+	result[] = add_sub_cella[].sout;
+END;
+--VALID FILE
diff --git a/Firmware/OrionCOM-AY/db/logic_util_heursitic.dat b/Firmware/OrionCOM-AY/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..e69de29
diff --git a/Firmware/OrionCOM-AY/db/prev_cmp_OrionCOM-AY.qmsg b/Firmware/OrionCOM-AY/db/prev_cmp_OrionCOM-AY.qmsg
new file mode 100644
index 0000000..87e441e
--- /dev/null
+++ b/Firmware/OrionCOM-AY/db/prev_cmp_OrionCOM-AY.qmsg
@@ -0,0 +1,70 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1612509799154 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612509799156 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 10:23:18 2021 " "Processing started: Fri Feb  5 10:23:18 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612509799156 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1612509799156 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off OrionCOM-AY -c OrionCOM-AY " "Command: quartus_map --read_settings_files=on --write_settings_files=off OrionCOM-AY -c OrionCOM-AY" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1612509799157 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1612509800562 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "OrionCOM_AY.sv 3 3 " "Found 3 design units, including 3 entities, in source file OrionCOM_AY.sv" { { "Info" "ISGN_ENTITY_NAME" "1 OrionCOM_AY " "Found entity 1: OrionCOM_AY" {  } { { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1612509800889 ""} { "Info" "ISGN_ENTITY_NAME" "2 ViClkDiv " "Found entity 2: ViClkDiv" {  } { { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 87 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1612509800889 ""} { "Info" "ISGN_ENTITY_NAME" "3 AyClkDiv " "Found entity 3: AyClkDiv" {  } { { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 119 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1612509800889 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1612509800889 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "OrionCOM_AY " "Elaborating entity \"OrionCOM_AY\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1612509801106 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AyClkDiv AyClkDiv:ayClkDiv " "Elaborating entity \"AyClkDiv\" for hierarchy \"AyClkDiv:ayClkDiv\"" {  } { { "OrionCOM_AY.sv" "ayClkDiv" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 75 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801131 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ViClkDiv ViClkDiv:viClkDiv " "Elaborating entity \"ViClkDiv\" for hierarchy \"ViClkDiv:viClkDiv\"" {  } { { "OrionCOM_AY.sv" "viClkDiv" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 78 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801138 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "AyClkDiv:ayClkDiv\|Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"AyClkDiv:ayClkDiv\|Add0\"" {  } { { "OrionCOM_AY.sv" "Add0" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1612509801179 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1612509801179 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1612509801369 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Instantiated megafunction \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 10 " "Parameter \"LPM_WIDTH\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801370 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801370 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801370 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801370 ""}  } { { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1612509801370 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\] AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801384 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:oflow_node AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801391 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:result_node AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[1\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801393 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[0\] AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801397 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|look_add:look_ahead_unit AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801408 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801414 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs AyClkDiv:ayClkDiv\|lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"AyClkDiv:ayClkDiv\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "/opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "OrionCOM_AY.sv" "" { Text "/home/romych/projects/CPLD/OrionCOM-AY/OrionCOM_AY.sv" 133 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1612509801415 ""}
+{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "12 " "Ignored 12 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "12 " "Ignored 12 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1612509801513 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1612509801513 ""}
+{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1612509801557 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset_n " "Promoted clear signal driven by pin \"reset_n\" to global clear signal" {  } {  } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1612509801557 ""}  } {  } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1612509801557 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "53 " "Implemented 53 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "19 " "Implemented 19 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1612509801662 ""} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Implemented 12 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1612509801662 ""} { "Info" "ICUT_CUT_TM_MCELLS" "22 " "Implemented 22 macrocells" {  } {  } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1612509801662 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1612509801662 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "335 " "Peak virtual memory: 335 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612509802104 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 10:23:22 2021 " "Processing ended: Fri Feb  5 10:23:22 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612509802104 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612509802104 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612509802104 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1612509802104 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1612509804497 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612509804498 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 10:23:24 2021 " "Processing started: Fri Feb  5 10:23:24 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612509804498 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1612509804498 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY " "Command: quartus_fit --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1612509804499 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1612509805078 ""}
+{ "Info" "0" "" "Project  = OrionCOM-AY" {  } {  } 0 0 "Project  = OrionCOM-AY" 0 0 "Fitter" 0 0 1612509805082 ""}
+{ "Info" "0" "" "Revision = OrionCOM-AY" {  } {  } 0 0 "Revision = OrionCOM-AY" 0 0 "Fitter" 0 0 1612509805082 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1612509805197 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "OrionCOM-AY EPM7064STC44-7 " "Selected device EPM7064STC44-7 for design \"OrionCOM-AY\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1612509805200 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCK " "Node \"TCK\" is assigned to location or region, but does not exist in design" {  } { { "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1612509805374 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDI " "Node \"TDI\" is assigned to location or region, but does not exist in design" {  } { { "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1612509805374 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDO " "Node \"TDO\" is assigned to location or region, but does not exist in design" {  } { { "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1612509805374 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TMS " "Node \"TMS\" is assigned to location or region, but does not exist in design" {  } { { "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/romych/Quartus_13.sp1/quartus/linux/Assignment Editor.qase" 1 { { 0 "TMS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1612509805374 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1612509805374 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "294 " "Peak virtual memory: 294 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612509805881 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 10:23:25 2021 " "Processing ended: Fri Feb  5 10:23:25 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612509805881 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612509805881 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612509805881 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1612509805881 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1612509808331 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612509808332 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 10:23:28 2021 " "Processing started: Fri Feb  5 10:23:28 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612509808332 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1612509808332 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY " "Command: quartus_asm --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1612509808332 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1612509808517 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "299 " "Peak virtual memory: 299 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612509808747 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 10:23:28 2021 " "Processing ended: Fri Feb  5 10:23:28 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612509808747 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612509808747 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612509808747 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1612509808747 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1612509808853 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1612509810697 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612509810698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 10:23:30 2021 " "Processing started: Fri Feb  5 10:23:30 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612509810698 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1612509810698 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta OrionCOM-AY -c OrionCOM-AY " "Command: quartus_sta OrionCOM-AY -c OrionCOM-AY" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1612509810698 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1612509810752 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1612509810894 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1612509810929 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1612509810933 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." {  } {  } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1612509811008 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "OrionCOM-AY.sdc " "Synopsys Design Constraints File file not found: 'OrionCOM-AY.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1612509811018 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1612509811018 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811027 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811027 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1612509811037 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1612509811046 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -7.800 " "Worst-case setup slack is -7.800" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811047 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -7.800       -77.800 clk  " "   -7.800       -77.800 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811047 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1612509811047 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.000 " "Worst-case hold slack is 3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.000         0.000 clk  " "    3.000         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811048 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1612509811048 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1612509811050 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1612509811051 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.500 " "Worst-case minimum pulse width slack is -2.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.500       -55.000 clk  " "   -2.500       -55.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1612509811051 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1612509811051 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1612509811067 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1612509811073 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1612509811073 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "285 " "Peak virtual memory: 285 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612509811094 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 10:23:31 2021 " "Processing ended: Fri Feb  5 10:23:31 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612509811094 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612509811094 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612509811094 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1612509811094 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1612509813834 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612509813835 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 10:23:33 2021 " "Processing started: Fri Feb  5 10:23:33 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612509813835 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1612509813835 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY " "Command: quartus_eda --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1612509813836 ""}
+{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "OrionCOM-AY.vo OrionCOM-AY_v.sdo /home/romych/projects/CPLD/OrionCOM-AY/simulation/modelsim/ simulation " "Generated files \"OrionCOM-AY.vo\" and \"OrionCOM-AY_v.sdo\" in directory \"/home/romych/projects/CPLD/OrionCOM-AY/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204018 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "Quartus II" 0 -1 1612509814054 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "304 " "Peak virtual memory: 304 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612509814084 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 10:23:34 2021 " "Processing ended: Fri Feb  5 10:23:34 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612509814084 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612509814084 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612509814084 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1612509814084 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Quartus II Full Compilation was successful. 0 errors, 11 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1612509814176 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1612509848878 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1612509848879 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb  5 10:24:08 2021 " "Processing started: Fri Feb  5 10:24:08 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1612509848879 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1612509848879 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp OrionCOM-AY -c OrionCOM-AY --netlist_type=sgate " "Command: quartus_rpp OrionCOM-AY -c OrionCOM-AY --netlist_type=sgate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1612509848880 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "255 " "Peak virtual memory: 255 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1612509848963 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb  5 10:24:08 2021 " "Processing ended: Fri Feb  5 10:24:08 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1612509848963 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1612509848963 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1612509848963 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1612509848963 ""}
diff --git a/Firmware/OrionCOM-AY/incremental_db/README b/Firmware/OrionCOM-AY/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/Firmware/OrionCOM-AY/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/Firmware/OrionCOM-AY/incremental_db/compiled_partitions/OrionCOM-AY.db_info b/Firmware/OrionCOM-AY/incremental_db/compiled_partitions/OrionCOM-AY.db_info
new file mode 100644
index 0000000..afab88b
--- /dev/null
+++ b/Firmware/OrionCOM-AY/incremental_db/compiled_partitions/OrionCOM-AY.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+Version_Index = 302049280
+Creation_Time = Sat Nov 28 14:49:22 2020
diff --git a/Firmware/OrionCOM-AY/incremental_db/compiled_partitions/OrionCOM-AY.root_partition.map.kpt b/Firmware/OrionCOM-AY/incremental_db/compiled_partitions/OrionCOM-AY.root_partition.map.kpt
new file mode 100644
index 0000000..0a2d72b
Binary files /dev/null and b/Firmware/OrionCOM-AY/incremental_db/compiled_partitions/OrionCOM-AY.root_partition.map.kpt differ
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.asm.rpt b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.asm.rpt
new file mode 100644
index 0000000..b9ce46f
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.asm.rpt
@@ -0,0 +1,111 @@
+Assembler report for OrionCOM-AY
+Fri Feb  5 16:21:29 2021
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: OrionCOM-AY.pof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Feb  5 16:21:29 2021 ;
+; Revision Name         ; OrionCOM-AY                           ;
+; Top-level Entity Name ; OrionCOM_AY                           ;
+; Family                ; MAX7000S                              ;
+; Device                ; EPM7064STC44-7                        ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; Off      ; Off           ;
+; Security bit                                                                ; Off      ; Off           ;
+; Use configuration device                                                    ; On       ; On            ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------+
+; Assembler Generated Files ;
++---------------------------+
+; File Name                 ;
++---------------------------+
+; OrionCOM-AY.pof           ;
++---------------------------+
+
+
++-------------------------------------------+
+; Assembler Device Options: OrionCOM-AY.pof ;
++----------------+--------------------------+
+; Option         ; Setting                  ;
++----------------+--------------------------+
+; Device         ; EPM7064STC44-7           ;
+; JTAG usercode  ; 0x00000000               ;
+; Checksum       ; 0x000D666C               ;
++----------------+--------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Fri Feb  5 16:21:29 2021
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 299 megabytes
+    Info: Processing ended: Fri Feb  5 16:21:29 2021
+    Info: Elapsed time: 00:00:00
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.done b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.done
new file mode 100644
index 0000000..9c0aeea
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.done
@@ -0,0 +1 @@
+Fri Feb  5 16:21:35 2021
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.eda.rpt b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.eda.rpt
new file mode 100644
index 0000000..f3cf264
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.eda.rpt
@@ -0,0 +1,94 @@
+EDA Netlist Writer report for OrionCOM-AY
+Fri Feb  5 16:21:35 2021
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Fri Feb  5 16:21:34 2021 ;
+; Revision Name             ; OrionCOM-AY                           ;
+; Top-level Entity Name     ; OrionCOM_AY                           ;
+; Family                    ; MAX7000S                              ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                           ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option                                                                                            ; Setting                   ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
+; Generate netlist for functional simulation only                                                   ; Off                       ;
+; Time scale                                                                                        ; 1 ps                      ;
+; Truncate long hierarchy paths                                                                     ; Off                       ;
+; Map illegal HDL characters                                                                        ; Off                       ;
+; Flatten buses into individual nodes                                                               ; Off                       ;
+; Maintain hierarchy                                                                                ; Off                       ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
+; Enable glitch filtering                                                                           ; Off                       ;
+; Do not write top level VHDL entity                                                                ; Off                       ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
+; Architecture name in VHDL output netlist                                                          ; structure                 ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++-------------------------------------------------------------+
+; Simulation Generated Files                                  ;
++-------------------------------------------------------------+
+; Generated Files                                             ;
++-------------------------------------------------------------+
+; /opt/cpld/OrionCOM-AY/simulation/modelsim/OrionCOM-AY.vo    ;
+; /opt/cpld/OrionCOM-AY/simulation/modelsim/OrionCOM-AY_v.sdo ;
++-------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit EDA Netlist Writer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Fri Feb  5 16:21:34 2021
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY
+Info (204018): Generated files "OrionCOM-AY.vo" and "OrionCOM-AY_v.sdo" in directory "/opt/cpld/OrionCOM-AY/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 304 megabytes
+    Info: Processing ended: Fri Feb  5 16:21:35 2021
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.fit.rpt b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.fit.rpt
new file mode 100644
index 0000000..a64f251
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.fit.rpt
@@ -0,0 +1,442 @@
+Fitter report for OrionCOM-AY
+Fri Feb  5 16:21:26 2021
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. Pin-Out File
+  6. Fitter Resource Usage Summary
+  7. Input Pins
+  8. Output Pins
+  9. All Package Pins
+ 10. I/O Standard
+ 11. Dedicated Inputs I/O
+ 12. Output Pin Default Load For Reported TCO
+ 13. Fitter Resource Utilization by Entity
+ 14. Control Signals
+ 15. Global & Other Fast Signals
+ 16. Non-Global High Fan-Out Signals
+ 17. Other Routing Usage Summary
+ 18. LAB Macrocells
+ 19. Parallel Expander
+ 20. Logic Cell Interconnection
+ 21. Fitter Device Options
+ 22. Fitter Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------+
+; Fitter Summary                                                              ;
++---------------------------+-------------------------------------------------+
+; Fitter Status             ; Successful - Fri Feb  5 16:21:26 2021           ;
+; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name             ; OrionCOM-AY                                     ;
+; Top-level Entity Name     ; OrionCOM_AY                                     ;
+; Family                    ; MAX7000S                                        ;
+; Device                    ; EPM7064STC44-7                                  ;
+; Timing Models             ; Final                                           ;
+; Total macrocells          ; 22 / 64 ( 34 % )                                ;
+; Total pins                ; 35 / 36 ( 97 % )                                ;
++---------------------------+-------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                             ;
++----------------------------------------------------------------------------+----------------+---------------+
+; Option                                                                     ; Setting        ; Default Value ;
++----------------------------------------------------------------------------+----------------+---------------+
+; Device                                                                     ; EPM7064STC44-7 ;               ;
+; Fitter Effort                                                              ; Standard Fit   ; Auto Fit      ;
+; Use smart compilation                                                      ; Off            ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On             ; On            ;
+; Enable compact report table                                                ; Off            ; Off           ;
+; Optimize Multi-Corner Timing                                               ; Off            ; Off           ;
+; Optimize Timing for ECOs                                                   ; Off            ; Off           ;
+; Regenerate full fit report during ECO compiles                             ; Off            ; Off           ;
+; Optimize IOC Register Placement for Timing                                 ; Normal         ; Normal        ;
+; Fitter Initial Placement Seed                                              ; 1              ; 1             ;
+; Slow Slew Rate                                                             ; Off            ; Off           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off            ; Off           ;
++----------------------------------------------------------------------------+----------------+---------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 8      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /opt/cpld/OrionCOM-AY/output_files/OrionCOM-AY.pin.
+
+
++-------------------------------------------------+
+; Fitter Resource Usage Summary                   ;
++------------------------------+------------------+
+; Resource                     ; Usage            ;
++------------------------------+------------------+
+; Logic cells                  ; 22 / 64 ( 34 % ) ;
+; Registers                    ; 11 / 64 ( 17 % ) ;
+; Number of pterms used        ; 51               ;
+; I/O pins                     ; 35 / 36 ( 97 % ) ;
+;     -- Clock pins            ; 1 / 2 ( 50 % )   ;
+;     -- Dedicated input pins  ; 2 / 2 ( 100 % )  ;
+;                              ;                  ;
+; Global signals               ; 2                ;
+; Shareable expanders          ; 0 / 64 ( 0 % )   ;
+; Parallel expanders           ; 1 / 60 ( 2 % )   ;
+; Cells using turbo bit        ; 22 / 64 ( 34 % ) ;
+; Maximum fan-out              ; 12               ;
+; Highest non-global fan-out   ; 10               ;
+; Total fan-out                ; 144              ;
+; Average fan-out              ; 2.53             ;
++------------------------------+------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                    ;
++---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
+; Name    ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ;
++---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
+; a[0]    ; 2     ; --       ; 1   ; 2                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; a[1]    ; 3     ; --       ; 1   ; 2                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; a[2]    ; 5     ; --       ; 1   ; 5                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; a[3]    ; 6     ; --       ; 1   ; 5                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; a[4]    ; 8     ; --       ; 2   ; 5                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; a[5]    ; 10    ; --       ; 2   ; 5                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; a[6]    ; 11    ; --       ; 2   ; 5                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; a[7]    ; 12    ; --       ; 2   ; 5                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; a[8]    ; 15    ; --       ; 2   ; 1                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; a[9]    ; 18    ; --       ; 3   ; 2                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; clk     ; 37    ; --       ; --  ; 11                    ; 0                  ; yes    ; no             ; TTL          ; User                 ;
+; iorq_n  ; 21    ; --       ; 3   ; 5                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; m1_n    ; 23    ; --       ; 3   ; 2                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; rd_n    ; 19    ; --       ; 3   ; 1                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; rdy1    ; 38    ; --       ; --  ; 1                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; rdy2    ; 31    ; --       ; 4   ; 1                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; reset_n ; 39    ; --       ; --  ; 12                    ; 0                  ; yes    ; no             ; TTL          ; User                 ;
+; wait_n  ; 22    ; --       ; 3   ; 1                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
+; wr_n    ; 20    ; --       ; 3   ; 3                     ; 0                  ; no     ; no             ; TTL          ; User                 ;
++---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                  ;
++----------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
+; Name     ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load  ; Output Enable Source ; Output Enable Group ;
++----------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
+; bc1      ; 42    ; --       ; 1   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; bdir     ; 43    ; --       ; 1   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; clk1     ; 27    ; --       ; 4   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; clk2     ; 44    ; --       ; 1   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; cs_vi_n  ; 25    ; --       ; 3   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; cs_vv1_n ; 35    ; --       ; 4   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; cs_vv2_n ; 30    ; --       ; 4   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; debug    ; 33    ; --       ; 4   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; irq3     ; 14    ; --       ; 2   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; irq4     ; 13    ; --       ; 2   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; reset    ; 34    ; --       ; 4   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
+; w1       ; 28    ; --       ; 4   ; no              ; no             ; no         ; no            ; TTL          ; User                 ; 10 pF ; -                    ; -                   ;
++----------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+-------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                      ;
++----------+------------+----------+----------------+--------+--------------+---------+-----------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage ; User Assignment ;
++----------+------------+----------+----------------+--------+--------------+---------+-----------------+
+; 1        ; 6          ; --       ; TDI            ; input  ; TTL          ;         ; Y               ;
+; 2        ; 7          ; --       ; a[0]           ; input  ; TTL          ;         ; Y               ;
+; 3        ; 8          ; --       ; a[1]           ; input  ; TTL          ;         ; Y               ;
+; 4        ; 9          ; --       ; GND            ; gnd    ;              ;         ;                 ;
+; 5        ; 10         ; --       ; a[2]           ; input  ; TTL          ;         ; Y               ;
+; 6        ; 11         ; --       ; a[3]           ; input  ; TTL          ;         ; Y               ;
+; 7        ; 12         ; --       ; TMS            ; input  ; TTL          ;         ; Y               ;
+; 8        ; 13         ; --       ; a[4]           ; input  ; TTL          ;         ; Y               ;
+; 9        ; 14         ; --       ; VCC            ; power  ;              ;         ;                 ;
+; 10       ; 15         ; --       ; a[5]           ; input  ; TTL          ;         ; Y               ;
+; 11       ; 16         ; --       ; a[6]           ; input  ; TTL          ;         ; Y               ;
+; 12       ; 17         ; --       ; a[7]           ; input  ; TTL          ;         ; Y               ;
+; 13       ; 18         ; --       ; irq4           ; output ; TTL          ;         ; Y               ;
+; 14       ; 19         ; --       ; irq3           ; output ; TTL          ;         ; Y               ;
+; 15       ; 20         ; --       ; a[8]           ; input  ; TTL          ;         ; Y               ;
+; 16       ; 21         ; --       ; GND            ; gnd    ;              ;         ;                 ;
+; 17       ; 22         ; --       ; VCC            ; power  ;              ;         ;                 ;
+; 18       ; 23         ; --       ; a[9]           ; input  ; TTL          ;         ; Y               ;
+; 19       ; 24         ; --       ; rd_n           ; input  ; TTL          ;         ; Y               ;
+; 20       ; 25         ; --       ; wr_n           ; input  ; TTL          ;         ; Y               ;
+; 21       ; 26         ; --       ; iorq_n         ; input  ; TTL          ;         ; Y               ;
+; 22       ; 27         ; --       ; wait_n         ; input  ; TTL          ;         ; Y               ;
+; 23       ; 28         ; --       ; m1_n           ; input  ; TTL          ;         ; Y               ;
+; 24       ; 29         ; --       ; GND            ; gnd    ;              ;         ;                 ;
+; 25       ; 30         ; --       ; cs_vi_n        ; output ; TTL          ;         ; Y               ;
+; 26       ; 31         ; --       ; TCK            ; input  ; TTL          ;         ; Y               ;
+; 27       ; 32         ; --       ; clk1           ; output ; TTL          ;         ; Y               ;
+; 28       ; 33         ; --       ; w1             ; output ; TTL          ;         ; Y               ;
+; 29       ; 34         ; --       ; VCC            ; power  ;              ;         ;                 ;
+; 30       ; 35         ; --       ; cs_vv2_n       ; output ; TTL          ;         ; Y               ;
+; 31       ; 36         ; --       ; rdy2           ; input  ; TTL          ;         ; Y               ;
+; 32       ; 37         ; --       ; TDO            ; output ; TTL          ;         ; Y               ;
+; 33       ; 38         ; --       ; debug          ; output ; TTL          ;         ; Y               ;
+; 34       ; 39         ; --       ; reset          ; output ; TTL          ;         ; Y               ;
+; 35       ; 40         ; --       ; cs_vv1_n       ; output ; TTL          ;         ; Y               ;
+; 36       ; 41         ; --       ; GND            ; gnd    ;              ;         ;                 ;
+; 37       ; 42         ; --       ; clk            ; input  ; TTL          ;         ; Y               ;
+; 38       ; 43         ; --       ; rdy1           ; input  ; TTL          ;         ; Y               ;
+; 39       ; 0          ; --       ; reset_n        ; input  ; TTL          ;         ; Y               ;
+; 40       ; 1          ; --       ; GND+           ;        ;              ;         ;                 ;
+; 41       ; 2          ; --       ; VCC            ; power  ;              ;         ;                 ;
+; 42       ; 3          ; --       ; bc1            ; output ; TTL          ;         ; Y               ;
+; 43       ; 4          ; --       ; bdir           ; output ; TTL          ;         ; Y               ;
+; 44       ; 5          ; --       ; clk2           ; output ; TTL          ;         ; Y               ;
++----------+------------+----------+----------------+--------+--------------+---------+-----------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++--------------------------------------------------------------------------------------------------+
+; I/O Standard                                                                                     ;
++--------------+------------+----------------------+-------------------+-------------------+-------+
+; I/O Standard ; Input Vref ; Dedicated Input Pins ; Pins in I/O Bank1 ; Pins in I/O Bank2 ; Total ;
++--------------+------------+----------------------+-------------------+-------------------+-------+
+; TTL          ; -          ; 3                    ; 0                 ; 0                 ; 3     ;
++--------------+------------+----------------------+-------------------+-------------------+-------+
+
+
++-----------------------------------------------------------------------+
+; Dedicated Inputs I/O                                                  ;
++---------+-------+-------+-------+--------------+------------+---------+
+; Name    ; Pin # ; Type  ; VCCIO ; I/O Standard ; Input Vref ; Current ;
++---------+-------+-------+-------+--------------+------------+---------+
+; clk     ; 37    ; Input ; --    ; TTL          ; -          ; 0 mA    ;
+; rdy1    ; 38    ; Input ; --    ; TTL          ; -          ; 0 mA    ;
+; reset_n ; 39    ; Input ; --    ; TTL          ; -          ; 0 mA    ;
++---------+-------+-------+-------+--------------+------------+---------+
+
+
++-----------------------------------------------+
+; Output Pin Default Load For Reported TCO      ;
++--------------+-------+------------------------+
+; I/O Standard ; Load  ; Termination Resistance ;
++--------------+-------+------------------------+
+; TTL          ; 10 pF ; Not Available          ;
++--------------+-------+------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                               ;
++---------------------------------------+------------+------+------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node            ; Macrocells ; Pins ; Full Hierarchy Name                                                                      ; Library Name ;
++---------------------------------------+------------+------+------------------------------------------------------------------------------------------+--------------+
+; |OrionCOM_AY                          ; 22         ; 35   ; |OrionCOM_AY                                                                             ; work         ;
+;    |AyClkDiv:ayClkDiv|                ; 11         ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv                                                           ; work         ;
+;       |lpm_add_sub:Add0|              ; 1          ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0                                          ; work         ;
+;          |addcore:adder[1]|           ; 1          ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]                         ; work         ;
+;             |a_csnbuffer:result_node| ; 1          ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node ; work         ;
+;    |ViClkDiv:viClkDiv|                ; 2          ; 0    ; |OrionCOM_AY|ViClkDiv:viClkDiv                                                           ; work         ;
++---------------------------------------+------------+------+------------------------------------------------------------------------------------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                ;
++---------+----------+---------+--------------+--------+----------------------+------------------+
+; Name    ; Location ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ;
++---------+----------+---------+--------------+--------+----------------------+------------------+
+; clk     ; PIN_37   ; 11      ; Clock        ; yes    ; On                   ; --               ;
+; reset_n ; PIN_39   ; 12      ; Async. clear ; yes    ; On                   ; --               ;
++---------+----------+---------+--------------+--------+----------------------+------------------+
+
+
++------------------------------------------------------------------------+
+; Global & Other Fast Signals                                            ;
++---------+----------+---------+----------------------+------------------+
+; Name    ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
++---------+----------+---------+----------------------+------------------+
+; clk     ; PIN_37   ; 11      ; On                   ; --               ;
+; reset_n ; PIN_39   ; 12      ; On                   ; --               ;
++---------+----------+---------+----------------------+------------------+
+
+
++-------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                                       ;
++---------------------------------------------------------------------------------------------+---------+
+; Name                                                                                        ; Fan-Out ;
++---------------------------------------------------------------------------------------------+---------+
+; ViClkDiv:viClkDiv|div1[0]                                                                   ; 10      ;
+; AyClkDiv:ayClkDiv|sum[1]                                                                    ; 9       ;
+; AyClkDiv:ayClkDiv|sum[2]                                                                    ; 8       ;
+; AyClkDiv:ayClkDiv|sum[3]                                                                    ; 7       ;
+; AyClkDiv:ayClkDiv|sum[4]                                                                    ; 6       ;
+; a[7]                                                                                        ; 5       ;
+; a[6]                                                                                        ; 5       ;
+; a[5]                                                                                        ; 5       ;
+; a[4]                                                                                        ; 5       ;
+; a[3]                                                                                        ; 5       ;
+; a[2]                                                                                        ; 5       ;
+; iorq_n                                                                                      ; 5       ;
+; AyClkDiv:ayClkDiv|sum[5]                                                                    ; 5       ;
+; AyClkDiv:ayClkDiv|sum[6]                                                                    ; 4       ;
+; wr_n                                                                                        ; 3       ;
+; AyClkDiv:ayClkDiv|sum[9]                                                                    ; 3       ;
+; AyClkDiv:ayClkDiv|sum[8]                                                                    ; 3       ;
+; AyClkDiv:ayClkDiv|sum[7]                                                                    ; 3       ;
+; a[9]                                                                                        ; 2       ;
+; a[1]                                                                                        ; 2       ;
+; a[0]                                                                                        ; 2       ;
+; m1_n                                                                                        ; 2       ;
+; rdy2                                                                                        ; 1       ;
+; rdy1                                                                                        ; 1       ;
+; a[8]                                                                                        ; 1       ;
+; wait_n                                                                                      ; 1       ;
+; rd_n                                                                                        ; 1       ;
+; AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~32 ; 1       ;
+; AyClkDiv:ayClkDiv|sum[9]~1                                                                  ; 1       ;
+; bc1~9                                                                                       ; 1       ;
+; bdir~7                                                                                      ; 1       ;
+; cs_vv1_n~2                                                                                  ; 1       ;
+; ViClkDiv:viClkDiv|div1[1]                                                                   ; 1       ;
+; cs_vi_n~3                                                                                   ; 1       ;
+; cs_vv2_n~2                                                                                  ; 1       ;
+; reset_n~4                                                                                   ; 1       ;
+; rdy2~1                                                                                      ; 1       ;
+; rdy1~1                                                                                      ; 1       ;
+; w1~1                                                                                        ; 1       ;
++---------------------------------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------+
+; Other Routing Usage Summary                     ;
++-----------------------------+-------------------+
+; Other Routing Resource Type ; Usage             ;
++-----------------------------+-------------------+
+; Output enables              ; 0 / 6 ( 0 % )     ;
+; PIA buffers                 ; 45 / 144 ( 31 % ) ;
++-----------------------------+-------------------+
+
+
++----------------------------------------------------------------------+
+; LAB Macrocells                                                       ;
++----------------------------------------+-----------------------------+
+; Number of Macrocells  (Average = 5.50) ; Number of LABs  (Total = 4) ;
++----------------------------------------+-----------------------------+
+; 0                                      ; 0                           ;
+; 1                                      ; 1                           ;
+; 2                                      ; 1                           ;
+; 3                                      ; 0                           ;
+; 4                                      ; 0                           ;
+; 5                                      ; 0                           ;
+; 6                                      ; 1                           ;
+; 7                                      ; 0                           ;
+; 8                                      ; 0                           ;
+; 9                                      ; 0                           ;
+; 10                                     ; 0                           ;
+; 11                                     ; 0                           ;
+; 12                                     ; 0                           ;
+; 13                                     ; 1                           ;
++----------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------+
+; Parallel Expander                                       ;
++--------------------------+------------------------------+
+; Parallel Expander Length ; Number of Parallel Expanders ;
++--------------------------+------------------------------+
+; 0                        ; 0                            ;
+; 1                        ; 1                            ;
++--------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Logic Cell Interconnection                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
++-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; LAB ; Logic Cell ; Input                                                                                                                                                                                                                                                                                                                                                ; Output                                                                                                                                                                                                                                                              ;
++-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+;  A  ; LC4        ; clk, reset_n                                                                                                                                                                                                                                                                                                                                         ; ViClkDiv:viClkDiv|div1[1], AyClkDiv:ayClkDiv|sum[1], AyClkDiv:ayClkDiv|sum[2], AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[6], AyClkDiv:ayClkDiv|sum[7], AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|sum[9] ;
+;  A  ; LC14       ; wr_n, a[6], a[7], iorq_n, a[4], a[5], a[2], a[3], m1_n, a[0], a[1], a[9]                                                                                                                                                                                                                                                                             ; bdir                                                                                                                                                                                                                                                                ;
+;  A  ; LC1        ; clk, reset_n, AyClkDiv:ayClkDiv|sum[1], ViClkDiv:viClkDiv|div1[0]                                                                                                                                                                                                                                                                                    ; AyClkDiv:ayClkDiv|sum[1], AyClkDiv:ayClkDiv|sum[2], AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[6], AyClkDiv:ayClkDiv|sum[7], AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|sum[9]                            ;
+;  A  ; LC16       ; a[8], m1_n, a[1], a[9], wr_n, a[0], a[6], a[7], iorq_n, a[4], a[5], a[2], a[3], rd_n                                                                                                                                                                                                                                                                 ; bc1                                                                                                                                                                                                                                                                 ;
+;  A  ; LC2        ; clk, reset_n, AyClkDiv:ayClkDiv|sum[1], ViClkDiv:viClkDiv|div1[0], AyClkDiv:ayClkDiv|sum[2]                                                                                                                                                                                                                                                          ; AyClkDiv:ayClkDiv|sum[2], AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[6], AyClkDiv:ayClkDiv|sum[7], AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|sum[9]                                                      ;
+;  A  ; LC5        ; clk, reset_n, AyClkDiv:ayClkDiv|sum[2], AyClkDiv:ayClkDiv|sum[1], ViClkDiv:viClkDiv|div1[0], AyClkDiv:ayClkDiv|sum[3]                                                                                                                                                                                                                                ; AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[6], AyClkDiv:ayClkDiv|sum[7], AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|sum[9]                                                                                ;
+;  A  ; LC7        ; clk, reset_n, AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[2], AyClkDiv:ayClkDiv|sum[1], ViClkDiv:viClkDiv|div1[0], AyClkDiv:ayClkDiv|sum[4]                                                                                                                                                                                                      ; AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[6], AyClkDiv:ayClkDiv|sum[7], AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|sum[9]                                                                                                          ;
+;  A  ; LC8        ; clk, reset_n, AyClkDiv:ayClkDiv|sum[1], AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[2], ViClkDiv:viClkDiv|div1[0], AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[5]                                                                                                                                                                            ; AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[6], AyClkDiv:ayClkDiv|sum[7], AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|sum[9]                                                                                                                                    ;
+;  A  ; LC6        ; clk, reset_n, AyClkDiv:ayClkDiv|sum[1], AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[2], ViClkDiv:viClkDiv|div1[0], AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[6]                                                                                                                                                  ; AyClkDiv:ayClkDiv|sum[6], AyClkDiv:ayClkDiv|sum[7], AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|sum[9]                                                                                                                                                              ;
+;  A  ; LC12       ; clk, reset_n, AyClkDiv:ayClkDiv|sum[1], AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[2], AyClkDiv:ayClkDiv|sum[6], ViClkDiv:viClkDiv|div1[0], AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[7]                                                                                                                        ; AyClkDiv:ayClkDiv|sum[7], AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~32                                                                                                                     ;
+;  A  ; LC13       ; clk, reset_n, AyClkDiv:ayClkDiv|sum[1], AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[7], ViClkDiv:viClkDiv|div1[0], AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[2], AyClkDiv:ayClkDiv|sum[6], AyClkDiv:ayClkDiv|sum[8]                                                                                              ; AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|sum[9], AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~32                                                                                                                     ;
+;  A  ; LC11       ; clk, reset_n, AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~32, AyClkDiv:ayClkDiv|sum[5], AyClkDiv:ayClkDiv|sum[8], AyClkDiv:ayClkDiv|sum[6], AyClkDiv:ayClkDiv|sum[4], AyClkDiv:ayClkDiv|sum[1], AyClkDiv:ayClkDiv|sum[3], AyClkDiv:ayClkDiv|sum[2], ViClkDiv:viClkDiv|div1[0], AyClkDiv:ayClkDiv|sum[9] ; AyClkDiv:ayClkDiv|sum[9], clk2, AyClkDiv:ayClkDiv|sum[9]~1                                                                                                                                                                                                          ;
+;  A  ; LC10       ; AyClkDiv:ayClkDiv|sum[7], AyClkDiv:ayClkDiv|sum[8]                                                                                                                                                                                                                                                                                                   ; AyClkDiv:ayClkDiv|sum[9]                                                                                                                                                                                                                                            ;
+;  B  ; LC19       ; rdy1                                                                                                                                                                                                                                                                                                                                                 ; irq3                                                                                                                                                                                                                                                                ;
+;  B  ; LC20       ; rdy2                                                                                                                                                                                                                                                                                                                                                 ; irq4                                                                                                                                                                                                                                                                ;
+;  C  ; LC46       ; a[3], a[6], a[7], iorq_n, a[4], a[5], a[2]                                                                                                                                                                                                                                                                                                           ; cs_vi_n                                                                                                                                                                                                                                                             ;
+;  D  ; LC51       ; wr_n, wait_n                                                                                                                                                                                                                                                                                                                                         ; w1                                                                                                                                                                                                                                                                  ;
+;  D  ; LC62       ; reset_n                                                                                                                                                                                                                                                                                                                                              ; reset                                                                                                                                                                                                                                                               ;
+;  D  ; LC52       ; a[6], a[7], iorq_n, a[4], a[5], a[2], a[3]                                                                                                                                                                                                                                                                                                           ; cs_vv2_n                                                                                                                                                                                                                                                            ;
+;  D  ; LC49       ; clk, reset_n, ViClkDiv:viClkDiv|div1[0]                                                                                                                                                                                                                                                                                                              ; clk1                                                                                                                                                                                                                                                                ;
+;  D  ; LC64       ; a[3], a[6], a[7], iorq_n, a[4], a[5], a[2]                                                                                                                                                                                                                                                                                                           ; cs_vv1_n                                                                                                                                                                                                                                                            ;
+;  D  ; LC57       ; AyClkDiv:ayClkDiv|sum[9]                                                                                                                                                                                                                                                                                                                             ; debug                                                                                                                                                                                                                                                               ;
++-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------+
+; Fitter Device Options                                         ;
++----------------------------------------------+----------------+
+; Option                                       ; Setting        ;
++----------------------------------------------+----------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off            ;
+; Enable device-wide reset (DEV_CLRn)          ; Off            ;
+; Enable device-wide output enable (DEV_OE)    ; Off            ;
+; Enable INIT_DONE output                      ; Off            ;
+; Configuration scheme                         ; Passive Serial ;
+; Security bit                                 ; Off            ;
+; Base pin-out file on sameframe device        ; Off            ;
++----------------------------------------------+----------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119006): Selected device EPM7064STC44-7 for design "OrionCOM-AY"
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "TCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "TDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "TDO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "TMS" is assigned to location or region, but does not exist in design
+Info: Quartus II 32-bit Fitter was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 294 megabytes
+    Info: Processing ended: Fri Feb  5 16:21:26 2021
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.fit.summary b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.fit.summary
new file mode 100644
index 0000000..e14b302
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.fit.summary
@@ -0,0 +1,9 @@
+Fitter Status : Successful - Fri Feb  5 16:21:26 2021
+Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : OrionCOM-AY
+Top-level Entity Name : OrionCOM_AY
+Family : MAX7000S
+Device : EPM7064STC44-7
+Timing Models : Final
+Total macrocells : 22 / 64 ( 34 % )
+Total pins : 35 / 36 ( 97 % )
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.flow.rpt b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.flow.rpt
new file mode 100644
index 0000000..34ab0ad
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.flow.rpt
@@ -0,0 +1,118 @@
+Flow report for OrionCOM-AY
+Fri Feb  5 16:21:35 2021
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------+
+; Flow Summary                                                                ;
++---------------------------+-------------------------------------------------+
+; Flow Status               ; Successful - Fri Feb  5 16:21:34 2021           ;
+; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name             ; OrionCOM-AY                                     ;
+; Top-level Entity Name     ; OrionCOM_AY                                     ;
+; Family                    ; MAX7000S                                        ;
+; Device                    ; EPM7064STC44-7                                  ;
+; Timing Models             ; Final                                           ;
+; Total macrocells          ; 22 / 64 ( 34 % )                                ;
+; Total pins                ; 35 / 36 ( 97 % )                                ;
++---------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/05/2021 16:21:20 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; OrionCOM-AY         ;
++-------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                    ;
++--------------------------+---------------------------+---------------+-------------+----------------+
+; Assignment Name          ; Value                     ; Default Value ; Entity Name ; Section Id     ;
++--------------------------+---------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID    ; 0.161253128028552         ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT   ; Verilog Hdl               ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL      ; ModelSim-Altera (Verilog) ; <None>        ; --          ; --             ;
+; FITTER_EFFORT            ; Standard Fit              ; Auto Fit      ; --          ; --             ;
+; OPTIMIZE_HOLD_TIMING     ; Off                       ; --            ; --          ; --             ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files              ; --            ; --          ; --             ;
+; TOP_LEVEL_ENTITY         ; OrionCOM_AY               ; OrionCOM-AY   ; --          ; --             ;
++--------------------------+---------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:03     ; 1.0                     ; 335 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:02     ; 1.0                     ; 294 MB              ; 00:00:01                           ;
+; Assembler                 ; 00:00:00     ; 1.0                     ; 299 MB              ; 00:00:00                           ;
+; TimeQuest Timing Analyzer ; 00:00:01     ; 1.0                     ; 285 MB              ; 00:00:01                           ;
+; EDA Netlist Writer        ; 00:00:00     ; 1.0                     ; 293 MB              ; 00:00:00                           ;
+; Total                     ; 00:00:06     ; --                      ; --                  ; 00:00:03                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++-----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                         ;
++---------------------------+------------------+------------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
++---------------------------+------------------+------------+------------+----------------+
+; Analysis & Synthesis      ; my-note      ; Linux Mint ; 19         ; x86_64         ;
+; Fitter                    ; my-note      ; Linux Mint ; 19         ; x86_64         ;
+; Assembler                 ; my-note      ; Linux Mint ; 19         ; x86_64         ;
+; TimeQuest Timing Analyzer ; my-note      ; Linux Mint ; 19         ; x86_64         ;
+; EDA Netlist Writer        ; my-note      ; Linux Mint ; 19         ; x86_64         ;
++---------------------------+------------------+------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off OrionCOM-AY -c OrionCOM-AY
+quartus_fit --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY
+quartus_asm --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY
+quartus_sta OrionCOM-AY -c OrionCOM-AY
+quartus_eda --read_settings_files=off --write_settings_files=off OrionCOM-AY -c OrionCOM-AY
+
+
+
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.jdi b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.jdi
new file mode 100644
index 0000000..f543902
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="c57ac2a86f5beea206bc"/>
+  </project>
+  <file_info>
+    <file device="EPM7064STC44-7" path="OrionCOM-AY.sof" usercode="0x00000000"/>
+  </file_info>
+</sld_project_info>
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.map.rpt b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.map.rpt
new file mode 100644
index 0000000..5723290
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.map.rpt
@@ -0,0 +1,264 @@
+Analysis & Synthesis report for OrionCOM-AY
+Fri Feb  5 16:21:22 2021
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Registers Removed During Synthesis
+  9. Parameter Settings for Inferred Entity Instance: AyClkDiv:ayClkDiv|lpm_add_sub:Add0
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                  ;
++-----------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Fri Feb  5 16:21:22 2021           ;
+; Quartus II 32-bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
+; Revision Name               ; OrionCOM-AY                                     ;
+; Top-level Entity Name       ; OrionCOM_AY                                     ;
+; Family                      ; MAX7000S                                        ;
+; Total macrocells            ; 22                                              ;
+; Total pins                  ; 31                                              ;
++-----------------------------+-------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                               ;
++----------------------------------------------------------------------------+----------------+---------------+
+; Option                                                                     ; Setting        ; Default Value ;
++----------------------------------------------------------------------------+----------------+---------------+
+; Device                                                                     ; EPM7064STC44-7 ;               ;
+; Top-level entity name                                                      ; OrionCOM_AY    ; OrionCOM-AY   ;
+; Family name                                                                ; MAX7000S       ; Cyclone IV GX ;
+; Use smart compilation                                                      ; Off            ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On             ; On            ;
+; Enable compact report table                                                ; Off            ; Off           ;
+; Create Debugging Nodes for IP Cores                                        ; Off            ; Off           ;
+; Preserve fewer node names                                                  ; On             ; On            ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off            ; Off           ;
+; Verilog Version                                                            ; Verilog_2001   ; Verilog_2001  ;
+; VHDL Version                                                               ; VHDL_1993      ; VHDL_1993     ;
+; State Machine Processing                                                   ; Auto           ; Auto          ;
+; Safe State Machine                                                         ; Off            ; Off           ;
+; Extract Verilog State Machines                                             ; On             ; On            ;
+; Extract VHDL State Machines                                                ; On             ; On            ;
+; Ignore Verilog initial constructs                                          ; Off            ; Off           ;
+; Iteration limit for constant Verilog loops                                 ; 5000           ; 5000          ;
+; Iteration limit for non-constant Verilog loops                             ; 250            ; 250           ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On             ; On            ;
+; Infer RAMs from Raw Logic                                                  ; On             ; On            ;
+; Parallel Synthesis                                                         ; On             ; On            ;
+; NOT Gate Push-Back                                                         ; On             ; On            ;
+; Power-Up Don't Care                                                        ; On             ; On            ;
+; Remove Duplicate Registers                                                 ; On             ; On            ;
+; Ignore CARRY Buffers                                                       ; Off            ; Off           ;
+; Ignore CASCADE Buffers                                                     ; Off            ; Off           ;
+; Ignore GLOBAL Buffers                                                      ; Off            ; Off           ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off            ; Off           ;
+; Ignore LCELL Buffers                                                       ; Auto           ; Auto          ;
+; Ignore SOFT Buffers                                                        ; Off            ; Off           ;
+; Limit AHDL Integers to 32 Bits                                             ; Off            ; Off           ;
+; Optimization Technique                                                     ; Speed          ; Speed         ;
+; Allow XOR Gate Usage                                                       ; On             ; On            ;
+; Auto Logic Cell Insertion                                                  ; On             ; On            ;
+; Parallel Expander Chain Length                                             ; 4              ; 4             ;
+; Auto Parallel Expanders                                                    ; On             ; On            ;
+; Auto Open-Drain Pins                                                       ; On             ; On            ;
+; Auto Resource Sharing                                                      ; Off            ; Off           ;
+; Maximum Fan-in Per Macrocell                                               ; 100            ; 100           ;
+; Use LogicLock Constraints during Resource Balancing                        ; On             ; On            ;
+; Ignore translate_off and synthesis_off directives                          ; Off            ; Off           ;
+; Report Parameter Settings                                                  ; On             ; On            ;
+; Report Source Assignments                                                  ; On             ; On            ;
+; Report Connectivity Checks                                                 ; On             ; On            ;
+; HDL message level                                                          ; Level2         ; Level2        ;
+; Suppress Register Optimization Related Messages                            ; Off            ; Off           ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000           ; 5000          ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000           ; 5000          ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100            ; 100           ;
+; Block Design Naming                                                        ; Auto           ; Auto          ;
+; Synthesis Effort                                                           ; Auto           ; Auto          ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On             ; On            ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off            ; Off           ;
+; Analysis & Synthesis Message Level                                         ; Medium         ; Medium        ;
+; Disable Register Merging Across Hierarchies                                ; Auto           ; Auto          ;
+; Synthesis Seed                                                             ; 1              ; 1             ;
++----------------------------------------------------------------------------+----------------+---------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 8      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                             ;
++----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                         ; Library ;
++----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------+---------+
+; OrionCOM_AY.sv                   ; yes             ; User SystemVerilog HDL File  ; /opt/cpld/OrionCOM-AY/OrionCOM_AY.sv                                                 ;         ;
+; lpm_add_sub.tdf                  ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;         ;
+; addcore.inc                      ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.inc             ;         ;
+; look_add.inc                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/look_add.inc            ;         ;
+; bypassff.inc                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/bypassff.inc            ;         ;
+; altshift.inc                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/altshift.inc            ;         ;
+; alt_stratix_add_sub.inc          ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;         ;
+; aglobal130.inc                   ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/aglobal130.inc          ;         ;
+; addcore.tdf                      ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.tdf             ;         ;
+; a_csnbuffer.inc                  ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/a_csnbuffer.inc         ;         ;
+; a_csnbuffer.tdf                  ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/a_csnbuffer.tdf         ;         ;
+; look_add.tdf                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/look_add.tdf            ;         ;
+; altshift.tdf                     ; yes             ; Megafunction                 ; /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/altshift.tdf            ;         ;
++----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++----------------------+----------------------+
+; Resource             ; Usage                ;
++----------------------+----------------------+
+; Logic cells          ; 22                   ;
+; Total registers      ; 11                   ;
+; I/O pins             ; 31                   ;
+; Parallel expanders   ; 1                    ;
+; Maximum fan-out node ; reset_n              ;
+; Maximum fan-out      ; 12                   ;
+; Total fan-out        ; 144                  ;
+; Average fan-out      ; 2.72                 ;
++----------------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
++---------------------------------------+------------+------+------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node            ; Macrocells ; Pins ; Full Hierarchy Name                                                                      ; Library Name ;
++---------------------------------------+------------+------+------------------------------------------------------------------------------------------+--------------+
+; |OrionCOM_AY                          ; 22         ; 31   ; |OrionCOM_AY                                                                             ; work         ;
+;    |AyClkDiv:ayClkDiv|                ; 11         ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv                                                           ; work         ;
+;       |lpm_add_sub:Add0|              ; 1          ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0                                          ; work         ;
+;          |addcore:adder[1]|           ; 1          ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]                         ; work         ;
+;             |a_csnbuffer:result_node| ; 1          ; 0    ; |OrionCOM_AY|AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node ; work         ;
+;    |ViClkDiv:viClkDiv|                ; 2          ; 0    ; |OrionCOM_AY|ViClkDiv:viClkDiv                                                           ; work         ;
++---------------------------------------+------------+------+------------------------------------------------------------------------------------------+--------------+
+
+
++-------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                            ;
++---------------------------------------+---------------------------------------+
+; Register name                         ; Reason for Removal                    ;
++---------------------------------------+---------------------------------------+
+; AyClkDiv:ayClkDiv|sum[0]              ; Merged with ViClkDiv:viClkDiv|div1[0] ;
+; Total Number of Removed Registers = 1 ;                                       ;
++---------------------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: AyClkDiv:ayClkDiv|lpm_add_sub:Add0 ;
++------------------------+-------------+----------------------------------------------+
+; Parameter Name         ; Value       ; Type                                         ;
++------------------------+-------------+----------------------------------------------+
+; LPM_WIDTH              ; 10          ; Untyped                                      ;
+; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                      ;
+; LPM_DIRECTION          ; ADD         ; Untyped                                      ;
+; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                      ;
+; LPM_PIPELINE           ; 0           ; Untyped                                      ;
+; MAXIMIZE_SPEED         ; 5           ; Untyped                                      ;
+; REGISTERED_AT_END      ; 0           ; Untyped                                      ;
+; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                      ;
+; USE_CS_BUFFERS         ; 1           ; Untyped                                      ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                      ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                           ;
+; DEVICE_FAMILY          ; MAX7000S    ; Untyped                                      ;
+; USE_WYS                ; OFF         ; Untyped                                      ;
+; STYLE                  ; FAST        ; Untyped                                      ;
+; CBXI_PARAMETER         ; add_sub_4ph ; Untyped                                      ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                   ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                 ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                 ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                               ;
++------------------------+-------------+----------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Fri Feb  5 16:21:19 2021
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off OrionCOM-AY -c OrionCOM-AY
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 3 design units, including 3 entities, in source file OrionCOM_AY.sv
+    Info (12023): Found entity 1: OrionCOM_AY
+    Info (12023): Found entity 2: ViClkDiv
+    Info (12023): Found entity 3: AyClkDiv
+Info (12127): Elaborating entity "OrionCOM_AY" for the top level hierarchy
+Info (12128): Elaborating entity "AyClkDiv" for hierarchy "AyClkDiv:ayClkDiv"
+Info (12128): Elaborating entity "ViClkDiv" for hierarchy "ViClkDiv:viClkDiv"
+Info (278001): Inferred 1 megafunctions from design logic
+    Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "AyClkDiv:ayClkDiv|Add0"
+Info (12130): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
+Info (12133): Instantiated megafunction "AyClkDiv:ayClkDiv|lpm_add_sub:Add0" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTH" = "10"
+    Info (12134): Parameter "LPM_DIRECTION" = "ADD"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
+Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
+Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
+Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
+Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|addcore:adder[0]", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
+Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
+Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
+Info (12131): Elaborated megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "AyClkDiv:ayClkDiv|lpm_add_sub:Add0"
+Info (13014): Ignored 12 buffer(s)
+    Info (13019): Ignored 12 SOFT buffer(s)
+Info (280013): Promoted pin-driven signal(s) to global signal
+    Info (280014): Promoted clock signal driven by pin "clk" to global clock signal
+    Info (280015): Promoted clear signal driven by pin "reset_n" to global clear signal
+Info (21057): Implemented 53 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 19 input pins
+    Info (21059): Implemented 12 output pins
+    Info (21063): Implemented 22 macrocells
+Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 335 megabytes
+    Info: Processing ended: Fri Feb  5 16:21:22 2021
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.map.summary b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.map.summary
new file mode 100644
index 0000000..c70ffac
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.map.summary
@@ -0,0 +1,7 @@
+Analysis & Synthesis Status : Successful - Fri Feb  5 16:21:22 2021
+Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+Revision Name : OrionCOM-AY
+Top-level Entity Name : OrionCOM_AY
+Family : MAX7000S
+Total macrocells : 22
+Total pins : 31
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.pin b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.pin
new file mode 100644
index 0000000..b7bf680
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.pin
@@ -0,0 +1,107 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCC           : Dedicated power pin, which MUST be connected to VCC.
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- NON_MIGRATABLE: This pin cannot be migrated.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+CHIP  "OrionCOM-AY"  ASSIGNED TO AN: EPM7064STC44-7
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+TDI                          : 1         : input  : TTL               :         :           : Y              
+a[0]                         : 2         : input  : TTL               :         :           : Y              
+a[1]                         : 3         : input  : TTL               :         :           : Y              
+GND                          : 4         : gnd    :                   :         :           :                
+a[2]                         : 5         : input  : TTL               :         :           : Y              
+a[3]                         : 6         : input  : TTL               :         :           : Y              
+TMS                          : 7         : input  : TTL               :         :           : Y              
+a[4]                         : 8         : input  : TTL               :         :           : Y              
+VCC                          : 9         : power  :                   :         :           :                
+a[5]                         : 10        : input  : TTL               :         :           : Y              
+a[6]                         : 11        : input  : TTL               :         :           : Y              
+a[7]                         : 12        : input  : TTL               :         :           : Y              
+irq4                         : 13        : output : TTL               :         :           : Y              
+irq3                         : 14        : output : TTL               :         :           : Y              
+a[8]                         : 15        : input  : TTL               :         :           : Y              
+GND                          : 16        : gnd    :                   :         :           :                
+VCC                          : 17        : power  :                   :         :           :                
+a[9]                         : 18        : input  : TTL               :         :           : Y              
+rd_n                         : 19        : input  : TTL               :         :           : Y              
+wr_n                         : 20        : input  : TTL               :         :           : Y              
+iorq_n                       : 21        : input  : TTL               :         :           : Y              
+wait_n                       : 22        : input  : TTL               :         :           : Y              
+m1_n                         : 23        : input  : TTL               :         :           : Y              
+GND                          : 24        : gnd    :                   :         :           :                
+cs_vi_n                      : 25        : output : TTL               :         :           : Y              
+TCK                          : 26        : input  : TTL               :         :           : Y              
+clk1                         : 27        : output : TTL               :         :           : Y              
+w1                           : 28        : output : TTL               :         :           : Y              
+VCC                          : 29        : power  :                   :         :           :                
+cs_vv2_n                     : 30        : output : TTL               :         :           : Y              
+rdy2                         : 31        : input  : TTL               :         :           : Y              
+TDO                          : 32        : output : TTL               :         :           : Y              
+debug                        : 33        : output : TTL               :         :           : Y              
+reset                        : 34        : output : TTL               :         :           : Y              
+cs_vv1_n                     : 35        : output : TTL               :         :           : Y              
+GND                          : 36        : gnd    :                   :         :           :                
+clk                          : 37        : input  : TTL               :         :           : Y              
+rdy1                         : 38        : input  : TTL               :         :           : Y              
+reset_n                      : 39        : input  : TTL               :         :           : Y              
+GND+                         : 40        :        :                   :         :           :                
+VCC                          : 41        : power  :                   :         :           :                
+bc1                          : 42        : output : TTL               :         :           : Y              
+bdir                         : 43        : output : TTL               :         :           : Y              
+clk2                         : 44        : output : TTL               :         :           : Y              
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.pof b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.pof
new file mode 100644
index 0000000..0cf5d9c
Binary files /dev/null and b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.pof differ
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.sta.rpt b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.sta.rpt
new file mode 100644
index 0000000..bae6b5f
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.sta.rpt
@@ -0,0 +1,550 @@
+TimeQuest Timing Analyzer report for OrionCOM-AY
+Fri Feb  5 16:21:32 2021
+Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Fmax Summary
+  6. Setup Summary
+  7. Hold Summary
+  8. Recovery Summary
+  9. Removal Summary
+ 10. Minimum Pulse Width Summary
+ 11. Setup: 'clk'
+ 12. Hold: 'clk'
+ 13. Minimum Pulse Width: 'clk'
+ 14. Clock to Output Times
+ 15. Minimum Clock to Output Times
+ 16. Propagation Delay
+ 17. Minimum Propagation Delay
+ 18. Setup Transfers
+ 19. Hold Transfers
+ 20. Report TCCS
+ 21. Report RSKM
+ 22. Unconstrained Paths
+ 23. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                      ;
++--------------------+-------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
+; Revision Name      ; OrionCOM-AY                                                       ;
+; Device Family      ; MAX7000S                                                          ;
+; Device Name        ; EPM7064STC44-7                                                    ;
+; Timing Models      ; Final                                                             ;
+; Delay Model        ; Slow Model                                                        ;
+; Rise/Fall Delays   ; Unavailable                                                       ;
++--------------------+-------------------------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 8      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                          ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; clk        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+
+
++--------------------------------------------------+
+; Fmax Summary                                     ;
++------------+-----------------+------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 113.64 MHz ; 113.64 MHz      ; clk        ;      ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++--------------------------------+
+; Setup Summary                  ;
++-------+--------+---------------+
+; Clock ; Slack  ; End Point TNS ;
++-------+--------+---------------+
+; clk   ; -7.800 ; -77.800       ;
++-------+--------+---------------+
+
+
++-------------------------------+
+; Hold Summary                  ;
++-------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++-------+-------+---------------+
+; clk   ; 3.000 ; 0.000         ;
++-------+-------+---------------+
+
+
+--------------------
+; Recovery Summary ;
+--------------------
+No paths to report.
+
+
+-------------------
+; Removal Summary ;
+-------------------
+No paths to report.
+
+
++--------------------------------+
+; Minimum Pulse Width Summary    ;
++-------+--------+---------------+
+; Clock ; Slack  ; End Point TNS ;
++-------+--------+---------------+
+; clk   ; -2.500 ; -55.000       ;
++-------+--------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Setup: 'clk'                                                                                                                         ;
++--------+---------------------------+---------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                 ; To Node                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------+---------------------------+--------------+-------------+--------------+------------+------------+
+; -7.800 ; AyClkDiv:ayClkDiv|sum[7]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.800      ;
+; -7.800 ; AyClkDiv:ayClkDiv|sum[8]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.800      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; ViClkDiv:viClkDiv|div1[0] ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[1] ; ViClkDiv:viClkDiv|div1[1] ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; ViClkDiv:viClkDiv|div1[1] ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[1]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[1]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[2]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[2]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[2]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[3]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[3]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[3]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[3]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[6]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[6]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[7]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[7]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[6]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[8]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[6]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[9]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
+; -7.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 1.000        ; 0.000      ; 5.000      ;
++--------+---------------------------+---------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Hold: 'clk'                                                                                                                         ;
++-------+---------------------------+---------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                 ; To Node                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------+---------------------------+--------------+-------------+--------------+------------+------------+
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; ViClkDiv:viClkDiv|div1[0] ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[1] ; ViClkDiv:viClkDiv|div1[1] ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; ViClkDiv:viClkDiv|div1[1] ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[1]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[1]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[2]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[2]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[2]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[3]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[3]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[3]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[3]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[4]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[5]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[6]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[6]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[6]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[7]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[7]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[7]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[6]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[8]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[8]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[8]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[6]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[3]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[2]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; ViClkDiv:viClkDiv|div1[0] ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[9]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[5]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[4]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.000 ; AyClkDiv:ayClkDiv|sum[1]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.000      ;
+; 3.800 ; AyClkDiv:ayClkDiv|sum[7]  ; AyClkDiv:ayClkDiv|sum[9]  ; clk          ; clk         ; 0.000        ; 0.000      ; 5.800      ;
++-------+---------------------------+---------------------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Minimum Pulse Width: 'clk'                                                                                 ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[1]  ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[1]  ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[2]  ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[2]  ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[3]  ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[3]  ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[4]  ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[4]  ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[5]  ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[5]  ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[6]  ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[6]  ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[7]  ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[7]  ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[8]  ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[8]  ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[9]  ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; AyClkDiv:ayClkDiv|sum[9]  ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; ViClkDiv:viClkDiv|div1[0] ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; ViClkDiv:viClkDiv|div1[0] ;
+; -2.500 ; 0.500        ; 3.000          ; High Pulse Width ; clk   ; Rise       ; ViClkDiv:viClkDiv|div1[1] ;
+; -2.500 ; 0.500        ; 3.000          ; Low Pulse Width  ; clk   ; Rise       ; ViClkDiv:viClkDiv|div1[1] ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; ayClkDiv|sum[1]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; ayClkDiv|sum[1]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; ayClkDiv|sum[2]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; ayClkDiv|sum[2]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; ayClkDiv|sum[3]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; ayClkDiv|sum[3]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; ayClkDiv|sum[4]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; ayClkDiv|sum[4]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; ayClkDiv|sum[5]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; ayClkDiv|sum[5]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; ayClkDiv|sum[6]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; ayClkDiv|sum[6]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; ayClkDiv|sum[7]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; ayClkDiv|sum[7]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; ayClkDiv|sum[8]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; ayClkDiv|sum[8]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; ayClkDiv|sum[9]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; ayClkDiv|sum[9]|clk       ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk|dataout               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk|dataout               ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; viClkDiv|div1[0]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; viClkDiv|div1[0]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; viClkDiv|div1[1]|clk      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; viClkDiv|div1[1]|clk      ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; clk1      ; clk        ; 4.500 ; 4.500 ; Rise       ; clk             ;
+; clk2      ; clk        ; 4.500 ; 4.500 ; Rise       ; clk             ;
+; debug     ; clk        ; 9.500 ; 9.500 ; Rise       ; clk             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; clk1      ; clk        ; 4.500 ; 4.500 ; Rise       ; clk             ;
+; clk2      ; clk        ; 4.500 ; 4.500 ; Rise       ; clk             ;
+; debug     ; clk        ; 9.500 ; 9.500 ; Rise       ; clk             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; a[0]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[0]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[1]       ; bc1         ;       ; 7.500 ; 7.500 ;       ;
+; a[1]       ; bdir        ;       ; 7.500 ; 7.500 ;       ;
+; a[2]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[2]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[2]       ; cs_vi_n     ;       ; 7.500 ; 7.500 ;       ;
+; a[2]       ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[2]       ; cs_vv2_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[3]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[3]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[3]       ; cs_vi_n     ; 7.500 ;       ;       ; 7.500 ;
+; a[3]       ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[3]       ; cs_vv2_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[4]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[4]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[4]       ; cs_vi_n     ; 7.500 ;       ;       ; 7.500 ;
+; a[4]       ; cs_vv1_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[4]       ; cs_vv2_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; cs_vi_n     ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; cs_vv1_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; cs_vv2_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[6]       ; bc1         ; 7.500 ; 7.500 ; 7.500 ; 7.500 ;
+; a[6]       ; bdir        ; 7.500 ; 7.500 ; 7.500 ; 7.500 ;
+; a[6]       ; cs_vi_n     ;       ; 7.500 ; 7.500 ;       ;
+; a[6]       ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[6]       ; cs_vv2_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[7]       ; bc1         ; 7.500 ; 7.500 ; 7.500 ; 7.500 ;
+; a[7]       ; bdir        ; 7.500 ; 7.500 ; 7.500 ; 7.500 ;
+; a[7]       ; cs_vi_n     ;       ; 7.500 ; 7.500 ;       ;
+; a[7]       ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[7]       ; cs_vv2_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[8]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[9]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[9]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; iorq_n     ; bc1         ;       ; 7.500 ; 7.500 ;       ;
+; iorq_n     ; bdir        ;       ; 7.500 ; 7.500 ;       ;
+; iorq_n     ; cs_vi_n     ;       ; 7.500 ; 7.500 ;       ;
+; iorq_n     ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; iorq_n     ; cs_vv2_n    ;       ; 7.500 ; 7.500 ;       ;
+; m1_n       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; m1_n       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; rd_n       ; bc1         ;       ; 7.500 ; 7.500 ;       ;
+; rdy1       ; irq3        ;       ; 7.500 ; 7.500 ;       ;
+; rdy2       ; irq4        ;       ; 7.500 ; 7.500 ;       ;
+; reset_n    ; reset       ;       ; 7.500 ; 7.500 ;       ;
+; wait_n     ; w1          ;       ; 7.500 ; 7.500 ;       ;
+; wr_n       ; bc1         ;       ; 7.500 ; 7.500 ;       ;
+; wr_n       ; bdir        ;       ; 7.500 ; 7.500 ;       ;
+; wr_n       ; w1          ;       ; 7.500 ; 7.500 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; a[0]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[0]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[1]       ; bc1         ;       ; 7.500 ; 7.500 ;       ;
+; a[1]       ; bdir        ;       ; 7.500 ; 7.500 ;       ;
+; a[2]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[2]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[2]       ; cs_vi_n     ;       ; 7.500 ; 7.500 ;       ;
+; a[2]       ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[2]       ; cs_vv2_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[3]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[3]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[3]       ; cs_vi_n     ; 7.500 ;       ;       ; 7.500 ;
+; a[3]       ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[3]       ; cs_vv2_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[4]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[4]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[4]       ; cs_vi_n     ; 7.500 ;       ;       ; 7.500 ;
+; a[4]       ; cs_vv1_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[4]       ; cs_vv2_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; cs_vi_n     ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; cs_vv1_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[5]       ; cs_vv2_n    ; 7.500 ;       ;       ; 7.500 ;
+; a[6]       ; bc1         ; 7.500 ; 7.500 ; 7.500 ; 7.500 ;
+; a[6]       ; bdir        ; 7.500 ; 7.500 ; 7.500 ; 7.500 ;
+; a[6]       ; cs_vi_n     ;       ; 7.500 ; 7.500 ;       ;
+; a[6]       ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[6]       ; cs_vv2_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[7]       ; bc1         ; 7.500 ; 7.500 ; 7.500 ; 7.500 ;
+; a[7]       ; bdir        ; 7.500 ; 7.500 ; 7.500 ; 7.500 ;
+; a[7]       ; cs_vi_n     ;       ; 7.500 ; 7.500 ;       ;
+; a[7]       ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[7]       ; cs_vv2_n    ;       ; 7.500 ; 7.500 ;       ;
+; a[8]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[9]       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; a[9]       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; iorq_n     ; bc1         ;       ; 7.500 ; 7.500 ;       ;
+; iorq_n     ; bdir        ;       ; 7.500 ; 7.500 ;       ;
+; iorq_n     ; cs_vi_n     ;       ; 7.500 ; 7.500 ;       ;
+; iorq_n     ; cs_vv1_n    ;       ; 7.500 ; 7.500 ;       ;
+; iorq_n     ; cs_vv2_n    ;       ; 7.500 ; 7.500 ;       ;
+; m1_n       ; bc1         ; 7.500 ;       ;       ; 7.500 ;
+; m1_n       ; bdir        ; 7.500 ;       ;       ; 7.500 ;
+; rd_n       ; bc1         ;       ; 7.500 ; 7.500 ;       ;
+; rdy1       ; irq3        ;       ; 7.500 ; 7.500 ;       ;
+; rdy2       ; irq4        ;       ; 7.500 ; 7.500 ;       ;
+; reset_n    ; reset       ;       ; 7.500 ; 7.500 ;       ;
+; wait_n     ; w1          ;       ; 7.500 ; 7.500 ;       ;
+; wr_n       ; bc1         ;       ; 7.500 ; 7.500 ;       ;
+; wr_n       ; bdir        ;       ; 7.500 ; 7.500 ;       ;
+; wr_n       ; w1          ;       ; 7.500 ; 7.500 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; clk        ; clk      ; 85       ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; clk        ; clk      ; 85       ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 18    ; 18   ;
+; Unconstrained Input Port Paths  ; 63    ; 63   ;
+; Unconstrained Output Ports      ; 12    ; 12   ;
+; Unconstrained Output Port Paths ; 55    ; 55   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+    Info: Processing started: Fri Feb  5 16:21:31 2021
+Info: Command: quartus_sta OrionCOM-AY -c OrionCOM-AY
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (306004): Started post-fitting delay annotation
+Info (306005): Delay annotation completed successfully
+Warning (335095): TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'OrionCOM-AY.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name clk clk
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Critical Warning (332148): Timing requirements not met
+Info (332146): Worst-case setup slack is -7.800
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -7.800       -77.800 clk 
+Info (332146): Worst-case hold slack is 3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     3.000         0.000 clk 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.500
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -2.500       -55.000 clk 
+Info (332001): The selected device family is not supported by the report_metastability command.
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 285 megabytes
+    Info: Processing ended: Fri Feb  5 16:21:32 2021
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.sta.summary b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.sta.summary
new file mode 100644
index 0000000..01f2cc3
--- /dev/null
+++ b/Firmware/OrionCOM-AY/output_files/OrionCOM-AY.sta.summary
@@ -0,0 +1,17 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Setup 'clk'
+Slack : -7.800
+TNS   : -77.800
+
+Type  : Hold 'clk'
+Slack : 3.000
+TNS   : 0.000
+
+Type  : Minimum Pulse Width 'clk'
+Slack : -2.500
+TNS   : -55.000
+
+------------------------------------------------------------
diff --git a/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY.sft b/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY.sft
new file mode 100644
index 0000000..e78d655
--- /dev/null
+++ b/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY.sft
@@ -0,0 +1,4 @@
+set tool_name "ModelSim-Altera (Verilog)"
+set corner_file_list {
+	{{"Slow Model"} {OrionCOM-AY.vo OrionCOM-AY_v.sdo}}
+}
diff --git a/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY.vo b/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY.vo
new file mode 100644
index 0000000..7572a16
--- /dev/null
+++ b/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY.vo
@@ -0,0 +1,1126 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 32-bit"
+// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
+
+// DATE "02/05/2021 16:21:34"
+
+// 
+// Device: Altera EPM7064STC44-7 Package TQFP44
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module OrionCOM_AY (
+	clk,
+	reset_n,
+	iorq_n,
+	m1_n,
+	wr_n,
+	rd_n,
+	wait_n,
+	a,
+	rdy1,
+	rdy2,
+	cs_vi_n,
+	cs_vv1_n,
+	cs_vv2_n,
+	bdir,
+	bc1,
+	w1,
+	clk1,
+	clk2,
+	reset,
+	irq3,
+	irq4,
+	debug);
+input 	clk;
+input 	reset_n;
+input 	iorq_n;
+input 	m1_n;
+input 	wr_n;
+input 	rd_n;
+input 	wait_n;
+input 	[9:0] a;
+input 	rdy1;
+input 	rdy2;
+output 	cs_vi_n;
+output 	cs_vv1_n;
+output 	cs_vv2_n;
+output 	bdir;
+output 	bc1;
+output 	w1;
+output 	clk1;
+output 	clk2;
+output 	reset;
+output 	irq3;
+output 	irq4;
+output 	debug;
+
+// Design Ports Information
+// clk	=>  Location: PIN_37
+// reset_n	=>  Location: PIN_39
+// iorq_n	=>  Location: PIN_21
+// m1_n	=>  Location: PIN_23
+// wr_n	=>  Location: PIN_20
+// rd_n	=>  Location: PIN_19
+// wait_n	=>  Location: PIN_22
+// a[0]	=>  Location: PIN_2
+// a[1]	=>  Location: PIN_3
+// a[2]	=>  Location: PIN_5
+// a[3]	=>  Location: PIN_6
+// a[4]	=>  Location: PIN_8
+// a[5]	=>  Location: PIN_10
+// a[6]	=>  Location: PIN_11
+// a[7]	=>  Location: PIN_12
+// a[8]	=>  Location: PIN_15
+// a[9]	=>  Location: PIN_18
+// rdy1	=>  Location: PIN_38
+// rdy2	=>  Location: PIN_31
+// w1	=>  Location: PIN_28
+// irq3	=>  Location: PIN_14
+// irq4	=>  Location: PIN_13
+// reset	=>  Location: PIN_34
+// cs_vv2_n	=>  Location: PIN_30
+// cs_vi_n	=>  Location: PIN_25
+// cs_vv1_n	=>  Location: PIN_35
+// clk1	=>  Location: PIN_27
+// bdir	=>  Location: PIN_43
+// bc1	=>  Location: PIN_42
+// clk2	=>  Location: PIN_44
+// debug	=>  Location: PIN_33
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+// synopsys translate_off
+initial $sdf_annotate("OrionCOM-AY_v.sdo");
+// synopsys translate_on
+
+wire \wr_n~dataout ;
+wire \wait_n~dataout ;
+wire \w1~1_dataout ;
+wire \rdy1~dataout ;
+wire \rdy1~1_dataout ;
+wire \rdy2~dataout ;
+wire \rdy2~1_dataout ;
+wire \reset_n~dataout ;
+wire \reset_n~4_dataout ;
+wire \iorq_n~dataout ;
+wire \cs_vv2_n~2_dataout ;
+wire \cs_vi_n~3_dataout ;
+wire \cs_vv1_n~2_dataout ;
+wire \clk~dataout ;
+wire \m1_n~dataout ;
+wire \bdir~7_dataout ;
+wire \rd_n~dataout ;
+wire \bc1~9_dataout ;
+wire \ayClkDiv|Add0|adder[1]|result_node|sout_node[1]~32_pexpout ;
+wire \ayClkDiv|sum[9]~1_dataout ;
+wire [9:0] \a~dataout ;
+wire [1:0] \viClkDiv|div1 ;
+wire [9:0] \ayClkDiv|sum ;
+
+
+// Location: PIN_20
+max_io \wr_n~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\wr_n~dataout ),
+	.padio(wr_n));
+// synopsys translate_off
+defparam \wr_n~I .bus_hold = "false";
+defparam \wr_n~I .open_drain_output = "false";
+defparam \wr_n~I .operation_mode = "input";
+defparam \wr_n~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_22
+max_io \wait_n~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\wait_n~dataout ),
+	.padio(wait_n));
+// synopsys translate_off
+defparam \wait_n~I .bus_hold = "false";
+defparam \wait_n~I .open_drain_output = "false";
+defparam \wait_n~I .operation_mode = "input";
+defparam \wait_n~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: LC51
+max_mcell \w1~1 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\wait_n~dataout ,!\wr_n~dataout }),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\w1~1_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \w1~1 .operation_mode = "invert";
+defparam \w1~1 .output_mode = "comb";
+defparam \w1~1 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: PIN_38
+max_io \rdy1~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\rdy1~dataout ),
+	.padio(rdy1));
+// synopsys translate_off
+defparam \rdy1~I .bus_hold = "false";
+defparam \rdy1~I .open_drain_output = "false";
+defparam \rdy1~I .operation_mode = "input";
+defparam \rdy1~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: LC19
+max_mcell \rdy1~1 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\rdy1~dataout }),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\rdy1~1_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \rdy1~1 .operation_mode = "normal";
+defparam \rdy1~1 .output_mode = "comb";
+defparam \rdy1~1 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: PIN_31
+max_io \rdy2~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\rdy2~dataout ),
+	.padio(rdy2));
+// synopsys translate_off
+defparam \rdy2~I .bus_hold = "false";
+defparam \rdy2~I .open_drain_output = "false";
+defparam \rdy2~I .operation_mode = "input";
+defparam \rdy2~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: LC20
+max_mcell \rdy2~1 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\rdy2~dataout }),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\rdy2~1_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \rdy2~1 .operation_mode = "normal";
+defparam \rdy2~1 .output_mode = "comb";
+defparam \rdy2~1 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: PIN_39
+max_io \reset_n~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\reset_n~dataout ),
+	.padio(reset_n));
+// synopsys translate_off
+defparam \reset_n~I .bus_hold = "false";
+defparam \reset_n~I .open_drain_output = "false";
+defparam \reset_n~I .operation_mode = "input";
+defparam \reset_n~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: LC62
+max_mcell \reset_n~4 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\reset_n~dataout }),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\reset_n~4_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \reset_n~4 .operation_mode = "normal";
+defparam \reset_n~4 .output_mode = "comb";
+defparam \reset_n~4 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: PIN_11
+max_io \a[6]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [6]),
+	.padio(a[6]));
+// synopsys translate_off
+defparam \a[6]~I .bus_hold = "false";
+defparam \a[6]~I .open_drain_output = "false";
+defparam \a[6]~I .operation_mode = "input";
+defparam \a[6]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_12
+max_io \a[7]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [7]),
+	.padio(a[7]));
+// synopsys translate_off
+defparam \a[7]~I .bus_hold = "false";
+defparam \a[7]~I .open_drain_output = "false";
+defparam \a[7]~I .operation_mode = "input";
+defparam \a[7]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_21
+max_io \iorq_n~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\iorq_n~dataout ),
+	.padio(iorq_n));
+// synopsys translate_off
+defparam \iorq_n~I .bus_hold = "false";
+defparam \iorq_n~I .open_drain_output = "false";
+defparam \iorq_n~I .operation_mode = "input";
+defparam \iorq_n~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_8
+max_io \a[4]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [4]),
+	.padio(a[4]));
+// synopsys translate_off
+defparam \a[4]~I .bus_hold = "false";
+defparam \a[4]~I .open_drain_output = "false";
+defparam \a[4]~I .operation_mode = "input";
+defparam \a[4]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_10
+max_io \a[5]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [5]),
+	.padio(a[5]));
+// synopsys translate_off
+defparam \a[5]~I .bus_hold = "false";
+defparam \a[5]~I .open_drain_output = "false";
+defparam \a[5]~I .operation_mode = "input";
+defparam \a[5]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_5
+max_io \a[2]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [2]),
+	.padio(a[2]));
+// synopsys translate_off
+defparam \a[2]~I .bus_hold = "false";
+defparam \a[2]~I .open_drain_output = "false";
+defparam \a[2]~I .operation_mode = "input";
+defparam \a[2]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_6
+max_io \a[3]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [3]),
+	.padio(a[3]));
+// synopsys translate_off
+defparam \a[3]~I .bus_hold = "false";
+defparam \a[3]~I .open_drain_output = "false";
+defparam \a[3]~I .operation_mode = "input";
+defparam \a[3]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: LC52
+max_mcell \cs_vv2_n~2 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\a~dataout [3],\a~dataout [2],\a~dataout [5],\a~dataout [4],!\iorq_n~dataout ,!\a~dataout [7],!\a~dataout [6]}),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\cs_vv2_n~2_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \cs_vv2_n~2 .operation_mode = "invert";
+defparam \cs_vv2_n~2 .output_mode = "comb";
+defparam \cs_vv2_n~2 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: LC46
+max_mcell \cs_vi_n~3 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\a~dataout [2],\a~dataout [5],\a~dataout [4],!\iorq_n~dataout ,!\a~dataout [7],!\a~dataout [6],\a~dataout [3]}),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\cs_vi_n~3_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \cs_vi_n~3 .operation_mode = "invert";
+defparam \cs_vi_n~3 .output_mode = "comb";
+defparam \cs_vi_n~3 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: LC64
+max_mcell \cs_vv1_n~2 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\a~dataout [2],\a~dataout [5],\a~dataout [4],!\iorq_n~dataout ,!\a~dataout [7],!\a~dataout [6],!\a~dataout [3]}),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\cs_vv1_n~2_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \cs_vv1_n~2 .operation_mode = "invert";
+defparam \cs_vv1_n~2 .output_mode = "comb";
+defparam \cs_vv1_n~2 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: PIN_37
+max_io \clk~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\clk~dataout ),
+	.padio(clk));
+// synopsys translate_off
+defparam \clk~I .bus_hold = "false";
+defparam \clk~I .open_drain_output = "false";
+defparam \clk~I .operation_mode = "input";
+defparam \clk~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: LC4
+max_mcell \viClkDiv|div1[0] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\viClkDiv|div1 [0]),
+	.pexpout());
+// synopsys translate_off
+defparam \viClkDiv|div1[0] .operation_mode = "vcc";
+defparam \viClkDiv|div1[0] .output_mode = "reg";
+defparam \viClkDiv|div1[0] .pexp_mode = "on";
+defparam \viClkDiv|div1[0] .power_up = "low";
+defparam \viClkDiv|div1[0] .register_mode = "tff";
+// synopsys translate_on
+
+// Location: LC49
+max_mcell \viClkDiv|div1[1] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\viClkDiv|div1 [0]}),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\viClkDiv|div1 [1]),
+	.pexpout());
+// synopsys translate_off
+defparam \viClkDiv|div1[1] .operation_mode = "normal";
+defparam \viClkDiv|div1[1] .output_mode = "reg";
+defparam \viClkDiv|div1[1] .pexp_mode = "off";
+defparam \viClkDiv|div1[1] .power_up = "low";
+defparam \viClkDiv|div1[1] .register_mode = "tff";
+// synopsys translate_on
+
+// Location: PIN_23
+max_io \m1_n~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\m1_n~dataout ),
+	.padio(m1_n));
+// synopsys translate_off
+defparam \m1_n~I .bus_hold = "false";
+defparam \m1_n~I .open_drain_output = "false";
+defparam \m1_n~I .operation_mode = "input";
+defparam \m1_n~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_2
+max_io \a[0]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [0]),
+	.padio(a[0]));
+// synopsys translate_off
+defparam \a[0]~I .bus_hold = "false";
+defparam \a[0]~I .open_drain_output = "false";
+defparam \a[0]~I .operation_mode = "input";
+defparam \a[0]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_3
+max_io \a[1]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [1]),
+	.padio(a[1]));
+// synopsys translate_off
+defparam \a[1]~I .bus_hold = "false";
+defparam \a[1]~I .open_drain_output = "false";
+defparam \a[1]~I .operation_mode = "input";
+defparam \a[1]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_18
+max_io \a[9]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [9]),
+	.padio(a[9]));
+// synopsys translate_off
+defparam \a[9]~I .bus_hold = "false";
+defparam \a[9]~I .open_drain_output = "false";
+defparam \a[9]~I .operation_mode = "input";
+defparam \a[9]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: LC14
+max_mcell \bdir~7 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\a~dataout [3],\a~dataout [2],\a~dataout [5],\a~dataout [4],!\iorq_n~dataout ,!\a~dataout [7],!\a~dataout [6],!\wr_n~dataout }),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\a~dataout [9],!\a~dataout [1],\a~dataout [0],\m1_n~dataout ,\a~dataout [3],\a~dataout [2],\a~dataout [5],\a~dataout [4],!\iorq_n~dataout ,\a~dataout [7],\a~dataout [6],!
+\wr_n~dataout }),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\bdir~7_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \bdir~7 .operation_mode = "normal";
+defparam \bdir~7 .output_mode = "comb";
+defparam \bdir~7 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: PIN_15
+max_io \a[8]~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\a~dataout [8]),
+	.padio(a[8]));
+// synopsys translate_off
+defparam \a[8]~I .bus_hold = "false";
+defparam \a[8]~I .open_drain_output = "false";
+defparam \a[8]~I .operation_mode = "input";
+defparam \a[8]~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_19
+max_io \rd_n~I (
+	.datain(gnd),
+	.oe(gnd),
+	.dataout(\rd_n~dataout ),
+	.padio(rd_n));
+// synopsys translate_off
+defparam \rd_n~I .bus_hold = "false";
+defparam \rd_n~I .open_drain_output = "false";
+defparam \rd_n~I .operation_mode = "input";
+defparam \rd_n~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: LC16
+max_mcell \bc1~9 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\a~dataout [3],\a~dataout [2],\a~dataout [5],\a~dataout [4],!\iorq_n~dataout ,\a~dataout [7],\a~dataout [6],\a~dataout [0],!\wr_n~dataout ,\a~dataout [9],!\a~dataout [1],
+\m1_n~dataout ,\a~dataout [8]}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\rd_n~dataout ,\a~dataout [3],\a~dataout [2],\a~dataout [5],\a~dataout [4],!\iorq_n~dataout ,\a~dataout [7],\a~dataout [6],\a~dataout [0],\a~dataout [9],!\a~dataout [1],
+\m1_n~dataout ,\a~dataout [8]}),
+	.pterm3({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\a~dataout [3],\a~dataout [2],\a~dataout [5],\a~dataout [4],!\iorq_n~dataout ,!\a~dataout [7],!\a~dataout [6],\a~dataout [0],!\wr_n~dataout }),
+	.pterm4({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\rd_n~dataout ,\a~dataout [3],\a~dataout [2],\a~dataout [5],\a~dataout [4],!\iorq_n~dataout ,!\a~dataout [7],!\a~dataout [6],\a~dataout [0]}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\bc1~9_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \bc1~9 .operation_mode = "normal";
+defparam \bc1~9 .output_mode = "comb";
+defparam \bc1~9 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: LC1
+max_mcell \ayClkDiv|sum[1] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\viClkDiv|div1 [0]}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\ayClkDiv|sum [1]}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum [1]),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[1] .operation_mode = "xor";
+defparam \ayClkDiv|sum[1] .output_mode = "reg";
+defparam \ayClkDiv|sum[1] .pexp_mode = "off";
+defparam \ayClkDiv|sum[1] .power_up = "low";
+defparam \ayClkDiv|sum[1] .register_mode = "dff";
+// synopsys translate_on
+
+// Location: LC2
+max_mcell \ayClkDiv|sum[2] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [1]}),
+	.pterm3({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\viClkDiv|div1 [0]}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [2]}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum [2]),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[2] .operation_mode = "xor";
+defparam \ayClkDiv|sum[2] .output_mode = "reg";
+defparam \ayClkDiv|sum[2] .pexp_mode = "off";
+defparam \ayClkDiv|sum[2] .power_up = "low";
+defparam \ayClkDiv|sum[2] .register_mode = "dff";
+// synopsys translate_on
+
+// Location: LC5
+max_mcell \ayClkDiv|sum[3] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [1],\ayClkDiv|sum [2]}),
+	.pterm3({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\viClkDiv|div1 [0],\ayClkDiv|sum [2]}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [3]}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum [3]),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[3] .operation_mode = "xor";
+defparam \ayClkDiv|sum[3] .output_mode = "reg";
+defparam \ayClkDiv|sum[3] .pexp_mode = "off";
+defparam \ayClkDiv|sum[3] .power_up = "low";
+defparam \ayClkDiv|sum[3] .register_mode = "dff";
+// synopsys translate_on
+
+// Location: LC7
+max_mcell \ayClkDiv|sum[4] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [1],\ayClkDiv|sum [2],\ayClkDiv|sum [3]}),
+	.pterm3({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\viClkDiv|div1 [0],\ayClkDiv|sum [2],\ayClkDiv|sum [3]}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\ayClkDiv|sum [4]}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum [4]),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[4] .operation_mode = "xor";
+defparam \ayClkDiv|sum[4] .output_mode = "reg";
+defparam \ayClkDiv|sum[4] .pexp_mode = "off";
+defparam \ayClkDiv|sum[4] .power_up = "low";
+defparam \ayClkDiv|sum[4] .register_mode = "dff";
+// synopsys translate_on
+
+// Location: LC8
+max_mcell \ayClkDiv|sum[5] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [2],\ayClkDiv|sum [3],\ayClkDiv|sum [1]}),
+	.pterm3({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\viClkDiv|div1 [0],\ayClkDiv|sum [2],\ayClkDiv|sum [3]}),
+	.pterm4({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [4]}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\ayClkDiv|sum [5]}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum [5]),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[5] .operation_mode = "xor";
+defparam \ayClkDiv|sum[5] .output_mode = "reg";
+defparam \ayClkDiv|sum[5] .pexp_mode = "off";
+defparam \ayClkDiv|sum[5] .power_up = "low";
+defparam \ayClkDiv|sum[5] .register_mode = "dff";
+// synopsys translate_on
+
+// Location: LC6
+max_mcell \ayClkDiv|sum[6] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [4]}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [2],\ayClkDiv|sum [3],\ayClkDiv|sum [1]}),
+	.pterm3({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\viClkDiv|div1 [0],\ayClkDiv|sum [2],\ayClkDiv|sum [3]}),
+	.pterm4({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [5]}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [6]}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum [6]),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[6] .operation_mode = "xor";
+defparam \ayClkDiv|sum[6] .output_mode = "reg";
+defparam \ayClkDiv|sum[6] .pexp_mode = "off";
+defparam \ayClkDiv|sum[6] .power_up = "low";
+defparam \ayClkDiv|sum[6] .register_mode = "dff";
+// synopsys translate_on
+
+// Location: LC12
+max_mcell \ayClkDiv|sum[7] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [4],\ayClkDiv|sum [6]}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [6],\ayClkDiv|sum [2],\ayClkDiv|sum [3],\ayClkDiv|sum [1]}),
+	.pterm3({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\viClkDiv|div1 [0],\ayClkDiv|sum [6],\ayClkDiv|sum [2],\ayClkDiv|sum [3]}),
+	.pterm4({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [5],\ayClkDiv|sum [6]}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\ayClkDiv|sum [7]}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum [7]),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[7] .operation_mode = "xor";
+defparam \ayClkDiv|sum[7] .output_mode = "reg";
+defparam \ayClkDiv|sum[7] .pexp_mode = "off";
+defparam \ayClkDiv|sum[7] .power_up = "low";
+defparam \ayClkDiv|sum[7] .register_mode = "dff";
+// synopsys translate_on
+
+// Location: LC13
+max_mcell \ayClkDiv|sum[8] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\ayClkDiv|sum [6],!\ayClkDiv|sum [7]}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\viClkDiv|div1 [0],!\ayClkDiv|sum [7],!\ayClkDiv|sum [4],!\ayClkDiv|sum [5],!\ayClkDiv|sum [1]}),
+	.pterm3({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\ayClkDiv|sum [3],!\ayClkDiv|sum [7],!\ayClkDiv|sum [4],!\ayClkDiv|sum [5]}),
+	.pterm4({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\ayClkDiv|sum [2],!\ayClkDiv|sum [7],!\ayClkDiv|sum [4],!\ayClkDiv|sum [5]}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,!\ayClkDiv|sum [8]}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum [8]),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[8] .operation_mode = "xor";
+defparam \ayClkDiv|sum[8] .output_mode = "reg";
+defparam \ayClkDiv|sum[8] .pexp_mode = "off";
+defparam \ayClkDiv|sum[8] .power_up = "low";
+defparam \ayClkDiv|sum[8] .register_mode = "dff";
+// synopsys translate_on
+
+// Location: LC10
+max_mcell \ayClkDiv|Add0|adder[1]|result_node|sout_node[1]~32 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [8],\ayClkDiv|sum [7]}),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(),
+	.pexpout(\ayClkDiv|Add0|adder[1]|result_node|sout_node[1]~32_pexpout ));
+// synopsys translate_off
+defparam \ayClkDiv|Add0|adder[1]|result_node|sout_node[1]~32 .operation_mode = "vcc";
+defparam \ayClkDiv|Add0|adder[1]|result_node|sout_node[1]~32 .output_mode = "comb";
+defparam \ayClkDiv|Add0|adder[1]|result_node|sout_node[1]~32 .pexp_mode = "on";
+// synopsys translate_on
+
+// Location: LC11
+max_mcell \ayClkDiv|sum[9] (
+	.clk(\clk~dataout ),
+	.aclr(!\reset_n~dataout ),
+	.pexpin(\ayClkDiv|Add0|adder[1]|result_node|sout_node[1]~32_pexpout ),
+	.fpin(vcc),
+	.pterm0({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\viClkDiv|div1 [0],\ayClkDiv|sum [2],\ayClkDiv|sum [3],\ayClkDiv|sum [6],\ayClkDiv|sum [8]}),
+	.pterm1({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm2({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [6],\ayClkDiv|sum [8],\ayClkDiv|sum [5]}),
+	.pterm3({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [4],\ayClkDiv|sum [6],\ayClkDiv|sum [8]}),
+	.pterm4({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [2],\ayClkDiv|sum [3],\ayClkDiv|sum [1],\ayClkDiv|sum [6],\ayClkDiv|sum [8]}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [9]}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum [9]),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[9] .operation_mode = "xor";
+defparam \ayClkDiv|sum[9] .output_mode = "reg";
+defparam \ayClkDiv|sum[9] .pexp_mode = "off";
+defparam \ayClkDiv|sum[9] .power_up = "low";
+defparam \ayClkDiv|sum[9] .register_mode = "dff";
+// synopsys translate_on
+
+// Location: LC57
+max_mcell \ayClkDiv|sum[9]~1 (
+	.clk(gnd),
+	.aclr(gnd),
+	.pexpin(gnd),
+	.fpin(vcc),
+	.pterm0({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm1({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,\ayClkDiv|sum [9]}),
+	.pterm2({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm3({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm4({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pterm5({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pxor({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.pena({vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc,vcc}),
+	.paclr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.papre({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+	.dataout(\ayClkDiv|sum[9]~1_dataout ),
+	.pexpout());
+// synopsys translate_off
+defparam \ayClkDiv|sum[9]~1 .operation_mode = "normal";
+defparam \ayClkDiv|sum[9]~1 .output_mode = "comb";
+defparam \ayClkDiv|sum[9]~1 .pexp_mode = "off";
+// synopsys translate_on
+
+// Location: PIN_28
+max_io \w1~I (
+	.datain(\w1~1_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(w1));
+// synopsys translate_off
+defparam \w1~I .bus_hold = "false";
+defparam \w1~I .open_drain_output = "false";
+defparam \w1~I .operation_mode = "output";
+defparam \w1~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_14
+max_io \irq3~I (
+	.datain(\rdy1~1_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(irq3));
+// synopsys translate_off
+defparam \irq3~I .bus_hold = "false";
+defparam \irq3~I .open_drain_output = "false";
+defparam \irq3~I .operation_mode = "output";
+defparam \irq3~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_13
+max_io \irq4~I (
+	.datain(\rdy2~1_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(irq4));
+// synopsys translate_off
+defparam \irq4~I .bus_hold = "false";
+defparam \irq4~I .open_drain_output = "false";
+defparam \irq4~I .operation_mode = "output";
+defparam \irq4~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_34
+max_io \reset~I (
+	.datain(\reset_n~4_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(reset));
+// synopsys translate_off
+defparam \reset~I .bus_hold = "false";
+defparam \reset~I .open_drain_output = "false";
+defparam \reset~I .operation_mode = "output";
+defparam \reset~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_30
+max_io \cs_vv2_n~I (
+	.datain(\cs_vv2_n~2_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(cs_vv2_n));
+// synopsys translate_off
+defparam \cs_vv2_n~I .bus_hold = "false";
+defparam \cs_vv2_n~I .open_drain_output = "false";
+defparam \cs_vv2_n~I .operation_mode = "output";
+defparam \cs_vv2_n~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_25
+max_io \cs_vi_n~I (
+	.datain(\cs_vi_n~3_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(cs_vi_n));
+// synopsys translate_off
+defparam \cs_vi_n~I .bus_hold = "false";
+defparam \cs_vi_n~I .open_drain_output = "false";
+defparam \cs_vi_n~I .operation_mode = "output";
+defparam \cs_vi_n~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_35
+max_io \cs_vv1_n~I (
+	.datain(\cs_vv1_n~2_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(cs_vv1_n));
+// synopsys translate_off
+defparam \cs_vv1_n~I .bus_hold = "false";
+defparam \cs_vv1_n~I .open_drain_output = "false";
+defparam \cs_vv1_n~I .operation_mode = "output";
+defparam \cs_vv1_n~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_27
+max_io \clk1~I (
+	.datain(\viClkDiv|div1 [1]),
+	.oe(vcc),
+	.dataout(),
+	.padio(clk1));
+// synopsys translate_off
+defparam \clk1~I .bus_hold = "false";
+defparam \clk1~I .open_drain_output = "false";
+defparam \clk1~I .operation_mode = "output";
+defparam \clk1~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_43
+max_io \bdir~I (
+	.datain(\bdir~7_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(bdir));
+// synopsys translate_off
+defparam \bdir~I .bus_hold = "false";
+defparam \bdir~I .open_drain_output = "false";
+defparam \bdir~I .operation_mode = "output";
+defparam \bdir~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_42
+max_io \bc1~I (
+	.datain(\bc1~9_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(bc1));
+// synopsys translate_off
+defparam \bc1~I .bus_hold = "false";
+defparam \bc1~I .open_drain_output = "false";
+defparam \bc1~I .operation_mode = "output";
+defparam \bc1~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_44
+max_io \clk2~I (
+	.datain(\ayClkDiv|sum [9]),
+	.oe(vcc),
+	.dataout(),
+	.padio(clk2));
+// synopsys translate_off
+defparam \clk2~I .bus_hold = "false";
+defparam \clk2~I .open_drain_output = "false";
+defparam \clk2~I .operation_mode = "output";
+defparam \clk2~I .weak_pull_up = "false";
+// synopsys translate_on
+
+// Location: PIN_33
+max_io \debug~I (
+	.datain(\ayClkDiv|sum[9]~1_dataout ),
+	.oe(vcc),
+	.dataout(),
+	.padio(debug));
+// synopsys translate_off
+defparam \debug~I .bus_hold = "false";
+defparam \debug~I .open_drain_output = "false";
+defparam \debug~I .operation_mode = "output";
+defparam \debug~I .weak_pull_up = "false";
+// synopsys translate_on
+
+endmodule
diff --git a/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY_modelsim.xrf b/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY_modelsim.xrf
new file mode 100644
index 0000000..0964df5
--- /dev/null
+++ b/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY_modelsim.xrf
@@ -0,0 +1,70 @@
+vendor_name = ModelSim
+source_file = 1, /opt/cpld/OrionCOM-AY/OrionCOM_AY.sv
+source_file = 1, /opt/cpld/OrionCOM-AY/db/OrionCOM-AY.cbx.xml
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.inc
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/look_add.inc
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/bypassff.inc
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/altshift.inc
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/aglobal130.inc
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/cbx.lst
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/addcore.tdf
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/a_csnbuffer.inc
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/a_csnbuffer.tdf
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/look_add.tdf
+source_file = 1, /opt/romych/Quartus_13.sp1/quartus/libraries/megafunctions/altshift.tdf
+design_name = OrionCOM_AY
+instance = comp, \wr_n~I , wr_n, OrionCOM_AY, 1
+instance = comp, \wait_n~I , wait_n, OrionCOM_AY, 1
+instance = comp, \w1~1 , w1~1, OrionCOM_AY, 1
+instance = comp, \rdy1~I , rdy1, OrionCOM_AY, 1
+instance = comp, \rdy1~1 , rdy1~1, OrionCOM_AY, 1
+instance = comp, \rdy2~I , rdy2, OrionCOM_AY, 1
+instance = comp, \rdy2~1 , rdy2~1, OrionCOM_AY, 1
+instance = comp, \reset_n~I , reset_n, OrionCOM_AY, 1
+instance = comp, \reset_n~4 , reset_n~4, OrionCOM_AY, 1
+instance = comp, \a[6]~I , a[6], OrionCOM_AY, 1
+instance = comp, \a[7]~I , a[7], OrionCOM_AY, 1
+instance = comp, \iorq_n~I , iorq_n, OrionCOM_AY, 1
+instance = comp, \a[4]~I , a[4], OrionCOM_AY, 1
+instance = comp, \a[5]~I , a[5], OrionCOM_AY, 1
+instance = comp, \a[2]~I , a[2], OrionCOM_AY, 1
+instance = comp, \a[3]~I , a[3], OrionCOM_AY, 1
+instance = comp, \cs_vv2_n~2 , cs_vv2_n~2, OrionCOM_AY, 1
+instance = comp, \cs_vi_n~3 , cs_vi_n~3, OrionCOM_AY, 1
+instance = comp, \cs_vv1_n~2 , cs_vv1_n~2, OrionCOM_AY, 1
+instance = comp, \clk~I , clk, OrionCOM_AY, 1
+instance = comp, \viClkDiv|div1[0] , viClkDiv|div1[0], OrionCOM_AY, 1
+instance = comp, \viClkDiv|div1[1] , viClkDiv|div1[1], OrionCOM_AY, 1
+instance = comp, \m1_n~I , m1_n, OrionCOM_AY, 1
+instance = comp, \a[0]~I , a[0], OrionCOM_AY, 1
+instance = comp, \a[1]~I , a[1], OrionCOM_AY, 1
+instance = comp, \a[9]~I , a[9], OrionCOM_AY, 1
+instance = comp, \bdir~7 , bdir~7, OrionCOM_AY, 1
+instance = comp, \a[8]~I , a[8], OrionCOM_AY, 1
+instance = comp, \rd_n~I , rd_n, OrionCOM_AY, 1
+instance = comp, \bc1~9 , bc1~9, OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[1] , ayClkDiv|sum[1], OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[2] , ayClkDiv|sum[2], OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[3] , ayClkDiv|sum[3], OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[4] , ayClkDiv|sum[4], OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[5] , ayClkDiv|sum[5], OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[6] , ayClkDiv|sum[6], OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[7] , ayClkDiv|sum[7], OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[8] , ayClkDiv|sum[8], OrionCOM_AY, 1
+instance = comp, \ayClkDiv|Add0|adder[1]|result_node|sout_node[1]~32 , ayClkDiv|Add0|adder[1]|result_node|sout_node[1]~32, OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[9] , ayClkDiv|sum[9], OrionCOM_AY, 1
+instance = comp, \ayClkDiv|sum[9]~1 , ayClkDiv|sum[9]~1, OrionCOM_AY, 1
+instance = comp, \w1~I , w1, OrionCOM_AY, 1
+instance = comp, \irq3~I , irq3, OrionCOM_AY, 1
+instance = comp, \irq4~I , irq4, OrionCOM_AY, 1
+instance = comp, \reset~I , reset, OrionCOM_AY, 1
+instance = comp, \cs_vv2_n~I , cs_vv2_n, OrionCOM_AY, 1
+instance = comp, \cs_vi_n~I , cs_vi_n, OrionCOM_AY, 1
+instance = comp, \cs_vv1_n~I , cs_vv1_n, OrionCOM_AY, 1
+instance = comp, \clk1~I , clk1, OrionCOM_AY, 1
+instance = comp, \bdir~I , bdir, OrionCOM_AY, 1
+instance = comp, \bc1~I , bc1, OrionCOM_AY, 1
+instance = comp, \clk2~I , clk2, OrionCOM_AY, 1
+instance = comp, \debug~I , debug, OrionCOM_AY, 1
diff --git a/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY_v.sdo b/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY_v.sdo
new file mode 100644
index 0000000..f7555b9
--- /dev/null
+++ b/Firmware/OrionCOM-AY/simulation/modelsim/OrionCOM-AY_v.sdo
@@ -0,0 +1,852 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EPM7064STC44-7 Package TQFP44
+// 
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "OrionCOM_AY")
+  (DATE "02/05/2021 16:21:34")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 32-bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE wr_n\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE wait_n\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE w1\~1.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[1] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE rdy1\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (1500:1500:1500) (1500:1500:1500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE rdy1\~1.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE rdy2\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE rdy2\~1.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE reset_n\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (1500:1500:1500) (1500:1500:1500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE reset_n\~4.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[6\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[7\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE iorq_n\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[4\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[5\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[2\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[3\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE cs_vv2_n\~2.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[1] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[2] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[3] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[4] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[5] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[6] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE cs_vi_n\~3.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[1] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[2] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[3] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[4] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[5] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[6] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE cs_vv1_n\~2.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[1] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[2] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[3] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[4] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[5] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[6] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE clk\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (1500:1500:1500) (1500:1500:1500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE viClkDiv\|div1\[0\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE viClkDiv\|div1\[0\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE viClkDiv\|div1\[1\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE viClkDiv\|div1\[1\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE m1_n\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[0\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[1\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[9\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE bdir\~7.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[1] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[2] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[3] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[4] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[5] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[6] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[7] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[1] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[2] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[3] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[4] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[5] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[6] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[7] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[8] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[9] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[10] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[11] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE a\[8\]\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE rd_n\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio dataout (500:500:500) (500:500:500))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE bc1\~9.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[1] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[2] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[3] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[4] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[5] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[6] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[7] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[8] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[9] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[10] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[11] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm1[12] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[1] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[2] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[3] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[4] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[5] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[6] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[7] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[8] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[9] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[10] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[11] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm2[12] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm3[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm3[1] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm3[2] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm3[3] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm3[4] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm3[5] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm3[6] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm3[7] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm3[8] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm4[0] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm4[1] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm4[2] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm4[3] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm4[4] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm4[5] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm4[6] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm4[7] combout (4000:4000:4000) (4000:4000:4000))
+        (IOPATH pterm4[8] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[1\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pxor[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE ayClkDiv\|sum\[1\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[2\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pxor[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE ayClkDiv\|sum\[2\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[3\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pxor[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE ayClkDiv\|sum\[3\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[4\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pxor[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE ayClkDiv\|sum\[4\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[5\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pxor[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE ayClkDiv\|sum\[5\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[6\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm0[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pxor[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE ayClkDiv\|sum\[6\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[7\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm0[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm0[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pxor[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[3] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[3] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE ayClkDiv\|sum\[7\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[8\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm0[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm0[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pxor[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[3] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[4] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[3] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[3] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE ayClkDiv\|sum\[8\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|Add0\|adder\[1\]\|result_node\|sout_node\[1\]\~32.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] pexpout (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm1[1] pexpout (3000:3000:3000) (3000:3000:3000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[9\].pcom)
+    (DELAY
+      (ABSOLUTE
+        (PORT pexpin (0:0:0) (0:0:0))
+        (IOPATH pterm0[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm0[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm0[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm0[3] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm0[4] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pxor[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm2[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm3[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[0] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[1] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[2] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[3] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pterm4[4] regin (3000:3000:3000) (3000:3000:3000))
+        (IOPATH pexpin regin (800:800:800) (800:800:800))
+        (IOPATH fbkin regin (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_mcell_register")
+    (INSTANCE ayClkDiv\|sum\[9\].preg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (0:0:0) (0:0:0))
+        (PORT clk (0:0:0) (0:0:0))
+        (IOPATH (posedge clk) regout (1000:1000:1000) (1000:1000:1000))
+        (IOPATH (posedge aclr) regout (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (3000:3000:3000))
+      (HOLD datain (posedge clk) (2000:2000:2000))
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_mcell")
+    (INSTANCE ayClkDiv\|sum\[9\]\~1.pcom)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH pterm1[0] combout (4000:4000:4000) (4000:4000:4000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE w1\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE irq3\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE irq4\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE reset\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE cs_vv2_n\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE cs_vi_n\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE cs_vv1_n\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE clk1\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE bdir\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE bc1\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE clk2\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "max_asynch_io")
+    (INSTANCE debug\~I.asynch_inst)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datain padio (2000:2000:2000) (2000:2000:2000))
+      )
+    )
+  )
+)
diff --git a/Gerber/Gerber_PCB_COMPACT_v1.zip b/Gerber/Gerber_PCB_COMPACT_v1.zip
new file mode 100644
index 0000000..a17927b
Binary files /dev/null and b/Gerber/Gerber_PCB_COMPACT_v1.zip differ
diff --git a/README.md b/README.md
index b1bbf77..c3fb671 100644
--- a/README.md
+++ b/README.md
@@ -1,2 +1,5 @@
-# OPro-COM-AY
-Two serial ports and AY-sound board for Orion-PRO amateur personal computer
+OPro-COM-AY
+===========
+
+Плата с двумя COM-портами и со звуковым чипом AY-3-8912 для персонального любительского компьютера Орион-ПРО.
+