fix errors aft refactoring

This commit is contained in:
Роман Бойков 2026-03-08 00:05:03 +03:00
parent eb4339b86a
commit 9cb2af2145
3 changed files with 20 additions and 5 deletions

View File

@ -104,10 +104,10 @@ const RstTimerNo = 4
//const Rst7Mask = 0x80 // User device 1 interrupt
// PicDd75a Port A (a0=0)
//const PicDd75a = 0x80
const PicDd75a = 0x80
// PIC_DD75B Port B (a0=1)
//const PIC_DD75B = 0x81
const PicDd75b = 0x81
/*
* КР580ВВ51 DD72
@ -143,8 +143,8 @@ const SysDd17ctr = 0xC3
// LPT_DD67PA Port A - Printer Data
//const LPT_DD67PA = 0xE0
// VID_DD67PB Port B - Video control [VSU,C/M,FL3:1,COL3:1]
//const VID_DD67PB = 0xE1
// VidDd67pb Port B - Video control [VSU,C/M,FL3:1,COL3:1]
const VidDd67pb = 0xE1
// DD67PC Port C - [USER3:1, STB-LP, BELL, TAPE3:1]
//const DD67PC = 0xE2

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@ -15,6 +15,8 @@ func (c *ComputerType) IORead(port uint16) byte {
case PicDd75a:
// PIO xx59, get IRR register
return c.pic.IRR()
case PicDd75b:
return c.pic.CSW()
case UartDd72rr:
// USART VV51 CMD
return c.usart.Status()
@ -56,7 +58,7 @@ func (c *ComputerType) IOWrite(port uint16, val byte) {
}
case SysDd17ctr:
c.dd17EnableOut = val == 0x80
case VID_DD67PB:
case VidDd67pb:
if val&VidVsuBit == 0 {
// video page 0
c.vRAM = c.memory.allMemory[VRAMBlock0]
@ -96,6 +98,8 @@ func (c *ComputerType) IOWrite(port uint16, val byte) {
case UartDd72rd:
// USART VV51 Data
c.usart.Send(val)
case PicDd75b:
c.pic.SetCSW(val)
case FdcCmd:
c.fdc.SetCmd(val)
case FdcData:

View File

@ -11,11 +11,14 @@ import log "github.com/sirupsen/logrus"
type I8259 struct {
irr byte
csw byte
}
type I8259Interface interface {
SetIRQ(irq byte)
IRR() byte
CSW() byte
SetCSW(val byte)
}
func (c *I8259) IRR() byte {
@ -47,6 +50,14 @@ func (c *I8259) SetIRQ(irq byte) {
}
}
func (c *I8259) CSW() byte {
return c.csw
}
func (c *I8259) SetCSW(val byte) {
c.csw = val
}
func New() *I8259 {
return &I8259{
irr: 0,