mirror of
https://github.com/romychs/Ocean-240.2-Emulator.git
synced 2026-04-21 11:03:21 +03:00
476 lines
11 KiB
Go
476 lines
11 KiB
Go
package z80em
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var ddInstructions = []func(s *Z80Type){
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// 0x09 : ADD IX, BC
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0x09: func(s *Z80Type) {
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s.doIxAdd(s.bc())
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},
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// 0x19 : ADD IX, DE
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0x19: func(s *Z80Type) {
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s.doIxAdd(s.de())
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},
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// 0x21 : LD IX, nn
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0x21: func(s *Z80Type) {
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s.IX = s.nextWord()
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},
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// 0x22 : LD (nn), IX
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0x22: func(s *Z80Type) {
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s.setWord(s.nextWord(), s.IX)
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},
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// 0x23 : INC IX
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0x23: func(s *Z80Type) {
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s.IX++
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},
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// 0x24 : INC IXH (Undocumented)
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0x24: func(s *Z80Type) {
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s.IX = (uint16(s.doInc(byte(s.IX>>8))) << 8) | (s.IX & 0x00ff)
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},
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// 0x25 : DEC IXH (Undocumented)
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0x25: func(s *Z80Type) {
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s.IX = (uint16(s.doDec(byte(s.IX>>8))) << 8) | (s.IX & 0x00ff)
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},
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// 0x26 : LD IXH, n (Undocumented)
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0x26: func(s *Z80Type) {
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s.PC++
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s.IX = (uint16(s.core.MemRead(s.PC)) << 8) | (s.IX & 0x00ff)
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},
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// 0x29 : ADD IX, IX
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0x29: func(s *Z80Type) {
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s.doIxAdd(s.IX)
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},
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// 0x2a : LD IX, (nn)
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0x2A: func(s *Z80Type) {
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s.IX = s.getWord(s.nextWord())
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},
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// 0x2b : DEC IX
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0x2B: func(s *Z80Type) {
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s.IX--
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},
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// 0x2c : INC IXL (Undocumented)
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0x2C: func(s *Z80Type) {
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s.IX = (uint16(s.doInc(byte(s.IX & 0x00ff)))) | (s.IX & 0xff00)
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},
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// 0x2d : DEC IXL (Undocumented)
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0x2D: func(s *Z80Type) {
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s.IX = (uint16(s.doDec(byte(s.IX & 0x00ff)))) | (s.IX & 0xff00)
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},
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// 0x2e : LD IXL, n (Undocumented)
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0x2E: func(s *Z80Type) {
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s.PC++
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s.IX = (uint16(s.core.MemRead(s.PC))) | (s.IX & 0xff00)
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},
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// 0x34 : INC (IX+n)
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0x34: func(s *Z80Type) {
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offset := s.getOffset(s.IX)
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value := s.core.MemRead(offset)
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s.core.MemWrite(offset, s.doInc(value))
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},
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// 0x35 : DEC (IX+n)
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0x35: func(s *Z80Type) {
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offset := s.getOffset(s.IX)
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value := s.core.MemRead(offset)
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s.core.MemWrite(offset, s.doDec(value))
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},
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// 0x36 : LD (IX+n), n
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0x36: func(s *Z80Type) {
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offset := s.getOffset(s.IX)
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s.PC++
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s.core.MemWrite(offset, s.core.MemRead(s.PC))
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},
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// 0x39 : ADD IX, SP
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0x39: func(s *Z80Type) {
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s.doIxAdd(s.SP)
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},
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// 0x44 : LD B, IXH (Undocumented)
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0x44: func(s *Z80Type) {
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s.B = byte(s.IX >> 8)
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},
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// 0x45 : LD B, IXL (Undocumented)
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0x45: func(s *Z80Type) {
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s.B = byte(s.IX & 0x00ff)
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},
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// 0x46 : LD B, (IX+n)
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0x46: func(s *Z80Type) {
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s.B = s.core.MemRead(s.getOffset(s.IX))
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},
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// 0x4c : LD C, IXH (Undocumented)
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0x4C: func(s *Z80Type) {
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s.C = byte(s.IX >> 8)
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},
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// 0x4d : LD C, IXL (Undocumented)
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0x4D: func(s *Z80Type) {
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s.C = byte(s.IX & 0x00ff)
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},
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// 0x4e : LD C, (IX+n)
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0x4E: func(s *Z80Type) {
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s.C = s.core.MemRead(s.getOffset(s.IX))
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},
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// 0x54 : LD D, IXH (Undocumented)
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0x54: func(s *Z80Type) {
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s.D = byte(s.IX >> 8)
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},
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// 0x55 : LD D, IXL (Undocumented)
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0x55: func(s *Z80Type) {
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s.D = byte(s.IX)
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},
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// 0x56 : LD D, (IX+n)
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0x56: func(s *Z80Type) {
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offset := s.getOffset(s.IX)
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s.D = s.core.MemRead(offset)
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},
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// 0x5d : LD E, IXL (Undocumented)
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0x5D: func(s *Z80Type) {
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s.E = byte(s.IX)
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},
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// 0x5e : LD E, (IX+n)
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0x5E: func(s *Z80Type) {
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s.E = s.core.MemRead(s.getOffset(s.IX))
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},
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// 0x60 : LD IXH, B (Undocumented)
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0x60: func(s *Z80Type) {
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s.IX = uint16(s.B)<<8 | s.IX&0x00ff
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},
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// 0x61 : LD IXH, C (Undocumented)
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0x61: func(s *Z80Type) {
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s.IX = uint16(s.C)<<8 | s.IX&0x00ff
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},
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// 0x62 : LD IXH, D (Undocumented)
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0x62: func(s *Z80Type) {
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s.IX = uint16(s.D)<<8 | s.IX&0x00ff
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},
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// 0x63 : LD IXH, E (Undocumented)
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0x63: func(s *Z80Type) {
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s.IX = uint16(s.E)<<8 | s.IX&0x00ff
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},
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// 0x64 : LD IXH, IXH (Undocumented)
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0x64: func(s *Z80Type) {
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// NOP
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},
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// 0x65 : LD IXH, IXL (Undocumented)
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0x65: func(s *Z80Type) {
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s.IX = (s.IX << 8) | (s.IX & 0x00ff)
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},
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// 0x66 : LD H, (IX+n)
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0x66: func(s *Z80Type) {
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s.H = s.core.MemRead(s.getOffset(s.IX))
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},
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// 0x67 : LD IXH, A (Undocumented)
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0x67: func(s *Z80Type) {
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s.IX = (uint16(s.A) << 8) | (s.IX & 0x00ff)
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},
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// 0x68 : LD IXL, B (Undocumented)
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0x68: func(s *Z80Type) {
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s.IX = (s.IX & 0xff00) | uint16(s.B)
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},
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// 0x69 : LD IXL, C (Undocumented)
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0x69: func(s *Z80Type) {
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s.IX = (s.IX & 0xff00) | uint16(s.C)
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},
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// 0x6a : LD IXL, D (Undocumented)
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0x6a: func(s *Z80Type) {
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s.IX = (s.IX & 0xff00) | uint16(s.D)
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},
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// 0x6b : LD IXL, E (Undocumented)
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0x6b: func(s *Z80Type) {
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s.IX = (s.IX & 0xff00) | uint16(s.E)
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},
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// 0x6c : LD IXL, IXH (Undocumented)
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0x6c: func(s *Z80Type) {
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s.IX = (s.IX >> 8) | (s.IX & 0xff00)
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},
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// 0x6d : LD IXL, IXL (Undocumented)
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0x6d: func(s *Z80Type) {
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// NOP
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},
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// 0x6e : LD L, (IX+n)
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0x6e: func(s *Z80Type) {
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s.L = s.core.MemRead(s.getOffset(s.IX))
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},
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// 0x6f : LD IXL, A (Undocumented)
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0x6f: func(s *Z80Type) {
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s.IX = uint16(s.A) | (s.IX & 0xff00)
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},
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// 0x70 : LD (IX+n), B
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0x70: func(s *Z80Type) {
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s.core.MemWrite(s.getOffset(s.IX), s.B)
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},
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// 0x71 : LD (IX+n), C
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0x71: func(s *Z80Type) {
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s.core.MemWrite(s.getOffset(s.IX), s.C)
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},
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// 0x72 : LD (IX+n), D
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0x72: func(s *Z80Type) {
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s.core.MemWrite(s.getOffset(s.IX), s.D)
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},
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// 0x73 : LD (IX+n), E
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0x73: func(s *Z80Type) {
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s.core.MemWrite(s.getOffset(s.IX), s.E)
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},
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// 0x74 : LD (IX+n), H
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0x74: func(s *Z80Type) {
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s.core.MemWrite(s.getOffset(s.IX), s.H)
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},
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// 0x75 : LD (IX+n), L
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0x75: func(s *Z80Type) {
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s.core.MemWrite(s.getOffset(s.IX), s.L)
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},
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// 0x77 : LD (IX+n), A
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0x77: func(s *Z80Type) {
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s.core.MemWrite(s.getOffset(s.IX), s.A)
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},
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// 0x7c : LD A, IXH (Undocumented)
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0x7C: func(s *Z80Type) {
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s.A = byte(s.IX >> 8)
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},
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// 0x7d : LD A, IXL (Undocumented)
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0x7D: func(s *Z80Type) {
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s.A = byte(s.IX & 0x00ff)
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},
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// 0x7e : LD A, (IX+n)
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0x7E: func(s *Z80Type) {
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s.A = s.core.MemRead(s.getOffset(s.IX))
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},
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// 0x84 : ADD A, IXH (Undocumented)
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0x84: func(s *Z80Type) {
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s.doAdd(byte(s.IX >> 8))
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},
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// 0x85 : ADD A, IXL (Undocumented)
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0x85: func(s *Z80Type) {
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s.doAdd(byte(s.IX))
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},
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// 0x86 : ADD A, (IX+n)
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0x86: func(s *Z80Type) {
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s.doAdd(s.core.MemRead(s.getOffset(s.IX)))
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},
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// 0x8c : ADC A, IXH (Undocumented)
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0x8C: func(s *Z80Type) {
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s.doAdc(byte(s.IX >> 8))
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},
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// 0x8d : ADC A, IXL (Undocumented)
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0x8D: func(s *Z80Type) {
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s.doAdc(byte(s.IX))
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},
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// 0x8e : ADC A, (IX+n)
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0x8E: func(s *Z80Type) {
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s.doAdc(s.core.MemRead(s.getOffset(s.IX)))
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},
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// 0x94 : SUB IXH (Undocumented)
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0x94: func(s *Z80Type) {
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s.doSub(byte(s.IX >> 8))
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},
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// 0x95 : SUB IXL (Undocumented)
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0x95: func(s *Z80Type) {
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s.doSub(byte(s.IX))
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},
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// 0x96 : SUB A, (IX+n)
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0x96: func(s *Z80Type) {
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s.doSub(s.core.MemRead(s.getOffset(s.IX)))
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},
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// 0x9c : SBC IXH (Undocumented)
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0x9C: func(s *Z80Type) {
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s.doSbc(byte(s.IX >> 8))
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},
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// 0x9d : SBC IXL (Undocumented)
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0x9D: func(s *Z80Type) {
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s.doSbc(byte(s.IX))
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},
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// 0x9e : SBC A, (IX+n)
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0x9E: func(s *Z80Type) {
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s.doSbc(s.core.MemRead(s.getOffset(s.IX)))
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},
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// 0xa4 : AND IXH (Undocumented)
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0xA4: func(s *Z80Type) {
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s.doAnd(byte(s.IX >> 8))
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},
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// 0xa5 : AND IXL (Undocumented)
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0xA5: func(s *Z80Type) {
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s.doAnd(byte(s.IX))
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},
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// 0xa6 : AND A, (IX+n)
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0xA6: func(s *Z80Type) {
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s.doAnd(s.core.MemRead(s.getOffset(s.IX)))
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},
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// 0xac : XOR IXH (Undocumented)
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0xAC: func(s *Z80Type) {
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s.doXor(byte(s.IX >> 8))
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},
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// 0xad : XOR IXL (Undocumented)
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0xAD: func(s *Z80Type) {
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s.doXor(byte(s.IX))
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},
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// 0xae : XOR A, (IX+n)
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0xAE: func(s *Z80Type) {
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s.doXor(s.core.MemRead(s.getOffset(s.IX)))
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},
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// 0xb4 : OR IXH (Undocumented)
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0xB4: func(s *Z80Type) {
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s.doOr(byte(s.IX >> 8))
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},
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// 0xb5 : OR IXL (Undocumented)
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0xB5: func(s *Z80Type) {
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s.doOr(byte(s.IX))
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},
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// 0xb6 : OR A, (IX+n)
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0xB6: func(s *Z80Type) {
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s.doOr(s.core.MemRead(s.getOffset(s.IX)))
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},
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// 0xbc : CP IXH (Undocumented)
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0xBC: func(s *Z80Type) {
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s.doCp(byte(s.IX >> 8))
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},
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// 0xbd : CP IXL (Undocumented)
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0xBD: func(s *Z80Type) {
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s.doCp(byte(s.IX))
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},
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// 0xbe : CP A, (IX+n)
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0xBE: func(s *Z80Type) {
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s.doCp(s.core.MemRead(s.getOffset(s.IX)))
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},
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// 0xcb : CB Prefix (IX bit instructions)
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0xCB: func(s *Z80Type) {
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s.opcodeDDCB()
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},
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// 0xe1 : POP IX
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0xE1: func(s *Z80Type) {
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s.IX = s.PopWord()
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},
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// 0xe3 : EX (SP), IX
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0xE3: func(s *Z80Type) {
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ix := s.IX
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s.IX = s.getWord(s.SP)
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s.setWord(s.SP, ix)
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},
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// 0xe5 : PUSH IX
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0xE5: func(s *Z80Type) {
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s.pushWord(s.IX)
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},
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// 0xe9 : JP (IX)
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0xE9: func(s *Z80Type) {
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s.PC = s.IX - 1
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},
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// 0xf9 : LD SP, IX
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0xf9: func(s *Z80Type) {
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s.SP = s.IX
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},
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}
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// =====================================================
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func (z *Z80Type) getOffset(reg uint16) uint16 {
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z.PC++
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offset := z.core.MemRead(z.PC)
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if offset < 0 {
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reg -= uint16(-offset)
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} else {
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reg += uint16(offset)
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}
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return reg
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}
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func (z *Z80Type) opcodeDD() {
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z.incR()
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z.PC++
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opcode := z.core.M1MemRead(z.PC)
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fun := ddInstructions[opcode]
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if fun != nil {
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fun(z)
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z.CycleCounter += CycleCountsDd[opcode]
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} else {
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// Apparently if a DD opcode doesn't exist,
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// it gets treated as an unprefixed opcode.
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// What we'll do to handle that is just back up the
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// program counter, so that this byte gets decoded
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// as a normal instruction.
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z.PC--
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// And we'll add in the cycle count for a NOP.
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z.CycleCounter += CycleCounts[0]
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}
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}
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func (z *Z80Type) opcodeDDCB() {
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offset := z.getOffset(z.IX)
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z.PC++
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opcode := z.core.MemRead(z.PC)
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value := byte(0)
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bitTestOp := false
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// As with the "normal" CB prefix, we implement the DDCB prefix
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// by decoding the opcode directly, rather than using a table.
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if opcode < 0x40 {
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// Shift and rotate instructions.
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ddcbFunctions := []OpShift{z.doRlc, z.doRrc, z.doRl, z.doRr, z.doSla, z.doSra, z.doSll, z.doSrl}
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// Most of the opcodes in this range are not valid,
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// so we map this opcode onto one of the ones that is.
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fun := ddcbFunctions[(opcode&0x38)>>3]
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value = fun(z.core.MemRead(offset))
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z.core.MemWrite(offset, value)
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} else {
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bitNumber := (opcode & 0x38) >> 3
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if opcode < 0x80 {
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// bit test
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bitTestOp = true
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z.Flags.N = false
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z.Flags.H = true
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z.Flags.Z = z.core.MemRead(offset)&(1<<bitNumber) == 0
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z.Flags.P = z.Flags.Z
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z.Flags.S = (bitNumber == 7) && !z.Flags.Z
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} else if opcode < 0xc0 {
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// RES
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value = z.core.MemRead(offset) & (^(1 << bitNumber))
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z.core.MemWrite(offset, value)
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} else {
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// SET
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value = z.core.MemRead(offset) | (1 << bitNumber)
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z.core.MemWrite(offset, value)
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}
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}
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// This implements the undocumented shift, RES, and SET opcodes,
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// which write their result to memory and also to an 8080 register.
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if !bitTestOp {
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//value := byte(1)
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switch opcode & 0x07 {
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case 0:
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z.B = value
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case 1:
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z.C = value
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case 2:
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z.D = value
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case 3:
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z.E = value
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case 4:
|
|
z.H = value
|
|
case 5:
|
|
z.L = value
|
|
// 6 is the documented opcode, which doesn't set a register.
|
|
case 7:
|
|
z.A = value
|
|
}
|
|
}
|
|
|
|
z.CycleCounter += CycleCountsCb[opcode] + 8
|
|
}
|
|
|
|
// opcodeFD do same for IY as for IX (DD prefix)
|
|
func (z *Z80Type) opcodeFD() {
|
|
z.incR()
|
|
z.PC++
|
|
opcode := z.core.M1MemRead(z.PC)
|
|
fun := ddInstructions[opcode]
|
|
if fun != nil {
|
|
var temp = z.IX
|
|
z.IX = z.IY
|
|
fun(z)
|
|
z.IY = z.IX
|
|
z.IX = temp
|
|
z.CycleCounter += CycleCountsDd[opcode]
|
|
} else {
|
|
z.PC--
|
|
z.CycleCounter += CycleCounts[0]
|
|
}
|
|
}
|