mirror of
https://github.com/romychs/Ocean-240.2-Emulator.git
synced 2026-04-21 11:03:21 +03:00
109 lines
2.4 KiB
Go
109 lines
2.4 KiB
Go
package js
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func (z *Z80) opcodeCB() {
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z.incR()
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z.PC++
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opcode := z.core.M1MemRead(z.PC)
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bitNumber := (opcode & 0x38) >> 3
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regCode := opcode & 0x07
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if opcode < 0x40 {
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// Shift/rotate instructions
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opArray := []OpShift{z.doRlc, z.doRrc, z.doRl, z.doRr, z.doSla, z.doSra, z.doSll, z.doSrl}
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switch regCode {
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case 0:
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z.B = opArray[bitNumber](z.B)
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case 1:
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z.C = opArray[bitNumber](z.C)
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case 2:
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z.D = opArray[bitNumber](z.D)
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case 3:
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z.E = opArray[bitNumber](z.E)
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case 4:
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z.H = opArray[bitNumber](z.H)
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case 5:
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z.L = opArray[bitNumber](z.L)
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case 6:
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z.core.MemWrite(z.hl(), opArray[bitNumber](z.core.MemRead(z.hl())))
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default:
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z.A = opArray[bitNumber](z.A)
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}
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} else if opcode < 0x80 {
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// BIT instructions
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mask := byte(1 << bitNumber)
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switch regCode {
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case 0:
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z.Flags.Z = z.B&mask == 0
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case 1:
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z.Flags.Z = z.C&mask == 0
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case 2:
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z.Flags.Z = z.D&mask == 0
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case 3:
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z.Flags.Z = z.E&mask == 0
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case 4:
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z.Flags.Z = z.H&mask == 0
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case 5:
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z.Flags.Z = z.L&mask == 0
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case 6:
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z.Flags.Z = z.core.MemRead(z.hl())&mask == 0
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default:
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z.Flags.Z = z.A&mask == 0
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}
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z.Flags.N = false
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z.Flags.H = true
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z.Flags.P = z.Flags.Z
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z.Flags.S = (bitNumber == 7) && !z.Flags.Z
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// TODO: ZXALL fail this
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// For the BIT n, (HL) instruction, the X and Y flags are obtained
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// from what is apparently an internal temporary register used for
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// some of the 16-bit arithmetic instructions.
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// I haven't implemented that register here,
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// so for now we'll set X and Y the same way for every BIT opcode,
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// which means that they will usually be wrong for BIT n, (HL).
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z.Flags.Y = (bitNumber == 5) && !z.Flags.Z
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z.Flags.X = (bitNumber == 3) && !z.Flags.Z
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} else if opcode < 0xC0 {
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// RES instructions
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negMask := byte(^(1 << bitNumber))
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switch regCode {
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case 0:
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z.B &= negMask
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case 1:
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z.C &= negMask
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case 2:
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z.D &= negMask
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case 3:
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z.E &= negMask
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case 4:
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z.H &= negMask
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case 5:
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z.L &= negMask
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case 6:
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z.core.MemWrite(z.hl(), z.core.MemRead(z.hl())&negMask)
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default:
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z.A &= negMask
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}
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} else {
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// SET instructions
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mask := byte(1 << bitNumber)
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switch regCode {
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case 0:
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z.B |= mask
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case 1:
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z.C |= mask
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case 2:
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z.D |= mask
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case 3:
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z.E |= mask
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case 4:
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z.H |= mask
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case 5:
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z.L |= mask
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case 6:
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z.core.MemWrite(z.hl(), z.core.MemRead(z.hl())|mask)
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default:
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z.A |= mask
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}
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}
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z.CycleCounter += CycleCountsCb[opcode]
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}
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