mirror of
https://github.com/romychs/Ocean-240.2-Emulator.git
synced 2026-04-21 11:03:21 +03:00
76 lines
1.3 KiB
Go
76 lines
1.3 KiB
Go
package okean240
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import (
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"z80em/config"
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"z80em/z80em"
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log "github.com/sirupsen/logrus"
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)
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type ComputerType struct {
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cpu z80em.Z80Type
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memory Memory
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ioPorts [256]byte
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cycles uint64
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dd17EnableOut bool
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}
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type ComputerInterface interface {
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//Init(rom0 string, rom1 string)
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Run()
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}
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func (c *ComputerType) M1MemRead(addr uint16) byte {
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return c.memory.M1MemRead(addr)
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}
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func (c *ComputerType) MemRead(addr uint16) byte {
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return c.memory.MemRead(addr)
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}
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func (c *ComputerType) MemWrite(addr uint16, val byte) {
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c.memory.MemWrite(addr, val)
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}
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func (c *ComputerType) IORead(port uint16) byte {
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return c.ioPorts[port]
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}
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func (c *ComputerType) IOWrite(port uint16, val byte) {
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c.ioPorts[byte(port&0x00ff)] = val
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switch byte(port & 0x00ff) {
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case SYS_DD17PB:
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if c.dd17EnableOut {
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c.memory.Configure(val)
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}
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case SYS_DD17CTR:
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c.dd17EnableOut = val == 0x80
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case KBD_DD78CTR:
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}
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}
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// New Builds new computer
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func New(cfg config.OkEmuConfig) *ComputerType {
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c := ComputerType{}
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c.memory = Memory{}
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c.memory.Init(cfg.MonitorFile, cfg.CPMFile)
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c.cpu = *z80em.New(&c)
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c.cycles = 0
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c.dd17EnableOut = false
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return &c
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}
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func (c *ComputerType) Run() {
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c.cpu.Reset()
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for {
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state := c.cpu.GetState()
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log.Infof("%d - [%x]: %x\n", c.cycles, state.PC, c.MemRead(state.PC))
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c.cycles += uint64(c.cpu.RunInstruction())
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}
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}
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