First fixed version

Export/README.md

@@ -0,0 +1,3 @@
+Sprinter-ESP
+============
+Схема и печатная плата в доступных для просмотра форматах.

Gerber/README.md

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+Sprinter-ESP
+============
+
+При заказе платы, не забудте указать, что плата имеет контакты на краю платы и нужен скос, для удобства вставки платы в слот.

LICENSE

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+BSD 3-Clause License
+
+Copyright (c) 2021, Roman Boykov
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

README.md

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+Sprinter-ESP
+============
+
+Проект ISA-8 платы для подключения Wi-Fi модуля ESP8266 к персональному любительскому компьютеру Sprinter.
+
+Программное обеспечение, в настоящее время, в разработке.
+
+![image](Export/sprinter-esp.jpg)
+
+[Принципиальная схема](Export/Schematic_Sprinter-ESP_v1.0.2.pdf)
+
+[Монтажная схема](Export/PCB_Sprinter-ESP-v1.0.2.pdf)
+
+
+[Спринтер в Телеграм](https://t.me/zx_sprinter)
+[Спринтер в Web](https://www.sprinter.ru/)

Sources/ESPLib/esplib.asm

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+; ===========================================
+; SOLID C  Lbrary to work with Sprinter WiFi 
+; ESP ISA Card
+; ===========================================
+
+               DEVICE NOSLOT64K
+               ;INCLUDE "ports.inc"
+
+port_isa	   EQU 0x9FBD
+port_system EQU 0x1FFD
+emm_win_p3 	EQU 0xE2
+
+ISA_BASE_A 	EQU 0xC000                    ; Базовый адрес портов ISA в памяти
+PORT_UART   EQU 0x03E8                    ; Базовый номер порта COM3
+PORT_UART_A EQU ISA_BASE_A + PORT_UART    ; Порты чипа UART в памяти 
+
+            ; Порты UART TC16C550 в памяти 
+RBR 			EQU PORT_UART_A + 0
+THR 			EQU PORT_UART_A + 0
+IER 			EQU PORT_UART_A + 1
+IIR 			EQU PORT_UART_A + 2
+FCR 			EQU PORT_UART_A + 2
+LCR 			EQU PORT_UART_A + 3
+MCR 			EQU PORT_UART_A + 4
+LSR 			EQU PORT_UART_A + 5
+MSR 			EQU PORT_UART_A + 6
+SCR 			EQU PORT_UART_A + 7
+DLL 			EQU PORT_UART_A + 0
+DLM 			EQU PORT_UART_A + 1
+AFR 			EQU PORT_UART_A + 2
+
+BAUD_RATE 	EQU 115200                    ; Скорость соединения с ESP8266
+XIN_FREQ 	EQU 14745600                  ; Частота генератора для TL16C550
+DIVISOR 		EQU XIN_FREQ / (BAUD_RATE * 16)  ; Делитель частоты для передачи/приема данных
+
+            ORG 0x0000
+            jp main
+
+save_mmu3	DB 0		; Variable to save memory page
+
+				; ===============================================
+				; Small delay
+				; void delay(hl)
+				; in hl - number of cycles, if hl=0, then 2000
+				; ===============================================
+            MODULE delay
+delay_:
+				push af
+				ld a,h
+				or l
+				jp nz,delay_l1
+				ld hl,2000
+delay_l1:	dec hl
+				ld a,h
+				or l
+				jp nz,delay_l1
+				pop af
+				ret
+				ENDMODULE
+
+				; ===============================================
+				; Reset ISA device
+				; ===============================================
+            MODULE reset_isa
+reset_isa_:
+				push af
+				push bc
+            push hl
+				ld bc, port_isa
+            ld a, 0xC0		   ; RESET=1 AEN=1
+				out (c), a
+				ld hl,2000
+				call delay.delay_
+            xor a
+            out (c), a        ; RESET=0 AEN=0
+            add hl,hl
+            call delay.delay_
+            pop hl
+            pop bc
+            pop af
+            ret
+            ENDMODULE 
+
+				; ===============================================
+            ; Open access to ISA ports as memory
+            ;   input a = 0 - ISA slot 0, 1 - ISA SLOT 1
+				; ===============================================
+            MODULE open_isa
+open_isa_:
+            push af
+            push bc
+            ld bc, emm_win_p3
+            in a,(c)
+            ld (save_mmu3), a
+            push bc
+            ld bc, port_system
+            ld a, 0x11
+            out (c), a
+            pop bc            ; emm_win_p3
+            pop af
+            and a, 0x01
+            rlca
+            rlca
+            or a, 0xd0        ; 1101 - Magic number, 0100 - 0,ISA PORT, ISA SLOT, 0
+            out (c), a
+            ld bc, port_system
+            xor a
+            out (c), a
+            pop bc
+            
+            ret
+            ENDMODULE
+
+				; ===============================================
+            ; Close access to ISA ports
+				; ===============================================
+            MODULE close_isa
+close_isa_:
+            push af
+            push bc
+            ld bc, port_system
+            ld a, 0x01
+            out (c), a
+            ld a, save_mmu3
+            ld bc, emm_win_p3
+            out (c), a
+            pop bc
+            pop af
+            ret
+            ENDMODULE
+
+				; ===============================================
+            ;  Init ISA device
+				; ===============================================
+            MODULE init_isa
+init_isa_:
+            call reset_isa.reset_isa_      ; just only reset
+            ret            
+            ENDMODULE
+
+				; ===============================================
+            ; Init UART device TL16C550
+				; ===============================================
+            MODULE init_serial
+init_serial_:
+            push af
+            push hl
+            call open_isa.open_isa_
+            ld a, 1
+            ld (FCR), a            ; 8 byte FIFO buffer
+            ld a, 0x81   
+            ld (FCR), a
+            xor a
+            ld (IER), a            ; Disable interrupts
+            
+            ; Set baud rate
+            ld a, 0x83
+            ld (LCR), a            ; enable Baud rate latch
+            ld a, DIVISOR
+            ld (DLL), a            ; 8 - 115200
+            xor a
+            ld (DLM), a            
+            ld a, 0x03           ; disable Baud rate latch & 8N1
+            ld (LCR), a
+            
+            ; reset ESP
+            ld a,0x06            ; ESP -PGM=1, -RTS=0
+            ld (MCR), a
+            ld hl,2000
+            call delay.delay_
+            ld a,0x02            ; ESP -RST=1, -RTS=0
+            call delay.delay_
+            call close_isa.close_isa_
+            pop hl
+            pop af
+            ret
+            ENDMODULE
+
+				; ===============================================
+            ; Read TL16C550 register
+            ;   char read_reg(reg)
+            ;   input hl - register no
+            ;   output a - value from register
+				; ===============================================
+            MODULE read_reg
+read_reg_:  
+            call open_isa.open_isa_
+            ld a, (hl)
+            call close_isa.close_isa_
+            ret
+            ENDMODULE
+
+				; ===============================================
+            ; Write TL16C550 register
+            ;   void write_reg(reg, b)
+            ;   input hl - reg no, e - value            
+				; ===============================================
+            MODULE write_reg
+write_reg_:            
+            call open_isa.open_isa_
+            ld (hl), e
+            call close_isa.close_isa_
+            ret
+            ENDMODULE
+
+				; ===============================================
+            ; Wait for transmitter ready
+            ;   char wait_tr()
+            ;   output a = 0 - tr not ready, !=0 - tr ready
+				; ===============================================
+            MODULE wait_tr
+wait_tr_: 
+            push bc
+            push hl
+            ld bc, 100
+            ld hl, LSR
+wait_tr_r:            
+            call read_reg.read_reg_
+            and a, 0x20
+            jp nz,wait_tr_e
+            dec bc
+            ld a, c
+            or b
+            jp nz,wait_tr_r
+            xor a
+wait_tr_e:
+            pop hl
+            pop bc
+            ret
+            ENDMODULE
+
+				; ===============================================
+            ; Empty receiver FIFO buffer
+            ;   void empty_rs()
+				; ===============================================
+            MODULE empty_rs
+empty_rs_: 
+            push af
+            call open_isa.open_isa_
+            ld a, 0x83
+            ld (FCR), a
+            call close_isa.close_isa_
+            pop af
+            ret
+            ENDMODULE
+
+				; ===============================================
+            ; Wait byte in receiver fifo
+            ; char wait_rs()
+            ; output a=0 - fifo still empty, a!=0 - receiver fifo is not empty
+				; ===============================================
+            MODULE wait_rs
+wait_rs_:    
+            push bc
+            push hl
+            ld bc, 1000
+            ld hl, LSR
+wait_rs_r:            
+            call read_reg.read_reg_
+            and a, 0x01
+            jp nz,wait_rs_e
+            dec bc
+            ld a, c
+            or b
+            jp nz,wait_rs_r
+            xor a
+wait_rs_e:
+            pop hl
+            pop bc
+            ret
+            ENDMODULE
+
+				; ===============================================
+            ;  STUB
+				; ===============================================
+
+main:
+            call init_isa.init_isa_
+            ret

Sources/ESPLib/esplib.h

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+#pragma nonrec
+
+#define port_isa 0x9FBD
+#define port_system 0x1FFD
+#define isa_addr_base 0xC000
+#define com3_addr_base 0x3E8
+#define emm_win_p3 0xE2
+#define port_serial 0xC3E8
+
+#define RBR port_serial
+#define THR port_serial
+#define IER port_serial+1
+#define IIR port_serial+2
+#define FCR port_serial+2
+#define LCR port_serial+3
+#define MCR port_serial+4
+#define LSR port_serial+5
+#define MSR port_serial+6
+#define SCR port_serial+7
+#define DLL port_serial
+#define DLM port_serial+1
+#define AFR port_serial+2
+
+#define BAUD_RATE 115200
+#define XIN_FREQ 14745600
+#define DIVISOR XIN_FREQ / (BAUD_RATE * 16)
+
+   
+/**
+ * Small delay
+ */
+void delay();
+
+/**
+ * Reset ISA device
+ */
+void reset_isa();
+
+/*
+ * Open access to ISA ports as memory
+ */
+void open_isa();
+   
+/*
+ * Close access to ISA ports
+ */
+void close_isa();
+
+/*
+ *  Init ISA device
+ */
+void init_isa();
+
+/*
+ * Init UART device TL16C550
+ */
+void init_serial();
+
+/*
+ * Read TL16C550 register
+ */
+char read_reg();
+
+/*
+ * Write TL16C550 register
+ */
+void write_reg();
+
+/*
+ * Wait for transmitter ready
+ */
+void wait_tr();
+
+/*
+ * Clear receiver FIFO buffer
+ */
+void empty_rs();
+
+/*
+ * Wait byte in receiver fifo
+ */
+void wait_rs();
+

Sources/README.md

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+Sprinter-ESP
+============
+
+Исходники проекта в [EasyIDA:](https://easyeda.com/)
+
+Как использовать:
+В редакторе, кликнуть на тулбаре в меню "Document" > "Open" > "EasyEDA Source", и выберите json-файл.
+

Sources/TestESP/TESTESP.C

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+#pragma nonrec
+
+#include <stdio.h>
+#include <conio.h>
+#include <dos.h>
+
+unsigned port;
+char b;
+char save_mmu3;
+
+#define port_isa 0x9FBD
+#define port_system 0x1FFD
+#define isa_addr_base 0xC000
+#define com3_addr_base 0x3E8
+#define emm_win_p3 0xE2
+#define port_serial 0xC3E8
+
+#define RBR port_serial
+#define THR port_serial
+#define IER port_serial+1
+#define IIR port_serial+2
+#define FCR port_serial+2
+#define LCR port_serial+3
+#define MCR port_serial+4
+#define LSR port_serial+5
+#define MSR port_serial+6
+#define SCR port_serial+7
+#define DLL port_serial
+#define DLM port_serial+1
+#define AFR port_serial+2
+  
+/*
+ #define BAUD_RATE 115200
+ #define XIN_FREQ 14745600
+ #define DIVISOR XIN_FREQ / (BAUD_RATE * 16)
+*/
+   
+/**
+ * Small delay
+ */
+delay() {
+   unsigned ctr;
+   for (ctr=0; ctr<2000; ctr++) {
+   }
+}
+
+/**
+ * Reset ISA device
+ */
+reset_isa() {
+   outp(port_isa, 0xc0); // RESET=1 AEN=1
+   delay();
+   outp(port_isa,0); // RESET=0 AEN=0
+   delay();
+   delay();
+}
+
+/*
+ * Open access to ISA ports as memory
+ */
+open_isa() {
+   save_mmu3 = inp(emm_win_p3);
+   outp(port_system, 0x11);
+   outp(emm_win_p3, 0xd4);
+   outp(port_isa, 0);
+}                              
+   
+/*
+ * Close access to ISA ports
+ */
+close_isa() {
+   outp(port_system, 0x01);
+   outp(emm_win_p3, save_mmu3);
+}
+
+/*
+ *  Init ISA device
+ */
+init_isa() {
+   reset_isa();    // just only reset
+}            
+
+unsigned addr;
+char lcr;
+char *ptr;
+
+/*
+ * Init UART device TL16C550
+ */
+init_serial() {
+   open_isa(); 
+   mset(FCR, 0x01);  // 8 byte FIFO buffer
+   mset(FCR, 0x81);
+   mset(IER, 0x00);  // Disable interrupts
+
+   mset(LCR, 0x83);  // enable Baud rate latch
+   mset(DLL, 0x08);  // 8 - 115200;
+   mset(DLM, 0x00);
+
+   mset(LCR, 0x03);  // dis Baud rate latch & 8N1
+   
+   // reset ESP
+   mset(MCR, 0x06); // ESP -PGM=1, -RTS=0
+   delay();
+   mset(MCR, 0x02); // ESP -RST=1, -RTS=0
+   delay();
+   close_isa();
+}
+   
+char read_reg(reg)
+unsigned reg;
+{  
+   char rb;
+   open_isa();
+   rb = mget(reg);
+   close_isa();
+   return rb;
+}   
+
+
+void write_reg(reg, b)
+unsigned reg;
+char b;
+{
+   open_isa();
+   mset(reg, b);
+   close_isa();
+}
+
+char *scr_ptr = SCR;
+
+void write_sr(b)
+char b;
+{
+   open_isa();
+   *scr_ptr = b;
+   close_isa();
+}              
+
+char read_sr() {
+   char rb;
+   open_isa();
+   rb = *scr_ptr;
+   close_isa();
+   return rb;
+}
+
+void wait_tr() {
+   unsigned w;
+   char ls;
+   w = 0;
+   ls = read_reg(LSR);
+   while ((ls & 0x20) == 0 && w<100) {
+     delay(20);
+     ls = read_reg(LSR);
+     w++;
+   }
+}              
+
+/*
+ * Empty receiver FIFO buffer
+ */
+void empty_rs() {
+   open_isa();
+   mset(FCR, 0x83);
+   close_isa();
+}                            
+
+/*
+ * Wait byte in receiver fifo
+ */
+void wait_rs() {
+   unsigned w;
+   char ls;
+   w = 0;
+   ls = read_reg(LSR);
+   while ((ls & 0x01) == 0 && w<1000) {
+     delay();
+     ls = read_reg(LSR);
+     w++;
+   }
+}
+
+char tb;
+char rr;
+unsigned ctr;
+unsigned r;
+
+char* buff = "AT+GMR\r\n\0";
+char* tbuf;
+char rbuf[1024];
+
+main() {
+    char ok;
+
+    printf("\nInit ISA\n");
+    	
+    init_isa();
+    
+    printf("\nInit serial\n");
+    init_serial();
+    
+    r = port_serial;
+    rr = 0;
+    for (ctr=0; ctr<=7; ctr++) {
+      tb = read_reg(r);
+      printf("REG["); hex8(rr);
+      printf("]="); hex8(tb);
+      printf("\n");
+      r++;
+      rr++;
+    }     
+                      
+    r = port_serial; 
+    rr = 0;
+    write_reg(LCR,0x83);
+    for (ctr=0; ctr<3; ctr++) {
+       tb = read_reg(r);
+       printf("REG[1"); 
+       hex8(rr);
+       printf("]="); 
+       hex8(tb);
+       printf("\n");
+       r++;   
+       rr++;
+    }
+    write_reg(LCR,0x03);
+                 
+   // Wait ESP reload
+
+   for (ctr=0; ctr<400; ctr++) {
+     delay();
+   }                  
+   
+   printf("\nClear receiver buffer");
+   empty_rs();
+
+   printf("\nGet version\n");
+
+   tbuf = buff;
+   while (*tbuf != '\0') {
+      wait_tr();
+      tb = read_reg(LSR);
+      if ((tb & 0x20) == 0) {
+         printf(".TXNR.");
+      } else {
+         write_reg(THR, *tbuf++);
+      }
+   }
+
+   ctr = 0;
+   r = 0;
+   ok = 0;
+
+   disable();
+   open_isa();
+   do {
+      rr = mget(LSR);
+      if ((rr & 0x80) != 0) {
+         close_isa();
+         printf("\nReceiver error:");
+         rr = (rr>>1) & 0x07;
+         hex8(rr);  
+         break;
+      } else {
+         if ((rr & 0x01) == 1) {
+            tb = mget(RBR);
+            rbuf[ctr++] = tb;
+            if (ok == 0 && tb == 'O') {
+              ok = 1;
+            }
+            if (ok == 1 && tb == 'K') {
+              ok = 2;
+            } else {
+              ok = 0;
+            }
+            r = 0;
+         } else {
+            r++;
+         }
+      }
+   } while (ok<2 && r<10000 && ctr<1024);
+   enable();
+   close_isa();                 
+
+   printf("\nctr="); dec16(ctr);
+   printf("\nr="); dec16(r);
+
+   printf("\nReceived:\n");
+   printf(rbuf);
+
+}
+
+
+