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This commit is contained in:
boykovra 2024-07-01 16:09:12 +03:00
parent 5a153d3b29
commit fcda0b02d4
10 changed files with 17292 additions and 263 deletions
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16386
Sources/ESPLib/.tmp/disasm.list Normal file
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88
Sources/ESPLib/.vscode/launch.json vendored Normal file
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{
"version": "0.2.0",
"configurations": [
{
"type": "dezog",
"request": "launch",
"name": "Internal Simulator",
"remoteType": "zsim",
"zsim": {
"visualMemory": true,
"memoryModel": "CUSTOM",
"customMemory": {
"slots": [
{
"name": "PAGE0",
"range": ["0x0000","0x3FFF"],
"banks": [{"index": [0, 255]}],
"initialBank": 0
},
{
"name": "PAGE1",
"range": ["0x4000","0x7FFF"],
"banks": [{"index": [0, 255]}],
"initialBank": 1
},
{
"name": "PAGE2",
"range": ["0x8000","0xBFFF"],
"banks": [{"index": [0, 255]}],
"initialBank": 2
},
{
"name": "PAGE3",
"range": ["0xC000","0xFFFF"],
"banks": [{"index": [0, 255]}],
"initialBank": 3
}
],
"ioMmu": [
"if (portAddress == 0x82) {",
" bank = portValue;",
" PAGE0 = bank;",
"}",
"if (portAddress == 0xA2) {",
" bank = portValue;",
" PAGE1 = bank;",
"}",
"if (portAddress == 0xC2) {",
" bank = portValue;",
" PAGE2 = bank;",
"}",
"if (portAddress == 0xE2) {",
" bank = portValue;",
" PAGE3 = bank;",
"}"
]
},
"customCode": {
"debug": false,
"jsPath": "sim/ports.js"
},
},
"sjasmplus": [
{
"path": "espset.sld"
}
],
"history": {
"reverseDebugInstructionCount": 1000000,
"spotCount": 10,
"codeCoverageEnabled": true
},
"startAutomatically": false,
"commandsAfterLaunch": [],
"rootFolder": "${workspaceFolder}",
"topOfStack": "STACK_TOP",
"loadObjs": [
{
"path": "espset.exe",
"start": "0x0000"
}
],
"execAddress": "0x8100",
"smallValuesMaximum": 513,
"tmpDir": ".tmp"
}
]
}

41
Sources/ESPLib/.vscode/tasks.json vendored Normal file
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{
"version": "2.0.0",
"tasks": [
{
"label": "make (sjasmplus)",
"type": "shell",
"command": "sjasmplus",
"args": [
"--sld=espset.sld",
"--sym=espset.labels",
"--raw=espset.exe",
"--fullpath",
"espset.asm"
],
"problemMatcher": {
"owner": "sjasmplus",
"fileLocation": "autoDetect",
"pattern": {
"regexp": "^(.*)\\((\\d+)\\):\\s+(warning|error):\\s+(.*)$",
"file": 1,
"line": 2,
"severity": 3,
"message": 4
}
},
"group": {
"kind": "build",
"isDefault": true
}
},
{
"label": "start mame",
"type": "shell",
"command": "while true; do ./mame spectrum -window -debugger gdbstub -debug -debugger_port 12000 -verbose -resolution 512x384 ; sleep 2 ; done",
"options": {
"cwd": "${config:mame_dir}"
},
"problemMatcher": []
}
]
}

28
Sources/ESPLib/dss.inc Normal file
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; ======================================================
; Defines for DSS Estex for Sprinter computer
; By Romych, 2024
; https://github.com/romychs
; ======================================================
; DSS RST Entry
DSS EQU 0x10
; DSS Functions
DSS_CURDISK EQU 0x02
DSS_CREATE_FILE EQU 0x0B
DSS_OPEN_FILE EQU 0x11
DSS_CLOSE_FILE EQU 0x12
DSS_READ_FILE EQU 0x13
DSS_WRITE EQU 0x14
DSS_MOVE_FP_CP EQU 0x0115
DSS_FIND_FIRST EQU 0x0119
DSS_FIND_NEXT EQU 0x011A
DSS_MKDIR EQU 0x1B
DSS_CHDIR EQU 0x1D
DSS_CURDIR EQU 0x1E
DSS_EXIT EQU 0x41
DSS_PCHARS EQU 0x5C
; DSS Error codes
E_FILE_EXISTS EQU 7
E_FILE_NOT_FOUND EQU 3

649
Sources/ESPLib/esplib.asm
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; ===========================================
; SOLID C Lbrary to work with Sprinter WiFi
; ESP ISA Card
; ===========================================
; ======================================================
; Library for Sprinter-WiFi ESP ISA Card
;
; By Romych's, 2024 (c)
; ======================================================
DEVICE NOSLOT64K
;INCLUDE "ports.inc"
;ISA_BASE_A EQU 0xC000 ; Базовый адрес портов ISA в памяти
PORT_UART EQU 0x03E8 ; Базовый номер порта COM3
PORT_UART_A EQU ISA_BASE_A + PORT_UART ; Порты чипа UART в памяти
PORT_ISA EQU 0x9FBD
PORT_SYSTEM EQU 0x1FFD
PORT_MEM_W3 EQU 0xE2
; UART TC16C550 Registers in memory
REG_RBR EQU PORT_UART_A + 0
REG_THR EQU PORT_UART_A + 0
REG_IER EQU PORT_UART_A + 1
REG_IIR EQU PORT_UART_A + 2
REG_FCR EQU PORT_UART_A + 2
REG_LCR EQU PORT_UART_A + 3
REG_MCR EQU PORT_UART_A + 4
REG_LSR EQU PORT_UART_A + 5
REG_MSR EQU PORT_UART_A + 6
REG_SCR EQU PORT_UART_A + 7
REG_DLL EQU PORT_UART_A + 0
REG_DLM EQU PORT_UART_A + 1
REG_AFR EQU PORT_UART_A + 2
ISA_BASE_A EQU 0xC000 ; Базовый адрес портов ISA в памяти
PORT_UART EQU 0x03E8 ; Базовый номер порта COM3
PORT_UART_A EQU ISA_BASE_A + PORT_UART ; Порты чипа UART в памяти
; UART TC16C550 Register bits
MCR_DTR EQU 0x01
MCR_RTS EQU 0x02
MCR_RST EQU 0x04
MCR_PGM EQU 0x08
MCR_LOOP EQU 0x10
MCR_AFE EQU 0x20
LCR_WL8 EQU 0x03 ; 8 bits word len
LCR_SB2 EQU 0x04 ; 1.5 or 2 stp bits
LCR_DLAB EQU 0x80 ; Enable Divisor latch
FCR_FIFO EQU 0x01 ; Enable FIFO for rx and tx
FCR_RESET_RX EQU 0x02 ; Reset Rx FIFO
FCR_RESET_TX EQU 0x04 ; Reset Tx FIFO
FCR_DMA EQU 0x08 ; Set -RXRDY, -TXRDY to "1"
FCR_TR1 EQU 0x00 ; Trigger on 1 byte in fifo
FCR_TR4 EQU 0x40 ; Trigger on 4 bytes in fifo
FCR_TR8 EQU 0x80 ; Trigger on 8 bytes in fifo
FCR_TR14 EQU 0xC0 ; Trigger on 14 bytes in fifo
LSR_DR EQU 0x01 ; Data Ready
LSR_OE EQU 0x02 ; Overrun Error
LSR_PE EQU 0x04 ; Parity Error
LSR_FE EQU 0x08 ; Framing Error
LSR_BI EQU 0x10 ; Break Interrupt
LSR_THRE EQU 0x20 ; Transmitter Holding Register
LSR_TEMT EQU 0x40 ; Transmitter empty
LSR_RCVE EQU 0x80 ; Error in receiver FIFO
; Регистры UART TC16C550 в памяти
REG_RBR EQU PORT_UART_A + 0
REG_THR EQU PORT_UART_A + 0
REG_IER EQU PORT_UART_A + 1
REG_IIR EQU PORT_UART_A + 2
REG_FCR EQU PORT_UART_A + 2
REG_LCR EQU PORT_UART_A + 3
REG_MCR EQU PORT_UART_A + 4
REG_LSR EQU PORT_UART_A + 5
REG_MSR EQU PORT_UART_A + 6
REG_SCR EQU PORT_UART_A + 7
REG_DLL EQU PORT_UART_A + 0
REG_DLM EQU PORT_UART_A + 1
REG_AFR EQU PORT_UART_A + 2
; Speed divider for UART
BAUD_RATE EQU 115200 ; Скорость соединения с ESP8266
XIN_FREQ EQU 14745600 ; Частота генератора для TL16C550
DIVISOR EQU XIN_FREQ / (BAUD_RATE * 16) ; Делитель частоты для передачи/приема данных
BAUD_RATE EQU 115200 ; Скорость соединения с ESP8266
XIN_FREQ EQU 14745600 ; Частота генератора для TL16C550
DIVISOR EQU XIN_FREQ / (BAUD_RATE * 16) ; Делитель частоты для передачи/приема данных
RS_BUFF_SIZE EQU 2048 ; Receive buffer size
MAX_BUFF_SIZE EQU 16384
ORG 0x0000
jp main
LSTR_SIZE EQU 20 ; Size of buffer for last response line
LF EQU 0x0A
CR EQU 0x0D
save_mmu3 DB 0 ; Variable to save memory page
; --
RES_OK EQU 0
RES_ERROR EQU 1
RES_FAIL EQU 2
RES_TX_TIMEOUT EQU 3
RES_RS_TIMEOUT EQU 4
RES_CONNECTED EQU 5
RES_NOT_CONN EQU 6
RES_ENABLED EQU 7
RES_DISABLED EQU 8
; ===============================================
; Small delay
; void delay(hl)
; in hl - number of cycles, if hl=0, then 2000
; ===============================================
MODULE delay
delay_:
push af
ld a,h
or l
jp nz,delay_l1
ld hl,2000
delay_l1: dec hl
ld a,h
or l
jp nz,delay_l1
pop af
ret
ENDMODULE
; ===============================================
; Reset ISA device
; ===============================================
MODULE reset_isa
reset_isa_:
push af
push bc
push hl
ld bc, PORT_ISA
ld a, 0xC0 ; RESET=1 AEN=1
out (c), a
ld hl,2000
call delay.delay_
xor a
out (c), a ; RESET=0 AEN=0
add hl,hl
call delay.delay_
pop hl
pop bc
pop af
ret
ENDMODULE
; ===============================================
; Open access to ISA ports as memory
; input a = 0 - ISA slot 0, 1 - ISA SLOT 1
; ===============================================
MODULE open_isa
open_isa_:
push af
push bc
PORT_EMM_WIN_P3in_p3
in a,(c)
ld (save_mmu3), a
push bc
ld bc, PORT_SYSTEM
ld a, 0x11
out (c), a
PORT_MEM_W3 ; em m_win_p3
pop af
and a, 0x01
rlca
rlca
or a, 0xd0 ; 1101 - Magic number, 0100 - 0,ISA PORT, ISA SLOT, 0
out (c), a
ld bc, PORT_SYSTEM
xor a
out (c), a
pop bc
ret
ENDMODULE
MODULE WIFI
; ===============================================
; Close access to ISA ports
; ===============================================
MODULE close_isa
close_isa_:
push af
push bc
ld bc, PORT_SYSTEM
ld a, 0x01
out (c), a
ld a, save_mmu3
PORT_EMM_WIN_P3in_p3
out (c), a
pop bc
pop af
ret
ENDMODULE
RS_BUFF DS RS_BUFF_SIZE, 0
; ===============================================
; Init ISA device
; ===============================================
MODULE init_isa
init_isa_:
call reset_isa.reset_isa_ ; just only reset
ret
ENDMODULE
; ------------------------------------------------------
; Init UART device TL16C550
; ------------------------------------------------------
UART_INIT
PUSH AF
PUSH HL
CALL ISA.ISA_OPEN
LD A, FCR_TR14 | FCR_FIFO ; Enable FIFO buffer, trigger to 14 byte
LD (REG_FCR),A
XOR A
LD (REG_IER), A ; Disable interrupts
; ===============================================
; Init UART device TL16C550
; ===============================================
MODULE init_serial
init_serial_:
push af
push hl
call open_isa.open_isa_
ld a, 1
ld (REG_FCR
a ; 8 byte FIFO buffer
ld a, 0x81
ld (REG_FCR
a
xor a
ld (REG_IER
), a ; Disable interrupts
; Set baud rate
ld a, 0x83
ld (REG_LCR), a ; enable Baud rate latch
ld a, DIVISOR
ld (REG_DLL), a ; 8 - 115200
xor a
ld (REG_DLM), a
ld a, 0x03 ; disable Baud rate latch & 8N1
ld (REG_LCR), a
; reset ESP
ld a,0x06 ; ESP -PGM=1, -RTS=0
ld (REG_MCR), a
ld hl,2000
call delay.delay_
ld a,0x02 ; ESP -RST=1, -RTS=0
call delay.delay_
call close_isa.close_isa_
pop hl
pop af
ret
ENDMODULE
; Set 8bit word and Divisor for speed
LD A, LCR_DLAB | LCR_WL8
LD (REG_LCR), A ; Enable Baud rate latch
LD A, DIVISOR
LD (REG_DLL), A ; 8 - 115200
XOR A
LD (REG_DLM), A
LD A, LCR_WL8 ; 8bit word, disable latch
LD (REG_LCR), A
CALL ISA.ISA_CLOSE
POP HL
POP AF
RET
; ===============================================
; Read TL16C550 register
; char read_reg(reg)
; input hl - register no
; output a - value from register
; ===============================================
MODULE read_reg
read_reg_:
call open_isa.open_isa_
ld a, (hl)
call close_isa.close_isa_
ret
ENDMODULE
; ------------------------------------------------------
; Read TL16C550 register
; Inp: HL - register
; Out: A - value from register
; ------------------------------------------------------
UART_READ
IF DEBUG==0
CALL ISA.ISA_OPEN
LD A, (HL)
CALL ISA.ISA_CLOSE
RET
ELSE
; --- DEBUG
LD HL,(RX_PTR)
LD A,(HL)
OR A
JR NZ, RX_RET
LD BC, RX_MSG
LD (HL),BC
JR UART_READ
RX_RET
INC (HL)
RET
; ===============================================
; Write TL16C550 register
; void write_reg(reg, b)
; input hl - reg no, e - value
; ===============================================
MODULE write_reg
write_reg_:
call open_isa.open_isa_
ld (hl), e
call close_isa.close_isa_
ret
ENDMODULE
RX_PTR DW RX_MSG
RX_MSG DB "WiFi module\r\nOK\r\n",0
ENDIF
; ===============================================
; Wait for transmitter ready
; char wait_tr()
; output a = 0 - tr not ready, !=0 - tr ready
; ===============================================
MODULE wait_tr
wait_tr_:
push bc
push hl
ld bc, 100
ld hl, REG_LSR
wait_tr_r:
call read_reg.read_reg_
and a, 0x20
jp nz,wait_tr_e
dec bc
ld a, c
or b
jp nz,wait_tr_r
xor a
wait_tr_e:
pop hl
pop bc
ret
ENDMODULE
; ------------------------------------------------------
; Write TL16C550 register
; Inp: HL - register, E - value
; ------------------------------------------------------
UART_WRITE
CALL ISA.ISA_OPEN
LD (HL), E
CALL ISA.ISA_CLOSE
RET
; ===============================================
; Empty receiver FIFO buffer
; void empty_rs()
; ===============================================
MODULE empty_rs
empty_rs_:
push af
call open_isa.open_isa_
ld a, 0x83
ld (REG_FCR
a
call close_isa.close_isa_
pop af
ret
ENDMODULE
; ------------------------------------------------------
; Wait for transmitter ready
; Out: CF=1 - tr not ready, CF=0 ready
; ------------------------------------------------------
UART_WAIT_TR
PUSH BC, HL
CALL ISA.ISA_OPEN
LD BC, 200
LD HL, REG_LSR
WAIT_TR_R
LD A,(HL)
AND A, LSR_THRE
JP NZ,WAIT_TR_E
CALL UTIL.DELAY_1MS
DEC BC
LD A, C
OR B
JP NZ,WAIT_TR_R
SCF
WAIT_TR_E
CALL ISA.ISA_CLOSE
POP HL, BC
RET
; ===============================================
; Wait byte in receiver fifo
; char wait_rs()
; output a=0 - fifo still empty, a!=0 - receiver fifo is not empty
; ===============================================
MODULE wait_rs
wait_rs_:
push bc
push hl
ld bc, 1000
ld hl, REG_LSR
wait_rs_r:
call read_reg.read_reg_
and a, 0x01
jp nz,wait_rs_e
dec bc
ld a, c
or b
jp nz,wait_rs_r
xor a
wait_rs_e:
pop hl
pop bc
ret
ENDMODULE
; ------------------------------------------------------
; Transmit byte
; Inp: E - byte
; Out: CF=1 - Not ready
; ------------------------------------------------------
UART_TX_BYTE
CALL UART_WAIT_TR
JP C, UTB_NOT_R
LD HL, REG_THR
CALL UART_WRITE
XOR A
UTB_NOT_R
RET
; ===============================================
; STUB
; ===============================================
; ------------------------------------------------------
; char uart_tx_buffer(char* tbuff, int size)
; Inp: HL -> buffer, BC - size
; Out: CF=0 - Ok, CF=1 - Timeout
; ------------------------------------------------------
IF DEBUG==0
UART_TX_BUFFER
PUSH BC,DE,HL
LD DE, REG_THR
CALL ISA.ISA_OPEN
UTX_NEXT
; buff not empty?
LD A, B
OR C
JR Z,UTX_EMP
; check transmitter ready
CALL UART_WAIT_TR
JR C, UTX_EMP
; transmitt byte
LD A,(HL)
INC HL
LD (DE),A
DEC BC
JR UTX_NEXT
; CF=0
XOR A
UTX_EMP
CALL ISA.ISA_CLOSE
POP HL,DE,BC
RET
ELSE
; --- DEBUG
UART_TX_BUFFER
XOR A
RET
ENDIF
; ------------------------------------------------------
; Empty receiver FIFO buffer
; ------------------------------------------------------
UART_EMPTY_RS
PUSH AF
CALL ISA.ISA_OPEN
LD A, FCR_TR14 | FCR_RESET_RX | FCR_FIFO
LD (REG_FCR), A
CALL ISA.ISA_CLOSE
POP AF
RET
main:
call init_isa.init_isa_
ret
; ------------------------------------------------------
; Wait byte in receiver fifo
; Inp: BC - Wait ms
; Out: CF=1 - Timeout, FIFO is EMPTY
; ------------------------------------------------------
IF DEBUG==0
UART_WAIT_RS1
PUSH BC,HL
WAIT_MS+* LD BC,0x0000
JR UVR_NEXT
ENDIF
UART_WAIT_RS
PUSH BC,HL
UVR_NEXT
LD HL, REG_LSR
CALL UART_READ
AND LSR_DR
JR Z,UVR_OK
CALL UTIL.DELAY_1MS
DEC BC
LD A,B
OR A,C
JR NZ,UVR_NEXT
UVR_TO
SCF
UVR_OK
POP HL,BC
IF DEBUG==1
WAIT_MS DW 0
UART_WAIT_RS1
ENDIF
RET
; ------------------------------------------------------
; Reset ESP module
; Inp: A != 0 - Full Reset
; ------------------------------------------------------
ESP_RESET
PUSH HL, AF
CALL ISA.ISA_OPEN
AND A
JR Z, ESPR_SHRT
LD HL, REG_MCR
LD A, MCR_RST | MCR_RTS ; 0110b ESP -PGM=1, -RST=0, -RTS=0
LD (HL), A
CALL UTIL.DELAY
ESPR_SHRT
LD A, MCR_AFE | MCR_RTS ; 0x22 -RST = 1 -RTS=0 AutoFlow enabled
LD (HL), A
CALL ISA.ISA_CLOSE
POP AF
AND A
JR Z,ESPR_NW
LD HL,0xFFFF
CALL UTIL.DELAY
ESPR_NW
POP HL
RET
; Receive block size
BSIZE DW 0
; Received message for OK result
MSG_OK DB "OK", 0
; Received message for Error
MSG_ERROR DB "ERROR", 0
; Received message for Failure
MSG_FAIL DB "FAIL", 0
; ------------------------------------------------------
; UART TX Command
; Inp: HL - ptr to command,
; DE - ptr to receive buffer,
; BC - wait ms
; Out: CF=1 if Error
; ------------------------------------------------------
UART_TX_CMD
PUSH BC, DE, HL
LD A, low RS_BUFF_SIZE
LD (BSIZE), A
LD A, high RS_BUFF_SIZE
LD (BSIZE+1), A
;LD (RESBUF),DE
XOR A
LD (DE), A
LD (WAIT_MS), BC
CALL UART_EMPTY_RS
; HL - Buffer, BC - Size
CALL UTIL.STRLEN
CALL UART_TX_BUFFER
JR NC, UTC_RCV_NXT
; error, transmit timeout
LD A, RES_TX_TIMEOUT
JR UTC_RET
; no transmit timeout, receive response
UTC_RCV_NXT
; wait receiver ready
;LD BC,(WAIT_MS)
CALL UART_WAIT_RS1
JR NC, UTC_NO_RT
; error, read timeout
LD A, RES_RS_TIMEOUT
JR UTC_RET
; no receive timeout
UTC_NO_RT
; IX - pointer to begin of current line
LD IXH, D
LD IXL, E
LD BC,(BSIZE)
;UTC_RCV_NXT
; read symbol from tty
LD HL, REG_RBR
CALL UART_READ
CP CR
JP Z, UTC_RCV_NXT ; Skip CR
CP LF
JR Z, UTC_END ; LF - last symbol in responce
LD (DE),A
INC DE
;LD BC,(BSIZE)
DEC BC
LD A, B
OR C
;LD (BSIZE),BC
JR NZ, UTC_RCV_NXT
UTC_END
XOR A
LD (DE),A ; temporary mark end of string
PUSH DE ; store DE
POP IY
PUSH IX
POP DE ; DE - ptr to begin pf current line
; It is 'OK<LF>'?
LD HL, MSG_OK
CALL UTIL.STRCMP
JR NC, UTC_RET
; It is 'ERROR<LF>'?
LD HL,MSG_ERROR
CALL UTIL.STRCMP
JR C, UTC_CP_FAIL
LD A, RES_ERROR
; It is 'FAIL<LF>'?
JR UTC_RET
UTC_CP_FAIL
LD HL,MSG_FAIL
CALL UTIL.STRCMP
JR C, UTC_NOMSG
LD A, RES_FAIL
JR UTC_RET
UTC_NOMSG
; no resp message, continue receive
PUSH IY
POP DE
LD A, LF
LD (DE),A ; change 0 - EOL to LF
INC DE
LD IXH,D ; store new start line ptr
LD IXL,E
JR UTC_RCV_NXT
UTC_RET
POP HL, DE, BC
RET
ENDMODULE

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; ======================================================
; ESPSET for SprinterWiFi for Sprinter computer
; By Romych, 2024
; https://github.com/romychs
; ======================================================
; Set to 1 to turn debug ON with DeZog VSCode plugin
; Set to 0 to compile .EXE
DEBUG EQU 1
EXE_VERSION EQU 1
SLDOPT COMMENT WPMEM, LOGPOINT, ASSERTION
DEVICE NOSLOT64K
IF DEBUG == 1
DS 0x8080, 0
ENDIF
INCLUDE "dss.inc"
INCLUDE "sprinter.inc"
MODULE MAIN
ORG 0x8080
EXE_HEADER
DB "EXE"
DB EXE_VERSION ; EXE Version
DW 0x0080 ; Code offset
DW 0
DW 0 ; Primary loader size
DW 0 ; Reserved
DW 0
DW 0
DW START ; Loading Address
DW START ; Entry Point
DW STACK_TOP ; Stack address
DS 106, 0 ; Reserved
ORG 0x8100
@STACK_TOP
START
; IF DEBUG == 1
; LD IX,CMD_LINE1
; ENDIF
CALL ISA.ISA_RESET
LD HL,MSG_START
LD C,DSS_PCHARS
RST DSS
IF DEBUG==1
LD HL, CMD_TEST1
LD DE, BUFF_TEST1
LD BC, 100
CALL WIFI.UART_TX_CMD
ENDIF
; PUSH IX ; IX ptr to cmd line
; POP HL
; INC HL ; Skip size of Command line
; LD DE,ZIP_FILE
; CALL GET_CMD_PARAM
; JR C,INVALID_CMDLINE
; LD DE,FILES_TO_ZIP
; CALL GET_CMD_PARAM
; JR C,INVALID_CMDLINE
EXIT
LD BC,DSS_EXIT
RST DSS
MSG_START
DB "ESPSET for Sprinter by Romych's, (c) 2024\n\r\n\r", 0
IF DEBUG == 1
CMD_TEST1 DB "ATE0\r\n",0
BUFF_TEST1 DS RS_BUFF_SIZE,0
ENDIF
ENDMODULE
INCLUDE "util.asm"
INCLUDE "isa.asm"
INCLUDE "esplib.asm"
END MAIN.START

116
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; ======================================================
; ISA Library for Sprinter
; By Romych's, 2024 (c)
; ======================================================
PORT_ISA EQU 0x9FBD
PORT_SYSTEM EQU 0x1FFD
ISA_BASE_A EQU 0xC000 ; Базовый адрес портов ISA в памяти
; --- PORT_ISA bits
ISA_A14 EQU 0x01
ISA_A15 EQU 0x02
ISA_A16 EQU 0x04
ISA_A17 EQU 0x08
ISA_A18 EQU 0x10
ISA_A19 EQU 0x20
ISA_AEN EQU 0x40
ISA_RST EQU 0x80
MODULE ISA
; ------------------------------------------------------
; Reset ISA device
; ------------------------------------------------------
ISA_RESET
PUSH AF
PUSH BC
PUSH HL
LD BC, PORT_ISA
LD A,ISA_RST | ISA_AEN ; RESET=1 AEN=1
OUT (C), A
LD HL,2000
CALL UTIL.DELAY
XOR A
OUT (C), A ; RESET=0 AEN=0
ADD HL,HL
CALL UTIL.DELAY
POP HL
POP BC
POP AF
RET
; ------------------------------------------------------
; Open access to ISA ports as memory
; Inp: A = 0 - ISA slot 0, 1 - ISA SLOT 1
; ------------------------------------------------------
ISA_OPEN
PUSH BC
PUSH AF
LD BC, PAGE3
IN A,(C)
LD (SAVE_MMU3), A
LD BC, PORT_SYSTEM
LD A, 0x11
OUT (C), A
POP AF
AND A, 0x01
RLCA
RLCA
OR A, 0xD0 ; 1101 - MAGIC NUMBER, 0100 - 0,ISA PORT, ISA SLOT, 0
LD BC, PAGE3
OUT (C), A
LD BC, PORT_ISA
XOR A
OUT (C), A
POP BC
RET
; ------------------------------------------------------
; Close access to ISA ports
; ------------------------------------------------------
ISA_CLOSE
PUSH AF,BC
LD A,0x01
LD BC,PORT_SYSTEM
OUT (C),A
LD BC,PAGE3
LD A,(SAVE_MMU3)
OUT (C),A
POP BC,AF
RET
; DELAY_20
; ;IN A,(PAGE1)
; LD A, CTC_CR_VEC | CTC_CR_SWR ; stop timer
; OUT (CTC_CH1), A
; ; Init Ch2 CTC - clk source for Ch3
; LD A,CTC_CT_PRE | CTC_CR_TCF | CTC_CR_SWR | CTC_CR_VEC
; OUT (CTC_CH2), A
; LD A, 4
; ; TO2->TRG3 = 875kHz / 256 / 4 = 854,5 Hz
; OUT (CTC_CH2), A
; LD A, CTC_CT_EI | CTC_CT_CTR | CTC_CR_TCF | CTC_CR_SWR | CTC_CR_VEC
; OUT (CTC_CH3), A
; LD A, 17
; OUT (CTC_CH3), A
; it vector defined in bit 7­3,bit 2­1 don't care, bit 0 = 0
; and loaded into channel 0
; To save memory page 0
SAVE_MMU0 DB 0
; To save memory page 3
SAVE_MMU3 DB 0
; ALIGN 256,0
ENDMODULE

44
Sources/ESPLib/sim/ports.js Normal file
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port_p0 = 0;
port_p1 = 1;
port_p2 = 2;
port_p3 = 3;
message = "";
// This function is called when time (t-states) advances.
API.tick = () => {
}
// This function is called when an 'out' is executed in Z80.
API.writePort = (port, value) => {
// Go through all ports
if (port == 0x9000) {
if (value != 0) {
message += String.fromCharCode(value);
} else {
API.log("> " + message);
message = "";
}
} else if (port == 0x82) {
port_p0 = value;
} else if (port == 0xA2) {
port_p1 = value;
} else if (port == 0xC2) {
port_p2 = value;
} else if (port == 0xE2) {
port_p3 = value;
}
}
API.readPort = (port) => {
if (port == 0x82) {
return port_p0;
} else if (port == 0xA2) {
return port_p1;
} else if (port == 0xC2) {
return port_p2;
} else if (port == 0xE2) {
return port_p3;
}
}

32
Sources/ESPLib/sprinter.inc Normal file
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; ======================================================
; Defines for Sprinter computer hardware
; By Romych, 2024
; https://github.com/romychs
; ======================================================
; Memory pages
PAGE0_ADDR EQU 0x0000
PAGE1_ADDR EQU 0x4000
PAGE2_ADDR EQU 0x8000
PAGE3_ADDR EQU 0xC000
; Sprinter ports to switch mem pages
PAGE0 EQU 0x82
PAGE1 EQU 0xA2
PAGE2 EQU 0xC2
PAGE3 EQU 0xE2
; CTC Control register ports
CTC_CH0 EQU 0x10
CTC_CH1 EQU 0x11
CTC_CH2 EQU 0x12
CTC_CH3 EQU 0x13
CTC_CR_VEC EQU 0x01 ; 1 - Vector, 0 - Control
CTC_CR_SWR EQU 0x02 ; 1 - Software Reset, 0 - Continued operation
CTC_CR_TCF EQU 0x04 ; 1 - TYime const follows
CTC_CR_TTR EQU 0x08 ; 1 - Time trigger
CTC_CT_TRE EQU 0x10 ; 1 - Trigger Edge
CTC_CT_PRE EQU 0x20 ; 1 - 256 Prescaler, 0 - 16
CTC_CT_CTR EQU 0x40 ; 0 - Timer, 1 - Counter
CTC_CT_EI EQU 0x80 ; Interrupt 1 - enable, 0 - disable

79
Sources/ESPLib/util.asm Normal file
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MODULE UTIL
; ------------------------------------------------------
; Small delay
; Inp: HL - number of cycles, if HL=0, then 2000
; ------------------------------------------------------
DELAY
PUSH AF
PUSH HL
LD A,H
OR L
JP NZ,DELAY_L1
LD HL,2000
DELAY_L1:
DEC HL
LD A,H
OR L
JP NZ,DELAY_L1
POP HL
POP AF
RET
; TODO: Do it with timer
DELAY_1MS
PUSH HL
LD HL,100
CALL DELAY
POP HL
RET
; ------------------------------------------------------
; Calc length of zero ended string
; Inp: HL - pointer to string
; Out: BC - length of string
; ------------------------------------------------------
STRLEN
PUSH DE,HL
LD BC,MAX_BUFF_SIZE
XOR A
CPIR
POP DE
SUB HL,DE ; llength of zero ended string
LD BC,HL
POP HL,DE
RET
; ------------------------------------------------------
; Compare zero-ended strings
; Inp: HL, DE - pointers to strinngs to compare
; Out: CF=0 - equal, CF=1 - not equal
; ------------------------------------------------------
STRCMP INCLUDE "util.asm"
INCLUDE "isa.asm"
INCLUDE "esplib.asm"
LD A, (DE)
CP (HL)
JR NZ, STC_NE
AND A
JR Z, STC_EQ
INC DE
INC HL
JR STC_NEXT
STC_NE
SCF
STC_EQ
POP BC,HL,DE
RET
POP BC,HL,DE
RET
ENDMODULE