mirror of
https://github.com/romychs/SprinterESP.git
synced 2025-11-01 23:36:00 +03:00
283 lines
7.9 KiB
NASM
283 lines
7.9 KiB
NASM
; ===========================================
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; SOLID C Lbrary to work with Sprinter WiFi
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; ESP ISA Card
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; ===========================================
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DEVICE NOSLOT64K
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;INCLUDE "ports.inc"
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PORT_ISA EQU 0x9FBD
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PORT_SYSTEM EQU 0x1FFD
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PORT_MEM_W3 EQU 0xE2
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ISA_BASE_A EQU 0xC000 ; Базовый адрес портов ISA в памяти
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PORT_UART EQU 0x03E8 ; Базовый номер порта COM3
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PORT_UART_A EQU ISA_BASE_A + PORT_UART ; Порты чипа UART в памяти
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; Регистры UART TC16C550 в памяти
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REG_RBR EQU PORT_UART_A + 0
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REG_THR EQU PORT_UART_A + 0
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REG_IER EQU PORT_UART_A + 1
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REG_IIR EQU PORT_UART_A + 2
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REG_FCR EQU PORT_UART_A + 2
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REG_LCR EQU PORT_UART_A + 3
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REG_MCR EQU PORT_UART_A + 4
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REG_LSR EQU PORT_UART_A + 5
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REG_MSR EQU PORT_UART_A + 6
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REG_SCR EQU PORT_UART_A + 7
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REG_DLL EQU PORT_UART_A + 0
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REG_DLM EQU PORT_UART_A + 1
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REG_AFR EQU PORT_UART_A + 2
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BAUD_RATE EQU 115200 ; Скорость соединения с ESP8266
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XIN_FREQ EQU 14745600 ; Частота генератора для TL16C550
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DIVISOR EQU XIN_FREQ / (BAUD_RATE * 16) ; Делитель частоты для передачи/приема данных
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ORG 0x0000
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jp main
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save_mmu3 DB 0 ; Variable to save memory page
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; ===============================================
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; Small delay
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; void delay(hl)
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; in hl - number of cycles, if hl=0, then 2000
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; ===============================================
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MODULE delay
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delay_:
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push af
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ld a,h
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or l
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jp nz,delay_l1
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ld hl,2000
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delay_l1: dec hl
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ld a,h
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or l
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jp nz,delay_l1
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pop af
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ret
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ENDMODULE
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; ===============================================
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; Reset ISA device
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; ===============================================
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MODULE reset_isa
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reset_isa_:
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push af
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push bc
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push hl
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ld bc, PORT_ISA
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ld a, 0xC0 ; RESET=1 AEN=1
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out (c), a
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ld hl,2000
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call delay.delay_
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xor a
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out (c), a ; RESET=0 AEN=0
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add hl,hl
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call delay.delay_
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pop hl
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pop bc
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pop af
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ret
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ENDMODULE
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; ===============================================
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; Open access to ISA ports as memory
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; input a = 0 - ISA slot 0, 1 - ISA SLOT 1
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; ===============================================
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MODULE open_isa
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open_isa_:
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push af
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push bc
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PORT_EMM_WIN_P3in_p3
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in a,(c)
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ld (save_mmu3), a
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push bc
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ld bc, PORT_SYSTEM
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ld a, 0x11
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out (c), a
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PORT_MEM_W3 ; em m_win_p3
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pop af
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and a, 0x01
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rlca
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rlca
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or a, 0xd0 ; 1101 - Magic number, 0100 - 0,ISA PORT, ISA SLOT, 0
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out (c), a
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ld bc, PORT_SYSTEM
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xor a
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out (c), a
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pop bc
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ret
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ENDMODULE
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; ===============================================
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; Close access to ISA ports
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; ===============================================
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MODULE close_isa
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close_isa_:
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push af
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push bc
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ld bc, PORT_SYSTEM
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ld a, 0x01
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out (c), a
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ld a, save_mmu3
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PORT_EMM_WIN_P3in_p3
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out (c), a
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pop bc
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pop af
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ret
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ENDMODULE
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; ===============================================
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; Init ISA device
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; ===============================================
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MODULE init_isa
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init_isa_:
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call reset_isa.reset_isa_ ; just only reset
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ret
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ENDMODULE
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; ===============================================
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; Init UART device TL16C550
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; ===============================================
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MODULE init_serial
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init_serial_:
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push af
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push hl
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call open_isa.open_isa_
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ld a, 1
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ld (REG_FCR
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a ; 8 byte FIFO buffer
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ld a, 0x81
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ld (REG_FCR
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a
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xor a
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ld (REG_IER
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), a ; Disable interrupts
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; Set baud rate
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ld a, 0x83
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ld (REG_LCR), a ; enable Baud rate latch
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ld a, DIVISOR
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ld (REG_DLL), a ; 8 - 115200
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xor a
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ld (REG_DLM), a
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ld a, 0x03 ; disable Baud rate latch & 8N1
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ld (REG_LCR), a
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; reset ESP
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ld a,0x06 ; ESP -PGM=1, -RTS=0
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ld (REG_MCR), a
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ld hl,2000
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call delay.delay_
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ld a,0x02 ; ESP -RST=1, -RTS=0
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call delay.delay_
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call close_isa.close_isa_
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pop hl
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pop af
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ret
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ENDMODULE
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; ===============================================
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; Read TL16C550 register
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; char read_reg(reg)
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; input hl - register no
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; output a - value from register
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; ===============================================
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MODULE read_reg
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read_reg_:
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call open_isa.open_isa_
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ld a, (hl)
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call close_isa.close_isa_
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ret
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ENDMODULE
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; ===============================================
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; Write TL16C550 register
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; void write_reg(reg, b)
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; input hl - reg no, e - value
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; ===============================================
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MODULE write_reg
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write_reg_:
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call open_isa.open_isa_
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ld (hl), e
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call close_isa.close_isa_
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ret
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ENDMODULE
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; ===============================================
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; Wait for transmitter ready
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; char wait_tr()
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; output a = 0 - tr not ready, !=0 - tr ready
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; ===============================================
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MODULE wait_tr
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wait_tr_:
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push bc
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push hl
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ld bc, 100
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ld hl, REG_LSR
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wait_tr_r:
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call read_reg.read_reg_
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and a, 0x20
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jp nz,wait_tr_e
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dec bc
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ld a, c
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or b
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jp nz,wait_tr_r
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xor a
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wait_tr_e:
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pop hl
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pop bc
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ret
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ENDMODULE
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; ===============================================
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; Empty receiver FIFO buffer
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; void empty_rs()
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; ===============================================
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MODULE empty_rs
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empty_rs_:
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push af
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call open_isa.open_isa_
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ld a, 0x83
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ld (REG_FCR
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a
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call close_isa.close_isa_
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pop af
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ret
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ENDMODULE
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; ===============================================
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; Wait byte in receiver fifo
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; char wait_rs()
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; output a=0 - fifo still empty, a!=0 - receiver fifo is not empty
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; ===============================================
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MODULE wait_rs
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wait_rs_:
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push bc
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push hl
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ld bc, 1000
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ld hl, REG_LSR
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wait_rs_r:
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call read_reg.read_reg_
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and a, 0x01
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jp nz,wait_rs_e
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dec bc
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ld a, c
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or b
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jp nz,wait_rs_r
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xor a
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wait_rs_e:
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pop hl
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pop bc
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ret
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ENDMODULE
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; ===============================================
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; STUB
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; ===============================================
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main:
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call init_isa.init_isa_
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ret |